Commit | Line | Data |
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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
760285e7 DH |
25 | #include <drm/drmP.h> |
26 | #include <drm/i915_drm.h> | |
76aaf220 DV |
27 | #include "i915_drv.h" |
28 | #include "i915_trace.h" | |
29 | #include "intel_drv.h" | |
30 | ||
6670a5a5 BW |
31 | #define GEN6_PPGTT_PD_ENTRIES 512 |
32 | #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t)) | |
33 | ||
26b1ff35 BW |
34 | /* PPGTT stuff */ |
35 | #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) | |
0d8ff15e | 36 | #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) |
26b1ff35 BW |
37 | |
38 | #define GEN6_PDE_VALID (1 << 0) | |
39 | /* gen6+ has bit 11-4 for physical addr bit 39-32 */ | |
40 | #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
41 | ||
42 | #define GEN6_PTE_VALID (1 << 0) | |
43 | #define GEN6_PTE_UNCACHED (1 << 1) | |
44 | #define HSW_PTE_UNCACHED (0) | |
45 | #define GEN6_PTE_CACHE_LLC (2 << 1) | |
350ec881 | 46 | #define GEN7_PTE_CACHE_L3_LLC (3 << 1) |
26b1ff35 | 47 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) |
0d8ff15e BW |
48 | #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) |
49 | ||
50 | /* Cacheability Control is a 4-bit value. The low three bits are stored in * | |
51 | * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. | |
52 | */ | |
53 | #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ | |
54 | (((bits) & 0x8) << (11 - 3))) | |
87a6b688 | 55 | #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) |
0d8ff15e | 56 | #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) |
4d15c145 | 57 | #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) |
651d794f | 58 | #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) |
26b1ff35 | 59 | |
350ec881 | 60 | static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr, |
b35b380e BW |
61 | enum i915_cache_level level, |
62 | bool valid) | |
54d12527 | 63 | { |
b35b380e | 64 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
54d12527 | 65 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
66 | |
67 | switch (level) { | |
350ec881 CW |
68 | case I915_CACHE_L3_LLC: |
69 | case I915_CACHE_LLC: | |
70 | pte |= GEN6_PTE_CACHE_LLC; | |
71 | break; | |
72 | case I915_CACHE_NONE: | |
73 | pte |= GEN6_PTE_UNCACHED; | |
74 | break; | |
75 | default: | |
76 | WARN_ON(1); | |
77 | } | |
78 | ||
79 | return pte; | |
80 | } | |
81 | ||
82 | static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr, | |
b35b380e BW |
83 | enum i915_cache_level level, |
84 | bool valid) | |
350ec881 | 85 | { |
b35b380e | 86 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
350ec881 CW |
87 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
88 | ||
89 | switch (level) { | |
90 | case I915_CACHE_L3_LLC: | |
91 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
92 | break; |
93 | case I915_CACHE_LLC: | |
94 | pte |= GEN6_PTE_CACHE_LLC; | |
95 | break; | |
96 | case I915_CACHE_NONE: | |
9119708c | 97 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
98 | break; |
99 | default: | |
350ec881 | 100 | WARN_ON(1); |
e7210c3c BW |
101 | } |
102 | ||
54d12527 BW |
103 | return pte; |
104 | } | |
105 | ||
93c34e70 KG |
106 | #define BYT_PTE_WRITEABLE (1 << 1) |
107 | #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) | |
108 | ||
80a74f7f | 109 | static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr, |
b35b380e BW |
110 | enum i915_cache_level level, |
111 | bool valid) | |
93c34e70 | 112 | { |
b35b380e | 113 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
93c34e70 KG |
114 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
115 | ||
116 | /* Mark the page as writeable. Other platforms don't have a | |
117 | * setting for read-only/writable, so this matches that behavior. | |
118 | */ | |
119 | pte |= BYT_PTE_WRITEABLE; | |
120 | ||
121 | if (level != I915_CACHE_NONE) | |
122 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
123 | ||
124 | return pte; | |
125 | } | |
126 | ||
80a74f7f | 127 | static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr, |
b35b380e BW |
128 | enum i915_cache_level level, |
129 | bool valid) | |
9119708c | 130 | { |
b35b380e | 131 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
0d8ff15e | 132 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
133 | |
134 | if (level != I915_CACHE_NONE) | |
87a6b688 | 135 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
136 | |
137 | return pte; | |
138 | } | |
139 | ||
4d15c145 | 140 | static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr, |
b35b380e BW |
141 | enum i915_cache_level level, |
142 | bool valid) | |
4d15c145 | 143 | { |
b35b380e | 144 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4d15c145 BW |
145 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
146 | ||
651d794f CW |
147 | switch (level) { |
148 | case I915_CACHE_NONE: | |
149 | break; | |
150 | case I915_CACHE_WT: | |
151 | pte |= HSW_WT_ELLC_LLC_AGE0; | |
152 | break; | |
153 | default: | |
4d15c145 | 154 | pte |= HSW_WB_ELLC_LLC_AGE0; |
651d794f CW |
155 | break; |
156 | } | |
4d15c145 BW |
157 | |
158 | return pte; | |
159 | } | |
160 | ||
3e302542 | 161 | static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt) |
6197349b | 162 | { |
853ba5d2 | 163 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; |
6197349b BW |
164 | gen6_gtt_pte_t __iomem *pd_addr; |
165 | uint32_t pd_entry; | |
166 | int i; | |
167 | ||
0a732870 | 168 | WARN_ON(ppgtt->pd_offset & 0x3f); |
6197349b BW |
169 | pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm + |
170 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
171 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
172 | dma_addr_t pt_addr; | |
173 | ||
174 | pt_addr = ppgtt->pt_dma_addr[i]; | |
175 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
176 | pd_entry |= GEN6_PDE_VALID; | |
177 | ||
178 | writel(pd_entry, pd_addr + i); | |
179 | } | |
180 | readl(pd_addr); | |
3e302542 BW |
181 | } |
182 | ||
183 | static int gen6_ppgtt_enable(struct drm_device *dev) | |
184 | { | |
185 | drm_i915_private_t *dev_priv = dev->dev_private; | |
186 | uint32_t pd_offset; | |
187 | struct intel_ring_buffer *ring; | |
188 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
189 | int i; | |
190 | ||
191 | BUG_ON(ppgtt->pd_offset & 0x3f); | |
192 | ||
193 | gen6_write_pdes(ppgtt); | |
6197349b BW |
194 | |
195 | pd_offset = ppgtt->pd_offset; | |
196 | pd_offset /= 64; /* in cachelines, */ | |
197 | pd_offset <<= 16; | |
198 | ||
199 | if (INTEL_INFO(dev)->gen == 6) { | |
200 | uint32_t ecochk, gab_ctl, ecobits; | |
201 | ||
202 | ecobits = I915_READ(GAC_ECO_BITS); | |
3b9d7888 VS |
203 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | |
204 | ECOBITS_PPGTT_CACHE64B); | |
6197349b BW |
205 | |
206 | gab_ctl = I915_READ(GAB_CTL); | |
207 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
208 | ||
209 | ecochk = I915_READ(GAM_ECOCHK); | |
210 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | | |
211 | ECOCHK_PPGTT_CACHE64B); | |
212 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
213 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
a6f429a5 | 214 | uint32_t ecochk, ecobits; |
a65c2fcd VS |
215 | |
216 | ecobits = I915_READ(GAC_ECO_BITS); | |
217 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
218 | ||
a6f429a5 VS |
219 | ecochk = I915_READ(GAM_ECOCHK); |
220 | if (IS_HASWELL(dev)) { | |
221 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
222 | } else { | |
223 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
224 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
225 | } | |
226 | I915_WRITE(GAM_ECOCHK, ecochk); | |
6197349b BW |
227 | /* GFX_MODE is per-ring on gen7+ */ |
228 | } | |
229 | ||
230 | for_each_ring(ring, dev_priv, i) { | |
231 | if (INTEL_INFO(dev)->gen >= 7) | |
232 | I915_WRITE(RING_MODE_GEN7(ring), | |
233 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
234 | ||
235 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
236 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); | |
237 | } | |
b7c36d25 | 238 | return 0; |
6197349b BW |
239 | } |
240 | ||
1d2a314c | 241 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 242 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
1d2a314c | 243 | unsigned first_entry, |
828c7908 BW |
244 | unsigned num_entries, |
245 | bool use_scratch) | |
1d2a314c | 246 | { |
853ba5d2 BW |
247 | struct i915_hw_ppgtt *ppgtt = |
248 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 249 | gen6_gtt_pte_t *pt_vaddr, scratch_pte; |
a15326a5 | 250 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
7bddb01f DV |
251 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
252 | unsigned last_pte, i; | |
1d2a314c | 253 | |
b35b380e | 254 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true); |
1d2a314c | 255 | |
7bddb01f DV |
256 | while (num_entries) { |
257 | last_pte = first_pte + num_entries; | |
258 | if (last_pte > I915_PPGTT_PT_ENTRIES) | |
259 | last_pte = I915_PPGTT_PT_ENTRIES; | |
260 | ||
a15326a5 | 261 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
1d2a314c | 262 | |
7bddb01f DV |
263 | for (i = first_pte; i < last_pte; i++) |
264 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
265 | |
266 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 267 | |
7bddb01f DV |
268 | num_entries -= last_pte - first_pte; |
269 | first_pte = 0; | |
a15326a5 | 270 | act_pt++; |
7bddb01f | 271 | } |
1d2a314c DV |
272 | } |
273 | ||
853ba5d2 | 274 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 DV |
275 | struct sg_table *pages, |
276 | unsigned first_entry, | |
277 | enum i915_cache_level cache_level) | |
278 | { | |
853ba5d2 BW |
279 | struct i915_hw_ppgtt *ppgtt = |
280 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 281 | gen6_gtt_pte_t *pt_vaddr; |
a15326a5 | 282 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
6e995e23 ID |
283 | unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
284 | struct sg_page_iter sg_iter; | |
285 | ||
a15326a5 | 286 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
6e995e23 ID |
287 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
288 | dma_addr_t page_addr; | |
289 | ||
2db76d7c | 290 | page_addr = sg_page_iter_dma_address(&sg_iter); |
b35b380e | 291 | pt_vaddr[act_pte] = vm->pte_encode(page_addr, cache_level, true); |
6e995e23 ID |
292 | if (++act_pte == I915_PPGTT_PT_ENTRIES) { |
293 | kunmap_atomic(pt_vaddr); | |
a15326a5 DV |
294 | act_pt++; |
295 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); | |
6e995e23 | 296 | act_pte = 0; |
def886c3 | 297 | |
def886c3 | 298 | } |
def886c3 | 299 | } |
6e995e23 | 300 | kunmap_atomic(pt_vaddr); |
def886c3 DV |
301 | } |
302 | ||
853ba5d2 | 303 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
1d2a314c | 304 | { |
853ba5d2 BW |
305 | struct i915_hw_ppgtt *ppgtt = |
306 | container_of(vm, struct i915_hw_ppgtt, base); | |
3440d265 DV |
307 | int i; |
308 | ||
93bd8649 BW |
309 | drm_mm_takedown(&ppgtt->base.mm); |
310 | ||
3440d265 DV |
311 | if (ppgtt->pt_dma_addr) { |
312 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
853ba5d2 | 313 | pci_unmap_page(ppgtt->base.dev->pdev, |
3440d265 DV |
314 | ppgtt->pt_dma_addr[i], |
315 | 4096, PCI_DMA_BIDIRECTIONAL); | |
316 | } | |
317 | ||
318 | kfree(ppgtt->pt_dma_addr); | |
319 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
320 | __free_page(ppgtt->pt_pages[i]); | |
321 | kfree(ppgtt->pt_pages); | |
322 | kfree(ppgtt); | |
323 | } | |
324 | ||
325 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) | |
326 | { | |
853ba5d2 | 327 | struct drm_device *dev = ppgtt->base.dev; |
1d2a314c | 328 | struct drm_i915_private *dev_priv = dev->dev_private; |
1d2a314c | 329 | unsigned first_pd_entry_in_global_pt; |
1d2a314c DV |
330 | int i; |
331 | int ret = -ENOMEM; | |
332 | ||
333 | /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024 | |
334 | * entries. For aliasing ppgtt support we just steal them at the end for | |
335 | * now. */ | |
e1b73cba | 336 | first_pd_entry_in_global_pt = gtt_total_entries(dev_priv->gtt); |
1d2a314c | 337 | |
08c45263 | 338 | ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; |
6670a5a5 | 339 | ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES; |
6197349b | 340 | ppgtt->enable = gen6_ppgtt_enable; |
853ba5d2 BW |
341 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
342 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
343 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; | |
344 | ppgtt->base.scratch = dev_priv->gtt.base.scratch; | |
a1e22653 | 345 | ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *), |
1d2a314c DV |
346 | GFP_KERNEL); |
347 | if (!ppgtt->pt_pages) | |
3440d265 | 348 | return -ENOMEM; |
1d2a314c DV |
349 | |
350 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
351 | ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL); | |
352 | if (!ppgtt->pt_pages[i]) | |
353 | goto err_pt_alloc; | |
354 | } | |
355 | ||
a1e22653 | 356 | ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t), |
8d2e6308 BW |
357 | GFP_KERNEL); |
358 | if (!ppgtt->pt_dma_addr) | |
359 | goto err_pt_alloc; | |
1d2a314c | 360 | |
8d2e6308 BW |
361 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
362 | dma_addr_t pt_addr; | |
211c568b | 363 | |
8d2e6308 BW |
364 | pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096, |
365 | PCI_DMA_BIDIRECTIONAL); | |
1d2a314c | 366 | |
8d2e6308 BW |
367 | if (pci_dma_mapping_error(dev->pdev, pt_addr)) { |
368 | ret = -EIO; | |
369 | goto err_pd_pin; | |
1d2a314c | 370 | |
211c568b | 371 | } |
8d2e6308 | 372 | ppgtt->pt_dma_addr[i] = pt_addr; |
1d2a314c | 373 | } |
1d2a314c | 374 | |
853ba5d2 | 375 | ppgtt->base.clear_range(&ppgtt->base, 0, |
828c7908 | 376 | ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES, true); |
1d2a314c | 377 | |
e7c2b58b | 378 | ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t); |
1d2a314c | 379 | |
1d2a314c DV |
380 | return 0; |
381 | ||
382 | err_pd_pin: | |
383 | if (ppgtt->pt_dma_addr) { | |
384 | for (i--; i >= 0; i--) | |
385 | pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i], | |
386 | 4096, PCI_DMA_BIDIRECTIONAL); | |
387 | } | |
388 | err_pt_alloc: | |
389 | kfree(ppgtt->pt_dma_addr); | |
390 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
391 | if (ppgtt->pt_pages[i]) | |
392 | __free_page(ppgtt->pt_pages[i]); | |
393 | } | |
394 | kfree(ppgtt->pt_pages); | |
3440d265 DV |
395 | |
396 | return ret; | |
397 | } | |
398 | ||
399 | static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev) | |
400 | { | |
401 | struct drm_i915_private *dev_priv = dev->dev_private; | |
402 | struct i915_hw_ppgtt *ppgtt; | |
403 | int ret; | |
404 | ||
405 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
406 | if (!ppgtt) | |
407 | return -ENOMEM; | |
408 | ||
853ba5d2 | 409 | ppgtt->base.dev = dev; |
3440d265 | 410 | |
3ed124b2 BW |
411 | if (INTEL_INFO(dev)->gen < 8) |
412 | ret = gen6_ppgtt_init(ppgtt); | |
8fe6bd23 DV |
413 | else if (IS_GEN8(dev)) |
414 | ret = -ENOSYS; | |
3ed124b2 BW |
415 | else |
416 | BUG(); | |
417 | ||
3440d265 DV |
418 | if (ret) |
419 | kfree(ppgtt); | |
93bd8649 | 420 | else { |
3440d265 | 421 | dev_priv->mm.aliasing_ppgtt = ppgtt; |
93bd8649 BW |
422 | drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, |
423 | ppgtt->base.total); | |
424 | } | |
1d2a314c DV |
425 | |
426 | return ret; | |
427 | } | |
428 | ||
429 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev) | |
430 | { | |
431 | struct drm_i915_private *dev_priv = dev->dev_private; | |
432 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1d2a314c DV |
433 | |
434 | if (!ppgtt) | |
435 | return; | |
436 | ||
853ba5d2 | 437 | ppgtt->base.cleanup(&ppgtt->base); |
5963cf04 | 438 | dev_priv->mm.aliasing_ppgtt = NULL; |
1d2a314c DV |
439 | } |
440 | ||
7bddb01f DV |
441 | void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, |
442 | struct drm_i915_gem_object *obj, | |
443 | enum i915_cache_level cache_level) | |
444 | { | |
853ba5d2 BW |
445 | ppgtt->base.insert_entries(&ppgtt->base, obj->pages, |
446 | i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT, | |
447 | cache_level); | |
7bddb01f DV |
448 | } |
449 | ||
450 | void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, | |
451 | struct drm_i915_gem_object *obj) | |
452 | { | |
853ba5d2 BW |
453 | ppgtt->base.clear_range(&ppgtt->base, |
454 | i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT, | |
828c7908 BW |
455 | obj->base.size >> PAGE_SHIFT, |
456 | true); | |
7bddb01f DV |
457 | } |
458 | ||
a81cc00c BW |
459 | extern int intel_iommu_gfx_mapped; |
460 | /* Certain Gen5 chipsets require require idling the GPU before | |
461 | * unmapping anything from the GTT when VT-d is enabled. | |
462 | */ | |
463 | static inline bool needs_idle_maps(struct drm_device *dev) | |
464 | { | |
465 | #ifdef CONFIG_INTEL_IOMMU | |
466 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
467 | * was loaded first. | |
468 | */ | |
469 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
470 | return true; | |
471 | #endif | |
472 | return false; | |
473 | } | |
474 | ||
5c042287 BW |
475 | static bool do_idling(struct drm_i915_private *dev_priv) |
476 | { | |
477 | bool ret = dev_priv->mm.interruptible; | |
478 | ||
a81cc00c | 479 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 480 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 481 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
482 | DRM_ERROR("Couldn't idle GPU\n"); |
483 | /* Wait a bit, in hopes it avoids the hang */ | |
484 | udelay(10); | |
485 | } | |
486 | } | |
487 | ||
488 | return ret; | |
489 | } | |
490 | ||
491 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
492 | { | |
a81cc00c | 493 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
494 | dev_priv->mm.interruptible = interruptible; |
495 | } | |
496 | ||
828c7908 BW |
497 | void i915_check_and_clear_faults(struct drm_device *dev) |
498 | { | |
499 | struct drm_i915_private *dev_priv = dev->dev_private; | |
500 | struct intel_ring_buffer *ring; | |
501 | int i; | |
502 | ||
503 | if (INTEL_INFO(dev)->gen < 6) | |
504 | return; | |
505 | ||
506 | for_each_ring(ring, dev_priv, i) { | |
507 | u32 fault_reg; | |
508 | fault_reg = I915_READ(RING_FAULT_REG(ring)); | |
509 | if (fault_reg & RING_FAULT_VALID) { | |
510 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
511 | "\tAddr: 0x%08lx\\n" | |
512 | "\tAddress space: %s\n" | |
513 | "\tSource ID: %d\n" | |
514 | "\tType: %d\n", | |
515 | fault_reg & PAGE_MASK, | |
516 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
517 | RING_FAULT_SRCID(fault_reg), | |
518 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
519 | I915_WRITE(RING_FAULT_REG(ring), | |
520 | fault_reg & ~RING_FAULT_VALID); | |
521 | } | |
522 | } | |
523 | POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); | |
524 | } | |
525 | ||
526 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) | |
527 | { | |
528 | struct drm_i915_private *dev_priv = dev->dev_private; | |
529 | ||
530 | /* Don't bother messing with faults pre GEN6 as we have little | |
531 | * documentation supporting that it's a good idea. | |
532 | */ | |
533 | if (INTEL_INFO(dev)->gen < 6) | |
534 | return; | |
535 | ||
536 | i915_check_and_clear_faults(dev); | |
537 | ||
538 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, | |
539 | dev_priv->gtt.base.start / PAGE_SIZE, | |
540 | dev_priv->gtt.base.total / PAGE_SIZE, | |
541 | false); | |
542 | } | |
543 | ||
76aaf220 DV |
544 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
545 | { | |
546 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 547 | struct drm_i915_gem_object *obj; |
76aaf220 | 548 | |
828c7908 BW |
549 | i915_check_and_clear_faults(dev); |
550 | ||
bee4a186 | 551 | /* First fill our portion of the GTT with scratch pages */ |
853ba5d2 BW |
552 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
553 | dev_priv->gtt.base.start / PAGE_SIZE, | |
828c7908 BW |
554 | dev_priv->gtt.base.total / PAGE_SIZE, |
555 | true); | |
bee4a186 | 556 | |
35c20a60 | 557 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
2c22569b | 558 | i915_gem_clflush_object(obj, obj->pin_display); |
74163907 | 559 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
76aaf220 DV |
560 | } |
561 | ||
e76e9aeb | 562 | i915_gem_chipset_flush(dev); |
76aaf220 | 563 | } |
7c2e6fdf | 564 | |
74163907 | 565 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 566 | { |
9da3da66 | 567 | if (obj->has_dma_mapping) |
74163907 | 568 | return 0; |
9da3da66 CW |
569 | |
570 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
571 | obj->pages->sgl, obj->pages->nents, | |
572 | PCI_DMA_BIDIRECTIONAL)) | |
573 | return -ENOSPC; | |
574 | ||
575 | return 0; | |
7c2e6fdf DV |
576 | } |
577 | ||
e76e9aeb BW |
578 | /* |
579 | * Binds an object into the global gtt with the specified cache level. The object | |
580 | * will be accessible to the GPU via commands whose operands reference offsets | |
581 | * within the global GTT as well as accessible by the GPU through the GMADR | |
582 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
583 | */ | |
853ba5d2 | 584 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 DV |
585 | struct sg_table *st, |
586 | unsigned int first_entry, | |
587 | enum i915_cache_level level) | |
e76e9aeb | 588 | { |
853ba5d2 | 589 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
e7c2b58b BW |
590 | gen6_gtt_pte_t __iomem *gtt_entries = |
591 | (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
592 | int i = 0; |
593 | struct sg_page_iter sg_iter; | |
e76e9aeb BW |
594 | dma_addr_t addr; |
595 | ||
6e995e23 | 596 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 597 | addr = sg_page_iter_dma_address(&sg_iter); |
b35b380e | 598 | iowrite32(vm->pte_encode(addr, level, true), >t_entries[i]); |
6e995e23 | 599 | i++; |
e76e9aeb BW |
600 | } |
601 | ||
e76e9aeb BW |
602 | /* XXX: This serves as a posting read to make sure that the PTE has |
603 | * actually been updated. There is some concern that even though | |
604 | * registers and PTEs are within the same BAR that they are potentially | |
605 | * of NUMA access patterns. Therefore, even with the way we assume | |
606 | * hardware should work, we must keep this posting read for paranoia. | |
607 | */ | |
608 | if (i != 0) | |
853ba5d2 | 609 | WARN_ON(readl(>t_entries[i-1]) != |
b35b380e | 610 | vm->pte_encode(addr, level, true)); |
0f9b91c7 BW |
611 | |
612 | /* This next bit makes the above posting read even more important. We | |
613 | * want to flush the TLBs only after we're certain all the PTE updates | |
614 | * have finished. | |
615 | */ | |
616 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
617 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
618 | } |
619 | ||
853ba5d2 | 620 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
7faf1ab2 | 621 | unsigned int first_entry, |
828c7908 BW |
622 | unsigned int num_entries, |
623 | bool use_scratch) | |
7faf1ab2 | 624 | { |
853ba5d2 | 625 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
e7c2b58b BW |
626 | gen6_gtt_pte_t scratch_pte, __iomem *gtt_base = |
627 | (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 628 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
629 | int i; |
630 | ||
631 | if (WARN(num_entries > max_entries, | |
632 | "First entry = %d; Num entries = %d (max=%d)\n", | |
633 | first_entry, num_entries, max_entries)) | |
634 | num_entries = max_entries; | |
635 | ||
828c7908 BW |
636 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch); |
637 | ||
7faf1ab2 DV |
638 | for (i = 0; i < num_entries; i++) |
639 | iowrite32(scratch_pte, >t_base[i]); | |
640 | readl(gtt_base); | |
641 | } | |
642 | ||
643 | ||
853ba5d2 | 644 | static void i915_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 DV |
645 | struct sg_table *st, |
646 | unsigned int pg_start, | |
647 | enum i915_cache_level cache_level) | |
648 | { | |
649 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? | |
650 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
651 | ||
652 | intel_gtt_insert_sg_entries(st, pg_start, flags); | |
653 | ||
654 | } | |
655 | ||
853ba5d2 | 656 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
7faf1ab2 | 657 | unsigned int first_entry, |
828c7908 BW |
658 | unsigned int num_entries, |
659 | bool unused) | |
7faf1ab2 DV |
660 | { |
661 | intel_gtt_clear_range(first_entry, num_entries); | |
662 | } | |
663 | ||
664 | ||
74163907 DV |
665 | void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, |
666 | enum i915_cache_level cache_level) | |
d5bd1449 CW |
667 | { |
668 | struct drm_device *dev = obj->base.dev; | |
7faf1ab2 | 669 | struct drm_i915_private *dev_priv = dev->dev_private; |
853ba5d2 | 670 | const unsigned long entry = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT; |
7faf1ab2 | 671 | |
853ba5d2 BW |
672 | dev_priv->gtt.base.insert_entries(&dev_priv->gtt.base, obj->pages, |
673 | entry, | |
674 | cache_level); | |
d5bd1449 | 675 | |
74898d7e | 676 | obj->has_global_gtt_mapping = 1; |
d5bd1449 CW |
677 | } |
678 | ||
05394f39 | 679 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj) |
74163907 | 680 | { |
7faf1ab2 DV |
681 | struct drm_device *dev = obj->base.dev; |
682 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 | 683 | const unsigned long entry = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT; |
7faf1ab2 | 684 | |
853ba5d2 BW |
685 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
686 | entry, | |
828c7908 BW |
687 | obj->base.size >> PAGE_SHIFT, |
688 | true); | |
74898d7e DV |
689 | |
690 | obj->has_global_gtt_mapping = 0; | |
74163907 DV |
691 | } |
692 | ||
693 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 694 | { |
5c042287 BW |
695 | struct drm_device *dev = obj->base.dev; |
696 | struct drm_i915_private *dev_priv = dev->dev_private; | |
697 | bool interruptible; | |
698 | ||
699 | interruptible = do_idling(dev_priv); | |
700 | ||
9da3da66 CW |
701 | if (!obj->has_dma_mapping) |
702 | dma_unmap_sg(&dev->pdev->dev, | |
703 | obj->pages->sgl, obj->pages->nents, | |
704 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
705 | |
706 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 707 | } |
644ec02b | 708 | |
42d6ab48 CW |
709 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
710 | unsigned long color, | |
711 | unsigned long *start, | |
712 | unsigned long *end) | |
713 | { | |
714 | if (node->color != color) | |
715 | *start += 4096; | |
716 | ||
717 | if (!list_empty(&node->node_list)) { | |
718 | node = list_entry(node->node_list.next, | |
719 | struct drm_mm_node, | |
720 | node_list); | |
721 | if (node->allocated && node->color != color) | |
722 | *end -= 4096; | |
723 | } | |
724 | } | |
d7e5008f BW |
725 | void i915_gem_setup_global_gtt(struct drm_device *dev, |
726 | unsigned long start, | |
727 | unsigned long mappable_end, | |
728 | unsigned long end) | |
644ec02b | 729 | { |
e78891ca BW |
730 | /* Let GEM Manage all of the aperture. |
731 | * | |
732 | * However, leave one page at the end still bound to the scratch page. | |
733 | * There are a number of places where the hardware apparently prefetches | |
734 | * past the end of the object, and we've seen multiple hangs with the | |
735 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
736 | * aperture. One page should be enough to keep any prefetching inside | |
737 | * of the aperture. | |
738 | */ | |
40d74980 BW |
739 | struct drm_i915_private *dev_priv = dev->dev_private; |
740 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; | |
ed2f3452 CW |
741 | struct drm_mm_node *entry; |
742 | struct drm_i915_gem_object *obj; | |
743 | unsigned long hole_start, hole_end; | |
644ec02b | 744 | |
35451cb6 BW |
745 | BUG_ON(mappable_end > end); |
746 | ||
ed2f3452 | 747 | /* Subtract the guard page ... */ |
40d74980 | 748 | drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); |
42d6ab48 | 749 | if (!HAS_LLC(dev)) |
93bd8649 | 750 | dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; |
644ec02b | 751 | |
ed2f3452 | 752 | /* Mark any preallocated objects as occupied */ |
35c20a60 | 753 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
40d74980 | 754 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
b3a070cc | 755 | int ret; |
edd41a87 | 756 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
c6cfb325 BW |
757 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
758 | ||
759 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); | |
40d74980 | 760 | ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); |
c6cfb325 | 761 | if (ret) |
b3a070cc | 762 | DRM_DEBUG_KMS("Reservation failed\n"); |
ed2f3452 | 763 | obj->has_global_gtt_mapping = 1; |
2f633156 | 764 | list_add(&vma->vma_link, &obj->vma_list); |
ed2f3452 CW |
765 | } |
766 | ||
853ba5d2 BW |
767 | dev_priv->gtt.base.start = start; |
768 | dev_priv->gtt.base.total = end - start; | |
644ec02b | 769 | |
ed2f3452 | 770 | /* Clear any non-preallocated blocks */ |
40d74980 | 771 | drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { |
853ba5d2 | 772 | const unsigned long count = (hole_end - hole_start) / PAGE_SIZE; |
ed2f3452 CW |
773 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
774 | hole_start, hole_end); | |
828c7908 | 775 | ggtt_vm->clear_range(ggtt_vm, hole_start / PAGE_SIZE, count, true); |
ed2f3452 CW |
776 | } |
777 | ||
778 | /* And finally clear the reserved guard page */ | |
828c7908 | 779 | ggtt_vm->clear_range(ggtt_vm, end / PAGE_SIZE - 1, 1, true); |
e76e9aeb BW |
780 | } |
781 | ||
d7e5008f BW |
782 | static bool |
783 | intel_enable_ppgtt(struct drm_device *dev) | |
784 | { | |
785 | if (i915_enable_ppgtt >= 0) | |
786 | return i915_enable_ppgtt; | |
787 | ||
788 | #ifdef CONFIG_INTEL_IOMMU | |
789 | /* Disable ppgtt on SNB if VT-d is on. */ | |
790 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) | |
791 | return false; | |
792 | #endif | |
793 | ||
794 | return true; | |
795 | } | |
796 | ||
797 | void i915_gem_init_global_gtt(struct drm_device *dev) | |
798 | { | |
799 | struct drm_i915_private *dev_priv = dev->dev_private; | |
800 | unsigned long gtt_size, mappable_size; | |
d7e5008f | 801 | |
853ba5d2 | 802 | gtt_size = dev_priv->gtt.base.total; |
93d18799 | 803 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f BW |
804 | |
805 | if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { | |
e78891ca | 806 | int ret; |
3eb1c005 BW |
807 | |
808 | if (INTEL_INFO(dev)->gen <= 7) { | |
809 | /* PPGTT pdes are stolen from global gtt ptes, so shrink the | |
810 | * aperture accordingly when using aliasing ppgtt. */ | |
6670a5a5 | 811 | gtt_size -= GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE; |
3eb1c005 | 812 | } |
d7e5008f BW |
813 | |
814 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); | |
815 | ||
816 | ret = i915_gem_init_aliasing_ppgtt(dev); | |
e78891ca | 817 | if (!ret) |
d7e5008f | 818 | return; |
e78891ca BW |
819 | |
820 | DRM_ERROR("Aliased PPGTT setup failed %d\n", ret); | |
93bd8649 | 821 | drm_mm_takedown(&dev_priv->gtt.base.mm); |
6670a5a5 | 822 | gtt_size += GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE; |
d7e5008f | 823 | } |
e78891ca | 824 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
825 | } |
826 | ||
827 | static int setup_scratch_page(struct drm_device *dev) | |
828 | { | |
829 | struct drm_i915_private *dev_priv = dev->dev_private; | |
830 | struct page *page; | |
831 | dma_addr_t dma_addr; | |
832 | ||
833 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
834 | if (page == NULL) | |
835 | return -ENOMEM; | |
836 | get_page(page); | |
837 | set_pages_uc(page, 1); | |
838 | ||
839 | #ifdef CONFIG_INTEL_IOMMU | |
840 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
841 | PCI_DMA_BIDIRECTIONAL); | |
842 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) | |
843 | return -EINVAL; | |
844 | #else | |
845 | dma_addr = page_to_phys(page); | |
846 | #endif | |
853ba5d2 BW |
847 | dev_priv->gtt.base.scratch.page = page; |
848 | dev_priv->gtt.base.scratch.addr = dma_addr; | |
e76e9aeb BW |
849 | |
850 | return 0; | |
851 | } | |
852 | ||
853 | static void teardown_scratch_page(struct drm_device *dev) | |
854 | { | |
855 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 BW |
856 | struct page *page = dev_priv->gtt.base.scratch.page; |
857 | ||
858 | set_pages_wb(page, 1); | |
859 | pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr, | |
e76e9aeb | 860 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
853ba5d2 BW |
861 | put_page(page); |
862 | __free_page(page); | |
e76e9aeb BW |
863 | } |
864 | ||
865 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) | |
866 | { | |
867 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
868 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
869 | return snb_gmch_ctl << 20; | |
870 | } | |
871 | ||
baa09f5f | 872 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
873 | { |
874 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
875 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
876 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
877 | } | |
878 | ||
baa09f5f BW |
879 | static int gen6_gmch_probe(struct drm_device *dev, |
880 | size_t *gtt_total, | |
41907ddc BW |
881 | size_t *stolen, |
882 | phys_addr_t *mappable_base, | |
883 | unsigned long *mappable_end) | |
e76e9aeb BW |
884 | { |
885 | struct drm_i915_private *dev_priv = dev->dev_private; | |
886 | phys_addr_t gtt_bus_addr; | |
baa09f5f | 887 | unsigned int gtt_size; |
e76e9aeb | 888 | u16 snb_gmch_ctl; |
e76e9aeb BW |
889 | int ret; |
890 | ||
41907ddc BW |
891 | *mappable_base = pci_resource_start(dev->pdev, 2); |
892 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
893 | ||
baa09f5f BW |
894 | /* 64/512MB is the current min/max we actually know of, but this is just |
895 | * a coarse sanity check. | |
e76e9aeb | 896 | */ |
41907ddc | 897 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
baa09f5f BW |
898 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
899 | dev_priv->gtt.mappable_end); | |
900 | return -ENXIO; | |
e76e9aeb BW |
901 | } |
902 | ||
e76e9aeb BW |
903 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
904 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 905 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
baa09f5f | 906 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
e76e9aeb | 907 | |
c4ae25ec | 908 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
e7c2b58b | 909 | *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT; |
e76e9aeb | 910 | |
a93e4161 BW |
911 | /* For Modern GENs the PTEs and register space are split in the BAR */ |
912 | gtt_bus_addr = pci_resource_start(dev->pdev, 0) + | |
913 | (pci_resource_len(dev->pdev, 0) / 2); | |
914 | ||
baa09f5f | 915 | dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size); |
5d4545ae | 916 | if (!dev_priv->gtt.gsm) { |
e76e9aeb | 917 | DRM_ERROR("Failed to map the gtt page table\n"); |
baa09f5f | 918 | return -ENOMEM; |
e76e9aeb BW |
919 | } |
920 | ||
baa09f5f BW |
921 | ret = setup_scratch_page(dev); |
922 | if (ret) | |
923 | DRM_ERROR("Scratch setup failed\n"); | |
e76e9aeb | 924 | |
853ba5d2 BW |
925 | dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; |
926 | dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; | |
7faf1ab2 | 927 | |
e76e9aeb BW |
928 | return ret; |
929 | } | |
930 | ||
853ba5d2 | 931 | static void gen6_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 932 | { |
853ba5d2 BW |
933 | |
934 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); | |
935 | iounmap(gtt->gsm); | |
936 | teardown_scratch_page(vm->dev); | |
644ec02b | 937 | } |
baa09f5f BW |
938 | |
939 | static int i915_gmch_probe(struct drm_device *dev, | |
940 | size_t *gtt_total, | |
41907ddc BW |
941 | size_t *stolen, |
942 | phys_addr_t *mappable_base, | |
943 | unsigned long *mappable_end) | |
baa09f5f BW |
944 | { |
945 | struct drm_i915_private *dev_priv = dev->dev_private; | |
946 | int ret; | |
947 | ||
baa09f5f BW |
948 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
949 | if (!ret) { | |
950 | DRM_ERROR("failed to set up gmch\n"); | |
951 | return -EIO; | |
952 | } | |
953 | ||
41907ddc | 954 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
955 | |
956 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
853ba5d2 BW |
957 | dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; |
958 | dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries; | |
baa09f5f BW |
959 | |
960 | return 0; | |
961 | } | |
962 | ||
853ba5d2 | 963 | static void i915_gmch_remove(struct i915_address_space *vm) |
baa09f5f BW |
964 | { |
965 | intel_gmch_remove(); | |
966 | } | |
967 | ||
968 | int i915_gem_gtt_init(struct drm_device *dev) | |
969 | { | |
970 | struct drm_i915_private *dev_priv = dev->dev_private; | |
971 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
972 | int ret; |
973 | ||
baa09f5f | 974 | if (INTEL_INFO(dev)->gen <= 5) { |
b2f21b4d | 975 | gtt->gtt_probe = i915_gmch_probe; |
853ba5d2 | 976 | gtt->base.cleanup = i915_gmch_remove; |
baa09f5f | 977 | } else { |
b2f21b4d | 978 | gtt->gtt_probe = gen6_gmch_probe; |
853ba5d2 | 979 | gtt->base.cleanup = gen6_gmch_remove; |
4d15c145 | 980 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
853ba5d2 | 981 | gtt->base.pte_encode = iris_pte_encode; |
4d15c145 | 982 | else if (IS_HASWELL(dev)) |
853ba5d2 | 983 | gtt->base.pte_encode = hsw_pte_encode; |
b2f21b4d | 984 | else if (IS_VALLEYVIEW(dev)) |
853ba5d2 | 985 | gtt->base.pte_encode = byt_pte_encode; |
350ec881 CW |
986 | else if (INTEL_INFO(dev)->gen >= 7) |
987 | gtt->base.pte_encode = ivb_pte_encode; | |
b2f21b4d | 988 | else |
350ec881 | 989 | gtt->base.pte_encode = snb_pte_encode; |
baa09f5f BW |
990 | } |
991 | ||
853ba5d2 | 992 | ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, |
b2f21b4d | 993 | >t->mappable_base, >t->mappable_end); |
a54c0c27 | 994 | if (ret) |
baa09f5f | 995 | return ret; |
baa09f5f | 996 | |
853ba5d2 BW |
997 | gtt->base.dev = dev; |
998 | ||
baa09f5f | 999 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
853ba5d2 BW |
1000 | DRM_INFO("Memory usable by graphics device = %zdM\n", |
1001 | gtt->base.total >> 20); | |
b2f21b4d BW |
1002 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); |
1003 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); | |
baa09f5f BW |
1004 | |
1005 | return 0; | |
1006 | } |