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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
760285e7 DH |
25 | #include <drm/drmP.h> |
26 | #include <drm/i915_drm.h> | |
76aaf220 DV |
27 | #include "i915_drv.h" |
28 | #include "i915_trace.h" | |
29 | #include "intel_drv.h" | |
30 | ||
f61c0609 BW |
31 | typedef uint32_t gtt_pte_t; |
32 | ||
26b1ff35 BW |
33 | /* PPGTT stuff */ |
34 | #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) | |
35 | ||
36 | #define GEN6_PDE_VALID (1 << 0) | |
37 | /* gen6+ has bit 11-4 for physical addr bit 39-32 */ | |
38 | #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
39 | ||
40 | #define GEN6_PTE_VALID (1 << 0) | |
41 | #define GEN6_PTE_UNCACHED (1 << 1) | |
42 | #define HSW_PTE_UNCACHED (0) | |
43 | #define GEN6_PTE_CACHE_LLC (2 << 1) | |
44 | #define GEN6_PTE_CACHE_LLC_MLC (3 << 1) | |
45 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
46 | ||
960e3e42 DV |
47 | static inline gtt_pte_t gen6_pte_encode(struct drm_device *dev, |
48 | dma_addr_t addr, | |
49 | enum i915_cache_level level) | |
54d12527 BW |
50 | { |
51 | gtt_pte_t pte = GEN6_PTE_VALID; | |
52 | pte |= GEN6_PTE_ADDR_ENCODE(addr); | |
e7210c3c BW |
53 | |
54 | switch (level) { | |
55 | case I915_CACHE_LLC_MLC: | |
56 | /* Haswell doesn't set L3 this way */ | |
57 | if (IS_HASWELL(dev)) | |
58 | pte |= GEN6_PTE_CACHE_LLC; | |
59 | else | |
60 | pte |= GEN6_PTE_CACHE_LLC_MLC; | |
61 | break; | |
62 | case I915_CACHE_LLC: | |
63 | pte |= GEN6_PTE_CACHE_LLC; | |
64 | break; | |
65 | case I915_CACHE_NONE: | |
66 | if (IS_HASWELL(dev)) | |
67 | pte |= HSW_PTE_UNCACHED; | |
68 | else | |
69 | pte |= GEN6_PTE_UNCACHED; | |
70 | break; | |
71 | default: | |
72 | BUG(); | |
73 | } | |
74 | ||
54d12527 BW |
75 | |
76 | return pte; | |
77 | } | |
78 | ||
1d2a314c | 79 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
def886c3 | 80 | static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt, |
1d2a314c DV |
81 | unsigned first_entry, |
82 | unsigned num_entries) | |
83 | { | |
f61c0609 BW |
84 | gtt_pte_t *pt_vaddr; |
85 | gtt_pte_t scratch_pte; | |
a15326a5 | 86 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
7bddb01f DV |
87 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
88 | unsigned last_pte, i; | |
1d2a314c | 89 | |
960e3e42 DV |
90 | scratch_pte = gen6_pte_encode(ppgtt->dev, |
91 | ppgtt->scratch_page_dma_addr, | |
92 | I915_CACHE_LLC); | |
1d2a314c | 93 | |
7bddb01f DV |
94 | while (num_entries) { |
95 | last_pte = first_pte + num_entries; | |
96 | if (last_pte > I915_PPGTT_PT_ENTRIES) | |
97 | last_pte = I915_PPGTT_PT_ENTRIES; | |
98 | ||
a15326a5 | 99 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
1d2a314c | 100 | |
7bddb01f DV |
101 | for (i = first_pte; i < last_pte; i++) |
102 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
103 | |
104 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 105 | |
7bddb01f DV |
106 | num_entries -= last_pte - first_pte; |
107 | first_pte = 0; | |
a15326a5 | 108 | act_pt++; |
7bddb01f | 109 | } |
1d2a314c DV |
110 | } |
111 | ||
def886c3 DV |
112 | static void gen6_ppgtt_insert_entries(struct i915_hw_ppgtt *ppgtt, |
113 | struct sg_table *pages, | |
114 | unsigned first_entry, | |
115 | enum i915_cache_level cache_level) | |
116 | { | |
117 | gtt_pte_t *pt_vaddr; | |
a15326a5 | 118 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
6e995e23 ID |
119 | unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
120 | struct sg_page_iter sg_iter; | |
121 | ||
a15326a5 | 122 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
6e995e23 ID |
123 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
124 | dma_addr_t page_addr; | |
125 | ||
2db76d7c | 126 | page_addr = sg_page_iter_dma_address(&sg_iter); |
6e995e23 | 127 | pt_vaddr[act_pte] = gen6_pte_encode(ppgtt->dev, page_addr, |
6ddc4fc7 | 128 | cache_level); |
6e995e23 ID |
129 | if (++act_pte == I915_PPGTT_PT_ENTRIES) { |
130 | kunmap_atomic(pt_vaddr); | |
a15326a5 DV |
131 | act_pt++; |
132 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); | |
6e995e23 | 133 | act_pte = 0; |
def886c3 | 134 | |
def886c3 | 135 | } |
def886c3 | 136 | } |
6e995e23 | 137 | kunmap_atomic(pt_vaddr); |
def886c3 DV |
138 | } |
139 | ||
3440d265 | 140 | static void gen6_ppgtt_cleanup(struct i915_hw_ppgtt *ppgtt) |
1d2a314c | 141 | { |
3440d265 DV |
142 | int i; |
143 | ||
144 | if (ppgtt->pt_dma_addr) { | |
145 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
146 | pci_unmap_page(ppgtt->dev->pdev, | |
147 | ppgtt->pt_dma_addr[i], | |
148 | 4096, PCI_DMA_BIDIRECTIONAL); | |
149 | } | |
150 | ||
151 | kfree(ppgtt->pt_dma_addr); | |
152 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
153 | __free_page(ppgtt->pt_pages[i]); | |
154 | kfree(ppgtt->pt_pages); | |
155 | kfree(ppgtt); | |
156 | } | |
157 | ||
158 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) | |
159 | { | |
160 | struct drm_device *dev = ppgtt->dev; | |
1d2a314c | 161 | struct drm_i915_private *dev_priv = dev->dev_private; |
1d2a314c | 162 | unsigned first_pd_entry_in_global_pt; |
1d2a314c DV |
163 | int i; |
164 | int ret = -ENOMEM; | |
165 | ||
166 | /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024 | |
167 | * entries. For aliasing ppgtt support we just steal them at the end for | |
168 | * now. */ | |
a54c0c27 BW |
169 | first_pd_entry_in_global_pt = |
170 | gtt_total_entries(dev_priv->gtt) - I915_PPGTT_PD_ENTRIES; | |
1d2a314c | 171 | |
1d2a314c | 172 | ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES; |
def886c3 DV |
173 | ppgtt->clear_range = gen6_ppgtt_clear_range; |
174 | ppgtt->insert_entries = gen6_ppgtt_insert_entries; | |
3440d265 | 175 | ppgtt->cleanup = gen6_ppgtt_cleanup; |
1d2a314c DV |
176 | ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries, |
177 | GFP_KERNEL); | |
178 | if (!ppgtt->pt_pages) | |
3440d265 | 179 | return -ENOMEM; |
1d2a314c DV |
180 | |
181 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
182 | ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL); | |
183 | if (!ppgtt->pt_pages[i]) | |
184 | goto err_pt_alloc; | |
185 | } | |
186 | ||
8d2e6308 BW |
187 | ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t) *ppgtt->num_pd_entries, |
188 | GFP_KERNEL); | |
189 | if (!ppgtt->pt_dma_addr) | |
190 | goto err_pt_alloc; | |
1d2a314c | 191 | |
8d2e6308 BW |
192 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
193 | dma_addr_t pt_addr; | |
211c568b | 194 | |
8d2e6308 BW |
195 | pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096, |
196 | PCI_DMA_BIDIRECTIONAL); | |
1d2a314c | 197 | |
8d2e6308 BW |
198 | if (pci_dma_mapping_error(dev->pdev, pt_addr)) { |
199 | ret = -EIO; | |
200 | goto err_pd_pin; | |
1d2a314c | 201 | |
211c568b | 202 | } |
8d2e6308 | 203 | ppgtt->pt_dma_addr[i] = pt_addr; |
1d2a314c | 204 | } |
1d2a314c | 205 | |
9c61a32d | 206 | ppgtt->scratch_page_dma_addr = dev_priv->gtt.scratch_page_dma; |
1d2a314c | 207 | |
def886c3 DV |
208 | ppgtt->clear_range(ppgtt, 0, |
209 | ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES); | |
1d2a314c | 210 | |
f61c0609 | 211 | ppgtt->pd_offset = (first_pd_entry_in_global_pt)*sizeof(gtt_pte_t); |
1d2a314c | 212 | |
1d2a314c DV |
213 | return 0; |
214 | ||
215 | err_pd_pin: | |
216 | if (ppgtt->pt_dma_addr) { | |
217 | for (i--; i >= 0; i--) | |
218 | pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i], | |
219 | 4096, PCI_DMA_BIDIRECTIONAL); | |
220 | } | |
221 | err_pt_alloc: | |
222 | kfree(ppgtt->pt_dma_addr); | |
223 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
224 | if (ppgtt->pt_pages[i]) | |
225 | __free_page(ppgtt->pt_pages[i]); | |
226 | } | |
227 | kfree(ppgtt->pt_pages); | |
3440d265 DV |
228 | |
229 | return ret; | |
230 | } | |
231 | ||
232 | static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev) | |
233 | { | |
234 | struct drm_i915_private *dev_priv = dev->dev_private; | |
235 | struct i915_hw_ppgtt *ppgtt; | |
236 | int ret; | |
237 | ||
238 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
239 | if (!ppgtt) | |
240 | return -ENOMEM; | |
241 | ||
242 | ppgtt->dev = dev; | |
243 | ||
244 | ret = gen6_ppgtt_init(ppgtt); | |
245 | if (ret) | |
246 | kfree(ppgtt); | |
247 | else | |
248 | dev_priv->mm.aliasing_ppgtt = ppgtt; | |
1d2a314c DV |
249 | |
250 | return ret; | |
251 | } | |
252 | ||
253 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev) | |
254 | { | |
255 | struct drm_i915_private *dev_priv = dev->dev_private; | |
256 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1d2a314c DV |
257 | |
258 | if (!ppgtt) | |
259 | return; | |
260 | ||
3440d265 | 261 | ppgtt->cleanup(ppgtt); |
1d2a314c DV |
262 | } |
263 | ||
7bddb01f DV |
264 | void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, |
265 | struct drm_i915_gem_object *obj, | |
266 | enum i915_cache_level cache_level) | |
267 | { | |
def886c3 DV |
268 | ppgtt->insert_entries(ppgtt, obj->pages, |
269 | obj->gtt_space->start >> PAGE_SHIFT, | |
270 | cache_level); | |
7bddb01f DV |
271 | } |
272 | ||
273 | void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, | |
274 | struct drm_i915_gem_object *obj) | |
275 | { | |
def886c3 DV |
276 | ppgtt->clear_range(ppgtt, |
277 | obj->gtt_space->start >> PAGE_SHIFT, | |
278 | obj->base.size >> PAGE_SHIFT); | |
7bddb01f DV |
279 | } |
280 | ||
26b1ff35 BW |
281 | void i915_gem_init_ppgtt(struct drm_device *dev) |
282 | { | |
283 | drm_i915_private_t *dev_priv = dev->dev_private; | |
284 | uint32_t pd_offset; | |
285 | struct intel_ring_buffer *ring; | |
286 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
079a43f6 | 287 | gtt_pte_t __iomem *pd_addr; |
26b1ff35 BW |
288 | uint32_t pd_entry; |
289 | int i; | |
290 | ||
291 | if (!dev_priv->mm.aliasing_ppgtt) | |
292 | return; | |
293 | ||
294 | ||
5d4545ae | 295 | pd_addr = (gtt_pte_t __iomem*)dev_priv->gtt.gsm + ppgtt->pd_offset/sizeof(gtt_pte_t); |
26b1ff35 BW |
296 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
297 | dma_addr_t pt_addr; | |
298 | ||
8d2e6308 | 299 | pt_addr = ppgtt->pt_dma_addr[i]; |
26b1ff35 BW |
300 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); |
301 | pd_entry |= GEN6_PDE_VALID; | |
302 | ||
303 | writel(pd_entry, pd_addr + i); | |
304 | } | |
305 | readl(pd_addr); | |
306 | ||
307 | pd_offset = ppgtt->pd_offset; | |
308 | pd_offset /= 64; /* in cachelines, */ | |
309 | pd_offset <<= 16; | |
310 | ||
311 | if (INTEL_INFO(dev)->gen == 6) { | |
312 | uint32_t ecochk, gab_ctl, ecobits; | |
313 | ||
314 | ecobits = I915_READ(GAC_ECO_BITS); | |
315 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
316 | ||
317 | gab_ctl = I915_READ(GAB_CTL); | |
318 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
319 | ||
320 | ecochk = I915_READ(GAM_ECOCHK); | |
321 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | | |
322 | ECOCHK_PPGTT_CACHE64B); | |
323 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
324 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
325 | I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B); | |
326 | /* GFX_MODE is per-ring on gen7+ */ | |
327 | } | |
328 | ||
329 | for_each_ring(ring, dev_priv, i) { | |
330 | if (INTEL_INFO(dev)->gen >= 7) | |
331 | I915_WRITE(RING_MODE_GEN7(ring), | |
332 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
333 | ||
334 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
335 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); | |
336 | } | |
337 | } | |
338 | ||
a81cc00c BW |
339 | extern int intel_iommu_gfx_mapped; |
340 | /* Certain Gen5 chipsets require require idling the GPU before | |
341 | * unmapping anything from the GTT when VT-d is enabled. | |
342 | */ | |
343 | static inline bool needs_idle_maps(struct drm_device *dev) | |
344 | { | |
345 | #ifdef CONFIG_INTEL_IOMMU | |
346 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
347 | * was loaded first. | |
348 | */ | |
349 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
350 | return true; | |
351 | #endif | |
352 | return false; | |
353 | } | |
354 | ||
5c042287 BW |
355 | static bool do_idling(struct drm_i915_private *dev_priv) |
356 | { | |
357 | bool ret = dev_priv->mm.interruptible; | |
358 | ||
a81cc00c | 359 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 360 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 361 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
362 | DRM_ERROR("Couldn't idle GPU\n"); |
363 | /* Wait a bit, in hopes it avoids the hang */ | |
364 | udelay(10); | |
365 | } | |
366 | } | |
367 | ||
368 | return ret; | |
369 | } | |
370 | ||
371 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
372 | { | |
a81cc00c | 373 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
374 | dev_priv->mm.interruptible = interruptible; |
375 | } | |
376 | ||
76aaf220 DV |
377 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
378 | { | |
379 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 380 | struct drm_i915_gem_object *obj; |
76aaf220 | 381 | |
bee4a186 | 382 | /* First fill our portion of the GTT with scratch pages */ |
7faf1ab2 DV |
383 | dev_priv->gtt.gtt_clear_range(dev, dev_priv->gtt.start / PAGE_SIZE, |
384 | dev_priv->gtt.total / PAGE_SIZE); | |
bee4a186 | 385 | |
6c085a72 | 386 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) { |
a8e93126 | 387 | i915_gem_clflush_object(obj); |
74163907 | 388 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
76aaf220 DV |
389 | } |
390 | ||
e76e9aeb | 391 | i915_gem_chipset_flush(dev); |
76aaf220 | 392 | } |
7c2e6fdf | 393 | |
74163907 | 394 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 395 | { |
9da3da66 | 396 | if (obj->has_dma_mapping) |
74163907 | 397 | return 0; |
9da3da66 CW |
398 | |
399 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
400 | obj->pages->sgl, obj->pages->nents, | |
401 | PCI_DMA_BIDIRECTIONAL)) | |
402 | return -ENOSPC; | |
403 | ||
404 | return 0; | |
7c2e6fdf DV |
405 | } |
406 | ||
e76e9aeb BW |
407 | /* |
408 | * Binds an object into the global gtt with the specified cache level. The object | |
409 | * will be accessible to the GPU via commands whose operands reference offsets | |
410 | * within the global GTT as well as accessible by the GPU through the GMADR | |
411 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
412 | */ | |
7faf1ab2 DV |
413 | static void gen6_ggtt_insert_entries(struct drm_device *dev, |
414 | struct sg_table *st, | |
415 | unsigned int first_entry, | |
416 | enum i915_cache_level level) | |
e76e9aeb | 417 | { |
e76e9aeb | 418 | struct drm_i915_private *dev_priv = dev->dev_private; |
1c45140d | 419 | gtt_pte_t __iomem *gtt_entries = |
5d4545ae | 420 | (gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; |
6e995e23 ID |
421 | int i = 0; |
422 | struct sg_page_iter sg_iter; | |
e76e9aeb BW |
423 | dma_addr_t addr; |
424 | ||
6e995e23 | 425 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 426 | addr = sg_page_iter_dma_address(&sg_iter); |
6e995e23 ID |
427 | iowrite32(gen6_pte_encode(dev, addr, level), >t_entries[i]); |
428 | i++; | |
e76e9aeb BW |
429 | } |
430 | ||
e76e9aeb BW |
431 | /* XXX: This serves as a posting read to make sure that the PTE has |
432 | * actually been updated. There is some concern that even though | |
433 | * registers and PTEs are within the same BAR that they are potentially | |
434 | * of NUMA access patterns. Therefore, even with the way we assume | |
435 | * hardware should work, we must keep this posting read for paranoia. | |
436 | */ | |
437 | if (i != 0) | |
960e3e42 DV |
438 | WARN_ON(readl(>t_entries[i-1]) |
439 | != gen6_pte_encode(dev, addr, level)); | |
0f9b91c7 BW |
440 | |
441 | /* This next bit makes the above posting read even more important. We | |
442 | * want to flush the TLBs only after we're certain all the PTE updates | |
443 | * have finished. | |
444 | */ | |
445 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
446 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
447 | } |
448 | ||
7faf1ab2 DV |
449 | static void gen6_ggtt_clear_range(struct drm_device *dev, |
450 | unsigned int first_entry, | |
451 | unsigned int num_entries) | |
452 | { | |
453 | struct drm_i915_private *dev_priv = dev->dev_private; | |
454 | gtt_pte_t scratch_pte; | |
455 | gtt_pte_t __iomem *gtt_base = (gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 456 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
457 | int i; |
458 | ||
459 | if (WARN(num_entries > max_entries, | |
460 | "First entry = %d; Num entries = %d (max=%d)\n", | |
461 | first_entry, num_entries, max_entries)) | |
462 | num_entries = max_entries; | |
463 | ||
960e3e42 DV |
464 | scratch_pte = gen6_pte_encode(dev, dev_priv->gtt.scratch_page_dma, |
465 | I915_CACHE_LLC); | |
7faf1ab2 DV |
466 | for (i = 0; i < num_entries; i++) |
467 | iowrite32(scratch_pte, >t_base[i]); | |
468 | readl(gtt_base); | |
469 | } | |
470 | ||
471 | ||
472 | static void i915_ggtt_insert_entries(struct drm_device *dev, | |
473 | struct sg_table *st, | |
474 | unsigned int pg_start, | |
475 | enum i915_cache_level cache_level) | |
476 | { | |
477 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? | |
478 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
479 | ||
480 | intel_gtt_insert_sg_entries(st, pg_start, flags); | |
481 | ||
482 | } | |
483 | ||
484 | static void i915_ggtt_clear_range(struct drm_device *dev, | |
485 | unsigned int first_entry, | |
486 | unsigned int num_entries) | |
487 | { | |
488 | intel_gtt_clear_range(first_entry, num_entries); | |
489 | } | |
490 | ||
491 | ||
74163907 DV |
492 | void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, |
493 | enum i915_cache_level cache_level) | |
d5bd1449 CW |
494 | { |
495 | struct drm_device *dev = obj->base.dev; | |
7faf1ab2 DV |
496 | struct drm_i915_private *dev_priv = dev->dev_private; |
497 | ||
498 | dev_priv->gtt.gtt_insert_entries(dev, obj->pages, | |
499 | obj->gtt_space->start >> PAGE_SHIFT, | |
500 | cache_level); | |
d5bd1449 | 501 | |
74898d7e | 502 | obj->has_global_gtt_mapping = 1; |
d5bd1449 CW |
503 | } |
504 | ||
05394f39 | 505 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj) |
74163907 | 506 | { |
7faf1ab2 DV |
507 | struct drm_device *dev = obj->base.dev; |
508 | struct drm_i915_private *dev_priv = dev->dev_private; | |
509 | ||
510 | dev_priv->gtt.gtt_clear_range(obj->base.dev, | |
511 | obj->gtt_space->start >> PAGE_SHIFT, | |
512 | obj->base.size >> PAGE_SHIFT); | |
74898d7e DV |
513 | |
514 | obj->has_global_gtt_mapping = 0; | |
74163907 DV |
515 | } |
516 | ||
517 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 518 | { |
5c042287 BW |
519 | struct drm_device *dev = obj->base.dev; |
520 | struct drm_i915_private *dev_priv = dev->dev_private; | |
521 | bool interruptible; | |
522 | ||
523 | interruptible = do_idling(dev_priv); | |
524 | ||
9da3da66 CW |
525 | if (!obj->has_dma_mapping) |
526 | dma_unmap_sg(&dev->pdev->dev, | |
527 | obj->pages->sgl, obj->pages->nents, | |
528 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
529 | |
530 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 531 | } |
644ec02b | 532 | |
42d6ab48 CW |
533 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
534 | unsigned long color, | |
535 | unsigned long *start, | |
536 | unsigned long *end) | |
537 | { | |
538 | if (node->color != color) | |
539 | *start += 4096; | |
540 | ||
541 | if (!list_empty(&node->node_list)) { | |
542 | node = list_entry(node->node_list.next, | |
543 | struct drm_mm_node, | |
544 | node_list); | |
545 | if (node->allocated && node->color != color) | |
546 | *end -= 4096; | |
547 | } | |
548 | } | |
d7e5008f BW |
549 | void i915_gem_setup_global_gtt(struct drm_device *dev, |
550 | unsigned long start, | |
551 | unsigned long mappable_end, | |
552 | unsigned long end) | |
644ec02b | 553 | { |
e78891ca BW |
554 | /* Let GEM Manage all of the aperture. |
555 | * | |
556 | * However, leave one page at the end still bound to the scratch page. | |
557 | * There are a number of places where the hardware apparently prefetches | |
558 | * past the end of the object, and we've seen multiple hangs with the | |
559 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
560 | * aperture. One page should be enough to keep any prefetching inside | |
561 | * of the aperture. | |
562 | */ | |
644ec02b | 563 | drm_i915_private_t *dev_priv = dev->dev_private; |
ed2f3452 CW |
564 | struct drm_mm_node *entry; |
565 | struct drm_i915_gem_object *obj; | |
566 | unsigned long hole_start, hole_end; | |
644ec02b | 567 | |
35451cb6 BW |
568 | BUG_ON(mappable_end > end); |
569 | ||
ed2f3452 | 570 | /* Subtract the guard page ... */ |
d1dd20a9 | 571 | drm_mm_init(&dev_priv->mm.gtt_space, start, end - start - PAGE_SIZE); |
42d6ab48 CW |
572 | if (!HAS_LLC(dev)) |
573 | dev_priv->mm.gtt_space.color_adjust = i915_gtt_color_adjust; | |
644ec02b | 574 | |
ed2f3452 CW |
575 | /* Mark any preallocated objects as occupied */ |
576 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) { | |
577 | DRM_DEBUG_KMS("reserving preallocated space: %x + %zx\n", | |
578 | obj->gtt_offset, obj->base.size); | |
579 | ||
580 | BUG_ON(obj->gtt_space != I915_GTT_RESERVED); | |
581 | obj->gtt_space = drm_mm_create_block(&dev_priv->mm.gtt_space, | |
582 | obj->gtt_offset, | |
583 | obj->base.size, | |
584 | false); | |
585 | obj->has_global_gtt_mapping = 1; | |
586 | } | |
587 | ||
5d4545ae | 588 | dev_priv->gtt.start = start; |
5d4545ae | 589 | dev_priv->gtt.total = end - start; |
644ec02b | 590 | |
ed2f3452 CW |
591 | /* Clear any non-preallocated blocks */ |
592 | drm_mm_for_each_hole(entry, &dev_priv->mm.gtt_space, | |
593 | hole_start, hole_end) { | |
594 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", | |
595 | hole_start, hole_end); | |
7faf1ab2 DV |
596 | dev_priv->gtt.gtt_clear_range(dev, hole_start / PAGE_SIZE, |
597 | (hole_end-hole_start) / PAGE_SIZE); | |
ed2f3452 CW |
598 | } |
599 | ||
600 | /* And finally clear the reserved guard page */ | |
7faf1ab2 | 601 | dev_priv->gtt.gtt_clear_range(dev, end / PAGE_SIZE - 1, 1); |
e76e9aeb BW |
602 | } |
603 | ||
d7e5008f BW |
604 | static bool |
605 | intel_enable_ppgtt(struct drm_device *dev) | |
606 | { | |
607 | if (i915_enable_ppgtt >= 0) | |
608 | return i915_enable_ppgtt; | |
609 | ||
610 | #ifdef CONFIG_INTEL_IOMMU | |
611 | /* Disable ppgtt on SNB if VT-d is on. */ | |
612 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) | |
613 | return false; | |
614 | #endif | |
615 | ||
616 | return true; | |
617 | } | |
618 | ||
619 | void i915_gem_init_global_gtt(struct drm_device *dev) | |
620 | { | |
621 | struct drm_i915_private *dev_priv = dev->dev_private; | |
622 | unsigned long gtt_size, mappable_size; | |
d7e5008f | 623 | |
a54c0c27 | 624 | gtt_size = dev_priv->gtt.total; |
93d18799 | 625 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f BW |
626 | |
627 | if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { | |
e78891ca | 628 | int ret; |
d7e5008f BW |
629 | /* PPGTT pdes are stolen from global gtt ptes, so shrink the |
630 | * aperture accordingly when using aliasing ppgtt. */ | |
631 | gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE; | |
632 | ||
633 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); | |
634 | ||
635 | ret = i915_gem_init_aliasing_ppgtt(dev); | |
e78891ca | 636 | if (!ret) |
d7e5008f | 637 | return; |
e78891ca BW |
638 | |
639 | DRM_ERROR("Aliased PPGTT setup failed %d\n", ret); | |
640 | drm_mm_takedown(&dev_priv->mm.gtt_space); | |
641 | gtt_size += I915_PPGTT_PD_ENTRIES*PAGE_SIZE; | |
d7e5008f | 642 | } |
e78891ca | 643 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
644 | } |
645 | ||
646 | static int setup_scratch_page(struct drm_device *dev) | |
647 | { | |
648 | struct drm_i915_private *dev_priv = dev->dev_private; | |
649 | struct page *page; | |
650 | dma_addr_t dma_addr; | |
651 | ||
652 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
653 | if (page == NULL) | |
654 | return -ENOMEM; | |
655 | get_page(page); | |
656 | set_pages_uc(page, 1); | |
657 | ||
658 | #ifdef CONFIG_INTEL_IOMMU | |
659 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
660 | PCI_DMA_BIDIRECTIONAL); | |
661 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) | |
662 | return -EINVAL; | |
663 | #else | |
664 | dma_addr = page_to_phys(page); | |
665 | #endif | |
9c61a32d BW |
666 | dev_priv->gtt.scratch_page = page; |
667 | dev_priv->gtt.scratch_page_dma = dma_addr; | |
e76e9aeb BW |
668 | |
669 | return 0; | |
670 | } | |
671 | ||
672 | static void teardown_scratch_page(struct drm_device *dev) | |
673 | { | |
674 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9c61a32d BW |
675 | set_pages_wb(dev_priv->gtt.scratch_page, 1); |
676 | pci_unmap_page(dev->pdev, dev_priv->gtt.scratch_page_dma, | |
e76e9aeb | 677 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
9c61a32d BW |
678 | put_page(dev_priv->gtt.scratch_page); |
679 | __free_page(dev_priv->gtt.scratch_page); | |
e76e9aeb BW |
680 | } |
681 | ||
682 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) | |
683 | { | |
684 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
685 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
686 | return snb_gmch_ctl << 20; | |
687 | } | |
688 | ||
baa09f5f | 689 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
690 | { |
691 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
692 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
693 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
694 | } | |
695 | ||
baa09f5f | 696 | static inline size_t gen7_get_stolen_size(u16 snb_gmch_ctl) |
03752f5b BW |
697 | { |
698 | static const int stolen_decoder[] = { | |
699 | 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352}; | |
700 | snb_gmch_ctl >>= IVB_GMCH_GMS_SHIFT; | |
701 | snb_gmch_ctl &= IVB_GMCH_GMS_MASK; | |
702 | return stolen_decoder[snb_gmch_ctl] << 20; | |
703 | } | |
704 | ||
baa09f5f BW |
705 | static int gen6_gmch_probe(struct drm_device *dev, |
706 | size_t *gtt_total, | |
41907ddc BW |
707 | size_t *stolen, |
708 | phys_addr_t *mappable_base, | |
709 | unsigned long *mappable_end) | |
e76e9aeb BW |
710 | { |
711 | struct drm_i915_private *dev_priv = dev->dev_private; | |
712 | phys_addr_t gtt_bus_addr; | |
baa09f5f | 713 | unsigned int gtt_size; |
e76e9aeb | 714 | u16 snb_gmch_ctl; |
e76e9aeb BW |
715 | int ret; |
716 | ||
41907ddc BW |
717 | *mappable_base = pci_resource_start(dev->pdev, 2); |
718 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
719 | ||
baa09f5f BW |
720 | /* 64/512MB is the current min/max we actually know of, but this is just |
721 | * a coarse sanity check. | |
e76e9aeb | 722 | */ |
41907ddc | 723 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
baa09f5f BW |
724 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
725 | dev_priv->gtt.mappable_end); | |
726 | return -ENXIO; | |
e76e9aeb BW |
727 | } |
728 | ||
e76e9aeb BW |
729 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
730 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 731 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
baa09f5f | 732 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
e76e9aeb | 733 | |
086ddcce | 734 | if (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) |
baa09f5f BW |
735 | *stolen = gen7_get_stolen_size(snb_gmch_ctl); |
736 | else | |
737 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); | |
e76e9aeb | 738 | |
baa09f5f | 739 | *gtt_total = (gtt_size / sizeof(gtt_pte_t)) << PAGE_SHIFT; |
e76e9aeb | 740 | |
baa09f5f BW |
741 | /* For GEN6+ the PTEs for the ggtt live at 2MB + BAR0 */ |
742 | gtt_bus_addr = pci_resource_start(dev->pdev, 0) + (2<<20); | |
743 | dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size); | |
5d4545ae | 744 | if (!dev_priv->gtt.gsm) { |
e76e9aeb | 745 | DRM_ERROR("Failed to map the gtt page table\n"); |
baa09f5f | 746 | return -ENOMEM; |
e76e9aeb BW |
747 | } |
748 | ||
baa09f5f BW |
749 | ret = setup_scratch_page(dev); |
750 | if (ret) | |
751 | DRM_ERROR("Scratch setup failed\n"); | |
e76e9aeb | 752 | |
7faf1ab2 DV |
753 | dev_priv->gtt.gtt_clear_range = gen6_ggtt_clear_range; |
754 | dev_priv->gtt.gtt_insert_entries = gen6_ggtt_insert_entries; | |
755 | ||
e76e9aeb BW |
756 | return ret; |
757 | } | |
758 | ||
d93c6233 | 759 | static void gen6_gmch_remove(struct drm_device *dev) |
e76e9aeb BW |
760 | { |
761 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5d4545ae | 762 | iounmap(dev_priv->gtt.gsm); |
baa09f5f | 763 | teardown_scratch_page(dev_priv->dev); |
644ec02b | 764 | } |
baa09f5f BW |
765 | |
766 | static int i915_gmch_probe(struct drm_device *dev, | |
767 | size_t *gtt_total, | |
41907ddc BW |
768 | size_t *stolen, |
769 | phys_addr_t *mappable_base, | |
770 | unsigned long *mappable_end) | |
baa09f5f BW |
771 | { |
772 | struct drm_i915_private *dev_priv = dev->dev_private; | |
773 | int ret; | |
774 | ||
baa09f5f BW |
775 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
776 | if (!ret) { | |
777 | DRM_ERROR("failed to set up gmch\n"); | |
778 | return -EIO; | |
779 | } | |
780 | ||
41907ddc | 781 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
782 | |
783 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
784 | dev_priv->gtt.gtt_clear_range = i915_ggtt_clear_range; | |
785 | dev_priv->gtt.gtt_insert_entries = i915_ggtt_insert_entries; | |
786 | ||
787 | return 0; | |
788 | } | |
789 | ||
790 | static void i915_gmch_remove(struct drm_device *dev) | |
791 | { | |
792 | intel_gmch_remove(); | |
793 | } | |
794 | ||
795 | int i915_gem_gtt_init(struct drm_device *dev) | |
796 | { | |
797 | struct drm_i915_private *dev_priv = dev->dev_private; | |
798 | struct i915_gtt *gtt = &dev_priv->gtt; | |
799 | unsigned long gtt_size; | |
800 | int ret; | |
801 | ||
baa09f5f BW |
802 | if (INTEL_INFO(dev)->gen <= 5) { |
803 | dev_priv->gtt.gtt_probe = i915_gmch_probe; | |
804 | dev_priv->gtt.gtt_remove = i915_gmch_remove; | |
805 | } else { | |
806 | dev_priv->gtt.gtt_probe = gen6_gmch_probe; | |
807 | dev_priv->gtt.gtt_remove = gen6_gmch_remove; | |
808 | } | |
809 | ||
810 | ret = dev_priv->gtt.gtt_probe(dev, &dev_priv->gtt.total, | |
41907ddc BW |
811 | &dev_priv->gtt.stolen_size, |
812 | >t->mappable_base, | |
813 | >t->mappable_end); | |
a54c0c27 | 814 | if (ret) |
baa09f5f | 815 | return ret; |
baa09f5f BW |
816 | |
817 | gtt_size = (dev_priv->gtt.total >> PAGE_SHIFT) * sizeof(gtt_pte_t); | |
818 | ||
819 | /* GMADR is the PCI mmio aperture into the global GTT. */ | |
820 | DRM_INFO("Memory usable by graphics device = %zdM\n", | |
821 | dev_priv->gtt.total >> 20); | |
822 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", | |
823 | dev_priv->gtt.mappable_end >> 20); | |
824 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", | |
825 | dev_priv->gtt.stolen_size >> 20); | |
826 | ||
827 | return 0; | |
828 | } |