Commit | Line | Data |
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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
c4ac524c | 3 | * Copyright © 2011-2014 Intel Corporation |
76aaf220 DV |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
0e46ce2e | 26 | #include <linux/seq_file.h> |
760285e7 DH |
27 | #include <drm/drmP.h> |
28 | #include <drm/i915_drm.h> | |
76aaf220 | 29 | #include "i915_drv.h" |
5dda8fa3 | 30 | #include "i915_vgpu.h" |
76aaf220 DV |
31 | #include "i915_trace.h" |
32 | #include "intel_drv.h" | |
33 | ||
45f8f69a TU |
34 | /** |
35 | * DOC: Global GTT views | |
36 | * | |
37 | * Background and previous state | |
38 | * | |
39 | * Historically objects could exists (be bound) in global GTT space only as | |
40 | * singular instances with a view representing all of the object's backing pages | |
41 | * in a linear fashion. This view will be called a normal view. | |
42 | * | |
43 | * To support multiple views of the same object, where the number of mapped | |
44 | * pages is not equal to the backing store, or where the layout of the pages | |
45 | * is not linear, concept of a GGTT view was added. | |
46 | * | |
47 | * One example of an alternative view is a stereo display driven by a single | |
48 | * image. In this case we would have a framebuffer looking like this | |
49 | * (2x2 pages): | |
50 | * | |
51 | * 12 | |
52 | * 34 | |
53 | * | |
54 | * Above would represent a normal GGTT view as normally mapped for GPU or CPU | |
55 | * rendering. In contrast, fed to the display engine would be an alternative | |
56 | * view which could look something like this: | |
57 | * | |
58 | * 1212 | |
59 | * 3434 | |
60 | * | |
61 | * In this example both the size and layout of pages in the alternative view is | |
62 | * different from the normal view. | |
63 | * | |
64 | * Implementation and usage | |
65 | * | |
66 | * GGTT views are implemented using VMAs and are distinguished via enum | |
67 | * i915_ggtt_view_type and struct i915_ggtt_view. | |
68 | * | |
69 | * A new flavour of core GEM functions which work with GGTT bound objects were | |
ec7adb6e JL |
70 | * added with the _ggtt_ infix, and sometimes with _view postfix to avoid |
71 | * renaming in large amounts of code. They take the struct i915_ggtt_view | |
72 | * parameter encapsulating all metadata required to implement a view. | |
45f8f69a TU |
73 | * |
74 | * As a helper for callers which are only interested in the normal view, | |
75 | * globally const i915_ggtt_view_normal singleton instance exists. All old core | |
76 | * GEM API functions, the ones not taking the view parameter, are operating on, | |
77 | * or with the normal GGTT view. | |
78 | * | |
79 | * Code wanting to add or use a new GGTT view needs to: | |
80 | * | |
81 | * 1. Add a new enum with a suitable name. | |
82 | * 2. Extend the metadata in the i915_ggtt_view structure if required. | |
83 | * 3. Add support to i915_get_vma_pages(). | |
84 | * | |
85 | * New views are required to build a scatter-gather table from within the | |
86 | * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and | |
87 | * exists for the lifetime of an VMA. | |
88 | * | |
89 | * Core API is designed to have copy semantics which means that passed in | |
90 | * struct i915_ggtt_view does not need to be persistent (left around after | |
91 | * calling the core API functions). | |
92 | * | |
93 | */ | |
94 | ||
70b9f6f8 DV |
95 | static int |
96 | i915_get_ggtt_vma_pages(struct i915_vma *vma); | |
97 | ||
fe14d5f4 | 98 | const struct i915_ggtt_view i915_ggtt_view_normal; |
9abc4648 JL |
99 | const struct i915_ggtt_view i915_ggtt_view_rotated = { |
100 | .type = I915_GGTT_VIEW_ROTATED | |
101 | }; | |
fe14d5f4 | 102 | |
cfa7c862 DV |
103 | static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt) |
104 | { | |
1893a71b CW |
105 | bool has_aliasing_ppgtt; |
106 | bool has_full_ppgtt; | |
107 | ||
108 | has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6; | |
109 | has_full_ppgtt = INTEL_INFO(dev)->gen >= 7; | |
1893a71b | 110 | |
71ba2d64 YZ |
111 | if (intel_vgpu_active(dev)) |
112 | has_full_ppgtt = false; /* emulation is too hard */ | |
113 | ||
70ee45e1 DL |
114 | /* |
115 | * We don't allow disabling PPGTT for gen9+ as it's a requirement for | |
116 | * execlists, the sole mechanism available to submit work. | |
117 | */ | |
118 | if (INTEL_INFO(dev)->gen < 9 && | |
119 | (enable_ppgtt == 0 || !has_aliasing_ppgtt)) | |
cfa7c862 DV |
120 | return 0; |
121 | ||
122 | if (enable_ppgtt == 1) | |
123 | return 1; | |
124 | ||
1893a71b | 125 | if (enable_ppgtt == 2 && has_full_ppgtt) |
cfa7c862 DV |
126 | return 2; |
127 | ||
93a25a9e DV |
128 | #ifdef CONFIG_INTEL_IOMMU |
129 | /* Disable ppgtt on SNB if VT-d is on. */ | |
130 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) { | |
131 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); | |
cfa7c862 | 132 | return 0; |
93a25a9e DV |
133 | } |
134 | #endif | |
135 | ||
62942ed7 | 136 | /* Early VLV doesn't have this */ |
ca2aed6c VS |
137 | if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
138 | dev->pdev->revision < 0xb) { | |
62942ed7 JB |
139 | DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n"); |
140 | return 0; | |
141 | } | |
142 | ||
2f82bbdf MT |
143 | if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists) |
144 | return 2; | |
145 | else | |
146 | return has_aliasing_ppgtt ? 1 : 0; | |
93a25a9e DV |
147 | } |
148 | ||
70b9f6f8 DV |
149 | static int ppgtt_bind_vma(struct i915_vma *vma, |
150 | enum i915_cache_level cache_level, | |
151 | u32 unused) | |
47552659 DV |
152 | { |
153 | u32 pte_flags = 0; | |
154 | ||
155 | /* Currently applicable only to VLV */ | |
156 | if (vma->obj->gt_ro) | |
157 | pte_flags |= PTE_READ_ONLY; | |
158 | ||
159 | vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start, | |
160 | cache_level, pte_flags); | |
70b9f6f8 DV |
161 | |
162 | return 0; | |
47552659 DV |
163 | } |
164 | ||
165 | static void ppgtt_unbind_vma(struct i915_vma *vma) | |
166 | { | |
167 | vma->vm->clear_range(vma->vm, | |
168 | vma->node.start, | |
169 | vma->obj->base.size, | |
170 | true); | |
171 | } | |
6f65e29a | 172 | |
2c642b07 DV |
173 | static gen8_pte_t gen8_pte_encode(dma_addr_t addr, |
174 | enum i915_cache_level level, | |
175 | bool valid) | |
94ec8f61 | 176 | { |
07749ef3 | 177 | gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; |
94ec8f61 | 178 | pte |= addr; |
63c42e56 BW |
179 | |
180 | switch (level) { | |
181 | case I915_CACHE_NONE: | |
fbe5d36e | 182 | pte |= PPAT_UNCACHED_INDEX; |
63c42e56 BW |
183 | break; |
184 | case I915_CACHE_WT: | |
185 | pte |= PPAT_DISPLAY_ELLC_INDEX; | |
186 | break; | |
187 | default: | |
188 | pte |= PPAT_CACHED_INDEX; | |
189 | break; | |
190 | } | |
191 | ||
94ec8f61 BW |
192 | return pte; |
193 | } | |
194 | ||
2c642b07 DV |
195 | static gen8_pde_t gen8_pde_encode(struct drm_device *dev, |
196 | dma_addr_t addr, | |
197 | enum i915_cache_level level) | |
b1fe6673 | 198 | { |
07749ef3 | 199 | gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW; |
b1fe6673 BW |
200 | pde |= addr; |
201 | if (level != I915_CACHE_NONE) | |
202 | pde |= PPAT_CACHED_PDE_INDEX; | |
203 | else | |
204 | pde |= PPAT_UNCACHED_INDEX; | |
205 | return pde; | |
206 | } | |
207 | ||
07749ef3 MT |
208 | static gen6_pte_t snb_pte_encode(dma_addr_t addr, |
209 | enum i915_cache_level level, | |
210 | bool valid, u32 unused) | |
54d12527 | 211 | { |
07749ef3 | 212 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
54d12527 | 213 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
214 | |
215 | switch (level) { | |
350ec881 CW |
216 | case I915_CACHE_L3_LLC: |
217 | case I915_CACHE_LLC: | |
218 | pte |= GEN6_PTE_CACHE_LLC; | |
219 | break; | |
220 | case I915_CACHE_NONE: | |
221 | pte |= GEN6_PTE_UNCACHED; | |
222 | break; | |
223 | default: | |
5f77eeb0 | 224 | MISSING_CASE(level); |
350ec881 CW |
225 | } |
226 | ||
227 | return pte; | |
228 | } | |
229 | ||
07749ef3 MT |
230 | static gen6_pte_t ivb_pte_encode(dma_addr_t addr, |
231 | enum i915_cache_level level, | |
232 | bool valid, u32 unused) | |
350ec881 | 233 | { |
07749ef3 | 234 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
350ec881 CW |
235 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
236 | ||
237 | switch (level) { | |
238 | case I915_CACHE_L3_LLC: | |
239 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
240 | break; |
241 | case I915_CACHE_LLC: | |
242 | pte |= GEN6_PTE_CACHE_LLC; | |
243 | break; | |
244 | case I915_CACHE_NONE: | |
9119708c | 245 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
246 | break; |
247 | default: | |
5f77eeb0 | 248 | MISSING_CASE(level); |
e7210c3c BW |
249 | } |
250 | ||
54d12527 BW |
251 | return pte; |
252 | } | |
253 | ||
07749ef3 MT |
254 | static gen6_pte_t byt_pte_encode(dma_addr_t addr, |
255 | enum i915_cache_level level, | |
256 | bool valid, u32 flags) | |
93c34e70 | 257 | { |
07749ef3 | 258 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
93c34e70 KG |
259 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
260 | ||
24f3a8cf AG |
261 | if (!(flags & PTE_READ_ONLY)) |
262 | pte |= BYT_PTE_WRITEABLE; | |
93c34e70 KG |
263 | |
264 | if (level != I915_CACHE_NONE) | |
265 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
266 | ||
267 | return pte; | |
268 | } | |
269 | ||
07749ef3 MT |
270 | static gen6_pte_t hsw_pte_encode(dma_addr_t addr, |
271 | enum i915_cache_level level, | |
272 | bool valid, u32 unused) | |
9119708c | 273 | { |
07749ef3 | 274 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
0d8ff15e | 275 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
276 | |
277 | if (level != I915_CACHE_NONE) | |
87a6b688 | 278 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
279 | |
280 | return pte; | |
281 | } | |
282 | ||
07749ef3 MT |
283 | static gen6_pte_t iris_pte_encode(dma_addr_t addr, |
284 | enum i915_cache_level level, | |
285 | bool valid, u32 unused) | |
4d15c145 | 286 | { |
07749ef3 | 287 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4d15c145 BW |
288 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
289 | ||
651d794f CW |
290 | switch (level) { |
291 | case I915_CACHE_NONE: | |
292 | break; | |
293 | case I915_CACHE_WT: | |
c51e9701 | 294 | pte |= HSW_WT_ELLC_LLC_AGE3; |
651d794f CW |
295 | break; |
296 | default: | |
c51e9701 | 297 | pte |= HSW_WB_ELLC_LLC_AGE3; |
651d794f CW |
298 | break; |
299 | } | |
4d15c145 BW |
300 | |
301 | return pte; | |
302 | } | |
303 | ||
44159ddb | 304 | static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p) |
678d96fb BW |
305 | { |
306 | struct device *device = &dev->pdev->dev; | |
307 | ||
44159ddb MK |
308 | p->page = alloc_page(GFP_KERNEL); |
309 | if (!p->page) | |
310 | return -ENOMEM; | |
678d96fb | 311 | |
44159ddb MK |
312 | p->daddr = dma_map_page(device, |
313 | p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL); | |
678d96fb | 314 | |
44159ddb MK |
315 | if (dma_mapping_error(device, p->daddr)) { |
316 | __free_page(p->page); | |
317 | return -EINVAL; | |
318 | } | |
1266cdb1 MT |
319 | |
320 | return 0; | |
678d96fb BW |
321 | } |
322 | ||
44159ddb | 323 | static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p) |
06fda602 | 324 | { |
44159ddb | 325 | if (WARN_ON(!p->page)) |
06fda602 | 326 | return; |
678d96fb | 327 | |
44159ddb MK |
328 | dma_unmap_page(&dev->pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL); |
329 | __free_page(p->page); | |
330 | memset(p, 0, sizeof(*p)); | |
331 | } | |
332 | ||
333 | static void unmap_and_free_pt(struct i915_page_table *pt, | |
334 | struct drm_device *dev) | |
335 | { | |
336 | cleanup_page_dma(dev, &pt->base); | |
678d96fb | 337 | kfree(pt->used_ptes); |
06fda602 BW |
338 | kfree(pt); |
339 | } | |
340 | ||
5a8e9943 | 341 | static void gen8_initialize_pt(struct i915_address_space *vm, |
e5815a2e | 342 | struct i915_page_table *pt) |
5a8e9943 MT |
343 | { |
344 | gen8_pte_t *pt_vaddr, scratch_pte; | |
345 | int i; | |
346 | ||
44159ddb | 347 | pt_vaddr = kmap_atomic(pt->base.page); |
5a8e9943 MT |
348 | scratch_pte = gen8_pte_encode(vm->scratch.addr, |
349 | I915_CACHE_LLC, true); | |
350 | ||
351 | for (i = 0; i < GEN8_PTES; i++) | |
352 | pt_vaddr[i] = scratch_pte; | |
353 | ||
354 | if (!HAS_LLC(vm->dev)) | |
355 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
356 | kunmap_atomic(pt_vaddr); | |
357 | } | |
358 | ||
8a1ebd74 | 359 | static struct i915_page_table *alloc_pt(struct drm_device *dev) |
06fda602 | 360 | { |
ec565b3c | 361 | struct i915_page_table *pt; |
678d96fb BW |
362 | const size_t count = INTEL_INFO(dev)->gen >= 8 ? |
363 | GEN8_PTES : GEN6_PTES; | |
364 | int ret = -ENOMEM; | |
06fda602 BW |
365 | |
366 | pt = kzalloc(sizeof(*pt), GFP_KERNEL); | |
367 | if (!pt) | |
368 | return ERR_PTR(-ENOMEM); | |
369 | ||
678d96fb BW |
370 | pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes), |
371 | GFP_KERNEL); | |
372 | ||
373 | if (!pt->used_ptes) | |
374 | goto fail_bitmap; | |
375 | ||
44159ddb | 376 | ret = setup_page_dma(dev, &pt->base); |
678d96fb | 377 | if (ret) |
44159ddb | 378 | goto fail_page_m; |
06fda602 BW |
379 | |
380 | return pt; | |
678d96fb | 381 | |
44159ddb | 382 | fail_page_m: |
678d96fb BW |
383 | kfree(pt->used_ptes); |
384 | fail_bitmap: | |
385 | kfree(pt); | |
386 | ||
387 | return ERR_PTR(ret); | |
06fda602 BW |
388 | } |
389 | ||
e5815a2e MT |
390 | static void unmap_and_free_pd(struct i915_page_directory *pd, |
391 | struct drm_device *dev) | |
06fda602 | 392 | { |
44159ddb MK |
393 | if (pd->base.page) { |
394 | cleanup_page_dma(dev, &pd->base); | |
33c8819f | 395 | kfree(pd->used_pdes); |
06fda602 BW |
396 | kfree(pd); |
397 | } | |
398 | } | |
399 | ||
8a1ebd74 | 400 | static struct i915_page_directory *alloc_pd(struct drm_device *dev) |
06fda602 | 401 | { |
ec565b3c | 402 | struct i915_page_directory *pd; |
33c8819f | 403 | int ret = -ENOMEM; |
06fda602 BW |
404 | |
405 | pd = kzalloc(sizeof(*pd), GFP_KERNEL); | |
406 | if (!pd) | |
407 | return ERR_PTR(-ENOMEM); | |
408 | ||
33c8819f MT |
409 | pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES), |
410 | sizeof(*pd->used_pdes), GFP_KERNEL); | |
411 | if (!pd->used_pdes) | |
412 | goto free_pd; | |
413 | ||
44159ddb | 414 | ret = setup_page_dma(dev, &pd->base); |
33c8819f | 415 | if (ret) |
44159ddb | 416 | goto free_bitmap; |
e5815a2e | 417 | |
06fda602 | 418 | return pd; |
33c8819f | 419 | |
33c8819f MT |
420 | free_bitmap: |
421 | kfree(pd->used_pdes); | |
422 | free_pd: | |
423 | kfree(pd); | |
424 | ||
425 | return ERR_PTR(ret); | |
06fda602 BW |
426 | } |
427 | ||
94e409c1 | 428 | /* Broadwell Page Directory Pointer Descriptors */ |
e85b26dc | 429 | static int gen8_write_pdp(struct drm_i915_gem_request *req, |
7cb6d7ac MT |
430 | unsigned entry, |
431 | dma_addr_t addr) | |
94e409c1 | 432 | { |
e85b26dc | 433 | struct intel_engine_cs *ring = req->ring; |
94e409c1 BW |
434 | int ret; |
435 | ||
436 | BUG_ON(entry >= 4); | |
437 | ||
5fb9de1a | 438 | ret = intel_ring_begin(req, 6); |
94e409c1 BW |
439 | if (ret) |
440 | return ret; | |
441 | ||
442 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
443 | intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry)); | |
7cb6d7ac | 444 | intel_ring_emit(ring, upper_32_bits(addr)); |
94e409c1 BW |
445 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
446 | intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry)); | |
7cb6d7ac | 447 | intel_ring_emit(ring, lower_32_bits(addr)); |
94e409c1 BW |
448 | intel_ring_advance(ring); |
449 | ||
450 | return 0; | |
451 | } | |
452 | ||
eeb9488e | 453 | static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 454 | struct drm_i915_gem_request *req) |
94e409c1 | 455 | { |
eeb9488e | 456 | int i, ret; |
94e409c1 | 457 | |
7cb6d7ac | 458 | for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) { |
d852c7bf MK |
459 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); |
460 | ||
e85b26dc | 461 | ret = gen8_write_pdp(req, i, pd_daddr); |
eeb9488e BW |
462 | if (ret) |
463 | return ret; | |
94e409c1 | 464 | } |
d595bd4b | 465 | |
eeb9488e | 466 | return 0; |
94e409c1 BW |
467 | } |
468 | ||
459108b8 | 469 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
470 | uint64_t start, |
471 | uint64_t length, | |
459108b8 BW |
472 | bool use_scratch) |
473 | { | |
474 | struct i915_hw_ppgtt *ppgtt = | |
475 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 476 | gen8_pte_t *pt_vaddr, scratch_pte; |
7ad47cf2 BW |
477 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
478 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
479 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
782f1495 | 480 | unsigned num_entries = length >> PAGE_SHIFT; |
459108b8 BW |
481 | unsigned last_pte, i; |
482 | ||
483 | scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr, | |
484 | I915_CACHE_LLC, use_scratch); | |
485 | ||
486 | while (num_entries) { | |
ec565b3c MT |
487 | struct i915_page_directory *pd; |
488 | struct i915_page_table *pt; | |
06fda602 BW |
489 | struct page *page_table; |
490 | ||
491 | if (WARN_ON(!ppgtt->pdp.page_directory[pdpe])) | |
492 | continue; | |
493 | ||
494 | pd = ppgtt->pdp.page_directory[pdpe]; | |
495 | ||
496 | if (WARN_ON(!pd->page_table[pde])) | |
497 | continue; | |
498 | ||
499 | pt = pd->page_table[pde]; | |
500 | ||
44159ddb | 501 | if (WARN_ON(!pt->base.page)) |
06fda602 BW |
502 | continue; |
503 | ||
44159ddb | 504 | page_table = pt->base.page; |
459108b8 | 505 | |
7ad47cf2 | 506 | last_pte = pte + num_entries; |
07749ef3 MT |
507 | if (last_pte > GEN8_PTES) |
508 | last_pte = GEN8_PTES; | |
459108b8 BW |
509 | |
510 | pt_vaddr = kmap_atomic(page_table); | |
511 | ||
7ad47cf2 | 512 | for (i = pte; i < last_pte; i++) { |
459108b8 | 513 | pt_vaddr[i] = scratch_pte; |
7ad47cf2 BW |
514 | num_entries--; |
515 | } | |
459108b8 | 516 | |
fd1ab8f4 RB |
517 | if (!HAS_LLC(ppgtt->base.dev)) |
518 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
459108b8 BW |
519 | kunmap_atomic(pt_vaddr); |
520 | ||
7ad47cf2 | 521 | pte = 0; |
07749ef3 | 522 | if (++pde == I915_PDES) { |
7ad47cf2 BW |
523 | pdpe++; |
524 | pde = 0; | |
525 | } | |
459108b8 BW |
526 | } |
527 | } | |
528 | ||
9df15b49 BW |
529 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
530 | struct sg_table *pages, | |
782f1495 | 531 | uint64_t start, |
24f3a8cf | 532 | enum i915_cache_level cache_level, u32 unused) |
9df15b49 BW |
533 | { |
534 | struct i915_hw_ppgtt *ppgtt = | |
535 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 536 | gen8_pte_t *pt_vaddr; |
7ad47cf2 BW |
537 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
538 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
539 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
9df15b49 BW |
540 | struct sg_page_iter sg_iter; |
541 | ||
6f1cc993 | 542 | pt_vaddr = NULL; |
7ad47cf2 | 543 | |
9df15b49 | 544 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
76643600 | 545 | if (WARN_ON(pdpe >= GEN8_LEGACY_PDPES)) |
7ad47cf2 BW |
546 | break; |
547 | ||
d7b3de91 | 548 | if (pt_vaddr == NULL) { |
ec565b3c MT |
549 | struct i915_page_directory *pd = ppgtt->pdp.page_directory[pdpe]; |
550 | struct i915_page_table *pt = pd->page_table[pde]; | |
44159ddb | 551 | struct page *page_table = pt->base.page; |
d7b3de91 BW |
552 | |
553 | pt_vaddr = kmap_atomic(page_table); | |
554 | } | |
9df15b49 | 555 | |
7ad47cf2 | 556 | pt_vaddr[pte] = |
6f1cc993 CW |
557 | gen8_pte_encode(sg_page_iter_dma_address(&sg_iter), |
558 | cache_level, true); | |
07749ef3 | 559 | if (++pte == GEN8_PTES) { |
fd1ab8f4 RB |
560 | if (!HAS_LLC(ppgtt->base.dev)) |
561 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
9df15b49 | 562 | kunmap_atomic(pt_vaddr); |
6f1cc993 | 563 | pt_vaddr = NULL; |
07749ef3 | 564 | if (++pde == I915_PDES) { |
7ad47cf2 BW |
565 | pdpe++; |
566 | pde = 0; | |
567 | } | |
568 | pte = 0; | |
9df15b49 BW |
569 | } |
570 | } | |
fd1ab8f4 RB |
571 | if (pt_vaddr) { |
572 | if (!HAS_LLC(ppgtt->base.dev)) | |
573 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
6f1cc993 | 574 | kunmap_atomic(pt_vaddr); |
fd1ab8f4 | 575 | } |
9df15b49 BW |
576 | } |
577 | ||
69876bed MT |
578 | static void __gen8_do_map_pt(gen8_pde_t * const pde, |
579 | struct i915_page_table *pt, | |
580 | struct drm_device *dev) | |
581 | { | |
582 | gen8_pde_t entry = | |
44159ddb | 583 | gen8_pde_encode(dev, pt->base.daddr, I915_CACHE_LLC); |
69876bed MT |
584 | *pde = entry; |
585 | } | |
586 | ||
587 | static void gen8_initialize_pd(struct i915_address_space *vm, | |
588 | struct i915_page_directory *pd) | |
589 | { | |
590 | struct i915_hw_ppgtt *ppgtt = | |
591 | container_of(vm, struct i915_hw_ppgtt, base); | |
592 | gen8_pde_t *page_directory; | |
593 | struct i915_page_table *pt; | |
594 | int i; | |
595 | ||
44159ddb | 596 | page_directory = kmap_atomic(pd->base.page); |
69876bed MT |
597 | pt = ppgtt->scratch_pt; |
598 | for (i = 0; i < I915_PDES; i++) | |
599 | /* Map the PDE to the page table */ | |
600 | __gen8_do_map_pt(page_directory + i, pt, vm->dev); | |
601 | ||
602 | if (!HAS_LLC(vm->dev)) | |
603 | drm_clflush_virt_range(page_directory, PAGE_SIZE); | |
e5815a2e MT |
604 | kunmap_atomic(page_directory); |
605 | } | |
606 | ||
ec565b3c | 607 | static void gen8_free_page_tables(struct i915_page_directory *pd, struct drm_device *dev) |
7ad47cf2 BW |
608 | { |
609 | int i; | |
610 | ||
44159ddb | 611 | if (!pd->base.page) |
7ad47cf2 BW |
612 | return; |
613 | ||
33c8819f | 614 | for_each_set_bit(i, pd->used_pdes, I915_PDES) { |
06fda602 BW |
615 | if (WARN_ON(!pd->page_table[i])) |
616 | continue; | |
7ad47cf2 | 617 | |
06dc68d6 | 618 | unmap_and_free_pt(pd->page_table[i], dev); |
06fda602 BW |
619 | pd->page_table[i] = NULL; |
620 | } | |
d7b3de91 BW |
621 | } |
622 | ||
061dd493 | 623 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) |
b45a6715 | 624 | { |
061dd493 DV |
625 | struct i915_hw_ppgtt *ppgtt = |
626 | container_of(vm, struct i915_hw_ppgtt, base); | |
b45a6715 BW |
627 | int i; |
628 | ||
33c8819f | 629 | for_each_set_bit(i, ppgtt->pdp.used_pdpes, GEN8_LEGACY_PDPES) { |
06fda602 BW |
630 | if (WARN_ON(!ppgtt->pdp.page_directory[i])) |
631 | continue; | |
632 | ||
06dc68d6 | 633 | gen8_free_page_tables(ppgtt->pdp.page_directory[i], ppgtt->base.dev); |
e5815a2e | 634 | unmap_and_free_pd(ppgtt->pdp.page_directory[i], ppgtt->base.dev); |
7ad47cf2 | 635 | } |
69876bed | 636 | |
e5815a2e | 637 | unmap_and_free_pd(ppgtt->scratch_pd, ppgtt->base.dev); |
69876bed | 638 | unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev); |
b45a6715 BW |
639 | } |
640 | ||
d7b2633d MT |
641 | /** |
642 | * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range. | |
643 | * @ppgtt: Master ppgtt structure. | |
644 | * @pd: Page directory for this address range. | |
645 | * @start: Starting virtual address to begin allocations. | |
646 | * @length Size of the allocations. | |
647 | * @new_pts: Bitmap set by function with new allocations. Likely used by the | |
648 | * caller to free on error. | |
649 | * | |
650 | * Allocate the required number of page tables. Extremely similar to | |
651 | * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by | |
652 | * the page directory boundary (instead of the page directory pointer). That | |
653 | * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is | |
654 | * possible, and likely that the caller will need to use multiple calls of this | |
655 | * function to achieve the appropriate allocation. | |
656 | * | |
657 | * Return: 0 if success; negative error code otherwise. | |
658 | */ | |
e5815a2e MT |
659 | static int gen8_ppgtt_alloc_pagetabs(struct i915_hw_ppgtt *ppgtt, |
660 | struct i915_page_directory *pd, | |
5441f0cb | 661 | uint64_t start, |
d7b2633d MT |
662 | uint64_t length, |
663 | unsigned long *new_pts) | |
bf2b4ed2 | 664 | { |
e5815a2e | 665 | struct drm_device *dev = ppgtt->base.dev; |
d7b2633d | 666 | struct i915_page_table *pt; |
5441f0cb MT |
667 | uint64_t temp; |
668 | uint32_t pde; | |
bf2b4ed2 | 669 | |
d7b2633d MT |
670 | gen8_for_each_pde(pt, pd, start, length, temp, pde) { |
671 | /* Don't reallocate page tables */ | |
672 | if (pt) { | |
673 | /* Scratch is never allocated this way */ | |
674 | WARN_ON(pt == ppgtt->scratch_pt); | |
675 | continue; | |
676 | } | |
677 | ||
8a1ebd74 | 678 | pt = alloc_pt(dev); |
d7b2633d | 679 | if (IS_ERR(pt)) |
5441f0cb MT |
680 | goto unwind_out; |
681 | ||
d7b2633d MT |
682 | gen8_initialize_pt(&ppgtt->base, pt); |
683 | pd->page_table[pde] = pt; | |
684 | set_bit(pde, new_pts); | |
7ad47cf2 BW |
685 | } |
686 | ||
bf2b4ed2 | 687 | return 0; |
7ad47cf2 BW |
688 | |
689 | unwind_out: | |
d7b2633d | 690 | for_each_set_bit(pde, new_pts, I915_PDES) |
e5815a2e | 691 | unmap_and_free_pt(pd->page_table[pde], dev); |
7ad47cf2 | 692 | |
d7b3de91 | 693 | return -ENOMEM; |
bf2b4ed2 BW |
694 | } |
695 | ||
d7b2633d MT |
696 | /** |
697 | * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range. | |
698 | * @ppgtt: Master ppgtt structure. | |
699 | * @pdp: Page directory pointer for this address range. | |
700 | * @start: Starting virtual address to begin allocations. | |
701 | * @length Size of the allocations. | |
702 | * @new_pds Bitmap set by function with new allocations. Likely used by the | |
703 | * caller to free on error. | |
704 | * | |
705 | * Allocate the required number of page directories starting at the pde index of | |
706 | * @start, and ending at the pde index @start + @length. This function will skip | |
707 | * over already allocated page directories within the range, and only allocate | |
708 | * new ones, setting the appropriate pointer within the pdp as well as the | |
709 | * correct position in the bitmap @new_pds. | |
710 | * | |
711 | * The function will only allocate the pages within the range for a give page | |
712 | * directory pointer. In other words, if @start + @length straddles a virtually | |
713 | * addressed PDP boundary (512GB for 4k pages), there will be more allocations | |
714 | * required by the caller, This is not currently possible, and the BUG in the | |
715 | * code will prevent it. | |
716 | * | |
717 | * Return: 0 if success; negative error code otherwise. | |
718 | */ | |
c488dbba MT |
719 | static int gen8_ppgtt_alloc_page_directories(struct i915_hw_ppgtt *ppgtt, |
720 | struct i915_page_directory_pointer *pdp, | |
69876bed | 721 | uint64_t start, |
d7b2633d MT |
722 | uint64_t length, |
723 | unsigned long *new_pds) | |
bf2b4ed2 | 724 | { |
e5815a2e | 725 | struct drm_device *dev = ppgtt->base.dev; |
d7b2633d | 726 | struct i915_page_directory *pd; |
69876bed MT |
727 | uint64_t temp; |
728 | uint32_t pdpe; | |
729 | ||
d7b2633d MT |
730 | WARN_ON(!bitmap_empty(new_pds, GEN8_LEGACY_PDPES)); |
731 | ||
d7b2633d MT |
732 | gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) { |
733 | if (pd) | |
734 | continue; | |
33c8819f | 735 | |
8a1ebd74 | 736 | pd = alloc_pd(dev); |
d7b2633d | 737 | if (IS_ERR(pd)) |
d7b3de91 | 738 | goto unwind_out; |
69876bed | 739 | |
d7b2633d MT |
740 | gen8_initialize_pd(&ppgtt->base, pd); |
741 | pdp->page_directory[pdpe] = pd; | |
742 | set_bit(pdpe, new_pds); | |
d7b3de91 BW |
743 | } |
744 | ||
bf2b4ed2 | 745 | return 0; |
d7b3de91 BW |
746 | |
747 | unwind_out: | |
d7b2633d | 748 | for_each_set_bit(pdpe, new_pds, GEN8_LEGACY_PDPES) |
e5815a2e | 749 | unmap_and_free_pd(pdp->page_directory[pdpe], dev); |
d7b3de91 BW |
750 | |
751 | return -ENOMEM; | |
bf2b4ed2 BW |
752 | } |
753 | ||
d7b2633d MT |
754 | static void |
755 | free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long **new_pts) | |
756 | { | |
757 | int i; | |
758 | ||
759 | for (i = 0; i < GEN8_LEGACY_PDPES; i++) | |
760 | kfree(new_pts[i]); | |
761 | kfree(new_pts); | |
762 | kfree(new_pds); | |
763 | } | |
764 | ||
765 | /* Fills in the page directory bitmap, and the array of page tables bitmap. Both | |
766 | * of these are based on the number of PDPEs in the system. | |
767 | */ | |
768 | static | |
769 | int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds, | |
770 | unsigned long ***new_pts) | |
771 | { | |
772 | int i; | |
773 | unsigned long *pds; | |
774 | unsigned long **pts; | |
775 | ||
776 | pds = kcalloc(BITS_TO_LONGS(GEN8_LEGACY_PDPES), sizeof(unsigned long), GFP_KERNEL); | |
777 | if (!pds) | |
778 | return -ENOMEM; | |
779 | ||
780 | pts = kcalloc(GEN8_LEGACY_PDPES, sizeof(unsigned long *), GFP_KERNEL); | |
781 | if (!pts) { | |
782 | kfree(pds); | |
783 | return -ENOMEM; | |
784 | } | |
785 | ||
786 | for (i = 0; i < GEN8_LEGACY_PDPES; i++) { | |
787 | pts[i] = kcalloc(BITS_TO_LONGS(I915_PDES), | |
788 | sizeof(unsigned long), GFP_KERNEL); | |
789 | if (!pts[i]) | |
790 | goto err_out; | |
791 | } | |
792 | ||
793 | *new_pds = pds; | |
794 | *new_pts = pts; | |
795 | ||
796 | return 0; | |
797 | ||
798 | err_out: | |
799 | free_gen8_temp_bitmaps(pds, pts); | |
800 | return -ENOMEM; | |
801 | } | |
802 | ||
5b7e4c9c MK |
803 | /* PDE TLBs are a pain to invalidate on GEN8+. When we modify |
804 | * the page table structures, we mark them dirty so that | |
805 | * context switching/execlist queuing code takes extra steps | |
806 | * to ensure that tlbs are flushed. | |
807 | */ | |
808 | static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt) | |
809 | { | |
810 | ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask; | |
811 | } | |
812 | ||
e5815a2e MT |
813 | static int gen8_alloc_va_range(struct i915_address_space *vm, |
814 | uint64_t start, | |
815 | uint64_t length) | |
bf2b4ed2 | 816 | { |
e5815a2e MT |
817 | struct i915_hw_ppgtt *ppgtt = |
818 | container_of(vm, struct i915_hw_ppgtt, base); | |
d7b2633d | 819 | unsigned long *new_page_dirs, **new_page_tables; |
5441f0cb | 820 | struct i915_page_directory *pd; |
33c8819f MT |
821 | const uint64_t orig_start = start; |
822 | const uint64_t orig_length = length; | |
5441f0cb MT |
823 | uint64_t temp; |
824 | uint32_t pdpe; | |
bf2b4ed2 BW |
825 | int ret; |
826 | ||
d7b2633d MT |
827 | /* Wrap is never okay since we can only represent 48b, and we don't |
828 | * actually use the other side of the canonical address space. | |
829 | */ | |
830 | if (WARN_ON(start + length < start)) | |
a05d80ee MK |
831 | return -ENODEV; |
832 | ||
833 | if (WARN_ON(start + length > ppgtt->base.total)) | |
834 | return -ENODEV; | |
d7b2633d MT |
835 | |
836 | ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables); | |
bf2b4ed2 BW |
837 | if (ret) |
838 | return ret; | |
839 | ||
d7b2633d MT |
840 | /* Do the allocations first so we can easily bail out */ |
841 | ret = gen8_ppgtt_alloc_page_directories(ppgtt, &ppgtt->pdp, start, length, | |
842 | new_page_dirs); | |
843 | if (ret) { | |
844 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); | |
845 | return ret; | |
846 | } | |
847 | ||
848 | /* For every page directory referenced, allocate page tables */ | |
5441f0cb | 849 | gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) { |
d7b2633d MT |
850 | ret = gen8_ppgtt_alloc_pagetabs(ppgtt, pd, start, length, |
851 | new_page_tables[pdpe]); | |
5441f0cb MT |
852 | if (ret) |
853 | goto err_out; | |
5441f0cb MT |
854 | } |
855 | ||
33c8819f MT |
856 | start = orig_start; |
857 | length = orig_length; | |
858 | ||
d7b2633d MT |
859 | /* Allocations have completed successfully, so set the bitmaps, and do |
860 | * the mappings. */ | |
33c8819f | 861 | gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) { |
44159ddb | 862 | gen8_pde_t *const page_directory = kmap_atomic(pd->base.page); |
33c8819f MT |
863 | struct i915_page_table *pt; |
864 | uint64_t pd_len = gen8_clamp_pd(start, length); | |
865 | uint64_t pd_start = start; | |
866 | uint32_t pde; | |
867 | ||
d7b2633d MT |
868 | /* Every pd should be allocated, we just did that above. */ |
869 | WARN_ON(!pd); | |
870 | ||
871 | gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) { | |
872 | /* Same reasoning as pd */ | |
873 | WARN_ON(!pt); | |
874 | WARN_ON(!pd_len); | |
875 | WARN_ON(!gen8_pte_count(pd_start, pd_len)); | |
876 | ||
877 | /* Set our used ptes within the page table */ | |
878 | bitmap_set(pt->used_ptes, | |
879 | gen8_pte_index(pd_start), | |
880 | gen8_pte_count(pd_start, pd_len)); | |
881 | ||
882 | /* Our pde is now pointing to the pagetable, pt */ | |
33c8819f | 883 | set_bit(pde, pd->used_pdes); |
d7b2633d MT |
884 | |
885 | /* Map the PDE to the page table */ | |
886 | __gen8_do_map_pt(page_directory + pde, pt, vm->dev); | |
887 | ||
888 | /* NB: We haven't yet mapped ptes to pages. At this | |
889 | * point we're still relying on insert_entries() */ | |
33c8819f | 890 | } |
d7b2633d MT |
891 | |
892 | if (!HAS_LLC(vm->dev)) | |
893 | drm_clflush_virt_range(page_directory, PAGE_SIZE); | |
894 | ||
895 | kunmap_atomic(page_directory); | |
896 | ||
33c8819f MT |
897 | set_bit(pdpe, ppgtt->pdp.used_pdpes); |
898 | } | |
899 | ||
d7b2633d | 900 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
5b7e4c9c | 901 | mark_tlbs_dirty(ppgtt); |
d7b3de91 | 902 | return 0; |
bf2b4ed2 | 903 | |
d7b3de91 | 904 | err_out: |
d7b2633d MT |
905 | while (pdpe--) { |
906 | for_each_set_bit(temp, new_page_tables[pdpe], I915_PDES) | |
907 | unmap_and_free_pt(ppgtt->pdp.page_directory[pdpe]->page_table[temp], vm->dev); | |
908 | } | |
909 | ||
910 | for_each_set_bit(pdpe, new_page_dirs, GEN8_LEGACY_PDPES) | |
911 | unmap_and_free_pd(ppgtt->pdp.page_directory[pdpe], vm->dev); | |
912 | ||
913 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); | |
5b7e4c9c | 914 | mark_tlbs_dirty(ppgtt); |
bf2b4ed2 BW |
915 | return ret; |
916 | } | |
917 | ||
eb0b44ad | 918 | /* |
f3a964b9 BW |
919 | * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers |
920 | * with a net effect resembling a 2-level page table in normal x86 terms. Each | |
921 | * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address | |
922 | * space. | |
37aca44a | 923 | * |
f3a964b9 | 924 | */ |
5c5f6457 | 925 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
37aca44a | 926 | { |
8a1ebd74 | 927 | ppgtt->scratch_pt = alloc_pt(ppgtt->base.dev); |
69876bed MT |
928 | if (IS_ERR(ppgtt->scratch_pt)) |
929 | return PTR_ERR(ppgtt->scratch_pt); | |
930 | ||
8a1ebd74 | 931 | ppgtt->scratch_pd = alloc_pd(ppgtt->base.dev); |
7cb6d7ac MT |
932 | if (IS_ERR(ppgtt->scratch_pd)) |
933 | return PTR_ERR(ppgtt->scratch_pd); | |
934 | ||
69876bed | 935 | gen8_initialize_pt(&ppgtt->base, ppgtt->scratch_pt); |
7cb6d7ac | 936 | gen8_initialize_pd(&ppgtt->base, ppgtt->scratch_pd); |
69876bed | 937 | |
d7b2633d | 938 | ppgtt->base.start = 0; |
5c5f6457 | 939 | ppgtt->base.total = 1ULL << 32; |
501fd70f MT |
940 | if (IS_ENABLED(CONFIG_X86_32)) |
941 | /* While we have a proliferation of size_t variables | |
942 | * we cannot represent the full ppgtt size on 32bit, | |
943 | * so limit it to the same size as the GGTT (currently | |
944 | * 2GiB). | |
945 | */ | |
946 | ppgtt->base.total = to_i915(ppgtt->base.dev)->gtt.base.total; | |
d7b2633d | 947 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; |
5c5f6457 | 948 | ppgtt->base.allocate_va_range = gen8_alloc_va_range; |
d7b2633d | 949 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; |
c7e16f22 | 950 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; |
777dc5bb DV |
951 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; |
952 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
d7b2633d MT |
953 | |
954 | ppgtt->switch_mm = gen8_mm_switch; | |
955 | ||
956 | return 0; | |
957 | } | |
958 | ||
87d60b63 BW |
959 | static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) |
960 | { | |
87d60b63 | 961 | struct i915_address_space *vm = &ppgtt->base; |
09942c65 | 962 | struct i915_page_table *unused; |
07749ef3 | 963 | gen6_pte_t scratch_pte; |
87d60b63 | 964 | uint32_t pd_entry; |
09942c65 MT |
965 | uint32_t pte, pde, temp; |
966 | uint32_t start = ppgtt->base.start, length = ppgtt->base.total; | |
87d60b63 | 967 | |
24f3a8cf | 968 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0); |
87d60b63 | 969 | |
09942c65 | 970 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) { |
87d60b63 | 971 | u32 expected; |
07749ef3 | 972 | gen6_pte_t *pt_vaddr; |
44159ddb | 973 | dma_addr_t pt_addr = ppgtt->pd.page_table[pde]->base.daddr; |
09942c65 | 974 | pd_entry = readl(ppgtt->pd_addr + pde); |
87d60b63 BW |
975 | expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); |
976 | ||
977 | if (pd_entry != expected) | |
978 | seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", | |
979 | pde, | |
980 | pd_entry, | |
981 | expected); | |
982 | seq_printf(m, "\tPDE: %x\n", pd_entry); | |
983 | ||
44159ddb | 984 | pt_vaddr = kmap_atomic(ppgtt->pd.page_table[pde]->base.page); |
07749ef3 | 985 | for (pte = 0; pte < GEN6_PTES; pte+=4) { |
87d60b63 | 986 | unsigned long va = |
07749ef3 | 987 | (pde * PAGE_SIZE * GEN6_PTES) + |
87d60b63 BW |
988 | (pte * PAGE_SIZE); |
989 | int i; | |
990 | bool found = false; | |
991 | for (i = 0; i < 4; i++) | |
992 | if (pt_vaddr[pte + i] != scratch_pte) | |
993 | found = true; | |
994 | if (!found) | |
995 | continue; | |
996 | ||
997 | seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); | |
998 | for (i = 0; i < 4; i++) { | |
999 | if (pt_vaddr[pte + i] != scratch_pte) | |
1000 | seq_printf(m, " %08x", pt_vaddr[pte + i]); | |
1001 | else | |
1002 | seq_puts(m, " SCRATCH "); | |
1003 | } | |
1004 | seq_puts(m, "\n"); | |
1005 | } | |
1006 | kunmap_atomic(pt_vaddr); | |
1007 | } | |
1008 | } | |
1009 | ||
678d96fb | 1010 | /* Write pde (index) from the page directory @pd to the page table @pt */ |
ec565b3c MT |
1011 | static void gen6_write_pde(struct i915_page_directory *pd, |
1012 | const int pde, struct i915_page_table *pt) | |
6197349b | 1013 | { |
678d96fb BW |
1014 | /* Caller needs to make sure the write completes if necessary */ |
1015 | struct i915_hw_ppgtt *ppgtt = | |
1016 | container_of(pd, struct i915_hw_ppgtt, pd); | |
1017 | u32 pd_entry; | |
6197349b | 1018 | |
44159ddb | 1019 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt->base.daddr); |
678d96fb | 1020 | pd_entry |= GEN6_PDE_VALID; |
6197349b | 1021 | |
678d96fb BW |
1022 | writel(pd_entry, ppgtt->pd_addr + pde); |
1023 | } | |
6197349b | 1024 | |
678d96fb BW |
1025 | /* Write all the page tables found in the ppgtt structure to incrementing page |
1026 | * directories. */ | |
1027 | static void gen6_write_page_range(struct drm_i915_private *dev_priv, | |
ec565b3c | 1028 | struct i915_page_directory *pd, |
678d96fb BW |
1029 | uint32_t start, uint32_t length) |
1030 | { | |
ec565b3c | 1031 | struct i915_page_table *pt; |
678d96fb BW |
1032 | uint32_t pde, temp; |
1033 | ||
1034 | gen6_for_each_pde(pt, pd, start, length, temp, pde) | |
1035 | gen6_write_pde(pd, pde, pt); | |
1036 | ||
1037 | /* Make sure write is complete before other code can use this page | |
1038 | * table. Also require for WC mapped PTEs */ | |
1039 | readl(dev_priv->gtt.gsm); | |
3e302542 BW |
1040 | } |
1041 | ||
b4a74e3a | 1042 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 1043 | { |
44159ddb | 1044 | BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f); |
b4a74e3a | 1045 | |
44159ddb | 1046 | return (ppgtt->pd.base.ggtt_offset / 64) << 16; |
b4a74e3a BW |
1047 | } |
1048 | ||
90252e5c | 1049 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1050 | struct drm_i915_gem_request *req) |
90252e5c | 1051 | { |
e85b26dc | 1052 | struct intel_engine_cs *ring = req->ring; |
90252e5c BW |
1053 | int ret; |
1054 | ||
90252e5c | 1055 | /* NB: TLBs must be flushed and invalidated before a switch */ |
a84c3ae1 | 1056 | ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
90252e5c BW |
1057 | if (ret) |
1058 | return ret; | |
1059 | ||
5fb9de1a | 1060 | ret = intel_ring_begin(req, 6); |
90252e5c BW |
1061 | if (ret) |
1062 | return ret; | |
1063 | ||
1064 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
1065 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
1066 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
1067 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
1068 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
1069 | intel_ring_emit(ring, MI_NOOP); | |
1070 | intel_ring_advance(ring); | |
1071 | ||
1072 | return 0; | |
1073 | } | |
1074 | ||
71ba2d64 | 1075 | static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1076 | struct drm_i915_gem_request *req) |
71ba2d64 | 1077 | { |
e85b26dc | 1078 | struct intel_engine_cs *ring = req->ring; |
71ba2d64 YZ |
1079 | struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev); |
1080 | ||
1081 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
1082 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
1083 | return 0; | |
1084 | } | |
1085 | ||
48a10389 | 1086 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1087 | struct drm_i915_gem_request *req) |
48a10389 | 1088 | { |
e85b26dc | 1089 | struct intel_engine_cs *ring = req->ring; |
48a10389 BW |
1090 | int ret; |
1091 | ||
48a10389 | 1092 | /* NB: TLBs must be flushed and invalidated before a switch */ |
a84c3ae1 | 1093 | ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
48a10389 BW |
1094 | if (ret) |
1095 | return ret; | |
1096 | ||
5fb9de1a | 1097 | ret = intel_ring_begin(req, 6); |
48a10389 BW |
1098 | if (ret) |
1099 | return ret; | |
1100 | ||
1101 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
1102 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
1103 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
1104 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
1105 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
1106 | intel_ring_emit(ring, MI_NOOP); | |
1107 | intel_ring_advance(ring); | |
1108 | ||
90252e5c BW |
1109 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
1110 | if (ring->id != RCS) { | |
a84c3ae1 | 1111 | ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
90252e5c BW |
1112 | if (ret) |
1113 | return ret; | |
1114 | } | |
1115 | ||
48a10389 BW |
1116 | return 0; |
1117 | } | |
1118 | ||
eeb9488e | 1119 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1120 | struct drm_i915_gem_request *req) |
eeb9488e | 1121 | { |
e85b26dc | 1122 | struct intel_engine_cs *ring = req->ring; |
eeb9488e BW |
1123 | struct drm_device *dev = ppgtt->base.dev; |
1124 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1125 | ||
48a10389 | 1126 | |
eeb9488e BW |
1127 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
1128 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
1129 | ||
1130 | POSTING_READ(RING_PP_DIR_DCLV(ring)); | |
1131 | ||
1132 | return 0; | |
1133 | } | |
1134 | ||
82460d97 | 1135 | static void gen8_ppgtt_enable(struct drm_device *dev) |
eeb9488e | 1136 | { |
eeb9488e | 1137 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 1138 | struct intel_engine_cs *ring; |
82460d97 | 1139 | int j; |
3e302542 | 1140 | |
eeb9488e BW |
1141 | for_each_ring(ring, dev_priv, j) { |
1142 | I915_WRITE(RING_MODE_GEN7(ring), | |
1143 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
eeb9488e | 1144 | } |
eeb9488e | 1145 | } |
6197349b | 1146 | |
82460d97 | 1147 | static void gen7_ppgtt_enable(struct drm_device *dev) |
3e302542 | 1148 | { |
50227e1c | 1149 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 1150 | struct intel_engine_cs *ring; |
b4a74e3a | 1151 | uint32_t ecochk, ecobits; |
3e302542 | 1152 | int i; |
6197349b | 1153 | |
b4a74e3a BW |
1154 | ecobits = I915_READ(GAC_ECO_BITS); |
1155 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
a65c2fcd | 1156 | |
b4a74e3a BW |
1157 | ecochk = I915_READ(GAM_ECOCHK); |
1158 | if (IS_HASWELL(dev)) { | |
1159 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
1160 | } else { | |
1161 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
1162 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
1163 | } | |
1164 | I915_WRITE(GAM_ECOCHK, ecochk); | |
a65c2fcd | 1165 | |
b4a74e3a | 1166 | for_each_ring(ring, dev_priv, i) { |
6197349b | 1167 | /* GFX_MODE is per-ring on gen7+ */ |
b4a74e3a BW |
1168 | I915_WRITE(RING_MODE_GEN7(ring), |
1169 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b | 1170 | } |
b4a74e3a | 1171 | } |
6197349b | 1172 | |
82460d97 | 1173 | static void gen6_ppgtt_enable(struct drm_device *dev) |
b4a74e3a | 1174 | { |
50227e1c | 1175 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4a74e3a | 1176 | uint32_t ecochk, gab_ctl, ecobits; |
a65c2fcd | 1177 | |
b4a74e3a BW |
1178 | ecobits = I915_READ(GAC_ECO_BITS); |
1179 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | | |
1180 | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 1181 | |
b4a74e3a BW |
1182 | gab_ctl = I915_READ(GAB_CTL); |
1183 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
1184 | ||
1185 | ecochk = I915_READ(GAM_ECOCHK); | |
1186 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); | |
1187 | ||
1188 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b BW |
1189 | } |
1190 | ||
1d2a314c | 1191 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 1192 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1193 | uint64_t start, |
1194 | uint64_t length, | |
828c7908 | 1195 | bool use_scratch) |
1d2a314c | 1196 | { |
853ba5d2 BW |
1197 | struct i915_hw_ppgtt *ppgtt = |
1198 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 1199 | gen6_pte_t *pt_vaddr, scratch_pte; |
782f1495 BW |
1200 | unsigned first_entry = start >> PAGE_SHIFT; |
1201 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1202 | unsigned act_pt = first_entry / GEN6_PTES; |
1203 | unsigned first_pte = first_entry % GEN6_PTES; | |
7bddb01f | 1204 | unsigned last_pte, i; |
1d2a314c | 1205 | |
24f3a8cf | 1206 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0); |
1d2a314c | 1207 | |
7bddb01f DV |
1208 | while (num_entries) { |
1209 | last_pte = first_pte + num_entries; | |
07749ef3 MT |
1210 | if (last_pte > GEN6_PTES) |
1211 | last_pte = GEN6_PTES; | |
7bddb01f | 1212 | |
44159ddb | 1213 | pt_vaddr = kmap_atomic(ppgtt->pd.page_table[act_pt]->base.page); |
1d2a314c | 1214 | |
7bddb01f DV |
1215 | for (i = first_pte; i < last_pte; i++) |
1216 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
1217 | |
1218 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 1219 | |
7bddb01f DV |
1220 | num_entries -= last_pte - first_pte; |
1221 | first_pte = 0; | |
a15326a5 | 1222 | act_pt++; |
7bddb01f | 1223 | } |
1d2a314c DV |
1224 | } |
1225 | ||
853ba5d2 | 1226 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 | 1227 | struct sg_table *pages, |
782f1495 | 1228 | uint64_t start, |
24f3a8cf | 1229 | enum i915_cache_level cache_level, u32 flags) |
def886c3 | 1230 | { |
853ba5d2 BW |
1231 | struct i915_hw_ppgtt *ppgtt = |
1232 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 1233 | gen6_pte_t *pt_vaddr; |
782f1495 | 1234 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1235 | unsigned act_pt = first_entry / GEN6_PTES; |
1236 | unsigned act_pte = first_entry % GEN6_PTES; | |
6e995e23 ID |
1237 | struct sg_page_iter sg_iter; |
1238 | ||
cc79714f | 1239 | pt_vaddr = NULL; |
6e995e23 | 1240 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
cc79714f | 1241 | if (pt_vaddr == NULL) |
44159ddb | 1242 | pt_vaddr = kmap_atomic(ppgtt->pd.page_table[act_pt]->base.page); |
6e995e23 | 1243 | |
cc79714f CW |
1244 | pt_vaddr[act_pte] = |
1245 | vm->pte_encode(sg_page_iter_dma_address(&sg_iter), | |
24f3a8cf AG |
1246 | cache_level, true, flags); |
1247 | ||
07749ef3 | 1248 | if (++act_pte == GEN6_PTES) { |
6e995e23 | 1249 | kunmap_atomic(pt_vaddr); |
cc79714f | 1250 | pt_vaddr = NULL; |
a15326a5 | 1251 | act_pt++; |
6e995e23 | 1252 | act_pte = 0; |
def886c3 | 1253 | } |
def886c3 | 1254 | } |
cc79714f CW |
1255 | if (pt_vaddr) |
1256 | kunmap_atomic(pt_vaddr); | |
def886c3 DV |
1257 | } |
1258 | ||
4933d519 | 1259 | static void gen6_initialize_pt(struct i915_address_space *vm, |
ec565b3c | 1260 | struct i915_page_table *pt) |
4933d519 MT |
1261 | { |
1262 | gen6_pte_t *pt_vaddr, scratch_pte; | |
1263 | int i; | |
1264 | ||
1265 | WARN_ON(vm->scratch.addr == 0); | |
1266 | ||
1267 | scratch_pte = vm->pte_encode(vm->scratch.addr, | |
1268 | I915_CACHE_LLC, true, 0); | |
1269 | ||
44159ddb | 1270 | pt_vaddr = kmap_atomic(pt->base.page); |
4933d519 MT |
1271 | |
1272 | for (i = 0; i < GEN6_PTES; i++) | |
1273 | pt_vaddr[i] = scratch_pte; | |
1274 | ||
1275 | kunmap_atomic(pt_vaddr); | |
1276 | } | |
1277 | ||
678d96fb | 1278 | static int gen6_alloc_va_range(struct i915_address_space *vm, |
a05d80ee | 1279 | uint64_t start_in, uint64_t length_in) |
678d96fb | 1280 | { |
4933d519 MT |
1281 | DECLARE_BITMAP(new_page_tables, I915_PDES); |
1282 | struct drm_device *dev = vm->dev; | |
1283 | struct drm_i915_private *dev_priv = dev->dev_private; | |
678d96fb BW |
1284 | struct i915_hw_ppgtt *ppgtt = |
1285 | container_of(vm, struct i915_hw_ppgtt, base); | |
ec565b3c | 1286 | struct i915_page_table *pt; |
a05d80ee | 1287 | uint32_t start, length, start_save, length_save; |
678d96fb | 1288 | uint32_t pde, temp; |
4933d519 MT |
1289 | int ret; |
1290 | ||
a05d80ee MK |
1291 | if (WARN_ON(start_in + length_in > ppgtt->base.total)) |
1292 | return -ENODEV; | |
1293 | ||
1294 | start = start_save = start_in; | |
1295 | length = length_save = length_in; | |
4933d519 MT |
1296 | |
1297 | bitmap_zero(new_page_tables, I915_PDES); | |
1298 | ||
1299 | /* The allocation is done in two stages so that we can bail out with | |
1300 | * minimal amount of pain. The first stage finds new page tables that | |
1301 | * need allocation. The second stage marks use ptes within the page | |
1302 | * tables. | |
1303 | */ | |
1304 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) { | |
1305 | if (pt != ppgtt->scratch_pt) { | |
1306 | WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES)); | |
1307 | continue; | |
1308 | } | |
1309 | ||
1310 | /* We've already allocated a page table */ | |
1311 | WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES)); | |
1312 | ||
8a1ebd74 | 1313 | pt = alloc_pt(dev); |
4933d519 MT |
1314 | if (IS_ERR(pt)) { |
1315 | ret = PTR_ERR(pt); | |
1316 | goto unwind_out; | |
1317 | } | |
1318 | ||
1319 | gen6_initialize_pt(vm, pt); | |
1320 | ||
1321 | ppgtt->pd.page_table[pde] = pt; | |
1322 | set_bit(pde, new_page_tables); | |
72744cb1 | 1323 | trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT); |
4933d519 MT |
1324 | } |
1325 | ||
1326 | start = start_save; | |
1327 | length = length_save; | |
678d96fb BW |
1328 | |
1329 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) { | |
1330 | DECLARE_BITMAP(tmp_bitmap, GEN6_PTES); | |
1331 | ||
1332 | bitmap_zero(tmp_bitmap, GEN6_PTES); | |
1333 | bitmap_set(tmp_bitmap, gen6_pte_index(start), | |
1334 | gen6_pte_count(start, length)); | |
1335 | ||
4933d519 MT |
1336 | if (test_and_clear_bit(pde, new_page_tables)) |
1337 | gen6_write_pde(&ppgtt->pd, pde, pt); | |
1338 | ||
72744cb1 MT |
1339 | trace_i915_page_table_entry_map(vm, pde, pt, |
1340 | gen6_pte_index(start), | |
1341 | gen6_pte_count(start, length), | |
1342 | GEN6_PTES); | |
4933d519 | 1343 | bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes, |
678d96fb BW |
1344 | GEN6_PTES); |
1345 | } | |
1346 | ||
4933d519 MT |
1347 | WARN_ON(!bitmap_empty(new_page_tables, I915_PDES)); |
1348 | ||
1349 | /* Make sure write is complete before other code can use this page | |
1350 | * table. Also require for WC mapped PTEs */ | |
1351 | readl(dev_priv->gtt.gsm); | |
1352 | ||
563222a7 | 1353 | mark_tlbs_dirty(ppgtt); |
678d96fb | 1354 | return 0; |
4933d519 MT |
1355 | |
1356 | unwind_out: | |
1357 | for_each_set_bit(pde, new_page_tables, I915_PDES) { | |
ec565b3c | 1358 | struct i915_page_table *pt = ppgtt->pd.page_table[pde]; |
4933d519 MT |
1359 | |
1360 | ppgtt->pd.page_table[pde] = ppgtt->scratch_pt; | |
1361 | unmap_and_free_pt(pt, vm->dev); | |
1362 | } | |
1363 | ||
1364 | mark_tlbs_dirty(ppgtt); | |
1365 | return ret; | |
678d96fb BW |
1366 | } |
1367 | ||
061dd493 | 1368 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
a00d825d | 1369 | { |
061dd493 DV |
1370 | struct i915_hw_ppgtt *ppgtt = |
1371 | container_of(vm, struct i915_hw_ppgtt, base); | |
09942c65 MT |
1372 | struct i915_page_table *pt; |
1373 | uint32_t pde; | |
4933d519 | 1374 | |
061dd493 DV |
1375 | |
1376 | drm_mm_remove_node(&ppgtt->node); | |
1377 | ||
09942c65 | 1378 | gen6_for_all_pdes(pt, ppgtt, pde) { |
4933d519 | 1379 | if (pt != ppgtt->scratch_pt) |
09942c65 | 1380 | unmap_and_free_pt(pt, ppgtt->base.dev); |
4933d519 | 1381 | } |
06fda602 | 1382 | |
4933d519 | 1383 | unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev); |
e5815a2e | 1384 | unmap_and_free_pd(&ppgtt->pd, ppgtt->base.dev); |
3440d265 DV |
1385 | } |
1386 | ||
b146520f | 1387 | static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) |
3440d265 | 1388 | { |
853ba5d2 | 1389 | struct drm_device *dev = ppgtt->base.dev; |
1d2a314c | 1390 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3cc1995 | 1391 | bool retried = false; |
b146520f | 1392 | int ret; |
1d2a314c | 1393 | |
c8d4c0d6 BW |
1394 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
1395 | * allocator works in address space sizes, so it's multiplied by page | |
1396 | * size. We allocate at the top of the GTT to avoid fragmentation. | |
1397 | */ | |
1398 | BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm)); | |
8a1ebd74 | 1399 | ppgtt->scratch_pt = alloc_pt(ppgtt->base.dev); |
4933d519 MT |
1400 | if (IS_ERR(ppgtt->scratch_pt)) |
1401 | return PTR_ERR(ppgtt->scratch_pt); | |
1402 | ||
1403 | gen6_initialize_pt(&ppgtt->base, ppgtt->scratch_pt); | |
1404 | ||
e3cc1995 | 1405 | alloc: |
c8d4c0d6 BW |
1406 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm, |
1407 | &ppgtt->node, GEN6_PD_SIZE, | |
1408 | GEN6_PD_ALIGN, 0, | |
1409 | 0, dev_priv->gtt.base.total, | |
3e8b5ae9 | 1410 | DRM_MM_TOPDOWN); |
e3cc1995 BW |
1411 | if (ret == -ENOSPC && !retried) { |
1412 | ret = i915_gem_evict_something(dev, &dev_priv->gtt.base, | |
1413 | GEN6_PD_SIZE, GEN6_PD_ALIGN, | |
d23db88c CW |
1414 | I915_CACHE_NONE, |
1415 | 0, dev_priv->gtt.base.total, | |
1416 | 0); | |
e3cc1995 | 1417 | if (ret) |
678d96fb | 1418 | goto err_out; |
e3cc1995 BW |
1419 | |
1420 | retried = true; | |
1421 | goto alloc; | |
1422 | } | |
c8d4c0d6 | 1423 | |
c8c26622 | 1424 | if (ret) |
678d96fb BW |
1425 | goto err_out; |
1426 | ||
c8c26622 | 1427 | |
c8d4c0d6 BW |
1428 | if (ppgtt->node.start < dev_priv->gtt.mappable_end) |
1429 | DRM_DEBUG("Forced to use aperture for PDEs\n"); | |
1d2a314c | 1430 | |
c8c26622 | 1431 | return 0; |
678d96fb BW |
1432 | |
1433 | err_out: | |
4933d519 | 1434 | unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev); |
678d96fb | 1435 | return ret; |
b146520f BW |
1436 | } |
1437 | ||
b146520f BW |
1438 | static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) |
1439 | { | |
2f2cf682 | 1440 | return gen6_ppgtt_allocate_page_directories(ppgtt); |
4933d519 | 1441 | } |
06dc68d6 | 1442 | |
4933d519 MT |
1443 | static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt, |
1444 | uint64_t start, uint64_t length) | |
1445 | { | |
ec565b3c | 1446 | struct i915_page_table *unused; |
4933d519 | 1447 | uint32_t pde, temp; |
1d2a314c | 1448 | |
4933d519 MT |
1449 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) |
1450 | ppgtt->pd.page_table[pde] = ppgtt->scratch_pt; | |
b146520f BW |
1451 | } |
1452 | ||
5c5f6457 | 1453 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
b146520f BW |
1454 | { |
1455 | struct drm_device *dev = ppgtt->base.dev; | |
1456 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1457 | int ret; | |
1458 | ||
1459 | ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; | |
1460 | if (IS_GEN6(dev)) { | |
b146520f BW |
1461 | ppgtt->switch_mm = gen6_mm_switch; |
1462 | } else if (IS_HASWELL(dev)) { | |
b146520f BW |
1463 | ppgtt->switch_mm = hsw_mm_switch; |
1464 | } else if (IS_GEN7(dev)) { | |
b146520f BW |
1465 | ppgtt->switch_mm = gen7_mm_switch; |
1466 | } else | |
1467 | BUG(); | |
1468 | ||
71ba2d64 YZ |
1469 | if (intel_vgpu_active(dev)) |
1470 | ppgtt->switch_mm = vgpu_mm_switch; | |
1471 | ||
b146520f BW |
1472 | ret = gen6_ppgtt_alloc(ppgtt); |
1473 | if (ret) | |
1474 | return ret; | |
1475 | ||
5c5f6457 | 1476 | ppgtt->base.allocate_va_range = gen6_alloc_va_range; |
b146520f BW |
1477 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
1478 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
777dc5bb DV |
1479 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; |
1480 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
b146520f | 1481 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; |
b146520f | 1482 | ppgtt->base.start = 0; |
09942c65 | 1483 | ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE; |
87d60b63 | 1484 | ppgtt->debug_dump = gen6_dump_ppgtt; |
1d2a314c | 1485 | |
44159ddb | 1486 | ppgtt->pd.base.ggtt_offset = |
07749ef3 | 1487 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t); |
1d2a314c | 1488 | |
678d96fb | 1489 | ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm + |
44159ddb | 1490 | ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t); |
678d96fb | 1491 | |
5c5f6457 | 1492 | gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total); |
1d2a314c | 1493 | |
678d96fb BW |
1494 | gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total); |
1495 | ||
440fd528 | 1496 | DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n", |
b146520f BW |
1497 | ppgtt->node.size >> 20, |
1498 | ppgtt->node.start / PAGE_SIZE); | |
3440d265 | 1499 | |
fa76da34 | 1500 | DRM_DEBUG("Adding PPGTT at offset %x\n", |
44159ddb | 1501 | ppgtt->pd.base.ggtt_offset << 10); |
fa76da34 | 1502 | |
b146520f | 1503 | return 0; |
3440d265 DV |
1504 | } |
1505 | ||
5c5f6457 | 1506 | static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) |
3440d265 DV |
1507 | { |
1508 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3440d265 | 1509 | |
853ba5d2 | 1510 | ppgtt->base.dev = dev; |
8407bb91 | 1511 | ppgtt->base.scratch = dev_priv->gtt.base.scratch; |
3440d265 | 1512 | |
3ed124b2 | 1513 | if (INTEL_INFO(dev)->gen < 8) |
5c5f6457 | 1514 | return gen6_ppgtt_init(ppgtt); |
3ed124b2 | 1515 | else |
d7b2633d | 1516 | return gen8_ppgtt_init(ppgtt); |
fa76da34 DV |
1517 | } |
1518 | int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) | |
1519 | { | |
1520 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1521 | int ret = 0; | |
3ed124b2 | 1522 | |
5c5f6457 | 1523 | ret = __hw_ppgtt_init(dev, ppgtt); |
fa76da34 | 1524 | if (ret == 0) { |
c7c48dfd | 1525 | kref_init(&ppgtt->ref); |
93bd8649 BW |
1526 | drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, |
1527 | ppgtt->base.total); | |
7e0d96bc | 1528 | i915_init_vm(dev_priv, &ppgtt->base); |
93bd8649 | 1529 | } |
1d2a314c DV |
1530 | |
1531 | return ret; | |
1532 | } | |
1533 | ||
82460d97 DV |
1534 | int i915_ppgtt_init_hw(struct drm_device *dev) |
1535 | { | |
671b5013 TD |
1536 | /* In the case of execlists, PPGTT is enabled by the context descriptor |
1537 | * and the PDPs are contained within the context itself. We don't | |
1538 | * need to do anything here. */ | |
1539 | if (i915.enable_execlists) | |
1540 | return 0; | |
1541 | ||
82460d97 DV |
1542 | if (!USES_PPGTT(dev)) |
1543 | return 0; | |
1544 | ||
1545 | if (IS_GEN6(dev)) | |
1546 | gen6_ppgtt_enable(dev); | |
1547 | else if (IS_GEN7(dev)) | |
1548 | gen7_ppgtt_enable(dev); | |
1549 | else if (INTEL_INFO(dev)->gen >= 8) | |
1550 | gen8_ppgtt_enable(dev); | |
1551 | else | |
5f77eeb0 | 1552 | MISSING_CASE(INTEL_INFO(dev)->gen); |
82460d97 | 1553 | |
4ad2fd88 JH |
1554 | return 0; |
1555 | } | |
1d2a314c | 1556 | |
b3dd6b96 | 1557 | int i915_ppgtt_init_ring(struct drm_i915_gem_request *req) |
4ad2fd88 | 1558 | { |
b3dd6b96 | 1559 | struct drm_i915_private *dev_priv = req->ring->dev->dev_private; |
4ad2fd88 JH |
1560 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
1561 | ||
1562 | if (i915.enable_execlists) | |
1563 | return 0; | |
1564 | ||
1565 | if (!ppgtt) | |
1566 | return 0; | |
1567 | ||
e85b26dc | 1568 | return ppgtt->switch_mm(ppgtt, req); |
1d2a314c | 1569 | } |
4ad2fd88 | 1570 | |
4d884705 DV |
1571 | struct i915_hw_ppgtt * |
1572 | i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv) | |
1573 | { | |
1574 | struct i915_hw_ppgtt *ppgtt; | |
1575 | int ret; | |
1576 | ||
1577 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
1578 | if (!ppgtt) | |
1579 | return ERR_PTR(-ENOMEM); | |
1580 | ||
1581 | ret = i915_ppgtt_init(dev, ppgtt); | |
1582 | if (ret) { | |
1583 | kfree(ppgtt); | |
1584 | return ERR_PTR(ret); | |
1585 | } | |
1586 | ||
1587 | ppgtt->file_priv = fpriv; | |
1588 | ||
198c974d DCS |
1589 | trace_i915_ppgtt_create(&ppgtt->base); |
1590 | ||
4d884705 DV |
1591 | return ppgtt; |
1592 | } | |
1593 | ||
ee960be7 DV |
1594 | void i915_ppgtt_release(struct kref *kref) |
1595 | { | |
1596 | struct i915_hw_ppgtt *ppgtt = | |
1597 | container_of(kref, struct i915_hw_ppgtt, ref); | |
1598 | ||
198c974d DCS |
1599 | trace_i915_ppgtt_release(&ppgtt->base); |
1600 | ||
ee960be7 DV |
1601 | /* vmas should already be unbound */ |
1602 | WARN_ON(!list_empty(&ppgtt->base.active_list)); | |
1603 | WARN_ON(!list_empty(&ppgtt->base.inactive_list)); | |
1604 | ||
19dd120c DV |
1605 | list_del(&ppgtt->base.global_link); |
1606 | drm_mm_takedown(&ppgtt->base.mm); | |
1607 | ||
ee960be7 DV |
1608 | ppgtt->base.cleanup(&ppgtt->base); |
1609 | kfree(ppgtt); | |
1610 | } | |
1d2a314c | 1611 | |
a81cc00c BW |
1612 | extern int intel_iommu_gfx_mapped; |
1613 | /* Certain Gen5 chipsets require require idling the GPU before | |
1614 | * unmapping anything from the GTT when VT-d is enabled. | |
1615 | */ | |
2c642b07 | 1616 | static bool needs_idle_maps(struct drm_device *dev) |
a81cc00c BW |
1617 | { |
1618 | #ifdef CONFIG_INTEL_IOMMU | |
1619 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
1620 | * was loaded first. | |
1621 | */ | |
1622 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
1623 | return true; | |
1624 | #endif | |
1625 | return false; | |
1626 | } | |
1627 | ||
5c042287 BW |
1628 | static bool do_idling(struct drm_i915_private *dev_priv) |
1629 | { | |
1630 | bool ret = dev_priv->mm.interruptible; | |
1631 | ||
a81cc00c | 1632 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 1633 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 1634 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
1635 | DRM_ERROR("Couldn't idle GPU\n"); |
1636 | /* Wait a bit, in hopes it avoids the hang */ | |
1637 | udelay(10); | |
1638 | } | |
1639 | } | |
1640 | ||
1641 | return ret; | |
1642 | } | |
1643 | ||
1644 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
1645 | { | |
a81cc00c | 1646 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
1647 | dev_priv->mm.interruptible = interruptible; |
1648 | } | |
1649 | ||
828c7908 BW |
1650 | void i915_check_and_clear_faults(struct drm_device *dev) |
1651 | { | |
1652 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 1653 | struct intel_engine_cs *ring; |
828c7908 BW |
1654 | int i; |
1655 | ||
1656 | if (INTEL_INFO(dev)->gen < 6) | |
1657 | return; | |
1658 | ||
1659 | for_each_ring(ring, dev_priv, i) { | |
1660 | u32 fault_reg; | |
1661 | fault_reg = I915_READ(RING_FAULT_REG(ring)); | |
1662 | if (fault_reg & RING_FAULT_VALID) { | |
1663 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
59a5d290 | 1664 | "\tAddr: 0x%08lx\n" |
828c7908 BW |
1665 | "\tAddress space: %s\n" |
1666 | "\tSource ID: %d\n" | |
1667 | "\tType: %d\n", | |
1668 | fault_reg & PAGE_MASK, | |
1669 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
1670 | RING_FAULT_SRCID(fault_reg), | |
1671 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
1672 | I915_WRITE(RING_FAULT_REG(ring), | |
1673 | fault_reg & ~RING_FAULT_VALID); | |
1674 | } | |
1675 | } | |
1676 | POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); | |
1677 | } | |
1678 | ||
91e56499 CW |
1679 | static void i915_ggtt_flush(struct drm_i915_private *dev_priv) |
1680 | { | |
1681 | if (INTEL_INFO(dev_priv->dev)->gen < 6) { | |
1682 | intel_gtt_chipset_flush(); | |
1683 | } else { | |
1684 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1685 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
1686 | } | |
1687 | } | |
1688 | ||
828c7908 BW |
1689 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) |
1690 | { | |
1691 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1692 | ||
1693 | /* Don't bother messing with faults pre GEN6 as we have little | |
1694 | * documentation supporting that it's a good idea. | |
1695 | */ | |
1696 | if (INTEL_INFO(dev)->gen < 6) | |
1697 | return; | |
1698 | ||
1699 | i915_check_and_clear_faults(dev); | |
1700 | ||
1701 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, | |
782f1495 BW |
1702 | dev_priv->gtt.base.start, |
1703 | dev_priv->gtt.base.total, | |
e568af1c | 1704 | true); |
91e56499 CW |
1705 | |
1706 | i915_ggtt_flush(dev_priv); | |
828c7908 BW |
1707 | } |
1708 | ||
74163907 | 1709 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 1710 | { |
9da3da66 | 1711 | if (obj->has_dma_mapping) |
74163907 | 1712 | return 0; |
9da3da66 CW |
1713 | |
1714 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
1715 | obj->pages->sgl, obj->pages->nents, | |
1716 | PCI_DMA_BIDIRECTIONAL)) | |
1717 | return -ENOSPC; | |
1718 | ||
1719 | return 0; | |
7c2e6fdf DV |
1720 | } |
1721 | ||
2c642b07 | 1722 | static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte) |
94ec8f61 BW |
1723 | { |
1724 | #ifdef writeq | |
1725 | writeq(pte, addr); | |
1726 | #else | |
1727 | iowrite32((u32)pte, addr); | |
1728 | iowrite32(pte >> 32, addr + 4); | |
1729 | #endif | |
1730 | } | |
1731 | ||
1732 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, | |
1733 | struct sg_table *st, | |
782f1495 | 1734 | uint64_t start, |
24f3a8cf | 1735 | enum i915_cache_level level, u32 unused) |
94ec8f61 BW |
1736 | { |
1737 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 | 1738 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1739 | gen8_pte_t __iomem *gtt_entries = |
1740 | (gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
94ec8f61 BW |
1741 | int i = 0; |
1742 | struct sg_page_iter sg_iter; | |
57007df7 | 1743 | dma_addr_t addr = 0; /* shut up gcc */ |
94ec8f61 BW |
1744 | |
1745 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { | |
1746 | addr = sg_dma_address(sg_iter.sg) + | |
1747 | (sg_iter.sg_pgoffset << PAGE_SHIFT); | |
1748 | gen8_set_pte(>t_entries[i], | |
1749 | gen8_pte_encode(addr, level, true)); | |
1750 | i++; | |
1751 | } | |
1752 | ||
1753 | /* | |
1754 | * XXX: This serves as a posting read to make sure that the PTE has | |
1755 | * actually been updated. There is some concern that even though | |
1756 | * registers and PTEs are within the same BAR that they are potentially | |
1757 | * of NUMA access patterns. Therefore, even with the way we assume | |
1758 | * hardware should work, we must keep this posting read for paranoia. | |
1759 | */ | |
1760 | if (i != 0) | |
1761 | WARN_ON(readq(>t_entries[i-1]) | |
1762 | != gen8_pte_encode(addr, level, true)); | |
1763 | ||
94ec8f61 BW |
1764 | /* This next bit makes the above posting read even more important. We |
1765 | * want to flush the TLBs only after we're certain all the PTE updates | |
1766 | * have finished. | |
1767 | */ | |
1768 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1769 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
94ec8f61 BW |
1770 | } |
1771 | ||
e76e9aeb BW |
1772 | /* |
1773 | * Binds an object into the global gtt with the specified cache level. The object | |
1774 | * will be accessible to the GPU via commands whose operands reference offsets | |
1775 | * within the global GTT as well as accessible by the GPU through the GMADR | |
1776 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
1777 | */ | |
853ba5d2 | 1778 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 | 1779 | struct sg_table *st, |
782f1495 | 1780 | uint64_t start, |
24f3a8cf | 1781 | enum i915_cache_level level, u32 flags) |
e76e9aeb | 1782 | { |
853ba5d2 | 1783 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 | 1784 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1785 | gen6_pte_t __iomem *gtt_entries = |
1786 | (gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
1787 | int i = 0; |
1788 | struct sg_page_iter sg_iter; | |
57007df7 | 1789 | dma_addr_t addr = 0; |
e76e9aeb | 1790 | |
6e995e23 | 1791 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 1792 | addr = sg_page_iter_dma_address(&sg_iter); |
24f3a8cf | 1793 | iowrite32(vm->pte_encode(addr, level, true, flags), >t_entries[i]); |
6e995e23 | 1794 | i++; |
e76e9aeb BW |
1795 | } |
1796 | ||
e76e9aeb BW |
1797 | /* XXX: This serves as a posting read to make sure that the PTE has |
1798 | * actually been updated. There is some concern that even though | |
1799 | * registers and PTEs are within the same BAR that they are potentially | |
1800 | * of NUMA access patterns. Therefore, even with the way we assume | |
1801 | * hardware should work, we must keep this posting read for paranoia. | |
1802 | */ | |
57007df7 PM |
1803 | if (i != 0) { |
1804 | unsigned long gtt = readl(>t_entries[i-1]); | |
1805 | WARN_ON(gtt != vm->pte_encode(addr, level, true, flags)); | |
1806 | } | |
0f9b91c7 BW |
1807 | |
1808 | /* This next bit makes the above posting read even more important. We | |
1809 | * want to flush the TLBs only after we're certain all the PTE updates | |
1810 | * have finished. | |
1811 | */ | |
1812 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1813 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
1814 | } |
1815 | ||
94ec8f61 | 1816 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1817 | uint64_t start, |
1818 | uint64_t length, | |
94ec8f61 BW |
1819 | bool use_scratch) |
1820 | { | |
1821 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 BW |
1822 | unsigned first_entry = start >> PAGE_SHIFT; |
1823 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1824 | gen8_pte_t scratch_pte, __iomem *gtt_base = |
1825 | (gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
94ec8f61 BW |
1826 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
1827 | int i; | |
1828 | ||
1829 | if (WARN(num_entries > max_entries, | |
1830 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1831 | first_entry, num_entries, max_entries)) | |
1832 | num_entries = max_entries; | |
1833 | ||
1834 | scratch_pte = gen8_pte_encode(vm->scratch.addr, | |
1835 | I915_CACHE_LLC, | |
1836 | use_scratch); | |
1837 | for (i = 0; i < num_entries; i++) | |
1838 | gen8_set_pte(>t_base[i], scratch_pte); | |
1839 | readl(gtt_base); | |
1840 | } | |
1841 | ||
853ba5d2 | 1842 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1843 | uint64_t start, |
1844 | uint64_t length, | |
828c7908 | 1845 | bool use_scratch) |
7faf1ab2 | 1846 | { |
853ba5d2 | 1847 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 BW |
1848 | unsigned first_entry = start >> PAGE_SHIFT; |
1849 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1850 | gen6_pte_t scratch_pte, __iomem *gtt_base = |
1851 | (gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 1852 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
1853 | int i; |
1854 | ||
1855 | if (WARN(num_entries > max_entries, | |
1856 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1857 | first_entry, num_entries, max_entries)) | |
1858 | num_entries = max_entries; | |
1859 | ||
24f3a8cf | 1860 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch, 0); |
828c7908 | 1861 | |
7faf1ab2 DV |
1862 | for (i = 0; i < num_entries; i++) |
1863 | iowrite32(scratch_pte, >t_base[i]); | |
1864 | readl(gtt_base); | |
1865 | } | |
1866 | ||
d369d2d9 DV |
1867 | static void i915_ggtt_insert_entries(struct i915_address_space *vm, |
1868 | struct sg_table *pages, | |
1869 | uint64_t start, | |
1870 | enum i915_cache_level cache_level, u32 unused) | |
7faf1ab2 DV |
1871 | { |
1872 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? | |
1873 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
1874 | ||
d369d2d9 | 1875 | intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags); |
0875546c | 1876 | |
7faf1ab2 DV |
1877 | } |
1878 | ||
853ba5d2 | 1879 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1880 | uint64_t start, |
1881 | uint64_t length, | |
828c7908 | 1882 | bool unused) |
7faf1ab2 | 1883 | { |
782f1495 BW |
1884 | unsigned first_entry = start >> PAGE_SHIFT; |
1885 | unsigned num_entries = length >> PAGE_SHIFT; | |
7faf1ab2 DV |
1886 | intel_gtt_clear_range(first_entry, num_entries); |
1887 | } | |
1888 | ||
70b9f6f8 DV |
1889 | static int ggtt_bind_vma(struct i915_vma *vma, |
1890 | enum i915_cache_level cache_level, | |
1891 | u32 flags) | |
d5bd1449 | 1892 | { |
6f65e29a | 1893 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1894 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1895 | struct drm_i915_gem_object *obj = vma->obj; |
ec7adb6e | 1896 | struct sg_table *pages = obj->pages; |
f329f5f6 | 1897 | u32 pte_flags = 0; |
70b9f6f8 DV |
1898 | int ret; |
1899 | ||
1900 | ret = i915_get_ggtt_vma_pages(vma); | |
1901 | if (ret) | |
1902 | return ret; | |
1903 | pages = vma->ggtt_view.pages; | |
7faf1ab2 | 1904 | |
24f3a8cf AG |
1905 | /* Currently applicable only to VLV */ |
1906 | if (obj->gt_ro) | |
f329f5f6 | 1907 | pte_flags |= PTE_READ_ONLY; |
24f3a8cf | 1908 | |
ec7adb6e | 1909 | |
6f65e29a | 1910 | if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) { |
0875546c DV |
1911 | vma->vm->insert_entries(vma->vm, pages, |
1912 | vma->node.start, | |
1913 | cache_level, pte_flags); | |
6f65e29a | 1914 | } |
d5bd1449 | 1915 | |
0875546c | 1916 | if (dev_priv->mm.aliasing_ppgtt && flags & LOCAL_BIND) { |
6f65e29a | 1917 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; |
ec7adb6e | 1918 | appgtt->base.insert_entries(&appgtt->base, pages, |
782f1495 | 1919 | vma->node.start, |
f329f5f6 | 1920 | cache_level, pte_flags); |
6f65e29a | 1921 | } |
70b9f6f8 DV |
1922 | |
1923 | return 0; | |
d5bd1449 CW |
1924 | } |
1925 | ||
6f65e29a | 1926 | static void ggtt_unbind_vma(struct i915_vma *vma) |
74163907 | 1927 | { |
6f65e29a | 1928 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1929 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1930 | struct drm_i915_gem_object *obj = vma->obj; |
06615ee5 JL |
1931 | const uint64_t size = min_t(uint64_t, |
1932 | obj->base.size, | |
1933 | vma->node.size); | |
6f65e29a | 1934 | |
aff43766 | 1935 | if (vma->bound & GLOBAL_BIND) { |
782f1495 BW |
1936 | vma->vm->clear_range(vma->vm, |
1937 | vma->node.start, | |
06615ee5 | 1938 | size, |
6f65e29a | 1939 | true); |
6f65e29a | 1940 | } |
74898d7e | 1941 | |
0875546c | 1942 | if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) { |
6f65e29a | 1943 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; |
06615ee5 | 1944 | |
6f65e29a | 1945 | appgtt->base.clear_range(&appgtt->base, |
782f1495 | 1946 | vma->node.start, |
06615ee5 | 1947 | size, |
6f65e29a | 1948 | true); |
6f65e29a | 1949 | } |
74163907 DV |
1950 | } |
1951 | ||
1952 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 1953 | { |
5c042287 BW |
1954 | struct drm_device *dev = obj->base.dev; |
1955 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1956 | bool interruptible; | |
1957 | ||
1958 | interruptible = do_idling(dev_priv); | |
1959 | ||
9da3da66 CW |
1960 | if (!obj->has_dma_mapping) |
1961 | dma_unmap_sg(&dev->pdev->dev, | |
1962 | obj->pages->sgl, obj->pages->nents, | |
1963 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
1964 | |
1965 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 1966 | } |
644ec02b | 1967 | |
42d6ab48 CW |
1968 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
1969 | unsigned long color, | |
440fd528 TR |
1970 | u64 *start, |
1971 | u64 *end) | |
42d6ab48 CW |
1972 | { |
1973 | if (node->color != color) | |
1974 | *start += 4096; | |
1975 | ||
1976 | if (!list_empty(&node->node_list)) { | |
1977 | node = list_entry(node->node_list.next, | |
1978 | struct drm_mm_node, | |
1979 | node_list); | |
1980 | if (node->allocated && node->color != color) | |
1981 | *end -= 4096; | |
1982 | } | |
1983 | } | |
fbe5d36e | 1984 | |
f548c0e9 DV |
1985 | static int i915_gem_setup_global_gtt(struct drm_device *dev, |
1986 | unsigned long start, | |
1987 | unsigned long mappable_end, | |
1988 | unsigned long end) | |
644ec02b | 1989 | { |
e78891ca BW |
1990 | /* Let GEM Manage all of the aperture. |
1991 | * | |
1992 | * However, leave one page at the end still bound to the scratch page. | |
1993 | * There are a number of places where the hardware apparently prefetches | |
1994 | * past the end of the object, and we've seen multiple hangs with the | |
1995 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
1996 | * aperture. One page should be enough to keep any prefetching inside | |
1997 | * of the aperture. | |
1998 | */ | |
40d74980 BW |
1999 | struct drm_i915_private *dev_priv = dev->dev_private; |
2000 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; | |
ed2f3452 CW |
2001 | struct drm_mm_node *entry; |
2002 | struct drm_i915_gem_object *obj; | |
2003 | unsigned long hole_start, hole_end; | |
fa76da34 | 2004 | int ret; |
644ec02b | 2005 | |
35451cb6 BW |
2006 | BUG_ON(mappable_end > end); |
2007 | ||
ed2f3452 | 2008 | /* Subtract the guard page ... */ |
40d74980 | 2009 | drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); |
5dda8fa3 YZ |
2010 | |
2011 | dev_priv->gtt.base.start = start; | |
2012 | dev_priv->gtt.base.total = end - start; | |
2013 | ||
2014 | if (intel_vgpu_active(dev)) { | |
2015 | ret = intel_vgt_balloon(dev); | |
2016 | if (ret) | |
2017 | return ret; | |
2018 | } | |
2019 | ||
42d6ab48 | 2020 | if (!HAS_LLC(dev)) |
93bd8649 | 2021 | dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; |
644ec02b | 2022 | |
ed2f3452 | 2023 | /* Mark any preallocated objects as occupied */ |
35c20a60 | 2024 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
40d74980 | 2025 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
fa76da34 | 2026 | |
edd41a87 | 2027 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
c6cfb325 BW |
2028 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
2029 | ||
2030 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); | |
40d74980 | 2031 | ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); |
6c5566a8 DV |
2032 | if (ret) { |
2033 | DRM_DEBUG_KMS("Reservation failed: %i\n", ret); | |
2034 | return ret; | |
2035 | } | |
aff43766 | 2036 | vma->bound |= GLOBAL_BIND; |
ed2f3452 CW |
2037 | } |
2038 | ||
ed2f3452 | 2039 | /* Clear any non-preallocated blocks */ |
40d74980 | 2040 | drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { |
ed2f3452 CW |
2041 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
2042 | hole_start, hole_end); | |
782f1495 BW |
2043 | ggtt_vm->clear_range(ggtt_vm, hole_start, |
2044 | hole_end - hole_start, true); | |
ed2f3452 CW |
2045 | } |
2046 | ||
2047 | /* And finally clear the reserved guard page */ | |
782f1495 | 2048 | ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true); |
6c5566a8 | 2049 | |
fa76da34 DV |
2050 | if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) { |
2051 | struct i915_hw_ppgtt *ppgtt; | |
2052 | ||
2053 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
2054 | if (!ppgtt) | |
2055 | return -ENOMEM; | |
2056 | ||
5c5f6457 DV |
2057 | ret = __hw_ppgtt_init(dev, ppgtt); |
2058 | if (ret) { | |
2059 | ppgtt->base.cleanup(&ppgtt->base); | |
2060 | kfree(ppgtt); | |
2061 | return ret; | |
2062 | } | |
2063 | ||
2064 | if (ppgtt->base.allocate_va_range) | |
2065 | ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0, | |
2066 | ppgtt->base.total); | |
4933d519 | 2067 | if (ret) { |
061dd493 | 2068 | ppgtt->base.cleanup(&ppgtt->base); |
4933d519 | 2069 | kfree(ppgtt); |
fa76da34 | 2070 | return ret; |
4933d519 | 2071 | } |
fa76da34 | 2072 | |
5c5f6457 DV |
2073 | ppgtt->base.clear_range(&ppgtt->base, |
2074 | ppgtt->base.start, | |
2075 | ppgtt->base.total, | |
2076 | true); | |
2077 | ||
fa76da34 DV |
2078 | dev_priv->mm.aliasing_ppgtt = ppgtt; |
2079 | } | |
2080 | ||
6c5566a8 | 2081 | return 0; |
e76e9aeb BW |
2082 | } |
2083 | ||
d7e5008f BW |
2084 | void i915_gem_init_global_gtt(struct drm_device *dev) |
2085 | { | |
2086 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c44ef60e | 2087 | u64 gtt_size, mappable_size; |
d7e5008f | 2088 | |
853ba5d2 | 2089 | gtt_size = dev_priv->gtt.base.total; |
93d18799 | 2090 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f | 2091 | |
e78891ca | 2092 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
2093 | } |
2094 | ||
90d0a0e8 DV |
2095 | void i915_global_gtt_cleanup(struct drm_device *dev) |
2096 | { | |
2097 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2098 | struct i915_address_space *vm = &dev_priv->gtt.base; | |
2099 | ||
70e32544 DV |
2100 | if (dev_priv->mm.aliasing_ppgtt) { |
2101 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2102 | ||
2103 | ppgtt->base.cleanup(&ppgtt->base); | |
2104 | } | |
2105 | ||
90d0a0e8 | 2106 | if (drm_mm_initialized(&vm->mm)) { |
5dda8fa3 YZ |
2107 | if (intel_vgpu_active(dev)) |
2108 | intel_vgt_deballoon(); | |
2109 | ||
90d0a0e8 DV |
2110 | drm_mm_takedown(&vm->mm); |
2111 | list_del(&vm->global_link); | |
2112 | } | |
2113 | ||
2114 | vm->cleanup(vm); | |
2115 | } | |
70e32544 | 2116 | |
e76e9aeb BW |
2117 | static int setup_scratch_page(struct drm_device *dev) |
2118 | { | |
2119 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2120 | struct page *page; | |
2121 | dma_addr_t dma_addr; | |
2122 | ||
2123 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
2124 | if (page == NULL) | |
2125 | return -ENOMEM; | |
e76e9aeb BW |
2126 | set_pages_uc(page, 1); |
2127 | ||
2128 | #ifdef CONFIG_INTEL_IOMMU | |
2129 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
2130 | PCI_DMA_BIDIRECTIONAL); | |
ea3f5d26 MK |
2131 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) { |
2132 | __free_page(page); | |
e76e9aeb | 2133 | return -EINVAL; |
ea3f5d26 | 2134 | } |
e76e9aeb BW |
2135 | #else |
2136 | dma_addr = page_to_phys(page); | |
2137 | #endif | |
853ba5d2 BW |
2138 | dev_priv->gtt.base.scratch.page = page; |
2139 | dev_priv->gtt.base.scratch.addr = dma_addr; | |
e76e9aeb BW |
2140 | |
2141 | return 0; | |
2142 | } | |
2143 | ||
2144 | static void teardown_scratch_page(struct drm_device *dev) | |
2145 | { | |
2146 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 BW |
2147 | struct page *page = dev_priv->gtt.base.scratch.page; |
2148 | ||
2149 | set_pages_wb(page, 1); | |
2150 | pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr, | |
e76e9aeb | 2151 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
853ba5d2 | 2152 | __free_page(page); |
e76e9aeb BW |
2153 | } |
2154 | ||
2c642b07 | 2155 | static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2156 | { |
2157 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
2158 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
2159 | return snb_gmch_ctl << 20; | |
2160 | } | |
2161 | ||
2c642b07 | 2162 | static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
9459d252 BW |
2163 | { |
2164 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
2165 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
2166 | if (bdw_gmch_ctl) | |
2167 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
562d55d9 BW |
2168 | |
2169 | #ifdef CONFIG_X86_32 | |
2170 | /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */ | |
2171 | if (bdw_gmch_ctl > 4) | |
2172 | bdw_gmch_ctl = 4; | |
2173 | #endif | |
2174 | ||
9459d252 BW |
2175 | return bdw_gmch_ctl << 20; |
2176 | } | |
2177 | ||
2c642b07 | 2178 | static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) |
d7f25f23 DL |
2179 | { |
2180 | gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT; | |
2181 | gmch_ctrl &= SNB_GMCH_GGMS_MASK; | |
2182 | ||
2183 | if (gmch_ctrl) | |
2184 | return 1 << (20 + gmch_ctrl); | |
2185 | ||
2186 | return 0; | |
2187 | } | |
2188 | ||
2c642b07 | 2189 | static size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2190 | { |
2191 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
2192 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
2193 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
2194 | } | |
2195 | ||
2c642b07 | 2196 | static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
9459d252 BW |
2197 | { |
2198 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2199 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2200 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
2201 | } | |
2202 | ||
d7f25f23 DL |
2203 | static size_t chv_get_stolen_size(u16 gmch_ctrl) |
2204 | { | |
2205 | gmch_ctrl >>= SNB_GMCH_GMS_SHIFT; | |
2206 | gmch_ctrl &= SNB_GMCH_GMS_MASK; | |
2207 | ||
2208 | /* | |
2209 | * 0x0 to 0x10: 32MB increments starting at 0MB | |
2210 | * 0x11 to 0x16: 4MB increments starting at 8MB | |
2211 | * 0x17 to 0x1d: 4MB increments start at 36MB | |
2212 | */ | |
2213 | if (gmch_ctrl < 0x11) | |
2214 | return gmch_ctrl << 25; | |
2215 | else if (gmch_ctrl < 0x17) | |
2216 | return (gmch_ctrl - 0x11 + 2) << 22; | |
2217 | else | |
2218 | return (gmch_ctrl - 0x17 + 9) << 22; | |
2219 | } | |
2220 | ||
66375014 DL |
2221 | static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl) |
2222 | { | |
2223 | gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2224 | gen9_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2225 | ||
2226 | if (gen9_gmch_ctl < 0xf0) | |
2227 | return gen9_gmch_ctl << 25; /* 32 MB units */ | |
2228 | else | |
2229 | /* 4MB increments starting at 0xf0 for 4MB */ | |
2230 | return (gen9_gmch_ctl - 0xf0 + 1) << 22; | |
2231 | } | |
2232 | ||
63340133 BW |
2233 | static int ggtt_probe_common(struct drm_device *dev, |
2234 | size_t gtt_size) | |
2235 | { | |
2236 | struct drm_i915_private *dev_priv = dev->dev_private; | |
21c34607 | 2237 | phys_addr_t gtt_phys_addr; |
63340133 BW |
2238 | int ret; |
2239 | ||
2240 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
21c34607 | 2241 | gtt_phys_addr = pci_resource_start(dev->pdev, 0) + |
63340133 BW |
2242 | (pci_resource_len(dev->pdev, 0) / 2); |
2243 | ||
2a073f89 ID |
2244 | /* |
2245 | * On BXT writes larger than 64 bit to the GTT pagetable range will be | |
2246 | * dropped. For WC mappings in general we have 64 byte burst writes | |
2247 | * when the WC buffer is flushed, so we can't use it, but have to | |
2248 | * resort to an uncached mapping. The WC issue is easily caught by the | |
2249 | * readback check when writing GTT PTE entries. | |
2250 | */ | |
2251 | if (IS_BROXTON(dev)) | |
2252 | dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size); | |
2253 | else | |
2254 | dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size); | |
63340133 BW |
2255 | if (!dev_priv->gtt.gsm) { |
2256 | DRM_ERROR("Failed to map the gtt page table\n"); | |
2257 | return -ENOMEM; | |
2258 | } | |
2259 | ||
2260 | ret = setup_scratch_page(dev); | |
2261 | if (ret) { | |
2262 | DRM_ERROR("Scratch setup failed\n"); | |
2263 | /* iounmap will also get called at remove, but meh */ | |
2264 | iounmap(dev_priv->gtt.gsm); | |
2265 | } | |
2266 | ||
2267 | return ret; | |
2268 | } | |
2269 | ||
fbe5d36e BW |
2270 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
2271 | * bits. When using advanced contexts each context stores its own PAT, but | |
2272 | * writing this data shouldn't be harmful even in those cases. */ | |
ee0ce478 | 2273 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) |
fbe5d36e | 2274 | { |
fbe5d36e BW |
2275 | uint64_t pat; |
2276 | ||
2277 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
2278 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
2279 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
2280 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
2281 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
2282 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
2283 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
2284 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
2285 | ||
d6a8b72e RV |
2286 | if (!USES_PPGTT(dev_priv->dev)) |
2287 | /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry, | |
2288 | * so RTL will always use the value corresponding to | |
2289 | * pat_sel = 000". | |
2290 | * So let's disable cache for GGTT to avoid screen corruptions. | |
2291 | * MOCS still can be used though. | |
2292 | * - System agent ggtt writes (i.e. cpu gtt mmaps) already work | |
2293 | * before this patch, i.e. the same uncached + snooping access | |
2294 | * like on gen6/7 seems to be in effect. | |
2295 | * - So this just fixes blitter/render access. Again it looks | |
2296 | * like it's not just uncached access, but uncached + snooping. | |
2297 | * So we can still hold onto all our assumptions wrt cpu | |
2298 | * clflushing on LLC machines. | |
2299 | */ | |
2300 | pat = GEN8_PPAT(0, GEN8_PPAT_UC); | |
2301 | ||
fbe5d36e BW |
2302 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b |
2303 | * write would work. */ | |
2304 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
2305 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
2306 | } | |
2307 | ||
ee0ce478 VS |
2308 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) |
2309 | { | |
2310 | uint64_t pat; | |
2311 | ||
2312 | /* | |
2313 | * Map WB on BDW to snooped on CHV. | |
2314 | * | |
2315 | * Only the snoop bit has meaning for CHV, the rest is | |
2316 | * ignored. | |
2317 | * | |
cf3d262e VS |
2318 | * The hardware will never snoop for certain types of accesses: |
2319 | * - CPU GTT (GMADR->GGTT->no snoop->memory) | |
2320 | * - PPGTT page tables | |
2321 | * - some other special cycles | |
2322 | * | |
2323 | * As with BDW, we also need to consider the following for GT accesses: | |
2324 | * "For GGTT, there is NO pat_sel[2:0] from the entry, | |
2325 | * so RTL will always use the value corresponding to | |
2326 | * pat_sel = 000". | |
2327 | * Which means we must set the snoop bit in PAT entry 0 | |
2328 | * in order to keep the global status page working. | |
ee0ce478 VS |
2329 | */ |
2330 | pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | | |
2331 | GEN8_PPAT(1, 0) | | |
2332 | GEN8_PPAT(2, 0) | | |
2333 | GEN8_PPAT(3, 0) | | |
2334 | GEN8_PPAT(4, CHV_PPAT_SNOOP) | | |
2335 | GEN8_PPAT(5, CHV_PPAT_SNOOP) | | |
2336 | GEN8_PPAT(6, CHV_PPAT_SNOOP) | | |
2337 | GEN8_PPAT(7, CHV_PPAT_SNOOP); | |
2338 | ||
2339 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
2340 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
2341 | } | |
2342 | ||
63340133 | 2343 | static int gen8_gmch_probe(struct drm_device *dev, |
c44ef60e | 2344 | u64 *gtt_total, |
63340133 BW |
2345 | size_t *stolen, |
2346 | phys_addr_t *mappable_base, | |
c44ef60e | 2347 | u64 *mappable_end) |
63340133 BW |
2348 | { |
2349 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c44ef60e | 2350 | u64 gtt_size; |
63340133 BW |
2351 | u16 snb_gmch_ctl; |
2352 | int ret; | |
2353 | ||
2354 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
2355 | *mappable_base = pci_resource_start(dev->pdev, 2); | |
2356 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
2357 | ||
2358 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) | |
2359 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); | |
2360 | ||
2361 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
2362 | ||
66375014 DL |
2363 | if (INTEL_INFO(dev)->gen >= 9) { |
2364 | *stolen = gen9_get_stolen_size(snb_gmch_ctl); | |
2365 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
2366 | } else if (IS_CHERRYVIEW(dev)) { | |
d7f25f23 DL |
2367 | *stolen = chv_get_stolen_size(snb_gmch_ctl); |
2368 | gtt_size = chv_get_total_gtt_size(snb_gmch_ctl); | |
2369 | } else { | |
2370 | *stolen = gen8_get_stolen_size(snb_gmch_ctl); | |
2371 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
2372 | } | |
63340133 | 2373 | |
07749ef3 | 2374 | *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT; |
63340133 | 2375 | |
5a4e33a3 | 2376 | if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) |
ee0ce478 VS |
2377 | chv_setup_private_ppat(dev_priv); |
2378 | else | |
2379 | bdw_setup_private_ppat(dev_priv); | |
fbe5d36e | 2380 | |
63340133 BW |
2381 | ret = ggtt_probe_common(dev, gtt_size); |
2382 | ||
94ec8f61 BW |
2383 | dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range; |
2384 | dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries; | |
777dc5bb DV |
2385 | dev_priv->gtt.base.bind_vma = ggtt_bind_vma; |
2386 | dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma; | |
63340133 BW |
2387 | |
2388 | return ret; | |
2389 | } | |
2390 | ||
baa09f5f | 2391 | static int gen6_gmch_probe(struct drm_device *dev, |
c44ef60e | 2392 | u64 *gtt_total, |
41907ddc BW |
2393 | size_t *stolen, |
2394 | phys_addr_t *mappable_base, | |
c44ef60e | 2395 | u64 *mappable_end) |
e76e9aeb BW |
2396 | { |
2397 | struct drm_i915_private *dev_priv = dev->dev_private; | |
baa09f5f | 2398 | unsigned int gtt_size; |
e76e9aeb | 2399 | u16 snb_gmch_ctl; |
e76e9aeb BW |
2400 | int ret; |
2401 | ||
41907ddc BW |
2402 | *mappable_base = pci_resource_start(dev->pdev, 2); |
2403 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
2404 | ||
baa09f5f BW |
2405 | /* 64/512MB is the current min/max we actually know of, but this is just |
2406 | * a coarse sanity check. | |
e76e9aeb | 2407 | */ |
41907ddc | 2408 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
c44ef60e | 2409 | DRM_ERROR("Unknown GMADR size (%llx)\n", |
baa09f5f BW |
2410 | dev_priv->gtt.mappable_end); |
2411 | return -ENXIO; | |
e76e9aeb BW |
2412 | } |
2413 | ||
e76e9aeb BW |
2414 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
2415 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 2416 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
e76e9aeb | 2417 | |
c4ae25ec | 2418 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
a93e4161 | 2419 | |
63340133 | 2420 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
07749ef3 | 2421 | *gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT; |
e76e9aeb | 2422 | |
63340133 | 2423 | ret = ggtt_probe_common(dev, gtt_size); |
e76e9aeb | 2424 | |
853ba5d2 BW |
2425 | dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; |
2426 | dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; | |
777dc5bb DV |
2427 | dev_priv->gtt.base.bind_vma = ggtt_bind_vma; |
2428 | dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma; | |
7faf1ab2 | 2429 | |
e76e9aeb BW |
2430 | return ret; |
2431 | } | |
2432 | ||
853ba5d2 | 2433 | static void gen6_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 2434 | { |
853ba5d2 BW |
2435 | |
2436 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); | |
5ed16782 | 2437 | |
853ba5d2 BW |
2438 | iounmap(gtt->gsm); |
2439 | teardown_scratch_page(vm->dev); | |
644ec02b | 2440 | } |
baa09f5f BW |
2441 | |
2442 | static int i915_gmch_probe(struct drm_device *dev, | |
c44ef60e | 2443 | u64 *gtt_total, |
41907ddc BW |
2444 | size_t *stolen, |
2445 | phys_addr_t *mappable_base, | |
c44ef60e | 2446 | u64 *mappable_end) |
baa09f5f BW |
2447 | { |
2448 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2449 | int ret; | |
2450 | ||
baa09f5f BW |
2451 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
2452 | if (!ret) { | |
2453 | DRM_ERROR("failed to set up gmch\n"); | |
2454 | return -EIO; | |
2455 | } | |
2456 | ||
41907ddc | 2457 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
2458 | |
2459 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
d369d2d9 | 2460 | dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries; |
853ba5d2 | 2461 | dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; |
d369d2d9 DV |
2462 | dev_priv->gtt.base.bind_vma = ggtt_bind_vma; |
2463 | dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma; | |
baa09f5f | 2464 | |
c0a7f818 CW |
2465 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
2466 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); | |
2467 | ||
baa09f5f BW |
2468 | return 0; |
2469 | } | |
2470 | ||
853ba5d2 | 2471 | static void i915_gmch_remove(struct i915_address_space *vm) |
baa09f5f BW |
2472 | { |
2473 | intel_gmch_remove(); | |
2474 | } | |
2475 | ||
2476 | int i915_gem_gtt_init(struct drm_device *dev) | |
2477 | { | |
2478 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2479 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
2480 | int ret; |
2481 | ||
baa09f5f | 2482 | if (INTEL_INFO(dev)->gen <= 5) { |
b2f21b4d | 2483 | gtt->gtt_probe = i915_gmch_probe; |
853ba5d2 | 2484 | gtt->base.cleanup = i915_gmch_remove; |
63340133 | 2485 | } else if (INTEL_INFO(dev)->gen < 8) { |
b2f21b4d | 2486 | gtt->gtt_probe = gen6_gmch_probe; |
853ba5d2 | 2487 | gtt->base.cleanup = gen6_gmch_remove; |
4d15c145 | 2488 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
853ba5d2 | 2489 | gtt->base.pte_encode = iris_pte_encode; |
4d15c145 | 2490 | else if (IS_HASWELL(dev)) |
853ba5d2 | 2491 | gtt->base.pte_encode = hsw_pte_encode; |
b2f21b4d | 2492 | else if (IS_VALLEYVIEW(dev)) |
853ba5d2 | 2493 | gtt->base.pte_encode = byt_pte_encode; |
350ec881 CW |
2494 | else if (INTEL_INFO(dev)->gen >= 7) |
2495 | gtt->base.pte_encode = ivb_pte_encode; | |
b2f21b4d | 2496 | else |
350ec881 | 2497 | gtt->base.pte_encode = snb_pte_encode; |
63340133 BW |
2498 | } else { |
2499 | dev_priv->gtt.gtt_probe = gen8_gmch_probe; | |
2500 | dev_priv->gtt.base.cleanup = gen6_gmch_remove; | |
baa09f5f BW |
2501 | } |
2502 | ||
853ba5d2 | 2503 | ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, |
b2f21b4d | 2504 | >t->mappable_base, >t->mappable_end); |
a54c0c27 | 2505 | if (ret) |
baa09f5f | 2506 | return ret; |
baa09f5f | 2507 | |
853ba5d2 BW |
2508 | gtt->base.dev = dev; |
2509 | ||
baa09f5f | 2510 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
c44ef60e | 2511 | DRM_INFO("Memory usable by graphics device = %lluM\n", |
853ba5d2 | 2512 | gtt->base.total >> 20); |
c44ef60e | 2513 | DRM_DEBUG_DRIVER("GMADR size = %lldM\n", gtt->mappable_end >> 20); |
b2f21b4d | 2514 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); |
5db6c735 DV |
2515 | #ifdef CONFIG_INTEL_IOMMU |
2516 | if (intel_iommu_gfx_mapped) | |
2517 | DRM_INFO("VT-d active for gfx access\n"); | |
2518 | #endif | |
cfa7c862 DV |
2519 | /* |
2520 | * i915.enable_ppgtt is read-only, so do an early pass to validate the | |
2521 | * user's requested state against the hardware/driver capabilities. We | |
2522 | * do this now so that we can print out any log messages once rather | |
2523 | * than every time we check intel_enable_ppgtt(). | |
2524 | */ | |
2525 | i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt); | |
2526 | DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt); | |
baa09f5f BW |
2527 | |
2528 | return 0; | |
2529 | } | |
6f65e29a | 2530 | |
fa42331b DV |
2531 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
2532 | { | |
2533 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2534 | struct drm_i915_gem_object *obj; | |
2535 | struct i915_address_space *vm; | |
2536 | ||
2537 | i915_check_and_clear_faults(dev); | |
2538 | ||
2539 | /* First fill our portion of the GTT with scratch pages */ | |
2540 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, | |
2541 | dev_priv->gtt.base.start, | |
2542 | dev_priv->gtt.base.total, | |
2543 | true); | |
2544 | ||
2545 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
2546 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, | |
2547 | &dev_priv->gtt.base); | |
2548 | if (!vma) | |
2549 | continue; | |
2550 | ||
2551 | i915_gem_clflush_object(obj, obj->pin_display); | |
2552 | WARN_ON(i915_vma_bind(vma, obj->cache_level, PIN_UPDATE)); | |
2553 | } | |
2554 | ||
2555 | ||
2556 | if (INTEL_INFO(dev)->gen >= 8) { | |
2557 | if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) | |
2558 | chv_setup_private_ppat(dev_priv); | |
2559 | else | |
2560 | bdw_setup_private_ppat(dev_priv); | |
2561 | ||
2562 | return; | |
2563 | } | |
2564 | ||
2565 | if (USES_PPGTT(dev)) { | |
2566 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { | |
2567 | /* TODO: Perhaps it shouldn't be gen6 specific */ | |
2568 | ||
2569 | struct i915_hw_ppgtt *ppgtt = | |
2570 | container_of(vm, struct i915_hw_ppgtt, | |
2571 | base); | |
2572 | ||
2573 | if (i915_is_ggtt(vm)) | |
2574 | ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2575 | ||
2576 | gen6_write_page_range(dev_priv, &ppgtt->pd, | |
2577 | 0, ppgtt->base.total); | |
2578 | } | |
2579 | } | |
2580 | ||
2581 | i915_ggtt_flush(dev_priv); | |
2582 | } | |
2583 | ||
ec7adb6e JL |
2584 | static struct i915_vma * |
2585 | __i915_gem_vma_create(struct drm_i915_gem_object *obj, | |
2586 | struct i915_address_space *vm, | |
2587 | const struct i915_ggtt_view *ggtt_view) | |
6f65e29a | 2588 | { |
dabde5c7 | 2589 | struct i915_vma *vma; |
6f65e29a | 2590 | |
ec7adb6e JL |
2591 | if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)) |
2592 | return ERR_PTR(-EINVAL); | |
e20d2ab7 CW |
2593 | |
2594 | vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL); | |
dabde5c7 DC |
2595 | if (vma == NULL) |
2596 | return ERR_PTR(-ENOMEM); | |
ec7adb6e | 2597 | |
6f65e29a BW |
2598 | INIT_LIST_HEAD(&vma->vma_link); |
2599 | INIT_LIST_HEAD(&vma->mm_list); | |
2600 | INIT_LIST_HEAD(&vma->exec_list); | |
2601 | vma->vm = vm; | |
2602 | vma->obj = obj; | |
2603 | ||
777dc5bb | 2604 | if (i915_is_ggtt(vm)) |
ec7adb6e | 2605 | vma->ggtt_view = *ggtt_view; |
6f65e29a | 2606 | |
f7635669 TU |
2607 | list_add_tail(&vma->vma_link, &obj->vma_list); |
2608 | if (!i915_is_ggtt(vm)) | |
e07f0552 | 2609 | i915_ppgtt_get(i915_vm_to_ppgtt(vm)); |
6f65e29a BW |
2610 | |
2611 | return vma; | |
2612 | } | |
2613 | ||
2614 | struct i915_vma * | |
ec7adb6e JL |
2615 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, |
2616 | struct i915_address_space *vm) | |
2617 | { | |
2618 | struct i915_vma *vma; | |
2619 | ||
2620 | vma = i915_gem_obj_to_vma(obj, vm); | |
2621 | if (!vma) | |
2622 | vma = __i915_gem_vma_create(obj, vm, | |
2623 | i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL); | |
2624 | ||
2625 | return vma; | |
2626 | } | |
2627 | ||
2628 | struct i915_vma * | |
2629 | i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj, | |
fe14d5f4 | 2630 | const struct i915_ggtt_view *view) |
6f65e29a | 2631 | { |
ec7adb6e | 2632 | struct i915_address_space *ggtt = i915_obj_to_ggtt(obj); |
6f65e29a BW |
2633 | struct i915_vma *vma; |
2634 | ||
ec7adb6e JL |
2635 | if (WARN_ON(!view)) |
2636 | return ERR_PTR(-EINVAL); | |
2637 | ||
2638 | vma = i915_gem_obj_to_ggtt_view(obj, view); | |
2639 | ||
2640 | if (IS_ERR(vma)) | |
2641 | return vma; | |
2642 | ||
6f65e29a | 2643 | if (!vma) |
ec7adb6e | 2644 | vma = __i915_gem_vma_create(obj, ggtt, view); |
6f65e29a BW |
2645 | |
2646 | return vma; | |
ec7adb6e | 2647 | |
6f65e29a | 2648 | } |
fe14d5f4 | 2649 | |
50470bb0 TU |
2650 | static void |
2651 | rotate_pages(dma_addr_t *in, unsigned int width, unsigned int height, | |
2652 | struct sg_table *st) | |
2653 | { | |
2654 | unsigned int column, row; | |
2655 | unsigned int src_idx; | |
2656 | struct scatterlist *sg = st->sgl; | |
2657 | ||
2658 | st->nents = 0; | |
2659 | ||
2660 | for (column = 0; column < width; column++) { | |
2661 | src_idx = width * (height - 1) + column; | |
2662 | for (row = 0; row < height; row++) { | |
2663 | st->nents++; | |
2664 | /* We don't need the pages, but need to initialize | |
2665 | * the entries so the sg list can be happily traversed. | |
2666 | * The only thing we need are DMA addresses. | |
2667 | */ | |
2668 | sg_set_page(sg, NULL, PAGE_SIZE, 0); | |
2669 | sg_dma_address(sg) = in[src_idx]; | |
2670 | sg_dma_len(sg) = PAGE_SIZE; | |
2671 | sg = sg_next(sg); | |
2672 | src_idx -= width; | |
2673 | } | |
2674 | } | |
2675 | } | |
2676 | ||
2677 | static struct sg_table * | |
2678 | intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view, | |
2679 | struct drm_i915_gem_object *obj) | |
2680 | { | |
50470bb0 | 2681 | struct intel_rotation_info *rot_info = &ggtt_view->rotation_info; |
84fe03f7 | 2682 | unsigned int size_pages = rot_info->size >> PAGE_SHIFT; |
50470bb0 TU |
2683 | struct sg_page_iter sg_iter; |
2684 | unsigned long i; | |
2685 | dma_addr_t *page_addr_list; | |
2686 | struct sg_table *st; | |
1d00dad5 | 2687 | int ret = -ENOMEM; |
50470bb0 | 2688 | |
50470bb0 | 2689 | /* Allocate a temporary list of source pages for random access. */ |
84fe03f7 TU |
2690 | page_addr_list = drm_malloc_ab(obj->base.size / PAGE_SIZE, |
2691 | sizeof(dma_addr_t)); | |
50470bb0 TU |
2692 | if (!page_addr_list) |
2693 | return ERR_PTR(ret); | |
2694 | ||
2695 | /* Allocate target SG list. */ | |
2696 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
2697 | if (!st) | |
2698 | goto err_st_alloc; | |
2699 | ||
84fe03f7 | 2700 | ret = sg_alloc_table(st, size_pages, GFP_KERNEL); |
50470bb0 TU |
2701 | if (ret) |
2702 | goto err_sg_alloc; | |
2703 | ||
2704 | /* Populate source page list from the object. */ | |
2705 | i = 0; | |
2706 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { | |
2707 | page_addr_list[i] = sg_page_iter_dma_address(&sg_iter); | |
2708 | i++; | |
2709 | } | |
2710 | ||
2711 | /* Rotate the pages. */ | |
84fe03f7 TU |
2712 | rotate_pages(page_addr_list, |
2713 | rot_info->width_pages, rot_info->height_pages, | |
2714 | st); | |
50470bb0 TU |
2715 | |
2716 | DRM_DEBUG_KMS( | |
84fe03f7 | 2717 | "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages).\n", |
c9f8fd2d | 2718 | obj->base.size, rot_info->pitch, rot_info->height, |
84fe03f7 TU |
2719 | rot_info->pixel_format, rot_info->width_pages, |
2720 | rot_info->height_pages, size_pages); | |
50470bb0 TU |
2721 | |
2722 | drm_free_large(page_addr_list); | |
2723 | ||
2724 | return st; | |
2725 | ||
2726 | err_sg_alloc: | |
2727 | kfree(st); | |
2728 | err_st_alloc: | |
2729 | drm_free_large(page_addr_list); | |
2730 | ||
2731 | DRM_DEBUG_KMS( | |
84fe03f7 | 2732 | "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages)\n", |
c9f8fd2d | 2733 | obj->base.size, ret, rot_info->pitch, rot_info->height, |
84fe03f7 TU |
2734 | rot_info->pixel_format, rot_info->width_pages, |
2735 | rot_info->height_pages, size_pages); | |
50470bb0 TU |
2736 | return ERR_PTR(ret); |
2737 | } | |
ec7adb6e | 2738 | |
8bd7ef16 JL |
2739 | static struct sg_table * |
2740 | intel_partial_pages(const struct i915_ggtt_view *view, | |
2741 | struct drm_i915_gem_object *obj) | |
2742 | { | |
2743 | struct sg_table *st; | |
2744 | struct scatterlist *sg; | |
2745 | struct sg_page_iter obj_sg_iter; | |
2746 | int ret = -ENOMEM; | |
2747 | ||
2748 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
2749 | if (!st) | |
2750 | goto err_st_alloc; | |
2751 | ||
2752 | ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL); | |
2753 | if (ret) | |
2754 | goto err_sg_alloc; | |
2755 | ||
2756 | sg = st->sgl; | |
2757 | st->nents = 0; | |
2758 | for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents, | |
2759 | view->params.partial.offset) | |
2760 | { | |
2761 | if (st->nents >= view->params.partial.size) | |
2762 | break; | |
2763 | ||
2764 | sg_set_page(sg, NULL, PAGE_SIZE, 0); | |
2765 | sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter); | |
2766 | sg_dma_len(sg) = PAGE_SIZE; | |
2767 | ||
2768 | sg = sg_next(sg); | |
2769 | st->nents++; | |
2770 | } | |
2771 | ||
2772 | return st; | |
2773 | ||
2774 | err_sg_alloc: | |
2775 | kfree(st); | |
2776 | err_st_alloc: | |
2777 | return ERR_PTR(ret); | |
2778 | } | |
2779 | ||
70b9f6f8 | 2780 | static int |
50470bb0 | 2781 | i915_get_ggtt_vma_pages(struct i915_vma *vma) |
fe14d5f4 | 2782 | { |
50470bb0 TU |
2783 | int ret = 0; |
2784 | ||
fe14d5f4 TU |
2785 | if (vma->ggtt_view.pages) |
2786 | return 0; | |
2787 | ||
2788 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) | |
2789 | vma->ggtt_view.pages = vma->obj->pages; | |
50470bb0 TU |
2790 | else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED) |
2791 | vma->ggtt_view.pages = | |
2792 | intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj); | |
8bd7ef16 JL |
2793 | else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL) |
2794 | vma->ggtt_view.pages = | |
2795 | intel_partial_pages(&vma->ggtt_view, vma->obj); | |
fe14d5f4 TU |
2796 | else |
2797 | WARN_ONCE(1, "GGTT view %u not implemented!\n", | |
2798 | vma->ggtt_view.type); | |
2799 | ||
2800 | if (!vma->ggtt_view.pages) { | |
ec7adb6e | 2801 | DRM_ERROR("Failed to get pages for GGTT view type %u!\n", |
fe14d5f4 | 2802 | vma->ggtt_view.type); |
50470bb0 TU |
2803 | ret = -EINVAL; |
2804 | } else if (IS_ERR(vma->ggtt_view.pages)) { | |
2805 | ret = PTR_ERR(vma->ggtt_view.pages); | |
2806 | vma->ggtt_view.pages = NULL; | |
2807 | DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n", | |
2808 | vma->ggtt_view.type, ret); | |
fe14d5f4 TU |
2809 | } |
2810 | ||
50470bb0 | 2811 | return ret; |
fe14d5f4 TU |
2812 | } |
2813 | ||
2814 | /** | |
2815 | * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space. | |
2816 | * @vma: VMA to map | |
2817 | * @cache_level: mapping cache level | |
2818 | * @flags: flags like global or local mapping | |
2819 | * | |
2820 | * DMA addresses are taken from the scatter-gather table of this object (or of | |
2821 | * this VMA in case of non-default GGTT views) and PTE entries set up. | |
2822 | * Note that DMA addresses are also the only part of the SG table we care about. | |
2823 | */ | |
2824 | int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, | |
2825 | u32 flags) | |
2826 | { | |
75d04a37 MK |
2827 | int ret; |
2828 | u32 bind_flags; | |
1d335d1b | 2829 | |
75d04a37 MK |
2830 | if (WARN_ON(flags == 0)) |
2831 | return -EINVAL; | |
1d335d1b | 2832 | |
75d04a37 | 2833 | bind_flags = 0; |
0875546c DV |
2834 | if (flags & PIN_GLOBAL) |
2835 | bind_flags |= GLOBAL_BIND; | |
2836 | if (flags & PIN_USER) | |
2837 | bind_flags |= LOCAL_BIND; | |
2838 | ||
2839 | if (flags & PIN_UPDATE) | |
2840 | bind_flags |= vma->bound; | |
2841 | else | |
2842 | bind_flags &= ~vma->bound; | |
2843 | ||
75d04a37 MK |
2844 | if (bind_flags == 0) |
2845 | return 0; | |
2846 | ||
2847 | if (vma->bound == 0 && vma->vm->allocate_va_range) { | |
2848 | trace_i915_va_alloc(vma->vm, | |
2849 | vma->node.start, | |
2850 | vma->node.size, | |
2851 | VM_TO_TRACE_NAME(vma->vm)); | |
2852 | ||
2853 | ret = vma->vm->allocate_va_range(vma->vm, | |
2854 | vma->node.start, | |
2855 | vma->node.size); | |
2856 | if (ret) | |
2857 | return ret; | |
2858 | } | |
2859 | ||
2860 | ret = vma->vm->bind_vma(vma, cache_level, bind_flags); | |
70b9f6f8 DV |
2861 | if (ret) |
2862 | return ret; | |
0875546c DV |
2863 | |
2864 | vma->bound |= bind_flags; | |
fe14d5f4 TU |
2865 | |
2866 | return 0; | |
2867 | } | |
91e6711e JL |
2868 | |
2869 | /** | |
2870 | * i915_ggtt_view_size - Get the size of a GGTT view. | |
2871 | * @obj: Object the view is of. | |
2872 | * @view: The view in question. | |
2873 | * | |
2874 | * @return The size of the GGTT view in bytes. | |
2875 | */ | |
2876 | size_t | |
2877 | i915_ggtt_view_size(struct drm_i915_gem_object *obj, | |
2878 | const struct i915_ggtt_view *view) | |
2879 | { | |
9e759ff1 | 2880 | if (view->type == I915_GGTT_VIEW_NORMAL) { |
91e6711e | 2881 | return obj->base.size; |
9e759ff1 TU |
2882 | } else if (view->type == I915_GGTT_VIEW_ROTATED) { |
2883 | return view->rotation_info.size; | |
8bd7ef16 JL |
2884 | } else if (view->type == I915_GGTT_VIEW_PARTIAL) { |
2885 | return view->params.partial.size << PAGE_SHIFT; | |
91e6711e JL |
2886 | } else { |
2887 | WARN_ONCE(1, "GGTT view %u not implemented!\n", view->type); | |
2888 | return obj->base.size; | |
2889 | } | |
2890 | } |