Commit | Line | Data |
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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
760285e7 DH |
25 | #include <drm/drmP.h> |
26 | #include <drm/i915_drm.h> | |
76aaf220 DV |
27 | #include "i915_drv.h" |
28 | #include "i915_trace.h" | |
29 | #include "intel_drv.h" | |
30 | ||
6670a5a5 BW |
31 | #define GEN6_PPGTT_PD_ENTRIES 512 |
32 | #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t)) | |
d31eb10e | 33 | typedef uint64_t gen8_gtt_pte_t; |
37aca44a | 34 | typedef gen8_gtt_pte_t gen8_ppgtt_pde_t; |
6670a5a5 | 35 | |
26b1ff35 BW |
36 | /* PPGTT stuff */ |
37 | #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) | |
0d8ff15e | 38 | #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) |
26b1ff35 BW |
39 | |
40 | #define GEN6_PDE_VALID (1 << 0) | |
41 | /* gen6+ has bit 11-4 for physical addr bit 39-32 */ | |
42 | #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
43 | ||
44 | #define GEN6_PTE_VALID (1 << 0) | |
45 | #define GEN6_PTE_UNCACHED (1 << 1) | |
46 | #define HSW_PTE_UNCACHED (0) | |
47 | #define GEN6_PTE_CACHE_LLC (2 << 1) | |
350ec881 | 48 | #define GEN7_PTE_CACHE_L3_LLC (3 << 1) |
26b1ff35 | 49 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) |
0d8ff15e BW |
50 | #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) |
51 | ||
52 | /* Cacheability Control is a 4-bit value. The low three bits are stored in * | |
53 | * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. | |
54 | */ | |
55 | #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ | |
56 | (((bits) & 0x8) << (11 - 3))) | |
87a6b688 | 57 | #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) |
0d8ff15e | 58 | #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) |
4d15c145 | 59 | #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) |
651d794f | 60 | #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) |
26b1ff35 | 61 | |
37aca44a BW |
62 | #define GEN8_PDES_PER_PAGE (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t)) |
63 | #define GEN8_LEGACY_PDPS 4 | |
64 | ||
fbe5d36e BW |
65 | #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) |
66 | #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ | |
67 | #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ | |
68 | #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ | |
69 | ||
94ec8f61 BW |
70 | static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr, |
71 | enum i915_cache_level level, | |
72 | bool valid) | |
73 | { | |
74 | gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; | |
75 | pte |= addr; | |
fbe5d36e BW |
76 | if (level != I915_CACHE_NONE) |
77 | pte |= PPAT_CACHED_INDEX; | |
78 | else | |
79 | pte |= PPAT_UNCACHED_INDEX; | |
94ec8f61 BW |
80 | return pte; |
81 | } | |
82 | ||
350ec881 | 83 | static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr, |
b35b380e BW |
84 | enum i915_cache_level level, |
85 | bool valid) | |
54d12527 | 86 | { |
b35b380e | 87 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
54d12527 | 88 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
89 | |
90 | switch (level) { | |
350ec881 CW |
91 | case I915_CACHE_L3_LLC: |
92 | case I915_CACHE_LLC: | |
93 | pte |= GEN6_PTE_CACHE_LLC; | |
94 | break; | |
95 | case I915_CACHE_NONE: | |
96 | pte |= GEN6_PTE_UNCACHED; | |
97 | break; | |
98 | default: | |
99 | WARN_ON(1); | |
100 | } | |
101 | ||
102 | return pte; | |
103 | } | |
104 | ||
105 | static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr, | |
b35b380e BW |
106 | enum i915_cache_level level, |
107 | bool valid) | |
350ec881 | 108 | { |
b35b380e | 109 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
350ec881 CW |
110 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
111 | ||
112 | switch (level) { | |
113 | case I915_CACHE_L3_LLC: | |
114 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
115 | break; |
116 | case I915_CACHE_LLC: | |
117 | pte |= GEN6_PTE_CACHE_LLC; | |
118 | break; | |
119 | case I915_CACHE_NONE: | |
9119708c | 120 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
121 | break; |
122 | default: | |
350ec881 | 123 | WARN_ON(1); |
e7210c3c BW |
124 | } |
125 | ||
54d12527 BW |
126 | return pte; |
127 | } | |
128 | ||
93c34e70 KG |
129 | #define BYT_PTE_WRITEABLE (1 << 1) |
130 | #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) | |
131 | ||
80a74f7f | 132 | static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr, |
b35b380e BW |
133 | enum i915_cache_level level, |
134 | bool valid) | |
93c34e70 | 135 | { |
b35b380e | 136 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
93c34e70 KG |
137 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
138 | ||
139 | /* Mark the page as writeable. Other platforms don't have a | |
140 | * setting for read-only/writable, so this matches that behavior. | |
141 | */ | |
142 | pte |= BYT_PTE_WRITEABLE; | |
143 | ||
144 | if (level != I915_CACHE_NONE) | |
145 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
146 | ||
147 | return pte; | |
148 | } | |
149 | ||
80a74f7f | 150 | static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr, |
b35b380e BW |
151 | enum i915_cache_level level, |
152 | bool valid) | |
9119708c | 153 | { |
b35b380e | 154 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
0d8ff15e | 155 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
156 | |
157 | if (level != I915_CACHE_NONE) | |
87a6b688 | 158 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
159 | |
160 | return pte; | |
161 | } | |
162 | ||
4d15c145 | 163 | static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr, |
b35b380e BW |
164 | enum i915_cache_level level, |
165 | bool valid) | |
4d15c145 | 166 | { |
b35b380e | 167 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4d15c145 BW |
168 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
169 | ||
651d794f CW |
170 | switch (level) { |
171 | case I915_CACHE_NONE: | |
172 | break; | |
173 | case I915_CACHE_WT: | |
174 | pte |= HSW_WT_ELLC_LLC_AGE0; | |
175 | break; | |
176 | default: | |
4d15c145 | 177 | pte |= HSW_WB_ELLC_LLC_AGE0; |
651d794f CW |
178 | break; |
179 | } | |
4d15c145 BW |
180 | |
181 | return pte; | |
182 | } | |
183 | ||
37aca44a BW |
184 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) |
185 | { | |
186 | struct i915_hw_ppgtt *ppgtt = | |
187 | container_of(vm, struct i915_hw_ppgtt, base); | |
188 | int i, j; | |
189 | ||
190 | for (i = 0; i < ppgtt->num_pd_pages ; i++) { | |
191 | if (ppgtt->pd_dma_addr[i]) { | |
192 | pci_unmap_page(ppgtt->base.dev->pdev, | |
193 | ppgtt->pd_dma_addr[i], | |
194 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
195 | ||
196 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
197 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; | |
198 | if (addr) | |
199 | pci_unmap_page(ppgtt->base.dev->pdev, | |
200 | addr, | |
201 | PAGE_SIZE, | |
202 | PCI_DMA_BIDIRECTIONAL); | |
203 | ||
204 | } | |
205 | } | |
206 | kfree(ppgtt->gen8_pt_dma_addr[i]); | |
207 | } | |
208 | ||
209 | __free_pages(ppgtt->gen8_pt_pages, ppgtt->num_pt_pages << PAGE_SHIFT); | |
210 | __free_pages(ppgtt->pd_pages, ppgtt->num_pd_pages << PAGE_SHIFT); | |
211 | } | |
212 | ||
213 | /** | |
214 | * GEN8 legacy ppgtt programming is accomplished through 4 PDP registers with a | |
215 | * net effect resembling a 2-level page table in normal x86 terms. Each PDP | |
216 | * represents 1GB of memory | |
217 | * 4 * 512 * 512 * 4096 = 4GB legacy 32b address space. | |
218 | * | |
219 | * TODO: Do something with the size parameter | |
220 | **/ | |
221 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) | |
222 | { | |
223 | struct page *pt_pages; | |
224 | int i, j, ret = -ENOMEM; | |
225 | const int max_pdp = DIV_ROUND_UP(size, 1 << 30); | |
226 | const int num_pt_pages = GEN8_PDES_PER_PAGE * max_pdp; | |
227 | ||
228 | if (size % (1<<30)) | |
229 | DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size); | |
230 | ||
231 | /* FIXME: split allocation into smaller pieces. For now we only ever do | |
232 | * this once, but with full PPGTT, the multiple contiguous allocations | |
233 | * will be bad. | |
234 | */ | |
235 | ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT)); | |
236 | if (!ppgtt->pd_pages) | |
237 | return -ENOMEM; | |
238 | ||
239 | pt_pages = alloc_pages(GFP_KERNEL, get_order(num_pt_pages << PAGE_SHIFT)); | |
240 | if (!pt_pages) { | |
241 | __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT)); | |
242 | return -ENOMEM; | |
243 | } | |
244 | ||
245 | ppgtt->gen8_pt_pages = pt_pages; | |
246 | ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT); | |
247 | ppgtt->num_pt_pages = 1 << get_order(num_pt_pages << PAGE_SHIFT); | |
248 | ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE; | |
249 | ppgtt->base.clear_range = NULL; | |
250 | ppgtt->base.insert_entries = NULL; | |
251 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; | |
252 | ||
253 | BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS); | |
254 | ||
255 | /* | |
256 | * - Create a mapping for the page directories. | |
257 | * - For each page directory: | |
258 | * allocate space for page table mappings. | |
259 | * map each page table | |
260 | */ | |
261 | for (i = 0; i < max_pdp; i++) { | |
262 | dma_addr_t temp; | |
263 | temp = pci_map_page(ppgtt->base.dev->pdev, | |
264 | &ppgtt->pd_pages[i], 0, | |
265 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
266 | if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp)) | |
267 | goto err_out; | |
268 | ||
269 | ppgtt->pd_dma_addr[i] = temp; | |
270 | ||
271 | ppgtt->gen8_pt_dma_addr[i] = kmalloc(sizeof(dma_addr_t) * GEN8_PDES_PER_PAGE, GFP_KERNEL); | |
272 | if (!ppgtt->gen8_pt_dma_addr[i]) | |
273 | goto err_out; | |
274 | ||
275 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
276 | struct page *p = &pt_pages[i * GEN8_PDES_PER_PAGE + j]; | |
277 | temp = pci_map_page(ppgtt->base.dev->pdev, | |
278 | p, 0, PAGE_SIZE, | |
279 | PCI_DMA_BIDIRECTIONAL); | |
280 | ||
281 | if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp)) | |
282 | goto err_out; | |
283 | ||
284 | ppgtt->gen8_pt_dma_addr[i][j] = temp; | |
285 | } | |
286 | } | |
287 | ||
288 | DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n", | |
289 | ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp); | |
290 | DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n", | |
291 | ppgtt->num_pt_pages, | |
292 | (ppgtt->num_pt_pages - num_pt_pages) + | |
293 | size % (1<<30)); | |
294 | return -ENOSYS; /* Not ready yet */ | |
295 | ||
296 | err_out: | |
297 | ppgtt->base.cleanup(&ppgtt->base); | |
298 | return ret; | |
299 | } | |
300 | ||
3e302542 | 301 | static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt) |
6197349b | 302 | { |
853ba5d2 | 303 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; |
6197349b BW |
304 | gen6_gtt_pte_t __iomem *pd_addr; |
305 | uint32_t pd_entry; | |
306 | int i; | |
307 | ||
0a732870 | 308 | WARN_ON(ppgtt->pd_offset & 0x3f); |
6197349b BW |
309 | pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm + |
310 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
311 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
312 | dma_addr_t pt_addr; | |
313 | ||
314 | pt_addr = ppgtt->pt_dma_addr[i]; | |
315 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
316 | pd_entry |= GEN6_PDE_VALID; | |
317 | ||
318 | writel(pd_entry, pd_addr + i); | |
319 | } | |
320 | readl(pd_addr); | |
3e302542 BW |
321 | } |
322 | ||
323 | static int gen6_ppgtt_enable(struct drm_device *dev) | |
324 | { | |
325 | drm_i915_private_t *dev_priv = dev->dev_private; | |
326 | uint32_t pd_offset; | |
327 | struct intel_ring_buffer *ring; | |
328 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
329 | int i; | |
330 | ||
331 | BUG_ON(ppgtt->pd_offset & 0x3f); | |
332 | ||
333 | gen6_write_pdes(ppgtt); | |
6197349b BW |
334 | |
335 | pd_offset = ppgtt->pd_offset; | |
336 | pd_offset /= 64; /* in cachelines, */ | |
337 | pd_offset <<= 16; | |
338 | ||
339 | if (INTEL_INFO(dev)->gen == 6) { | |
340 | uint32_t ecochk, gab_ctl, ecobits; | |
341 | ||
342 | ecobits = I915_READ(GAC_ECO_BITS); | |
3b9d7888 VS |
343 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | |
344 | ECOBITS_PPGTT_CACHE64B); | |
6197349b BW |
345 | |
346 | gab_ctl = I915_READ(GAB_CTL); | |
347 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
348 | ||
349 | ecochk = I915_READ(GAM_ECOCHK); | |
350 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | | |
351 | ECOCHK_PPGTT_CACHE64B); | |
352 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
353 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
a6f429a5 | 354 | uint32_t ecochk, ecobits; |
a65c2fcd VS |
355 | |
356 | ecobits = I915_READ(GAC_ECO_BITS); | |
357 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
358 | ||
a6f429a5 VS |
359 | ecochk = I915_READ(GAM_ECOCHK); |
360 | if (IS_HASWELL(dev)) { | |
361 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
362 | } else { | |
363 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
364 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
365 | } | |
366 | I915_WRITE(GAM_ECOCHK, ecochk); | |
6197349b BW |
367 | /* GFX_MODE is per-ring on gen7+ */ |
368 | } | |
369 | ||
370 | for_each_ring(ring, dev_priv, i) { | |
371 | if (INTEL_INFO(dev)->gen >= 7) | |
372 | I915_WRITE(RING_MODE_GEN7(ring), | |
373 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
374 | ||
375 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
376 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); | |
377 | } | |
b7c36d25 | 378 | return 0; |
6197349b BW |
379 | } |
380 | ||
1d2a314c | 381 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 382 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
1d2a314c | 383 | unsigned first_entry, |
828c7908 BW |
384 | unsigned num_entries, |
385 | bool use_scratch) | |
1d2a314c | 386 | { |
853ba5d2 BW |
387 | struct i915_hw_ppgtt *ppgtt = |
388 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 389 | gen6_gtt_pte_t *pt_vaddr, scratch_pte; |
a15326a5 | 390 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
7bddb01f DV |
391 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
392 | unsigned last_pte, i; | |
1d2a314c | 393 | |
b35b380e | 394 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true); |
1d2a314c | 395 | |
7bddb01f DV |
396 | while (num_entries) { |
397 | last_pte = first_pte + num_entries; | |
398 | if (last_pte > I915_PPGTT_PT_ENTRIES) | |
399 | last_pte = I915_PPGTT_PT_ENTRIES; | |
400 | ||
a15326a5 | 401 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
1d2a314c | 402 | |
7bddb01f DV |
403 | for (i = first_pte; i < last_pte; i++) |
404 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
405 | |
406 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 407 | |
7bddb01f DV |
408 | num_entries -= last_pte - first_pte; |
409 | first_pte = 0; | |
a15326a5 | 410 | act_pt++; |
7bddb01f | 411 | } |
1d2a314c DV |
412 | } |
413 | ||
853ba5d2 | 414 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 DV |
415 | struct sg_table *pages, |
416 | unsigned first_entry, | |
417 | enum i915_cache_level cache_level) | |
418 | { | |
853ba5d2 BW |
419 | struct i915_hw_ppgtt *ppgtt = |
420 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 421 | gen6_gtt_pte_t *pt_vaddr; |
a15326a5 | 422 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
6e995e23 ID |
423 | unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
424 | struct sg_page_iter sg_iter; | |
425 | ||
a15326a5 | 426 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
6e995e23 ID |
427 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
428 | dma_addr_t page_addr; | |
429 | ||
2db76d7c | 430 | page_addr = sg_page_iter_dma_address(&sg_iter); |
b35b380e | 431 | pt_vaddr[act_pte] = vm->pte_encode(page_addr, cache_level, true); |
6e995e23 ID |
432 | if (++act_pte == I915_PPGTT_PT_ENTRIES) { |
433 | kunmap_atomic(pt_vaddr); | |
a15326a5 DV |
434 | act_pt++; |
435 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); | |
6e995e23 | 436 | act_pte = 0; |
def886c3 | 437 | |
def886c3 | 438 | } |
def886c3 | 439 | } |
6e995e23 | 440 | kunmap_atomic(pt_vaddr); |
def886c3 DV |
441 | } |
442 | ||
853ba5d2 | 443 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
1d2a314c | 444 | { |
853ba5d2 BW |
445 | struct i915_hw_ppgtt *ppgtt = |
446 | container_of(vm, struct i915_hw_ppgtt, base); | |
3440d265 DV |
447 | int i; |
448 | ||
93bd8649 BW |
449 | drm_mm_takedown(&ppgtt->base.mm); |
450 | ||
3440d265 DV |
451 | if (ppgtt->pt_dma_addr) { |
452 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
853ba5d2 | 453 | pci_unmap_page(ppgtt->base.dev->pdev, |
3440d265 DV |
454 | ppgtt->pt_dma_addr[i], |
455 | 4096, PCI_DMA_BIDIRECTIONAL); | |
456 | } | |
457 | ||
458 | kfree(ppgtt->pt_dma_addr); | |
459 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
460 | __free_page(ppgtt->pt_pages[i]); | |
461 | kfree(ppgtt->pt_pages); | |
462 | kfree(ppgtt); | |
463 | } | |
464 | ||
465 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) | |
466 | { | |
853ba5d2 | 467 | struct drm_device *dev = ppgtt->base.dev; |
1d2a314c | 468 | struct drm_i915_private *dev_priv = dev->dev_private; |
1d2a314c | 469 | unsigned first_pd_entry_in_global_pt; |
1d2a314c DV |
470 | int i; |
471 | int ret = -ENOMEM; | |
472 | ||
473 | /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024 | |
474 | * entries. For aliasing ppgtt support we just steal them at the end for | |
475 | * now. */ | |
e1b73cba | 476 | first_pd_entry_in_global_pt = gtt_total_entries(dev_priv->gtt); |
1d2a314c | 477 | |
08c45263 | 478 | ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; |
6670a5a5 | 479 | ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES; |
6197349b | 480 | ppgtt->enable = gen6_ppgtt_enable; |
853ba5d2 BW |
481 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
482 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
483 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; | |
484 | ppgtt->base.scratch = dev_priv->gtt.base.scratch; | |
a1e22653 | 485 | ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *), |
1d2a314c DV |
486 | GFP_KERNEL); |
487 | if (!ppgtt->pt_pages) | |
3440d265 | 488 | return -ENOMEM; |
1d2a314c DV |
489 | |
490 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
491 | ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL); | |
492 | if (!ppgtt->pt_pages[i]) | |
493 | goto err_pt_alloc; | |
494 | } | |
495 | ||
a1e22653 | 496 | ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t), |
8d2e6308 BW |
497 | GFP_KERNEL); |
498 | if (!ppgtt->pt_dma_addr) | |
499 | goto err_pt_alloc; | |
1d2a314c | 500 | |
8d2e6308 BW |
501 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
502 | dma_addr_t pt_addr; | |
211c568b | 503 | |
8d2e6308 BW |
504 | pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096, |
505 | PCI_DMA_BIDIRECTIONAL); | |
1d2a314c | 506 | |
8d2e6308 BW |
507 | if (pci_dma_mapping_error(dev->pdev, pt_addr)) { |
508 | ret = -EIO; | |
509 | goto err_pd_pin; | |
1d2a314c | 510 | |
211c568b | 511 | } |
8d2e6308 | 512 | ppgtt->pt_dma_addr[i] = pt_addr; |
1d2a314c | 513 | } |
1d2a314c | 514 | |
853ba5d2 | 515 | ppgtt->base.clear_range(&ppgtt->base, 0, |
828c7908 | 516 | ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES, true); |
1d2a314c | 517 | |
e7c2b58b | 518 | ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t); |
1d2a314c | 519 | |
1d2a314c DV |
520 | return 0; |
521 | ||
522 | err_pd_pin: | |
523 | if (ppgtt->pt_dma_addr) { | |
524 | for (i--; i >= 0; i--) | |
525 | pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i], | |
526 | 4096, PCI_DMA_BIDIRECTIONAL); | |
527 | } | |
528 | err_pt_alloc: | |
529 | kfree(ppgtt->pt_dma_addr); | |
530 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
531 | if (ppgtt->pt_pages[i]) | |
532 | __free_page(ppgtt->pt_pages[i]); | |
533 | } | |
534 | kfree(ppgtt->pt_pages); | |
3440d265 DV |
535 | |
536 | return ret; | |
537 | } | |
538 | ||
539 | static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev) | |
540 | { | |
541 | struct drm_i915_private *dev_priv = dev->dev_private; | |
542 | struct i915_hw_ppgtt *ppgtt; | |
543 | int ret; | |
544 | ||
545 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
546 | if (!ppgtt) | |
547 | return -ENOMEM; | |
548 | ||
853ba5d2 | 549 | ppgtt->base.dev = dev; |
3440d265 | 550 | |
3ed124b2 BW |
551 | if (INTEL_INFO(dev)->gen < 8) |
552 | ret = gen6_ppgtt_init(ppgtt); | |
8fe6bd23 | 553 | else if (IS_GEN8(dev)) |
37aca44a | 554 | ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total); |
3ed124b2 BW |
555 | else |
556 | BUG(); | |
557 | ||
3440d265 DV |
558 | if (ret) |
559 | kfree(ppgtt); | |
93bd8649 | 560 | else { |
3440d265 | 561 | dev_priv->mm.aliasing_ppgtt = ppgtt; |
93bd8649 BW |
562 | drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, |
563 | ppgtt->base.total); | |
564 | } | |
1d2a314c DV |
565 | |
566 | return ret; | |
567 | } | |
568 | ||
569 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev) | |
570 | { | |
571 | struct drm_i915_private *dev_priv = dev->dev_private; | |
572 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1d2a314c DV |
573 | |
574 | if (!ppgtt) | |
575 | return; | |
576 | ||
853ba5d2 | 577 | ppgtt->base.cleanup(&ppgtt->base); |
5963cf04 | 578 | dev_priv->mm.aliasing_ppgtt = NULL; |
1d2a314c DV |
579 | } |
580 | ||
7bddb01f DV |
581 | void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, |
582 | struct drm_i915_gem_object *obj, | |
583 | enum i915_cache_level cache_level) | |
584 | { | |
853ba5d2 BW |
585 | ppgtt->base.insert_entries(&ppgtt->base, obj->pages, |
586 | i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT, | |
587 | cache_level); | |
7bddb01f DV |
588 | } |
589 | ||
590 | void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, | |
591 | struct drm_i915_gem_object *obj) | |
592 | { | |
853ba5d2 BW |
593 | ppgtt->base.clear_range(&ppgtt->base, |
594 | i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT, | |
828c7908 BW |
595 | obj->base.size >> PAGE_SHIFT, |
596 | true); | |
7bddb01f DV |
597 | } |
598 | ||
a81cc00c BW |
599 | extern int intel_iommu_gfx_mapped; |
600 | /* Certain Gen5 chipsets require require idling the GPU before | |
601 | * unmapping anything from the GTT when VT-d is enabled. | |
602 | */ | |
603 | static inline bool needs_idle_maps(struct drm_device *dev) | |
604 | { | |
605 | #ifdef CONFIG_INTEL_IOMMU | |
606 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
607 | * was loaded first. | |
608 | */ | |
609 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
610 | return true; | |
611 | #endif | |
612 | return false; | |
613 | } | |
614 | ||
5c042287 BW |
615 | static bool do_idling(struct drm_i915_private *dev_priv) |
616 | { | |
617 | bool ret = dev_priv->mm.interruptible; | |
618 | ||
a81cc00c | 619 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 620 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 621 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
622 | DRM_ERROR("Couldn't idle GPU\n"); |
623 | /* Wait a bit, in hopes it avoids the hang */ | |
624 | udelay(10); | |
625 | } | |
626 | } | |
627 | ||
628 | return ret; | |
629 | } | |
630 | ||
631 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
632 | { | |
a81cc00c | 633 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
634 | dev_priv->mm.interruptible = interruptible; |
635 | } | |
636 | ||
828c7908 BW |
637 | void i915_check_and_clear_faults(struct drm_device *dev) |
638 | { | |
639 | struct drm_i915_private *dev_priv = dev->dev_private; | |
640 | struct intel_ring_buffer *ring; | |
641 | int i; | |
642 | ||
643 | if (INTEL_INFO(dev)->gen < 6) | |
644 | return; | |
645 | ||
646 | for_each_ring(ring, dev_priv, i) { | |
647 | u32 fault_reg; | |
648 | fault_reg = I915_READ(RING_FAULT_REG(ring)); | |
649 | if (fault_reg & RING_FAULT_VALID) { | |
650 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
651 | "\tAddr: 0x%08lx\\n" | |
652 | "\tAddress space: %s\n" | |
653 | "\tSource ID: %d\n" | |
654 | "\tType: %d\n", | |
655 | fault_reg & PAGE_MASK, | |
656 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
657 | RING_FAULT_SRCID(fault_reg), | |
658 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
659 | I915_WRITE(RING_FAULT_REG(ring), | |
660 | fault_reg & ~RING_FAULT_VALID); | |
661 | } | |
662 | } | |
663 | POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); | |
664 | } | |
665 | ||
666 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) | |
667 | { | |
668 | struct drm_i915_private *dev_priv = dev->dev_private; | |
669 | ||
670 | /* Don't bother messing with faults pre GEN6 as we have little | |
671 | * documentation supporting that it's a good idea. | |
672 | */ | |
673 | if (INTEL_INFO(dev)->gen < 6) | |
674 | return; | |
675 | ||
676 | i915_check_and_clear_faults(dev); | |
677 | ||
678 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, | |
679 | dev_priv->gtt.base.start / PAGE_SIZE, | |
680 | dev_priv->gtt.base.total / PAGE_SIZE, | |
681 | false); | |
682 | } | |
683 | ||
76aaf220 DV |
684 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
685 | { | |
686 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 687 | struct drm_i915_gem_object *obj; |
76aaf220 | 688 | |
828c7908 BW |
689 | i915_check_and_clear_faults(dev); |
690 | ||
bee4a186 | 691 | /* First fill our portion of the GTT with scratch pages */ |
853ba5d2 BW |
692 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
693 | dev_priv->gtt.base.start / PAGE_SIZE, | |
828c7908 BW |
694 | dev_priv->gtt.base.total / PAGE_SIZE, |
695 | true); | |
bee4a186 | 696 | |
35c20a60 | 697 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
2c22569b | 698 | i915_gem_clflush_object(obj, obj->pin_display); |
74163907 | 699 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
76aaf220 DV |
700 | } |
701 | ||
e76e9aeb | 702 | i915_gem_chipset_flush(dev); |
76aaf220 | 703 | } |
7c2e6fdf | 704 | |
74163907 | 705 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 706 | { |
9da3da66 | 707 | if (obj->has_dma_mapping) |
74163907 | 708 | return 0; |
9da3da66 CW |
709 | |
710 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
711 | obj->pages->sgl, obj->pages->nents, | |
712 | PCI_DMA_BIDIRECTIONAL)) | |
713 | return -ENOSPC; | |
714 | ||
715 | return 0; | |
7c2e6fdf DV |
716 | } |
717 | ||
94ec8f61 BW |
718 | static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte) |
719 | { | |
720 | #ifdef writeq | |
721 | writeq(pte, addr); | |
722 | #else | |
723 | iowrite32((u32)pte, addr); | |
724 | iowrite32(pte >> 32, addr + 4); | |
725 | #endif | |
726 | } | |
727 | ||
728 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, | |
729 | struct sg_table *st, | |
730 | unsigned int first_entry, | |
731 | enum i915_cache_level level) | |
732 | { | |
733 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
734 | gen8_gtt_pte_t __iomem *gtt_entries = | |
735 | (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
736 | int i = 0; | |
737 | struct sg_page_iter sg_iter; | |
738 | dma_addr_t addr; | |
739 | ||
740 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { | |
741 | addr = sg_dma_address(sg_iter.sg) + | |
742 | (sg_iter.sg_pgoffset << PAGE_SHIFT); | |
743 | gen8_set_pte(>t_entries[i], | |
744 | gen8_pte_encode(addr, level, true)); | |
745 | i++; | |
746 | } | |
747 | ||
748 | /* | |
749 | * XXX: This serves as a posting read to make sure that the PTE has | |
750 | * actually been updated. There is some concern that even though | |
751 | * registers and PTEs are within the same BAR that they are potentially | |
752 | * of NUMA access patterns. Therefore, even with the way we assume | |
753 | * hardware should work, we must keep this posting read for paranoia. | |
754 | */ | |
755 | if (i != 0) | |
756 | WARN_ON(readq(>t_entries[i-1]) | |
757 | != gen8_pte_encode(addr, level, true)); | |
758 | ||
759 | #if 0 /* TODO: Still needed on GEN8? */ | |
760 | /* This next bit makes the above posting read even more important. We | |
761 | * want to flush the TLBs only after we're certain all the PTE updates | |
762 | * have finished. | |
763 | */ | |
764 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
765 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
766 | #endif | |
767 | } | |
768 | ||
e76e9aeb BW |
769 | /* |
770 | * Binds an object into the global gtt with the specified cache level. The object | |
771 | * will be accessible to the GPU via commands whose operands reference offsets | |
772 | * within the global GTT as well as accessible by the GPU through the GMADR | |
773 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
774 | */ | |
853ba5d2 | 775 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 DV |
776 | struct sg_table *st, |
777 | unsigned int first_entry, | |
778 | enum i915_cache_level level) | |
e76e9aeb | 779 | { |
853ba5d2 | 780 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
e7c2b58b BW |
781 | gen6_gtt_pte_t __iomem *gtt_entries = |
782 | (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
783 | int i = 0; |
784 | struct sg_page_iter sg_iter; | |
e76e9aeb BW |
785 | dma_addr_t addr; |
786 | ||
6e995e23 | 787 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 788 | addr = sg_page_iter_dma_address(&sg_iter); |
b35b380e | 789 | iowrite32(vm->pte_encode(addr, level, true), >t_entries[i]); |
6e995e23 | 790 | i++; |
e76e9aeb BW |
791 | } |
792 | ||
e76e9aeb BW |
793 | /* XXX: This serves as a posting read to make sure that the PTE has |
794 | * actually been updated. There is some concern that even though | |
795 | * registers and PTEs are within the same BAR that they are potentially | |
796 | * of NUMA access patterns. Therefore, even with the way we assume | |
797 | * hardware should work, we must keep this posting read for paranoia. | |
798 | */ | |
799 | if (i != 0) | |
853ba5d2 | 800 | WARN_ON(readl(>t_entries[i-1]) != |
b35b380e | 801 | vm->pte_encode(addr, level, true)); |
0f9b91c7 BW |
802 | |
803 | /* This next bit makes the above posting read even more important. We | |
804 | * want to flush the TLBs only after we're certain all the PTE updates | |
805 | * have finished. | |
806 | */ | |
807 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
808 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
809 | } |
810 | ||
94ec8f61 BW |
811 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
812 | unsigned int first_entry, | |
813 | unsigned int num_entries, | |
814 | bool use_scratch) | |
815 | { | |
816 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
817 | gen8_gtt_pte_t scratch_pte, __iomem *gtt_base = | |
818 | (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
819 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; | |
820 | int i; | |
821 | ||
822 | if (WARN(num_entries > max_entries, | |
823 | "First entry = %d; Num entries = %d (max=%d)\n", | |
824 | first_entry, num_entries, max_entries)) | |
825 | num_entries = max_entries; | |
826 | ||
827 | scratch_pte = gen8_pte_encode(vm->scratch.addr, | |
828 | I915_CACHE_LLC, | |
829 | use_scratch); | |
830 | for (i = 0; i < num_entries; i++) | |
831 | gen8_set_pte(>t_base[i], scratch_pte); | |
832 | readl(gtt_base); | |
833 | } | |
834 | ||
853ba5d2 | 835 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
7faf1ab2 | 836 | unsigned int first_entry, |
828c7908 BW |
837 | unsigned int num_entries, |
838 | bool use_scratch) | |
7faf1ab2 | 839 | { |
853ba5d2 | 840 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
e7c2b58b BW |
841 | gen6_gtt_pte_t scratch_pte, __iomem *gtt_base = |
842 | (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 843 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
844 | int i; |
845 | ||
846 | if (WARN(num_entries > max_entries, | |
847 | "First entry = %d; Num entries = %d (max=%d)\n", | |
848 | first_entry, num_entries, max_entries)) | |
849 | num_entries = max_entries; | |
850 | ||
828c7908 BW |
851 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch); |
852 | ||
7faf1ab2 DV |
853 | for (i = 0; i < num_entries; i++) |
854 | iowrite32(scratch_pte, >t_base[i]); | |
855 | readl(gtt_base); | |
856 | } | |
857 | ||
853ba5d2 | 858 | static void i915_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 DV |
859 | struct sg_table *st, |
860 | unsigned int pg_start, | |
861 | enum i915_cache_level cache_level) | |
862 | { | |
863 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? | |
864 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
865 | ||
866 | intel_gtt_insert_sg_entries(st, pg_start, flags); | |
867 | ||
868 | } | |
869 | ||
853ba5d2 | 870 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
7faf1ab2 | 871 | unsigned int first_entry, |
828c7908 BW |
872 | unsigned int num_entries, |
873 | bool unused) | |
7faf1ab2 DV |
874 | { |
875 | intel_gtt_clear_range(first_entry, num_entries); | |
876 | } | |
877 | ||
878 | ||
74163907 DV |
879 | void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, |
880 | enum i915_cache_level cache_level) | |
d5bd1449 CW |
881 | { |
882 | struct drm_device *dev = obj->base.dev; | |
7faf1ab2 | 883 | struct drm_i915_private *dev_priv = dev->dev_private; |
853ba5d2 | 884 | const unsigned long entry = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT; |
7faf1ab2 | 885 | |
853ba5d2 BW |
886 | dev_priv->gtt.base.insert_entries(&dev_priv->gtt.base, obj->pages, |
887 | entry, | |
888 | cache_level); | |
d5bd1449 | 889 | |
74898d7e | 890 | obj->has_global_gtt_mapping = 1; |
d5bd1449 CW |
891 | } |
892 | ||
05394f39 | 893 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj) |
74163907 | 894 | { |
7faf1ab2 DV |
895 | struct drm_device *dev = obj->base.dev; |
896 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 | 897 | const unsigned long entry = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT; |
7faf1ab2 | 898 | |
853ba5d2 BW |
899 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
900 | entry, | |
828c7908 BW |
901 | obj->base.size >> PAGE_SHIFT, |
902 | true); | |
74898d7e DV |
903 | |
904 | obj->has_global_gtt_mapping = 0; | |
74163907 DV |
905 | } |
906 | ||
907 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 908 | { |
5c042287 BW |
909 | struct drm_device *dev = obj->base.dev; |
910 | struct drm_i915_private *dev_priv = dev->dev_private; | |
911 | bool interruptible; | |
912 | ||
913 | interruptible = do_idling(dev_priv); | |
914 | ||
9da3da66 CW |
915 | if (!obj->has_dma_mapping) |
916 | dma_unmap_sg(&dev->pdev->dev, | |
917 | obj->pages->sgl, obj->pages->nents, | |
918 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
919 | |
920 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 921 | } |
644ec02b | 922 | |
42d6ab48 CW |
923 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
924 | unsigned long color, | |
925 | unsigned long *start, | |
926 | unsigned long *end) | |
927 | { | |
928 | if (node->color != color) | |
929 | *start += 4096; | |
930 | ||
931 | if (!list_empty(&node->node_list)) { | |
932 | node = list_entry(node->node_list.next, | |
933 | struct drm_mm_node, | |
934 | node_list); | |
935 | if (node->allocated && node->color != color) | |
936 | *end -= 4096; | |
937 | } | |
938 | } | |
fbe5d36e | 939 | |
d7e5008f BW |
940 | void i915_gem_setup_global_gtt(struct drm_device *dev, |
941 | unsigned long start, | |
942 | unsigned long mappable_end, | |
943 | unsigned long end) | |
644ec02b | 944 | { |
e78891ca BW |
945 | /* Let GEM Manage all of the aperture. |
946 | * | |
947 | * However, leave one page at the end still bound to the scratch page. | |
948 | * There are a number of places where the hardware apparently prefetches | |
949 | * past the end of the object, and we've seen multiple hangs with the | |
950 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
951 | * aperture. One page should be enough to keep any prefetching inside | |
952 | * of the aperture. | |
953 | */ | |
40d74980 BW |
954 | struct drm_i915_private *dev_priv = dev->dev_private; |
955 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; | |
ed2f3452 CW |
956 | struct drm_mm_node *entry; |
957 | struct drm_i915_gem_object *obj; | |
958 | unsigned long hole_start, hole_end; | |
644ec02b | 959 | |
35451cb6 BW |
960 | BUG_ON(mappable_end > end); |
961 | ||
ed2f3452 | 962 | /* Subtract the guard page ... */ |
40d74980 | 963 | drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); |
42d6ab48 | 964 | if (!HAS_LLC(dev)) |
93bd8649 | 965 | dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; |
644ec02b | 966 | |
ed2f3452 | 967 | /* Mark any preallocated objects as occupied */ |
35c20a60 | 968 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
40d74980 | 969 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
b3a070cc | 970 | int ret; |
edd41a87 | 971 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
c6cfb325 BW |
972 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
973 | ||
974 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); | |
40d74980 | 975 | ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); |
c6cfb325 | 976 | if (ret) |
b3a070cc | 977 | DRM_DEBUG_KMS("Reservation failed\n"); |
ed2f3452 | 978 | obj->has_global_gtt_mapping = 1; |
2f633156 | 979 | list_add(&vma->vma_link, &obj->vma_list); |
ed2f3452 CW |
980 | } |
981 | ||
853ba5d2 BW |
982 | dev_priv->gtt.base.start = start; |
983 | dev_priv->gtt.base.total = end - start; | |
644ec02b | 984 | |
ed2f3452 | 985 | /* Clear any non-preallocated blocks */ |
40d74980 | 986 | drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { |
853ba5d2 | 987 | const unsigned long count = (hole_end - hole_start) / PAGE_SIZE; |
ed2f3452 CW |
988 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
989 | hole_start, hole_end); | |
828c7908 | 990 | ggtt_vm->clear_range(ggtt_vm, hole_start / PAGE_SIZE, count, true); |
ed2f3452 CW |
991 | } |
992 | ||
993 | /* And finally clear the reserved guard page */ | |
828c7908 | 994 | ggtt_vm->clear_range(ggtt_vm, end / PAGE_SIZE - 1, 1, true); |
e76e9aeb BW |
995 | } |
996 | ||
d7e5008f BW |
997 | static bool |
998 | intel_enable_ppgtt(struct drm_device *dev) | |
999 | { | |
1000 | if (i915_enable_ppgtt >= 0) | |
1001 | return i915_enable_ppgtt; | |
1002 | ||
1003 | #ifdef CONFIG_INTEL_IOMMU | |
1004 | /* Disable ppgtt on SNB if VT-d is on. */ | |
1005 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) | |
1006 | return false; | |
1007 | #endif | |
1008 | ||
1009 | return true; | |
1010 | } | |
1011 | ||
1012 | void i915_gem_init_global_gtt(struct drm_device *dev) | |
1013 | { | |
1014 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1015 | unsigned long gtt_size, mappable_size; | |
d7e5008f | 1016 | |
853ba5d2 | 1017 | gtt_size = dev_priv->gtt.base.total; |
93d18799 | 1018 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f BW |
1019 | |
1020 | if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { | |
e78891ca | 1021 | int ret; |
3eb1c005 BW |
1022 | |
1023 | if (INTEL_INFO(dev)->gen <= 7) { | |
1024 | /* PPGTT pdes are stolen from global gtt ptes, so shrink the | |
1025 | * aperture accordingly when using aliasing ppgtt. */ | |
6670a5a5 | 1026 | gtt_size -= GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE; |
3eb1c005 | 1027 | } |
d7e5008f BW |
1028 | |
1029 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); | |
1030 | ||
1031 | ret = i915_gem_init_aliasing_ppgtt(dev); | |
e78891ca | 1032 | if (!ret) |
d7e5008f | 1033 | return; |
e78891ca BW |
1034 | |
1035 | DRM_ERROR("Aliased PPGTT setup failed %d\n", ret); | |
93bd8649 | 1036 | drm_mm_takedown(&dev_priv->gtt.base.mm); |
6670a5a5 | 1037 | gtt_size += GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE; |
d7e5008f | 1038 | } |
e78891ca | 1039 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
1040 | } |
1041 | ||
1042 | static int setup_scratch_page(struct drm_device *dev) | |
1043 | { | |
1044 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1045 | struct page *page; | |
1046 | dma_addr_t dma_addr; | |
1047 | ||
1048 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
1049 | if (page == NULL) | |
1050 | return -ENOMEM; | |
1051 | get_page(page); | |
1052 | set_pages_uc(page, 1); | |
1053 | ||
1054 | #ifdef CONFIG_INTEL_IOMMU | |
1055 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
1056 | PCI_DMA_BIDIRECTIONAL); | |
1057 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) | |
1058 | return -EINVAL; | |
1059 | #else | |
1060 | dma_addr = page_to_phys(page); | |
1061 | #endif | |
853ba5d2 BW |
1062 | dev_priv->gtt.base.scratch.page = page; |
1063 | dev_priv->gtt.base.scratch.addr = dma_addr; | |
e76e9aeb BW |
1064 | |
1065 | return 0; | |
1066 | } | |
1067 | ||
1068 | static void teardown_scratch_page(struct drm_device *dev) | |
1069 | { | |
1070 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 BW |
1071 | struct page *page = dev_priv->gtt.base.scratch.page; |
1072 | ||
1073 | set_pages_wb(page, 1); | |
1074 | pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr, | |
e76e9aeb | 1075 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
853ba5d2 BW |
1076 | put_page(page); |
1077 | __free_page(page); | |
e76e9aeb BW |
1078 | } |
1079 | ||
1080 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) | |
1081 | { | |
1082 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
1083 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
1084 | return snb_gmch_ctl << 20; | |
1085 | } | |
1086 | ||
9459d252 BW |
1087 | static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
1088 | { | |
1089 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
1090 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
1091 | if (bdw_gmch_ctl) | |
1092 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
1093 | return bdw_gmch_ctl << 20; | |
1094 | } | |
1095 | ||
baa09f5f | 1096 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
1097 | { |
1098 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
1099 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
1100 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
1101 | } | |
1102 | ||
9459d252 BW |
1103 | static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
1104 | { | |
1105 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
1106 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
1107 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
1108 | } | |
1109 | ||
63340133 BW |
1110 | static int ggtt_probe_common(struct drm_device *dev, |
1111 | size_t gtt_size) | |
1112 | { | |
1113 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1114 | phys_addr_t gtt_bus_addr; | |
1115 | int ret; | |
1116 | ||
1117 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
1118 | gtt_bus_addr = pci_resource_start(dev->pdev, 0) + | |
1119 | (pci_resource_len(dev->pdev, 0) / 2); | |
1120 | ||
1121 | dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size); | |
1122 | if (!dev_priv->gtt.gsm) { | |
1123 | DRM_ERROR("Failed to map the gtt page table\n"); | |
1124 | return -ENOMEM; | |
1125 | } | |
1126 | ||
1127 | ret = setup_scratch_page(dev); | |
1128 | if (ret) { | |
1129 | DRM_ERROR("Scratch setup failed\n"); | |
1130 | /* iounmap will also get called at remove, but meh */ | |
1131 | iounmap(dev_priv->gtt.gsm); | |
1132 | } | |
1133 | ||
1134 | return ret; | |
1135 | } | |
1136 | ||
fbe5d36e BW |
1137 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
1138 | * bits. When using advanced contexts each context stores its own PAT, but | |
1139 | * writing this data shouldn't be harmful even in those cases. */ | |
1140 | static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv) | |
1141 | { | |
1142 | #define GEN8_PPAT_UC (0<<0) | |
1143 | #define GEN8_PPAT_WC (1<<0) | |
1144 | #define GEN8_PPAT_WT (2<<0) | |
1145 | #define GEN8_PPAT_WB (3<<0) | |
1146 | #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) | |
1147 | /* FIXME(BDW): Bspec is completely confused about cache control bits. */ | |
1148 | #define GEN8_PPAT_LLC (1<<2) | |
1149 | #define GEN8_PPAT_LLCELLC (2<<2) | |
1150 | #define GEN8_PPAT_LLCeLLC (3<<2) | |
1151 | #define GEN8_PPAT_AGE(x) (x<<4) | |
1152 | #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) | |
1153 | uint64_t pat; | |
1154 | ||
1155 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
1156 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
1157 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
1158 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
1159 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
1160 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
1161 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
1162 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
1163 | ||
1164 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b | |
1165 | * write would work. */ | |
1166 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
1167 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
1168 | } | |
1169 | ||
63340133 BW |
1170 | static int gen8_gmch_probe(struct drm_device *dev, |
1171 | size_t *gtt_total, | |
1172 | size_t *stolen, | |
1173 | phys_addr_t *mappable_base, | |
1174 | unsigned long *mappable_end) | |
1175 | { | |
1176 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1177 | unsigned int gtt_size; | |
1178 | u16 snb_gmch_ctl; | |
1179 | int ret; | |
1180 | ||
1181 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
1182 | *mappable_base = pci_resource_start(dev->pdev, 2); | |
1183 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
1184 | ||
1185 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) | |
1186 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); | |
1187 | ||
1188 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
1189 | ||
1190 | *stolen = gen8_get_stolen_size(snb_gmch_ctl); | |
1191 | ||
1192 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
d31eb10e | 1193 | *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT; |
63340133 | 1194 | |
fbe5d36e BW |
1195 | gen8_setup_private_ppat(dev_priv); |
1196 | ||
63340133 BW |
1197 | ret = ggtt_probe_common(dev, gtt_size); |
1198 | ||
94ec8f61 BW |
1199 | dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range; |
1200 | dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries; | |
63340133 BW |
1201 | |
1202 | return ret; | |
1203 | } | |
1204 | ||
baa09f5f BW |
1205 | static int gen6_gmch_probe(struct drm_device *dev, |
1206 | size_t *gtt_total, | |
41907ddc BW |
1207 | size_t *stolen, |
1208 | phys_addr_t *mappable_base, | |
1209 | unsigned long *mappable_end) | |
e76e9aeb BW |
1210 | { |
1211 | struct drm_i915_private *dev_priv = dev->dev_private; | |
baa09f5f | 1212 | unsigned int gtt_size; |
e76e9aeb | 1213 | u16 snb_gmch_ctl; |
e76e9aeb BW |
1214 | int ret; |
1215 | ||
41907ddc BW |
1216 | *mappable_base = pci_resource_start(dev->pdev, 2); |
1217 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
1218 | ||
baa09f5f BW |
1219 | /* 64/512MB is the current min/max we actually know of, but this is just |
1220 | * a coarse sanity check. | |
e76e9aeb | 1221 | */ |
41907ddc | 1222 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
baa09f5f BW |
1223 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
1224 | dev_priv->gtt.mappable_end); | |
1225 | return -ENXIO; | |
e76e9aeb BW |
1226 | } |
1227 | ||
e76e9aeb BW |
1228 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
1229 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 1230 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
e76e9aeb | 1231 | |
63340133 | 1232 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
e76e9aeb | 1233 | |
63340133 BW |
1234 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
1235 | *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT; | |
a93e4161 | 1236 | |
63340133 | 1237 | ret = ggtt_probe_common(dev, gtt_size); |
e76e9aeb | 1238 | |
853ba5d2 BW |
1239 | dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; |
1240 | dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; | |
7faf1ab2 | 1241 | |
e76e9aeb BW |
1242 | return ret; |
1243 | } | |
1244 | ||
853ba5d2 | 1245 | static void gen6_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 1246 | { |
853ba5d2 BW |
1247 | |
1248 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); | |
1249 | iounmap(gtt->gsm); | |
1250 | teardown_scratch_page(vm->dev); | |
644ec02b | 1251 | } |
baa09f5f BW |
1252 | |
1253 | static int i915_gmch_probe(struct drm_device *dev, | |
1254 | size_t *gtt_total, | |
41907ddc BW |
1255 | size_t *stolen, |
1256 | phys_addr_t *mappable_base, | |
1257 | unsigned long *mappable_end) | |
baa09f5f BW |
1258 | { |
1259 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1260 | int ret; | |
1261 | ||
baa09f5f BW |
1262 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
1263 | if (!ret) { | |
1264 | DRM_ERROR("failed to set up gmch\n"); | |
1265 | return -EIO; | |
1266 | } | |
1267 | ||
41907ddc | 1268 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
1269 | |
1270 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
853ba5d2 BW |
1271 | dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; |
1272 | dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries; | |
baa09f5f BW |
1273 | |
1274 | return 0; | |
1275 | } | |
1276 | ||
853ba5d2 | 1277 | static void i915_gmch_remove(struct i915_address_space *vm) |
baa09f5f BW |
1278 | { |
1279 | intel_gmch_remove(); | |
1280 | } | |
1281 | ||
1282 | int i915_gem_gtt_init(struct drm_device *dev) | |
1283 | { | |
1284 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1285 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
1286 | int ret; |
1287 | ||
baa09f5f | 1288 | if (INTEL_INFO(dev)->gen <= 5) { |
b2f21b4d | 1289 | gtt->gtt_probe = i915_gmch_probe; |
853ba5d2 | 1290 | gtt->base.cleanup = i915_gmch_remove; |
63340133 | 1291 | } else if (INTEL_INFO(dev)->gen < 8) { |
b2f21b4d | 1292 | gtt->gtt_probe = gen6_gmch_probe; |
853ba5d2 | 1293 | gtt->base.cleanup = gen6_gmch_remove; |
4d15c145 | 1294 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
853ba5d2 | 1295 | gtt->base.pte_encode = iris_pte_encode; |
4d15c145 | 1296 | else if (IS_HASWELL(dev)) |
853ba5d2 | 1297 | gtt->base.pte_encode = hsw_pte_encode; |
b2f21b4d | 1298 | else if (IS_VALLEYVIEW(dev)) |
853ba5d2 | 1299 | gtt->base.pte_encode = byt_pte_encode; |
350ec881 CW |
1300 | else if (INTEL_INFO(dev)->gen >= 7) |
1301 | gtt->base.pte_encode = ivb_pte_encode; | |
b2f21b4d | 1302 | else |
350ec881 | 1303 | gtt->base.pte_encode = snb_pte_encode; |
63340133 BW |
1304 | } else { |
1305 | dev_priv->gtt.gtt_probe = gen8_gmch_probe; | |
1306 | dev_priv->gtt.base.cleanup = gen6_gmch_remove; | |
baa09f5f BW |
1307 | } |
1308 | ||
853ba5d2 | 1309 | ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, |
b2f21b4d | 1310 | >t->mappable_base, >t->mappable_end); |
a54c0c27 | 1311 | if (ret) |
baa09f5f | 1312 | return ret; |
baa09f5f | 1313 | |
853ba5d2 BW |
1314 | gtt->base.dev = dev; |
1315 | ||
baa09f5f | 1316 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
853ba5d2 BW |
1317 | DRM_INFO("Memory usable by graphics device = %zdM\n", |
1318 | gtt->base.total >> 20); | |
b2f21b4d BW |
1319 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); |
1320 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); | |
baa09f5f BW |
1321 | |
1322 | return 0; | |
1323 | } |