Commit | Line | Data |
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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
760285e7 DH |
25 | #include <drm/drmP.h> |
26 | #include <drm/i915_drm.h> | |
76aaf220 DV |
27 | #include "i915_drv.h" |
28 | #include "i915_trace.h" | |
29 | #include "intel_drv.h" | |
30 | ||
f61c0609 BW |
31 | typedef uint32_t gtt_pte_t; |
32 | ||
26b1ff35 BW |
33 | /* PPGTT stuff */ |
34 | #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) | |
35 | ||
36 | #define GEN6_PDE_VALID (1 << 0) | |
37 | /* gen6+ has bit 11-4 for physical addr bit 39-32 */ | |
38 | #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
39 | ||
40 | #define GEN6_PTE_VALID (1 << 0) | |
41 | #define GEN6_PTE_UNCACHED (1 << 1) | |
42 | #define HSW_PTE_UNCACHED (0) | |
43 | #define GEN6_PTE_CACHE_LLC (2 << 1) | |
44 | #define GEN6_PTE_CACHE_LLC_MLC (3 << 1) | |
45 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
46 | ||
54d12527 BW |
47 | static inline gtt_pte_t pte_encode(struct drm_device *dev, |
48 | dma_addr_t addr, | |
e7210c3c | 49 | enum i915_cache_level level) |
54d12527 BW |
50 | { |
51 | gtt_pte_t pte = GEN6_PTE_VALID; | |
52 | pte |= GEN6_PTE_ADDR_ENCODE(addr); | |
e7210c3c BW |
53 | |
54 | switch (level) { | |
55 | case I915_CACHE_LLC_MLC: | |
56 | /* Haswell doesn't set L3 this way */ | |
57 | if (IS_HASWELL(dev)) | |
58 | pte |= GEN6_PTE_CACHE_LLC; | |
59 | else | |
60 | pte |= GEN6_PTE_CACHE_LLC_MLC; | |
61 | break; | |
62 | case I915_CACHE_LLC: | |
63 | pte |= GEN6_PTE_CACHE_LLC; | |
64 | break; | |
65 | case I915_CACHE_NONE: | |
66 | if (IS_HASWELL(dev)) | |
67 | pte |= HSW_PTE_UNCACHED; | |
68 | else | |
69 | pte |= GEN6_PTE_UNCACHED; | |
70 | break; | |
71 | default: | |
72 | BUG(); | |
73 | } | |
74 | ||
54d12527 BW |
75 | |
76 | return pte; | |
77 | } | |
78 | ||
1d2a314c DV |
79 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
80 | static void i915_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt, | |
81 | unsigned first_entry, | |
82 | unsigned num_entries) | |
83 | { | |
f61c0609 BW |
84 | gtt_pte_t *pt_vaddr; |
85 | gtt_pte_t scratch_pte; | |
7bddb01f DV |
86 | unsigned act_pd = first_entry / I915_PPGTT_PT_ENTRIES; |
87 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; | |
88 | unsigned last_pte, i; | |
1d2a314c | 89 | |
54d12527 | 90 | scratch_pte = pte_encode(ppgtt->dev, ppgtt->scratch_page_dma_addr, |
e7210c3c | 91 | I915_CACHE_LLC); |
1d2a314c | 92 | |
7bddb01f DV |
93 | while (num_entries) { |
94 | last_pte = first_pte + num_entries; | |
95 | if (last_pte > I915_PPGTT_PT_ENTRIES) | |
96 | last_pte = I915_PPGTT_PT_ENTRIES; | |
97 | ||
98 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pd]); | |
1d2a314c | 99 | |
7bddb01f DV |
100 | for (i = first_pte; i < last_pte; i++) |
101 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
102 | |
103 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 104 | |
7bddb01f DV |
105 | num_entries -= last_pte - first_pte; |
106 | first_pte = 0; | |
107 | act_pd++; | |
108 | } | |
1d2a314c DV |
109 | } |
110 | ||
111 | int i915_gem_init_aliasing_ppgtt(struct drm_device *dev) | |
112 | { | |
113 | struct drm_i915_private *dev_priv = dev->dev_private; | |
114 | struct i915_hw_ppgtt *ppgtt; | |
1d2a314c | 115 | unsigned first_pd_entry_in_global_pt; |
1d2a314c DV |
116 | int i; |
117 | int ret = -ENOMEM; | |
118 | ||
119 | /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024 | |
120 | * entries. For aliasing ppgtt support we just steal them at the end for | |
121 | * now. */ | |
9a0f938b | 122 | first_pd_entry_in_global_pt = dev_priv->mm.gtt->gtt_total_entries - I915_PPGTT_PD_ENTRIES; |
1d2a314c DV |
123 | |
124 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
125 | if (!ppgtt) | |
126 | return ret; | |
127 | ||
8f2c59f0 | 128 | ppgtt->dev = dev; |
1d2a314c DV |
129 | ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES; |
130 | ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries, | |
131 | GFP_KERNEL); | |
132 | if (!ppgtt->pt_pages) | |
133 | goto err_ppgtt; | |
134 | ||
135 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
136 | ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL); | |
137 | if (!ppgtt->pt_pages[i]) | |
138 | goto err_pt_alloc; | |
139 | } | |
140 | ||
8d2e6308 BW |
141 | ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t) *ppgtt->num_pd_entries, |
142 | GFP_KERNEL); | |
143 | if (!ppgtt->pt_dma_addr) | |
144 | goto err_pt_alloc; | |
1d2a314c | 145 | |
8d2e6308 BW |
146 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
147 | dma_addr_t pt_addr; | |
211c568b | 148 | |
8d2e6308 BW |
149 | pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096, |
150 | PCI_DMA_BIDIRECTIONAL); | |
1d2a314c | 151 | |
8d2e6308 BW |
152 | if (pci_dma_mapping_error(dev->pdev, pt_addr)) { |
153 | ret = -EIO; | |
154 | goto err_pd_pin; | |
1d2a314c | 155 | |
211c568b | 156 | } |
8d2e6308 | 157 | ppgtt->pt_dma_addr[i] = pt_addr; |
1d2a314c | 158 | } |
1d2a314c | 159 | |
9c61a32d | 160 | ppgtt->scratch_page_dma_addr = dev_priv->gtt.scratch_page_dma; |
1d2a314c DV |
161 | |
162 | i915_ppgtt_clear_range(ppgtt, 0, | |
163 | ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES); | |
164 | ||
f61c0609 | 165 | ppgtt->pd_offset = (first_pd_entry_in_global_pt)*sizeof(gtt_pte_t); |
1d2a314c DV |
166 | |
167 | dev_priv->mm.aliasing_ppgtt = ppgtt; | |
168 | ||
169 | return 0; | |
170 | ||
171 | err_pd_pin: | |
172 | if (ppgtt->pt_dma_addr) { | |
173 | for (i--; i >= 0; i--) | |
174 | pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i], | |
175 | 4096, PCI_DMA_BIDIRECTIONAL); | |
176 | } | |
177 | err_pt_alloc: | |
178 | kfree(ppgtt->pt_dma_addr); | |
179 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
180 | if (ppgtt->pt_pages[i]) | |
181 | __free_page(ppgtt->pt_pages[i]); | |
182 | } | |
183 | kfree(ppgtt->pt_pages); | |
184 | err_ppgtt: | |
185 | kfree(ppgtt); | |
186 | ||
187 | return ret; | |
188 | } | |
189 | ||
190 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev) | |
191 | { | |
192 | struct drm_i915_private *dev_priv = dev->dev_private; | |
193 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
194 | int i; | |
195 | ||
196 | if (!ppgtt) | |
197 | return; | |
198 | ||
199 | if (ppgtt->pt_dma_addr) { | |
200 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
201 | pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i], | |
202 | 4096, PCI_DMA_BIDIRECTIONAL); | |
203 | } | |
204 | ||
205 | kfree(ppgtt->pt_dma_addr); | |
206 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
207 | __free_page(ppgtt->pt_pages[i]); | |
208 | kfree(ppgtt->pt_pages); | |
209 | kfree(ppgtt); | |
210 | } | |
211 | ||
7bddb01f | 212 | static void i915_ppgtt_insert_sg_entries(struct i915_hw_ppgtt *ppgtt, |
9da3da66 | 213 | const struct sg_table *pages, |
7bddb01f | 214 | unsigned first_entry, |
e7210c3c | 215 | enum i915_cache_level cache_level) |
7bddb01f | 216 | { |
54d12527 | 217 | gtt_pte_t *pt_vaddr; |
7bddb01f DV |
218 | unsigned act_pd = first_entry / I915_PPGTT_PT_ENTRIES; |
219 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; | |
220 | unsigned i, j, m, segment_len; | |
221 | dma_addr_t page_addr; | |
222 | struct scatterlist *sg; | |
223 | ||
224 | /* init sg walking */ | |
9da3da66 | 225 | sg = pages->sgl; |
7bddb01f DV |
226 | i = 0; |
227 | segment_len = sg_dma_len(sg) >> PAGE_SHIFT; | |
228 | m = 0; | |
229 | ||
9da3da66 | 230 | while (i < pages->nents) { |
7bddb01f DV |
231 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pd]); |
232 | ||
233 | for (j = first_pte; j < I915_PPGTT_PT_ENTRIES; j++) { | |
234 | page_addr = sg_dma_address(sg) + (m << PAGE_SHIFT); | |
54d12527 | 235 | pt_vaddr[j] = pte_encode(ppgtt->dev, page_addr, |
e7210c3c | 236 | cache_level); |
7bddb01f DV |
237 | |
238 | /* grab the next page */ | |
9da3da66 CW |
239 | if (++m == segment_len) { |
240 | if (++i == pages->nents) | |
7bddb01f DV |
241 | break; |
242 | ||
9da3da66 | 243 | sg = sg_next(sg); |
7bddb01f DV |
244 | segment_len = sg_dma_len(sg) >> PAGE_SHIFT; |
245 | m = 0; | |
246 | } | |
247 | } | |
248 | ||
249 | kunmap_atomic(pt_vaddr); | |
250 | ||
251 | first_pte = 0; | |
252 | act_pd++; | |
253 | } | |
254 | } | |
255 | ||
7bddb01f DV |
256 | void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, |
257 | struct drm_i915_gem_object *obj, | |
258 | enum i915_cache_level cache_level) | |
259 | { | |
9da3da66 | 260 | i915_ppgtt_insert_sg_entries(ppgtt, |
2f745ad3 | 261 | obj->pages, |
9da3da66 | 262 | obj->gtt_space->start >> PAGE_SHIFT, |
e7210c3c | 263 | cache_level); |
7bddb01f DV |
264 | } |
265 | ||
266 | void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, | |
267 | struct drm_i915_gem_object *obj) | |
268 | { | |
269 | i915_ppgtt_clear_range(ppgtt, | |
270 | obj->gtt_space->start >> PAGE_SHIFT, | |
271 | obj->base.size >> PAGE_SHIFT); | |
272 | } | |
273 | ||
26b1ff35 BW |
274 | void i915_gem_init_ppgtt(struct drm_device *dev) |
275 | { | |
276 | drm_i915_private_t *dev_priv = dev->dev_private; | |
277 | uint32_t pd_offset; | |
278 | struct intel_ring_buffer *ring; | |
279 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
079a43f6 | 280 | gtt_pte_t __iomem *pd_addr; |
26b1ff35 BW |
281 | uint32_t pd_entry; |
282 | int i; | |
283 | ||
284 | if (!dev_priv->mm.aliasing_ppgtt) | |
285 | return; | |
286 | ||
287 | ||
5d4545ae | 288 | pd_addr = (gtt_pte_t __iomem*)dev_priv->gtt.gsm + ppgtt->pd_offset/sizeof(gtt_pte_t); |
26b1ff35 BW |
289 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
290 | dma_addr_t pt_addr; | |
291 | ||
8d2e6308 | 292 | pt_addr = ppgtt->pt_dma_addr[i]; |
26b1ff35 BW |
293 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); |
294 | pd_entry |= GEN6_PDE_VALID; | |
295 | ||
296 | writel(pd_entry, pd_addr + i); | |
297 | } | |
298 | readl(pd_addr); | |
299 | ||
300 | pd_offset = ppgtt->pd_offset; | |
301 | pd_offset /= 64; /* in cachelines, */ | |
302 | pd_offset <<= 16; | |
303 | ||
304 | if (INTEL_INFO(dev)->gen == 6) { | |
305 | uint32_t ecochk, gab_ctl, ecobits; | |
306 | ||
307 | ecobits = I915_READ(GAC_ECO_BITS); | |
308 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
309 | ||
310 | gab_ctl = I915_READ(GAB_CTL); | |
311 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
312 | ||
313 | ecochk = I915_READ(GAM_ECOCHK); | |
314 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | | |
315 | ECOCHK_PPGTT_CACHE64B); | |
316 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
317 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
318 | I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B); | |
319 | /* GFX_MODE is per-ring on gen7+ */ | |
320 | } | |
321 | ||
322 | for_each_ring(ring, dev_priv, i) { | |
323 | if (INTEL_INFO(dev)->gen >= 7) | |
324 | I915_WRITE(RING_MODE_GEN7(ring), | |
325 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
326 | ||
327 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
328 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); | |
329 | } | |
330 | } | |
331 | ||
a81cc00c BW |
332 | extern int intel_iommu_gfx_mapped; |
333 | /* Certain Gen5 chipsets require require idling the GPU before | |
334 | * unmapping anything from the GTT when VT-d is enabled. | |
335 | */ | |
336 | static inline bool needs_idle_maps(struct drm_device *dev) | |
337 | { | |
338 | #ifdef CONFIG_INTEL_IOMMU | |
339 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
340 | * was loaded first. | |
341 | */ | |
342 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
343 | return true; | |
344 | #endif | |
345 | return false; | |
346 | } | |
347 | ||
5c042287 BW |
348 | static bool do_idling(struct drm_i915_private *dev_priv) |
349 | { | |
350 | bool ret = dev_priv->mm.interruptible; | |
351 | ||
a81cc00c | 352 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 353 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 354 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
355 | DRM_ERROR("Couldn't idle GPU\n"); |
356 | /* Wait a bit, in hopes it avoids the hang */ | |
357 | udelay(10); | |
358 | } | |
359 | } | |
360 | ||
361 | return ret; | |
362 | } | |
363 | ||
364 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
365 | { | |
a81cc00c | 366 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
367 | dev_priv->mm.interruptible = interruptible; |
368 | } | |
369 | ||
e76e9aeb BW |
370 | static void i915_ggtt_clear_range(struct drm_device *dev, |
371 | unsigned first_entry, | |
372 | unsigned num_entries) | |
373 | { | |
374 | struct drm_i915_private *dev_priv = dev->dev_private; | |
375 | gtt_pte_t scratch_pte; | |
5d4545ae | 376 | gtt_pte_t __iomem *gtt_base = (gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; |
e76e9aeb | 377 | const int max_entries = dev_priv->mm.gtt->gtt_total_entries - first_entry; |
2ff4aeac | 378 | int i; |
e76e9aeb BW |
379 | |
380 | if (INTEL_INFO(dev)->gen < 6) { | |
381 | intel_gtt_clear_range(first_entry, num_entries); | |
382 | return; | |
383 | } | |
384 | ||
385 | if (WARN(num_entries > max_entries, | |
386 | "First entry = %d; Num entries = %d (max=%d)\n", | |
387 | first_entry, num_entries, max_entries)) | |
388 | num_entries = max_entries; | |
389 | ||
9c61a32d | 390 | scratch_pte = pte_encode(dev, dev_priv->gtt.scratch_page_dma, I915_CACHE_LLC); |
2ff4aeac BW |
391 | for (i = 0; i < num_entries; i++) |
392 | iowrite32(scratch_pte, >t_base[i]); | |
e76e9aeb BW |
393 | readl(gtt_base); |
394 | } | |
395 | ||
76aaf220 DV |
396 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
397 | { | |
398 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 399 | struct drm_i915_gem_object *obj; |
76aaf220 | 400 | |
bee4a186 | 401 | /* First fill our portion of the GTT with scratch pages */ |
5d4545ae BW |
402 | i915_ggtt_clear_range(dev, dev_priv->gtt.start / PAGE_SIZE, |
403 | dev_priv->gtt.total / PAGE_SIZE); | |
bee4a186 | 404 | |
6c085a72 | 405 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) { |
a8e93126 | 406 | i915_gem_clflush_object(obj); |
74163907 | 407 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
76aaf220 DV |
408 | } |
409 | ||
e76e9aeb | 410 | i915_gem_chipset_flush(dev); |
76aaf220 | 411 | } |
7c2e6fdf | 412 | |
74163907 | 413 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 414 | { |
9da3da66 | 415 | if (obj->has_dma_mapping) |
74163907 | 416 | return 0; |
9da3da66 CW |
417 | |
418 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
419 | obj->pages->sgl, obj->pages->nents, | |
420 | PCI_DMA_BIDIRECTIONAL)) | |
421 | return -ENOSPC; | |
422 | ||
423 | return 0; | |
7c2e6fdf DV |
424 | } |
425 | ||
e76e9aeb BW |
426 | /* |
427 | * Binds an object into the global gtt with the specified cache level. The object | |
428 | * will be accessible to the GPU via commands whose operands reference offsets | |
429 | * within the global GTT as well as accessible by the GPU through the GMADR | |
430 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
431 | */ | |
432 | static void gen6_ggtt_bind_object(struct drm_i915_gem_object *obj, | |
433 | enum i915_cache_level level) | |
434 | { | |
435 | struct drm_device *dev = obj->base.dev; | |
436 | struct drm_i915_private *dev_priv = dev->dev_private; | |
437 | struct sg_table *st = obj->pages; | |
438 | struct scatterlist *sg = st->sgl; | |
439 | const int first_entry = obj->gtt_space->start >> PAGE_SHIFT; | |
440 | const int max_entries = dev_priv->mm.gtt->gtt_total_entries - first_entry; | |
1c45140d | 441 | gtt_pte_t __iomem *gtt_entries = |
5d4545ae | 442 | (gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; |
e76e9aeb BW |
443 | int unused, i = 0; |
444 | unsigned int len, m = 0; | |
445 | dma_addr_t addr; | |
446 | ||
447 | for_each_sg(st->sgl, sg, st->nents, unused) { | |
448 | len = sg_dma_len(sg) >> PAGE_SHIFT; | |
449 | for (m = 0; m < len; m++) { | |
450 | addr = sg_dma_address(sg) + (m << PAGE_SHIFT); | |
ccdf56cd | 451 | iowrite32(pte_encode(dev, addr, level), >t_entries[i]); |
e76e9aeb BW |
452 | i++; |
453 | } | |
454 | } | |
455 | ||
456 | BUG_ON(i > max_entries); | |
457 | BUG_ON(i != obj->base.size / PAGE_SIZE); | |
458 | ||
459 | /* XXX: This serves as a posting read to make sure that the PTE has | |
460 | * actually been updated. There is some concern that even though | |
461 | * registers and PTEs are within the same BAR that they are potentially | |
462 | * of NUMA access patterns. Therefore, even with the way we assume | |
463 | * hardware should work, we must keep this posting read for paranoia. | |
464 | */ | |
465 | if (i != 0) | |
466 | WARN_ON(readl(>t_entries[i-1]) != pte_encode(dev, addr, level)); | |
0f9b91c7 BW |
467 | |
468 | /* This next bit makes the above posting read even more important. We | |
469 | * want to flush the TLBs only after we're certain all the PTE updates | |
470 | * have finished. | |
471 | */ | |
472 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
473 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
474 | } |
475 | ||
74163907 DV |
476 | void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, |
477 | enum i915_cache_level cache_level) | |
d5bd1449 CW |
478 | { |
479 | struct drm_device *dev = obj->base.dev; | |
e76e9aeb BW |
480 | if (INTEL_INFO(dev)->gen < 6) { |
481 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? | |
482 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
483 | intel_gtt_insert_sg_entries(obj->pages, | |
484 | obj->gtt_space->start >> PAGE_SHIFT, | |
485 | flags); | |
486 | } else { | |
487 | gen6_ggtt_bind_object(obj, cache_level); | |
488 | } | |
d5bd1449 | 489 | |
74898d7e | 490 | obj->has_global_gtt_mapping = 1; |
d5bd1449 CW |
491 | } |
492 | ||
05394f39 | 493 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj) |
74163907 | 494 | { |
e76e9aeb BW |
495 | i915_ggtt_clear_range(obj->base.dev, |
496 | obj->gtt_space->start >> PAGE_SHIFT, | |
74163907 | 497 | obj->base.size >> PAGE_SHIFT); |
74898d7e DV |
498 | |
499 | obj->has_global_gtt_mapping = 0; | |
74163907 DV |
500 | } |
501 | ||
502 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 503 | { |
5c042287 BW |
504 | struct drm_device *dev = obj->base.dev; |
505 | struct drm_i915_private *dev_priv = dev->dev_private; | |
506 | bool interruptible; | |
507 | ||
508 | interruptible = do_idling(dev_priv); | |
509 | ||
9da3da66 CW |
510 | if (!obj->has_dma_mapping) |
511 | dma_unmap_sg(&dev->pdev->dev, | |
512 | obj->pages->sgl, obj->pages->nents, | |
513 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
514 | |
515 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 516 | } |
644ec02b | 517 | |
42d6ab48 CW |
518 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
519 | unsigned long color, | |
520 | unsigned long *start, | |
521 | unsigned long *end) | |
522 | { | |
523 | if (node->color != color) | |
524 | *start += 4096; | |
525 | ||
526 | if (!list_empty(&node->node_list)) { | |
527 | node = list_entry(node->node_list.next, | |
528 | struct drm_mm_node, | |
529 | node_list); | |
530 | if (node->allocated && node->color != color) | |
531 | *end -= 4096; | |
532 | } | |
533 | } | |
534 | ||
d7e5008f BW |
535 | void i915_gem_setup_global_gtt(struct drm_device *dev, |
536 | unsigned long start, | |
537 | unsigned long mappable_end, | |
538 | unsigned long end) | |
644ec02b DV |
539 | { |
540 | drm_i915_private_t *dev_priv = dev->dev_private; | |
ed2f3452 CW |
541 | struct drm_mm_node *entry; |
542 | struct drm_i915_gem_object *obj; | |
543 | unsigned long hole_start, hole_end; | |
644ec02b | 544 | |
35451cb6 BW |
545 | BUG_ON(mappable_end > end); |
546 | ||
ed2f3452 | 547 | /* Subtract the guard page ... */ |
d1dd20a9 | 548 | drm_mm_init(&dev_priv->mm.gtt_space, start, end - start - PAGE_SIZE); |
42d6ab48 CW |
549 | if (!HAS_LLC(dev)) |
550 | dev_priv->mm.gtt_space.color_adjust = i915_gtt_color_adjust; | |
644ec02b | 551 | |
ed2f3452 CW |
552 | /* Mark any preallocated objects as occupied */ |
553 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) { | |
554 | DRM_DEBUG_KMS("reserving preallocated space: %x + %zx\n", | |
555 | obj->gtt_offset, obj->base.size); | |
556 | ||
557 | BUG_ON(obj->gtt_space != I915_GTT_RESERVED); | |
558 | obj->gtt_space = drm_mm_create_block(&dev_priv->mm.gtt_space, | |
559 | obj->gtt_offset, | |
560 | obj->base.size, | |
561 | false); | |
562 | obj->has_global_gtt_mapping = 1; | |
563 | } | |
564 | ||
5d4545ae | 565 | dev_priv->gtt.start = start; |
5d4545ae | 566 | dev_priv->gtt.total = end - start; |
644ec02b | 567 | |
ed2f3452 CW |
568 | /* Clear any non-preallocated blocks */ |
569 | drm_mm_for_each_hole(entry, &dev_priv->mm.gtt_space, | |
570 | hole_start, hole_end) { | |
571 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", | |
572 | hole_start, hole_end); | |
573 | i915_ggtt_clear_range(dev, | |
574 | hole_start / PAGE_SIZE, | |
575 | (hole_end-hole_start) / PAGE_SIZE); | |
576 | } | |
577 | ||
578 | /* And finally clear the reserved guard page */ | |
579 | i915_ggtt_clear_range(dev, end / PAGE_SIZE - 1, 1); | |
e76e9aeb BW |
580 | } |
581 | ||
d7e5008f BW |
582 | static bool |
583 | intel_enable_ppgtt(struct drm_device *dev) | |
584 | { | |
585 | if (i915_enable_ppgtt >= 0) | |
586 | return i915_enable_ppgtt; | |
587 | ||
588 | #ifdef CONFIG_INTEL_IOMMU | |
589 | /* Disable ppgtt on SNB if VT-d is on. */ | |
590 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) | |
591 | return false; | |
592 | #endif | |
593 | ||
594 | return true; | |
595 | } | |
596 | ||
597 | void i915_gem_init_global_gtt(struct drm_device *dev) | |
598 | { | |
599 | struct drm_i915_private *dev_priv = dev->dev_private; | |
600 | unsigned long gtt_size, mappable_size; | |
601 | int ret; | |
602 | ||
603 | gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT; | |
93d18799 | 604 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f BW |
605 | |
606 | if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { | |
607 | /* PPGTT pdes are stolen from global gtt ptes, so shrink the | |
608 | * aperture accordingly when using aliasing ppgtt. */ | |
609 | gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE; | |
610 | ||
611 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); | |
612 | ||
613 | ret = i915_gem_init_aliasing_ppgtt(dev); | |
614 | if (ret) { | |
615 | mutex_unlock(&dev->struct_mutex); | |
616 | return; | |
617 | } | |
618 | } else { | |
619 | /* Let GEM Manage all of the aperture. | |
620 | * | |
621 | * However, leave one page at the end still bound to the scratch | |
622 | * page. There are a number of places where the hardware | |
623 | * apparently prefetches past the end of the object, and we've | |
624 | * seen multiple hangs with the GPU head pointer stuck in a | |
625 | * batchbuffer bound at the last page of the aperture. One page | |
626 | * should be enough to keep any prefetching inside of the | |
627 | * aperture. | |
628 | */ | |
629 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); | |
630 | } | |
e76e9aeb BW |
631 | } |
632 | ||
633 | static int setup_scratch_page(struct drm_device *dev) | |
634 | { | |
635 | struct drm_i915_private *dev_priv = dev->dev_private; | |
636 | struct page *page; | |
637 | dma_addr_t dma_addr; | |
638 | ||
639 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
640 | if (page == NULL) | |
641 | return -ENOMEM; | |
642 | get_page(page); | |
643 | set_pages_uc(page, 1); | |
644 | ||
645 | #ifdef CONFIG_INTEL_IOMMU | |
646 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
647 | PCI_DMA_BIDIRECTIONAL); | |
648 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) | |
649 | return -EINVAL; | |
650 | #else | |
651 | dma_addr = page_to_phys(page); | |
652 | #endif | |
9c61a32d BW |
653 | dev_priv->gtt.scratch_page = page; |
654 | dev_priv->gtt.scratch_page_dma = dma_addr; | |
e76e9aeb BW |
655 | |
656 | return 0; | |
657 | } | |
658 | ||
659 | static void teardown_scratch_page(struct drm_device *dev) | |
660 | { | |
661 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9c61a32d BW |
662 | set_pages_wb(dev_priv->gtt.scratch_page, 1); |
663 | pci_unmap_page(dev->pdev, dev_priv->gtt.scratch_page_dma, | |
e76e9aeb | 664 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
9c61a32d BW |
665 | put_page(dev_priv->gtt.scratch_page); |
666 | __free_page(dev_priv->gtt.scratch_page); | |
e76e9aeb BW |
667 | } |
668 | ||
669 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) | |
670 | { | |
671 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
672 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
673 | return snb_gmch_ctl << 20; | |
674 | } | |
675 | ||
676 | static inline unsigned int gen6_get_stolen_size(u16 snb_gmch_ctl) | |
677 | { | |
678 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
679 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
680 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
681 | } | |
682 | ||
03752f5b BW |
683 | static inline unsigned int gen7_get_stolen_size(u16 snb_gmch_ctl) |
684 | { | |
685 | static const int stolen_decoder[] = { | |
686 | 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352}; | |
687 | snb_gmch_ctl >>= IVB_GMCH_GMS_SHIFT; | |
688 | snb_gmch_ctl &= IVB_GMCH_GMS_MASK; | |
689 | return stolen_decoder[snb_gmch_ctl] << 20; | |
690 | } | |
691 | ||
e76e9aeb BW |
692 | int i915_gem_gtt_init(struct drm_device *dev) |
693 | { | |
694 | struct drm_i915_private *dev_priv = dev->dev_private; | |
695 | phys_addr_t gtt_bus_addr; | |
696 | u16 snb_gmch_ctl; | |
e76e9aeb BW |
697 | int ret; |
698 | ||
dabb7a91 | 699 | dev_priv->gtt.mappable_base = pci_resource_start(dev->pdev, 2); |
93d18799 | 700 | dev_priv->gtt.mappable_end = pci_resource_len(dev->pdev, 2); |
dabb7a91 | 701 | |
e76e9aeb BW |
702 | /* On modern platforms we need not worry ourself with the legacy |
703 | * hostbridge query stuff. Skip it entirely | |
704 | */ | |
705 | if (INTEL_INFO(dev)->gen < 6) { | |
706 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev->pdev, NULL); | |
707 | if (!ret) { | |
708 | DRM_ERROR("failed to set up gmch\n"); | |
709 | return -EIO; | |
710 | } | |
711 | ||
712 | dev_priv->mm.gtt = intel_gtt_get(); | |
713 | if (!dev_priv->mm.gtt) { | |
714 | DRM_ERROR("Failed to initialize GTT\n"); | |
715 | intel_gmch_remove(); | |
716 | return -ENODEV; | |
717 | } | |
a81cc00c BW |
718 | |
719 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev); | |
720 | ||
e76e9aeb BW |
721 | return 0; |
722 | } | |
723 | ||
e76e9aeb BW |
724 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
725 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
726 | ||
8d2e6308 BW |
727 | dev_priv->mm.gtt = kzalloc(sizeof(*dev_priv->mm.gtt), GFP_KERNEL); |
728 | if (!dev_priv->mm.gtt) | |
729 | return -ENOMEM; | |
20652097 | 730 | |
e76e9aeb | 731 | /* For GEN6+ the PTEs for the ggtt live at 2MB + BAR0 */ |
b5c62158 | 732 | gtt_bus_addr = pci_resource_start(dev->pdev, 0) + (2<<20); |
e76e9aeb BW |
733 | |
734 | /* i9xx_setup */ | |
735 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
736 | dev_priv->mm.gtt->gtt_total_entries = | |
737 | gen6_get_total_gtt_size(snb_gmch_ctl) / sizeof(gtt_pte_t); | |
03752f5b BW |
738 | if (INTEL_INFO(dev)->gen < 7) |
739 | dev_priv->mm.gtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl); | |
740 | else | |
741 | dev_priv->mm.gtt->stolen_size = gen7_get_stolen_size(snb_gmch_ctl); | |
e76e9aeb | 742 | |
e76e9aeb BW |
743 | /* 64/512MB is the current min/max we actually know of, but this is just a |
744 | * coarse sanity check. | |
745 | */ | |
93d18799 BW |
746 | if ((dev_priv->gtt.mappable_end < (64<<20) || |
747 | (dev_priv->gtt.mappable_end > (512<<20)))) { | |
748 | DRM_ERROR("Unknown GMADR size (%lx)\n", | |
749 | dev_priv->gtt.mappable_end); | |
e76e9aeb BW |
750 | ret = -ENXIO; |
751 | goto err_out; | |
752 | } | |
753 | ||
754 | ret = setup_scratch_page(dev); | |
755 | if (ret) { | |
756 | DRM_ERROR("Scratch setup failed\n"); | |
757 | goto err_out; | |
758 | } | |
759 | ||
5d4545ae BW |
760 | dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, |
761 | dev_priv->mm.gtt->gtt_total_entries * sizeof(gtt_pte_t)); | |
762 | if (!dev_priv->gtt.gsm) { | |
e76e9aeb BW |
763 | DRM_ERROR("Failed to map the gtt page table\n"); |
764 | teardown_scratch_page(dev); | |
765 | ret = -ENOMEM; | |
766 | goto err_out; | |
767 | } | |
768 | ||
769 | /* GMADR is the PCI aperture used by SW to access tiled GFX surfaces in a linear fashion. */ | |
d640c4b0 | 770 | DRM_INFO("Memory usable by graphics device = %dM\n", dev_priv->mm.gtt->gtt_total_entries >> 8); |
93d18799 | 771 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", dev_priv->gtt.mappable_end >> 20); |
e76e9aeb BW |
772 | DRM_DEBUG_DRIVER("GTT stolen size = %dM\n", dev_priv->mm.gtt->stolen_size >> 20); |
773 | ||
774 | return 0; | |
775 | ||
776 | err_out: | |
777 | kfree(dev_priv->mm.gtt); | |
778 | if (INTEL_INFO(dev)->gen < 6) | |
779 | intel_gmch_remove(); | |
780 | return ret; | |
781 | } | |
782 | ||
783 | void i915_gem_gtt_fini(struct drm_device *dev) | |
784 | { | |
785 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5d4545ae | 786 | iounmap(dev_priv->gtt.gsm); |
e76e9aeb BW |
787 | teardown_scratch_page(dev); |
788 | if (INTEL_INFO(dev)->gen < 6) | |
789 | intel_gmch_remove(); | |
790 | kfree(dev_priv->mm.gtt); | |
644ec02b | 791 | } |