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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
c4ac524c | 3 | * Copyright © 2011-2014 Intel Corporation |
76aaf220 DV |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
0e46ce2e | 26 | #include <linux/seq_file.h> |
760285e7 DH |
27 | #include <drm/drmP.h> |
28 | #include <drm/i915_drm.h> | |
76aaf220 | 29 | #include "i915_drv.h" |
5dda8fa3 | 30 | #include "i915_vgpu.h" |
76aaf220 DV |
31 | #include "i915_trace.h" |
32 | #include "intel_drv.h" | |
33 | ||
45f8f69a TU |
34 | /** |
35 | * DOC: Global GTT views | |
36 | * | |
37 | * Background and previous state | |
38 | * | |
39 | * Historically objects could exists (be bound) in global GTT space only as | |
40 | * singular instances with a view representing all of the object's backing pages | |
41 | * in a linear fashion. This view will be called a normal view. | |
42 | * | |
43 | * To support multiple views of the same object, where the number of mapped | |
44 | * pages is not equal to the backing store, or where the layout of the pages | |
45 | * is not linear, concept of a GGTT view was added. | |
46 | * | |
47 | * One example of an alternative view is a stereo display driven by a single | |
48 | * image. In this case we would have a framebuffer looking like this | |
49 | * (2x2 pages): | |
50 | * | |
51 | * 12 | |
52 | * 34 | |
53 | * | |
54 | * Above would represent a normal GGTT view as normally mapped for GPU or CPU | |
55 | * rendering. In contrast, fed to the display engine would be an alternative | |
56 | * view which could look something like this: | |
57 | * | |
58 | * 1212 | |
59 | * 3434 | |
60 | * | |
61 | * In this example both the size and layout of pages in the alternative view is | |
62 | * different from the normal view. | |
63 | * | |
64 | * Implementation and usage | |
65 | * | |
66 | * GGTT views are implemented using VMAs and are distinguished via enum | |
67 | * i915_ggtt_view_type and struct i915_ggtt_view. | |
68 | * | |
69 | * A new flavour of core GEM functions which work with GGTT bound objects were | |
ec7adb6e JL |
70 | * added with the _ggtt_ infix, and sometimes with _view postfix to avoid |
71 | * renaming in large amounts of code. They take the struct i915_ggtt_view | |
72 | * parameter encapsulating all metadata required to implement a view. | |
45f8f69a TU |
73 | * |
74 | * As a helper for callers which are only interested in the normal view, | |
75 | * globally const i915_ggtt_view_normal singleton instance exists. All old core | |
76 | * GEM API functions, the ones not taking the view parameter, are operating on, | |
77 | * or with the normal GGTT view. | |
78 | * | |
79 | * Code wanting to add or use a new GGTT view needs to: | |
80 | * | |
81 | * 1. Add a new enum with a suitable name. | |
82 | * 2. Extend the metadata in the i915_ggtt_view structure if required. | |
83 | * 3. Add support to i915_get_vma_pages(). | |
84 | * | |
85 | * New views are required to build a scatter-gather table from within the | |
86 | * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and | |
87 | * exists for the lifetime of an VMA. | |
88 | * | |
89 | * Core API is designed to have copy semantics which means that passed in | |
90 | * struct i915_ggtt_view does not need to be persistent (left around after | |
91 | * calling the core API functions). | |
92 | * | |
93 | */ | |
94 | ||
fe14d5f4 TU |
95 | const struct i915_ggtt_view i915_ggtt_view_normal; |
96 | ||
ee0ce478 VS |
97 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv); |
98 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv); | |
a2319c08 | 99 | |
cfa7c862 DV |
100 | static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt) |
101 | { | |
1893a71b CW |
102 | bool has_aliasing_ppgtt; |
103 | bool has_full_ppgtt; | |
104 | ||
105 | has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6; | |
106 | has_full_ppgtt = INTEL_INFO(dev)->gen >= 7; | |
1893a71b | 107 | |
71ba2d64 YZ |
108 | if (intel_vgpu_active(dev)) |
109 | has_full_ppgtt = false; /* emulation is too hard */ | |
110 | ||
70ee45e1 DL |
111 | /* |
112 | * We don't allow disabling PPGTT for gen9+ as it's a requirement for | |
113 | * execlists, the sole mechanism available to submit work. | |
114 | */ | |
115 | if (INTEL_INFO(dev)->gen < 9 && | |
116 | (enable_ppgtt == 0 || !has_aliasing_ppgtt)) | |
cfa7c862 DV |
117 | return 0; |
118 | ||
119 | if (enable_ppgtt == 1) | |
120 | return 1; | |
121 | ||
1893a71b | 122 | if (enable_ppgtt == 2 && has_full_ppgtt) |
cfa7c862 DV |
123 | return 2; |
124 | ||
93a25a9e DV |
125 | #ifdef CONFIG_INTEL_IOMMU |
126 | /* Disable ppgtt on SNB if VT-d is on. */ | |
127 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) { | |
128 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); | |
cfa7c862 | 129 | return 0; |
93a25a9e DV |
130 | } |
131 | #endif | |
132 | ||
62942ed7 | 133 | /* Early VLV doesn't have this */ |
ca2aed6c VS |
134 | if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
135 | dev->pdev->revision < 0xb) { | |
62942ed7 JB |
136 | DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n"); |
137 | return 0; | |
138 | } | |
139 | ||
2f82bbdf MT |
140 | if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists) |
141 | return 2; | |
142 | else | |
143 | return has_aliasing_ppgtt ? 1 : 0; | |
93a25a9e DV |
144 | } |
145 | ||
6f65e29a BW |
146 | static void ppgtt_bind_vma(struct i915_vma *vma, |
147 | enum i915_cache_level cache_level, | |
148 | u32 flags); | |
149 | static void ppgtt_unbind_vma(struct i915_vma *vma); | |
150 | ||
07749ef3 MT |
151 | static inline gen8_pte_t gen8_pte_encode(dma_addr_t addr, |
152 | enum i915_cache_level level, | |
153 | bool valid) | |
94ec8f61 | 154 | { |
07749ef3 | 155 | gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; |
94ec8f61 | 156 | pte |= addr; |
63c42e56 BW |
157 | |
158 | switch (level) { | |
159 | case I915_CACHE_NONE: | |
fbe5d36e | 160 | pte |= PPAT_UNCACHED_INDEX; |
63c42e56 BW |
161 | break; |
162 | case I915_CACHE_WT: | |
163 | pte |= PPAT_DISPLAY_ELLC_INDEX; | |
164 | break; | |
165 | default: | |
166 | pte |= PPAT_CACHED_INDEX; | |
167 | break; | |
168 | } | |
169 | ||
94ec8f61 BW |
170 | return pte; |
171 | } | |
172 | ||
07749ef3 MT |
173 | static inline gen8_pde_t gen8_pde_encode(struct drm_device *dev, |
174 | dma_addr_t addr, | |
175 | enum i915_cache_level level) | |
b1fe6673 | 176 | { |
07749ef3 | 177 | gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW; |
b1fe6673 BW |
178 | pde |= addr; |
179 | if (level != I915_CACHE_NONE) | |
180 | pde |= PPAT_CACHED_PDE_INDEX; | |
181 | else | |
182 | pde |= PPAT_UNCACHED_INDEX; | |
183 | return pde; | |
184 | } | |
185 | ||
07749ef3 MT |
186 | static gen6_pte_t snb_pte_encode(dma_addr_t addr, |
187 | enum i915_cache_level level, | |
188 | bool valid, u32 unused) | |
54d12527 | 189 | { |
07749ef3 | 190 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
54d12527 | 191 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
192 | |
193 | switch (level) { | |
350ec881 CW |
194 | case I915_CACHE_L3_LLC: |
195 | case I915_CACHE_LLC: | |
196 | pte |= GEN6_PTE_CACHE_LLC; | |
197 | break; | |
198 | case I915_CACHE_NONE: | |
199 | pte |= GEN6_PTE_UNCACHED; | |
200 | break; | |
201 | default: | |
5f77eeb0 | 202 | MISSING_CASE(level); |
350ec881 CW |
203 | } |
204 | ||
205 | return pte; | |
206 | } | |
207 | ||
07749ef3 MT |
208 | static gen6_pte_t ivb_pte_encode(dma_addr_t addr, |
209 | enum i915_cache_level level, | |
210 | bool valid, u32 unused) | |
350ec881 | 211 | { |
07749ef3 | 212 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
350ec881 CW |
213 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
214 | ||
215 | switch (level) { | |
216 | case I915_CACHE_L3_LLC: | |
217 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
218 | break; |
219 | case I915_CACHE_LLC: | |
220 | pte |= GEN6_PTE_CACHE_LLC; | |
221 | break; | |
222 | case I915_CACHE_NONE: | |
9119708c | 223 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
224 | break; |
225 | default: | |
5f77eeb0 | 226 | MISSING_CASE(level); |
e7210c3c BW |
227 | } |
228 | ||
54d12527 BW |
229 | return pte; |
230 | } | |
231 | ||
07749ef3 MT |
232 | static gen6_pte_t byt_pte_encode(dma_addr_t addr, |
233 | enum i915_cache_level level, | |
234 | bool valid, u32 flags) | |
93c34e70 | 235 | { |
07749ef3 | 236 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
93c34e70 KG |
237 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
238 | ||
24f3a8cf AG |
239 | if (!(flags & PTE_READ_ONLY)) |
240 | pte |= BYT_PTE_WRITEABLE; | |
93c34e70 KG |
241 | |
242 | if (level != I915_CACHE_NONE) | |
243 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
244 | ||
245 | return pte; | |
246 | } | |
247 | ||
07749ef3 MT |
248 | static gen6_pte_t hsw_pte_encode(dma_addr_t addr, |
249 | enum i915_cache_level level, | |
250 | bool valid, u32 unused) | |
9119708c | 251 | { |
07749ef3 | 252 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
0d8ff15e | 253 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
254 | |
255 | if (level != I915_CACHE_NONE) | |
87a6b688 | 256 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
257 | |
258 | return pte; | |
259 | } | |
260 | ||
07749ef3 MT |
261 | static gen6_pte_t iris_pte_encode(dma_addr_t addr, |
262 | enum i915_cache_level level, | |
263 | bool valid, u32 unused) | |
4d15c145 | 264 | { |
07749ef3 | 265 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4d15c145 BW |
266 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
267 | ||
651d794f CW |
268 | switch (level) { |
269 | case I915_CACHE_NONE: | |
270 | break; | |
271 | case I915_CACHE_WT: | |
c51e9701 | 272 | pte |= HSW_WT_ELLC_LLC_AGE3; |
651d794f CW |
273 | break; |
274 | default: | |
c51e9701 | 275 | pte |= HSW_WB_ELLC_LLC_AGE3; |
651d794f CW |
276 | break; |
277 | } | |
4d15c145 BW |
278 | |
279 | return pte; | |
280 | } | |
281 | ||
678d96fb BW |
282 | #define i915_dma_unmap_single(px, dev) \ |
283 | __i915_dma_unmap_single((px)->daddr, dev) | |
284 | ||
285 | static inline void __i915_dma_unmap_single(dma_addr_t daddr, | |
286 | struct drm_device *dev) | |
287 | { | |
288 | struct device *device = &dev->pdev->dev; | |
289 | ||
290 | dma_unmap_page(device, daddr, 4096, PCI_DMA_BIDIRECTIONAL); | |
291 | } | |
292 | ||
293 | /** | |
294 | * i915_dma_map_single() - Create a dma mapping for a page table/dir/etc. | |
295 | * @px: Page table/dir/etc to get a DMA map for | |
296 | * @dev: drm device | |
297 | * | |
298 | * Page table allocations are unified across all gens. They always require a | |
299 | * single 4k allocation, as well as a DMA mapping. If we keep the structs | |
300 | * symmetric here, the simple macro covers us for every page table type. | |
301 | * | |
302 | * Return: 0 if success. | |
303 | */ | |
304 | #define i915_dma_map_single(px, dev) \ | |
305 | i915_dma_map_page_single((px)->page, (dev), &(px)->daddr) | |
306 | ||
307 | static inline int i915_dma_map_page_single(struct page *page, | |
308 | struct drm_device *dev, | |
309 | dma_addr_t *daddr) | |
310 | { | |
311 | struct device *device = &dev->pdev->dev; | |
312 | ||
313 | *daddr = dma_map_page(device, page, 0, 4096, PCI_DMA_BIDIRECTIONAL); | |
1266cdb1 MT |
314 | if (dma_mapping_error(device, *daddr)) |
315 | return -ENOMEM; | |
316 | ||
317 | return 0; | |
678d96fb BW |
318 | } |
319 | ||
320 | static void unmap_and_free_pt(struct i915_page_table_entry *pt, | |
321 | struct drm_device *dev) | |
06fda602 BW |
322 | { |
323 | if (WARN_ON(!pt->page)) | |
324 | return; | |
678d96fb BW |
325 | |
326 | i915_dma_unmap_single(pt, dev); | |
06fda602 | 327 | __free_page(pt->page); |
678d96fb | 328 | kfree(pt->used_ptes); |
06fda602 BW |
329 | kfree(pt); |
330 | } | |
331 | ||
06dc68d6 | 332 | static struct i915_page_table_entry *alloc_pt_single(struct drm_device *dev) |
06fda602 BW |
333 | { |
334 | struct i915_page_table_entry *pt; | |
678d96fb BW |
335 | const size_t count = INTEL_INFO(dev)->gen >= 8 ? |
336 | GEN8_PTES : GEN6_PTES; | |
337 | int ret = -ENOMEM; | |
06fda602 BW |
338 | |
339 | pt = kzalloc(sizeof(*pt), GFP_KERNEL); | |
340 | if (!pt) | |
341 | return ERR_PTR(-ENOMEM); | |
342 | ||
678d96fb BW |
343 | pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes), |
344 | GFP_KERNEL); | |
345 | ||
346 | if (!pt->used_ptes) | |
347 | goto fail_bitmap; | |
348 | ||
4933d519 | 349 | pt->page = alloc_page(GFP_KERNEL); |
678d96fb BW |
350 | if (!pt->page) |
351 | goto fail_page; | |
352 | ||
353 | ret = i915_dma_map_single(pt, dev); | |
354 | if (ret) | |
355 | goto fail_dma; | |
06fda602 BW |
356 | |
357 | return pt; | |
678d96fb BW |
358 | |
359 | fail_dma: | |
360 | __free_page(pt->page); | |
361 | fail_page: | |
362 | kfree(pt->used_ptes); | |
363 | fail_bitmap: | |
364 | kfree(pt); | |
365 | ||
366 | return ERR_PTR(ret); | |
06fda602 BW |
367 | } |
368 | ||
369 | /** | |
370 | * alloc_pt_range() - Allocate a multiple page tables | |
371 | * @pd: The page directory which will have at least @count entries | |
372 | * available to point to the allocated page tables. | |
373 | * @pde: First page directory entry for which we are allocating. | |
374 | * @count: Number of pages to allocate. | |
719cd21c | 375 | * @dev: DRM device. |
06fda602 BW |
376 | * |
377 | * Allocates multiple page table pages and sets the appropriate entries in the | |
378 | * page table structure within the page directory. Function cleans up after | |
379 | * itself on any failures. | |
380 | * | |
381 | * Return: 0 if allocation succeeded. | |
382 | */ | |
06dc68d6 | 383 | static int alloc_pt_range(struct i915_page_directory_entry *pd, uint16_t pde, size_t count, |
4933d519 | 384 | struct drm_device *dev) |
06fda602 BW |
385 | { |
386 | int i, ret; | |
387 | ||
388 | /* 512 is the max page tables per page_directory on any platform. */ | |
07749ef3 | 389 | if (WARN_ON(pde + count > I915_PDES)) |
06fda602 BW |
390 | return -EINVAL; |
391 | ||
392 | for (i = pde; i < pde + count; i++) { | |
06dc68d6 | 393 | struct i915_page_table_entry *pt = alloc_pt_single(dev); |
06fda602 BW |
394 | |
395 | if (IS_ERR(pt)) { | |
396 | ret = PTR_ERR(pt); | |
397 | goto err_out; | |
398 | } | |
399 | WARN(pd->page_table[i], | |
686135da | 400 | "Leaking page directory entry %d (%p)\n", |
06fda602 BW |
401 | i, pd->page_table[i]); |
402 | pd->page_table[i] = pt; | |
403 | } | |
404 | ||
405 | return 0; | |
406 | ||
407 | err_out: | |
408 | while (i-- > pde) | |
06dc68d6 | 409 | unmap_and_free_pt(pd->page_table[i], dev); |
06fda602 BW |
410 | return ret; |
411 | } | |
412 | ||
413 | static void unmap_and_free_pd(struct i915_page_directory_entry *pd) | |
414 | { | |
415 | if (pd->page) { | |
416 | __free_page(pd->page); | |
417 | kfree(pd); | |
418 | } | |
419 | } | |
420 | ||
421 | static struct i915_page_directory_entry *alloc_pd_single(void) | |
422 | { | |
423 | struct i915_page_directory_entry *pd; | |
424 | ||
425 | pd = kzalloc(sizeof(*pd), GFP_KERNEL); | |
426 | if (!pd) | |
427 | return ERR_PTR(-ENOMEM); | |
428 | ||
429 | pd->page = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
430 | if (!pd->page) { | |
431 | kfree(pd); | |
432 | return ERR_PTR(-ENOMEM); | |
433 | } | |
434 | ||
435 | return pd; | |
436 | } | |
437 | ||
94e409c1 | 438 | /* Broadwell Page Directory Pointer Descriptors */ |
a4872ba6 | 439 | static int gen8_write_pdp(struct intel_engine_cs *ring, unsigned entry, |
6689c167 | 440 | uint64_t val) |
94e409c1 BW |
441 | { |
442 | int ret; | |
443 | ||
444 | BUG_ON(entry >= 4); | |
445 | ||
446 | ret = intel_ring_begin(ring, 6); | |
447 | if (ret) | |
448 | return ret; | |
449 | ||
450 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
451 | intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry)); | |
452 | intel_ring_emit(ring, (u32)(val >> 32)); | |
453 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
454 | intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry)); | |
455 | intel_ring_emit(ring, (u32)(val)); | |
456 | intel_ring_advance(ring); | |
457 | ||
458 | return 0; | |
459 | } | |
460 | ||
eeb9488e | 461 | static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt, |
6689c167 | 462 | struct intel_engine_cs *ring) |
94e409c1 | 463 | { |
eeb9488e | 464 | int i, ret; |
94e409c1 BW |
465 | |
466 | /* bit of a hack to find the actual last used pd */ | |
07749ef3 | 467 | int used_pd = ppgtt->num_pd_entries / I915_PDES; |
94e409c1 | 468 | |
94e409c1 | 469 | for (i = used_pd - 1; i >= 0; i--) { |
06fda602 | 470 | dma_addr_t addr = ppgtt->pdp.page_directory[i]->daddr; |
6689c167 | 471 | ret = gen8_write_pdp(ring, i, addr); |
eeb9488e BW |
472 | if (ret) |
473 | return ret; | |
94e409c1 | 474 | } |
d595bd4b | 475 | |
eeb9488e | 476 | return 0; |
94e409c1 BW |
477 | } |
478 | ||
459108b8 | 479 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
480 | uint64_t start, |
481 | uint64_t length, | |
459108b8 BW |
482 | bool use_scratch) |
483 | { | |
484 | struct i915_hw_ppgtt *ppgtt = | |
485 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 486 | gen8_pte_t *pt_vaddr, scratch_pte; |
7ad47cf2 BW |
487 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
488 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
489 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
782f1495 | 490 | unsigned num_entries = length >> PAGE_SHIFT; |
459108b8 BW |
491 | unsigned last_pte, i; |
492 | ||
493 | scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr, | |
494 | I915_CACHE_LLC, use_scratch); | |
495 | ||
496 | while (num_entries) { | |
06fda602 BW |
497 | struct i915_page_directory_entry *pd; |
498 | struct i915_page_table_entry *pt; | |
499 | struct page *page_table; | |
500 | ||
501 | if (WARN_ON(!ppgtt->pdp.page_directory[pdpe])) | |
502 | continue; | |
503 | ||
504 | pd = ppgtt->pdp.page_directory[pdpe]; | |
505 | ||
506 | if (WARN_ON(!pd->page_table[pde])) | |
507 | continue; | |
508 | ||
509 | pt = pd->page_table[pde]; | |
510 | ||
511 | if (WARN_ON(!pt->page)) | |
512 | continue; | |
513 | ||
514 | page_table = pt->page; | |
459108b8 | 515 | |
7ad47cf2 | 516 | last_pte = pte + num_entries; |
07749ef3 MT |
517 | if (last_pte > GEN8_PTES) |
518 | last_pte = GEN8_PTES; | |
459108b8 BW |
519 | |
520 | pt_vaddr = kmap_atomic(page_table); | |
521 | ||
7ad47cf2 | 522 | for (i = pte; i < last_pte; i++) { |
459108b8 | 523 | pt_vaddr[i] = scratch_pte; |
7ad47cf2 BW |
524 | num_entries--; |
525 | } | |
459108b8 | 526 | |
fd1ab8f4 RB |
527 | if (!HAS_LLC(ppgtt->base.dev)) |
528 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
459108b8 BW |
529 | kunmap_atomic(pt_vaddr); |
530 | ||
7ad47cf2 | 531 | pte = 0; |
07749ef3 | 532 | if (++pde == I915_PDES) { |
7ad47cf2 BW |
533 | pdpe++; |
534 | pde = 0; | |
535 | } | |
459108b8 BW |
536 | } |
537 | } | |
538 | ||
9df15b49 BW |
539 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
540 | struct sg_table *pages, | |
782f1495 | 541 | uint64_t start, |
24f3a8cf | 542 | enum i915_cache_level cache_level, u32 unused) |
9df15b49 BW |
543 | { |
544 | struct i915_hw_ppgtt *ppgtt = | |
545 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 546 | gen8_pte_t *pt_vaddr; |
7ad47cf2 BW |
547 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
548 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
549 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
9df15b49 BW |
550 | struct sg_page_iter sg_iter; |
551 | ||
6f1cc993 | 552 | pt_vaddr = NULL; |
7ad47cf2 | 553 | |
9df15b49 | 554 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
76643600 | 555 | if (WARN_ON(pdpe >= GEN8_LEGACY_PDPES)) |
7ad47cf2 BW |
556 | break; |
557 | ||
d7b3de91 | 558 | if (pt_vaddr == NULL) { |
06fda602 BW |
559 | struct i915_page_directory_entry *pd = ppgtt->pdp.page_directory[pdpe]; |
560 | struct i915_page_table_entry *pt = pd->page_table[pde]; | |
561 | struct page *page_table = pt->page; | |
d7b3de91 BW |
562 | |
563 | pt_vaddr = kmap_atomic(page_table); | |
564 | } | |
9df15b49 | 565 | |
7ad47cf2 | 566 | pt_vaddr[pte] = |
6f1cc993 CW |
567 | gen8_pte_encode(sg_page_iter_dma_address(&sg_iter), |
568 | cache_level, true); | |
07749ef3 | 569 | if (++pte == GEN8_PTES) { |
fd1ab8f4 RB |
570 | if (!HAS_LLC(ppgtt->base.dev)) |
571 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
9df15b49 | 572 | kunmap_atomic(pt_vaddr); |
6f1cc993 | 573 | pt_vaddr = NULL; |
07749ef3 | 574 | if (++pde == I915_PDES) { |
7ad47cf2 BW |
575 | pdpe++; |
576 | pde = 0; | |
577 | } | |
578 | pte = 0; | |
9df15b49 BW |
579 | } |
580 | } | |
fd1ab8f4 RB |
581 | if (pt_vaddr) { |
582 | if (!HAS_LLC(ppgtt->base.dev)) | |
583 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
6f1cc993 | 584 | kunmap_atomic(pt_vaddr); |
fd1ab8f4 | 585 | } |
9df15b49 BW |
586 | } |
587 | ||
06dc68d6 | 588 | static void gen8_free_page_tables(struct i915_page_directory_entry *pd, struct drm_device *dev) |
7ad47cf2 BW |
589 | { |
590 | int i; | |
591 | ||
06fda602 | 592 | if (!pd->page) |
7ad47cf2 BW |
593 | return; |
594 | ||
07749ef3 | 595 | for (i = 0; i < I915_PDES; i++) { |
06fda602 BW |
596 | if (WARN_ON(!pd->page_table[i])) |
597 | continue; | |
7ad47cf2 | 598 | |
06dc68d6 | 599 | unmap_and_free_pt(pd->page_table[i], dev); |
06fda602 BW |
600 | pd->page_table[i] = NULL; |
601 | } | |
d7b3de91 BW |
602 | } |
603 | ||
604 | static void gen8_ppgtt_free(struct i915_hw_ppgtt *ppgtt) | |
b45a6715 BW |
605 | { |
606 | int i; | |
607 | ||
7ad47cf2 | 608 | for (i = 0; i < ppgtt->num_pd_pages; i++) { |
06fda602 BW |
609 | if (WARN_ON(!ppgtt->pdp.page_directory[i])) |
610 | continue; | |
611 | ||
06dc68d6 | 612 | gen8_free_page_tables(ppgtt->pdp.page_directory[i], ppgtt->base.dev); |
06fda602 | 613 | unmap_and_free_pd(ppgtt->pdp.page_directory[i]); |
7ad47cf2 | 614 | } |
b45a6715 BW |
615 | } |
616 | ||
617 | static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt) | |
618 | { | |
f3a964b9 | 619 | struct pci_dev *hwdev = ppgtt->base.dev->pdev; |
b45a6715 BW |
620 | int i, j; |
621 | ||
622 | for (i = 0; i < ppgtt->num_pd_pages; i++) { | |
623 | /* TODO: In the future we'll support sparse mappings, so this | |
624 | * will have to change. */ | |
06fda602 | 625 | if (!ppgtt->pdp.page_directory[i]->daddr) |
b45a6715 BW |
626 | continue; |
627 | ||
06fda602 | 628 | pci_unmap_page(hwdev, ppgtt->pdp.page_directory[i]->daddr, PAGE_SIZE, |
f3a964b9 | 629 | PCI_DMA_BIDIRECTIONAL); |
b45a6715 | 630 | |
07749ef3 | 631 | for (j = 0; j < I915_PDES; j++) { |
06fda602 BW |
632 | struct i915_page_directory_entry *pd = ppgtt->pdp.page_directory[i]; |
633 | struct i915_page_table_entry *pt; | |
634 | dma_addr_t addr; | |
635 | ||
636 | if (WARN_ON(!pd->page_table[j])) | |
637 | continue; | |
638 | ||
639 | pt = pd->page_table[j]; | |
640 | addr = pt->daddr; | |
641 | ||
b45a6715 | 642 | if (addr) |
f3a964b9 BW |
643 | pci_unmap_page(hwdev, addr, PAGE_SIZE, |
644 | PCI_DMA_BIDIRECTIONAL); | |
b45a6715 BW |
645 | } |
646 | } | |
647 | } | |
648 | ||
37aca44a BW |
649 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) |
650 | { | |
651 | struct i915_hw_ppgtt *ppgtt = | |
652 | container_of(vm, struct i915_hw_ppgtt, base); | |
37aca44a | 653 | |
b45a6715 BW |
654 | gen8_ppgtt_unmap_pages(ppgtt); |
655 | gen8_ppgtt_free(ppgtt); | |
37aca44a BW |
656 | } |
657 | ||
d7b3de91 | 658 | static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt) |
bf2b4ed2 | 659 | { |
06fda602 | 660 | int i, ret; |
bf2b4ed2 | 661 | |
d7b3de91 | 662 | for (i = 0; i < ppgtt->num_pd_pages; i++) { |
06fda602 | 663 | ret = alloc_pt_range(ppgtt->pdp.page_directory[i], |
07749ef3 | 664 | 0, I915_PDES, ppgtt->base.dev); |
06fda602 BW |
665 | if (ret) |
666 | goto unwind_out; | |
7ad47cf2 BW |
667 | } |
668 | ||
bf2b4ed2 | 669 | return 0; |
7ad47cf2 BW |
670 | |
671 | unwind_out: | |
d7b3de91 | 672 | while (i--) |
06dc68d6 | 673 | gen8_free_page_tables(ppgtt->pdp.page_directory[i], ppgtt->base.dev); |
7ad47cf2 | 674 | |
d7b3de91 | 675 | return -ENOMEM; |
bf2b4ed2 BW |
676 | } |
677 | ||
d7b3de91 BW |
678 | static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt, |
679 | const int max_pdp) | |
bf2b4ed2 BW |
680 | { |
681 | int i; | |
682 | ||
d7b3de91 | 683 | for (i = 0; i < max_pdp; i++) { |
06fda602 BW |
684 | ppgtt->pdp.page_directory[i] = alloc_pd_single(); |
685 | if (IS_ERR(ppgtt->pdp.page_directory[i])) | |
d7b3de91 | 686 | goto unwind_out; |
d7b3de91 BW |
687 | } |
688 | ||
689 | ppgtt->num_pd_pages = max_pdp; | |
76643600 | 690 | BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPES); |
bf2b4ed2 BW |
691 | |
692 | return 0; | |
d7b3de91 BW |
693 | |
694 | unwind_out: | |
06fda602 BW |
695 | while (i--) |
696 | unmap_and_free_pd(ppgtt->pdp.page_directory[i]); | |
d7b3de91 BW |
697 | |
698 | return -ENOMEM; | |
bf2b4ed2 BW |
699 | } |
700 | ||
701 | static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt, | |
702 | const int max_pdp) | |
703 | { | |
704 | int ret; | |
705 | ||
706 | ret = gen8_ppgtt_allocate_page_directories(ppgtt, max_pdp); | |
707 | if (ret) | |
708 | return ret; | |
709 | ||
d7b3de91 BW |
710 | ret = gen8_ppgtt_allocate_page_tables(ppgtt); |
711 | if (ret) | |
712 | goto err_out; | |
bf2b4ed2 | 713 | |
07749ef3 | 714 | ppgtt->num_pd_entries = max_pdp * I915_PDES; |
bf2b4ed2 | 715 | |
d7b3de91 | 716 | return 0; |
bf2b4ed2 | 717 | |
d7b3de91 BW |
718 | err_out: |
719 | gen8_ppgtt_free(ppgtt); | |
bf2b4ed2 BW |
720 | return ret; |
721 | } | |
722 | ||
723 | static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt *ppgtt, | |
724 | const int pd) | |
725 | { | |
726 | dma_addr_t pd_addr; | |
727 | int ret; | |
728 | ||
729 | pd_addr = pci_map_page(ppgtt->base.dev->pdev, | |
06fda602 | 730 | ppgtt->pdp.page_directory[pd]->page, 0, |
bf2b4ed2 BW |
731 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
732 | ||
733 | ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr); | |
734 | if (ret) | |
735 | return ret; | |
736 | ||
06fda602 | 737 | ppgtt->pdp.page_directory[pd]->daddr = pd_addr; |
bf2b4ed2 BW |
738 | |
739 | return 0; | |
740 | } | |
741 | ||
742 | static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt, | |
743 | const int pd, | |
744 | const int pt) | |
745 | { | |
746 | dma_addr_t pt_addr; | |
06fda602 BW |
747 | struct i915_page_directory_entry *pdir = ppgtt->pdp.page_directory[pd]; |
748 | struct i915_page_table_entry *ptab = pdir->page_table[pt]; | |
7324cc04 | 749 | struct page *p = ptab->page; |
bf2b4ed2 BW |
750 | int ret; |
751 | ||
bf2b4ed2 BW |
752 | pt_addr = pci_map_page(ppgtt->base.dev->pdev, |
753 | p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
754 | ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr); | |
755 | if (ret) | |
756 | return ret; | |
757 | ||
7324cc04 | 758 | ptab->daddr = pt_addr; |
bf2b4ed2 BW |
759 | |
760 | return 0; | |
761 | } | |
762 | ||
eb0b44ad | 763 | /* |
f3a964b9 BW |
764 | * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers |
765 | * with a net effect resembling a 2-level page table in normal x86 terms. Each | |
766 | * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address | |
767 | * space. | |
37aca44a | 768 | * |
f3a964b9 BW |
769 | * FIXME: split allocation into smaller pieces. For now we only ever do this |
770 | * once, but with full PPGTT, the multiple contiguous allocations will be bad. | |
37aca44a | 771 | * TODO: Do something with the size parameter |
f3a964b9 | 772 | */ |
37aca44a BW |
773 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) |
774 | { | |
37aca44a | 775 | const int max_pdp = DIV_ROUND_UP(size, 1 << 30); |
07749ef3 | 776 | const int min_pt_pages = I915_PDES * max_pdp; |
f3a964b9 | 777 | int i, j, ret; |
37aca44a BW |
778 | |
779 | if (size % (1<<30)) | |
780 | DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size); | |
781 | ||
2934368e MK |
782 | /* 1. Do all our allocations for page directories and page tables. |
783 | * We allocate more than was asked so that we can point the unused parts | |
784 | * to valid entries that point to scratch page. Dynamic page tables | |
785 | * will fix this eventually. | |
786 | */ | |
787 | ret = gen8_ppgtt_alloc(ppgtt, GEN8_LEGACY_PDPES); | |
bf2b4ed2 BW |
788 | if (ret) |
789 | return ret; | |
f3a964b9 | 790 | |
37aca44a | 791 | /* |
bf2b4ed2 | 792 | * 2. Create DMA mappings for the page directories and page tables. |
37aca44a | 793 | */ |
2934368e | 794 | for (i = 0; i < GEN8_LEGACY_PDPES; i++) { |
bf2b4ed2 | 795 | ret = gen8_ppgtt_setup_page_directories(ppgtt, i); |
f3a964b9 BW |
796 | if (ret) |
797 | goto bail; | |
37aca44a | 798 | |
07749ef3 | 799 | for (j = 0; j < I915_PDES; j++) { |
bf2b4ed2 | 800 | ret = gen8_ppgtt_setup_page_tables(ppgtt, i, j); |
f3a964b9 BW |
801 | if (ret) |
802 | goto bail; | |
37aca44a BW |
803 | } |
804 | } | |
805 | ||
f3a964b9 BW |
806 | /* |
807 | * 3. Map all the page directory entires to point to the page tables | |
808 | * we've allocated. | |
809 | * | |
810 | * For now, the PPGTT helper functions all require that the PDEs are | |
b1fe6673 | 811 | * plugged in correctly. So we do that now/here. For aliasing PPGTT, we |
f3a964b9 BW |
812 | * will never need to touch the PDEs again. |
813 | */ | |
2934368e | 814 | for (i = 0; i < GEN8_LEGACY_PDPES; i++) { |
06fda602 | 815 | struct i915_page_directory_entry *pd = ppgtt->pdp.page_directory[i]; |
07749ef3 | 816 | gen8_pde_t *pd_vaddr; |
06fda602 | 817 | pd_vaddr = kmap_atomic(ppgtt->pdp.page_directory[i]->page); |
07749ef3 | 818 | for (j = 0; j < I915_PDES; j++) { |
06fda602 BW |
819 | struct i915_page_table_entry *pt = pd->page_table[j]; |
820 | dma_addr_t addr = pt->daddr; | |
b1fe6673 BW |
821 | pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr, |
822 | I915_CACHE_LLC); | |
823 | } | |
fd1ab8f4 RB |
824 | if (!HAS_LLC(ppgtt->base.dev)) |
825 | drm_clflush_virt_range(pd_vaddr, PAGE_SIZE); | |
b1fe6673 BW |
826 | kunmap_atomic(pd_vaddr); |
827 | } | |
828 | ||
f3a964b9 BW |
829 | ppgtt->switch_mm = gen8_mm_switch; |
830 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; | |
831 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; | |
832 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; | |
833 | ppgtt->base.start = 0; | |
f3a964b9 | 834 | |
2934368e | 835 | /* This is the area that we advertise as usable for the caller */ |
07749ef3 | 836 | ppgtt->base.total = max_pdp * I915_PDES * GEN8_PTES * PAGE_SIZE; |
2934368e MK |
837 | |
838 | /* Set all ptes to a valid scratch page. Also above requested space */ | |
839 | ppgtt->base.clear_range(&ppgtt->base, 0, | |
07749ef3 | 840 | ppgtt->num_pd_pages * GEN8_PTES * PAGE_SIZE, |
2934368e | 841 | true); |
459108b8 | 842 | |
37aca44a BW |
843 | DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n", |
844 | ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp); | |
845 | DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n", | |
5abbcca3 BW |
846 | ppgtt->num_pd_entries, |
847 | (ppgtt->num_pd_entries - min_pt_pages) + size % (1<<30)); | |
28cf5415 | 848 | return 0; |
37aca44a | 849 | |
f3a964b9 BW |
850 | bail: |
851 | gen8_ppgtt_unmap_pages(ppgtt); | |
852 | gen8_ppgtt_free(ppgtt); | |
37aca44a BW |
853 | return ret; |
854 | } | |
855 | ||
87d60b63 BW |
856 | static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) |
857 | { | |
858 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; | |
859 | struct i915_address_space *vm = &ppgtt->base; | |
07749ef3 MT |
860 | gen6_pte_t __iomem *pd_addr; |
861 | gen6_pte_t scratch_pte; | |
87d60b63 BW |
862 | uint32_t pd_entry; |
863 | int pte, pde; | |
864 | ||
24f3a8cf | 865 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0); |
87d60b63 | 866 | |
07749ef3 MT |
867 | pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm + |
868 | ppgtt->pd.pd_offset / sizeof(gen6_pte_t); | |
87d60b63 BW |
869 | |
870 | seq_printf(m, " VM %p (pd_offset %x-%x):\n", vm, | |
7324cc04 BW |
871 | ppgtt->pd.pd_offset, |
872 | ppgtt->pd.pd_offset + ppgtt->num_pd_entries); | |
87d60b63 BW |
873 | for (pde = 0; pde < ppgtt->num_pd_entries; pde++) { |
874 | u32 expected; | |
07749ef3 | 875 | gen6_pte_t *pt_vaddr; |
06fda602 | 876 | dma_addr_t pt_addr = ppgtt->pd.page_table[pde]->daddr; |
87d60b63 BW |
877 | pd_entry = readl(pd_addr + pde); |
878 | expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); | |
879 | ||
880 | if (pd_entry != expected) | |
881 | seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", | |
882 | pde, | |
883 | pd_entry, | |
884 | expected); | |
885 | seq_printf(m, "\tPDE: %x\n", pd_entry); | |
886 | ||
06fda602 | 887 | pt_vaddr = kmap_atomic(ppgtt->pd.page_table[pde]->page); |
07749ef3 | 888 | for (pte = 0; pte < GEN6_PTES; pte+=4) { |
87d60b63 | 889 | unsigned long va = |
07749ef3 | 890 | (pde * PAGE_SIZE * GEN6_PTES) + |
87d60b63 BW |
891 | (pte * PAGE_SIZE); |
892 | int i; | |
893 | bool found = false; | |
894 | for (i = 0; i < 4; i++) | |
895 | if (pt_vaddr[pte + i] != scratch_pte) | |
896 | found = true; | |
897 | if (!found) | |
898 | continue; | |
899 | ||
900 | seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); | |
901 | for (i = 0; i < 4; i++) { | |
902 | if (pt_vaddr[pte + i] != scratch_pte) | |
903 | seq_printf(m, " %08x", pt_vaddr[pte + i]); | |
904 | else | |
905 | seq_puts(m, " SCRATCH "); | |
906 | } | |
907 | seq_puts(m, "\n"); | |
908 | } | |
909 | kunmap_atomic(pt_vaddr); | |
910 | } | |
911 | } | |
912 | ||
678d96fb BW |
913 | /* Write pde (index) from the page directory @pd to the page table @pt */ |
914 | static void gen6_write_pde(struct i915_page_directory_entry *pd, | |
915 | const int pde, struct i915_page_table_entry *pt) | |
6197349b | 916 | { |
678d96fb BW |
917 | /* Caller needs to make sure the write completes if necessary */ |
918 | struct i915_hw_ppgtt *ppgtt = | |
919 | container_of(pd, struct i915_hw_ppgtt, pd); | |
920 | u32 pd_entry; | |
6197349b | 921 | |
678d96fb BW |
922 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt->daddr); |
923 | pd_entry |= GEN6_PDE_VALID; | |
6197349b | 924 | |
678d96fb BW |
925 | writel(pd_entry, ppgtt->pd_addr + pde); |
926 | } | |
6197349b | 927 | |
678d96fb BW |
928 | /* Write all the page tables found in the ppgtt structure to incrementing page |
929 | * directories. */ | |
930 | static void gen6_write_page_range(struct drm_i915_private *dev_priv, | |
931 | struct i915_page_directory_entry *pd, | |
932 | uint32_t start, uint32_t length) | |
933 | { | |
934 | struct i915_page_table_entry *pt; | |
935 | uint32_t pde, temp; | |
936 | ||
937 | gen6_for_each_pde(pt, pd, start, length, temp, pde) | |
938 | gen6_write_pde(pd, pde, pt); | |
939 | ||
940 | /* Make sure write is complete before other code can use this page | |
941 | * table. Also require for WC mapped PTEs */ | |
942 | readl(dev_priv->gtt.gsm); | |
3e302542 BW |
943 | } |
944 | ||
b4a74e3a | 945 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 946 | { |
7324cc04 | 947 | BUG_ON(ppgtt->pd.pd_offset & 0x3f); |
b4a74e3a | 948 | |
7324cc04 | 949 | return (ppgtt->pd.pd_offset / 64) << 16; |
b4a74e3a BW |
950 | } |
951 | ||
90252e5c | 952 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
6689c167 | 953 | struct intel_engine_cs *ring) |
90252e5c | 954 | { |
90252e5c BW |
955 | int ret; |
956 | ||
90252e5c BW |
957 | /* NB: TLBs must be flushed and invalidated before a switch */ |
958 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
959 | if (ret) | |
960 | return ret; | |
961 | ||
962 | ret = intel_ring_begin(ring, 6); | |
963 | if (ret) | |
964 | return ret; | |
965 | ||
966 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
967 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
968 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
969 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
970 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
971 | intel_ring_emit(ring, MI_NOOP); | |
972 | intel_ring_advance(ring); | |
973 | ||
974 | return 0; | |
975 | } | |
976 | ||
71ba2d64 YZ |
977 | static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt, |
978 | struct intel_engine_cs *ring) | |
979 | { | |
980 | struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev); | |
981 | ||
982 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
983 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
984 | return 0; | |
985 | } | |
986 | ||
48a10389 | 987 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
6689c167 | 988 | struct intel_engine_cs *ring) |
48a10389 | 989 | { |
48a10389 BW |
990 | int ret; |
991 | ||
48a10389 BW |
992 | /* NB: TLBs must be flushed and invalidated before a switch */ |
993 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
994 | if (ret) | |
995 | return ret; | |
996 | ||
997 | ret = intel_ring_begin(ring, 6); | |
998 | if (ret) | |
999 | return ret; | |
1000 | ||
1001 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
1002 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
1003 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
1004 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
1005 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
1006 | intel_ring_emit(ring, MI_NOOP); | |
1007 | intel_ring_advance(ring); | |
1008 | ||
90252e5c BW |
1009 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
1010 | if (ring->id != RCS) { | |
1011 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
1012 | if (ret) | |
1013 | return ret; | |
1014 | } | |
1015 | ||
48a10389 BW |
1016 | return 0; |
1017 | } | |
1018 | ||
eeb9488e | 1019 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
6689c167 | 1020 | struct intel_engine_cs *ring) |
eeb9488e BW |
1021 | { |
1022 | struct drm_device *dev = ppgtt->base.dev; | |
1023 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1024 | ||
48a10389 | 1025 | |
eeb9488e BW |
1026 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
1027 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
1028 | ||
1029 | POSTING_READ(RING_PP_DIR_DCLV(ring)); | |
1030 | ||
1031 | return 0; | |
1032 | } | |
1033 | ||
82460d97 | 1034 | static void gen8_ppgtt_enable(struct drm_device *dev) |
eeb9488e | 1035 | { |
eeb9488e | 1036 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 1037 | struct intel_engine_cs *ring; |
82460d97 | 1038 | int j; |
3e302542 | 1039 | |
eeb9488e BW |
1040 | for_each_ring(ring, dev_priv, j) { |
1041 | I915_WRITE(RING_MODE_GEN7(ring), | |
1042 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
eeb9488e | 1043 | } |
eeb9488e | 1044 | } |
6197349b | 1045 | |
82460d97 | 1046 | static void gen7_ppgtt_enable(struct drm_device *dev) |
3e302542 | 1047 | { |
50227e1c | 1048 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 1049 | struct intel_engine_cs *ring; |
b4a74e3a | 1050 | uint32_t ecochk, ecobits; |
3e302542 | 1051 | int i; |
6197349b | 1052 | |
b4a74e3a BW |
1053 | ecobits = I915_READ(GAC_ECO_BITS); |
1054 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
a65c2fcd | 1055 | |
b4a74e3a BW |
1056 | ecochk = I915_READ(GAM_ECOCHK); |
1057 | if (IS_HASWELL(dev)) { | |
1058 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
1059 | } else { | |
1060 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
1061 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
1062 | } | |
1063 | I915_WRITE(GAM_ECOCHK, ecochk); | |
a65c2fcd | 1064 | |
b4a74e3a | 1065 | for_each_ring(ring, dev_priv, i) { |
6197349b | 1066 | /* GFX_MODE is per-ring on gen7+ */ |
b4a74e3a BW |
1067 | I915_WRITE(RING_MODE_GEN7(ring), |
1068 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b | 1069 | } |
b4a74e3a | 1070 | } |
6197349b | 1071 | |
82460d97 | 1072 | static void gen6_ppgtt_enable(struct drm_device *dev) |
b4a74e3a | 1073 | { |
50227e1c | 1074 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4a74e3a | 1075 | uint32_t ecochk, gab_ctl, ecobits; |
a65c2fcd | 1076 | |
b4a74e3a BW |
1077 | ecobits = I915_READ(GAC_ECO_BITS); |
1078 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | | |
1079 | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 1080 | |
b4a74e3a BW |
1081 | gab_ctl = I915_READ(GAB_CTL); |
1082 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
1083 | ||
1084 | ecochk = I915_READ(GAM_ECOCHK); | |
1085 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); | |
1086 | ||
1087 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b BW |
1088 | } |
1089 | ||
1d2a314c | 1090 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 1091 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1092 | uint64_t start, |
1093 | uint64_t length, | |
828c7908 | 1094 | bool use_scratch) |
1d2a314c | 1095 | { |
853ba5d2 BW |
1096 | struct i915_hw_ppgtt *ppgtt = |
1097 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 1098 | gen6_pte_t *pt_vaddr, scratch_pte; |
782f1495 BW |
1099 | unsigned first_entry = start >> PAGE_SHIFT; |
1100 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1101 | unsigned act_pt = first_entry / GEN6_PTES; |
1102 | unsigned first_pte = first_entry % GEN6_PTES; | |
7bddb01f | 1103 | unsigned last_pte, i; |
1d2a314c | 1104 | |
24f3a8cf | 1105 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0); |
1d2a314c | 1106 | |
7bddb01f DV |
1107 | while (num_entries) { |
1108 | last_pte = first_pte + num_entries; | |
07749ef3 MT |
1109 | if (last_pte > GEN6_PTES) |
1110 | last_pte = GEN6_PTES; | |
7bddb01f | 1111 | |
06fda602 | 1112 | pt_vaddr = kmap_atomic(ppgtt->pd.page_table[act_pt]->page); |
1d2a314c | 1113 | |
7bddb01f DV |
1114 | for (i = first_pte; i < last_pte; i++) |
1115 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
1116 | |
1117 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 1118 | |
7bddb01f DV |
1119 | num_entries -= last_pte - first_pte; |
1120 | first_pte = 0; | |
a15326a5 | 1121 | act_pt++; |
7bddb01f | 1122 | } |
1d2a314c DV |
1123 | } |
1124 | ||
853ba5d2 | 1125 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 | 1126 | struct sg_table *pages, |
782f1495 | 1127 | uint64_t start, |
24f3a8cf | 1128 | enum i915_cache_level cache_level, u32 flags) |
def886c3 | 1129 | { |
853ba5d2 BW |
1130 | struct i915_hw_ppgtt *ppgtt = |
1131 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 1132 | gen6_pte_t *pt_vaddr; |
782f1495 | 1133 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1134 | unsigned act_pt = first_entry / GEN6_PTES; |
1135 | unsigned act_pte = first_entry % GEN6_PTES; | |
6e995e23 ID |
1136 | struct sg_page_iter sg_iter; |
1137 | ||
cc79714f | 1138 | pt_vaddr = NULL; |
6e995e23 | 1139 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
cc79714f | 1140 | if (pt_vaddr == NULL) |
06fda602 | 1141 | pt_vaddr = kmap_atomic(ppgtt->pd.page_table[act_pt]->page); |
6e995e23 | 1142 | |
cc79714f CW |
1143 | pt_vaddr[act_pte] = |
1144 | vm->pte_encode(sg_page_iter_dma_address(&sg_iter), | |
24f3a8cf AG |
1145 | cache_level, true, flags); |
1146 | ||
07749ef3 | 1147 | if (++act_pte == GEN6_PTES) { |
6e995e23 | 1148 | kunmap_atomic(pt_vaddr); |
cc79714f | 1149 | pt_vaddr = NULL; |
a15326a5 | 1150 | act_pt++; |
6e995e23 | 1151 | act_pte = 0; |
def886c3 | 1152 | } |
def886c3 | 1153 | } |
cc79714f CW |
1154 | if (pt_vaddr) |
1155 | kunmap_atomic(pt_vaddr); | |
def886c3 DV |
1156 | } |
1157 | ||
563222a7 BW |
1158 | /* PDE TLBs are a pain invalidate pre GEN8. It requires a context reload. If we |
1159 | * are switching between contexts with the same LRCA, we also must do a force | |
1160 | * restore. | |
1161 | */ | |
1162 | static inline void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt) | |
1163 | { | |
1164 | /* If current vm != vm, */ | |
1165 | ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask; | |
1166 | } | |
1167 | ||
4933d519 MT |
1168 | static void gen6_initialize_pt(struct i915_address_space *vm, |
1169 | struct i915_page_table_entry *pt) | |
1170 | { | |
1171 | gen6_pte_t *pt_vaddr, scratch_pte; | |
1172 | int i; | |
1173 | ||
1174 | WARN_ON(vm->scratch.addr == 0); | |
1175 | ||
1176 | scratch_pte = vm->pte_encode(vm->scratch.addr, | |
1177 | I915_CACHE_LLC, true, 0); | |
1178 | ||
1179 | pt_vaddr = kmap_atomic(pt->page); | |
1180 | ||
1181 | for (i = 0; i < GEN6_PTES; i++) | |
1182 | pt_vaddr[i] = scratch_pte; | |
1183 | ||
1184 | kunmap_atomic(pt_vaddr); | |
1185 | } | |
1186 | ||
678d96fb BW |
1187 | static int gen6_alloc_va_range(struct i915_address_space *vm, |
1188 | uint64_t start, uint64_t length) | |
1189 | { | |
4933d519 MT |
1190 | DECLARE_BITMAP(new_page_tables, I915_PDES); |
1191 | struct drm_device *dev = vm->dev; | |
1192 | struct drm_i915_private *dev_priv = dev->dev_private; | |
678d96fb BW |
1193 | struct i915_hw_ppgtt *ppgtt = |
1194 | container_of(vm, struct i915_hw_ppgtt, base); | |
1195 | struct i915_page_table_entry *pt; | |
4933d519 | 1196 | const uint32_t start_save = start, length_save = length; |
678d96fb | 1197 | uint32_t pde, temp; |
4933d519 MT |
1198 | int ret; |
1199 | ||
1200 | WARN_ON(upper_32_bits(start)); | |
1201 | ||
1202 | bitmap_zero(new_page_tables, I915_PDES); | |
1203 | ||
1204 | /* The allocation is done in two stages so that we can bail out with | |
1205 | * minimal amount of pain. The first stage finds new page tables that | |
1206 | * need allocation. The second stage marks use ptes within the page | |
1207 | * tables. | |
1208 | */ | |
1209 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) { | |
1210 | if (pt != ppgtt->scratch_pt) { | |
1211 | WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES)); | |
1212 | continue; | |
1213 | } | |
1214 | ||
1215 | /* We've already allocated a page table */ | |
1216 | WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES)); | |
1217 | ||
1218 | pt = alloc_pt_single(dev); | |
1219 | if (IS_ERR(pt)) { | |
1220 | ret = PTR_ERR(pt); | |
1221 | goto unwind_out; | |
1222 | } | |
1223 | ||
1224 | gen6_initialize_pt(vm, pt); | |
1225 | ||
1226 | ppgtt->pd.page_table[pde] = pt; | |
1227 | set_bit(pde, new_page_tables); | |
72744cb1 | 1228 | trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT); |
4933d519 MT |
1229 | } |
1230 | ||
1231 | start = start_save; | |
1232 | length = length_save; | |
678d96fb BW |
1233 | |
1234 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) { | |
1235 | DECLARE_BITMAP(tmp_bitmap, GEN6_PTES); | |
1236 | ||
1237 | bitmap_zero(tmp_bitmap, GEN6_PTES); | |
1238 | bitmap_set(tmp_bitmap, gen6_pte_index(start), | |
1239 | gen6_pte_count(start, length)); | |
1240 | ||
4933d519 MT |
1241 | if (test_and_clear_bit(pde, new_page_tables)) |
1242 | gen6_write_pde(&ppgtt->pd, pde, pt); | |
1243 | ||
72744cb1 MT |
1244 | trace_i915_page_table_entry_map(vm, pde, pt, |
1245 | gen6_pte_index(start), | |
1246 | gen6_pte_count(start, length), | |
1247 | GEN6_PTES); | |
4933d519 | 1248 | bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes, |
678d96fb BW |
1249 | GEN6_PTES); |
1250 | } | |
1251 | ||
4933d519 MT |
1252 | WARN_ON(!bitmap_empty(new_page_tables, I915_PDES)); |
1253 | ||
1254 | /* Make sure write is complete before other code can use this page | |
1255 | * table. Also require for WC mapped PTEs */ | |
1256 | readl(dev_priv->gtt.gsm); | |
1257 | ||
563222a7 | 1258 | mark_tlbs_dirty(ppgtt); |
678d96fb | 1259 | return 0; |
4933d519 MT |
1260 | |
1261 | unwind_out: | |
1262 | for_each_set_bit(pde, new_page_tables, I915_PDES) { | |
1263 | struct i915_page_table_entry *pt = ppgtt->pd.page_table[pde]; | |
1264 | ||
1265 | ppgtt->pd.page_table[pde] = ppgtt->scratch_pt; | |
1266 | unmap_and_free_pt(pt, vm->dev); | |
1267 | } | |
1268 | ||
1269 | mark_tlbs_dirty(ppgtt); | |
1270 | return ret; | |
678d96fb BW |
1271 | } |
1272 | ||
a00d825d BW |
1273 | static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt) |
1274 | { | |
1275 | int i; | |
3440d265 | 1276 | |
4933d519 MT |
1277 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
1278 | struct i915_page_table_entry *pt = ppgtt->pd.page_table[i]; | |
1279 | ||
1280 | if (pt != ppgtt->scratch_pt) | |
1281 | unmap_and_free_pt(ppgtt->pd.page_table[i], ppgtt->base.dev); | |
1282 | } | |
06fda602 | 1283 | |
4933d519 | 1284 | unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev); |
06fda602 | 1285 | unmap_and_free_pd(&ppgtt->pd); |
3440d265 DV |
1286 | } |
1287 | ||
a00d825d BW |
1288 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
1289 | { | |
1290 | struct i915_hw_ppgtt *ppgtt = | |
1291 | container_of(vm, struct i915_hw_ppgtt, base); | |
1292 | ||
a00d825d BW |
1293 | drm_mm_remove_node(&ppgtt->node); |
1294 | ||
a00d825d BW |
1295 | gen6_ppgtt_free(ppgtt); |
1296 | } | |
1297 | ||
b146520f | 1298 | static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) |
3440d265 | 1299 | { |
853ba5d2 | 1300 | struct drm_device *dev = ppgtt->base.dev; |
1d2a314c | 1301 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3cc1995 | 1302 | bool retried = false; |
b146520f | 1303 | int ret; |
1d2a314c | 1304 | |
c8d4c0d6 BW |
1305 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
1306 | * allocator works in address space sizes, so it's multiplied by page | |
1307 | * size. We allocate at the top of the GTT to avoid fragmentation. | |
1308 | */ | |
1309 | BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm)); | |
4933d519 MT |
1310 | ppgtt->scratch_pt = alloc_pt_single(ppgtt->base.dev); |
1311 | if (IS_ERR(ppgtt->scratch_pt)) | |
1312 | return PTR_ERR(ppgtt->scratch_pt); | |
1313 | ||
1314 | gen6_initialize_pt(&ppgtt->base, ppgtt->scratch_pt); | |
1315 | ||
e3cc1995 | 1316 | alloc: |
c8d4c0d6 BW |
1317 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm, |
1318 | &ppgtt->node, GEN6_PD_SIZE, | |
1319 | GEN6_PD_ALIGN, 0, | |
1320 | 0, dev_priv->gtt.base.total, | |
3e8b5ae9 | 1321 | DRM_MM_TOPDOWN); |
e3cc1995 BW |
1322 | if (ret == -ENOSPC && !retried) { |
1323 | ret = i915_gem_evict_something(dev, &dev_priv->gtt.base, | |
1324 | GEN6_PD_SIZE, GEN6_PD_ALIGN, | |
d23db88c CW |
1325 | I915_CACHE_NONE, |
1326 | 0, dev_priv->gtt.base.total, | |
1327 | 0); | |
e3cc1995 | 1328 | if (ret) |
678d96fb | 1329 | goto err_out; |
e3cc1995 BW |
1330 | |
1331 | retried = true; | |
1332 | goto alloc; | |
1333 | } | |
c8d4c0d6 | 1334 | |
c8c26622 | 1335 | if (ret) |
678d96fb BW |
1336 | goto err_out; |
1337 | ||
c8c26622 | 1338 | |
c8d4c0d6 BW |
1339 | if (ppgtt->node.start < dev_priv->gtt.mappable_end) |
1340 | DRM_DEBUG("Forced to use aperture for PDEs\n"); | |
1d2a314c | 1341 | |
07749ef3 | 1342 | ppgtt->num_pd_entries = I915_PDES; |
c8c26622 | 1343 | return 0; |
678d96fb BW |
1344 | |
1345 | err_out: | |
4933d519 | 1346 | unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev); |
678d96fb | 1347 | return ret; |
b146520f BW |
1348 | } |
1349 | ||
b146520f BW |
1350 | static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) |
1351 | { | |
2f2cf682 | 1352 | return gen6_ppgtt_allocate_page_directories(ppgtt); |
4933d519 | 1353 | } |
06dc68d6 | 1354 | |
4933d519 MT |
1355 | static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt, |
1356 | uint64_t start, uint64_t length) | |
1357 | { | |
1358 | struct i915_page_table_entry *unused; | |
1359 | uint32_t pde, temp; | |
1d2a314c | 1360 | |
4933d519 MT |
1361 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) |
1362 | ppgtt->pd.page_table[pde] = ppgtt->scratch_pt; | |
b146520f BW |
1363 | } |
1364 | ||
4933d519 | 1365 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt, bool aliasing) |
b146520f BW |
1366 | { |
1367 | struct drm_device *dev = ppgtt->base.dev; | |
1368 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1369 | int ret; | |
1370 | ||
1371 | ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; | |
1372 | if (IS_GEN6(dev)) { | |
b146520f BW |
1373 | ppgtt->switch_mm = gen6_mm_switch; |
1374 | } else if (IS_HASWELL(dev)) { | |
b146520f BW |
1375 | ppgtt->switch_mm = hsw_mm_switch; |
1376 | } else if (IS_GEN7(dev)) { | |
b146520f BW |
1377 | ppgtt->switch_mm = gen7_mm_switch; |
1378 | } else | |
1379 | BUG(); | |
1380 | ||
71ba2d64 YZ |
1381 | if (intel_vgpu_active(dev)) |
1382 | ppgtt->switch_mm = vgpu_mm_switch; | |
1383 | ||
b146520f BW |
1384 | ret = gen6_ppgtt_alloc(ppgtt); |
1385 | if (ret) | |
1386 | return ret; | |
1387 | ||
4933d519 MT |
1388 | if (aliasing) { |
1389 | /* preallocate all pts */ | |
1390 | ret = alloc_pt_range(&ppgtt->pd, 0, ppgtt->num_pd_entries, | |
1391 | ppgtt->base.dev); | |
1392 | ||
1393 | if (ret) { | |
1394 | gen6_ppgtt_cleanup(&ppgtt->base); | |
1395 | return ret; | |
1396 | } | |
1397 | } | |
1398 | ||
678d96fb | 1399 | ppgtt->base.allocate_va_range = gen6_alloc_va_range; |
b146520f BW |
1400 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
1401 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
1402 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; | |
b146520f | 1403 | ppgtt->base.start = 0; |
07749ef3 | 1404 | ppgtt->base.total = ppgtt->num_pd_entries * GEN6_PTES * PAGE_SIZE; |
87d60b63 | 1405 | ppgtt->debug_dump = gen6_dump_ppgtt; |
1d2a314c | 1406 | |
7324cc04 | 1407 | ppgtt->pd.pd_offset = |
07749ef3 | 1408 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t); |
1d2a314c | 1409 | |
678d96fb BW |
1410 | ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm + |
1411 | ppgtt->pd.pd_offset / sizeof(gen6_pte_t); | |
1412 | ||
4933d519 MT |
1413 | if (aliasing) |
1414 | ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); | |
1415 | else | |
1416 | gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total); | |
1d2a314c | 1417 | |
678d96fb BW |
1418 | gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total); |
1419 | ||
440fd528 | 1420 | DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n", |
b146520f BW |
1421 | ppgtt->node.size >> 20, |
1422 | ppgtt->node.start / PAGE_SIZE); | |
3440d265 | 1423 | |
fa76da34 | 1424 | DRM_DEBUG("Adding PPGTT at offset %x\n", |
7324cc04 | 1425 | ppgtt->pd.pd_offset << 10); |
fa76da34 | 1426 | |
b146520f | 1427 | return 0; |
3440d265 DV |
1428 | } |
1429 | ||
4933d519 MT |
1430 | static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt, |
1431 | bool aliasing) | |
3440d265 DV |
1432 | { |
1433 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3440d265 | 1434 | |
853ba5d2 | 1435 | ppgtt->base.dev = dev; |
8407bb91 | 1436 | ppgtt->base.scratch = dev_priv->gtt.base.scratch; |
3440d265 | 1437 | |
3ed124b2 | 1438 | if (INTEL_INFO(dev)->gen < 8) |
4933d519 | 1439 | return gen6_ppgtt_init(ppgtt, aliasing); |
3ed124b2 | 1440 | else |
1eb0f006 | 1441 | return gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total); |
fa76da34 DV |
1442 | } |
1443 | int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) | |
1444 | { | |
1445 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1446 | int ret = 0; | |
3ed124b2 | 1447 | |
4933d519 | 1448 | ret = __hw_ppgtt_init(dev, ppgtt, false); |
fa76da34 | 1449 | if (ret == 0) { |
c7c48dfd | 1450 | kref_init(&ppgtt->ref); |
93bd8649 BW |
1451 | drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, |
1452 | ppgtt->base.total); | |
7e0d96bc | 1453 | i915_init_vm(dev_priv, &ppgtt->base); |
93bd8649 | 1454 | } |
1d2a314c DV |
1455 | |
1456 | return ret; | |
1457 | } | |
1458 | ||
82460d97 DV |
1459 | int i915_ppgtt_init_hw(struct drm_device *dev) |
1460 | { | |
1461 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1462 | struct intel_engine_cs *ring; | |
1463 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1464 | int i, ret = 0; | |
1465 | ||
671b5013 TD |
1466 | /* In the case of execlists, PPGTT is enabled by the context descriptor |
1467 | * and the PDPs are contained within the context itself. We don't | |
1468 | * need to do anything here. */ | |
1469 | if (i915.enable_execlists) | |
1470 | return 0; | |
1471 | ||
82460d97 DV |
1472 | if (!USES_PPGTT(dev)) |
1473 | return 0; | |
1474 | ||
1475 | if (IS_GEN6(dev)) | |
1476 | gen6_ppgtt_enable(dev); | |
1477 | else if (IS_GEN7(dev)) | |
1478 | gen7_ppgtt_enable(dev); | |
1479 | else if (INTEL_INFO(dev)->gen >= 8) | |
1480 | gen8_ppgtt_enable(dev); | |
1481 | else | |
5f77eeb0 | 1482 | MISSING_CASE(INTEL_INFO(dev)->gen); |
82460d97 DV |
1483 | |
1484 | if (ppgtt) { | |
1485 | for_each_ring(ring, dev_priv, i) { | |
6689c167 | 1486 | ret = ppgtt->switch_mm(ppgtt, ring); |
82460d97 DV |
1487 | if (ret != 0) |
1488 | return ret; | |
7e0d96bc | 1489 | } |
93bd8649 | 1490 | } |
1d2a314c DV |
1491 | |
1492 | return ret; | |
1493 | } | |
4d884705 DV |
1494 | struct i915_hw_ppgtt * |
1495 | i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv) | |
1496 | { | |
1497 | struct i915_hw_ppgtt *ppgtt; | |
1498 | int ret; | |
1499 | ||
1500 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
1501 | if (!ppgtt) | |
1502 | return ERR_PTR(-ENOMEM); | |
1503 | ||
1504 | ret = i915_ppgtt_init(dev, ppgtt); | |
1505 | if (ret) { | |
1506 | kfree(ppgtt); | |
1507 | return ERR_PTR(ret); | |
1508 | } | |
1509 | ||
1510 | ppgtt->file_priv = fpriv; | |
1511 | ||
198c974d DCS |
1512 | trace_i915_ppgtt_create(&ppgtt->base); |
1513 | ||
4d884705 DV |
1514 | return ppgtt; |
1515 | } | |
1516 | ||
ee960be7 DV |
1517 | void i915_ppgtt_release(struct kref *kref) |
1518 | { | |
1519 | struct i915_hw_ppgtt *ppgtt = | |
1520 | container_of(kref, struct i915_hw_ppgtt, ref); | |
1521 | ||
198c974d DCS |
1522 | trace_i915_ppgtt_release(&ppgtt->base); |
1523 | ||
ee960be7 DV |
1524 | /* vmas should already be unbound */ |
1525 | WARN_ON(!list_empty(&ppgtt->base.active_list)); | |
1526 | WARN_ON(!list_empty(&ppgtt->base.inactive_list)); | |
1527 | ||
19dd120c DV |
1528 | list_del(&ppgtt->base.global_link); |
1529 | drm_mm_takedown(&ppgtt->base.mm); | |
1530 | ||
ee960be7 DV |
1531 | ppgtt->base.cleanup(&ppgtt->base); |
1532 | kfree(ppgtt); | |
1533 | } | |
1d2a314c | 1534 | |
7e0d96bc | 1535 | static void |
6f65e29a BW |
1536 | ppgtt_bind_vma(struct i915_vma *vma, |
1537 | enum i915_cache_level cache_level, | |
1538 | u32 flags) | |
1d2a314c | 1539 | { |
24f3a8cf AG |
1540 | /* Currently applicable only to VLV */ |
1541 | if (vma->obj->gt_ro) | |
1542 | flags |= PTE_READ_ONLY; | |
1543 | ||
782f1495 | 1544 | vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start, |
24f3a8cf | 1545 | cache_level, flags); |
1d2a314c DV |
1546 | } |
1547 | ||
7e0d96bc | 1548 | static void ppgtt_unbind_vma(struct i915_vma *vma) |
7bddb01f | 1549 | { |
6f65e29a | 1550 | vma->vm->clear_range(vma->vm, |
782f1495 BW |
1551 | vma->node.start, |
1552 | vma->obj->base.size, | |
6f65e29a | 1553 | true); |
7bddb01f DV |
1554 | } |
1555 | ||
a81cc00c BW |
1556 | extern int intel_iommu_gfx_mapped; |
1557 | /* Certain Gen5 chipsets require require idling the GPU before | |
1558 | * unmapping anything from the GTT when VT-d is enabled. | |
1559 | */ | |
1560 | static inline bool needs_idle_maps(struct drm_device *dev) | |
1561 | { | |
1562 | #ifdef CONFIG_INTEL_IOMMU | |
1563 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
1564 | * was loaded first. | |
1565 | */ | |
1566 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
1567 | return true; | |
1568 | #endif | |
1569 | return false; | |
1570 | } | |
1571 | ||
5c042287 BW |
1572 | static bool do_idling(struct drm_i915_private *dev_priv) |
1573 | { | |
1574 | bool ret = dev_priv->mm.interruptible; | |
1575 | ||
a81cc00c | 1576 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 1577 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 1578 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
1579 | DRM_ERROR("Couldn't idle GPU\n"); |
1580 | /* Wait a bit, in hopes it avoids the hang */ | |
1581 | udelay(10); | |
1582 | } | |
1583 | } | |
1584 | ||
1585 | return ret; | |
1586 | } | |
1587 | ||
1588 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
1589 | { | |
a81cc00c | 1590 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
1591 | dev_priv->mm.interruptible = interruptible; |
1592 | } | |
1593 | ||
828c7908 BW |
1594 | void i915_check_and_clear_faults(struct drm_device *dev) |
1595 | { | |
1596 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 1597 | struct intel_engine_cs *ring; |
828c7908 BW |
1598 | int i; |
1599 | ||
1600 | if (INTEL_INFO(dev)->gen < 6) | |
1601 | return; | |
1602 | ||
1603 | for_each_ring(ring, dev_priv, i) { | |
1604 | u32 fault_reg; | |
1605 | fault_reg = I915_READ(RING_FAULT_REG(ring)); | |
1606 | if (fault_reg & RING_FAULT_VALID) { | |
1607 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
59a5d290 | 1608 | "\tAddr: 0x%08lx\n" |
828c7908 BW |
1609 | "\tAddress space: %s\n" |
1610 | "\tSource ID: %d\n" | |
1611 | "\tType: %d\n", | |
1612 | fault_reg & PAGE_MASK, | |
1613 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
1614 | RING_FAULT_SRCID(fault_reg), | |
1615 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
1616 | I915_WRITE(RING_FAULT_REG(ring), | |
1617 | fault_reg & ~RING_FAULT_VALID); | |
1618 | } | |
1619 | } | |
1620 | POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); | |
1621 | } | |
1622 | ||
91e56499 CW |
1623 | static void i915_ggtt_flush(struct drm_i915_private *dev_priv) |
1624 | { | |
1625 | if (INTEL_INFO(dev_priv->dev)->gen < 6) { | |
1626 | intel_gtt_chipset_flush(); | |
1627 | } else { | |
1628 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1629 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
1630 | } | |
1631 | } | |
1632 | ||
828c7908 BW |
1633 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) |
1634 | { | |
1635 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1636 | ||
1637 | /* Don't bother messing with faults pre GEN6 as we have little | |
1638 | * documentation supporting that it's a good idea. | |
1639 | */ | |
1640 | if (INTEL_INFO(dev)->gen < 6) | |
1641 | return; | |
1642 | ||
1643 | i915_check_and_clear_faults(dev); | |
1644 | ||
1645 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, | |
782f1495 BW |
1646 | dev_priv->gtt.base.start, |
1647 | dev_priv->gtt.base.total, | |
e568af1c | 1648 | true); |
91e56499 CW |
1649 | |
1650 | i915_ggtt_flush(dev_priv); | |
828c7908 BW |
1651 | } |
1652 | ||
76aaf220 DV |
1653 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
1654 | { | |
1655 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 1656 | struct drm_i915_gem_object *obj; |
80da2161 | 1657 | struct i915_address_space *vm; |
76aaf220 | 1658 | |
828c7908 BW |
1659 | i915_check_and_clear_faults(dev); |
1660 | ||
bee4a186 | 1661 | /* First fill our portion of the GTT with scratch pages */ |
853ba5d2 | 1662 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
782f1495 BW |
1663 | dev_priv->gtt.base.start, |
1664 | dev_priv->gtt.base.total, | |
828c7908 | 1665 | true); |
bee4a186 | 1666 | |
35c20a60 | 1667 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6f65e29a BW |
1668 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, |
1669 | &dev_priv->gtt.base); | |
1670 | if (!vma) | |
1671 | continue; | |
1672 | ||
2c22569b | 1673 | i915_gem_clflush_object(obj, obj->pin_display); |
6f65e29a BW |
1674 | /* The bind_vma code tries to be smart about tracking mappings. |
1675 | * Unfortunately above, we've just wiped out the mappings | |
1676 | * without telling our object about it. So we need to fake it. | |
fe14d5f4 TU |
1677 | * |
1678 | * Bind is not expected to fail since this is only called on | |
1679 | * resume and assumption is all requirements exist already. | |
6f65e29a | 1680 | */ |
aff43766 | 1681 | vma->bound &= ~GLOBAL_BIND; |
fe14d5f4 | 1682 | WARN_ON(i915_vma_bind(vma, obj->cache_level, GLOBAL_BIND)); |
76aaf220 DV |
1683 | } |
1684 | ||
80da2161 | 1685 | |
a2319c08 | 1686 | if (INTEL_INFO(dev)->gen >= 8) { |
ee0ce478 VS |
1687 | if (IS_CHERRYVIEW(dev)) |
1688 | chv_setup_private_ppat(dev_priv); | |
1689 | else | |
1690 | bdw_setup_private_ppat(dev_priv); | |
1691 | ||
80da2161 | 1692 | return; |
a2319c08 | 1693 | } |
80da2161 | 1694 | |
678d96fb BW |
1695 | if (USES_PPGTT(dev)) { |
1696 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { | |
1697 | /* TODO: Perhaps it shouldn't be gen6 specific */ | |
1698 | ||
1699 | struct i915_hw_ppgtt *ppgtt = | |
1700 | container_of(vm, struct i915_hw_ppgtt, | |
1701 | base); | |
80da2161 | 1702 | |
678d96fb BW |
1703 | if (i915_is_ggtt(vm)) |
1704 | ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1705 | ||
1706 | gen6_write_page_range(dev_priv, &ppgtt->pd, | |
1707 | 0, ppgtt->base.total); | |
1708 | } | |
76aaf220 DV |
1709 | } |
1710 | ||
91e56499 | 1711 | i915_ggtt_flush(dev_priv); |
76aaf220 | 1712 | } |
7c2e6fdf | 1713 | |
74163907 | 1714 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 1715 | { |
9da3da66 | 1716 | if (obj->has_dma_mapping) |
74163907 | 1717 | return 0; |
9da3da66 CW |
1718 | |
1719 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
1720 | obj->pages->sgl, obj->pages->nents, | |
1721 | PCI_DMA_BIDIRECTIONAL)) | |
1722 | return -ENOSPC; | |
1723 | ||
1724 | return 0; | |
7c2e6fdf DV |
1725 | } |
1726 | ||
07749ef3 | 1727 | static inline void gen8_set_pte(void __iomem *addr, gen8_pte_t pte) |
94ec8f61 BW |
1728 | { |
1729 | #ifdef writeq | |
1730 | writeq(pte, addr); | |
1731 | #else | |
1732 | iowrite32((u32)pte, addr); | |
1733 | iowrite32(pte >> 32, addr + 4); | |
1734 | #endif | |
1735 | } | |
1736 | ||
1737 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, | |
1738 | struct sg_table *st, | |
782f1495 | 1739 | uint64_t start, |
24f3a8cf | 1740 | enum i915_cache_level level, u32 unused) |
94ec8f61 BW |
1741 | { |
1742 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 | 1743 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1744 | gen8_pte_t __iomem *gtt_entries = |
1745 | (gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
94ec8f61 BW |
1746 | int i = 0; |
1747 | struct sg_page_iter sg_iter; | |
57007df7 | 1748 | dma_addr_t addr = 0; /* shut up gcc */ |
94ec8f61 BW |
1749 | |
1750 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { | |
1751 | addr = sg_dma_address(sg_iter.sg) + | |
1752 | (sg_iter.sg_pgoffset << PAGE_SHIFT); | |
1753 | gen8_set_pte(>t_entries[i], | |
1754 | gen8_pte_encode(addr, level, true)); | |
1755 | i++; | |
1756 | } | |
1757 | ||
1758 | /* | |
1759 | * XXX: This serves as a posting read to make sure that the PTE has | |
1760 | * actually been updated. There is some concern that even though | |
1761 | * registers and PTEs are within the same BAR that they are potentially | |
1762 | * of NUMA access patterns. Therefore, even with the way we assume | |
1763 | * hardware should work, we must keep this posting read for paranoia. | |
1764 | */ | |
1765 | if (i != 0) | |
1766 | WARN_ON(readq(>t_entries[i-1]) | |
1767 | != gen8_pte_encode(addr, level, true)); | |
1768 | ||
94ec8f61 BW |
1769 | /* This next bit makes the above posting read even more important. We |
1770 | * want to flush the TLBs only after we're certain all the PTE updates | |
1771 | * have finished. | |
1772 | */ | |
1773 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1774 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
94ec8f61 BW |
1775 | } |
1776 | ||
e76e9aeb BW |
1777 | /* |
1778 | * Binds an object into the global gtt with the specified cache level. The object | |
1779 | * will be accessible to the GPU via commands whose operands reference offsets | |
1780 | * within the global GTT as well as accessible by the GPU through the GMADR | |
1781 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
1782 | */ | |
853ba5d2 | 1783 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 | 1784 | struct sg_table *st, |
782f1495 | 1785 | uint64_t start, |
24f3a8cf | 1786 | enum i915_cache_level level, u32 flags) |
e76e9aeb | 1787 | { |
853ba5d2 | 1788 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 | 1789 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1790 | gen6_pte_t __iomem *gtt_entries = |
1791 | (gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
1792 | int i = 0; |
1793 | struct sg_page_iter sg_iter; | |
57007df7 | 1794 | dma_addr_t addr = 0; |
e76e9aeb | 1795 | |
6e995e23 | 1796 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 1797 | addr = sg_page_iter_dma_address(&sg_iter); |
24f3a8cf | 1798 | iowrite32(vm->pte_encode(addr, level, true, flags), >t_entries[i]); |
6e995e23 | 1799 | i++; |
e76e9aeb BW |
1800 | } |
1801 | ||
e76e9aeb BW |
1802 | /* XXX: This serves as a posting read to make sure that the PTE has |
1803 | * actually been updated. There is some concern that even though | |
1804 | * registers and PTEs are within the same BAR that they are potentially | |
1805 | * of NUMA access patterns. Therefore, even with the way we assume | |
1806 | * hardware should work, we must keep this posting read for paranoia. | |
1807 | */ | |
57007df7 PM |
1808 | if (i != 0) { |
1809 | unsigned long gtt = readl(>t_entries[i-1]); | |
1810 | WARN_ON(gtt != vm->pte_encode(addr, level, true, flags)); | |
1811 | } | |
0f9b91c7 BW |
1812 | |
1813 | /* This next bit makes the above posting read even more important. We | |
1814 | * want to flush the TLBs only after we're certain all the PTE updates | |
1815 | * have finished. | |
1816 | */ | |
1817 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1818 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
1819 | } |
1820 | ||
94ec8f61 | 1821 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1822 | uint64_t start, |
1823 | uint64_t length, | |
94ec8f61 BW |
1824 | bool use_scratch) |
1825 | { | |
1826 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 BW |
1827 | unsigned first_entry = start >> PAGE_SHIFT; |
1828 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1829 | gen8_pte_t scratch_pte, __iomem *gtt_base = |
1830 | (gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
94ec8f61 BW |
1831 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
1832 | int i; | |
1833 | ||
1834 | if (WARN(num_entries > max_entries, | |
1835 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1836 | first_entry, num_entries, max_entries)) | |
1837 | num_entries = max_entries; | |
1838 | ||
1839 | scratch_pte = gen8_pte_encode(vm->scratch.addr, | |
1840 | I915_CACHE_LLC, | |
1841 | use_scratch); | |
1842 | for (i = 0; i < num_entries; i++) | |
1843 | gen8_set_pte(>t_base[i], scratch_pte); | |
1844 | readl(gtt_base); | |
1845 | } | |
1846 | ||
853ba5d2 | 1847 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1848 | uint64_t start, |
1849 | uint64_t length, | |
828c7908 | 1850 | bool use_scratch) |
7faf1ab2 | 1851 | { |
853ba5d2 | 1852 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 BW |
1853 | unsigned first_entry = start >> PAGE_SHIFT; |
1854 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1855 | gen6_pte_t scratch_pte, __iomem *gtt_base = |
1856 | (gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 1857 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
1858 | int i; |
1859 | ||
1860 | if (WARN(num_entries > max_entries, | |
1861 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1862 | first_entry, num_entries, max_entries)) | |
1863 | num_entries = max_entries; | |
1864 | ||
24f3a8cf | 1865 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch, 0); |
828c7908 | 1866 | |
7faf1ab2 DV |
1867 | for (i = 0; i < num_entries; i++) |
1868 | iowrite32(scratch_pte, >t_base[i]); | |
1869 | readl(gtt_base); | |
1870 | } | |
1871 | ||
6f65e29a BW |
1872 | |
1873 | static void i915_ggtt_bind_vma(struct i915_vma *vma, | |
1874 | enum i915_cache_level cache_level, | |
1875 | u32 unused) | |
7faf1ab2 | 1876 | { |
6f65e29a | 1877 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; |
7faf1ab2 DV |
1878 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? |
1879 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
1880 | ||
6f65e29a | 1881 | BUG_ON(!i915_is_ggtt(vma->vm)); |
fe14d5f4 | 1882 | intel_gtt_insert_sg_entries(vma->ggtt_view.pages, entry, flags); |
aff43766 | 1883 | vma->bound = GLOBAL_BIND; |
7faf1ab2 DV |
1884 | } |
1885 | ||
853ba5d2 | 1886 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1887 | uint64_t start, |
1888 | uint64_t length, | |
828c7908 | 1889 | bool unused) |
7faf1ab2 | 1890 | { |
782f1495 BW |
1891 | unsigned first_entry = start >> PAGE_SHIFT; |
1892 | unsigned num_entries = length >> PAGE_SHIFT; | |
7faf1ab2 DV |
1893 | intel_gtt_clear_range(first_entry, num_entries); |
1894 | } | |
1895 | ||
6f65e29a BW |
1896 | static void i915_ggtt_unbind_vma(struct i915_vma *vma) |
1897 | { | |
1898 | const unsigned int first = vma->node.start >> PAGE_SHIFT; | |
1899 | const unsigned int size = vma->obj->base.size >> PAGE_SHIFT; | |
7faf1ab2 | 1900 | |
6f65e29a | 1901 | BUG_ON(!i915_is_ggtt(vma->vm)); |
aff43766 | 1902 | vma->bound = 0; |
6f65e29a BW |
1903 | intel_gtt_clear_range(first, size); |
1904 | } | |
7faf1ab2 | 1905 | |
6f65e29a BW |
1906 | static void ggtt_bind_vma(struct i915_vma *vma, |
1907 | enum i915_cache_level cache_level, | |
1908 | u32 flags) | |
d5bd1449 | 1909 | { |
6f65e29a | 1910 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1911 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1912 | struct drm_i915_gem_object *obj = vma->obj; |
ec7adb6e | 1913 | struct sg_table *pages = obj->pages; |
7faf1ab2 | 1914 | |
24f3a8cf AG |
1915 | /* Currently applicable only to VLV */ |
1916 | if (obj->gt_ro) | |
1917 | flags |= PTE_READ_ONLY; | |
1918 | ||
ec7adb6e JL |
1919 | if (i915_is_ggtt(vma->vm)) |
1920 | pages = vma->ggtt_view.pages; | |
1921 | ||
6f65e29a BW |
1922 | /* If there is no aliasing PPGTT, or the caller needs a global mapping, |
1923 | * or we have a global mapping already but the cacheability flags have | |
1924 | * changed, set the global PTEs. | |
1925 | * | |
1926 | * If there is an aliasing PPGTT it is anecdotally faster, so use that | |
1927 | * instead if none of the above hold true. | |
1928 | * | |
1929 | * NB: A global mapping should only be needed for special regions like | |
1930 | * "gtt mappable", SNB errata, or if specified via special execbuf | |
1931 | * flags. At all other times, the GPU will use the aliasing PPGTT. | |
1932 | */ | |
1933 | if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) { | |
aff43766 | 1934 | if (!(vma->bound & GLOBAL_BIND) || |
6f65e29a | 1935 | (cache_level != obj->cache_level)) { |
ec7adb6e | 1936 | vma->vm->insert_entries(vma->vm, pages, |
782f1495 | 1937 | vma->node.start, |
24f3a8cf | 1938 | cache_level, flags); |
aff43766 | 1939 | vma->bound |= GLOBAL_BIND; |
6f65e29a BW |
1940 | } |
1941 | } | |
d5bd1449 | 1942 | |
6f65e29a | 1943 | if (dev_priv->mm.aliasing_ppgtt && |
aff43766 | 1944 | (!(vma->bound & LOCAL_BIND) || |
6f65e29a BW |
1945 | (cache_level != obj->cache_level))) { |
1946 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; | |
ec7adb6e | 1947 | appgtt->base.insert_entries(&appgtt->base, pages, |
782f1495 | 1948 | vma->node.start, |
24f3a8cf | 1949 | cache_level, flags); |
aff43766 | 1950 | vma->bound |= LOCAL_BIND; |
6f65e29a | 1951 | } |
d5bd1449 CW |
1952 | } |
1953 | ||
6f65e29a | 1954 | static void ggtt_unbind_vma(struct i915_vma *vma) |
74163907 | 1955 | { |
6f65e29a | 1956 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1957 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1958 | struct drm_i915_gem_object *obj = vma->obj; |
6f65e29a | 1959 | |
aff43766 | 1960 | if (vma->bound & GLOBAL_BIND) { |
782f1495 BW |
1961 | vma->vm->clear_range(vma->vm, |
1962 | vma->node.start, | |
1963 | obj->base.size, | |
6f65e29a | 1964 | true); |
aff43766 | 1965 | vma->bound &= ~GLOBAL_BIND; |
6f65e29a | 1966 | } |
74898d7e | 1967 | |
aff43766 | 1968 | if (vma->bound & LOCAL_BIND) { |
6f65e29a BW |
1969 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; |
1970 | appgtt->base.clear_range(&appgtt->base, | |
782f1495 BW |
1971 | vma->node.start, |
1972 | obj->base.size, | |
6f65e29a | 1973 | true); |
aff43766 | 1974 | vma->bound &= ~LOCAL_BIND; |
6f65e29a | 1975 | } |
74163907 DV |
1976 | } |
1977 | ||
1978 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 1979 | { |
5c042287 BW |
1980 | struct drm_device *dev = obj->base.dev; |
1981 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1982 | bool interruptible; | |
1983 | ||
1984 | interruptible = do_idling(dev_priv); | |
1985 | ||
9da3da66 CW |
1986 | if (!obj->has_dma_mapping) |
1987 | dma_unmap_sg(&dev->pdev->dev, | |
1988 | obj->pages->sgl, obj->pages->nents, | |
1989 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
1990 | |
1991 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 1992 | } |
644ec02b | 1993 | |
42d6ab48 CW |
1994 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
1995 | unsigned long color, | |
440fd528 TR |
1996 | u64 *start, |
1997 | u64 *end) | |
42d6ab48 CW |
1998 | { |
1999 | if (node->color != color) | |
2000 | *start += 4096; | |
2001 | ||
2002 | if (!list_empty(&node->node_list)) { | |
2003 | node = list_entry(node->node_list.next, | |
2004 | struct drm_mm_node, | |
2005 | node_list); | |
2006 | if (node->allocated && node->color != color) | |
2007 | *end -= 4096; | |
2008 | } | |
2009 | } | |
fbe5d36e | 2010 | |
f548c0e9 DV |
2011 | static int i915_gem_setup_global_gtt(struct drm_device *dev, |
2012 | unsigned long start, | |
2013 | unsigned long mappable_end, | |
2014 | unsigned long end) | |
644ec02b | 2015 | { |
e78891ca BW |
2016 | /* Let GEM Manage all of the aperture. |
2017 | * | |
2018 | * However, leave one page at the end still bound to the scratch page. | |
2019 | * There are a number of places where the hardware apparently prefetches | |
2020 | * past the end of the object, and we've seen multiple hangs with the | |
2021 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
2022 | * aperture. One page should be enough to keep any prefetching inside | |
2023 | * of the aperture. | |
2024 | */ | |
40d74980 BW |
2025 | struct drm_i915_private *dev_priv = dev->dev_private; |
2026 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; | |
ed2f3452 CW |
2027 | struct drm_mm_node *entry; |
2028 | struct drm_i915_gem_object *obj; | |
2029 | unsigned long hole_start, hole_end; | |
fa76da34 | 2030 | int ret; |
644ec02b | 2031 | |
35451cb6 BW |
2032 | BUG_ON(mappable_end > end); |
2033 | ||
ed2f3452 | 2034 | /* Subtract the guard page ... */ |
40d74980 | 2035 | drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); |
5dda8fa3 YZ |
2036 | |
2037 | dev_priv->gtt.base.start = start; | |
2038 | dev_priv->gtt.base.total = end - start; | |
2039 | ||
2040 | if (intel_vgpu_active(dev)) { | |
2041 | ret = intel_vgt_balloon(dev); | |
2042 | if (ret) | |
2043 | return ret; | |
2044 | } | |
2045 | ||
42d6ab48 | 2046 | if (!HAS_LLC(dev)) |
93bd8649 | 2047 | dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; |
644ec02b | 2048 | |
ed2f3452 | 2049 | /* Mark any preallocated objects as occupied */ |
35c20a60 | 2050 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
40d74980 | 2051 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
fa76da34 | 2052 | |
edd41a87 | 2053 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
c6cfb325 BW |
2054 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
2055 | ||
2056 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); | |
40d74980 | 2057 | ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); |
6c5566a8 DV |
2058 | if (ret) { |
2059 | DRM_DEBUG_KMS("Reservation failed: %i\n", ret); | |
2060 | return ret; | |
2061 | } | |
aff43766 | 2062 | vma->bound |= GLOBAL_BIND; |
ed2f3452 CW |
2063 | } |
2064 | ||
ed2f3452 | 2065 | /* Clear any non-preallocated blocks */ |
40d74980 | 2066 | drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { |
ed2f3452 CW |
2067 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
2068 | hole_start, hole_end); | |
782f1495 BW |
2069 | ggtt_vm->clear_range(ggtt_vm, hole_start, |
2070 | hole_end - hole_start, true); | |
ed2f3452 CW |
2071 | } |
2072 | ||
2073 | /* And finally clear the reserved guard page */ | |
782f1495 | 2074 | ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true); |
6c5566a8 | 2075 | |
fa76da34 DV |
2076 | if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) { |
2077 | struct i915_hw_ppgtt *ppgtt; | |
2078 | ||
2079 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
2080 | if (!ppgtt) | |
2081 | return -ENOMEM; | |
2082 | ||
4933d519 MT |
2083 | ret = __hw_ppgtt_init(dev, ppgtt, true); |
2084 | if (ret) { | |
2085 | kfree(ppgtt); | |
fa76da34 | 2086 | return ret; |
4933d519 | 2087 | } |
fa76da34 DV |
2088 | |
2089 | dev_priv->mm.aliasing_ppgtt = ppgtt; | |
2090 | } | |
2091 | ||
6c5566a8 | 2092 | return 0; |
e76e9aeb BW |
2093 | } |
2094 | ||
d7e5008f BW |
2095 | void i915_gem_init_global_gtt(struct drm_device *dev) |
2096 | { | |
2097 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2098 | unsigned long gtt_size, mappable_size; | |
d7e5008f | 2099 | |
853ba5d2 | 2100 | gtt_size = dev_priv->gtt.base.total; |
93d18799 | 2101 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f | 2102 | |
e78891ca | 2103 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
2104 | } |
2105 | ||
90d0a0e8 DV |
2106 | void i915_global_gtt_cleanup(struct drm_device *dev) |
2107 | { | |
2108 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2109 | struct i915_address_space *vm = &dev_priv->gtt.base; | |
2110 | ||
70e32544 DV |
2111 | if (dev_priv->mm.aliasing_ppgtt) { |
2112 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2113 | ||
2114 | ppgtt->base.cleanup(&ppgtt->base); | |
2115 | } | |
2116 | ||
90d0a0e8 | 2117 | if (drm_mm_initialized(&vm->mm)) { |
5dda8fa3 YZ |
2118 | if (intel_vgpu_active(dev)) |
2119 | intel_vgt_deballoon(); | |
2120 | ||
90d0a0e8 DV |
2121 | drm_mm_takedown(&vm->mm); |
2122 | list_del(&vm->global_link); | |
2123 | } | |
2124 | ||
2125 | vm->cleanup(vm); | |
2126 | } | |
70e32544 | 2127 | |
e76e9aeb BW |
2128 | static int setup_scratch_page(struct drm_device *dev) |
2129 | { | |
2130 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2131 | struct page *page; | |
2132 | dma_addr_t dma_addr; | |
2133 | ||
2134 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
2135 | if (page == NULL) | |
2136 | return -ENOMEM; | |
e76e9aeb BW |
2137 | set_pages_uc(page, 1); |
2138 | ||
2139 | #ifdef CONFIG_INTEL_IOMMU | |
2140 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
2141 | PCI_DMA_BIDIRECTIONAL); | |
2142 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) | |
2143 | return -EINVAL; | |
2144 | #else | |
2145 | dma_addr = page_to_phys(page); | |
2146 | #endif | |
853ba5d2 BW |
2147 | dev_priv->gtt.base.scratch.page = page; |
2148 | dev_priv->gtt.base.scratch.addr = dma_addr; | |
e76e9aeb BW |
2149 | |
2150 | return 0; | |
2151 | } | |
2152 | ||
2153 | static void teardown_scratch_page(struct drm_device *dev) | |
2154 | { | |
2155 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 BW |
2156 | struct page *page = dev_priv->gtt.base.scratch.page; |
2157 | ||
2158 | set_pages_wb(page, 1); | |
2159 | pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr, | |
e76e9aeb | 2160 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
853ba5d2 | 2161 | __free_page(page); |
e76e9aeb BW |
2162 | } |
2163 | ||
2164 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) | |
2165 | { | |
2166 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
2167 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
2168 | return snb_gmch_ctl << 20; | |
2169 | } | |
2170 | ||
9459d252 BW |
2171 | static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
2172 | { | |
2173 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
2174 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
2175 | if (bdw_gmch_ctl) | |
2176 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
562d55d9 BW |
2177 | |
2178 | #ifdef CONFIG_X86_32 | |
2179 | /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */ | |
2180 | if (bdw_gmch_ctl > 4) | |
2181 | bdw_gmch_ctl = 4; | |
2182 | #endif | |
2183 | ||
9459d252 BW |
2184 | return bdw_gmch_ctl << 20; |
2185 | } | |
2186 | ||
d7f25f23 DL |
2187 | static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) |
2188 | { | |
2189 | gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT; | |
2190 | gmch_ctrl &= SNB_GMCH_GGMS_MASK; | |
2191 | ||
2192 | if (gmch_ctrl) | |
2193 | return 1 << (20 + gmch_ctrl); | |
2194 | ||
2195 | return 0; | |
2196 | } | |
2197 | ||
baa09f5f | 2198 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2199 | { |
2200 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
2201 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
2202 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
2203 | } | |
2204 | ||
9459d252 BW |
2205 | static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
2206 | { | |
2207 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2208 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2209 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
2210 | } | |
2211 | ||
d7f25f23 DL |
2212 | static size_t chv_get_stolen_size(u16 gmch_ctrl) |
2213 | { | |
2214 | gmch_ctrl >>= SNB_GMCH_GMS_SHIFT; | |
2215 | gmch_ctrl &= SNB_GMCH_GMS_MASK; | |
2216 | ||
2217 | /* | |
2218 | * 0x0 to 0x10: 32MB increments starting at 0MB | |
2219 | * 0x11 to 0x16: 4MB increments starting at 8MB | |
2220 | * 0x17 to 0x1d: 4MB increments start at 36MB | |
2221 | */ | |
2222 | if (gmch_ctrl < 0x11) | |
2223 | return gmch_ctrl << 25; | |
2224 | else if (gmch_ctrl < 0x17) | |
2225 | return (gmch_ctrl - 0x11 + 2) << 22; | |
2226 | else | |
2227 | return (gmch_ctrl - 0x17 + 9) << 22; | |
2228 | } | |
2229 | ||
66375014 DL |
2230 | static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl) |
2231 | { | |
2232 | gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2233 | gen9_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2234 | ||
2235 | if (gen9_gmch_ctl < 0xf0) | |
2236 | return gen9_gmch_ctl << 25; /* 32 MB units */ | |
2237 | else | |
2238 | /* 4MB increments starting at 0xf0 for 4MB */ | |
2239 | return (gen9_gmch_ctl - 0xf0 + 1) << 22; | |
2240 | } | |
2241 | ||
63340133 BW |
2242 | static int ggtt_probe_common(struct drm_device *dev, |
2243 | size_t gtt_size) | |
2244 | { | |
2245 | struct drm_i915_private *dev_priv = dev->dev_private; | |
21c34607 | 2246 | phys_addr_t gtt_phys_addr; |
63340133 BW |
2247 | int ret; |
2248 | ||
2249 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
21c34607 | 2250 | gtt_phys_addr = pci_resource_start(dev->pdev, 0) + |
63340133 BW |
2251 | (pci_resource_len(dev->pdev, 0) / 2); |
2252 | ||
21c34607 | 2253 | dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size); |
63340133 BW |
2254 | if (!dev_priv->gtt.gsm) { |
2255 | DRM_ERROR("Failed to map the gtt page table\n"); | |
2256 | return -ENOMEM; | |
2257 | } | |
2258 | ||
2259 | ret = setup_scratch_page(dev); | |
2260 | if (ret) { | |
2261 | DRM_ERROR("Scratch setup failed\n"); | |
2262 | /* iounmap will also get called at remove, but meh */ | |
2263 | iounmap(dev_priv->gtt.gsm); | |
2264 | } | |
2265 | ||
2266 | return ret; | |
2267 | } | |
2268 | ||
fbe5d36e BW |
2269 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
2270 | * bits. When using advanced contexts each context stores its own PAT, but | |
2271 | * writing this data shouldn't be harmful even in those cases. */ | |
ee0ce478 | 2272 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) |
fbe5d36e | 2273 | { |
fbe5d36e BW |
2274 | uint64_t pat; |
2275 | ||
2276 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
2277 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
2278 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
2279 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
2280 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
2281 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
2282 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
2283 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
2284 | ||
d6a8b72e RV |
2285 | if (!USES_PPGTT(dev_priv->dev)) |
2286 | /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry, | |
2287 | * so RTL will always use the value corresponding to | |
2288 | * pat_sel = 000". | |
2289 | * So let's disable cache for GGTT to avoid screen corruptions. | |
2290 | * MOCS still can be used though. | |
2291 | * - System agent ggtt writes (i.e. cpu gtt mmaps) already work | |
2292 | * before this patch, i.e. the same uncached + snooping access | |
2293 | * like on gen6/7 seems to be in effect. | |
2294 | * - So this just fixes blitter/render access. Again it looks | |
2295 | * like it's not just uncached access, but uncached + snooping. | |
2296 | * So we can still hold onto all our assumptions wrt cpu | |
2297 | * clflushing on LLC machines. | |
2298 | */ | |
2299 | pat = GEN8_PPAT(0, GEN8_PPAT_UC); | |
2300 | ||
fbe5d36e BW |
2301 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b |
2302 | * write would work. */ | |
2303 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
2304 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
2305 | } | |
2306 | ||
ee0ce478 VS |
2307 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) |
2308 | { | |
2309 | uint64_t pat; | |
2310 | ||
2311 | /* | |
2312 | * Map WB on BDW to snooped on CHV. | |
2313 | * | |
2314 | * Only the snoop bit has meaning for CHV, the rest is | |
2315 | * ignored. | |
2316 | * | |
cf3d262e VS |
2317 | * The hardware will never snoop for certain types of accesses: |
2318 | * - CPU GTT (GMADR->GGTT->no snoop->memory) | |
2319 | * - PPGTT page tables | |
2320 | * - some other special cycles | |
2321 | * | |
2322 | * As with BDW, we also need to consider the following for GT accesses: | |
2323 | * "For GGTT, there is NO pat_sel[2:0] from the entry, | |
2324 | * so RTL will always use the value corresponding to | |
2325 | * pat_sel = 000". | |
2326 | * Which means we must set the snoop bit in PAT entry 0 | |
2327 | * in order to keep the global status page working. | |
ee0ce478 VS |
2328 | */ |
2329 | pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | | |
2330 | GEN8_PPAT(1, 0) | | |
2331 | GEN8_PPAT(2, 0) | | |
2332 | GEN8_PPAT(3, 0) | | |
2333 | GEN8_PPAT(4, CHV_PPAT_SNOOP) | | |
2334 | GEN8_PPAT(5, CHV_PPAT_SNOOP) | | |
2335 | GEN8_PPAT(6, CHV_PPAT_SNOOP) | | |
2336 | GEN8_PPAT(7, CHV_PPAT_SNOOP); | |
2337 | ||
2338 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
2339 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
2340 | } | |
2341 | ||
63340133 BW |
2342 | static int gen8_gmch_probe(struct drm_device *dev, |
2343 | size_t *gtt_total, | |
2344 | size_t *stolen, | |
2345 | phys_addr_t *mappable_base, | |
2346 | unsigned long *mappable_end) | |
2347 | { | |
2348 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2349 | unsigned int gtt_size; | |
2350 | u16 snb_gmch_ctl; | |
2351 | int ret; | |
2352 | ||
2353 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
2354 | *mappable_base = pci_resource_start(dev->pdev, 2); | |
2355 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
2356 | ||
2357 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) | |
2358 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); | |
2359 | ||
2360 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
2361 | ||
66375014 DL |
2362 | if (INTEL_INFO(dev)->gen >= 9) { |
2363 | *stolen = gen9_get_stolen_size(snb_gmch_ctl); | |
2364 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
2365 | } else if (IS_CHERRYVIEW(dev)) { | |
d7f25f23 DL |
2366 | *stolen = chv_get_stolen_size(snb_gmch_ctl); |
2367 | gtt_size = chv_get_total_gtt_size(snb_gmch_ctl); | |
2368 | } else { | |
2369 | *stolen = gen8_get_stolen_size(snb_gmch_ctl); | |
2370 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
2371 | } | |
63340133 | 2372 | |
07749ef3 | 2373 | *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT; |
63340133 | 2374 | |
ee0ce478 VS |
2375 | if (IS_CHERRYVIEW(dev)) |
2376 | chv_setup_private_ppat(dev_priv); | |
2377 | else | |
2378 | bdw_setup_private_ppat(dev_priv); | |
fbe5d36e | 2379 | |
63340133 BW |
2380 | ret = ggtt_probe_common(dev, gtt_size); |
2381 | ||
94ec8f61 BW |
2382 | dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range; |
2383 | dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries; | |
63340133 BW |
2384 | |
2385 | return ret; | |
2386 | } | |
2387 | ||
baa09f5f BW |
2388 | static int gen6_gmch_probe(struct drm_device *dev, |
2389 | size_t *gtt_total, | |
41907ddc BW |
2390 | size_t *stolen, |
2391 | phys_addr_t *mappable_base, | |
2392 | unsigned long *mappable_end) | |
e76e9aeb BW |
2393 | { |
2394 | struct drm_i915_private *dev_priv = dev->dev_private; | |
baa09f5f | 2395 | unsigned int gtt_size; |
e76e9aeb | 2396 | u16 snb_gmch_ctl; |
e76e9aeb BW |
2397 | int ret; |
2398 | ||
41907ddc BW |
2399 | *mappable_base = pci_resource_start(dev->pdev, 2); |
2400 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
2401 | ||
baa09f5f BW |
2402 | /* 64/512MB is the current min/max we actually know of, but this is just |
2403 | * a coarse sanity check. | |
e76e9aeb | 2404 | */ |
41907ddc | 2405 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
baa09f5f BW |
2406 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
2407 | dev_priv->gtt.mappable_end); | |
2408 | return -ENXIO; | |
e76e9aeb BW |
2409 | } |
2410 | ||
e76e9aeb BW |
2411 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
2412 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 2413 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
e76e9aeb | 2414 | |
c4ae25ec | 2415 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
a93e4161 | 2416 | |
63340133 | 2417 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
07749ef3 | 2418 | *gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT; |
e76e9aeb | 2419 | |
63340133 | 2420 | ret = ggtt_probe_common(dev, gtt_size); |
e76e9aeb | 2421 | |
853ba5d2 BW |
2422 | dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; |
2423 | dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; | |
7faf1ab2 | 2424 | |
e76e9aeb BW |
2425 | return ret; |
2426 | } | |
2427 | ||
853ba5d2 | 2428 | static void gen6_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 2429 | { |
853ba5d2 BW |
2430 | |
2431 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); | |
5ed16782 | 2432 | |
853ba5d2 BW |
2433 | iounmap(gtt->gsm); |
2434 | teardown_scratch_page(vm->dev); | |
644ec02b | 2435 | } |
baa09f5f BW |
2436 | |
2437 | static int i915_gmch_probe(struct drm_device *dev, | |
2438 | size_t *gtt_total, | |
41907ddc BW |
2439 | size_t *stolen, |
2440 | phys_addr_t *mappable_base, | |
2441 | unsigned long *mappable_end) | |
baa09f5f BW |
2442 | { |
2443 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2444 | int ret; | |
2445 | ||
baa09f5f BW |
2446 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
2447 | if (!ret) { | |
2448 | DRM_ERROR("failed to set up gmch\n"); | |
2449 | return -EIO; | |
2450 | } | |
2451 | ||
41907ddc | 2452 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
2453 | |
2454 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
853ba5d2 | 2455 | dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; |
baa09f5f | 2456 | |
c0a7f818 CW |
2457 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
2458 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); | |
2459 | ||
baa09f5f BW |
2460 | return 0; |
2461 | } | |
2462 | ||
853ba5d2 | 2463 | static void i915_gmch_remove(struct i915_address_space *vm) |
baa09f5f BW |
2464 | { |
2465 | intel_gmch_remove(); | |
2466 | } | |
2467 | ||
2468 | int i915_gem_gtt_init(struct drm_device *dev) | |
2469 | { | |
2470 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2471 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
2472 | int ret; |
2473 | ||
baa09f5f | 2474 | if (INTEL_INFO(dev)->gen <= 5) { |
b2f21b4d | 2475 | gtt->gtt_probe = i915_gmch_probe; |
853ba5d2 | 2476 | gtt->base.cleanup = i915_gmch_remove; |
63340133 | 2477 | } else if (INTEL_INFO(dev)->gen < 8) { |
b2f21b4d | 2478 | gtt->gtt_probe = gen6_gmch_probe; |
853ba5d2 | 2479 | gtt->base.cleanup = gen6_gmch_remove; |
4d15c145 | 2480 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
853ba5d2 | 2481 | gtt->base.pte_encode = iris_pte_encode; |
4d15c145 | 2482 | else if (IS_HASWELL(dev)) |
853ba5d2 | 2483 | gtt->base.pte_encode = hsw_pte_encode; |
b2f21b4d | 2484 | else if (IS_VALLEYVIEW(dev)) |
853ba5d2 | 2485 | gtt->base.pte_encode = byt_pte_encode; |
350ec881 CW |
2486 | else if (INTEL_INFO(dev)->gen >= 7) |
2487 | gtt->base.pte_encode = ivb_pte_encode; | |
b2f21b4d | 2488 | else |
350ec881 | 2489 | gtt->base.pte_encode = snb_pte_encode; |
63340133 BW |
2490 | } else { |
2491 | dev_priv->gtt.gtt_probe = gen8_gmch_probe; | |
2492 | dev_priv->gtt.base.cleanup = gen6_gmch_remove; | |
baa09f5f BW |
2493 | } |
2494 | ||
853ba5d2 | 2495 | ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, |
b2f21b4d | 2496 | >t->mappable_base, >t->mappable_end); |
a54c0c27 | 2497 | if (ret) |
baa09f5f | 2498 | return ret; |
baa09f5f | 2499 | |
853ba5d2 BW |
2500 | gtt->base.dev = dev; |
2501 | ||
baa09f5f | 2502 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
853ba5d2 BW |
2503 | DRM_INFO("Memory usable by graphics device = %zdM\n", |
2504 | gtt->base.total >> 20); | |
b2f21b4d BW |
2505 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); |
2506 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); | |
5db6c735 DV |
2507 | #ifdef CONFIG_INTEL_IOMMU |
2508 | if (intel_iommu_gfx_mapped) | |
2509 | DRM_INFO("VT-d active for gfx access\n"); | |
2510 | #endif | |
cfa7c862 DV |
2511 | /* |
2512 | * i915.enable_ppgtt is read-only, so do an early pass to validate the | |
2513 | * user's requested state against the hardware/driver capabilities. We | |
2514 | * do this now so that we can print out any log messages once rather | |
2515 | * than every time we check intel_enable_ppgtt(). | |
2516 | */ | |
2517 | i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt); | |
2518 | DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt); | |
baa09f5f BW |
2519 | |
2520 | return 0; | |
2521 | } | |
6f65e29a | 2522 | |
ec7adb6e JL |
2523 | static struct i915_vma * |
2524 | __i915_gem_vma_create(struct drm_i915_gem_object *obj, | |
2525 | struct i915_address_space *vm, | |
2526 | const struct i915_ggtt_view *ggtt_view) | |
6f65e29a | 2527 | { |
dabde5c7 | 2528 | struct i915_vma *vma; |
6f65e29a | 2529 | |
ec7adb6e JL |
2530 | if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)) |
2531 | return ERR_PTR(-EINVAL); | |
dabde5c7 DC |
2532 | vma = kzalloc(sizeof(*vma), GFP_KERNEL); |
2533 | if (vma == NULL) | |
2534 | return ERR_PTR(-ENOMEM); | |
ec7adb6e | 2535 | |
6f65e29a BW |
2536 | INIT_LIST_HEAD(&vma->vma_link); |
2537 | INIT_LIST_HEAD(&vma->mm_list); | |
2538 | INIT_LIST_HEAD(&vma->exec_list); | |
2539 | vma->vm = vm; | |
2540 | vma->obj = obj; | |
2541 | ||
b1252bcf | 2542 | if (INTEL_INFO(vm->dev)->gen >= 6) { |
7e0d96bc | 2543 | if (i915_is_ggtt(vm)) { |
ec7adb6e JL |
2544 | vma->ggtt_view = *ggtt_view; |
2545 | ||
7e0d96bc BW |
2546 | vma->unbind_vma = ggtt_unbind_vma; |
2547 | vma->bind_vma = ggtt_bind_vma; | |
2548 | } else { | |
2549 | vma->unbind_vma = ppgtt_unbind_vma; | |
2550 | vma->bind_vma = ppgtt_bind_vma; | |
2551 | } | |
b1252bcf | 2552 | } else { |
6f65e29a | 2553 | BUG_ON(!i915_is_ggtt(vm)); |
ec7adb6e | 2554 | vma->ggtt_view = *ggtt_view; |
6f65e29a BW |
2555 | vma->unbind_vma = i915_ggtt_unbind_vma; |
2556 | vma->bind_vma = i915_ggtt_bind_vma; | |
6f65e29a BW |
2557 | } |
2558 | ||
f7635669 TU |
2559 | list_add_tail(&vma->vma_link, &obj->vma_list); |
2560 | if (!i915_is_ggtt(vm)) | |
e07f0552 | 2561 | i915_ppgtt_get(i915_vm_to_ppgtt(vm)); |
6f65e29a BW |
2562 | |
2563 | return vma; | |
2564 | } | |
2565 | ||
2566 | struct i915_vma * | |
ec7adb6e JL |
2567 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, |
2568 | struct i915_address_space *vm) | |
2569 | { | |
2570 | struct i915_vma *vma; | |
2571 | ||
2572 | vma = i915_gem_obj_to_vma(obj, vm); | |
2573 | if (!vma) | |
2574 | vma = __i915_gem_vma_create(obj, vm, | |
2575 | i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL); | |
2576 | ||
2577 | return vma; | |
2578 | } | |
2579 | ||
2580 | struct i915_vma * | |
2581 | i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj, | |
fe14d5f4 | 2582 | const struct i915_ggtt_view *view) |
6f65e29a | 2583 | { |
ec7adb6e | 2584 | struct i915_address_space *ggtt = i915_obj_to_ggtt(obj); |
6f65e29a BW |
2585 | struct i915_vma *vma; |
2586 | ||
ec7adb6e JL |
2587 | if (WARN_ON(!view)) |
2588 | return ERR_PTR(-EINVAL); | |
2589 | ||
2590 | vma = i915_gem_obj_to_ggtt_view(obj, view); | |
2591 | ||
2592 | if (IS_ERR(vma)) | |
2593 | return vma; | |
2594 | ||
6f65e29a | 2595 | if (!vma) |
ec7adb6e | 2596 | vma = __i915_gem_vma_create(obj, ggtt, view); |
6f65e29a BW |
2597 | |
2598 | return vma; | |
ec7adb6e | 2599 | |
6f65e29a | 2600 | } |
fe14d5f4 | 2601 | |
50470bb0 TU |
2602 | static void |
2603 | rotate_pages(dma_addr_t *in, unsigned int width, unsigned int height, | |
2604 | struct sg_table *st) | |
2605 | { | |
2606 | unsigned int column, row; | |
2607 | unsigned int src_idx; | |
2608 | struct scatterlist *sg = st->sgl; | |
2609 | ||
2610 | st->nents = 0; | |
2611 | ||
2612 | for (column = 0; column < width; column++) { | |
2613 | src_idx = width * (height - 1) + column; | |
2614 | for (row = 0; row < height; row++) { | |
2615 | st->nents++; | |
2616 | /* We don't need the pages, but need to initialize | |
2617 | * the entries so the sg list can be happily traversed. | |
2618 | * The only thing we need are DMA addresses. | |
2619 | */ | |
2620 | sg_set_page(sg, NULL, PAGE_SIZE, 0); | |
2621 | sg_dma_address(sg) = in[src_idx]; | |
2622 | sg_dma_len(sg) = PAGE_SIZE; | |
2623 | sg = sg_next(sg); | |
2624 | src_idx -= width; | |
2625 | } | |
2626 | } | |
2627 | } | |
2628 | ||
2629 | static struct sg_table * | |
2630 | intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view, | |
2631 | struct drm_i915_gem_object *obj) | |
2632 | { | |
2633 | struct drm_device *dev = obj->base.dev; | |
2634 | struct intel_rotation_info *rot_info = &ggtt_view->rotation_info; | |
2635 | unsigned long size, pages, rot_pages; | |
2636 | struct sg_page_iter sg_iter; | |
2637 | unsigned long i; | |
2638 | dma_addr_t *page_addr_list; | |
2639 | struct sg_table *st; | |
2640 | unsigned int tile_pitch, tile_height; | |
2641 | unsigned int width_pages, height_pages; | |
1d00dad5 | 2642 | int ret = -ENOMEM; |
50470bb0 TU |
2643 | |
2644 | pages = obj->base.size / PAGE_SIZE; | |
2645 | ||
2646 | /* Calculate tiling geometry. */ | |
2647 | tile_height = intel_tile_height(dev, rot_info->pixel_format, | |
2648 | rot_info->fb_modifier); | |
2649 | tile_pitch = PAGE_SIZE / tile_height; | |
2650 | width_pages = DIV_ROUND_UP(rot_info->pitch, tile_pitch); | |
2651 | height_pages = DIV_ROUND_UP(rot_info->height, tile_height); | |
2652 | rot_pages = width_pages * height_pages; | |
2653 | size = rot_pages * PAGE_SIZE; | |
2654 | ||
2655 | /* Allocate a temporary list of source pages for random access. */ | |
2656 | page_addr_list = drm_malloc_ab(pages, sizeof(dma_addr_t)); | |
2657 | if (!page_addr_list) | |
2658 | return ERR_PTR(ret); | |
2659 | ||
2660 | /* Allocate target SG list. */ | |
2661 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
2662 | if (!st) | |
2663 | goto err_st_alloc; | |
2664 | ||
2665 | ret = sg_alloc_table(st, rot_pages, GFP_KERNEL); | |
2666 | if (ret) | |
2667 | goto err_sg_alloc; | |
2668 | ||
2669 | /* Populate source page list from the object. */ | |
2670 | i = 0; | |
2671 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { | |
2672 | page_addr_list[i] = sg_page_iter_dma_address(&sg_iter); | |
2673 | i++; | |
2674 | } | |
2675 | ||
2676 | /* Rotate the pages. */ | |
2677 | rotate_pages(page_addr_list, width_pages, height_pages, st); | |
2678 | ||
2679 | DRM_DEBUG_KMS( | |
2680 | "Created rotated page mapping for object size %lu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %lu pages).\n", | |
2681 | size, rot_info->pitch, rot_info->height, | |
2682 | rot_info->pixel_format, width_pages, height_pages, | |
2683 | rot_pages); | |
2684 | ||
2685 | drm_free_large(page_addr_list); | |
2686 | ||
2687 | return st; | |
2688 | ||
2689 | err_sg_alloc: | |
2690 | kfree(st); | |
2691 | err_st_alloc: | |
2692 | drm_free_large(page_addr_list); | |
2693 | ||
2694 | DRM_DEBUG_KMS( | |
2695 | "Failed to create rotated mapping for object size %lu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %lu pages)\n", | |
2696 | size, ret, rot_info->pitch, rot_info->height, | |
2697 | rot_info->pixel_format, width_pages, height_pages, | |
2698 | rot_pages); | |
2699 | return ERR_PTR(ret); | |
2700 | } | |
ec7adb6e | 2701 | |
50470bb0 TU |
2702 | static inline int |
2703 | i915_get_ggtt_vma_pages(struct i915_vma *vma) | |
fe14d5f4 | 2704 | { |
50470bb0 TU |
2705 | int ret = 0; |
2706 | ||
fe14d5f4 TU |
2707 | if (vma->ggtt_view.pages) |
2708 | return 0; | |
2709 | ||
2710 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) | |
2711 | vma->ggtt_view.pages = vma->obj->pages; | |
50470bb0 TU |
2712 | else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED) |
2713 | vma->ggtt_view.pages = | |
2714 | intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj); | |
fe14d5f4 TU |
2715 | else |
2716 | WARN_ONCE(1, "GGTT view %u not implemented!\n", | |
2717 | vma->ggtt_view.type); | |
2718 | ||
2719 | if (!vma->ggtt_view.pages) { | |
ec7adb6e | 2720 | DRM_ERROR("Failed to get pages for GGTT view type %u!\n", |
fe14d5f4 | 2721 | vma->ggtt_view.type); |
50470bb0 TU |
2722 | ret = -EINVAL; |
2723 | } else if (IS_ERR(vma->ggtt_view.pages)) { | |
2724 | ret = PTR_ERR(vma->ggtt_view.pages); | |
2725 | vma->ggtt_view.pages = NULL; | |
2726 | DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n", | |
2727 | vma->ggtt_view.type, ret); | |
fe14d5f4 TU |
2728 | } |
2729 | ||
50470bb0 | 2730 | return ret; |
fe14d5f4 TU |
2731 | } |
2732 | ||
2733 | /** | |
2734 | * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space. | |
2735 | * @vma: VMA to map | |
2736 | * @cache_level: mapping cache level | |
2737 | * @flags: flags like global or local mapping | |
2738 | * | |
2739 | * DMA addresses are taken from the scatter-gather table of this object (or of | |
2740 | * this VMA in case of non-default GGTT views) and PTE entries set up. | |
2741 | * Note that DMA addresses are also the only part of the SG table we care about. | |
2742 | */ | |
2743 | int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, | |
2744 | u32 flags) | |
2745 | { | |
ec7adb6e JL |
2746 | if (i915_is_ggtt(vma->vm)) { |
2747 | int ret = i915_get_ggtt_vma_pages(vma); | |
fe14d5f4 | 2748 | |
ec7adb6e JL |
2749 | if (ret) |
2750 | return ret; | |
2751 | } | |
fe14d5f4 TU |
2752 | |
2753 | vma->bind_vma(vma, cache_level, flags); | |
2754 | ||
2755 | return 0; | |
2756 | } |