Commit | Line | Data |
---|---|---|
76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
760285e7 DH |
25 | #include <drm/drmP.h> |
26 | #include <drm/i915_drm.h> | |
76aaf220 DV |
27 | #include "i915_drv.h" |
28 | #include "i915_trace.h" | |
29 | #include "intel_drv.h" | |
30 | ||
6670a5a5 BW |
31 | #define GEN6_PPGTT_PD_ENTRIES 512 |
32 | #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t)) | |
d31eb10e | 33 | typedef uint64_t gen8_gtt_pte_t; |
37aca44a | 34 | typedef gen8_gtt_pte_t gen8_ppgtt_pde_t; |
6670a5a5 | 35 | |
26b1ff35 BW |
36 | /* PPGTT stuff */ |
37 | #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) | |
0d8ff15e | 38 | #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) |
26b1ff35 BW |
39 | |
40 | #define GEN6_PDE_VALID (1 << 0) | |
41 | /* gen6+ has bit 11-4 for physical addr bit 39-32 */ | |
42 | #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
43 | ||
44 | #define GEN6_PTE_VALID (1 << 0) | |
45 | #define GEN6_PTE_UNCACHED (1 << 1) | |
46 | #define HSW_PTE_UNCACHED (0) | |
47 | #define GEN6_PTE_CACHE_LLC (2 << 1) | |
350ec881 | 48 | #define GEN7_PTE_CACHE_L3_LLC (3 << 1) |
26b1ff35 | 49 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) |
0d8ff15e BW |
50 | #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) |
51 | ||
52 | /* Cacheability Control is a 4-bit value. The low three bits are stored in * | |
53 | * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. | |
54 | */ | |
55 | #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ | |
56 | (((bits) & 0x8) << (11 - 3))) | |
87a6b688 | 57 | #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) |
0d8ff15e | 58 | #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) |
4d15c145 | 59 | #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) |
651d794f | 60 | #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) |
26b1ff35 | 61 | |
459108b8 | 62 | #define GEN8_PTES_PER_PAGE (PAGE_SIZE / sizeof(gen8_gtt_pte_t)) |
37aca44a BW |
63 | #define GEN8_PDES_PER_PAGE (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t)) |
64 | #define GEN8_LEGACY_PDPS 4 | |
65 | ||
fbe5d36e BW |
66 | #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) |
67 | #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ | |
68 | #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ | |
69 | #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ | |
70 | ||
6f65e29a BW |
71 | static void ppgtt_bind_vma(struct i915_vma *vma, |
72 | enum i915_cache_level cache_level, | |
73 | u32 flags); | |
74 | static void ppgtt_unbind_vma(struct i915_vma *vma); | |
eeb9488e | 75 | static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt); |
6f65e29a | 76 | |
94ec8f61 BW |
77 | static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr, |
78 | enum i915_cache_level level, | |
79 | bool valid) | |
80 | { | |
81 | gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; | |
82 | pte |= addr; | |
fbe5d36e BW |
83 | if (level != I915_CACHE_NONE) |
84 | pte |= PPAT_CACHED_INDEX; | |
85 | else | |
86 | pte |= PPAT_UNCACHED_INDEX; | |
94ec8f61 BW |
87 | return pte; |
88 | } | |
89 | ||
b1fe6673 BW |
90 | static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev, |
91 | dma_addr_t addr, | |
92 | enum i915_cache_level level) | |
93 | { | |
94 | gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW; | |
95 | pde |= addr; | |
96 | if (level != I915_CACHE_NONE) | |
97 | pde |= PPAT_CACHED_PDE_INDEX; | |
98 | else | |
99 | pde |= PPAT_UNCACHED_INDEX; | |
100 | return pde; | |
101 | } | |
102 | ||
350ec881 | 103 | static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr, |
b35b380e BW |
104 | enum i915_cache_level level, |
105 | bool valid) | |
54d12527 | 106 | { |
b35b380e | 107 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
54d12527 | 108 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
109 | |
110 | switch (level) { | |
350ec881 CW |
111 | case I915_CACHE_L3_LLC: |
112 | case I915_CACHE_LLC: | |
113 | pte |= GEN6_PTE_CACHE_LLC; | |
114 | break; | |
115 | case I915_CACHE_NONE: | |
116 | pte |= GEN6_PTE_UNCACHED; | |
117 | break; | |
118 | default: | |
119 | WARN_ON(1); | |
120 | } | |
121 | ||
122 | return pte; | |
123 | } | |
124 | ||
125 | static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr, | |
b35b380e BW |
126 | enum i915_cache_level level, |
127 | bool valid) | |
350ec881 | 128 | { |
b35b380e | 129 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
350ec881 CW |
130 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
131 | ||
132 | switch (level) { | |
133 | case I915_CACHE_L3_LLC: | |
134 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
135 | break; |
136 | case I915_CACHE_LLC: | |
137 | pte |= GEN6_PTE_CACHE_LLC; | |
138 | break; | |
139 | case I915_CACHE_NONE: | |
9119708c | 140 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
141 | break; |
142 | default: | |
350ec881 | 143 | WARN_ON(1); |
e7210c3c BW |
144 | } |
145 | ||
54d12527 BW |
146 | return pte; |
147 | } | |
148 | ||
93c34e70 KG |
149 | #define BYT_PTE_WRITEABLE (1 << 1) |
150 | #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) | |
151 | ||
80a74f7f | 152 | static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr, |
b35b380e BW |
153 | enum i915_cache_level level, |
154 | bool valid) | |
93c34e70 | 155 | { |
b35b380e | 156 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
93c34e70 KG |
157 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
158 | ||
159 | /* Mark the page as writeable. Other platforms don't have a | |
160 | * setting for read-only/writable, so this matches that behavior. | |
161 | */ | |
162 | pte |= BYT_PTE_WRITEABLE; | |
163 | ||
164 | if (level != I915_CACHE_NONE) | |
165 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
166 | ||
167 | return pte; | |
168 | } | |
169 | ||
80a74f7f | 170 | static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr, |
b35b380e BW |
171 | enum i915_cache_level level, |
172 | bool valid) | |
9119708c | 173 | { |
b35b380e | 174 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
0d8ff15e | 175 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
176 | |
177 | if (level != I915_CACHE_NONE) | |
87a6b688 | 178 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
179 | |
180 | return pte; | |
181 | } | |
182 | ||
4d15c145 | 183 | static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr, |
b35b380e BW |
184 | enum i915_cache_level level, |
185 | bool valid) | |
4d15c145 | 186 | { |
b35b380e | 187 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4d15c145 BW |
188 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
189 | ||
651d794f CW |
190 | switch (level) { |
191 | case I915_CACHE_NONE: | |
192 | break; | |
193 | case I915_CACHE_WT: | |
194 | pte |= HSW_WT_ELLC_LLC_AGE0; | |
195 | break; | |
196 | default: | |
4d15c145 | 197 | pte |= HSW_WB_ELLC_LLC_AGE0; |
651d794f CW |
198 | break; |
199 | } | |
4d15c145 BW |
200 | |
201 | return pte; | |
202 | } | |
203 | ||
94e409c1 BW |
204 | /* Broadwell Page Directory Pointer Descriptors */ |
205 | static int gen8_write_pdp(struct intel_ring_buffer *ring, unsigned entry, | |
e178f705 | 206 | uint64_t val, bool synchronous) |
94e409c1 | 207 | { |
e178f705 | 208 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
94e409c1 BW |
209 | int ret; |
210 | ||
211 | BUG_ON(entry >= 4); | |
212 | ||
e178f705 BW |
213 | if (synchronous) { |
214 | I915_WRITE(GEN8_RING_PDP_UDW(ring, entry), val >> 32); | |
215 | I915_WRITE(GEN8_RING_PDP_LDW(ring, entry), (u32)val); | |
216 | return 0; | |
217 | } | |
218 | ||
94e409c1 BW |
219 | ret = intel_ring_begin(ring, 6); |
220 | if (ret) | |
221 | return ret; | |
222 | ||
223 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
224 | intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry)); | |
225 | intel_ring_emit(ring, (u32)(val >> 32)); | |
226 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
227 | intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry)); | |
228 | intel_ring_emit(ring, (u32)(val)); | |
229 | intel_ring_advance(ring); | |
230 | ||
231 | return 0; | |
232 | } | |
233 | ||
eeb9488e BW |
234 | static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt, |
235 | struct intel_ring_buffer *ring, | |
236 | bool synchronous) | |
94e409c1 | 237 | { |
eeb9488e | 238 | int i, ret; |
94e409c1 BW |
239 | |
240 | /* bit of a hack to find the actual last used pd */ | |
241 | int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE; | |
242 | ||
94e409c1 BW |
243 | for (i = used_pd - 1; i >= 0; i--) { |
244 | dma_addr_t addr = ppgtt->pd_dma_addr[i]; | |
eeb9488e BW |
245 | ret = gen8_write_pdp(ring, i, addr, synchronous); |
246 | if (ret) | |
247 | return ret; | |
94e409c1 | 248 | } |
d595bd4b | 249 | |
eeb9488e | 250 | return 0; |
94e409c1 BW |
251 | } |
252 | ||
459108b8 BW |
253 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
254 | unsigned first_entry, | |
255 | unsigned num_entries, | |
256 | bool use_scratch) | |
257 | { | |
258 | struct i915_hw_ppgtt *ppgtt = | |
259 | container_of(vm, struct i915_hw_ppgtt, base); | |
260 | gen8_gtt_pte_t *pt_vaddr, scratch_pte; | |
261 | unsigned act_pt = first_entry / GEN8_PTES_PER_PAGE; | |
262 | unsigned first_pte = first_entry % GEN8_PTES_PER_PAGE; | |
263 | unsigned last_pte, i; | |
264 | ||
265 | scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr, | |
266 | I915_CACHE_LLC, use_scratch); | |
267 | ||
268 | while (num_entries) { | |
269 | struct page *page_table = &ppgtt->gen8_pt_pages[act_pt]; | |
270 | ||
271 | last_pte = first_pte + num_entries; | |
272 | if (last_pte > GEN8_PTES_PER_PAGE) | |
273 | last_pte = GEN8_PTES_PER_PAGE; | |
274 | ||
275 | pt_vaddr = kmap_atomic(page_table); | |
276 | ||
277 | for (i = first_pte; i < last_pte; i++) | |
278 | pt_vaddr[i] = scratch_pte; | |
279 | ||
280 | kunmap_atomic(pt_vaddr); | |
281 | ||
282 | num_entries -= last_pte - first_pte; | |
283 | first_pte = 0; | |
284 | act_pt++; | |
285 | } | |
286 | } | |
287 | ||
9df15b49 BW |
288 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
289 | struct sg_table *pages, | |
290 | unsigned first_entry, | |
291 | enum i915_cache_level cache_level) | |
292 | { | |
293 | struct i915_hw_ppgtt *ppgtt = | |
294 | container_of(vm, struct i915_hw_ppgtt, base); | |
295 | gen8_gtt_pte_t *pt_vaddr; | |
296 | unsigned act_pt = first_entry / GEN8_PTES_PER_PAGE; | |
297 | unsigned act_pte = first_entry % GEN8_PTES_PER_PAGE; | |
298 | struct sg_page_iter sg_iter; | |
299 | ||
300 | pt_vaddr = kmap_atomic(&ppgtt->gen8_pt_pages[act_pt]); | |
301 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { | |
302 | dma_addr_t page_addr; | |
303 | ||
304 | page_addr = sg_dma_address(sg_iter.sg) + | |
305 | (sg_iter.sg_pgoffset << PAGE_SHIFT); | |
306 | pt_vaddr[act_pte] = gen8_pte_encode(page_addr, cache_level, | |
307 | true); | |
308 | if (++act_pte == GEN8_PTES_PER_PAGE) { | |
309 | kunmap_atomic(pt_vaddr); | |
310 | act_pt++; | |
311 | pt_vaddr = kmap_atomic(&ppgtt->gen8_pt_pages[act_pt]); | |
312 | act_pte = 0; | |
313 | ||
314 | } | |
315 | } | |
316 | kunmap_atomic(pt_vaddr); | |
317 | } | |
318 | ||
37aca44a BW |
319 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) |
320 | { | |
321 | struct i915_hw_ppgtt *ppgtt = | |
322 | container_of(vm, struct i915_hw_ppgtt, base); | |
323 | int i, j; | |
324 | ||
686e1f6f BW |
325 | drm_mm_takedown(&vm->mm); |
326 | ||
37aca44a BW |
327 | for (i = 0; i < ppgtt->num_pd_pages ; i++) { |
328 | if (ppgtt->pd_dma_addr[i]) { | |
329 | pci_unmap_page(ppgtt->base.dev->pdev, | |
330 | ppgtt->pd_dma_addr[i], | |
331 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
332 | ||
333 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
334 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; | |
335 | if (addr) | |
336 | pci_unmap_page(ppgtt->base.dev->pdev, | |
337 | addr, | |
338 | PAGE_SIZE, | |
339 | PCI_DMA_BIDIRECTIONAL); | |
340 | ||
341 | } | |
342 | } | |
343 | kfree(ppgtt->gen8_pt_dma_addr[i]); | |
344 | } | |
345 | ||
230f955f BW |
346 | __free_pages(ppgtt->gen8_pt_pages, get_order(ppgtt->num_pt_pages << PAGE_SHIFT)); |
347 | __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT)); | |
37aca44a BW |
348 | } |
349 | ||
350 | /** | |
351 | * GEN8 legacy ppgtt programming is accomplished through 4 PDP registers with a | |
352 | * net effect resembling a 2-level page table in normal x86 terms. Each PDP | |
353 | * represents 1GB of memory | |
354 | * 4 * 512 * 512 * 4096 = 4GB legacy 32b address space. | |
355 | * | |
356 | * TODO: Do something with the size parameter | |
357 | **/ | |
358 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) | |
359 | { | |
360 | struct page *pt_pages; | |
361 | int i, j, ret = -ENOMEM; | |
362 | const int max_pdp = DIV_ROUND_UP(size, 1 << 30); | |
363 | const int num_pt_pages = GEN8_PDES_PER_PAGE * max_pdp; | |
364 | ||
365 | if (size % (1<<30)) | |
366 | DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size); | |
367 | ||
368 | /* FIXME: split allocation into smaller pieces. For now we only ever do | |
369 | * this once, but with full PPGTT, the multiple contiguous allocations | |
370 | * will be bad. | |
371 | */ | |
372 | ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT)); | |
373 | if (!ppgtt->pd_pages) | |
374 | return -ENOMEM; | |
375 | ||
376 | pt_pages = alloc_pages(GFP_KERNEL, get_order(num_pt_pages << PAGE_SHIFT)); | |
377 | if (!pt_pages) { | |
378 | __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT)); | |
379 | return -ENOMEM; | |
380 | } | |
381 | ||
382 | ppgtt->gen8_pt_pages = pt_pages; | |
383 | ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT); | |
384 | ppgtt->num_pt_pages = 1 << get_order(num_pt_pages << PAGE_SHIFT); | |
385 | ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE; | |
94e409c1 | 386 | ppgtt->enable = gen8_ppgtt_enable; |
eeb9488e | 387 | ppgtt->switch_mm = gen8_mm_switch; |
459108b8 | 388 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; |
9df15b49 | 389 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; |
37aca44a | 390 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; |
686e1f6f BW |
391 | ppgtt->base.start = 0; |
392 | ppgtt->base.total = ppgtt->num_pt_pages * GEN8_PTES_PER_PAGE * PAGE_SIZE; | |
37aca44a BW |
393 | |
394 | BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS); | |
395 | ||
396 | /* | |
397 | * - Create a mapping for the page directories. | |
398 | * - For each page directory: | |
399 | * allocate space for page table mappings. | |
400 | * map each page table | |
401 | */ | |
402 | for (i = 0; i < max_pdp; i++) { | |
403 | dma_addr_t temp; | |
404 | temp = pci_map_page(ppgtt->base.dev->pdev, | |
405 | &ppgtt->pd_pages[i], 0, | |
406 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
407 | if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp)) | |
408 | goto err_out; | |
409 | ||
410 | ppgtt->pd_dma_addr[i] = temp; | |
411 | ||
412 | ppgtt->gen8_pt_dma_addr[i] = kmalloc(sizeof(dma_addr_t) * GEN8_PDES_PER_PAGE, GFP_KERNEL); | |
413 | if (!ppgtt->gen8_pt_dma_addr[i]) | |
414 | goto err_out; | |
415 | ||
416 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
417 | struct page *p = &pt_pages[i * GEN8_PDES_PER_PAGE + j]; | |
418 | temp = pci_map_page(ppgtt->base.dev->pdev, | |
419 | p, 0, PAGE_SIZE, | |
420 | PCI_DMA_BIDIRECTIONAL); | |
421 | ||
422 | if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp)) | |
423 | goto err_out; | |
424 | ||
425 | ppgtt->gen8_pt_dma_addr[i][j] = temp; | |
426 | } | |
427 | } | |
428 | ||
b1fe6673 BW |
429 | /* For now, the PPGTT helper functions all require that the PDEs are |
430 | * plugged in correctly. So we do that now/here. For aliasing PPGTT, we | |
431 | * will never need to touch the PDEs again */ | |
432 | for (i = 0; i < max_pdp; i++) { | |
433 | gen8_ppgtt_pde_t *pd_vaddr; | |
434 | pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]); | |
435 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
436 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; | |
437 | pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr, | |
438 | I915_CACHE_LLC); | |
439 | } | |
440 | kunmap_atomic(pd_vaddr); | |
441 | } | |
442 | ||
459108b8 BW |
443 | ppgtt->base.clear_range(&ppgtt->base, 0, |
444 | ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE, | |
445 | true); | |
446 | ||
37aca44a BW |
447 | DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n", |
448 | ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp); | |
449 | DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n", | |
450 | ppgtt->num_pt_pages, | |
451 | (ppgtt->num_pt_pages - num_pt_pages) + | |
452 | size % (1<<30)); | |
28cf5415 | 453 | return 0; |
37aca44a BW |
454 | |
455 | err_out: | |
456 | ppgtt->base.cleanup(&ppgtt->base); | |
457 | return ret; | |
458 | } | |
459 | ||
3e302542 | 460 | static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt) |
6197349b | 461 | { |
853ba5d2 | 462 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; |
6197349b BW |
463 | gen6_gtt_pte_t __iomem *pd_addr; |
464 | uint32_t pd_entry; | |
465 | int i; | |
466 | ||
0a732870 | 467 | WARN_ON(ppgtt->pd_offset & 0x3f); |
6197349b BW |
468 | pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm + |
469 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
470 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
471 | dma_addr_t pt_addr; | |
472 | ||
473 | pt_addr = ppgtt->pt_dma_addr[i]; | |
474 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
475 | pd_entry |= GEN6_PDE_VALID; | |
476 | ||
477 | writel(pd_entry, pd_addr + i); | |
478 | } | |
479 | readl(pd_addr); | |
3e302542 BW |
480 | } |
481 | ||
b4a74e3a BW |
482 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
483 | { | |
484 | BUG_ON(ppgtt->pd_offset & 0x3f); | |
485 | ||
486 | return (ppgtt->pd_offset / 64) << 16; | |
487 | } | |
488 | ||
90252e5c BW |
489 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
490 | struct intel_ring_buffer *ring, | |
491 | bool synchronous) | |
492 | { | |
493 | struct drm_device *dev = ppgtt->base.dev; | |
494 | struct drm_i915_private *dev_priv = dev->dev_private; | |
495 | int ret; | |
496 | ||
497 | /* If we're in reset, we can assume the GPU is sufficiently idle to | |
498 | * manually frob these bits. Ideally we could use the ring functions, | |
499 | * except our error handling makes it quite difficult (can't use | |
500 | * intel_ring_begin, ring->flush, or intel_ring_advance) | |
501 | * | |
502 | * FIXME: We should try not to special case reset | |
503 | */ | |
504 | if (synchronous || | |
505 | i915_reset_in_progress(&dev_priv->gpu_error)) { | |
506 | WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt); | |
507 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
508 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
509 | POSTING_READ(RING_PP_DIR_BASE(ring)); | |
510 | return 0; | |
511 | } | |
512 | ||
513 | /* NB: TLBs must be flushed and invalidated before a switch */ | |
514 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
515 | if (ret) | |
516 | return ret; | |
517 | ||
518 | ret = intel_ring_begin(ring, 6); | |
519 | if (ret) | |
520 | return ret; | |
521 | ||
522 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
523 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
524 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
525 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
526 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
527 | intel_ring_emit(ring, MI_NOOP); | |
528 | intel_ring_advance(ring); | |
529 | ||
530 | return 0; | |
531 | } | |
532 | ||
48a10389 BW |
533 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
534 | struct intel_ring_buffer *ring, | |
535 | bool synchronous) | |
536 | { | |
537 | struct drm_device *dev = ppgtt->base.dev; | |
538 | struct drm_i915_private *dev_priv = dev->dev_private; | |
539 | int ret; | |
540 | ||
541 | /* If we're in reset, we can assume the GPU is sufficiently idle to | |
542 | * manually frob these bits. Ideally we could use the ring functions, | |
543 | * except our error handling makes it quite difficult (can't use | |
544 | * intel_ring_begin, ring->flush, or intel_ring_advance) | |
545 | * | |
546 | * FIXME: We should try not to special case reset | |
547 | */ | |
548 | if (synchronous || | |
549 | i915_reset_in_progress(&dev_priv->gpu_error)) { | |
550 | WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt); | |
551 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
552 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
553 | POSTING_READ(RING_PP_DIR_BASE(ring)); | |
554 | return 0; | |
555 | } | |
556 | ||
557 | /* NB: TLBs must be flushed and invalidated before a switch */ | |
558 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
559 | if (ret) | |
560 | return ret; | |
561 | ||
562 | ret = intel_ring_begin(ring, 6); | |
563 | if (ret) | |
564 | return ret; | |
565 | ||
566 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
567 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
568 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
569 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
570 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
571 | intel_ring_emit(ring, MI_NOOP); | |
572 | intel_ring_advance(ring); | |
573 | ||
90252e5c BW |
574 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
575 | if (ring->id != RCS) { | |
576 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
577 | if (ret) | |
578 | return ret; | |
579 | } | |
580 | ||
48a10389 BW |
581 | return 0; |
582 | } | |
583 | ||
eeb9488e BW |
584 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
585 | struct intel_ring_buffer *ring, | |
586 | bool synchronous) | |
587 | { | |
588 | struct drm_device *dev = ppgtt->base.dev; | |
589 | struct drm_i915_private *dev_priv = dev->dev_private; | |
590 | ||
48a10389 BW |
591 | if (!synchronous) |
592 | return 0; | |
593 | ||
eeb9488e BW |
594 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
595 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
596 | ||
597 | POSTING_READ(RING_PP_DIR_DCLV(ring)); | |
598 | ||
599 | return 0; | |
600 | } | |
601 | ||
602 | static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt) | |
603 | { | |
604 | struct drm_device *dev = ppgtt->base.dev; | |
605 | struct drm_i915_private *dev_priv = dev->dev_private; | |
606 | struct intel_ring_buffer *ring; | |
607 | int j, ret; | |
608 | ||
609 | for_each_ring(ring, dev_priv, j) { | |
610 | I915_WRITE(RING_MODE_GEN7(ring), | |
611 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
612 | ret = ppgtt->switch_mm(ppgtt, ring, true); | |
613 | if (ret) | |
614 | goto err_out; | |
615 | } | |
616 | ||
617 | return 0; | |
618 | ||
619 | err_out: | |
620 | for_each_ring(ring, dev_priv, j) | |
621 | I915_WRITE(RING_MODE_GEN7(ring), | |
622 | _MASKED_BIT_DISABLE(GFX_PPGTT_ENABLE)); | |
623 | return ret; | |
624 | } | |
625 | ||
b4a74e3a | 626 | static int gen7_ppgtt_enable(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 627 | { |
a3d67d23 | 628 | struct drm_device *dev = ppgtt->base.dev; |
3e302542 | 629 | drm_i915_private_t *dev_priv = dev->dev_private; |
3e302542 | 630 | struct intel_ring_buffer *ring; |
b4a74e3a | 631 | uint32_t ecochk, ecobits; |
3e302542 BW |
632 | int i; |
633 | ||
3e302542 | 634 | gen6_write_pdes(ppgtt); |
6197349b | 635 | |
b4a74e3a BW |
636 | ecobits = I915_READ(GAC_ECO_BITS); |
637 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 638 | |
b4a74e3a BW |
639 | ecochk = I915_READ(GAM_ECOCHK); |
640 | if (IS_HASWELL(dev)) { | |
641 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
642 | } else { | |
643 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
644 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
645 | } | |
646 | I915_WRITE(GAM_ECOCHK, ecochk); | |
6197349b | 647 | |
b4a74e3a | 648 | for_each_ring(ring, dev_priv, i) { |
eeb9488e BW |
649 | int ret; |
650 | /* GFX_MODE is per-ring on gen7+ */ | |
b4a74e3a BW |
651 | I915_WRITE(RING_MODE_GEN7(ring), |
652 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
eeb9488e BW |
653 | ret = ppgtt->switch_mm(ppgtt, ring, true); |
654 | if (ret) | |
655 | return ret; | |
6197349b | 656 | |
b4a74e3a BW |
657 | } |
658 | return 0; | |
659 | } | |
6197349b | 660 | |
b4a74e3a BW |
661 | static int gen6_ppgtt_enable(struct i915_hw_ppgtt *ppgtt) |
662 | { | |
663 | struct drm_device *dev = ppgtt->base.dev; | |
664 | drm_i915_private_t *dev_priv = dev->dev_private; | |
665 | struct intel_ring_buffer *ring; | |
666 | uint32_t ecochk, gab_ctl, ecobits; | |
667 | int i; | |
a65c2fcd | 668 | |
b4a74e3a | 669 | gen6_write_pdes(ppgtt); |
a65c2fcd | 670 | |
b4a74e3a BW |
671 | ecobits = I915_READ(GAC_ECO_BITS); |
672 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | | |
673 | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 674 | |
b4a74e3a BW |
675 | gab_ctl = I915_READ(GAB_CTL); |
676 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
677 | ||
678 | ecochk = I915_READ(GAM_ECOCHK); | |
679 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); | |
680 | ||
681 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b | 682 | |
b4a74e3a | 683 | for_each_ring(ring, dev_priv, i) { |
eeb9488e BW |
684 | int ret = ppgtt->switch_mm(ppgtt, ring, true); |
685 | if (ret) | |
686 | return ret; | |
6197349b | 687 | } |
b4a74e3a | 688 | |
b7c36d25 | 689 | return 0; |
6197349b BW |
690 | } |
691 | ||
1d2a314c | 692 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 693 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
1d2a314c | 694 | unsigned first_entry, |
828c7908 BW |
695 | unsigned num_entries, |
696 | bool use_scratch) | |
1d2a314c | 697 | { |
853ba5d2 BW |
698 | struct i915_hw_ppgtt *ppgtt = |
699 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 700 | gen6_gtt_pte_t *pt_vaddr, scratch_pte; |
a15326a5 | 701 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
7bddb01f DV |
702 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
703 | unsigned last_pte, i; | |
1d2a314c | 704 | |
b35b380e | 705 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true); |
1d2a314c | 706 | |
7bddb01f DV |
707 | while (num_entries) { |
708 | last_pte = first_pte + num_entries; | |
709 | if (last_pte > I915_PPGTT_PT_ENTRIES) | |
710 | last_pte = I915_PPGTT_PT_ENTRIES; | |
711 | ||
a15326a5 | 712 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
1d2a314c | 713 | |
7bddb01f DV |
714 | for (i = first_pte; i < last_pte; i++) |
715 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
716 | |
717 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 718 | |
7bddb01f DV |
719 | num_entries -= last_pte - first_pte; |
720 | first_pte = 0; | |
a15326a5 | 721 | act_pt++; |
7bddb01f | 722 | } |
1d2a314c DV |
723 | } |
724 | ||
853ba5d2 | 725 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 DV |
726 | struct sg_table *pages, |
727 | unsigned first_entry, | |
728 | enum i915_cache_level cache_level) | |
729 | { | |
853ba5d2 BW |
730 | struct i915_hw_ppgtt *ppgtt = |
731 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 732 | gen6_gtt_pte_t *pt_vaddr; |
a15326a5 | 733 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
6e995e23 ID |
734 | unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
735 | struct sg_page_iter sg_iter; | |
736 | ||
a15326a5 | 737 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
6e995e23 ID |
738 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
739 | dma_addr_t page_addr; | |
740 | ||
2db76d7c | 741 | page_addr = sg_page_iter_dma_address(&sg_iter); |
b35b380e | 742 | pt_vaddr[act_pte] = vm->pte_encode(page_addr, cache_level, true); |
6e995e23 ID |
743 | if (++act_pte == I915_PPGTT_PT_ENTRIES) { |
744 | kunmap_atomic(pt_vaddr); | |
a15326a5 DV |
745 | act_pt++; |
746 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); | |
6e995e23 | 747 | act_pte = 0; |
def886c3 | 748 | |
def886c3 | 749 | } |
def886c3 | 750 | } |
6e995e23 | 751 | kunmap_atomic(pt_vaddr); |
def886c3 DV |
752 | } |
753 | ||
853ba5d2 | 754 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
1d2a314c | 755 | { |
853ba5d2 BW |
756 | struct i915_hw_ppgtt *ppgtt = |
757 | container_of(vm, struct i915_hw_ppgtt, base); | |
3440d265 DV |
758 | int i; |
759 | ||
93bd8649 | 760 | drm_mm_takedown(&ppgtt->base.mm); |
c8d4c0d6 | 761 | drm_mm_remove_node(&ppgtt->node); |
93bd8649 | 762 | |
3440d265 DV |
763 | if (ppgtt->pt_dma_addr) { |
764 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
853ba5d2 | 765 | pci_unmap_page(ppgtt->base.dev->pdev, |
3440d265 DV |
766 | ppgtt->pt_dma_addr[i], |
767 | 4096, PCI_DMA_BIDIRECTIONAL); | |
768 | } | |
769 | ||
770 | kfree(ppgtt->pt_dma_addr); | |
771 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
772 | __free_page(ppgtt->pt_pages[i]); | |
773 | kfree(ppgtt->pt_pages); | |
774 | kfree(ppgtt); | |
775 | } | |
776 | ||
777 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) | |
778 | { | |
c8d4c0d6 BW |
779 | #define GEN6_PD_ALIGN (PAGE_SIZE * 16) |
780 | #define GEN6_PD_SIZE (GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE) | |
853ba5d2 | 781 | struct drm_device *dev = ppgtt->base.dev; |
1d2a314c | 782 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3cc1995 | 783 | bool retried = false; |
c8d4c0d6 | 784 | int i, ret; |
1d2a314c | 785 | |
c8d4c0d6 BW |
786 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
787 | * allocator works in address space sizes, so it's multiplied by page | |
788 | * size. We allocate at the top of the GTT to avoid fragmentation. | |
789 | */ | |
790 | BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm)); | |
e3cc1995 | 791 | alloc: |
c8d4c0d6 BW |
792 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm, |
793 | &ppgtt->node, GEN6_PD_SIZE, | |
794 | GEN6_PD_ALIGN, 0, | |
795 | 0, dev_priv->gtt.base.total, | |
796 | DRM_MM_SEARCH_DEFAULT); | |
e3cc1995 BW |
797 | if (ret == -ENOSPC && !retried) { |
798 | ret = i915_gem_evict_something(dev, &dev_priv->gtt.base, | |
799 | GEN6_PD_SIZE, GEN6_PD_ALIGN, | |
800 | I915_CACHE_NONE, false, true); | |
801 | if (ret) | |
802 | return ret; | |
803 | ||
804 | retried = true; | |
805 | goto alloc; | |
806 | } | |
c8d4c0d6 BW |
807 | |
808 | if (ppgtt->node.start < dev_priv->gtt.mappable_end) | |
809 | DRM_DEBUG("Forced to use aperture for PDEs\n"); | |
1d2a314c | 810 | |
08c45263 | 811 | ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; |
6670a5a5 | 812 | ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES; |
48a10389 | 813 | if (IS_GEN6(dev)) { |
b4a74e3a | 814 | ppgtt->enable = gen6_ppgtt_enable; |
48a10389 | 815 | ppgtt->switch_mm = gen6_mm_switch; |
90252e5c BW |
816 | } else if (IS_HASWELL(dev)) { |
817 | ppgtt->enable = gen7_ppgtt_enable; | |
818 | ppgtt->switch_mm = hsw_mm_switch; | |
48a10389 | 819 | } else if (IS_GEN7(dev)) { |
b4a74e3a | 820 | ppgtt->enable = gen7_ppgtt_enable; |
48a10389 BW |
821 | ppgtt->switch_mm = gen7_mm_switch; |
822 | } else | |
b4a74e3a | 823 | BUG(); |
853ba5d2 BW |
824 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
825 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
826 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; | |
827 | ppgtt->base.scratch = dev_priv->gtt.base.scratch; | |
686e1f6f BW |
828 | ppgtt->base.start = 0; |
829 | ppgtt->base.total = GEN6_PPGTT_PD_ENTRIES * I915_PPGTT_PT_ENTRIES * PAGE_SIZE; | |
a1e22653 | 830 | ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *), |
1d2a314c | 831 | GFP_KERNEL); |
c8d4c0d6 BW |
832 | if (!ppgtt->pt_pages) { |
833 | drm_mm_remove_node(&ppgtt->node); | |
3440d265 | 834 | return -ENOMEM; |
c8d4c0d6 | 835 | } |
1d2a314c DV |
836 | |
837 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
838 | ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL); | |
839 | if (!ppgtt->pt_pages[i]) | |
840 | goto err_pt_alloc; | |
841 | } | |
842 | ||
a1e22653 | 843 | ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t), |
8d2e6308 BW |
844 | GFP_KERNEL); |
845 | if (!ppgtt->pt_dma_addr) | |
846 | goto err_pt_alloc; | |
1d2a314c | 847 | |
8d2e6308 BW |
848 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
849 | dma_addr_t pt_addr; | |
211c568b | 850 | |
8d2e6308 BW |
851 | pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096, |
852 | PCI_DMA_BIDIRECTIONAL); | |
1d2a314c | 853 | |
8d2e6308 BW |
854 | if (pci_dma_mapping_error(dev->pdev, pt_addr)) { |
855 | ret = -EIO; | |
856 | goto err_pd_pin; | |
1d2a314c | 857 | |
211c568b | 858 | } |
8d2e6308 | 859 | ppgtt->pt_dma_addr[i] = pt_addr; |
1d2a314c | 860 | } |
1d2a314c | 861 | |
853ba5d2 | 862 | ppgtt->base.clear_range(&ppgtt->base, 0, |
828c7908 | 863 | ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES, true); |
1d2a314c | 864 | |
c8d4c0d6 BW |
865 | DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n", |
866 | ppgtt->node.size >> 20, | |
867 | ppgtt->node.start / PAGE_SIZE); | |
868 | ppgtt->pd_offset = | |
869 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t); | |
1d2a314c | 870 | |
1d2a314c DV |
871 | return 0; |
872 | ||
873 | err_pd_pin: | |
874 | if (ppgtt->pt_dma_addr) { | |
875 | for (i--; i >= 0; i--) | |
876 | pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i], | |
877 | 4096, PCI_DMA_BIDIRECTIONAL); | |
878 | } | |
879 | err_pt_alloc: | |
880 | kfree(ppgtt->pt_dma_addr); | |
881 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
882 | if (ppgtt->pt_pages[i]) | |
883 | __free_page(ppgtt->pt_pages[i]); | |
884 | } | |
885 | kfree(ppgtt->pt_pages); | |
c8d4c0d6 | 886 | drm_mm_remove_node(&ppgtt->node); |
3440d265 DV |
887 | |
888 | return ret; | |
889 | } | |
890 | ||
246cbfb5 | 891 | int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) |
3440d265 DV |
892 | { |
893 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d6660add | 894 | int ret = 0; |
3440d265 | 895 | |
853ba5d2 | 896 | ppgtt->base.dev = dev; |
3440d265 | 897 | |
3ed124b2 BW |
898 | if (INTEL_INFO(dev)->gen < 8) |
899 | ret = gen6_ppgtt_init(ppgtt); | |
8fe6bd23 | 900 | else if (IS_GEN8(dev)) |
37aca44a | 901 | ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total); |
3ed124b2 BW |
902 | else |
903 | BUG(); | |
904 | ||
d6660add | 905 | if (!ret) |
93bd8649 BW |
906 | drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, |
907 | ppgtt->base.total); | |
1d2a314c DV |
908 | |
909 | return ret; | |
910 | } | |
911 | ||
912 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev) | |
913 | { | |
914 | struct drm_i915_private *dev_priv = dev->dev_private; | |
915 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1d2a314c DV |
916 | |
917 | if (!ppgtt) | |
918 | return; | |
919 | ||
853ba5d2 | 920 | ppgtt->base.cleanup(&ppgtt->base); |
5963cf04 | 921 | dev_priv->mm.aliasing_ppgtt = NULL; |
1d2a314c DV |
922 | } |
923 | ||
6f65e29a BW |
924 | static void __always_unused |
925 | ppgtt_bind_vma(struct i915_vma *vma, | |
926 | enum i915_cache_level cache_level, | |
927 | u32 flags) | |
7bddb01f | 928 | { |
6f65e29a BW |
929 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; |
930 | ||
931 | WARN_ON(flags); | |
932 | ||
933 | vma->vm->insert_entries(vma->vm, vma->obj->pages, entry, cache_level); | |
7bddb01f DV |
934 | } |
935 | ||
6f65e29a | 936 | static void __always_unused ppgtt_unbind_vma(struct i915_vma *vma) |
7bddb01f | 937 | { |
6f65e29a BW |
938 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; |
939 | ||
940 | vma->vm->clear_range(vma->vm, | |
941 | entry, | |
942 | vma->obj->base.size >> PAGE_SHIFT, | |
943 | true); | |
7bddb01f DV |
944 | } |
945 | ||
a81cc00c BW |
946 | extern int intel_iommu_gfx_mapped; |
947 | /* Certain Gen5 chipsets require require idling the GPU before | |
948 | * unmapping anything from the GTT when VT-d is enabled. | |
949 | */ | |
950 | static inline bool needs_idle_maps(struct drm_device *dev) | |
951 | { | |
952 | #ifdef CONFIG_INTEL_IOMMU | |
953 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
954 | * was loaded first. | |
955 | */ | |
956 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
957 | return true; | |
958 | #endif | |
959 | return false; | |
960 | } | |
961 | ||
5c042287 BW |
962 | static bool do_idling(struct drm_i915_private *dev_priv) |
963 | { | |
964 | bool ret = dev_priv->mm.interruptible; | |
965 | ||
a81cc00c | 966 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 967 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 968 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
969 | DRM_ERROR("Couldn't idle GPU\n"); |
970 | /* Wait a bit, in hopes it avoids the hang */ | |
971 | udelay(10); | |
972 | } | |
973 | } | |
974 | ||
975 | return ret; | |
976 | } | |
977 | ||
978 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
979 | { | |
a81cc00c | 980 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
981 | dev_priv->mm.interruptible = interruptible; |
982 | } | |
983 | ||
828c7908 BW |
984 | void i915_check_and_clear_faults(struct drm_device *dev) |
985 | { | |
986 | struct drm_i915_private *dev_priv = dev->dev_private; | |
987 | struct intel_ring_buffer *ring; | |
988 | int i; | |
989 | ||
990 | if (INTEL_INFO(dev)->gen < 6) | |
991 | return; | |
992 | ||
993 | for_each_ring(ring, dev_priv, i) { | |
994 | u32 fault_reg; | |
995 | fault_reg = I915_READ(RING_FAULT_REG(ring)); | |
996 | if (fault_reg & RING_FAULT_VALID) { | |
997 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
998 | "\tAddr: 0x%08lx\\n" | |
999 | "\tAddress space: %s\n" | |
1000 | "\tSource ID: %d\n" | |
1001 | "\tType: %d\n", | |
1002 | fault_reg & PAGE_MASK, | |
1003 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
1004 | RING_FAULT_SRCID(fault_reg), | |
1005 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
1006 | I915_WRITE(RING_FAULT_REG(ring), | |
1007 | fault_reg & ~RING_FAULT_VALID); | |
1008 | } | |
1009 | } | |
1010 | POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); | |
1011 | } | |
1012 | ||
1013 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) | |
1014 | { | |
1015 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1016 | ||
1017 | /* Don't bother messing with faults pre GEN6 as we have little | |
1018 | * documentation supporting that it's a good idea. | |
1019 | */ | |
1020 | if (INTEL_INFO(dev)->gen < 6) | |
1021 | return; | |
1022 | ||
1023 | i915_check_and_clear_faults(dev); | |
1024 | ||
1025 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, | |
1026 | dev_priv->gtt.base.start / PAGE_SIZE, | |
1027 | dev_priv->gtt.base.total / PAGE_SIZE, | |
1028 | false); | |
1029 | } | |
1030 | ||
76aaf220 DV |
1031 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
1032 | { | |
1033 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 1034 | struct drm_i915_gem_object *obj; |
76aaf220 | 1035 | |
828c7908 BW |
1036 | i915_check_and_clear_faults(dev); |
1037 | ||
bee4a186 | 1038 | /* First fill our portion of the GTT with scratch pages */ |
853ba5d2 BW |
1039 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
1040 | dev_priv->gtt.base.start / PAGE_SIZE, | |
828c7908 BW |
1041 | dev_priv->gtt.base.total / PAGE_SIZE, |
1042 | true); | |
bee4a186 | 1043 | |
35c20a60 | 1044 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6f65e29a BW |
1045 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, |
1046 | &dev_priv->gtt.base); | |
1047 | if (!vma) | |
1048 | continue; | |
1049 | ||
2c22569b | 1050 | i915_gem_clflush_object(obj, obj->pin_display); |
6f65e29a BW |
1051 | /* The bind_vma code tries to be smart about tracking mappings. |
1052 | * Unfortunately above, we've just wiped out the mappings | |
1053 | * without telling our object about it. So we need to fake it. | |
1054 | */ | |
1055 | obj->has_global_gtt_mapping = 0; | |
1056 | vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND); | |
76aaf220 DV |
1057 | } |
1058 | ||
e76e9aeb | 1059 | i915_gem_chipset_flush(dev); |
76aaf220 | 1060 | } |
7c2e6fdf | 1061 | |
74163907 | 1062 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 1063 | { |
9da3da66 | 1064 | if (obj->has_dma_mapping) |
74163907 | 1065 | return 0; |
9da3da66 CW |
1066 | |
1067 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
1068 | obj->pages->sgl, obj->pages->nents, | |
1069 | PCI_DMA_BIDIRECTIONAL)) | |
1070 | return -ENOSPC; | |
1071 | ||
1072 | return 0; | |
7c2e6fdf DV |
1073 | } |
1074 | ||
94ec8f61 BW |
1075 | static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte) |
1076 | { | |
1077 | #ifdef writeq | |
1078 | writeq(pte, addr); | |
1079 | #else | |
1080 | iowrite32((u32)pte, addr); | |
1081 | iowrite32(pte >> 32, addr + 4); | |
1082 | #endif | |
1083 | } | |
1084 | ||
1085 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, | |
1086 | struct sg_table *st, | |
1087 | unsigned int first_entry, | |
1088 | enum i915_cache_level level) | |
1089 | { | |
1090 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
1091 | gen8_gtt_pte_t __iomem *gtt_entries = | |
1092 | (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
1093 | int i = 0; | |
1094 | struct sg_page_iter sg_iter; | |
1095 | dma_addr_t addr; | |
1096 | ||
1097 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { | |
1098 | addr = sg_dma_address(sg_iter.sg) + | |
1099 | (sg_iter.sg_pgoffset << PAGE_SHIFT); | |
1100 | gen8_set_pte(>t_entries[i], | |
1101 | gen8_pte_encode(addr, level, true)); | |
1102 | i++; | |
1103 | } | |
1104 | ||
1105 | /* | |
1106 | * XXX: This serves as a posting read to make sure that the PTE has | |
1107 | * actually been updated. There is some concern that even though | |
1108 | * registers and PTEs are within the same BAR that they are potentially | |
1109 | * of NUMA access patterns. Therefore, even with the way we assume | |
1110 | * hardware should work, we must keep this posting read for paranoia. | |
1111 | */ | |
1112 | if (i != 0) | |
1113 | WARN_ON(readq(>t_entries[i-1]) | |
1114 | != gen8_pte_encode(addr, level, true)); | |
1115 | ||
1116 | #if 0 /* TODO: Still needed on GEN8? */ | |
1117 | /* This next bit makes the above posting read even more important. We | |
1118 | * want to flush the TLBs only after we're certain all the PTE updates | |
1119 | * have finished. | |
1120 | */ | |
1121 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1122 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
1123 | #endif | |
1124 | } | |
1125 | ||
e76e9aeb BW |
1126 | /* |
1127 | * Binds an object into the global gtt with the specified cache level. The object | |
1128 | * will be accessible to the GPU via commands whose operands reference offsets | |
1129 | * within the global GTT as well as accessible by the GPU through the GMADR | |
1130 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
1131 | */ | |
853ba5d2 | 1132 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 DV |
1133 | struct sg_table *st, |
1134 | unsigned int first_entry, | |
1135 | enum i915_cache_level level) | |
e76e9aeb | 1136 | { |
853ba5d2 | 1137 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
e7c2b58b BW |
1138 | gen6_gtt_pte_t __iomem *gtt_entries = |
1139 | (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
1140 | int i = 0; |
1141 | struct sg_page_iter sg_iter; | |
e76e9aeb BW |
1142 | dma_addr_t addr; |
1143 | ||
6e995e23 | 1144 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 1145 | addr = sg_page_iter_dma_address(&sg_iter); |
b35b380e | 1146 | iowrite32(vm->pte_encode(addr, level, true), >t_entries[i]); |
6e995e23 | 1147 | i++; |
e76e9aeb BW |
1148 | } |
1149 | ||
e76e9aeb BW |
1150 | /* XXX: This serves as a posting read to make sure that the PTE has |
1151 | * actually been updated. There is some concern that even though | |
1152 | * registers and PTEs are within the same BAR that they are potentially | |
1153 | * of NUMA access patterns. Therefore, even with the way we assume | |
1154 | * hardware should work, we must keep this posting read for paranoia. | |
1155 | */ | |
1156 | if (i != 0) | |
853ba5d2 | 1157 | WARN_ON(readl(>t_entries[i-1]) != |
b35b380e | 1158 | vm->pte_encode(addr, level, true)); |
0f9b91c7 BW |
1159 | |
1160 | /* This next bit makes the above posting read even more important. We | |
1161 | * want to flush the TLBs only after we're certain all the PTE updates | |
1162 | * have finished. | |
1163 | */ | |
1164 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1165 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
1166 | } |
1167 | ||
94ec8f61 BW |
1168 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
1169 | unsigned int first_entry, | |
1170 | unsigned int num_entries, | |
1171 | bool use_scratch) | |
1172 | { | |
1173 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
1174 | gen8_gtt_pte_t scratch_pte, __iomem *gtt_base = | |
1175 | (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
1176 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; | |
1177 | int i; | |
1178 | ||
1179 | if (WARN(num_entries > max_entries, | |
1180 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1181 | first_entry, num_entries, max_entries)) | |
1182 | num_entries = max_entries; | |
1183 | ||
1184 | scratch_pte = gen8_pte_encode(vm->scratch.addr, | |
1185 | I915_CACHE_LLC, | |
1186 | use_scratch); | |
1187 | for (i = 0; i < num_entries; i++) | |
1188 | gen8_set_pte(>t_base[i], scratch_pte); | |
1189 | readl(gtt_base); | |
1190 | } | |
1191 | ||
853ba5d2 | 1192 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
7faf1ab2 | 1193 | unsigned int first_entry, |
828c7908 BW |
1194 | unsigned int num_entries, |
1195 | bool use_scratch) | |
7faf1ab2 | 1196 | { |
853ba5d2 | 1197 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
e7c2b58b BW |
1198 | gen6_gtt_pte_t scratch_pte, __iomem *gtt_base = |
1199 | (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 1200 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
1201 | int i; |
1202 | ||
1203 | if (WARN(num_entries > max_entries, | |
1204 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1205 | first_entry, num_entries, max_entries)) | |
1206 | num_entries = max_entries; | |
1207 | ||
828c7908 BW |
1208 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch); |
1209 | ||
7faf1ab2 DV |
1210 | for (i = 0; i < num_entries; i++) |
1211 | iowrite32(scratch_pte, >t_base[i]); | |
1212 | readl(gtt_base); | |
1213 | } | |
1214 | ||
6f65e29a BW |
1215 | |
1216 | static void i915_ggtt_bind_vma(struct i915_vma *vma, | |
1217 | enum i915_cache_level cache_level, | |
1218 | u32 unused) | |
7faf1ab2 | 1219 | { |
6f65e29a | 1220 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; |
7faf1ab2 DV |
1221 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? |
1222 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
1223 | ||
6f65e29a BW |
1224 | BUG_ON(!i915_is_ggtt(vma->vm)); |
1225 | intel_gtt_insert_sg_entries(vma->obj->pages, entry, flags); | |
1226 | vma->obj->has_global_gtt_mapping = 1; | |
7faf1ab2 DV |
1227 | } |
1228 | ||
853ba5d2 | 1229 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
7faf1ab2 | 1230 | unsigned int first_entry, |
828c7908 BW |
1231 | unsigned int num_entries, |
1232 | bool unused) | |
7faf1ab2 DV |
1233 | { |
1234 | intel_gtt_clear_range(first_entry, num_entries); | |
1235 | } | |
1236 | ||
6f65e29a BW |
1237 | static void i915_ggtt_unbind_vma(struct i915_vma *vma) |
1238 | { | |
1239 | const unsigned int first = vma->node.start >> PAGE_SHIFT; | |
1240 | const unsigned int size = vma->obj->base.size >> PAGE_SHIFT; | |
7faf1ab2 | 1241 | |
6f65e29a BW |
1242 | BUG_ON(!i915_is_ggtt(vma->vm)); |
1243 | vma->obj->has_global_gtt_mapping = 0; | |
1244 | intel_gtt_clear_range(first, size); | |
1245 | } | |
1246 | ||
1247 | static void ggtt_bind_vma(struct i915_vma *vma, | |
1248 | enum i915_cache_level cache_level, | |
1249 | u32 flags) | |
d5bd1449 | 1250 | { |
6f65e29a | 1251 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1252 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a BW |
1253 | struct drm_i915_gem_object *obj = vma->obj; |
1254 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; | |
7faf1ab2 | 1255 | |
6f65e29a BW |
1256 | /* If there is no aliasing PPGTT, or the caller needs a global mapping, |
1257 | * or we have a global mapping already but the cacheability flags have | |
1258 | * changed, set the global PTEs. | |
1259 | * | |
1260 | * If there is an aliasing PPGTT it is anecdotally faster, so use that | |
1261 | * instead if none of the above hold true. | |
1262 | * | |
1263 | * NB: A global mapping should only be needed for special regions like | |
1264 | * "gtt mappable", SNB errata, or if specified via special execbuf | |
1265 | * flags. At all other times, the GPU will use the aliasing PPGTT. | |
1266 | */ | |
1267 | if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) { | |
1268 | if (!obj->has_global_gtt_mapping || | |
1269 | (cache_level != obj->cache_level)) { | |
1270 | vma->vm->insert_entries(vma->vm, obj->pages, entry, | |
1271 | cache_level); | |
1272 | obj->has_global_gtt_mapping = 1; | |
1273 | } | |
1274 | } | |
d5bd1449 | 1275 | |
6f65e29a BW |
1276 | if (dev_priv->mm.aliasing_ppgtt && |
1277 | (!obj->has_aliasing_ppgtt_mapping || | |
1278 | (cache_level != obj->cache_level))) { | |
1279 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; | |
1280 | appgtt->base.insert_entries(&appgtt->base, | |
1281 | vma->obj->pages, entry, cache_level); | |
1282 | vma->obj->has_aliasing_ppgtt_mapping = 1; | |
1283 | } | |
d5bd1449 CW |
1284 | } |
1285 | ||
6f65e29a | 1286 | static void ggtt_unbind_vma(struct i915_vma *vma) |
74163907 | 1287 | { |
6f65e29a | 1288 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1289 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a BW |
1290 | struct drm_i915_gem_object *obj = vma->obj; |
1291 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; | |
1292 | ||
1293 | if (obj->has_global_gtt_mapping) { | |
1294 | vma->vm->clear_range(vma->vm, entry, | |
1295 | vma->obj->base.size >> PAGE_SHIFT, | |
1296 | true); | |
1297 | obj->has_global_gtt_mapping = 0; | |
1298 | } | |
74898d7e | 1299 | |
6f65e29a BW |
1300 | if (obj->has_aliasing_ppgtt_mapping) { |
1301 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; | |
1302 | appgtt->base.clear_range(&appgtt->base, | |
1303 | entry, | |
1304 | obj->base.size >> PAGE_SHIFT, | |
1305 | true); | |
1306 | obj->has_aliasing_ppgtt_mapping = 0; | |
1307 | } | |
74163907 DV |
1308 | } |
1309 | ||
1310 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 1311 | { |
5c042287 BW |
1312 | struct drm_device *dev = obj->base.dev; |
1313 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1314 | bool interruptible; | |
1315 | ||
1316 | interruptible = do_idling(dev_priv); | |
1317 | ||
9da3da66 CW |
1318 | if (!obj->has_dma_mapping) |
1319 | dma_unmap_sg(&dev->pdev->dev, | |
1320 | obj->pages->sgl, obj->pages->nents, | |
1321 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
1322 | |
1323 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 1324 | } |
644ec02b | 1325 | |
42d6ab48 CW |
1326 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
1327 | unsigned long color, | |
1328 | unsigned long *start, | |
1329 | unsigned long *end) | |
1330 | { | |
1331 | if (node->color != color) | |
1332 | *start += 4096; | |
1333 | ||
1334 | if (!list_empty(&node->node_list)) { | |
1335 | node = list_entry(node->node_list.next, | |
1336 | struct drm_mm_node, | |
1337 | node_list); | |
1338 | if (node->allocated && node->color != color) | |
1339 | *end -= 4096; | |
1340 | } | |
1341 | } | |
fbe5d36e | 1342 | |
d7e5008f BW |
1343 | void i915_gem_setup_global_gtt(struct drm_device *dev, |
1344 | unsigned long start, | |
1345 | unsigned long mappable_end, | |
1346 | unsigned long end) | |
644ec02b | 1347 | { |
e78891ca BW |
1348 | /* Let GEM Manage all of the aperture. |
1349 | * | |
1350 | * However, leave one page at the end still bound to the scratch page. | |
1351 | * There are a number of places where the hardware apparently prefetches | |
1352 | * past the end of the object, and we've seen multiple hangs with the | |
1353 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
1354 | * aperture. One page should be enough to keep any prefetching inside | |
1355 | * of the aperture. | |
1356 | */ | |
40d74980 BW |
1357 | struct drm_i915_private *dev_priv = dev->dev_private; |
1358 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; | |
ed2f3452 CW |
1359 | struct drm_mm_node *entry; |
1360 | struct drm_i915_gem_object *obj; | |
1361 | unsigned long hole_start, hole_end; | |
644ec02b | 1362 | |
35451cb6 BW |
1363 | BUG_ON(mappable_end > end); |
1364 | ||
ed2f3452 | 1365 | /* Subtract the guard page ... */ |
40d74980 | 1366 | drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); |
42d6ab48 | 1367 | if (!HAS_LLC(dev)) |
93bd8649 | 1368 | dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; |
644ec02b | 1369 | |
ed2f3452 | 1370 | /* Mark any preallocated objects as occupied */ |
35c20a60 | 1371 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
40d74980 | 1372 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
b3a070cc | 1373 | int ret; |
edd41a87 | 1374 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
c6cfb325 BW |
1375 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
1376 | ||
1377 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); | |
40d74980 | 1378 | ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); |
c6cfb325 | 1379 | if (ret) |
b3a070cc | 1380 | DRM_DEBUG_KMS("Reservation failed\n"); |
ed2f3452 CW |
1381 | obj->has_global_gtt_mapping = 1; |
1382 | } | |
1383 | ||
853ba5d2 BW |
1384 | dev_priv->gtt.base.start = start; |
1385 | dev_priv->gtt.base.total = end - start; | |
644ec02b | 1386 | |
ed2f3452 | 1387 | /* Clear any non-preallocated blocks */ |
40d74980 | 1388 | drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { |
853ba5d2 | 1389 | const unsigned long count = (hole_end - hole_start) / PAGE_SIZE; |
ed2f3452 CW |
1390 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
1391 | hole_start, hole_end); | |
828c7908 | 1392 | ggtt_vm->clear_range(ggtt_vm, hole_start / PAGE_SIZE, count, true); |
ed2f3452 CW |
1393 | } |
1394 | ||
1395 | /* And finally clear the reserved guard page */ | |
828c7908 | 1396 | ggtt_vm->clear_range(ggtt_vm, end / PAGE_SIZE - 1, 1, true); |
e76e9aeb BW |
1397 | } |
1398 | ||
d7e5008f BW |
1399 | void i915_gem_init_global_gtt(struct drm_device *dev) |
1400 | { | |
1401 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1402 | unsigned long gtt_size, mappable_size; | |
d7e5008f | 1403 | |
853ba5d2 | 1404 | gtt_size = dev_priv->gtt.base.total; |
93d18799 | 1405 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f | 1406 | |
c8d4c0d6 | 1407 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
246cbfb5 | 1408 | if (USES_ALIASING_PPGTT(dev)) { |
d6660add | 1409 | struct i915_hw_ppgtt *ppgtt; |
e78891ca | 1410 | int ret; |
3eb1c005 | 1411 | |
d6660add BW |
1412 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); |
1413 | if (!ppgtt) { | |
1414 | DRM_ERROR("Aliased PPGTT setup failed -ENOMEM\n"); | |
1415 | return; | |
1416 | } | |
1417 | ||
1418 | ret = i915_gem_init_ppgtt(dev, ppgtt); | |
1419 | if (!ret) { | |
1420 | dev_priv->mm.aliasing_ppgtt = ppgtt; | |
1421 | return; | |
1422 | } | |
1423 | ||
1424 | kfree(ppgtt); | |
1425 | DRM_ERROR("Aliased PPGTT setup failed %d\n", ret); | |
d7e5008f | 1426 | } |
e76e9aeb BW |
1427 | } |
1428 | ||
1429 | static int setup_scratch_page(struct drm_device *dev) | |
1430 | { | |
1431 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1432 | struct page *page; | |
1433 | dma_addr_t dma_addr; | |
1434 | ||
1435 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
1436 | if (page == NULL) | |
1437 | return -ENOMEM; | |
1438 | get_page(page); | |
1439 | set_pages_uc(page, 1); | |
1440 | ||
1441 | #ifdef CONFIG_INTEL_IOMMU | |
1442 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
1443 | PCI_DMA_BIDIRECTIONAL); | |
1444 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) | |
1445 | return -EINVAL; | |
1446 | #else | |
1447 | dma_addr = page_to_phys(page); | |
1448 | #endif | |
853ba5d2 BW |
1449 | dev_priv->gtt.base.scratch.page = page; |
1450 | dev_priv->gtt.base.scratch.addr = dma_addr; | |
e76e9aeb BW |
1451 | |
1452 | return 0; | |
1453 | } | |
1454 | ||
1455 | static void teardown_scratch_page(struct drm_device *dev) | |
1456 | { | |
1457 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 BW |
1458 | struct page *page = dev_priv->gtt.base.scratch.page; |
1459 | ||
1460 | set_pages_wb(page, 1); | |
1461 | pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr, | |
e76e9aeb | 1462 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
853ba5d2 BW |
1463 | put_page(page); |
1464 | __free_page(page); | |
e76e9aeb BW |
1465 | } |
1466 | ||
1467 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) | |
1468 | { | |
1469 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
1470 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
1471 | return snb_gmch_ctl << 20; | |
1472 | } | |
1473 | ||
9459d252 BW |
1474 | static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
1475 | { | |
1476 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
1477 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
1478 | if (bdw_gmch_ctl) | |
1479 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
3a2ffb65 BW |
1480 | if (bdw_gmch_ctl > 4) { |
1481 | WARN_ON(!i915_preliminary_hw_support); | |
1482 | return 4<<20; | |
1483 | } | |
1484 | ||
9459d252 BW |
1485 | return bdw_gmch_ctl << 20; |
1486 | } | |
1487 | ||
baa09f5f | 1488 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
1489 | { |
1490 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
1491 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
1492 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
1493 | } | |
1494 | ||
9459d252 BW |
1495 | static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
1496 | { | |
1497 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
1498 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
1499 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
1500 | } | |
1501 | ||
63340133 BW |
1502 | static int ggtt_probe_common(struct drm_device *dev, |
1503 | size_t gtt_size) | |
1504 | { | |
1505 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1506 | phys_addr_t gtt_bus_addr; | |
1507 | int ret; | |
1508 | ||
1509 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
1510 | gtt_bus_addr = pci_resource_start(dev->pdev, 0) + | |
1511 | (pci_resource_len(dev->pdev, 0) / 2); | |
1512 | ||
1513 | dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size); | |
1514 | if (!dev_priv->gtt.gsm) { | |
1515 | DRM_ERROR("Failed to map the gtt page table\n"); | |
1516 | return -ENOMEM; | |
1517 | } | |
1518 | ||
1519 | ret = setup_scratch_page(dev); | |
1520 | if (ret) { | |
1521 | DRM_ERROR("Scratch setup failed\n"); | |
1522 | /* iounmap will also get called at remove, but meh */ | |
1523 | iounmap(dev_priv->gtt.gsm); | |
1524 | } | |
1525 | ||
1526 | return ret; | |
1527 | } | |
1528 | ||
fbe5d36e BW |
1529 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
1530 | * bits. When using advanced contexts each context stores its own PAT, but | |
1531 | * writing this data shouldn't be harmful even in those cases. */ | |
1532 | static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv) | |
1533 | { | |
1534 | #define GEN8_PPAT_UC (0<<0) | |
1535 | #define GEN8_PPAT_WC (1<<0) | |
1536 | #define GEN8_PPAT_WT (2<<0) | |
1537 | #define GEN8_PPAT_WB (3<<0) | |
1538 | #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) | |
1539 | /* FIXME(BDW): Bspec is completely confused about cache control bits. */ | |
1540 | #define GEN8_PPAT_LLC (1<<2) | |
1541 | #define GEN8_PPAT_LLCELLC (2<<2) | |
1542 | #define GEN8_PPAT_LLCeLLC (3<<2) | |
1543 | #define GEN8_PPAT_AGE(x) (x<<4) | |
1544 | #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) | |
1545 | uint64_t pat; | |
1546 | ||
1547 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
1548 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
1549 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
1550 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
1551 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
1552 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
1553 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
1554 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
1555 | ||
1556 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b | |
1557 | * write would work. */ | |
1558 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
1559 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
1560 | } | |
1561 | ||
63340133 BW |
1562 | static int gen8_gmch_probe(struct drm_device *dev, |
1563 | size_t *gtt_total, | |
1564 | size_t *stolen, | |
1565 | phys_addr_t *mappable_base, | |
1566 | unsigned long *mappable_end) | |
1567 | { | |
1568 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1569 | unsigned int gtt_size; | |
1570 | u16 snb_gmch_ctl; | |
1571 | int ret; | |
1572 | ||
1573 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
1574 | *mappable_base = pci_resource_start(dev->pdev, 2); | |
1575 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
1576 | ||
1577 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) | |
1578 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); | |
1579 | ||
1580 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
1581 | ||
1582 | *stolen = gen8_get_stolen_size(snb_gmch_ctl); | |
1583 | ||
1584 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
d31eb10e | 1585 | *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT; |
63340133 | 1586 | |
fbe5d36e BW |
1587 | gen8_setup_private_ppat(dev_priv); |
1588 | ||
63340133 BW |
1589 | ret = ggtt_probe_common(dev, gtt_size); |
1590 | ||
94ec8f61 BW |
1591 | dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range; |
1592 | dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries; | |
63340133 BW |
1593 | |
1594 | return ret; | |
1595 | } | |
1596 | ||
baa09f5f BW |
1597 | static int gen6_gmch_probe(struct drm_device *dev, |
1598 | size_t *gtt_total, | |
41907ddc BW |
1599 | size_t *stolen, |
1600 | phys_addr_t *mappable_base, | |
1601 | unsigned long *mappable_end) | |
e76e9aeb BW |
1602 | { |
1603 | struct drm_i915_private *dev_priv = dev->dev_private; | |
baa09f5f | 1604 | unsigned int gtt_size; |
e76e9aeb | 1605 | u16 snb_gmch_ctl; |
e76e9aeb BW |
1606 | int ret; |
1607 | ||
41907ddc BW |
1608 | *mappable_base = pci_resource_start(dev->pdev, 2); |
1609 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
1610 | ||
baa09f5f BW |
1611 | /* 64/512MB is the current min/max we actually know of, but this is just |
1612 | * a coarse sanity check. | |
e76e9aeb | 1613 | */ |
41907ddc | 1614 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
baa09f5f BW |
1615 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
1616 | dev_priv->gtt.mappable_end); | |
1617 | return -ENXIO; | |
e76e9aeb BW |
1618 | } |
1619 | ||
e76e9aeb BW |
1620 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
1621 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 1622 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
e76e9aeb | 1623 | |
c4ae25ec | 1624 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
a93e4161 | 1625 | |
63340133 BW |
1626 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
1627 | *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT; | |
e76e9aeb | 1628 | |
63340133 | 1629 | ret = ggtt_probe_common(dev, gtt_size); |
e76e9aeb | 1630 | |
853ba5d2 BW |
1631 | dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; |
1632 | dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; | |
7faf1ab2 | 1633 | |
e76e9aeb BW |
1634 | return ret; |
1635 | } | |
1636 | ||
853ba5d2 | 1637 | static void gen6_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 1638 | { |
853ba5d2 BW |
1639 | |
1640 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); | |
5ed16782 BW |
1641 | |
1642 | drm_mm_takedown(&vm->mm); | |
853ba5d2 BW |
1643 | iounmap(gtt->gsm); |
1644 | teardown_scratch_page(vm->dev); | |
644ec02b | 1645 | } |
baa09f5f BW |
1646 | |
1647 | static int i915_gmch_probe(struct drm_device *dev, | |
1648 | size_t *gtt_total, | |
41907ddc BW |
1649 | size_t *stolen, |
1650 | phys_addr_t *mappable_base, | |
1651 | unsigned long *mappable_end) | |
baa09f5f BW |
1652 | { |
1653 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1654 | int ret; | |
1655 | ||
baa09f5f BW |
1656 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
1657 | if (!ret) { | |
1658 | DRM_ERROR("failed to set up gmch\n"); | |
1659 | return -EIO; | |
1660 | } | |
1661 | ||
41907ddc | 1662 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
1663 | |
1664 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
853ba5d2 | 1665 | dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; |
baa09f5f BW |
1666 | |
1667 | return 0; | |
1668 | } | |
1669 | ||
853ba5d2 | 1670 | static void i915_gmch_remove(struct i915_address_space *vm) |
baa09f5f BW |
1671 | { |
1672 | intel_gmch_remove(); | |
1673 | } | |
1674 | ||
1675 | int i915_gem_gtt_init(struct drm_device *dev) | |
1676 | { | |
1677 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1678 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
1679 | int ret; |
1680 | ||
baa09f5f | 1681 | if (INTEL_INFO(dev)->gen <= 5) { |
b2f21b4d | 1682 | gtt->gtt_probe = i915_gmch_probe; |
853ba5d2 | 1683 | gtt->base.cleanup = i915_gmch_remove; |
63340133 | 1684 | } else if (INTEL_INFO(dev)->gen < 8) { |
b2f21b4d | 1685 | gtt->gtt_probe = gen6_gmch_probe; |
853ba5d2 | 1686 | gtt->base.cleanup = gen6_gmch_remove; |
4d15c145 | 1687 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
853ba5d2 | 1688 | gtt->base.pte_encode = iris_pte_encode; |
4d15c145 | 1689 | else if (IS_HASWELL(dev)) |
853ba5d2 | 1690 | gtt->base.pte_encode = hsw_pte_encode; |
b2f21b4d | 1691 | else if (IS_VALLEYVIEW(dev)) |
853ba5d2 | 1692 | gtt->base.pte_encode = byt_pte_encode; |
350ec881 CW |
1693 | else if (INTEL_INFO(dev)->gen >= 7) |
1694 | gtt->base.pte_encode = ivb_pte_encode; | |
b2f21b4d | 1695 | else |
350ec881 | 1696 | gtt->base.pte_encode = snb_pte_encode; |
63340133 BW |
1697 | } else { |
1698 | dev_priv->gtt.gtt_probe = gen8_gmch_probe; | |
1699 | dev_priv->gtt.base.cleanup = gen6_gmch_remove; | |
baa09f5f BW |
1700 | } |
1701 | ||
853ba5d2 | 1702 | ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, |
b2f21b4d | 1703 | >t->mappable_base, >t->mappable_end); |
a54c0c27 | 1704 | if (ret) |
baa09f5f | 1705 | return ret; |
baa09f5f | 1706 | |
853ba5d2 BW |
1707 | gtt->base.dev = dev; |
1708 | ||
baa09f5f | 1709 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
853ba5d2 BW |
1710 | DRM_INFO("Memory usable by graphics device = %zdM\n", |
1711 | gtt->base.total >> 20); | |
b2f21b4d BW |
1712 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); |
1713 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); | |
baa09f5f BW |
1714 | |
1715 | return 0; | |
1716 | } | |
6f65e29a BW |
1717 | |
1718 | static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj, | |
1719 | struct i915_address_space *vm) | |
1720 | { | |
1721 | struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL); | |
1722 | if (vma == NULL) | |
1723 | return ERR_PTR(-ENOMEM); | |
1724 | ||
1725 | INIT_LIST_HEAD(&vma->vma_link); | |
1726 | INIT_LIST_HEAD(&vma->mm_list); | |
1727 | INIT_LIST_HEAD(&vma->exec_list); | |
1728 | vma->vm = vm; | |
1729 | vma->obj = obj; | |
1730 | ||
1731 | switch (INTEL_INFO(vm->dev)->gen) { | |
1732 | case 8: | |
1733 | case 7: | |
1734 | case 6: | |
1735 | vma->unbind_vma = ggtt_unbind_vma; | |
1736 | vma->bind_vma = ggtt_bind_vma; | |
1737 | break; | |
1738 | case 5: | |
1739 | case 4: | |
1740 | case 3: | |
1741 | case 2: | |
1742 | BUG_ON(!i915_is_ggtt(vm)); | |
1743 | vma->unbind_vma = i915_ggtt_unbind_vma; | |
1744 | vma->bind_vma = i915_ggtt_bind_vma; | |
1745 | break; | |
1746 | default: | |
1747 | BUG(); | |
1748 | } | |
1749 | ||
1750 | /* Keep GGTT vmas first to make debug easier */ | |
1751 | if (i915_is_ggtt(vm)) | |
1752 | list_add(&vma->vma_link, &obj->vma_list); | |
1753 | else | |
1754 | list_add_tail(&vma->vma_link, &obj->vma_list); | |
1755 | ||
1756 | return vma; | |
1757 | } | |
1758 | ||
1759 | struct i915_vma * | |
1760 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
1761 | struct i915_address_space *vm) | |
1762 | { | |
1763 | struct i915_vma *vma; | |
1764 | ||
1765 | vma = i915_gem_obj_to_vma(obj, vm); | |
1766 | if (!vma) | |
1767 | vma = __i915_gem_vma_create(obj, vm); | |
1768 | ||
1769 | return vma; | |
1770 | } |