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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
c4ac524c | 3 | * Copyright © 2011-2014 Intel Corporation |
76aaf220 DV |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
aae4a3d8 CW |
26 | #include <linux/slab.h> /* fault-inject.h is not standalone! */ |
27 | ||
28 | #include <linux/fault-inject.h> | |
e007b19d | 29 | #include <linux/log2.h> |
606fec95 | 30 | #include <linux/random.h> |
0e46ce2e | 31 | #include <linux/seq_file.h> |
5bab6f60 | 32 | #include <linux/stop_machine.h> |
e007b19d | 33 | |
ed3ba079 LA |
34 | #include <asm/set_memory.h> |
35 | ||
760285e7 DH |
36 | #include <drm/drmP.h> |
37 | #include <drm/i915_drm.h> | |
e007b19d | 38 | |
76aaf220 | 39 | #include "i915_drv.h" |
5dda8fa3 | 40 | #include "i915_vgpu.h" |
76aaf220 DV |
41 | #include "i915_trace.h" |
42 | #include "intel_drv.h" | |
d07f0e59 | 43 | #include "intel_frontbuffer.h" |
76aaf220 | 44 | |
1abb70f5 | 45 | #define I915_GFP_ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN) |
bb8f9cff | 46 | |
45f8f69a TU |
47 | /** |
48 | * DOC: Global GTT views | |
49 | * | |
50 | * Background and previous state | |
51 | * | |
52 | * Historically objects could exists (be bound) in global GTT space only as | |
53 | * singular instances with a view representing all of the object's backing pages | |
54 | * in a linear fashion. This view will be called a normal view. | |
55 | * | |
56 | * To support multiple views of the same object, where the number of mapped | |
57 | * pages is not equal to the backing store, or where the layout of the pages | |
58 | * is not linear, concept of a GGTT view was added. | |
59 | * | |
60 | * One example of an alternative view is a stereo display driven by a single | |
61 | * image. In this case we would have a framebuffer looking like this | |
62 | * (2x2 pages): | |
63 | * | |
64 | * 12 | |
65 | * 34 | |
66 | * | |
67 | * Above would represent a normal GGTT view as normally mapped for GPU or CPU | |
68 | * rendering. In contrast, fed to the display engine would be an alternative | |
69 | * view which could look something like this: | |
70 | * | |
71 | * 1212 | |
72 | * 3434 | |
73 | * | |
74 | * In this example both the size and layout of pages in the alternative view is | |
75 | * different from the normal view. | |
76 | * | |
77 | * Implementation and usage | |
78 | * | |
79 | * GGTT views are implemented using VMAs and are distinguished via enum | |
80 | * i915_ggtt_view_type and struct i915_ggtt_view. | |
81 | * | |
82 | * A new flavour of core GEM functions which work with GGTT bound objects were | |
ec7adb6e JL |
83 | * added with the _ggtt_ infix, and sometimes with _view postfix to avoid |
84 | * renaming in large amounts of code. They take the struct i915_ggtt_view | |
85 | * parameter encapsulating all metadata required to implement a view. | |
45f8f69a TU |
86 | * |
87 | * As a helper for callers which are only interested in the normal view, | |
88 | * globally const i915_ggtt_view_normal singleton instance exists. All old core | |
89 | * GEM API functions, the ones not taking the view parameter, are operating on, | |
90 | * or with the normal GGTT view. | |
91 | * | |
92 | * Code wanting to add or use a new GGTT view needs to: | |
93 | * | |
94 | * 1. Add a new enum with a suitable name. | |
95 | * 2. Extend the metadata in the i915_ggtt_view structure if required. | |
96 | * 3. Add support to i915_get_vma_pages(). | |
97 | * | |
98 | * New views are required to build a scatter-gather table from within the | |
99 | * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and | |
100 | * exists for the lifetime of an VMA. | |
101 | * | |
102 | * Core API is designed to have copy semantics which means that passed in | |
103 | * struct i915_ggtt_view does not need to be persistent (left around after | |
104 | * calling the core API functions). | |
105 | * | |
106 | */ | |
107 | ||
70b9f6f8 DV |
108 | static int |
109 | i915_get_ggtt_vma_pages(struct i915_vma *vma); | |
110 | ||
7c3f86b6 CW |
111 | static void gen6_ggtt_invalidate(struct drm_i915_private *dev_priv) |
112 | { | |
ca6acc25 MK |
113 | /* |
114 | * Note that as an uncached mmio write, this will flush the | |
7c3f86b6 CW |
115 | * WCB of the writes into the GGTT before it triggers the invalidate. |
116 | */ | |
117 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
118 | } | |
119 | ||
120 | static void guc_ggtt_invalidate(struct drm_i915_private *dev_priv) | |
121 | { | |
122 | gen6_ggtt_invalidate(dev_priv); | |
123 | I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); | |
124 | } | |
125 | ||
126 | static void gmch_ggtt_invalidate(struct drm_i915_private *dev_priv) | |
127 | { | |
128 | intel_gtt_chipset_flush(); | |
129 | } | |
130 | ||
131 | static inline void i915_ggtt_invalidate(struct drm_i915_private *i915) | |
132 | { | |
133 | i915->ggtt.invalidate(i915); | |
134 | } | |
135 | ||
c033666a CW |
136 | int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, |
137 | int enable_ppgtt) | |
cfa7c862 | 138 | { |
1893a71b | 139 | bool has_full_ppgtt; |
1f9a99e0 | 140 | bool has_full_48bit_ppgtt; |
1893a71b | 141 | |
612dde7e JL |
142 | if (!dev_priv->info.has_aliasing_ppgtt) |
143 | return 0; | |
144 | ||
9e1d0e60 MT |
145 | has_full_ppgtt = dev_priv->info.has_full_ppgtt; |
146 | has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt; | |
1893a71b | 147 | |
e320d400 | 148 | if (intel_vgpu_active(dev_priv)) { |
8a4ab66f | 149 | /* GVT-g has no support for 32bit ppgtt */ |
e320d400 | 150 | has_full_ppgtt = false; |
8a4ab66f | 151 | has_full_48bit_ppgtt = intel_vgpu_has_full_48bit_ppgtt(dev_priv); |
e320d400 | 152 | } |
71ba2d64 | 153 | |
70ee45e1 DL |
154 | /* |
155 | * We don't allow disabling PPGTT for gen9+ as it's a requirement for | |
156 | * execlists, the sole mechanism available to submit work. | |
157 | */ | |
c033666a | 158 | if (enable_ppgtt == 0 && INTEL_GEN(dev_priv) < 9) |
cfa7c862 DV |
159 | return 0; |
160 | ||
161 | if (enable_ppgtt == 1) | |
162 | return 1; | |
163 | ||
1893a71b | 164 | if (enable_ppgtt == 2 && has_full_ppgtt) |
cfa7c862 DV |
165 | return 2; |
166 | ||
1f9a99e0 MT |
167 | if (enable_ppgtt == 3 && has_full_48bit_ppgtt) |
168 | return 3; | |
169 | ||
93a25a9e | 170 | /* Disable ppgtt on SNB if VT-d is on. */ |
80debff8 | 171 | if (IS_GEN6(dev_priv) && intel_vtd_active()) { |
93a25a9e | 172 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); |
cfa7c862 | 173 | return 0; |
93a25a9e | 174 | } |
93a25a9e | 175 | |
62942ed7 | 176 | /* Early VLV doesn't have this */ |
91c8a326 | 177 | if (IS_VALLEYVIEW(dev_priv) && dev_priv->drm.pdev->revision < 0xb) { |
62942ed7 JB |
178 | DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n"); |
179 | return 0; | |
180 | } | |
181 | ||
fb5c551a | 182 | if (HAS_LOGICAL_RING_CONTEXTS(dev_priv)) { |
4fc05063 JL |
183 | if (has_full_48bit_ppgtt) |
184 | return 3; | |
185 | ||
186 | if (has_full_ppgtt) | |
187 | return 2; | |
188 | } | |
189 | ||
612dde7e | 190 | return 1; |
93a25a9e DV |
191 | } |
192 | ||
549fe88b CW |
193 | static int ppgtt_bind_vma(struct i915_vma *vma, |
194 | enum i915_cache_level cache_level, | |
195 | u32 unused) | |
47552659 | 196 | { |
ff685975 | 197 | u32 pte_flags; |
549fe88b CW |
198 | int err; |
199 | ||
200 | if (!(vma->flags & I915_VMA_LOCAL_BIND)) { | |
201 | err = vma->vm->allocate_va_range(vma->vm, | |
202 | vma->node.start, vma->size); | |
203 | if (err) | |
204 | return err; | |
205 | } | |
47552659 DV |
206 | |
207 | /* Currently applicable only to VLV */ | |
ff685975 | 208 | pte_flags = 0; |
47552659 DV |
209 | if (vma->obj->gt_ro) |
210 | pte_flags |= PTE_READ_ONLY; | |
211 | ||
4a234c5f | 212 | vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags); |
70b9f6f8 DV |
213 | |
214 | return 0; | |
47552659 DV |
215 | } |
216 | ||
217 | static void ppgtt_unbind_vma(struct i915_vma *vma) | |
218 | { | |
ff685975 | 219 | vma->vm->clear_range(vma->vm, vma->node.start, vma->size); |
47552659 | 220 | } |
6f65e29a | 221 | |
fa3f46af MA |
222 | static int ppgtt_set_pages(struct i915_vma *vma) |
223 | { | |
224 | GEM_BUG_ON(vma->pages); | |
225 | ||
226 | vma->pages = vma->obj->mm.pages; | |
227 | ||
7464284b MA |
228 | vma->page_sizes = vma->obj->mm.page_sizes; |
229 | ||
fa3f46af MA |
230 | return 0; |
231 | } | |
232 | ||
233 | static void clear_pages(struct i915_vma *vma) | |
234 | { | |
235 | GEM_BUG_ON(!vma->pages); | |
236 | ||
237 | if (vma->pages != vma->obj->mm.pages) { | |
238 | sg_free_table(vma->pages); | |
239 | kfree(vma->pages); | |
240 | } | |
241 | vma->pages = NULL; | |
7464284b MA |
242 | |
243 | memset(&vma->page_sizes, 0, sizeof(vma->page_sizes)); | |
fa3f46af MA |
244 | } |
245 | ||
2c642b07 | 246 | static gen8_pte_t gen8_pte_encode(dma_addr_t addr, |
4fb84d99 | 247 | enum i915_cache_level level) |
94ec8f61 | 248 | { |
4fb84d99 | 249 | gen8_pte_t pte = _PAGE_PRESENT | _PAGE_RW; |
94ec8f61 | 250 | pte |= addr; |
63c42e56 BW |
251 | |
252 | switch (level) { | |
253 | case I915_CACHE_NONE: | |
c095b97c | 254 | pte |= PPAT_UNCACHED; |
63c42e56 BW |
255 | break; |
256 | case I915_CACHE_WT: | |
c095b97c | 257 | pte |= PPAT_DISPLAY_ELLC; |
63c42e56 BW |
258 | break; |
259 | default: | |
c095b97c | 260 | pte |= PPAT_CACHED; |
63c42e56 BW |
261 | break; |
262 | } | |
263 | ||
94ec8f61 BW |
264 | return pte; |
265 | } | |
266 | ||
fe36f55d MK |
267 | static gen8_pde_t gen8_pde_encode(const dma_addr_t addr, |
268 | const enum i915_cache_level level) | |
b1fe6673 | 269 | { |
07749ef3 | 270 | gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW; |
b1fe6673 BW |
271 | pde |= addr; |
272 | if (level != I915_CACHE_NONE) | |
c095b97c | 273 | pde |= PPAT_CACHED_PDE; |
b1fe6673 | 274 | else |
c095b97c | 275 | pde |= PPAT_UNCACHED; |
b1fe6673 BW |
276 | return pde; |
277 | } | |
278 | ||
762d9936 MT |
279 | #define gen8_pdpe_encode gen8_pde_encode |
280 | #define gen8_pml4e_encode gen8_pde_encode | |
281 | ||
07749ef3 MT |
282 | static gen6_pte_t snb_pte_encode(dma_addr_t addr, |
283 | enum i915_cache_level level, | |
4fb84d99 | 284 | u32 unused) |
54d12527 | 285 | { |
4fb84d99 | 286 | gen6_pte_t pte = GEN6_PTE_VALID; |
54d12527 | 287 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
288 | |
289 | switch (level) { | |
350ec881 CW |
290 | case I915_CACHE_L3_LLC: |
291 | case I915_CACHE_LLC: | |
292 | pte |= GEN6_PTE_CACHE_LLC; | |
293 | break; | |
294 | case I915_CACHE_NONE: | |
295 | pte |= GEN6_PTE_UNCACHED; | |
296 | break; | |
297 | default: | |
5f77eeb0 | 298 | MISSING_CASE(level); |
350ec881 CW |
299 | } |
300 | ||
301 | return pte; | |
302 | } | |
303 | ||
07749ef3 MT |
304 | static gen6_pte_t ivb_pte_encode(dma_addr_t addr, |
305 | enum i915_cache_level level, | |
4fb84d99 | 306 | u32 unused) |
350ec881 | 307 | { |
4fb84d99 | 308 | gen6_pte_t pte = GEN6_PTE_VALID; |
350ec881 CW |
309 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
310 | ||
311 | switch (level) { | |
312 | case I915_CACHE_L3_LLC: | |
313 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
314 | break; |
315 | case I915_CACHE_LLC: | |
316 | pte |= GEN6_PTE_CACHE_LLC; | |
317 | break; | |
318 | case I915_CACHE_NONE: | |
9119708c | 319 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
320 | break; |
321 | default: | |
5f77eeb0 | 322 | MISSING_CASE(level); |
e7210c3c BW |
323 | } |
324 | ||
54d12527 BW |
325 | return pte; |
326 | } | |
327 | ||
07749ef3 MT |
328 | static gen6_pte_t byt_pte_encode(dma_addr_t addr, |
329 | enum i915_cache_level level, | |
4fb84d99 | 330 | u32 flags) |
93c34e70 | 331 | { |
4fb84d99 | 332 | gen6_pte_t pte = GEN6_PTE_VALID; |
93c34e70 KG |
333 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
334 | ||
24f3a8cf AG |
335 | if (!(flags & PTE_READ_ONLY)) |
336 | pte |= BYT_PTE_WRITEABLE; | |
93c34e70 KG |
337 | |
338 | if (level != I915_CACHE_NONE) | |
339 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
340 | ||
341 | return pte; | |
342 | } | |
343 | ||
07749ef3 MT |
344 | static gen6_pte_t hsw_pte_encode(dma_addr_t addr, |
345 | enum i915_cache_level level, | |
4fb84d99 | 346 | u32 unused) |
9119708c | 347 | { |
4fb84d99 | 348 | gen6_pte_t pte = GEN6_PTE_VALID; |
0d8ff15e | 349 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
350 | |
351 | if (level != I915_CACHE_NONE) | |
87a6b688 | 352 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
353 | |
354 | return pte; | |
355 | } | |
356 | ||
07749ef3 MT |
357 | static gen6_pte_t iris_pte_encode(dma_addr_t addr, |
358 | enum i915_cache_level level, | |
4fb84d99 | 359 | u32 unused) |
4d15c145 | 360 | { |
4fb84d99 | 361 | gen6_pte_t pte = GEN6_PTE_VALID; |
4d15c145 BW |
362 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
363 | ||
651d794f CW |
364 | switch (level) { |
365 | case I915_CACHE_NONE: | |
366 | break; | |
367 | case I915_CACHE_WT: | |
c51e9701 | 368 | pte |= HSW_WT_ELLC_LLC_AGE3; |
651d794f CW |
369 | break; |
370 | default: | |
c51e9701 | 371 | pte |= HSW_WB_ELLC_LLC_AGE3; |
651d794f CW |
372 | break; |
373 | } | |
4d15c145 BW |
374 | |
375 | return pte; | |
376 | } | |
377 | ||
8448661d | 378 | static struct page *vm_alloc_page(struct i915_address_space *vm, gfp_t gfp) |
678d96fb | 379 | { |
66df1014 | 380 | struct pagevec *pvec = &vm->free_pages; |
073cd781 | 381 | struct pagevec stash; |
678d96fb | 382 | |
8448661d CW |
383 | if (I915_SELFTEST_ONLY(should_fail(&vm->fault_attr, 1))) |
384 | i915_gem_shrink_all(vm->i915); | |
aae4a3d8 | 385 | |
66df1014 CW |
386 | if (likely(pvec->nr)) |
387 | return pvec->pages[--pvec->nr]; | |
388 | ||
389 | if (!vm->pt_kmap_wc) | |
390 | return alloc_page(gfp); | |
391 | ||
392 | /* A placeholder for a specific mutex to guard the WC stash */ | |
393 | lockdep_assert_held(&vm->i915->drm.struct_mutex); | |
394 | ||
395 | /* Look in our global stash of WC pages... */ | |
396 | pvec = &vm->i915->mm.wc_stash; | |
397 | if (likely(pvec->nr)) | |
398 | return pvec->pages[--pvec->nr]; | |
399 | ||
073cd781 CW |
400 | /* |
401 | * Otherwise batch allocate pages to amoritize cost of set_pages_wc. | |
402 | * | |
403 | * We have to be careful as page allocation may trigger the shrinker | |
404 | * (via direct reclaim) which will fill up the WC stash underneath us. | |
405 | * So we add our WB pages into a temporary pvec on the stack and merge | |
406 | * them into the WC stash after all the allocations are complete. | |
407 | */ | |
408 | pagevec_init(&stash); | |
66df1014 CW |
409 | do { |
410 | struct page *page; | |
8448661d | 411 | |
66df1014 CW |
412 | page = alloc_page(gfp); |
413 | if (unlikely(!page)) | |
414 | break; | |
415 | ||
073cd781 CW |
416 | stash.pages[stash.nr++] = page; |
417 | } while (stash.nr < pagevec_space(pvec)); | |
66df1014 | 418 | |
073cd781 CW |
419 | if (stash.nr) { |
420 | int nr = min_t(int, stash.nr, pagevec_space(pvec)); | |
421 | struct page **pages = stash.pages + stash.nr - nr; | |
8448661d | 422 | |
073cd781 CW |
423 | if (nr && !set_pages_array_wc(pages, nr)) { |
424 | memcpy(pvec->pages + pvec->nr, | |
425 | pages, sizeof(pages[0]) * nr); | |
426 | pvec->nr += nr; | |
427 | stash.nr -= nr; | |
428 | } | |
429 | ||
430 | pagevec_release(&stash); | |
431 | } | |
8448661d | 432 | |
073cd781 | 433 | return likely(pvec->nr) ? pvec->pages[--pvec->nr] : NULL; |
8448661d CW |
434 | } |
435 | ||
66df1014 CW |
436 | static void vm_free_pages_release(struct i915_address_space *vm, |
437 | bool immediate) | |
8448661d | 438 | { |
66df1014 CW |
439 | struct pagevec *pvec = &vm->free_pages; |
440 | ||
441 | GEM_BUG_ON(!pagevec_count(pvec)); | |
8448661d | 442 | |
66df1014 CW |
443 | if (vm->pt_kmap_wc) { |
444 | struct pagevec *stash = &vm->i915->mm.wc_stash; | |
445 | ||
446 | /* When we use WC, first fill up the global stash and then | |
447 | * only if full immediately free the overflow. | |
448 | */ | |
8448661d | 449 | |
66df1014 CW |
450 | lockdep_assert_held(&vm->i915->drm.struct_mutex); |
451 | if (pagevec_space(stash)) { | |
452 | do { | |
453 | stash->pages[stash->nr++] = | |
454 | pvec->pages[--pvec->nr]; | |
455 | if (!pvec->nr) | |
456 | return; | |
457 | } while (pagevec_space(stash)); | |
458 | ||
459 | /* As we have made some room in the VM's free_pages, | |
460 | * we can wait for it to fill again. Unless we are | |
461 | * inside i915_address_space_fini() and must | |
462 | * immediately release the pages! | |
463 | */ | |
464 | if (!immediate) | |
465 | return; | |
466 | } | |
467 | ||
468 | set_pages_array_wb(pvec->pages, pvec->nr); | |
469 | } | |
470 | ||
471 | __pagevec_release(pvec); | |
8448661d CW |
472 | } |
473 | ||
474 | static void vm_free_page(struct i915_address_space *vm, struct page *page) | |
475 | { | |
15e4cda9 CW |
476 | /* |
477 | * On !llc, we need to change the pages back to WB. We only do so | |
478 | * in bulk, so we rarely need to change the page attributes here, | |
479 | * but doing so requires a stop_machine() from deep inside arch/x86/mm. | |
480 | * To make detection of the possible sleep more likely, use an | |
481 | * unconditional might_sleep() for everybody. | |
482 | */ | |
483 | might_sleep(); | |
8448661d | 484 | if (!pagevec_add(&vm->free_pages, page)) |
66df1014 | 485 | vm_free_pages_release(vm, false); |
8448661d | 486 | } |
678d96fb | 487 | |
8448661d CW |
488 | static int __setup_page_dma(struct i915_address_space *vm, |
489 | struct i915_page_dma *p, | |
490 | gfp_t gfp) | |
491 | { | |
1abb70f5 | 492 | p->page = vm_alloc_page(vm, gfp | I915_GFP_ALLOW_FAIL); |
8448661d CW |
493 | if (unlikely(!p->page)) |
494 | return -ENOMEM; | |
678d96fb | 495 | |
8448661d CW |
496 | p->daddr = dma_map_page(vm->dma, p->page, 0, PAGE_SIZE, |
497 | PCI_DMA_BIDIRECTIONAL); | |
498 | if (unlikely(dma_mapping_error(vm->dma, p->daddr))) { | |
499 | vm_free_page(vm, p->page); | |
500 | return -ENOMEM; | |
44159ddb | 501 | } |
1266cdb1 MT |
502 | |
503 | return 0; | |
678d96fb BW |
504 | } |
505 | ||
8448661d | 506 | static int setup_page_dma(struct i915_address_space *vm, |
275a991c | 507 | struct i915_page_dma *p) |
c114f76a | 508 | { |
1abb70f5 | 509 | return __setup_page_dma(vm, p, __GFP_HIGHMEM); |
c114f76a MK |
510 | } |
511 | ||
8448661d | 512 | static void cleanup_page_dma(struct i915_address_space *vm, |
275a991c | 513 | struct i915_page_dma *p) |
06fda602 | 514 | { |
8448661d CW |
515 | dma_unmap_page(vm->dma, p->daddr, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
516 | vm_free_page(vm, p->page); | |
44159ddb MK |
517 | } |
518 | ||
9231da70 | 519 | #define kmap_atomic_px(px) kmap_atomic(px_base(px)->page) |
d1c54acd | 520 | |
8448661d CW |
521 | #define setup_px(vm, px) setup_page_dma((vm), px_base(px)) |
522 | #define cleanup_px(vm, px) cleanup_page_dma((vm), px_base(px)) | |
64b3c936 CW |
523 | #define fill_px(vm, px, v) fill_page_dma((vm), px_base(px), (v)) |
524 | #define fill32_px(vm, px, v) fill_page_dma_32((vm), px_base(px), (v)) | |
567047be | 525 | |
8448661d CW |
526 | static void fill_page_dma(struct i915_address_space *vm, |
527 | struct i915_page_dma *p, | |
528 | const u64 val) | |
d1c54acd | 529 | { |
9231da70 | 530 | u64 * const vaddr = kmap_atomic(p->page); |
d1c54acd | 531 | |
4dd504f7 | 532 | memset64(vaddr, val, PAGE_SIZE / sizeof(val)); |
d1c54acd | 533 | |
9231da70 | 534 | kunmap_atomic(vaddr); |
d1c54acd MK |
535 | } |
536 | ||
8448661d CW |
537 | static void fill_page_dma_32(struct i915_address_space *vm, |
538 | struct i915_page_dma *p, | |
539 | const u32 v) | |
73eeea53 | 540 | { |
8448661d | 541 | fill_page_dma(vm, p, (u64)v << 32 | v); |
73eeea53 MK |
542 | } |
543 | ||
8bcdd0f7 | 544 | static int |
8448661d | 545 | setup_scratch_page(struct i915_address_space *vm, gfp_t gfp) |
4ad2af1e | 546 | { |
7fb9ee5d | 547 | unsigned long size; |
66df1014 | 548 | |
aa095871 MA |
549 | /* |
550 | * In order to utilize 64K pages for an object with a size < 2M, we will | |
551 | * need to support a 64K scratch page, given that every 16th entry for a | |
552 | * page-table operating in 64K mode must point to a properly aligned 64K | |
553 | * region, including any PTEs which happen to point to scratch. | |
554 | * | |
555 | * This is only relevant for the 48b PPGTT where we support | |
556 | * huge-gtt-pages, see also i915_vma_insert(). | |
557 | * | |
558 | * TODO: we should really consider write-protecting the scratch-page and | |
559 | * sharing between ppgtt | |
560 | */ | |
7fb9ee5d | 561 | size = I915_GTT_PAGE_SIZE_4K; |
aa095871 MA |
562 | if (i915_vm_is_48bit(vm) && |
563 | HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K)) { | |
7fb9ee5d CW |
564 | size = I915_GTT_PAGE_SIZE_64K; |
565 | gfp |= __GFP_NOWARN; | |
aa095871 | 566 | } |
7fb9ee5d CW |
567 | gfp |= __GFP_ZERO | __GFP_RETRY_MAYFAIL; |
568 | ||
569 | do { | |
570 | int order = get_order(size); | |
571 | struct page *page; | |
572 | dma_addr_t addr; | |
66df1014 | 573 | |
7fb9ee5d | 574 | page = alloc_pages(gfp, order); |
aa095871 | 575 | if (unlikely(!page)) |
7fb9ee5d | 576 | goto skip; |
aa095871 | 577 | |
7fb9ee5d | 578 | addr = dma_map_page(vm->dma, page, 0, size, |
aa095871 | 579 | PCI_DMA_BIDIRECTIONAL); |
7fb9ee5d CW |
580 | if (unlikely(dma_mapping_error(vm->dma, addr))) |
581 | goto free_page; | |
66df1014 | 582 | |
7fb9ee5d CW |
583 | if (unlikely(!IS_ALIGNED(addr, size))) |
584 | goto unmap_page; | |
aa095871 | 585 | |
7fb9ee5d CW |
586 | vm->scratch_page.page = page; |
587 | vm->scratch_page.daddr = addr; | |
588 | vm->scratch_page.order = order; | |
589 | return 0; | |
590 | ||
591 | unmap_page: | |
592 | dma_unmap_page(vm->dma, addr, size, PCI_DMA_BIDIRECTIONAL); | |
593 | free_page: | |
594 | __free_pages(page, order); | |
595 | skip: | |
596 | if (size == I915_GTT_PAGE_SIZE_4K) | |
597 | return -ENOMEM; | |
598 | ||
599 | size = I915_GTT_PAGE_SIZE_4K; | |
600 | gfp &= ~__GFP_NOWARN; | |
601 | } while (1); | |
4ad2af1e MK |
602 | } |
603 | ||
8448661d | 604 | static void cleanup_scratch_page(struct i915_address_space *vm) |
4ad2af1e | 605 | { |
66df1014 CW |
606 | struct i915_page_dma *p = &vm->scratch_page; |
607 | ||
aa095871 MA |
608 | dma_unmap_page(vm->dma, p->daddr, BIT(p->order) << PAGE_SHIFT, |
609 | PCI_DMA_BIDIRECTIONAL); | |
610 | __free_pages(p->page, p->order); | |
4ad2af1e MK |
611 | } |
612 | ||
8448661d | 613 | static struct i915_page_table *alloc_pt(struct i915_address_space *vm) |
06fda602 | 614 | { |
ec565b3c | 615 | struct i915_page_table *pt; |
06fda602 | 616 | |
1abb70f5 | 617 | pt = kmalloc(sizeof(*pt), I915_GFP_ALLOW_FAIL); |
dd19674b | 618 | if (unlikely(!pt)) |
06fda602 BW |
619 | return ERR_PTR(-ENOMEM); |
620 | ||
dd19674b CW |
621 | if (unlikely(setup_px(vm, pt))) { |
622 | kfree(pt); | |
623 | return ERR_PTR(-ENOMEM); | |
624 | } | |
06fda602 | 625 | |
dd19674b | 626 | pt->used_ptes = 0; |
06fda602 BW |
627 | return pt; |
628 | } | |
629 | ||
8448661d | 630 | static void free_pt(struct i915_address_space *vm, struct i915_page_table *pt) |
06fda602 | 631 | { |
8448661d | 632 | cleanup_px(vm, pt); |
2e906bea MK |
633 | kfree(pt); |
634 | } | |
635 | ||
636 | static void gen8_initialize_pt(struct i915_address_space *vm, | |
637 | struct i915_page_table *pt) | |
638 | { | |
dd19674b CW |
639 | fill_px(vm, pt, |
640 | gen8_pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC)); | |
2e906bea MK |
641 | } |
642 | ||
986dbac4 | 643 | static void gen6_initialize_pt(struct gen6_hw_ppgtt *ppgtt, |
2e906bea MK |
644 | struct i915_page_table *pt) |
645 | { | |
986dbac4 | 646 | fill32_px(&ppgtt->base.vm, pt, ppgtt->scratch_pte); |
06fda602 BW |
647 | } |
648 | ||
8448661d | 649 | static struct i915_page_directory *alloc_pd(struct i915_address_space *vm) |
06fda602 | 650 | { |
ec565b3c | 651 | struct i915_page_directory *pd; |
06fda602 | 652 | |
1abb70f5 | 653 | pd = kzalloc(sizeof(*pd), I915_GFP_ALLOW_FAIL); |
fe52e37f | 654 | if (unlikely(!pd)) |
06fda602 BW |
655 | return ERR_PTR(-ENOMEM); |
656 | ||
fe52e37f CW |
657 | if (unlikely(setup_px(vm, pd))) { |
658 | kfree(pd); | |
659 | return ERR_PTR(-ENOMEM); | |
660 | } | |
e5815a2e | 661 | |
fe52e37f | 662 | pd->used_pdes = 0; |
06fda602 BW |
663 | return pd; |
664 | } | |
665 | ||
8448661d | 666 | static void free_pd(struct i915_address_space *vm, |
275a991c | 667 | struct i915_page_directory *pd) |
2e906bea | 668 | { |
fe52e37f CW |
669 | cleanup_px(vm, pd); |
670 | kfree(pd); | |
2e906bea MK |
671 | } |
672 | ||
673 | static void gen8_initialize_pd(struct i915_address_space *vm, | |
674 | struct i915_page_directory *pd) | |
675 | { | |
dd19674b CW |
676 | fill_px(vm, pd, |
677 | gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC)); | |
e53792f4 | 678 | memset_p((void **)pd->page_table, vm->scratch_pt, I915_PDES); |
2e906bea MK |
679 | } |
680 | ||
fe52e37f | 681 | static int __pdp_init(struct i915_address_space *vm, |
6ac18502 MT |
682 | struct i915_page_directory_pointer *pdp) |
683 | { | |
3e490042 | 684 | const unsigned int pdpes = i915_pdpes_per_pdp(vm); |
6ac18502 | 685 | |
fe52e37f | 686 | pdp->page_directory = kmalloc_array(pdpes, sizeof(*pdp->page_directory), |
1abb70f5 | 687 | I915_GFP_ALLOW_FAIL); |
e2b763ca | 688 | if (unlikely(!pdp->page_directory)) |
6ac18502 | 689 | return -ENOMEM; |
6ac18502 | 690 | |
e53792f4 | 691 | memset_p((void **)pdp->page_directory, vm->scratch_pd, pdpes); |
fe52e37f | 692 | |
6ac18502 MT |
693 | return 0; |
694 | } | |
695 | ||
696 | static void __pdp_fini(struct i915_page_directory_pointer *pdp) | |
697 | { | |
6ac18502 MT |
698 | kfree(pdp->page_directory); |
699 | pdp->page_directory = NULL; | |
700 | } | |
701 | ||
1e6437b0 MK |
702 | static inline bool use_4lvl(const struct i915_address_space *vm) |
703 | { | |
704 | return i915_vm_is_48bit(vm); | |
705 | } | |
706 | ||
8448661d CW |
707 | static struct i915_page_directory_pointer * |
708 | alloc_pdp(struct i915_address_space *vm) | |
762d9936 MT |
709 | { |
710 | struct i915_page_directory_pointer *pdp; | |
711 | int ret = -ENOMEM; | |
712 | ||
62d4028f | 713 | GEM_BUG_ON(!use_4lvl(vm)); |
762d9936 MT |
714 | |
715 | pdp = kzalloc(sizeof(*pdp), GFP_KERNEL); | |
716 | if (!pdp) | |
717 | return ERR_PTR(-ENOMEM); | |
718 | ||
fe52e37f | 719 | ret = __pdp_init(vm, pdp); |
762d9936 MT |
720 | if (ret) |
721 | goto fail_bitmap; | |
722 | ||
8448661d | 723 | ret = setup_px(vm, pdp); |
762d9936 MT |
724 | if (ret) |
725 | goto fail_page_m; | |
726 | ||
727 | return pdp; | |
728 | ||
729 | fail_page_m: | |
730 | __pdp_fini(pdp); | |
731 | fail_bitmap: | |
732 | kfree(pdp); | |
733 | ||
734 | return ERR_PTR(ret); | |
735 | } | |
736 | ||
8448661d | 737 | static void free_pdp(struct i915_address_space *vm, |
6ac18502 MT |
738 | struct i915_page_directory_pointer *pdp) |
739 | { | |
740 | __pdp_fini(pdp); | |
1e6437b0 MK |
741 | |
742 | if (!use_4lvl(vm)) | |
743 | return; | |
744 | ||
745 | cleanup_px(vm, pdp); | |
746 | kfree(pdp); | |
762d9936 MT |
747 | } |
748 | ||
69ab76fd MT |
749 | static void gen8_initialize_pdp(struct i915_address_space *vm, |
750 | struct i915_page_directory_pointer *pdp) | |
751 | { | |
752 | gen8_ppgtt_pdpe_t scratch_pdpe; | |
753 | ||
754 | scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC); | |
755 | ||
8448661d | 756 | fill_px(vm, pdp, scratch_pdpe); |
69ab76fd MT |
757 | } |
758 | ||
759 | static void gen8_initialize_pml4(struct i915_address_space *vm, | |
760 | struct i915_pml4 *pml4) | |
761 | { | |
e2b763ca CW |
762 | fill_px(vm, pml4, |
763 | gen8_pml4e_encode(px_dma(vm->scratch_pdp), I915_CACHE_LLC)); | |
e53792f4 | 764 | memset_p((void **)pml4->pdps, vm->scratch_pdp, GEN8_PML4ES_PER_PML4); |
6ac18502 MT |
765 | } |
766 | ||
fce93755 MK |
767 | /* PDE TLBs are a pain to invalidate on GEN8+. When we modify |
768 | * the page table structures, we mark them dirty so that | |
769 | * context switching/execlist queuing code takes extra steps | |
770 | * to ensure that tlbs are flushed. | |
771 | */ | |
772 | static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt) | |
773 | { | |
82ad6443 | 774 | ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->vm.i915)->ring_mask; |
fce93755 MK |
775 | } |
776 | ||
2ce5179f MW |
777 | /* Removes entries from a single page table, releasing it if it's empty. |
778 | * Caller can use the return value to update higher-level entries. | |
779 | */ | |
780 | static bool gen8_ppgtt_clear_pt(struct i915_address_space *vm, | |
d209b9c3 | 781 | struct i915_page_table *pt, |
dd19674b | 782 | u64 start, u64 length) |
459108b8 | 783 | { |
d209b9c3 | 784 | unsigned int num_entries = gen8_pte_count(start, length); |
37c63934 MK |
785 | unsigned int pte = gen8_pte_index(start); |
786 | unsigned int pte_end = pte + num_entries; | |
894ccebe CW |
787 | const gen8_pte_t scratch_pte = |
788 | gen8_pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC); | |
789 | gen8_pte_t *vaddr; | |
459108b8 | 790 | |
dd19674b | 791 | GEM_BUG_ON(num_entries > pt->used_ptes); |
37c63934 | 792 | |
dd19674b CW |
793 | pt->used_ptes -= num_entries; |
794 | if (!pt->used_ptes) | |
795 | return true; | |
2ce5179f | 796 | |
9231da70 | 797 | vaddr = kmap_atomic_px(pt); |
37c63934 | 798 | while (pte < pte_end) |
894ccebe | 799 | vaddr[pte++] = scratch_pte; |
9231da70 | 800 | kunmap_atomic(vaddr); |
2ce5179f MW |
801 | |
802 | return false; | |
d209b9c3 | 803 | } |
06fda602 | 804 | |
dd19674b CW |
805 | static void gen8_ppgtt_set_pde(struct i915_address_space *vm, |
806 | struct i915_page_directory *pd, | |
807 | struct i915_page_table *pt, | |
808 | unsigned int pde) | |
809 | { | |
810 | gen8_pde_t *vaddr; | |
811 | ||
812 | pd->page_table[pde] = pt; | |
813 | ||
814 | vaddr = kmap_atomic_px(pd); | |
815 | vaddr[pde] = gen8_pde_encode(px_dma(pt), I915_CACHE_LLC); | |
816 | kunmap_atomic(vaddr); | |
817 | } | |
818 | ||
2ce5179f | 819 | static bool gen8_ppgtt_clear_pd(struct i915_address_space *vm, |
d209b9c3 | 820 | struct i915_page_directory *pd, |
dd19674b | 821 | u64 start, u64 length) |
d209b9c3 MW |
822 | { |
823 | struct i915_page_table *pt; | |
dd19674b | 824 | u32 pde; |
d209b9c3 MW |
825 | |
826 | gen8_for_each_pde(pt, pd, start, length, pde) { | |
bf75d59e CW |
827 | GEM_BUG_ON(pt == vm->scratch_pt); |
828 | ||
dd19674b CW |
829 | if (!gen8_ppgtt_clear_pt(vm, pt, start, length)) |
830 | continue; | |
06fda602 | 831 | |
dd19674b | 832 | gen8_ppgtt_set_pde(vm, pd, vm->scratch_pt, pde); |
bf75d59e | 833 | GEM_BUG_ON(!pd->used_pdes); |
fe52e37f | 834 | pd->used_pdes--; |
dd19674b CW |
835 | |
836 | free_pt(vm, pt); | |
2ce5179f MW |
837 | } |
838 | ||
fe52e37f CW |
839 | return !pd->used_pdes; |
840 | } | |
2ce5179f | 841 | |
fe52e37f CW |
842 | static void gen8_ppgtt_set_pdpe(struct i915_address_space *vm, |
843 | struct i915_page_directory_pointer *pdp, | |
844 | struct i915_page_directory *pd, | |
845 | unsigned int pdpe) | |
846 | { | |
847 | gen8_ppgtt_pdpe_t *vaddr; | |
848 | ||
849 | pdp->page_directory[pdpe] = pd; | |
1e6437b0 | 850 | if (!use_4lvl(vm)) |
fe52e37f CW |
851 | return; |
852 | ||
853 | vaddr = kmap_atomic_px(pdp); | |
854 | vaddr[pdpe] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC); | |
855 | kunmap_atomic(vaddr); | |
d209b9c3 | 856 | } |
06fda602 | 857 | |
2ce5179f MW |
858 | /* Removes entries from a single page dir pointer, releasing it if it's empty. |
859 | * Caller can use the return value to update higher-level entries | |
860 | */ | |
861 | static bool gen8_ppgtt_clear_pdp(struct i915_address_space *vm, | |
d209b9c3 | 862 | struct i915_page_directory_pointer *pdp, |
fe52e37f | 863 | u64 start, u64 length) |
d209b9c3 MW |
864 | { |
865 | struct i915_page_directory *pd; | |
fe52e37f | 866 | unsigned int pdpe; |
06fda602 | 867 | |
d209b9c3 | 868 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
bf75d59e CW |
869 | GEM_BUG_ON(pd == vm->scratch_pd); |
870 | ||
fe52e37f CW |
871 | if (!gen8_ppgtt_clear_pd(vm, pd, start, length)) |
872 | continue; | |
459108b8 | 873 | |
fe52e37f | 874 | gen8_ppgtt_set_pdpe(vm, pdp, vm->scratch_pd, pdpe); |
bf75d59e | 875 | GEM_BUG_ON(!pdp->used_pdpes); |
e2b763ca | 876 | pdp->used_pdpes--; |
2ce5179f | 877 | |
fe52e37f CW |
878 | free_pd(vm, pd); |
879 | } | |
fce93755 | 880 | |
e2b763ca | 881 | return !pdp->used_pdpes; |
d209b9c3 | 882 | } |
459108b8 | 883 | |
fe52e37f CW |
884 | static void gen8_ppgtt_clear_3lvl(struct i915_address_space *vm, |
885 | u64 start, u64 length) | |
886 | { | |
887 | gen8_ppgtt_clear_pdp(vm, &i915_vm_to_ppgtt(vm)->pdp, start, length); | |
888 | } | |
889 | ||
e2b763ca CW |
890 | static void gen8_ppgtt_set_pml4e(struct i915_pml4 *pml4, |
891 | struct i915_page_directory_pointer *pdp, | |
892 | unsigned int pml4e) | |
893 | { | |
894 | gen8_ppgtt_pml4e_t *vaddr; | |
895 | ||
896 | pml4->pdps[pml4e] = pdp; | |
897 | ||
898 | vaddr = kmap_atomic_px(pml4); | |
899 | vaddr[pml4e] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC); | |
900 | kunmap_atomic(vaddr); | |
901 | } | |
902 | ||
2ce5179f MW |
903 | /* Removes entries from a single pml4. |
904 | * This is the top-level structure in 4-level page tables used on gen8+. | |
905 | * Empty entries are always scratch pml4e. | |
906 | */ | |
fe52e37f CW |
907 | static void gen8_ppgtt_clear_4lvl(struct i915_address_space *vm, |
908 | u64 start, u64 length) | |
d209b9c3 | 909 | { |
fe52e37f CW |
910 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
911 | struct i915_pml4 *pml4 = &ppgtt->pml4; | |
d209b9c3 | 912 | struct i915_page_directory_pointer *pdp; |
e2b763ca | 913 | unsigned int pml4e; |
2ce5179f | 914 | |
1e6437b0 | 915 | GEM_BUG_ON(!use_4lvl(vm)); |
459108b8 | 916 | |
d209b9c3 | 917 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
bf75d59e CW |
918 | GEM_BUG_ON(pdp == vm->scratch_pdp); |
919 | ||
e2b763ca CW |
920 | if (!gen8_ppgtt_clear_pdp(vm, pdp, start, length)) |
921 | continue; | |
459108b8 | 922 | |
e2b763ca | 923 | gen8_ppgtt_set_pml4e(pml4, vm->scratch_pdp, pml4e); |
e2b763ca CW |
924 | |
925 | free_pdp(vm, pdp); | |
459108b8 BW |
926 | } |
927 | } | |
928 | ||
5684514b | 929 | static inline struct sgt_dma { |
894ccebe CW |
930 | struct scatterlist *sg; |
931 | dma_addr_t dma, max; | |
5684514b CW |
932 | } sgt_dma(struct i915_vma *vma) { |
933 | struct scatterlist *sg = vma->pages->sgl; | |
934 | dma_addr_t addr = sg_dma_address(sg); | |
935 | return (struct sgt_dma) { sg, addr, addr + sg->length }; | |
936 | } | |
894ccebe | 937 | |
9e89f9ee CW |
938 | struct gen8_insert_pte { |
939 | u16 pml4e; | |
940 | u16 pdpe; | |
941 | u16 pde; | |
942 | u16 pte; | |
943 | }; | |
944 | ||
945 | static __always_inline struct gen8_insert_pte gen8_insert_pte(u64 start) | |
946 | { | |
947 | return (struct gen8_insert_pte) { | |
948 | gen8_pml4e_index(start), | |
949 | gen8_pdpe_index(start), | |
950 | gen8_pde_index(start), | |
951 | gen8_pte_index(start), | |
952 | }; | |
953 | } | |
954 | ||
894ccebe CW |
955 | static __always_inline bool |
956 | gen8_ppgtt_insert_pte_entries(struct i915_hw_ppgtt *ppgtt, | |
f9b5b782 | 957 | struct i915_page_directory_pointer *pdp, |
894ccebe | 958 | struct sgt_dma *iter, |
9e89f9ee | 959 | struct gen8_insert_pte *idx, |
f9b5b782 MT |
960 | enum i915_cache_level cache_level) |
961 | { | |
894ccebe CW |
962 | struct i915_page_directory *pd; |
963 | const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level); | |
964 | gen8_pte_t *vaddr; | |
965 | bool ret; | |
9df15b49 | 966 | |
82ad6443 | 967 | GEM_BUG_ON(idx->pdpe >= i915_pdpes_per_pdp(&ppgtt->vm)); |
9e89f9ee CW |
968 | pd = pdp->page_directory[idx->pdpe]; |
969 | vaddr = kmap_atomic_px(pd->page_table[idx->pde]); | |
894ccebe | 970 | do { |
9e89f9ee CW |
971 | vaddr[idx->pte] = pte_encode | iter->dma; |
972 | ||
894ccebe CW |
973 | iter->dma += PAGE_SIZE; |
974 | if (iter->dma >= iter->max) { | |
975 | iter->sg = __sg_next(iter->sg); | |
976 | if (!iter->sg) { | |
977 | ret = false; | |
978 | break; | |
979 | } | |
7ad47cf2 | 980 | |
894ccebe CW |
981 | iter->dma = sg_dma_address(iter->sg); |
982 | iter->max = iter->dma + iter->sg->length; | |
d7b3de91 | 983 | } |
9df15b49 | 984 | |
9e89f9ee CW |
985 | if (++idx->pte == GEN8_PTES) { |
986 | idx->pte = 0; | |
987 | ||
988 | if (++idx->pde == I915_PDES) { | |
989 | idx->pde = 0; | |
990 | ||
894ccebe | 991 | /* Limited by sg length for 3lvl */ |
9e89f9ee CW |
992 | if (++idx->pdpe == GEN8_PML4ES_PER_PML4) { |
993 | idx->pdpe = 0; | |
894ccebe | 994 | ret = true; |
de5ba8eb | 995 | break; |
894ccebe CW |
996 | } |
997 | ||
82ad6443 | 998 | GEM_BUG_ON(idx->pdpe >= i915_pdpes_per_pdp(&ppgtt->vm)); |
9e89f9ee | 999 | pd = pdp->page_directory[idx->pdpe]; |
7ad47cf2 | 1000 | } |
894ccebe | 1001 | |
9231da70 | 1002 | kunmap_atomic(vaddr); |
9e89f9ee | 1003 | vaddr = kmap_atomic_px(pd->page_table[idx->pde]); |
9df15b49 | 1004 | } |
894ccebe | 1005 | } while (1); |
9231da70 | 1006 | kunmap_atomic(vaddr); |
d1c54acd | 1007 | |
894ccebe | 1008 | return ret; |
9df15b49 BW |
1009 | } |
1010 | ||
894ccebe | 1011 | static void gen8_ppgtt_insert_3lvl(struct i915_address_space *vm, |
4a234c5f | 1012 | struct i915_vma *vma, |
894ccebe CW |
1013 | enum i915_cache_level cache_level, |
1014 | u32 unused) | |
f9b5b782 | 1015 | { |
17369ba0 | 1016 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
5684514b | 1017 | struct sgt_dma iter = sgt_dma(vma); |
4a234c5f | 1018 | struct gen8_insert_pte idx = gen8_insert_pte(vma->node.start); |
f9b5b782 | 1019 | |
9e89f9ee CW |
1020 | gen8_ppgtt_insert_pte_entries(ppgtt, &ppgtt->pdp, &iter, &idx, |
1021 | cache_level); | |
d9ec12f8 MA |
1022 | |
1023 | vma->page_sizes.gtt = I915_GTT_PAGE_SIZE; | |
894ccebe | 1024 | } |
de5ba8eb | 1025 | |
0a03852e MA |
1026 | static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma, |
1027 | struct i915_page_directory_pointer **pdps, | |
1028 | struct sgt_dma *iter, | |
1029 | enum i915_cache_level cache_level) | |
1030 | { | |
1031 | const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level); | |
1032 | u64 start = vma->node.start; | |
1033 | dma_addr_t rem = iter->sg->length; | |
1034 | ||
1035 | do { | |
1036 | struct gen8_insert_pte idx = gen8_insert_pte(start); | |
1037 | struct i915_page_directory_pointer *pdp = pdps[idx.pml4e]; | |
1038 | struct i915_page_directory *pd = pdp->page_directory[idx.pdpe]; | |
1039 | unsigned int page_size; | |
17a00cf7 | 1040 | bool maybe_64K = false; |
0a03852e MA |
1041 | gen8_pte_t encode = pte_encode; |
1042 | gen8_pte_t *vaddr; | |
1043 | u16 index, max; | |
1044 | ||
1045 | if (vma->page_sizes.sg & I915_GTT_PAGE_SIZE_2M && | |
1046 | IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_2M) && | |
1047 | rem >= I915_GTT_PAGE_SIZE_2M && !idx.pte) { | |
1048 | index = idx.pde; | |
1049 | max = I915_PDES; | |
1050 | page_size = I915_GTT_PAGE_SIZE_2M; | |
1051 | ||
1052 | encode |= GEN8_PDE_PS_2M; | |
1053 | ||
1054 | vaddr = kmap_atomic_px(pd); | |
1055 | } else { | |
1056 | struct i915_page_table *pt = pd->page_table[idx.pde]; | |
1057 | ||
1058 | index = idx.pte; | |
1059 | max = GEN8_PTES; | |
1060 | page_size = I915_GTT_PAGE_SIZE; | |
1061 | ||
17a00cf7 MA |
1062 | if (!index && |
1063 | vma->page_sizes.sg & I915_GTT_PAGE_SIZE_64K && | |
1064 | IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_64K) && | |
1065 | (IS_ALIGNED(rem, I915_GTT_PAGE_SIZE_64K) || | |
1066 | rem >= (max - index) << PAGE_SHIFT)) | |
1067 | maybe_64K = true; | |
1068 | ||
0a03852e MA |
1069 | vaddr = kmap_atomic_px(pt); |
1070 | } | |
1071 | ||
1072 | do { | |
1073 | GEM_BUG_ON(iter->sg->length < page_size); | |
1074 | vaddr[index++] = encode | iter->dma; | |
1075 | ||
1076 | start += page_size; | |
1077 | iter->dma += page_size; | |
1078 | rem -= page_size; | |
1079 | if (iter->dma >= iter->max) { | |
1080 | iter->sg = __sg_next(iter->sg); | |
1081 | if (!iter->sg) | |
1082 | break; | |
1083 | ||
1084 | rem = iter->sg->length; | |
1085 | iter->dma = sg_dma_address(iter->sg); | |
1086 | iter->max = iter->dma + rem; | |
1087 | ||
17a00cf7 MA |
1088 | if (maybe_64K && index < max && |
1089 | !(IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_64K) && | |
1090 | (IS_ALIGNED(rem, I915_GTT_PAGE_SIZE_64K) || | |
1091 | rem >= (max - index) << PAGE_SHIFT))) | |
1092 | maybe_64K = false; | |
1093 | ||
0a03852e MA |
1094 | if (unlikely(!IS_ALIGNED(iter->dma, page_size))) |
1095 | break; | |
1096 | } | |
1097 | } while (rem >= page_size && index < max); | |
1098 | ||
1099 | kunmap_atomic(vaddr); | |
17a00cf7 MA |
1100 | |
1101 | /* | |
1102 | * Is it safe to mark the 2M block as 64K? -- Either we have | |
1103 | * filled whole page-table with 64K entries, or filled part of | |
1104 | * it and have reached the end of the sg table and we have | |
1105 | * enough padding. | |
1106 | */ | |
1107 | if (maybe_64K && | |
1108 | (index == max || | |
1109 | (i915_vm_has_scratch_64K(vma->vm) && | |
1110 | !iter->sg && IS_ALIGNED(vma->node.start + | |
1111 | vma->node.size, | |
1112 | I915_GTT_PAGE_SIZE_2M)))) { | |
1113 | vaddr = kmap_atomic_px(pd); | |
1114 | vaddr[idx.pde] |= GEN8_PDE_IPS_64K; | |
1115 | kunmap_atomic(vaddr); | |
d9ec12f8 | 1116 | page_size = I915_GTT_PAGE_SIZE_64K; |
f79401b4 MA |
1117 | |
1118 | /* | |
1119 | * We write all 4K page entries, even when using 64K | |
1120 | * pages. In order to verify that the HW isn't cheating | |
1121 | * by using the 4K PTE instead of the 64K PTE, we want | |
1122 | * to remove all the surplus entries. If the HW skipped | |
1123 | * the 64K PTE, it will read/write into the scratch page | |
1124 | * instead - which we detect as missing results during | |
1125 | * selftests. | |
1126 | */ | |
1127 | if (I915_SELFTEST_ONLY(vma->vm->scrub_64K)) { | |
1128 | u16 i; | |
1129 | ||
1130 | encode = pte_encode | vma->vm->scratch_page.daddr; | |
1131 | vaddr = kmap_atomic_px(pd->page_table[idx.pde]); | |
1132 | ||
1133 | for (i = 1; i < index; i += 16) | |
1134 | memset64(vaddr + i, encode, 15); | |
1135 | ||
1136 | kunmap_atomic(vaddr); | |
1137 | } | |
17a00cf7 | 1138 | } |
d9ec12f8 MA |
1139 | |
1140 | vma->page_sizes.gtt |= page_size; | |
0a03852e MA |
1141 | } while (iter->sg); |
1142 | } | |
1143 | ||
894ccebe | 1144 | static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm, |
4a234c5f | 1145 | struct i915_vma *vma, |
894ccebe CW |
1146 | enum i915_cache_level cache_level, |
1147 | u32 unused) | |
1148 | { | |
1149 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); | |
5684514b | 1150 | struct sgt_dma iter = sgt_dma(vma); |
894ccebe | 1151 | struct i915_page_directory_pointer **pdps = ppgtt->pml4.pdps; |
de5ba8eb | 1152 | |
0a03852e MA |
1153 | if (vma->page_sizes.sg > I915_GTT_PAGE_SIZE) { |
1154 | gen8_ppgtt_insert_huge_entries(vma, pdps, &iter, cache_level); | |
1155 | } else { | |
1156 | struct gen8_insert_pte idx = gen8_insert_pte(vma->node.start); | |
1157 | ||
1158 | while (gen8_ppgtt_insert_pte_entries(ppgtt, pdps[idx.pml4e++], | |
1159 | &iter, &idx, cache_level)) | |
1160 | GEM_BUG_ON(idx.pml4e >= GEN8_PML4ES_PER_PML4); | |
d9ec12f8 MA |
1161 | |
1162 | vma->page_sizes.gtt = I915_GTT_PAGE_SIZE; | |
0a03852e | 1163 | } |
f9b5b782 MT |
1164 | } |
1165 | ||
8448661d | 1166 | static void gen8_free_page_tables(struct i915_address_space *vm, |
f37c0505 | 1167 | struct i915_page_directory *pd) |
7ad47cf2 BW |
1168 | { |
1169 | int i; | |
1170 | ||
567047be | 1171 | if (!px_page(pd)) |
7ad47cf2 BW |
1172 | return; |
1173 | ||
fe52e37f CW |
1174 | for (i = 0; i < I915_PDES; i++) { |
1175 | if (pd->page_table[i] != vm->scratch_pt) | |
1176 | free_pt(vm, pd->page_table[i]); | |
06fda602 | 1177 | } |
d7b3de91 BW |
1178 | } |
1179 | ||
8776f02b MK |
1180 | static int gen8_init_scratch(struct i915_address_space *vm) |
1181 | { | |
64c050db | 1182 | int ret; |
8776f02b | 1183 | |
1abb70f5 | 1184 | ret = setup_scratch_page(vm, __GFP_HIGHMEM); |
8bcdd0f7 CW |
1185 | if (ret) |
1186 | return ret; | |
8776f02b | 1187 | |
8448661d | 1188 | vm->scratch_pt = alloc_pt(vm); |
8776f02b | 1189 | if (IS_ERR(vm->scratch_pt)) { |
64c050db MA |
1190 | ret = PTR_ERR(vm->scratch_pt); |
1191 | goto free_scratch_page; | |
8776f02b MK |
1192 | } |
1193 | ||
8448661d | 1194 | vm->scratch_pd = alloc_pd(vm); |
8776f02b | 1195 | if (IS_ERR(vm->scratch_pd)) { |
64c050db MA |
1196 | ret = PTR_ERR(vm->scratch_pd); |
1197 | goto free_pt; | |
8776f02b MK |
1198 | } |
1199 | ||
1e6437b0 | 1200 | if (use_4lvl(vm)) { |
8448661d | 1201 | vm->scratch_pdp = alloc_pdp(vm); |
69ab76fd | 1202 | if (IS_ERR(vm->scratch_pdp)) { |
64c050db MA |
1203 | ret = PTR_ERR(vm->scratch_pdp); |
1204 | goto free_pd; | |
69ab76fd MT |
1205 | } |
1206 | } | |
1207 | ||
8776f02b MK |
1208 | gen8_initialize_pt(vm, vm->scratch_pt); |
1209 | gen8_initialize_pd(vm, vm->scratch_pd); | |
1e6437b0 | 1210 | if (use_4lvl(vm)) |
69ab76fd | 1211 | gen8_initialize_pdp(vm, vm->scratch_pdp); |
8776f02b MK |
1212 | |
1213 | return 0; | |
64c050db MA |
1214 | |
1215 | free_pd: | |
8448661d | 1216 | free_pd(vm, vm->scratch_pd); |
64c050db | 1217 | free_pt: |
8448661d | 1218 | free_pt(vm, vm->scratch_pt); |
64c050db | 1219 | free_scratch_page: |
8448661d | 1220 | cleanup_scratch_page(vm); |
64c050db MA |
1221 | |
1222 | return ret; | |
8776f02b MK |
1223 | } |
1224 | ||
650da34c ZL |
1225 | static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create) |
1226 | { | |
82ad6443 | 1227 | struct i915_address_space *vm = &ppgtt->vm; |
1e6437b0 | 1228 | struct drm_i915_private *dev_priv = vm->i915; |
650da34c | 1229 | enum vgt_g2v_type msg; |
650da34c ZL |
1230 | int i; |
1231 | ||
1e6437b0 MK |
1232 | if (use_4lvl(vm)) { |
1233 | const u64 daddr = px_dma(&ppgtt->pml4); | |
650da34c | 1234 | |
ab75bb5d VS |
1235 | I915_WRITE(vgtif_reg(pdp[0].lo), lower_32_bits(daddr)); |
1236 | I915_WRITE(vgtif_reg(pdp[0].hi), upper_32_bits(daddr)); | |
650da34c ZL |
1237 | |
1238 | msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE : | |
1239 | VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY); | |
1240 | } else { | |
e7167769 | 1241 | for (i = 0; i < GEN8_3LVL_PDPES; i++) { |
1e6437b0 | 1242 | const u64 daddr = i915_page_dir_dma_addr(ppgtt, i); |
650da34c | 1243 | |
ab75bb5d VS |
1244 | I915_WRITE(vgtif_reg(pdp[i].lo), lower_32_bits(daddr)); |
1245 | I915_WRITE(vgtif_reg(pdp[i].hi), upper_32_bits(daddr)); | |
650da34c ZL |
1246 | } |
1247 | ||
1248 | msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE : | |
1249 | VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY); | |
1250 | } | |
1251 | ||
1252 | I915_WRITE(vgtif_reg(g2v_notify), msg); | |
1253 | ||
1254 | return 0; | |
1255 | } | |
1256 | ||
8776f02b MK |
1257 | static void gen8_free_scratch(struct i915_address_space *vm) |
1258 | { | |
1e6437b0 | 1259 | if (use_4lvl(vm)) |
8448661d CW |
1260 | free_pdp(vm, vm->scratch_pdp); |
1261 | free_pd(vm, vm->scratch_pd); | |
1262 | free_pt(vm, vm->scratch_pt); | |
1263 | cleanup_scratch_page(vm); | |
8776f02b MK |
1264 | } |
1265 | ||
8448661d | 1266 | static void gen8_ppgtt_cleanup_3lvl(struct i915_address_space *vm, |
762d9936 | 1267 | struct i915_page_directory_pointer *pdp) |
b45a6715 | 1268 | { |
3e490042 | 1269 | const unsigned int pdpes = i915_pdpes_per_pdp(vm); |
b45a6715 BW |
1270 | int i; |
1271 | ||
3e490042 | 1272 | for (i = 0; i < pdpes; i++) { |
fe52e37f | 1273 | if (pdp->page_directory[i] == vm->scratch_pd) |
06fda602 BW |
1274 | continue; |
1275 | ||
8448661d CW |
1276 | gen8_free_page_tables(vm, pdp->page_directory[i]); |
1277 | free_pd(vm, pdp->page_directory[i]); | |
7ad47cf2 | 1278 | } |
69876bed | 1279 | |
8448661d | 1280 | free_pdp(vm, pdp); |
762d9936 MT |
1281 | } |
1282 | ||
1283 | static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt *ppgtt) | |
1284 | { | |
1285 | int i; | |
1286 | ||
c5d092a4 | 1287 | for (i = 0; i < GEN8_PML4ES_PER_PML4; i++) { |
82ad6443 | 1288 | if (ppgtt->pml4.pdps[i] == ppgtt->vm.scratch_pdp) |
762d9936 MT |
1289 | continue; |
1290 | ||
82ad6443 | 1291 | gen8_ppgtt_cleanup_3lvl(&ppgtt->vm, ppgtt->pml4.pdps[i]); |
762d9936 MT |
1292 | } |
1293 | ||
82ad6443 | 1294 | cleanup_px(&ppgtt->vm, &ppgtt->pml4); |
762d9936 MT |
1295 | } |
1296 | ||
1297 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) | |
1298 | { | |
49d73912 | 1299 | struct drm_i915_private *dev_priv = vm->i915; |
e5716f55 | 1300 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
762d9936 | 1301 | |
275a991c | 1302 | if (intel_vgpu_active(dev_priv)) |
650da34c ZL |
1303 | gen8_ppgtt_notify_vgt(ppgtt, false); |
1304 | ||
1e6437b0 | 1305 | if (use_4lvl(vm)) |
762d9936 | 1306 | gen8_ppgtt_cleanup_4lvl(ppgtt); |
1e6437b0 | 1307 | else |
82ad6443 | 1308 | gen8_ppgtt_cleanup_3lvl(&ppgtt->vm, &ppgtt->pdp); |
d4ec9da0 | 1309 | |
8776f02b | 1310 | gen8_free_scratch(vm); |
b45a6715 BW |
1311 | } |
1312 | ||
fe52e37f CW |
1313 | static int gen8_ppgtt_alloc_pd(struct i915_address_space *vm, |
1314 | struct i915_page_directory *pd, | |
1315 | u64 start, u64 length) | |
bf2b4ed2 | 1316 | { |
d7b2633d | 1317 | struct i915_page_table *pt; |
dd19674b | 1318 | u64 from = start; |
fe52e37f | 1319 | unsigned int pde; |
bf2b4ed2 | 1320 | |
e8ebd8e2 | 1321 | gen8_for_each_pde(pt, pd, start, length, pde) { |
14826673 CW |
1322 | int count = gen8_pte_count(start, length); |
1323 | ||
fe52e37f | 1324 | if (pt == vm->scratch_pt) { |
b715a2f0 CW |
1325 | pd->used_pdes++; |
1326 | ||
dd19674b | 1327 | pt = alloc_pt(vm); |
b715a2f0 CW |
1328 | if (IS_ERR(pt)) { |
1329 | pd->used_pdes--; | |
dd19674b | 1330 | goto unwind; |
b715a2f0 | 1331 | } |
5441f0cb | 1332 | |
22a8a4fc | 1333 | if (count < GEN8_PTES || intel_vgpu_active(vm->i915)) |
14826673 | 1334 | gen8_initialize_pt(vm, pt); |
fe52e37f CW |
1335 | |
1336 | gen8_ppgtt_set_pde(vm, pd, pt, pde); | |
bf75d59e | 1337 | GEM_BUG_ON(pd->used_pdes > I915_PDES); |
dd19674b | 1338 | } |
fe52e37f | 1339 | |
14826673 | 1340 | pt->used_ptes += count; |
7ad47cf2 | 1341 | } |
bf2b4ed2 | 1342 | return 0; |
7ad47cf2 | 1343 | |
dd19674b CW |
1344 | unwind: |
1345 | gen8_ppgtt_clear_pd(vm, pd, from, start - from); | |
d7b3de91 | 1346 | return -ENOMEM; |
bf2b4ed2 BW |
1347 | } |
1348 | ||
c5d092a4 CW |
1349 | static int gen8_ppgtt_alloc_pdp(struct i915_address_space *vm, |
1350 | struct i915_page_directory_pointer *pdp, | |
1351 | u64 start, u64 length) | |
bf2b4ed2 | 1352 | { |
5441f0cb | 1353 | struct i915_page_directory *pd; |
e2b763ca CW |
1354 | u64 from = start; |
1355 | unsigned int pdpe; | |
bf2b4ed2 BW |
1356 | int ret; |
1357 | ||
e8ebd8e2 | 1358 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
e2b763ca | 1359 | if (pd == vm->scratch_pd) { |
b715a2f0 CW |
1360 | pdp->used_pdpes++; |
1361 | ||
e2b763ca | 1362 | pd = alloc_pd(vm); |
b715a2f0 CW |
1363 | if (IS_ERR(pd)) { |
1364 | pdp->used_pdpes--; | |
e2b763ca | 1365 | goto unwind; |
b715a2f0 | 1366 | } |
5441f0cb | 1367 | |
e2b763ca | 1368 | gen8_initialize_pd(vm, pd); |
fe52e37f | 1369 | gen8_ppgtt_set_pdpe(vm, pdp, pd, pdpe); |
3e490042 | 1370 | GEM_BUG_ON(pdp->used_pdpes > i915_pdpes_per_pdp(vm)); |
75afcf72 CW |
1371 | |
1372 | mark_tlbs_dirty(i915_vm_to_ppgtt(vm)); | |
e2b763ca CW |
1373 | } |
1374 | ||
1375 | ret = gen8_ppgtt_alloc_pd(vm, pd, start, length); | |
bf75d59e CW |
1376 | if (unlikely(ret)) |
1377 | goto unwind_pd; | |
fe52e37f | 1378 | } |
33c8819f | 1379 | |
d7b3de91 | 1380 | return 0; |
bf2b4ed2 | 1381 | |
bf75d59e CW |
1382 | unwind_pd: |
1383 | if (!pd->used_pdes) { | |
1384 | gen8_ppgtt_set_pdpe(vm, pdp, vm->scratch_pd, pdpe); | |
1385 | GEM_BUG_ON(!pdp->used_pdpes); | |
1386 | pdp->used_pdpes--; | |
1387 | free_pd(vm, pd); | |
1388 | } | |
e2b763ca CW |
1389 | unwind: |
1390 | gen8_ppgtt_clear_pdp(vm, pdp, from, start - from); | |
1391 | return -ENOMEM; | |
bf2b4ed2 BW |
1392 | } |
1393 | ||
c5d092a4 CW |
1394 | static int gen8_ppgtt_alloc_3lvl(struct i915_address_space *vm, |
1395 | u64 start, u64 length) | |
762d9936 | 1396 | { |
c5d092a4 CW |
1397 | return gen8_ppgtt_alloc_pdp(vm, |
1398 | &i915_vm_to_ppgtt(vm)->pdp, start, length); | |
1399 | } | |
762d9936 | 1400 | |
c5d092a4 CW |
1401 | static int gen8_ppgtt_alloc_4lvl(struct i915_address_space *vm, |
1402 | u64 start, u64 length) | |
1403 | { | |
1404 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); | |
1405 | struct i915_pml4 *pml4 = &ppgtt->pml4; | |
1406 | struct i915_page_directory_pointer *pdp; | |
1407 | u64 from = start; | |
1408 | u32 pml4e; | |
1409 | int ret; | |
762d9936 | 1410 | |
e8ebd8e2 | 1411 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
c5d092a4 CW |
1412 | if (pml4->pdps[pml4e] == vm->scratch_pdp) { |
1413 | pdp = alloc_pdp(vm); | |
1414 | if (IS_ERR(pdp)) | |
1415 | goto unwind; | |
762d9936 | 1416 | |
c5d092a4 CW |
1417 | gen8_initialize_pdp(vm, pdp); |
1418 | gen8_ppgtt_set_pml4e(pml4, pdp, pml4e); | |
1419 | } | |
762d9936 | 1420 | |
c5d092a4 | 1421 | ret = gen8_ppgtt_alloc_pdp(vm, pdp, start, length); |
bf75d59e CW |
1422 | if (unlikely(ret)) |
1423 | goto unwind_pdp; | |
762d9936 MT |
1424 | } |
1425 | ||
762d9936 MT |
1426 | return 0; |
1427 | ||
bf75d59e CW |
1428 | unwind_pdp: |
1429 | if (!pdp->used_pdpes) { | |
1430 | gen8_ppgtt_set_pml4e(pml4, vm->scratch_pdp, pml4e); | |
1431 | free_pdp(vm, pdp); | |
1432 | } | |
c5d092a4 CW |
1433 | unwind: |
1434 | gen8_ppgtt_clear_4lvl(vm, from, start - from); | |
1435 | return -ENOMEM; | |
762d9936 MT |
1436 | } |
1437 | ||
8448661d CW |
1438 | static void gen8_dump_pdp(struct i915_hw_ppgtt *ppgtt, |
1439 | struct i915_page_directory_pointer *pdp, | |
75c7b0b8 | 1440 | u64 start, u64 length, |
ea91e401 MT |
1441 | gen8_pte_t scratch_pte, |
1442 | struct seq_file *m) | |
1443 | { | |
82ad6443 | 1444 | struct i915_address_space *vm = &ppgtt->vm; |
ea91e401 | 1445 | struct i915_page_directory *pd; |
75c7b0b8 | 1446 | u32 pdpe; |
ea91e401 | 1447 | |
e8ebd8e2 | 1448 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
ea91e401 | 1449 | struct i915_page_table *pt; |
75c7b0b8 CW |
1450 | u64 pd_len = length; |
1451 | u64 pd_start = start; | |
1452 | u32 pde; | |
ea91e401 | 1453 | |
82ad6443 | 1454 | if (pdp->page_directory[pdpe] == ppgtt->vm.scratch_pd) |
ea91e401 MT |
1455 | continue; |
1456 | ||
1457 | seq_printf(m, "\tPDPE #%d\n", pdpe); | |
e8ebd8e2 | 1458 | gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) { |
75c7b0b8 | 1459 | u32 pte; |
ea91e401 MT |
1460 | gen8_pte_t *pt_vaddr; |
1461 | ||
82ad6443 | 1462 | if (pd->page_table[pde] == ppgtt->vm.scratch_pt) |
ea91e401 MT |
1463 | continue; |
1464 | ||
9231da70 | 1465 | pt_vaddr = kmap_atomic_px(pt); |
ea91e401 | 1466 | for (pte = 0; pte < GEN8_PTES; pte += 4) { |
75c7b0b8 CW |
1467 | u64 va = (pdpe << GEN8_PDPE_SHIFT | |
1468 | pde << GEN8_PDE_SHIFT | | |
1469 | pte << GEN8_PTE_SHIFT); | |
ea91e401 MT |
1470 | int i; |
1471 | bool found = false; | |
1472 | ||
1473 | for (i = 0; i < 4; i++) | |
1474 | if (pt_vaddr[pte + i] != scratch_pte) | |
1475 | found = true; | |
1476 | if (!found) | |
1477 | continue; | |
1478 | ||
1479 | seq_printf(m, "\t\t0x%llx [%03d,%03d,%04d]: =", va, pdpe, pde, pte); | |
1480 | for (i = 0; i < 4; i++) { | |
1481 | if (pt_vaddr[pte + i] != scratch_pte) | |
1482 | seq_printf(m, " %llx", pt_vaddr[pte + i]); | |
1483 | else | |
1484 | seq_puts(m, " SCRATCH "); | |
1485 | } | |
1486 | seq_puts(m, "\n"); | |
1487 | } | |
ea91e401 MT |
1488 | kunmap_atomic(pt_vaddr); |
1489 | } | |
1490 | } | |
1491 | } | |
1492 | ||
1493 | static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) | |
1494 | { | |
82ad6443 | 1495 | struct i915_address_space *vm = &ppgtt->vm; |
894ccebe CW |
1496 | const gen8_pte_t scratch_pte = |
1497 | gen8_pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC); | |
82ad6443 | 1498 | u64 start = 0, length = ppgtt->vm.total; |
ea91e401 | 1499 | |
1e6437b0 | 1500 | if (use_4lvl(vm)) { |
75c7b0b8 | 1501 | u64 pml4e; |
ea91e401 MT |
1502 | struct i915_pml4 *pml4 = &ppgtt->pml4; |
1503 | struct i915_page_directory_pointer *pdp; | |
1504 | ||
e8ebd8e2 | 1505 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
82ad6443 | 1506 | if (pml4->pdps[pml4e] == ppgtt->vm.scratch_pdp) |
ea91e401 MT |
1507 | continue; |
1508 | ||
1509 | seq_printf(m, " PML4E #%llu\n", pml4e); | |
8448661d | 1510 | gen8_dump_pdp(ppgtt, pdp, start, length, scratch_pte, m); |
ea91e401 | 1511 | } |
1e6437b0 MK |
1512 | } else { |
1513 | gen8_dump_pdp(ppgtt, &ppgtt->pdp, start, length, scratch_pte, m); | |
ea91e401 MT |
1514 | } |
1515 | } | |
1516 | ||
e2b763ca | 1517 | static int gen8_preallocate_top_level_pdp(struct i915_hw_ppgtt *ppgtt) |
331f38e7 | 1518 | { |
82ad6443 | 1519 | struct i915_address_space *vm = &ppgtt->vm; |
e2b763ca CW |
1520 | struct i915_page_directory_pointer *pdp = &ppgtt->pdp; |
1521 | struct i915_page_directory *pd; | |
82ad6443 | 1522 | u64 start = 0, length = ppgtt->vm.total; |
e2b763ca CW |
1523 | u64 from = start; |
1524 | unsigned int pdpe; | |
331f38e7 | 1525 | |
e2b763ca CW |
1526 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
1527 | pd = alloc_pd(vm); | |
1528 | if (IS_ERR(pd)) | |
1529 | goto unwind; | |
331f38e7 | 1530 | |
e2b763ca CW |
1531 | gen8_initialize_pd(vm, pd); |
1532 | gen8_ppgtt_set_pdpe(vm, pdp, pd, pdpe); | |
1533 | pdp->used_pdpes++; | |
1534 | } | |
331f38e7 | 1535 | |
e2b763ca CW |
1536 | pdp->used_pdpes++; /* never remove */ |
1537 | return 0; | |
331f38e7 | 1538 | |
e2b763ca CW |
1539 | unwind: |
1540 | start -= from; | |
1541 | gen8_for_each_pdpe(pd, pdp, from, start, pdpe) { | |
1542 | gen8_ppgtt_set_pdpe(vm, pdp, vm->scratch_pd, pdpe); | |
1543 | free_pd(vm, pd); | |
1544 | } | |
1545 | pdp->used_pdpes = 0; | |
1546 | return -ENOMEM; | |
331f38e7 ZL |
1547 | } |
1548 | ||
eb0b44ad | 1549 | /* |
f3a964b9 BW |
1550 | * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers |
1551 | * with a net effect resembling a 2-level page table in normal x86 terms. Each | |
1552 | * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address | |
1553 | * space. | |
37aca44a | 1554 | * |
f3a964b9 | 1555 | */ |
17f297b4 | 1556 | static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915) |
37aca44a | 1557 | { |
17f297b4 CW |
1558 | struct i915_hw_ppgtt *ppgtt; |
1559 | int err; | |
1560 | ||
1561 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
1562 | if (!ppgtt) | |
1563 | return ERR_PTR(-ENOMEM); | |
1564 | ||
1565 | ppgtt->vm.i915 = i915; | |
1566 | ppgtt->vm.dma = &i915->drm.pdev->dev; | |
7cb6d7ac | 1567 | |
17f297b4 | 1568 | ppgtt->vm.total = USES_FULL_48BIT_PPGTT(i915) ? |
1e6437b0 MK |
1569 | 1ULL << 48 : |
1570 | 1ULL << 32; | |
1571 | ||
8448661d CW |
1572 | /* There are only few exceptions for gen >=6. chv and bxt. |
1573 | * And we are not sure about the latter so play safe for now. | |
1574 | */ | |
17f297b4 | 1575 | if (IS_CHERRYVIEW(i915) || IS_BROXTON(i915)) |
82ad6443 | 1576 | ppgtt->vm.pt_kmap_wc = true; |
8448661d | 1577 | |
17f297b4 CW |
1578 | err = gen8_init_scratch(&ppgtt->vm); |
1579 | if (err) | |
1580 | goto err_free; | |
66df1014 | 1581 | |
17f297b4 CW |
1582 | if (use_4lvl(&ppgtt->vm)) { |
1583 | err = setup_px(&ppgtt->vm, &ppgtt->pml4); | |
1584 | if (err) | |
1585 | goto err_scratch; | |
6ac18502 | 1586 | |
82ad6443 | 1587 | gen8_initialize_pml4(&ppgtt->vm, &ppgtt->pml4); |
69ab76fd | 1588 | |
82ad6443 CW |
1589 | ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc_4lvl; |
1590 | ppgtt->vm.insert_entries = gen8_ppgtt_insert_4lvl; | |
1591 | ppgtt->vm.clear_range = gen8_ppgtt_clear_4lvl; | |
762d9936 | 1592 | } else { |
17f297b4 CW |
1593 | err = __pdp_init(&ppgtt->vm, &ppgtt->pdp); |
1594 | if (err) | |
1595 | goto err_scratch; | |
81ba8aef | 1596 | |
17f297b4 CW |
1597 | if (intel_vgpu_active(i915)) { |
1598 | err = gen8_preallocate_top_level_pdp(ppgtt); | |
1599 | if (err) { | |
e2b763ca | 1600 | __pdp_fini(&ppgtt->pdp); |
17f297b4 | 1601 | goto err_scratch; |
e2b763ca | 1602 | } |
331f38e7 | 1603 | } |
894ccebe | 1604 | |
82ad6443 CW |
1605 | ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc_3lvl; |
1606 | ppgtt->vm.insert_entries = gen8_ppgtt_insert_3lvl; | |
1607 | ppgtt->vm.clear_range = gen8_ppgtt_clear_3lvl; | |
81ba8aef | 1608 | } |
6ac18502 | 1609 | |
17f297b4 | 1610 | if (intel_vgpu_active(i915)) |
650da34c ZL |
1611 | gen8_ppgtt_notify_vgt(ppgtt, true); |
1612 | ||
82ad6443 | 1613 | ppgtt->vm.cleanup = gen8_ppgtt_cleanup; |
054b9acd MK |
1614 | ppgtt->debug_dump = gen8_dump_ppgtt; |
1615 | ||
549fe88b | 1616 | ppgtt->vm.vma_ops.bind_vma = ppgtt_bind_vma; |
93f2cde2 CW |
1617 | ppgtt->vm.vma_ops.unbind_vma = ppgtt_unbind_vma; |
1618 | ppgtt->vm.vma_ops.set_pages = ppgtt_set_pages; | |
1619 | ppgtt->vm.vma_ops.clear_pages = clear_pages; | |
1620 | ||
17f297b4 | 1621 | return ppgtt; |
6ac18502 | 1622 | |
17f297b4 | 1623 | err_scratch: |
82ad6443 | 1624 | gen8_free_scratch(&ppgtt->vm); |
17f297b4 CW |
1625 | err_free: |
1626 | kfree(ppgtt); | |
1627 | return ERR_PTR(err); | |
d7b2633d MT |
1628 | } |
1629 | ||
35ac40d8 | 1630 | static void gen6_dump_ppgtt(struct i915_hw_ppgtt *base, struct seq_file *m) |
87d60b63 | 1631 | { |
35ac40d8 | 1632 | struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(base); |
986dbac4 | 1633 | const gen6_pte_t scratch_pte = ppgtt->scratch_pte; |
e9e7dc41 CW |
1634 | struct i915_page_table *pt; |
1635 | u32 pte, pde; | |
1636 | ||
1637 | gen6_for_all_pdes(pt, &base->pd, pde) { | |
1638 | gen6_pte_t *vaddr; | |
1639 | ||
1640 | if (pt == base->vm.scratch_pt) | |
1641 | continue; | |
1642 | ||
1643 | if (i915_vma_is_bound(ppgtt->vma, I915_VMA_GLOBAL_BIND)) { | |
1644 | u32 expected = | |
1645 | GEN6_PDE_ADDR_ENCODE(px_dma(pt)) | | |
1646 | GEN6_PDE_VALID; | |
1647 | u32 pd_entry = readl(ppgtt->pd_addr + pde); | |
1648 | ||
1649 | if (pd_entry != expected) | |
1650 | seq_printf(m, | |
1651 | "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", | |
1652 | pde, | |
1653 | pd_entry, | |
1654 | expected); | |
1655 | ||
1656 | seq_printf(m, "\tPDE: %x\n", pd_entry); | |
1657 | } | |
1658 | ||
1659 | vaddr = kmap_atomic_px(base->pd.page_table[pde]); | |
1660 | for (pte = 0; pte < GEN6_PTES; pte += 4) { | |
87d60b63 | 1661 | int i; |
e9e7dc41 | 1662 | |
87d60b63 | 1663 | for (i = 0; i < 4; i++) |
e9e7dc41 CW |
1664 | if (vaddr[pte + i] != scratch_pte) |
1665 | break; | |
1666 | if (i == 4) | |
87d60b63 BW |
1667 | continue; |
1668 | ||
e9e7dc41 CW |
1669 | seq_printf(m, "\t\t(%03d, %04d) %08lx: ", |
1670 | pde, pte, | |
1671 | (pde * GEN6_PTES + pte) * PAGE_SIZE); | |
87d60b63 | 1672 | for (i = 0; i < 4; i++) { |
e9e7dc41 CW |
1673 | if (vaddr[pte + i] != scratch_pte) |
1674 | seq_printf(m, " %08x", vaddr[pte + i]); | |
87d60b63 | 1675 | else |
e9e7dc41 | 1676 | seq_puts(m, " SCRATCH"); |
87d60b63 BW |
1677 | } |
1678 | seq_puts(m, "\n"); | |
1679 | } | |
e9e7dc41 | 1680 | kunmap_atomic(vaddr); |
87d60b63 BW |
1681 | } |
1682 | } | |
1683 | ||
678d96fb | 1684 | /* Write pde (index) from the page directory @pd to the page table @pt */ |
35ac40d8 | 1685 | static inline void gen6_write_pde(const struct gen6_hw_ppgtt *ppgtt, |
16a011c8 CW |
1686 | const unsigned int pde, |
1687 | const struct i915_page_table *pt) | |
6197349b | 1688 | { |
678d96fb | 1689 | /* Caller needs to make sure the write completes if necessary */ |
68a85703 CW |
1690 | iowrite32(GEN6_PDE_ADDR_ENCODE(px_dma(pt)) | GEN6_PDE_VALID, |
1691 | ppgtt->pd_addr + pde); | |
678d96fb | 1692 | } |
6197349b | 1693 | |
c6be607a | 1694 | static void gen8_ppgtt_enable(struct drm_i915_private *dev_priv) |
eeb9488e | 1695 | { |
e2f80391 | 1696 | struct intel_engine_cs *engine; |
3b3f1650 | 1697 | enum intel_engine_id id; |
3e302542 | 1698 | |
3b3f1650 | 1699 | for_each_engine(engine, dev_priv, id) { |
c6be607a TU |
1700 | u32 four_level = USES_FULL_48BIT_PPGTT(dev_priv) ? |
1701 | GEN8_GFX_PPGTT_48B : 0; | |
e2f80391 | 1702 | I915_WRITE(RING_MODE_GEN7(engine), |
2dba3239 | 1703 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level)); |
eeb9488e | 1704 | } |
eeb9488e | 1705 | } |
6197349b | 1706 | |
c6be607a | 1707 | static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv) |
3e302542 | 1708 | { |
e2f80391 | 1709 | struct intel_engine_cs *engine; |
75c7b0b8 | 1710 | u32 ecochk, ecobits; |
3b3f1650 | 1711 | enum intel_engine_id id; |
6197349b | 1712 | |
b4a74e3a BW |
1713 | ecobits = I915_READ(GAC_ECO_BITS); |
1714 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
a65c2fcd | 1715 | |
b4a74e3a | 1716 | ecochk = I915_READ(GAM_ECOCHK); |
772c2a51 | 1717 | if (IS_HASWELL(dev_priv)) { |
b4a74e3a BW |
1718 | ecochk |= ECOCHK_PPGTT_WB_HSW; |
1719 | } else { | |
1720 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
1721 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
1722 | } | |
1723 | I915_WRITE(GAM_ECOCHK, ecochk); | |
a65c2fcd | 1724 | |
3b3f1650 | 1725 | for_each_engine(engine, dev_priv, id) { |
6197349b | 1726 | /* GFX_MODE is per-ring on gen7+ */ |
e2f80391 | 1727 | I915_WRITE(RING_MODE_GEN7(engine), |
b4a74e3a | 1728 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
6197349b | 1729 | } |
b4a74e3a | 1730 | } |
6197349b | 1731 | |
c6be607a | 1732 | static void gen6_ppgtt_enable(struct drm_i915_private *dev_priv) |
b4a74e3a | 1733 | { |
75c7b0b8 | 1734 | u32 ecochk, gab_ctl, ecobits; |
a65c2fcd | 1735 | |
b4a74e3a BW |
1736 | ecobits = I915_READ(GAC_ECO_BITS); |
1737 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | | |
1738 | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 1739 | |
b4a74e3a BW |
1740 | gab_ctl = I915_READ(GAB_CTL); |
1741 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
1742 | ||
1743 | ecochk = I915_READ(GAM_ECOCHK); | |
1744 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); | |
1745 | ||
1746 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b BW |
1747 | } |
1748 | ||
1d2a314c | 1749 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 1750 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
dd19674b | 1751 | u64 start, u64 length) |
1d2a314c | 1752 | { |
4a192c7e | 1753 | struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(i915_vm_to_ppgtt(vm)); |
dd19674b CW |
1754 | unsigned int first_entry = start >> PAGE_SHIFT; |
1755 | unsigned int pde = first_entry / GEN6_PTES; | |
1756 | unsigned int pte = first_entry % GEN6_PTES; | |
1757 | unsigned int num_entries = length >> PAGE_SHIFT; | |
986dbac4 | 1758 | const gen6_pte_t scratch_pte = ppgtt->scratch_pte; |
1d2a314c | 1759 | |
7bddb01f | 1760 | while (num_entries) { |
4a192c7e CW |
1761 | struct i915_page_table *pt = ppgtt->base.pd.page_table[pde++]; |
1762 | const unsigned int end = min(pte + num_entries, GEN6_PTES); | |
1763 | const unsigned int count = end - pte; | |
dd19674b | 1764 | gen6_pte_t *vaddr; |
7bddb01f | 1765 | |
4a192c7e CW |
1766 | GEM_BUG_ON(pt == vm->scratch_pt); |
1767 | ||
1768 | num_entries -= count; | |
1769 | ||
1770 | GEM_BUG_ON(count > pt->used_ptes); | |
1771 | pt->used_ptes -= count; | |
1772 | if (!pt->used_ptes) | |
1773 | ppgtt->scan_for_unused_pt = true; | |
1d2a314c | 1774 | |
549fe88b CW |
1775 | /* |
1776 | * Note that the hw doesn't support removing PDE on the fly | |
dd19674b CW |
1777 | * (they are cached inside the context with no means to |
1778 | * invalidate the cache), so we can only reset the PTE | |
1779 | * entries back to scratch. | |
1780 | */ | |
1d2a314c | 1781 | |
dd19674b CW |
1782 | vaddr = kmap_atomic_px(pt); |
1783 | do { | |
1784 | vaddr[pte++] = scratch_pte; | |
1785 | } while (pte < end); | |
1786 | kunmap_atomic(vaddr); | |
1d2a314c | 1787 | |
dd19674b | 1788 | pte = 0; |
7bddb01f | 1789 | } |
1d2a314c DV |
1790 | } |
1791 | ||
853ba5d2 | 1792 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
4a234c5f | 1793 | struct i915_vma *vma, |
75c7b0b8 CW |
1794 | enum i915_cache_level cache_level, |
1795 | u32 flags) | |
def886c3 | 1796 | { |
e5716f55 | 1797 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
4a234c5f | 1798 | unsigned first_entry = vma->node.start >> PAGE_SHIFT; |
07749ef3 MT |
1799 | unsigned act_pt = first_entry / GEN6_PTES; |
1800 | unsigned act_pte = first_entry % GEN6_PTES; | |
b31144c0 | 1801 | const u32 pte_encode = vm->pte_encode(0, cache_level, flags); |
5684514b | 1802 | struct sgt_dma iter = sgt_dma(vma); |
b31144c0 CW |
1803 | gen6_pte_t *vaddr; |
1804 | ||
4a192c7e CW |
1805 | GEM_BUG_ON(ppgtt->pd.page_table[act_pt] == vm->scratch_pt); |
1806 | ||
9231da70 | 1807 | vaddr = kmap_atomic_px(ppgtt->pd.page_table[act_pt]); |
b31144c0 CW |
1808 | do { |
1809 | vaddr[act_pte] = pte_encode | GEN6_PTE_ADDR_ENCODE(iter.dma); | |
6e995e23 | 1810 | |
b31144c0 CW |
1811 | iter.dma += PAGE_SIZE; |
1812 | if (iter.dma == iter.max) { | |
1813 | iter.sg = __sg_next(iter.sg); | |
1814 | if (!iter.sg) | |
1815 | break; | |
6e995e23 | 1816 | |
b31144c0 CW |
1817 | iter.dma = sg_dma_address(iter.sg); |
1818 | iter.max = iter.dma + iter.sg->length; | |
1819 | } | |
24f3a8cf | 1820 | |
07749ef3 | 1821 | if (++act_pte == GEN6_PTES) { |
9231da70 CW |
1822 | kunmap_atomic(vaddr); |
1823 | vaddr = kmap_atomic_px(ppgtt->pd.page_table[++act_pt]); | |
6e995e23 | 1824 | act_pte = 0; |
def886c3 | 1825 | } |
b31144c0 | 1826 | } while (1); |
9231da70 | 1827 | kunmap_atomic(vaddr); |
d9ec12f8 MA |
1828 | |
1829 | vma->page_sizes.gtt = I915_GTT_PAGE_SIZE; | |
def886c3 DV |
1830 | } |
1831 | ||
678d96fb | 1832 | static int gen6_alloc_va_range(struct i915_address_space *vm, |
dd19674b | 1833 | u64 start, u64 length) |
678d96fb | 1834 | { |
35ac40d8 | 1835 | struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(i915_vm_to_ppgtt(vm)); |
ec565b3c | 1836 | struct i915_page_table *pt; |
dd19674b CW |
1837 | u64 from = start; |
1838 | unsigned int pde; | |
1839 | bool flush = false; | |
4933d519 | 1840 | |
35ac40d8 | 1841 | gen6_for_each_pde(pt, &ppgtt->base.pd, start, length, pde) { |
4a192c7e CW |
1842 | const unsigned int count = gen6_pte_count(start, length); |
1843 | ||
dd19674b CW |
1844 | if (pt == vm->scratch_pt) { |
1845 | pt = alloc_pt(vm); | |
1846 | if (IS_ERR(pt)) | |
1847 | goto unwind_out; | |
4933d519 | 1848 | |
986dbac4 | 1849 | gen6_initialize_pt(ppgtt, pt); |
35ac40d8 | 1850 | ppgtt->base.pd.page_table[pde] = pt; |
e9e7dc41 CW |
1851 | |
1852 | if (i915_vma_is_bound(ppgtt->vma, | |
1853 | I915_VMA_GLOBAL_BIND)) { | |
1854 | gen6_write_pde(ppgtt, pde, pt); | |
1855 | flush = true; | |
1856 | } | |
4a192c7e CW |
1857 | |
1858 | GEM_BUG_ON(pt->used_ptes); | |
4933d519 | 1859 | } |
4a192c7e CW |
1860 | |
1861 | pt->used_ptes += count; | |
4933d519 MT |
1862 | } |
1863 | ||
dd19674b | 1864 | if (flush) { |
35ac40d8 CW |
1865 | mark_tlbs_dirty(&ppgtt->base); |
1866 | gen6_ggtt_invalidate(ppgtt->base.vm.i915); | |
678d96fb BW |
1867 | } |
1868 | ||
1869 | return 0; | |
4933d519 MT |
1870 | |
1871 | unwind_out: | |
b4e2727d | 1872 | gen6_ppgtt_clear_range(vm, from, start - from); |
dd19674b | 1873 | return -ENOMEM; |
678d96fb BW |
1874 | } |
1875 | ||
e9e7dc41 | 1876 | static int gen6_ppgtt_init_scratch(struct gen6_hw_ppgtt *ppgtt) |
8776f02b | 1877 | { |
e9e7dc41 CW |
1878 | struct i915_address_space * const vm = &ppgtt->base.vm; |
1879 | struct i915_page_table *unused; | |
1880 | u32 pde; | |
8bcdd0f7 | 1881 | int ret; |
8776f02b | 1882 | |
1abb70f5 | 1883 | ret = setup_scratch_page(vm, __GFP_HIGHMEM); |
8bcdd0f7 CW |
1884 | if (ret) |
1885 | return ret; | |
8776f02b | 1886 | |
986dbac4 CW |
1887 | ppgtt->scratch_pte = |
1888 | vm->pte_encode(vm->scratch_page.daddr, | |
1889 | I915_CACHE_NONE, PTE_READ_ONLY); | |
1890 | ||
8448661d | 1891 | vm->scratch_pt = alloc_pt(vm); |
8776f02b | 1892 | if (IS_ERR(vm->scratch_pt)) { |
8448661d | 1893 | cleanup_scratch_page(vm); |
8776f02b MK |
1894 | return PTR_ERR(vm->scratch_pt); |
1895 | } | |
1896 | ||
986dbac4 | 1897 | gen6_initialize_pt(ppgtt, vm->scratch_pt); |
e9e7dc41 CW |
1898 | gen6_for_all_pdes(unused, &ppgtt->base.pd, pde) |
1899 | ppgtt->base.pd.page_table[pde] = vm->scratch_pt; | |
8776f02b MK |
1900 | |
1901 | return 0; | |
1902 | } | |
1903 | ||
a9ded785 | 1904 | static void gen6_ppgtt_free_scratch(struct i915_address_space *vm) |
8776f02b | 1905 | { |
8448661d CW |
1906 | free_pt(vm, vm->scratch_pt); |
1907 | cleanup_scratch_page(vm); | |
8776f02b MK |
1908 | } |
1909 | ||
a9ded785 | 1910 | static void gen6_ppgtt_free_pd(struct gen6_hw_ppgtt *ppgtt) |
a00d825d | 1911 | { |
09942c65 | 1912 | struct i915_page_table *pt; |
75c7b0b8 | 1913 | u32 pde; |
4933d519 | 1914 | |
35ac40d8 | 1915 | gen6_for_all_pdes(pt, &ppgtt->base.pd, pde) |
a9ded785 CW |
1916 | if (pt != ppgtt->base.vm.scratch_pt) |
1917 | free_pt(&ppgtt->base.vm, pt); | |
1918 | } | |
1919 | ||
1920 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) | |
1921 | { | |
1922 | struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(i915_vm_to_ppgtt(vm)); | |
06fda602 | 1923 | |
e9e7dc41 | 1924 | i915_vma_destroy(ppgtt->vma); |
a9ded785 CW |
1925 | |
1926 | gen6_ppgtt_free_pd(ppgtt); | |
1927 | gen6_ppgtt_free_scratch(vm); | |
3440d265 DV |
1928 | } |
1929 | ||
e9e7dc41 | 1930 | static int pd_vma_set_pages(struct i915_vma *vma) |
3440d265 | 1931 | { |
e9e7dc41 CW |
1932 | vma->pages = ERR_PTR(-ENODEV); |
1933 | return 0; | |
1934 | } | |
1d2a314c | 1935 | |
e9e7dc41 CW |
1936 | static void pd_vma_clear_pages(struct i915_vma *vma) |
1937 | { | |
1938 | GEM_BUG_ON(!vma->pages); | |
4933d519 | 1939 | |
e9e7dc41 CW |
1940 | vma->pages = NULL; |
1941 | } | |
1942 | ||
1943 | static int pd_vma_bind(struct i915_vma *vma, | |
1944 | enum i915_cache_level cache_level, | |
1945 | u32 unused) | |
1946 | { | |
1947 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vma->vm); | |
1948 | struct gen6_hw_ppgtt *ppgtt = vma->private; | |
1949 | u32 ggtt_offset = i915_ggtt_offset(vma) / PAGE_SIZE; | |
1950 | struct i915_page_table *pt; | |
1951 | unsigned int pde; | |
678d96fb | 1952 | |
e9e7dc41 CW |
1953 | ppgtt->base.pd.base.ggtt_offset = ggtt_offset * sizeof(gen6_pte_t); |
1954 | ppgtt->pd_addr = (gen6_pte_t __iomem *)ggtt->gsm + ggtt_offset; | |
1d2a314c | 1955 | |
e9e7dc41 CW |
1956 | gen6_for_all_pdes(pt, &ppgtt->base.pd, pde) |
1957 | gen6_write_pde(ppgtt, pde, pt); | |
52c126ee | 1958 | |
e9e7dc41 CW |
1959 | mark_tlbs_dirty(&ppgtt->base); |
1960 | gen6_ggtt_invalidate(ppgtt->base.vm.i915); | |
52c126ee | 1961 | |
c8c26622 | 1962 | return 0; |
4933d519 | 1963 | } |
06dc68d6 | 1964 | |
e9e7dc41 | 1965 | static void pd_vma_unbind(struct i915_vma *vma) |
4933d519 | 1966 | { |
4a192c7e CW |
1967 | struct gen6_hw_ppgtt *ppgtt = vma->private; |
1968 | struct i915_page_table * const scratch_pt = ppgtt->base.vm.scratch_pt; | |
1969 | struct i915_page_table *pt; | |
1970 | unsigned int pde; | |
1971 | ||
1972 | if (!ppgtt->scan_for_unused_pt) | |
1973 | return; | |
1974 | ||
1975 | /* Free all no longer used page tables */ | |
1976 | gen6_for_all_pdes(pt, &ppgtt->base.pd, pde) { | |
1977 | if (pt->used_ptes || pt == scratch_pt) | |
1978 | continue; | |
1979 | ||
1980 | free_pt(&ppgtt->base.vm, pt); | |
1981 | ppgtt->base.pd.page_table[pde] = scratch_pt; | |
1982 | } | |
1983 | ||
1984 | ppgtt->scan_for_unused_pt = false; | |
e9e7dc41 CW |
1985 | } |
1986 | ||
1987 | static const struct i915_vma_ops pd_vma_ops = { | |
1988 | .set_pages = pd_vma_set_pages, | |
1989 | .clear_pages = pd_vma_clear_pages, | |
1990 | .bind_vma = pd_vma_bind, | |
1991 | .unbind_vma = pd_vma_unbind, | |
1992 | }; | |
1993 | ||
1994 | static struct i915_vma *pd_vma_create(struct gen6_hw_ppgtt *ppgtt, int size) | |
1995 | { | |
1996 | struct drm_i915_private *i915 = ppgtt->base.vm.i915; | |
1997 | struct i915_ggtt *ggtt = &i915->ggtt; | |
1998 | struct i915_vma *vma; | |
1999 | int i; | |
2000 | ||
2001 | GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE)); | |
2002 | GEM_BUG_ON(size > ggtt->vm.total); | |
2003 | ||
2004 | vma = kmem_cache_zalloc(i915->vmas, GFP_KERNEL); | |
2005 | if (!vma) | |
2006 | return ERR_PTR(-ENOMEM); | |
2007 | ||
2008 | for (i = 0; i < ARRAY_SIZE(vma->last_read); i++) | |
2009 | init_request_active(&vma->last_read[i], NULL); | |
2010 | init_request_active(&vma->last_fence, NULL); | |
2011 | ||
2012 | vma->vm = &ggtt->vm; | |
2013 | vma->ops = &pd_vma_ops; | |
2014 | vma->private = ppgtt; | |
2015 | ||
2016 | vma->size = size; | |
2017 | vma->fence_size = size; | |
2018 | vma->flags = I915_VMA_GGTT; | |
2019 | vma->ggtt_view.type = I915_GGTT_VIEW_ROTATED; /* prevent fencing */ | |
2020 | ||
2021 | INIT_LIST_HEAD(&vma->obj_link); | |
2022 | list_add(&vma->vm_link, &vma->vm->unbound_list); | |
2023 | ||
2024 | return vma; | |
2025 | } | |
1d2a314c | 2026 | |
a2bbf714 | 2027 | int gen6_ppgtt_pin(struct i915_hw_ppgtt *base) |
e9e7dc41 CW |
2028 | { |
2029 | struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(base); | |
2030 | ||
a2bbf714 CW |
2031 | /* |
2032 | * Workaround the limited maximum vma->pin_count and the aliasing_ppgtt | |
2033 | * which will be pinned into every active context. | |
2034 | * (When vma->pin_count becomes atomic, I expect we will naturally | |
2035 | * need a larger, unpacked, type and kill this redundancy.) | |
2036 | */ | |
2037 | if (ppgtt->pin_count++) | |
2038 | return 0; | |
2039 | ||
e9e7dc41 CW |
2040 | /* |
2041 | * PPGTT PDEs reside in the GGTT and consists of 512 entries. The | |
2042 | * allocator works in address space sizes, so it's multiplied by page | |
2043 | * size. We allocate at the top of the GTT to avoid fragmentation. | |
2044 | */ | |
2045 | return i915_vma_pin(ppgtt->vma, | |
2046 | 0, GEN6_PD_ALIGN, | |
2047 | PIN_GLOBAL | PIN_HIGH); | |
b146520f BW |
2048 | } |
2049 | ||
a2bbf714 CW |
2050 | void gen6_ppgtt_unpin(struct i915_hw_ppgtt *base) |
2051 | { | |
2052 | struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(base); | |
2053 | ||
2054 | GEM_BUG_ON(!ppgtt->pin_count); | |
2055 | if (--ppgtt->pin_count) | |
2056 | return; | |
2057 | ||
2058 | i915_vma_unpin(ppgtt->vma); | |
2059 | } | |
2060 | ||
17f297b4 | 2061 | static struct i915_hw_ppgtt *gen6_ppgtt_create(struct drm_i915_private *i915) |
b146520f | 2062 | { |
17f297b4 | 2063 | struct i915_ggtt * const ggtt = &i915->ggtt; |
35ac40d8 | 2064 | struct gen6_hw_ppgtt *ppgtt; |
17f297b4 CW |
2065 | int err; |
2066 | ||
2067 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
2068 | if (!ppgtt) | |
2069 | return ERR_PTR(-ENOMEM); | |
2070 | ||
35ac40d8 CW |
2071 | ppgtt->base.vm.i915 = i915; |
2072 | ppgtt->base.vm.dma = &i915->drm.pdev->dev; | |
b146520f | 2073 | |
35ac40d8 | 2074 | ppgtt->base.vm.total = I915_PDES * GEN6_PTES * PAGE_SIZE; |
1d2a314c | 2075 | |
549fe88b | 2076 | ppgtt->base.vm.allocate_va_range = gen6_alloc_va_range; |
35ac40d8 CW |
2077 | ppgtt->base.vm.clear_range = gen6_ppgtt_clear_range; |
2078 | ppgtt->base.vm.insert_entries = gen6_ppgtt_insert_entries; | |
2079 | ppgtt->base.vm.cleanup = gen6_ppgtt_cleanup; | |
2080 | ppgtt->base.debug_dump = gen6_dump_ppgtt; | |
054b9acd | 2081 | |
549fe88b | 2082 | ppgtt->base.vm.vma_ops.bind_vma = ppgtt_bind_vma; |
35ac40d8 CW |
2083 | ppgtt->base.vm.vma_ops.unbind_vma = ppgtt_unbind_vma; |
2084 | ppgtt->base.vm.vma_ops.set_pages = ppgtt_set_pages; | |
2085 | ppgtt->base.vm.vma_ops.clear_pages = clear_pages; | |
93f2cde2 | 2086 | |
a9ded785 CW |
2087 | ppgtt->base.vm.pte_encode = ggtt->vm.pte_encode; |
2088 | ||
e9e7dc41 | 2089 | err = gen6_ppgtt_init_scratch(ppgtt); |
a9ded785 CW |
2090 | if (err) |
2091 | goto err_free; | |
2092 | ||
e9e7dc41 CW |
2093 | ppgtt->vma = pd_vma_create(ppgtt, GEN6_PD_SIZE); |
2094 | if (IS_ERR(ppgtt->vma)) { | |
2095 | err = PTR_ERR(ppgtt->vma); | |
a9ded785 | 2096 | goto err_scratch; |
e9e7dc41 | 2097 | } |
a9ded785 | 2098 | |
35ac40d8 | 2099 | return &ppgtt->base; |
3440d265 | 2100 | |
a9ded785 CW |
2101 | err_scratch: |
2102 | gen6_ppgtt_free_scratch(&ppgtt->base.vm); | |
17f297b4 CW |
2103 | err_free: |
2104 | kfree(ppgtt); | |
2105 | return ERR_PTR(err); | |
fa76da34 | 2106 | } |
c114f76a | 2107 | |
a2cad9df | 2108 | static void i915_address_space_init(struct i915_address_space *vm, |
80b204bc CW |
2109 | struct drm_i915_private *dev_priv, |
2110 | const char *name) | |
a2cad9df | 2111 | { |
381b943b | 2112 | drm_mm_init(&vm->mm, 0, vm->total); |
47db922f CW |
2113 | vm->mm.head_node.color = I915_COLOR_UNEVICTABLE; |
2114 | ||
a2cad9df MW |
2115 | INIT_LIST_HEAD(&vm->active_list); |
2116 | INIT_LIST_HEAD(&vm->inactive_list); | |
50e046b6 | 2117 | INIT_LIST_HEAD(&vm->unbound_list); |
47db922f | 2118 | |
a2cad9df | 2119 | list_add_tail(&vm->global_link, &dev_priv->vm_list); |
86679820 | 2120 | pagevec_init(&vm->free_pages); |
a2cad9df MW |
2121 | } |
2122 | ||
ed9724dd MA |
2123 | static void i915_address_space_fini(struct i915_address_space *vm) |
2124 | { | |
8448661d | 2125 | if (pagevec_count(&vm->free_pages)) |
66df1014 | 2126 | vm_free_pages_release(vm, true); |
8448661d | 2127 | |
ed9724dd MA |
2128 | drm_mm_takedown(&vm->mm); |
2129 | list_del(&vm->global_link); | |
2130 | } | |
2131 | ||
c6be607a | 2132 | static void gtt_write_workarounds(struct drm_i915_private *dev_priv) |
d5165ebd | 2133 | { |
d5165ebd TG |
2134 | /* This function is for gtt related workarounds. This function is |
2135 | * called on driver load and after a GPU reset, so you can place | |
2136 | * workarounds here even if they get overwritten by GPU reset. | |
2137 | */ | |
cc38cae7 | 2138 | /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */ |
8652744b | 2139 | if (IS_BROADWELL(dev_priv)) |
d5165ebd | 2140 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW); |
920a14b2 | 2141 | else if (IS_CHERRYVIEW(dev_priv)) |
d5165ebd | 2142 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); |
9fb5026f | 2143 | else if (IS_GEN9_LP(dev_priv)) |
d5165ebd | 2144 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); |
cc38cae7 OM |
2145 | else if (INTEL_GEN(dev_priv) >= 9) |
2146 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); | |
9a6330cf MA |
2147 | |
2148 | /* | |
2149 | * To support 64K PTEs we need to first enable the use of the | |
2150 | * Intermediate-Page-Size(IPS) bit of the PDE field via some magical | |
2151 | * mmio, otherwise the page-walker will simply ignore the IPS bit. This | |
2152 | * shouldn't be needed after GEN10. | |
2153 | * | |
2154 | * 64K pages were first introduced from BDW+, although technically they | |
2155 | * only *work* from gen9+. For pre-BDW we instead have the option for | |
2156 | * 32K pages, but we don't currently have any support for it in our | |
2157 | * driver. | |
2158 | */ | |
2159 | if (HAS_PAGE_SIZES(dev_priv, I915_GTT_PAGE_SIZE_64K) && | |
2160 | INTEL_GEN(dev_priv) <= 10) | |
2161 | I915_WRITE(GEN8_GAMW_ECO_DEV_RW_IA, | |
2162 | I915_READ(GEN8_GAMW_ECO_DEV_RW_IA) | | |
2163 | GAMW_ECO_ENABLE_64K_IPS_FIELD); | |
d5165ebd TG |
2164 | } |
2165 | ||
c6be607a | 2166 | int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv) |
82460d97 | 2167 | { |
c6be607a | 2168 | gtt_write_workarounds(dev_priv); |
d5165ebd | 2169 | |
671b5013 TD |
2170 | /* In the case of execlists, PPGTT is enabled by the context descriptor |
2171 | * and the PDPs are contained within the context itself. We don't | |
2172 | * need to do anything here. */ | |
fb5c551a | 2173 | if (HAS_LOGICAL_RING_CONTEXTS(dev_priv)) |
671b5013 TD |
2174 | return 0; |
2175 | ||
c6be607a | 2176 | if (!USES_PPGTT(dev_priv)) |
82460d97 DV |
2177 | return 0; |
2178 | ||
5db94019 | 2179 | if (IS_GEN6(dev_priv)) |
c6be607a | 2180 | gen6_ppgtt_enable(dev_priv); |
5db94019 | 2181 | else if (IS_GEN7(dev_priv)) |
c6be607a TU |
2182 | gen7_ppgtt_enable(dev_priv); |
2183 | else if (INTEL_GEN(dev_priv) >= 8) | |
2184 | gen8_ppgtt_enable(dev_priv); | |
82460d97 | 2185 | else |
c6be607a | 2186 | MISSING_CASE(INTEL_GEN(dev_priv)); |
82460d97 | 2187 | |
4ad2fd88 JH |
2188 | return 0; |
2189 | } | |
1d2a314c | 2190 | |
17f297b4 CW |
2191 | static struct i915_hw_ppgtt * |
2192 | __hw_ppgtt_create(struct drm_i915_private *i915) | |
2193 | { | |
2194 | if (INTEL_GEN(i915) < 8) | |
2195 | return gen6_ppgtt_create(i915); | |
2196 | else | |
2197 | return gen8_ppgtt_create(i915); | |
2198 | } | |
2199 | ||
4d884705 | 2200 | struct i915_hw_ppgtt * |
17f297b4 | 2201 | i915_ppgtt_create(struct drm_i915_private *i915, |
80b204bc CW |
2202 | struct drm_i915_file_private *fpriv, |
2203 | const char *name) | |
4d884705 DV |
2204 | { |
2205 | struct i915_hw_ppgtt *ppgtt; | |
4d884705 | 2206 | |
17f297b4 CW |
2207 | ppgtt = __hw_ppgtt_create(i915); |
2208 | if (IS_ERR(ppgtt)) | |
2209 | return ppgtt; | |
4d884705 | 2210 | |
1188bc66 | 2211 | kref_init(&ppgtt->ref); |
17f297b4 | 2212 | i915_address_space_init(&ppgtt->vm, i915, name); |
82ad6443 | 2213 | ppgtt->vm.file = fpriv; |
1188bc66 | 2214 | |
82ad6443 | 2215 | trace_i915_ppgtt_create(&ppgtt->vm); |
198c974d | 2216 | |
4d884705 DV |
2217 | return ppgtt; |
2218 | } | |
2219 | ||
0c7eeda1 | 2220 | void i915_ppgtt_close(struct i915_address_space *vm) |
3365e226 CW |
2221 | { |
2222 | GEM_BUG_ON(vm->closed); | |
2223 | vm->closed = true; | |
2224 | } | |
2225 | ||
2226 | static void ppgtt_destroy_vma(struct i915_address_space *vm) | |
0c7eeda1 CW |
2227 | { |
2228 | struct list_head *phases[] = { | |
2229 | &vm->active_list, | |
2230 | &vm->inactive_list, | |
2231 | &vm->unbound_list, | |
2232 | NULL, | |
2233 | }, **phase; | |
2234 | ||
0c7eeda1 | 2235 | vm->closed = true; |
0c7eeda1 CW |
2236 | for (phase = phases; *phase; phase++) { |
2237 | struct i915_vma *vma, *vn; | |
2238 | ||
2239 | list_for_each_entry_safe(vma, vn, *phase, vm_link) | |
3365e226 | 2240 | i915_vma_destroy(vma); |
0c7eeda1 CW |
2241 | } |
2242 | } | |
2243 | ||
ed9724dd | 2244 | void i915_ppgtt_release(struct kref *kref) |
ee960be7 DV |
2245 | { |
2246 | struct i915_hw_ppgtt *ppgtt = | |
2247 | container_of(kref, struct i915_hw_ppgtt, ref); | |
2248 | ||
82ad6443 | 2249 | trace_i915_ppgtt_release(&ppgtt->vm); |
198c974d | 2250 | |
82ad6443 | 2251 | ppgtt_destroy_vma(&ppgtt->vm); |
3365e226 | 2252 | |
82ad6443 CW |
2253 | GEM_BUG_ON(!list_empty(&ppgtt->vm.active_list)); |
2254 | GEM_BUG_ON(!list_empty(&ppgtt->vm.inactive_list)); | |
2255 | GEM_BUG_ON(!list_empty(&ppgtt->vm.unbound_list)); | |
ee960be7 | 2256 | |
82ad6443 CW |
2257 | ppgtt->vm.cleanup(&ppgtt->vm); |
2258 | i915_address_space_fini(&ppgtt->vm); | |
ee960be7 DV |
2259 | kfree(ppgtt); |
2260 | } | |
1d2a314c | 2261 | |
a81cc00c BW |
2262 | /* Certain Gen5 chipsets require require idling the GPU before |
2263 | * unmapping anything from the GTT when VT-d is enabled. | |
2264 | */ | |
97d6d7ab | 2265 | static bool needs_idle_maps(struct drm_i915_private *dev_priv) |
a81cc00c | 2266 | { |
a81cc00c BW |
2267 | /* Query intel_iommu to see if we need the workaround. Presumably that |
2268 | * was loaded first. | |
2269 | */ | |
80debff8 | 2270 | return IS_GEN5(dev_priv) && IS_MOBILE(dev_priv) && intel_vtd_active(); |
a81cc00c BW |
2271 | } |
2272 | ||
b03ec3d6 | 2273 | static void gen6_check_and_clear_faults(struct drm_i915_private *dev_priv) |
828c7908 | 2274 | { |
e2f80391 | 2275 | struct intel_engine_cs *engine; |
3b3f1650 | 2276 | enum intel_engine_id id; |
b03ec3d6 | 2277 | u32 fault; |
828c7908 | 2278 | |
3b3f1650 | 2279 | for_each_engine(engine, dev_priv, id) { |
b03ec3d6 MT |
2280 | fault = I915_READ(RING_FAULT_REG(engine)); |
2281 | if (fault & RING_FAULT_VALID) { | |
828c7908 | 2282 | DRM_DEBUG_DRIVER("Unexpected fault\n" |
59a5d290 | 2283 | "\tAddr: 0x%08lx\n" |
828c7908 BW |
2284 | "\tAddress space: %s\n" |
2285 | "\tSource ID: %d\n" | |
2286 | "\tType: %d\n", | |
b03ec3d6 MT |
2287 | fault & PAGE_MASK, |
2288 | fault & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
2289 | RING_FAULT_SRCID(fault), | |
2290 | RING_FAULT_FAULT_TYPE(fault)); | |
e2f80391 | 2291 | I915_WRITE(RING_FAULT_REG(engine), |
b03ec3d6 | 2292 | fault & ~RING_FAULT_VALID); |
828c7908 BW |
2293 | } |
2294 | } | |
3b3f1650 | 2295 | |
b03ec3d6 MT |
2296 | POSTING_READ(RING_FAULT_REG(dev_priv->engine[RCS])); |
2297 | } | |
2298 | ||
2299 | static void gen8_check_and_clear_faults(struct drm_i915_private *dev_priv) | |
2300 | { | |
2301 | u32 fault = I915_READ(GEN8_RING_FAULT_REG); | |
2302 | ||
2303 | if (fault & RING_FAULT_VALID) { | |
5a3f58df OM |
2304 | u32 fault_data0, fault_data1; |
2305 | u64 fault_addr; | |
2306 | ||
2307 | fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0); | |
2308 | fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1); | |
2309 | fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) | | |
2310 | ((u64)fault_data0 << 12); | |
2311 | ||
b03ec3d6 | 2312 | DRM_DEBUG_DRIVER("Unexpected fault\n" |
5a3f58df OM |
2313 | "\tAddr: 0x%08x_%08x\n" |
2314 | "\tAddress space: %s\n" | |
b03ec3d6 MT |
2315 | "\tEngine ID: %d\n" |
2316 | "\tSource ID: %d\n" | |
2317 | "\tType: %d\n", | |
5a3f58df OM |
2318 | upper_32_bits(fault_addr), |
2319 | lower_32_bits(fault_addr), | |
2320 | fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT", | |
b03ec3d6 MT |
2321 | GEN8_RING_FAULT_ENGINE_ID(fault), |
2322 | RING_FAULT_SRCID(fault), | |
2323 | RING_FAULT_FAULT_TYPE(fault)); | |
2324 | I915_WRITE(GEN8_RING_FAULT_REG, | |
2325 | fault & ~RING_FAULT_VALID); | |
2326 | } | |
2327 | ||
2328 | POSTING_READ(GEN8_RING_FAULT_REG); | |
2329 | } | |
2330 | ||
2331 | void i915_check_and_clear_faults(struct drm_i915_private *dev_priv) | |
2332 | { | |
2333 | /* From GEN8 onwards we only have one 'All Engine Fault Register' */ | |
2334 | if (INTEL_GEN(dev_priv) >= 8) | |
2335 | gen8_check_and_clear_faults(dev_priv); | |
2336 | else if (INTEL_GEN(dev_priv) >= 6) | |
2337 | gen6_check_and_clear_faults(dev_priv); | |
2338 | else | |
2339 | return; | |
828c7908 BW |
2340 | } |
2341 | ||
275a991c | 2342 | void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv) |
828c7908 | 2343 | { |
72e96d64 | 2344 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
828c7908 BW |
2345 | |
2346 | /* Don't bother messing with faults pre GEN6 as we have little | |
2347 | * documentation supporting that it's a good idea. | |
2348 | */ | |
275a991c | 2349 | if (INTEL_GEN(dev_priv) < 6) |
828c7908 BW |
2350 | return; |
2351 | ||
dc97997a | 2352 | i915_check_and_clear_faults(dev_priv); |
828c7908 | 2353 | |
82ad6443 | 2354 | ggtt->vm.clear_range(&ggtt->vm, 0, ggtt->vm.total); |
91e56499 | 2355 | |
7c3f86b6 | 2356 | i915_ggtt_invalidate(dev_priv); |
828c7908 BW |
2357 | } |
2358 | ||
03ac84f1 CW |
2359 | int i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj, |
2360 | struct sg_table *pages) | |
7c2e6fdf | 2361 | { |
1a292fa5 | 2362 | do { |
82e07602 CW |
2363 | if (dma_map_sg_attrs(&obj->base.dev->pdev->dev, |
2364 | pages->sgl, pages->nents, | |
2365 | PCI_DMA_BIDIRECTIONAL, | |
2366 | DMA_ATTR_NO_WARN)) | |
1a292fa5 CW |
2367 | return 0; |
2368 | ||
2369 | /* If the DMA remap fails, one cause can be that we have | |
2370 | * too many objects pinned in a small remapping table, | |
2371 | * such as swiotlb. Incrementally purge all other objects and | |
2372 | * try again - if there are no more pages to remove from | |
2373 | * the DMA remapper, i915_gem_shrink will return 0. | |
2374 | */ | |
2375 | GEM_BUG_ON(obj->mm.pages == pages); | |
2376 | } while (i915_gem_shrink(to_i915(obj->base.dev), | |
912d572d | 2377 | obj->base.size >> PAGE_SHIFT, NULL, |
1a292fa5 CW |
2378 | I915_SHRINK_BOUND | |
2379 | I915_SHRINK_UNBOUND | | |
2380 | I915_SHRINK_ACTIVE)); | |
9da3da66 | 2381 | |
03ac84f1 | 2382 | return -ENOSPC; |
7c2e6fdf DV |
2383 | } |
2384 | ||
2c642b07 | 2385 | static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte) |
94ec8f61 | 2386 | { |
94ec8f61 | 2387 | writeq(pte, addr); |
94ec8f61 BW |
2388 | } |
2389 | ||
d6473f56 CW |
2390 | static void gen8_ggtt_insert_page(struct i915_address_space *vm, |
2391 | dma_addr_t addr, | |
75c7b0b8 | 2392 | u64 offset, |
d6473f56 CW |
2393 | enum i915_cache_level level, |
2394 | u32 unused) | |
2395 | { | |
7c3f86b6 | 2396 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
d6473f56 | 2397 | gen8_pte_t __iomem *pte = |
7c3f86b6 | 2398 | (gen8_pte_t __iomem *)ggtt->gsm + (offset >> PAGE_SHIFT); |
d6473f56 | 2399 | |
4fb84d99 | 2400 | gen8_set_pte(pte, gen8_pte_encode(addr, level)); |
d6473f56 | 2401 | |
7c3f86b6 | 2402 | ggtt->invalidate(vm->i915); |
d6473f56 CW |
2403 | } |
2404 | ||
94ec8f61 | 2405 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, |
4a234c5f | 2406 | struct i915_vma *vma, |
75c7b0b8 CW |
2407 | enum i915_cache_level level, |
2408 | u32 unused) | |
94ec8f61 | 2409 | { |
ce7fda2e | 2410 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
85d1225e DG |
2411 | struct sgt_iter sgt_iter; |
2412 | gen8_pte_t __iomem *gtt_entries; | |
894ccebe | 2413 | const gen8_pte_t pte_encode = gen8_pte_encode(0, level); |
85d1225e | 2414 | dma_addr_t addr; |
be69459a | 2415 | |
894ccebe | 2416 | gtt_entries = (gen8_pte_t __iomem *)ggtt->gsm; |
4a234c5f MA |
2417 | gtt_entries += vma->node.start >> PAGE_SHIFT; |
2418 | for_each_sgt_dma(addr, sgt_iter, vma->pages) | |
894ccebe | 2419 | gen8_set_pte(gtt_entries++, pte_encode | addr); |
85d1225e | 2420 | |
ca6acc25 MK |
2421 | /* |
2422 | * We want to flush the TLBs only after we're certain all the PTE | |
2423 | * updates have finished. | |
94ec8f61 | 2424 | */ |
7c3f86b6 | 2425 | ggtt->invalidate(vm->i915); |
94ec8f61 BW |
2426 | } |
2427 | ||
d6473f56 CW |
2428 | static void gen6_ggtt_insert_page(struct i915_address_space *vm, |
2429 | dma_addr_t addr, | |
75c7b0b8 | 2430 | u64 offset, |
d6473f56 CW |
2431 | enum i915_cache_level level, |
2432 | u32 flags) | |
2433 | { | |
7c3f86b6 | 2434 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
d6473f56 | 2435 | gen6_pte_t __iomem *pte = |
7c3f86b6 | 2436 | (gen6_pte_t __iomem *)ggtt->gsm + (offset >> PAGE_SHIFT); |
d6473f56 | 2437 | |
4fb84d99 | 2438 | iowrite32(vm->pte_encode(addr, level, flags), pte); |
d6473f56 | 2439 | |
7c3f86b6 | 2440 | ggtt->invalidate(vm->i915); |
d6473f56 CW |
2441 | } |
2442 | ||
e76e9aeb BW |
2443 | /* |
2444 | * Binds an object into the global gtt with the specified cache level. The object | |
2445 | * will be accessible to the GPU via commands whose operands reference offsets | |
2446 | * within the global GTT as well as accessible by the GPU through the GMADR | |
2447 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
2448 | */ | |
853ba5d2 | 2449 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
4a234c5f | 2450 | struct i915_vma *vma, |
75c7b0b8 CW |
2451 | enum i915_cache_level level, |
2452 | u32 flags) | |
e76e9aeb | 2453 | { |
ce7fda2e | 2454 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
b31144c0 | 2455 | gen6_pte_t __iomem *entries = (gen6_pte_t __iomem *)ggtt->gsm; |
4a234c5f | 2456 | unsigned int i = vma->node.start >> PAGE_SHIFT; |
b31144c0 | 2457 | struct sgt_iter iter; |
85d1225e | 2458 | dma_addr_t addr; |
4a234c5f | 2459 | for_each_sgt_dma(addr, iter, vma->pages) |
b31144c0 | 2460 | iowrite32(vm->pte_encode(addr, level, flags), &entries[i++]); |
0f9b91c7 | 2461 | |
ca6acc25 MK |
2462 | /* |
2463 | * We want to flush the TLBs only after we're certain all the PTE | |
2464 | * updates have finished. | |
0f9b91c7 | 2465 | */ |
7c3f86b6 | 2466 | ggtt->invalidate(vm->i915); |
e76e9aeb BW |
2467 | } |
2468 | ||
f7770bfd | 2469 | static void nop_clear_range(struct i915_address_space *vm, |
75c7b0b8 | 2470 | u64 start, u64 length) |
f7770bfd CW |
2471 | { |
2472 | } | |
2473 | ||
94ec8f61 | 2474 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
75c7b0b8 | 2475 | u64 start, u64 length) |
94ec8f61 | 2476 | { |
ce7fda2e | 2477 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
782f1495 BW |
2478 | unsigned first_entry = start >> PAGE_SHIFT; |
2479 | unsigned num_entries = length >> PAGE_SHIFT; | |
894ccebe CW |
2480 | const gen8_pte_t scratch_pte = |
2481 | gen8_pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC); | |
2482 | gen8_pte_t __iomem *gtt_base = | |
72e96d64 JL |
2483 | (gen8_pte_t __iomem *)ggtt->gsm + first_entry; |
2484 | const int max_entries = ggtt_total_entries(ggtt) - first_entry; | |
94ec8f61 BW |
2485 | int i; |
2486 | ||
2487 | if (WARN(num_entries > max_entries, | |
2488 | "First entry = %d; Num entries = %d (max=%d)\n", | |
2489 | first_entry, num_entries, max_entries)) | |
2490 | num_entries = max_entries; | |
2491 | ||
94ec8f61 BW |
2492 | for (i = 0; i < num_entries; i++) |
2493 | gen8_set_pte(>t_base[i], scratch_pte); | |
94ec8f61 BW |
2494 | } |
2495 | ||
0ef34ad6 JB |
2496 | static void bxt_vtd_ggtt_wa(struct i915_address_space *vm) |
2497 | { | |
2498 | struct drm_i915_private *dev_priv = vm->i915; | |
2499 | ||
2500 | /* | |
2501 | * Make sure the internal GAM fifo has been cleared of all GTT | |
2502 | * writes before exiting stop_machine(). This guarantees that | |
2503 | * any aperture accesses waiting to start in another process | |
2504 | * cannot back up behind the GTT writes causing a hang. | |
2505 | * The register can be any arbitrary GAM register. | |
2506 | */ | |
2507 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
2508 | } | |
2509 | ||
2510 | struct insert_page { | |
2511 | struct i915_address_space *vm; | |
2512 | dma_addr_t addr; | |
2513 | u64 offset; | |
2514 | enum i915_cache_level level; | |
2515 | }; | |
2516 | ||
2517 | static int bxt_vtd_ggtt_insert_page__cb(void *_arg) | |
2518 | { | |
2519 | struct insert_page *arg = _arg; | |
2520 | ||
2521 | gen8_ggtt_insert_page(arg->vm, arg->addr, arg->offset, arg->level, 0); | |
2522 | bxt_vtd_ggtt_wa(arg->vm); | |
2523 | ||
2524 | return 0; | |
2525 | } | |
2526 | ||
2527 | static void bxt_vtd_ggtt_insert_page__BKL(struct i915_address_space *vm, | |
2528 | dma_addr_t addr, | |
2529 | u64 offset, | |
2530 | enum i915_cache_level level, | |
2531 | u32 unused) | |
2532 | { | |
2533 | struct insert_page arg = { vm, addr, offset, level }; | |
2534 | ||
2535 | stop_machine(bxt_vtd_ggtt_insert_page__cb, &arg, NULL); | |
2536 | } | |
2537 | ||
2538 | struct insert_entries { | |
2539 | struct i915_address_space *vm; | |
4a234c5f | 2540 | struct i915_vma *vma; |
0ef34ad6 JB |
2541 | enum i915_cache_level level; |
2542 | }; | |
2543 | ||
2544 | static int bxt_vtd_ggtt_insert_entries__cb(void *_arg) | |
2545 | { | |
2546 | struct insert_entries *arg = _arg; | |
2547 | ||
4a234c5f | 2548 | gen8_ggtt_insert_entries(arg->vm, arg->vma, arg->level, 0); |
0ef34ad6 JB |
2549 | bxt_vtd_ggtt_wa(arg->vm); |
2550 | ||
2551 | return 0; | |
2552 | } | |
2553 | ||
2554 | static void bxt_vtd_ggtt_insert_entries__BKL(struct i915_address_space *vm, | |
4a234c5f | 2555 | struct i915_vma *vma, |
0ef34ad6 JB |
2556 | enum i915_cache_level level, |
2557 | u32 unused) | |
2558 | { | |
17369ba0 | 2559 | struct insert_entries arg = { vm, vma, level }; |
0ef34ad6 JB |
2560 | |
2561 | stop_machine(bxt_vtd_ggtt_insert_entries__cb, &arg, NULL); | |
2562 | } | |
2563 | ||
2564 | struct clear_range { | |
2565 | struct i915_address_space *vm; | |
2566 | u64 start; | |
2567 | u64 length; | |
2568 | }; | |
2569 | ||
2570 | static int bxt_vtd_ggtt_clear_range__cb(void *_arg) | |
2571 | { | |
2572 | struct clear_range *arg = _arg; | |
2573 | ||
2574 | gen8_ggtt_clear_range(arg->vm, arg->start, arg->length); | |
2575 | bxt_vtd_ggtt_wa(arg->vm); | |
2576 | ||
2577 | return 0; | |
2578 | } | |
2579 | ||
2580 | static void bxt_vtd_ggtt_clear_range__BKL(struct i915_address_space *vm, | |
2581 | u64 start, | |
2582 | u64 length) | |
2583 | { | |
2584 | struct clear_range arg = { vm, start, length }; | |
2585 | ||
2586 | stop_machine(bxt_vtd_ggtt_clear_range__cb, &arg, NULL); | |
2587 | } | |
2588 | ||
853ba5d2 | 2589 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
75c7b0b8 | 2590 | u64 start, u64 length) |
7faf1ab2 | 2591 | { |
ce7fda2e | 2592 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
782f1495 BW |
2593 | unsigned first_entry = start >> PAGE_SHIFT; |
2594 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 | 2595 | gen6_pte_t scratch_pte, __iomem *gtt_base = |
72e96d64 JL |
2596 | (gen6_pte_t __iomem *)ggtt->gsm + first_entry; |
2597 | const int max_entries = ggtt_total_entries(ggtt) - first_entry; | |
7faf1ab2 DV |
2598 | int i; |
2599 | ||
2600 | if (WARN(num_entries > max_entries, | |
2601 | "First entry = %d; Num entries = %d (max=%d)\n", | |
2602 | first_entry, num_entries, max_entries)) | |
2603 | num_entries = max_entries; | |
2604 | ||
8bcdd0f7 | 2605 | scratch_pte = vm->pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 2606 | I915_CACHE_LLC, 0); |
828c7908 | 2607 | |
7faf1ab2 DV |
2608 | for (i = 0; i < num_entries; i++) |
2609 | iowrite32(scratch_pte, >t_base[i]); | |
7faf1ab2 DV |
2610 | } |
2611 | ||
d6473f56 CW |
2612 | static void i915_ggtt_insert_page(struct i915_address_space *vm, |
2613 | dma_addr_t addr, | |
75c7b0b8 | 2614 | u64 offset, |
d6473f56 CW |
2615 | enum i915_cache_level cache_level, |
2616 | u32 unused) | |
2617 | { | |
d6473f56 CW |
2618 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? |
2619 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
d6473f56 CW |
2620 | |
2621 | intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags); | |
d6473f56 CW |
2622 | } |
2623 | ||
d369d2d9 | 2624 | static void i915_ggtt_insert_entries(struct i915_address_space *vm, |
4a234c5f | 2625 | struct i915_vma *vma, |
75c7b0b8 CW |
2626 | enum i915_cache_level cache_level, |
2627 | u32 unused) | |
7faf1ab2 DV |
2628 | { |
2629 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? | |
2630 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
2631 | ||
4a234c5f MA |
2632 | intel_gtt_insert_sg_entries(vma->pages, vma->node.start >> PAGE_SHIFT, |
2633 | flags); | |
7faf1ab2 DV |
2634 | } |
2635 | ||
853ba5d2 | 2636 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
75c7b0b8 | 2637 | u64 start, u64 length) |
7faf1ab2 | 2638 | { |
2eedfc7d | 2639 | intel_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT); |
7faf1ab2 DV |
2640 | } |
2641 | ||
70b9f6f8 DV |
2642 | static int ggtt_bind_vma(struct i915_vma *vma, |
2643 | enum i915_cache_level cache_level, | |
2644 | u32 flags) | |
0a878716 | 2645 | { |
49d73912 | 2646 | struct drm_i915_private *i915 = vma->vm->i915; |
0a878716 | 2647 | struct drm_i915_gem_object *obj = vma->obj; |
ba7a5741 | 2648 | u32 pte_flags; |
0a878716 | 2649 | |
0a878716 | 2650 | /* Currently applicable only to VLV */ |
ba7a5741 | 2651 | pte_flags = 0; |
0a878716 DV |
2652 | if (obj->gt_ro) |
2653 | pte_flags |= PTE_READ_ONLY; | |
2654 | ||
9c870d03 | 2655 | intel_runtime_pm_get(i915); |
4a234c5f | 2656 | vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags); |
9c870d03 | 2657 | intel_runtime_pm_put(i915); |
0a878716 | 2658 | |
d9ec12f8 MA |
2659 | vma->page_sizes.gtt = I915_GTT_PAGE_SIZE; |
2660 | ||
0a878716 DV |
2661 | /* |
2662 | * Without aliasing PPGTT there's no difference between | |
2663 | * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally | |
2664 | * upgrade to both bound if we bind either to avoid double-binding. | |
2665 | */ | |
3272db53 | 2666 | vma->flags |= I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND; |
0a878716 DV |
2667 | |
2668 | return 0; | |
2669 | } | |
2670 | ||
cbc4e9e6 CW |
2671 | static void ggtt_unbind_vma(struct i915_vma *vma) |
2672 | { | |
2673 | struct drm_i915_private *i915 = vma->vm->i915; | |
2674 | ||
2675 | intel_runtime_pm_get(i915); | |
2676 | vma->vm->clear_range(vma->vm, vma->node.start, vma->size); | |
2677 | intel_runtime_pm_put(i915); | |
2678 | } | |
2679 | ||
0a878716 DV |
2680 | static int aliasing_gtt_bind_vma(struct i915_vma *vma, |
2681 | enum i915_cache_level cache_level, | |
2682 | u32 flags) | |
d5bd1449 | 2683 | { |
49d73912 | 2684 | struct drm_i915_private *i915 = vma->vm->i915; |
321d178e | 2685 | u32 pte_flags; |
ff685975 | 2686 | int ret; |
70b9f6f8 | 2687 | |
24f3a8cf | 2688 | /* Currently applicable only to VLV */ |
321d178e CW |
2689 | pte_flags = 0; |
2690 | if (vma->obj->gt_ro) | |
f329f5f6 | 2691 | pte_flags |= PTE_READ_ONLY; |
24f3a8cf | 2692 | |
ff685975 CW |
2693 | if (flags & I915_VMA_LOCAL_BIND) { |
2694 | struct i915_hw_ppgtt *appgtt = i915->mm.aliasing_ppgtt; | |
2695 | ||
549fe88b | 2696 | if (!(vma->flags & I915_VMA_LOCAL_BIND)) { |
82ad6443 CW |
2697 | ret = appgtt->vm.allocate_va_range(&appgtt->vm, |
2698 | vma->node.start, | |
2699 | vma->size); | |
ff685975 | 2700 | if (ret) |
fa3f46af | 2701 | return ret; |
ff685975 CW |
2702 | } |
2703 | ||
82ad6443 CW |
2704 | appgtt->vm.insert_entries(&appgtt->vm, vma, cache_level, |
2705 | pte_flags); | |
ff685975 CW |
2706 | } |
2707 | ||
3272db53 | 2708 | if (flags & I915_VMA_GLOBAL_BIND) { |
9c870d03 | 2709 | intel_runtime_pm_get(i915); |
4a234c5f | 2710 | vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags); |
9c870d03 | 2711 | intel_runtime_pm_put(i915); |
6f65e29a | 2712 | } |
d5bd1449 | 2713 | |
70b9f6f8 | 2714 | return 0; |
d5bd1449 CW |
2715 | } |
2716 | ||
cbc4e9e6 | 2717 | static void aliasing_gtt_unbind_vma(struct i915_vma *vma) |
74163907 | 2718 | { |
49d73912 | 2719 | struct drm_i915_private *i915 = vma->vm->i915; |
6f65e29a | 2720 | |
9c870d03 CW |
2721 | if (vma->flags & I915_VMA_GLOBAL_BIND) { |
2722 | intel_runtime_pm_get(i915); | |
cbc4e9e6 | 2723 | vma->vm->clear_range(vma->vm, vma->node.start, vma->size); |
9c870d03 CW |
2724 | intel_runtime_pm_put(i915); |
2725 | } | |
06615ee5 | 2726 | |
cbc4e9e6 | 2727 | if (vma->flags & I915_VMA_LOCAL_BIND) { |
82ad6443 | 2728 | struct i915_address_space *vm = &i915->mm.aliasing_ppgtt->vm; |
cbc4e9e6 CW |
2729 | |
2730 | vm->clear_range(vm, vma->node.start, vma->size); | |
2731 | } | |
74163907 DV |
2732 | } |
2733 | ||
03ac84f1 CW |
2734 | void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj, |
2735 | struct sg_table *pages) | |
7c2e6fdf | 2736 | { |
52a05c30 DW |
2737 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
2738 | struct device *kdev = &dev_priv->drm.pdev->dev; | |
307dc25b | 2739 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
5c042287 | 2740 | |
307dc25b | 2741 | if (unlikely(ggtt->do_idle_maps)) { |
228ec87c | 2742 | if (i915_gem_wait_for_idle(dev_priv, 0)) { |
307dc25b CW |
2743 | DRM_ERROR("Failed to wait for idle; VT'd may hang.\n"); |
2744 | /* Wait a bit, in hopes it avoids the hang */ | |
2745 | udelay(10); | |
2746 | } | |
2747 | } | |
5c042287 | 2748 | |
03ac84f1 | 2749 | dma_unmap_sg(kdev, pages->sgl, pages->nents, PCI_DMA_BIDIRECTIONAL); |
7c2e6fdf | 2750 | } |
644ec02b | 2751 | |
fa3f46af MA |
2752 | static int ggtt_set_pages(struct i915_vma *vma) |
2753 | { | |
2754 | int ret; | |
2755 | ||
2756 | GEM_BUG_ON(vma->pages); | |
2757 | ||
2758 | ret = i915_get_ggtt_vma_pages(vma); | |
2759 | if (ret) | |
2760 | return ret; | |
2761 | ||
7464284b MA |
2762 | vma->page_sizes = vma->obj->mm.page_sizes; |
2763 | ||
fa3f46af MA |
2764 | return 0; |
2765 | } | |
2766 | ||
45b186f1 | 2767 | static void i915_gtt_color_adjust(const struct drm_mm_node *node, |
42d6ab48 | 2768 | unsigned long color, |
440fd528 TR |
2769 | u64 *start, |
2770 | u64 *end) | |
42d6ab48 | 2771 | { |
a6508ded | 2772 | if (node->allocated && node->color != color) |
f51455d4 | 2773 | *start += I915_GTT_PAGE_SIZE; |
42d6ab48 | 2774 | |
a6508ded CW |
2775 | /* Also leave a space between the unallocated reserved node after the |
2776 | * GTT and any objects within the GTT, i.e. we use the color adjustment | |
2777 | * to insert a guard page to prevent prefetches crossing over the | |
2778 | * GTT boundary. | |
2779 | */ | |
b44f97fd | 2780 | node = list_next_entry(node, node_list); |
a6508ded | 2781 | if (node->color != color) |
f51455d4 | 2782 | *end -= I915_GTT_PAGE_SIZE; |
42d6ab48 | 2783 | } |
fbe5d36e | 2784 | |
6cde9a02 CW |
2785 | int i915_gem_init_aliasing_ppgtt(struct drm_i915_private *i915) |
2786 | { | |
2787 | struct i915_ggtt *ggtt = &i915->ggtt; | |
2788 | struct i915_hw_ppgtt *ppgtt; | |
2789 | int err; | |
2790 | ||
57202f47 | 2791 | ppgtt = i915_ppgtt_create(i915, ERR_PTR(-EPERM), "[alias]"); |
1188bc66 CW |
2792 | if (IS_ERR(ppgtt)) |
2793 | return PTR_ERR(ppgtt); | |
6cde9a02 | 2794 | |
a0fbacb5 | 2795 | if (GEM_WARN_ON(ppgtt->vm.total < ggtt->vm.total)) { |
e565ceb0 CW |
2796 | err = -ENODEV; |
2797 | goto err_ppgtt; | |
2798 | } | |
2799 | ||
549fe88b CW |
2800 | /* |
2801 | * Note we only pre-allocate as far as the end of the global | |
2802 | * GTT. On 48b / 4-level page-tables, the difference is very, | |
2803 | * very significant! We have to preallocate as GVT/vgpu does | |
2804 | * not like the page directory disappearing. | |
2805 | */ | |
2806 | err = ppgtt->vm.allocate_va_range(&ppgtt->vm, 0, ggtt->vm.total); | |
2807 | if (err) | |
2808 | goto err_ppgtt; | |
6cde9a02 | 2809 | |
6cde9a02 | 2810 | i915->mm.aliasing_ppgtt = ppgtt; |
cbc4e9e6 | 2811 | |
93f2cde2 CW |
2812 | GEM_BUG_ON(ggtt->vm.vma_ops.bind_vma != ggtt_bind_vma); |
2813 | ggtt->vm.vma_ops.bind_vma = aliasing_gtt_bind_vma; | |
6cde9a02 | 2814 | |
93f2cde2 CW |
2815 | GEM_BUG_ON(ggtt->vm.vma_ops.unbind_vma != ggtt_unbind_vma); |
2816 | ggtt->vm.vma_ops.unbind_vma = aliasing_gtt_unbind_vma; | |
cbc4e9e6 | 2817 | |
6cde9a02 CW |
2818 | return 0; |
2819 | ||
6cde9a02 | 2820 | err_ppgtt: |
1188bc66 | 2821 | i915_ppgtt_put(ppgtt); |
6cde9a02 CW |
2822 | return err; |
2823 | } | |
2824 | ||
2825 | void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private *i915) | |
2826 | { | |
2827 | struct i915_ggtt *ggtt = &i915->ggtt; | |
2828 | struct i915_hw_ppgtt *ppgtt; | |
2829 | ||
2830 | ppgtt = fetch_and_zero(&i915->mm.aliasing_ppgtt); | |
2831 | if (!ppgtt) | |
2832 | return; | |
2833 | ||
1188bc66 | 2834 | i915_ppgtt_put(ppgtt); |
6cde9a02 | 2835 | |
93f2cde2 CW |
2836 | ggtt->vm.vma_ops.bind_vma = ggtt_bind_vma; |
2837 | ggtt->vm.vma_ops.unbind_vma = ggtt_unbind_vma; | |
6cde9a02 CW |
2838 | } |
2839 | ||
f6b9d5ca | 2840 | int i915_gem_init_ggtt(struct drm_i915_private *dev_priv) |
644ec02b | 2841 | { |
e78891ca BW |
2842 | /* Let GEM Manage all of the aperture. |
2843 | * | |
2844 | * However, leave one page at the end still bound to the scratch page. | |
2845 | * There are a number of places where the hardware apparently prefetches | |
2846 | * past the end of the object, and we've seen multiple hangs with the | |
2847 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
2848 | * aperture. One page should be enough to keep any prefetching inside | |
2849 | * of the aperture. | |
2850 | */ | |
72e96d64 | 2851 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
ed2f3452 | 2852 | unsigned long hole_start, hole_end; |
f6b9d5ca | 2853 | struct drm_mm_node *entry; |
fa76da34 | 2854 | int ret; |
644ec02b | 2855 | |
b02d22a3 ZW |
2856 | ret = intel_vgt_balloon(dev_priv); |
2857 | if (ret) | |
2858 | return ret; | |
5dda8fa3 | 2859 | |
95374d75 | 2860 | /* Reserve a mappable slot for our lockless error capture */ |
82ad6443 | 2861 | ret = drm_mm_insert_node_in_range(&ggtt->vm.mm, &ggtt->error_capture, |
4e64e553 CW |
2862 | PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE, |
2863 | 0, ggtt->mappable_end, | |
2864 | DRM_MM_INSERT_LOW); | |
95374d75 CW |
2865 | if (ret) |
2866 | return ret; | |
2867 | ||
ed2f3452 | 2868 | /* Clear any non-preallocated blocks */ |
82ad6443 | 2869 | drm_mm_for_each_hole(entry, &ggtt->vm.mm, hole_start, hole_end) { |
ed2f3452 CW |
2870 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
2871 | hole_start, hole_end); | |
82ad6443 CW |
2872 | ggtt->vm.clear_range(&ggtt->vm, hole_start, |
2873 | hole_end - hole_start); | |
ed2f3452 CW |
2874 | } |
2875 | ||
2876 | /* And finally clear the reserved guard page */ | |
82ad6443 | 2877 | ggtt->vm.clear_range(&ggtt->vm, ggtt->vm.total - PAGE_SIZE, PAGE_SIZE); |
6c5566a8 | 2878 | |
97d6d7ab | 2879 | if (USES_PPGTT(dev_priv) && !USES_FULL_PPGTT(dev_priv)) { |
6cde9a02 | 2880 | ret = i915_gem_init_aliasing_ppgtt(dev_priv); |
95374d75 | 2881 | if (ret) |
6cde9a02 | 2882 | goto err; |
fa76da34 DV |
2883 | } |
2884 | ||
6c5566a8 | 2885 | return 0; |
95374d75 | 2886 | |
95374d75 CW |
2887 | err: |
2888 | drm_mm_remove_node(&ggtt->error_capture); | |
2889 | return ret; | |
e76e9aeb BW |
2890 | } |
2891 | ||
d85489d3 JL |
2892 | /** |
2893 | * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization | |
97d6d7ab | 2894 | * @dev_priv: i915 device |
d85489d3 | 2895 | */ |
97d6d7ab | 2896 | void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv) |
90d0a0e8 | 2897 | { |
72e96d64 | 2898 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
94d4a2a9 | 2899 | struct i915_vma *vma, *vn; |
66df1014 | 2900 | struct pagevec *pvec; |
94d4a2a9 | 2901 | |
82ad6443 | 2902 | ggtt->vm.closed = true; |
94d4a2a9 CW |
2903 | |
2904 | mutex_lock(&dev_priv->drm.struct_mutex); | |
eed28903 CW |
2905 | i915_gem_fini_aliasing_ppgtt(dev_priv); |
2906 | ||
82ad6443 CW |
2907 | GEM_BUG_ON(!list_empty(&ggtt->vm.active_list)); |
2908 | list_for_each_entry_safe(vma, vn, &ggtt->vm.inactive_list, vm_link) | |
94d4a2a9 | 2909 | WARN_ON(i915_vma_unbind(vma)); |
1188bc66 | 2910 | |
95374d75 CW |
2911 | if (drm_mm_node_allocated(&ggtt->error_capture)) |
2912 | drm_mm_remove_node(&ggtt->error_capture); | |
2913 | ||
82ad6443 | 2914 | if (drm_mm_initialized(&ggtt->vm.mm)) { |
b02d22a3 | 2915 | intel_vgt_deballoon(dev_priv); |
82ad6443 | 2916 | i915_address_space_fini(&ggtt->vm); |
90d0a0e8 DV |
2917 | } |
2918 | ||
82ad6443 | 2919 | ggtt->vm.cleanup(&ggtt->vm); |
66df1014 CW |
2920 | |
2921 | pvec = &dev_priv->mm.wc_stash; | |
2922 | if (pvec->nr) { | |
2923 | set_pages_array_wb(pvec->pages, pvec->nr); | |
2924 | __pagevec_release(pvec); | |
2925 | } | |
2926 | ||
1188bc66 | 2927 | mutex_unlock(&dev_priv->drm.struct_mutex); |
f6b9d5ca CW |
2928 | |
2929 | arch_phys_wc_del(ggtt->mtrr); | |
73ebd503 | 2930 | io_mapping_fini(&ggtt->iomap); |
eed28903 CW |
2931 | |
2932 | i915_gem_cleanup_stolen(&dev_priv->drm); | |
90d0a0e8 | 2933 | } |
70e32544 | 2934 | |
2c642b07 | 2935 | static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2936 | { |
2937 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
2938 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
2939 | return snb_gmch_ctl << 20; | |
2940 | } | |
2941 | ||
2c642b07 | 2942 | static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
9459d252 BW |
2943 | { |
2944 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
2945 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
2946 | if (bdw_gmch_ctl) | |
2947 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
562d55d9 BW |
2948 | |
2949 | #ifdef CONFIG_X86_32 | |
2950 | /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */ | |
2951 | if (bdw_gmch_ctl > 4) | |
2952 | bdw_gmch_ctl = 4; | |
2953 | #endif | |
2954 | ||
9459d252 BW |
2955 | return bdw_gmch_ctl << 20; |
2956 | } | |
2957 | ||
2c642b07 | 2958 | static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) |
d7f25f23 DL |
2959 | { |
2960 | gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT; | |
2961 | gmch_ctrl &= SNB_GMCH_GGMS_MASK; | |
2962 | ||
2963 | if (gmch_ctrl) | |
2964 | return 1 << (20 + gmch_ctrl); | |
2965 | ||
2966 | return 0; | |
2967 | } | |
2968 | ||
34c998b4 | 2969 | static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) |
63340133 | 2970 | { |
82ad6443 | 2971 | struct drm_i915_private *dev_priv = ggtt->vm.i915; |
49d73912 | 2972 | struct pci_dev *pdev = dev_priv->drm.pdev; |
34c998b4 | 2973 | phys_addr_t phys_addr; |
8bcdd0f7 | 2974 | int ret; |
63340133 BW |
2975 | |
2976 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
34c998b4 | 2977 | phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2; |
63340133 | 2978 | |
2a073f89 | 2979 | /* |
385db982 RV |
2980 | * On BXT+/CNL+ writes larger than 64 bit to the GTT pagetable range |
2981 | * will be dropped. For WC mappings in general we have 64 byte burst | |
2982 | * writes when the WC buffer is flushed, so we can't use it, but have to | |
2a073f89 ID |
2983 | * resort to an uncached mapping. The WC issue is easily caught by the |
2984 | * readback check when writing GTT PTE entries. | |
2985 | */ | |
385db982 | 2986 | if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) |
34c998b4 | 2987 | ggtt->gsm = ioremap_nocache(phys_addr, size); |
2a073f89 | 2988 | else |
34c998b4 | 2989 | ggtt->gsm = ioremap_wc(phys_addr, size); |
72e96d64 | 2990 | if (!ggtt->gsm) { |
34c998b4 | 2991 | DRM_ERROR("Failed to map the ggtt page table\n"); |
63340133 BW |
2992 | return -ENOMEM; |
2993 | } | |
2994 | ||
82ad6443 | 2995 | ret = setup_scratch_page(&ggtt->vm, GFP_DMA32); |
8bcdd0f7 | 2996 | if (ret) { |
63340133 BW |
2997 | DRM_ERROR("Scratch setup failed\n"); |
2998 | /* iounmap will also get called at remove, but meh */ | |
72e96d64 | 2999 | iounmap(ggtt->gsm); |
8bcdd0f7 | 3000 | return ret; |
63340133 BW |
3001 | } |
3002 | ||
4ad2af1e | 3003 | return 0; |
63340133 BW |
3004 | } |
3005 | ||
4395890a ZW |
3006 | static struct intel_ppat_entry * |
3007 | __alloc_ppat_entry(struct intel_ppat *ppat, unsigned int index, u8 value) | |
4e34935f | 3008 | { |
4395890a ZW |
3009 | struct intel_ppat_entry *entry = &ppat->entries[index]; |
3010 | ||
3011 | GEM_BUG_ON(index >= ppat->max_entries); | |
3012 | GEM_BUG_ON(test_bit(index, ppat->used)); | |
3013 | ||
3014 | entry->ppat = ppat; | |
3015 | entry->value = value; | |
3016 | kref_init(&entry->ref); | |
3017 | set_bit(index, ppat->used); | |
3018 | set_bit(index, ppat->dirty); | |
3019 | ||
3020 | return entry; | |
3021 | } | |
3022 | ||
3023 | static void __free_ppat_entry(struct intel_ppat_entry *entry) | |
3024 | { | |
3025 | struct intel_ppat *ppat = entry->ppat; | |
3026 | unsigned int index = entry - ppat->entries; | |
3027 | ||
3028 | GEM_BUG_ON(index >= ppat->max_entries); | |
3029 | GEM_BUG_ON(!test_bit(index, ppat->used)); | |
3030 | ||
3031 | entry->value = ppat->clear_value; | |
3032 | clear_bit(index, ppat->used); | |
3033 | set_bit(index, ppat->dirty); | |
3034 | } | |
3035 | ||
3036 | /** | |
3037 | * intel_ppat_get - get a usable PPAT entry | |
3038 | * @i915: i915 device instance | |
3039 | * @value: the PPAT value required by the caller | |
3040 | * | |
3041 | * The function tries to search if there is an existing PPAT entry which | |
3042 | * matches with the required value. If perfectly matched, the existing PPAT | |
3043 | * entry will be used. If only partially matched, it will try to check if | |
3044 | * there is any available PPAT index. If yes, it will allocate a new PPAT | |
3045 | * index for the required entry and update the HW. If not, the partially | |
3046 | * matched entry will be used. | |
3047 | */ | |
3048 | const struct intel_ppat_entry * | |
3049 | intel_ppat_get(struct drm_i915_private *i915, u8 value) | |
3050 | { | |
3051 | struct intel_ppat *ppat = &i915->ppat; | |
4667c2d5 | 3052 | struct intel_ppat_entry *entry = NULL; |
4395890a ZW |
3053 | unsigned int scanned, best_score; |
3054 | int i; | |
3055 | ||
3056 | GEM_BUG_ON(!ppat->max_entries); | |
3057 | ||
3058 | scanned = best_score = 0; | |
3059 | for_each_set_bit(i, ppat->used, ppat->max_entries) { | |
3060 | unsigned int score; | |
3061 | ||
3062 | score = ppat->match(ppat->entries[i].value, value); | |
3063 | if (score > best_score) { | |
3064 | entry = &ppat->entries[i]; | |
3065 | if (score == INTEL_PPAT_PERFECT_MATCH) { | |
3066 | kref_get(&entry->ref); | |
3067 | return entry; | |
3068 | } | |
3069 | best_score = score; | |
3070 | } | |
3071 | scanned++; | |
3072 | } | |
3073 | ||
3074 | if (scanned == ppat->max_entries) { | |
4667c2d5 | 3075 | if (!entry) |
4395890a ZW |
3076 | return ERR_PTR(-ENOSPC); |
3077 | ||
3078 | kref_get(&entry->ref); | |
3079 | return entry; | |
3080 | } | |
3081 | ||
3082 | i = find_first_zero_bit(ppat->used, ppat->max_entries); | |
3083 | entry = __alloc_ppat_entry(ppat, i, value); | |
3084 | ppat->update_hw(i915); | |
3085 | return entry; | |
3086 | } | |
3087 | ||
3088 | static void release_ppat(struct kref *kref) | |
3089 | { | |
3090 | struct intel_ppat_entry *entry = | |
3091 | container_of(kref, struct intel_ppat_entry, ref); | |
3092 | struct drm_i915_private *i915 = entry->ppat->i915; | |
3093 | ||
3094 | __free_ppat_entry(entry); | |
3095 | entry->ppat->update_hw(i915); | |
3096 | } | |
3097 | ||
3098 | /** | |
3099 | * intel_ppat_put - put back the PPAT entry got from intel_ppat_get() | |
3100 | * @entry: an intel PPAT entry | |
3101 | * | |
3102 | * Put back the PPAT entry got from intel_ppat_get(). If the PPAT index of the | |
3103 | * entry is dynamically allocated, its reference count will be decreased. Once | |
3104 | * the reference count becomes into zero, the PPAT index becomes free again. | |
3105 | */ | |
3106 | void intel_ppat_put(const struct intel_ppat_entry *entry) | |
3107 | { | |
3108 | struct intel_ppat *ppat = entry->ppat; | |
3109 | unsigned int index = entry - ppat->entries; | |
3110 | ||
3111 | GEM_BUG_ON(!ppat->max_entries); | |
3112 | ||
3113 | kref_put(&ppat->entries[index].ref, release_ppat); | |
3114 | } | |
3115 | ||
3116 | static void cnl_private_pat_update_hw(struct drm_i915_private *dev_priv) | |
3117 | { | |
3118 | struct intel_ppat *ppat = &dev_priv->ppat; | |
3119 | int i; | |
3120 | ||
3121 | for_each_set_bit(i, ppat->dirty, ppat->max_entries) { | |
3122 | I915_WRITE(GEN10_PAT_INDEX(i), ppat->entries[i].value); | |
3123 | clear_bit(i, ppat->dirty); | |
3124 | } | |
3125 | } | |
3126 | ||
3127 | static void bdw_private_pat_update_hw(struct drm_i915_private *dev_priv) | |
3128 | { | |
3129 | struct intel_ppat *ppat = &dev_priv->ppat; | |
3130 | u64 pat = 0; | |
3131 | int i; | |
3132 | ||
3133 | for (i = 0; i < ppat->max_entries; i++) | |
3134 | pat |= GEN8_PPAT(i, ppat->entries[i].value); | |
3135 | ||
3136 | bitmap_clear(ppat->dirty, 0, ppat->max_entries); | |
3137 | ||
3138 | I915_WRITE(GEN8_PRIVATE_PAT_LO, lower_32_bits(pat)); | |
3139 | I915_WRITE(GEN8_PRIVATE_PAT_HI, upper_32_bits(pat)); | |
3140 | } | |
3141 | ||
3142 | static unsigned int bdw_private_pat_match(u8 src, u8 dst) | |
3143 | { | |
3144 | unsigned int score = 0; | |
3145 | enum { | |
3146 | AGE_MATCH = BIT(0), | |
3147 | TC_MATCH = BIT(1), | |
3148 | CA_MATCH = BIT(2), | |
3149 | }; | |
3150 | ||
3151 | /* Cache attribute has to be matched. */ | |
1298d51c | 3152 | if (GEN8_PPAT_GET_CA(src) != GEN8_PPAT_GET_CA(dst)) |
4395890a ZW |
3153 | return 0; |
3154 | ||
3155 | score |= CA_MATCH; | |
3156 | ||
3157 | if (GEN8_PPAT_GET_TC(src) == GEN8_PPAT_GET_TC(dst)) | |
3158 | score |= TC_MATCH; | |
3159 | ||
3160 | if (GEN8_PPAT_GET_AGE(src) == GEN8_PPAT_GET_AGE(dst)) | |
3161 | score |= AGE_MATCH; | |
3162 | ||
3163 | if (score == (AGE_MATCH | TC_MATCH | CA_MATCH)) | |
3164 | return INTEL_PPAT_PERFECT_MATCH; | |
3165 | ||
3166 | return score; | |
3167 | } | |
3168 | ||
3169 | static unsigned int chv_private_pat_match(u8 src, u8 dst) | |
3170 | { | |
3171 | return (CHV_PPAT_GET_SNOOP(src) == CHV_PPAT_GET_SNOOP(dst)) ? | |
3172 | INTEL_PPAT_PERFECT_MATCH : 0; | |
3173 | } | |
3174 | ||
3175 | static void cnl_setup_private_ppat(struct intel_ppat *ppat) | |
3176 | { | |
3177 | ppat->max_entries = 8; | |
3178 | ppat->update_hw = cnl_private_pat_update_hw; | |
3179 | ppat->match = bdw_private_pat_match; | |
3180 | ppat->clear_value = GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3); | |
3181 | ||
4395890a ZW |
3182 | __alloc_ppat_entry(ppat, 0, GEN8_PPAT_WB | GEN8_PPAT_LLC); |
3183 | __alloc_ppat_entry(ppat, 1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC); | |
3184 | __alloc_ppat_entry(ppat, 2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC); | |
3185 | __alloc_ppat_entry(ppat, 3, GEN8_PPAT_UC); | |
3186 | __alloc_ppat_entry(ppat, 4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)); | |
3187 | __alloc_ppat_entry(ppat, 5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)); | |
3188 | __alloc_ppat_entry(ppat, 6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)); | |
3189 | __alloc_ppat_entry(ppat, 7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
4e34935f RV |
3190 | } |
3191 | ||
fbe5d36e BW |
3192 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
3193 | * bits. When using advanced contexts each context stores its own PAT, but | |
3194 | * writing this data shouldn't be harmful even in those cases. */ | |
4395890a | 3195 | static void bdw_setup_private_ppat(struct intel_ppat *ppat) |
fbe5d36e | 3196 | { |
4395890a ZW |
3197 | ppat->max_entries = 8; |
3198 | ppat->update_hw = bdw_private_pat_update_hw; | |
3199 | ppat->match = bdw_private_pat_match; | |
3200 | ppat->clear_value = GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3); | |
fbe5d36e | 3201 | |
4395890a | 3202 | if (!USES_PPGTT(ppat->i915)) { |
d6a8b72e RV |
3203 | /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry, |
3204 | * so RTL will always use the value corresponding to | |
3205 | * pat_sel = 000". | |
3206 | * So let's disable cache for GGTT to avoid screen corruptions. | |
3207 | * MOCS still can be used though. | |
3208 | * - System agent ggtt writes (i.e. cpu gtt mmaps) already work | |
3209 | * before this patch, i.e. the same uncached + snooping access | |
3210 | * like on gen6/7 seems to be in effect. | |
3211 | * - So this just fixes blitter/render access. Again it looks | |
3212 | * like it's not just uncached access, but uncached + snooping. | |
3213 | * So we can still hold onto all our assumptions wrt cpu | |
3214 | * clflushing on LLC machines. | |
3215 | */ | |
4395890a ZW |
3216 | __alloc_ppat_entry(ppat, 0, GEN8_PPAT_UC); |
3217 | return; | |
3218 | } | |
d6a8b72e | 3219 | |
4395890a ZW |
3220 | __alloc_ppat_entry(ppat, 0, GEN8_PPAT_WB | GEN8_PPAT_LLC); /* for normal objects, no eLLC */ |
3221 | __alloc_ppat_entry(ppat, 1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC); /* for something pointing to ptes? */ | |
3222 | __alloc_ppat_entry(ppat, 2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC); /* for scanout with eLLC */ | |
3223 | __alloc_ppat_entry(ppat, 3, GEN8_PPAT_UC); /* Uncached objects, mostly for scanout */ | |
3224 | __alloc_ppat_entry(ppat, 4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)); | |
3225 | __alloc_ppat_entry(ppat, 5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)); | |
3226 | __alloc_ppat_entry(ppat, 6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)); | |
3227 | __alloc_ppat_entry(ppat, 7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
fbe5d36e BW |
3228 | } |
3229 | ||
4395890a | 3230 | static void chv_setup_private_ppat(struct intel_ppat *ppat) |
ee0ce478 | 3231 | { |
4395890a ZW |
3232 | ppat->max_entries = 8; |
3233 | ppat->update_hw = bdw_private_pat_update_hw; | |
3234 | ppat->match = chv_private_pat_match; | |
3235 | ppat->clear_value = CHV_PPAT_SNOOP; | |
ee0ce478 VS |
3236 | |
3237 | /* | |
3238 | * Map WB on BDW to snooped on CHV. | |
3239 | * | |
3240 | * Only the snoop bit has meaning for CHV, the rest is | |
3241 | * ignored. | |
3242 | * | |
cf3d262e VS |
3243 | * The hardware will never snoop for certain types of accesses: |
3244 | * - CPU GTT (GMADR->GGTT->no snoop->memory) | |
3245 | * - PPGTT page tables | |
3246 | * - some other special cycles | |
3247 | * | |
3248 | * As with BDW, we also need to consider the following for GT accesses: | |
3249 | * "For GGTT, there is NO pat_sel[2:0] from the entry, | |
3250 | * so RTL will always use the value corresponding to | |
3251 | * pat_sel = 000". | |
3252 | * Which means we must set the snoop bit in PAT entry 0 | |
3253 | * in order to keep the global status page working. | |
ee0ce478 | 3254 | */ |
ee0ce478 | 3255 | |
4395890a ZW |
3256 | __alloc_ppat_entry(ppat, 0, CHV_PPAT_SNOOP); |
3257 | __alloc_ppat_entry(ppat, 1, 0); | |
3258 | __alloc_ppat_entry(ppat, 2, 0); | |
3259 | __alloc_ppat_entry(ppat, 3, 0); | |
3260 | __alloc_ppat_entry(ppat, 4, CHV_PPAT_SNOOP); | |
3261 | __alloc_ppat_entry(ppat, 5, CHV_PPAT_SNOOP); | |
3262 | __alloc_ppat_entry(ppat, 6, CHV_PPAT_SNOOP); | |
3263 | __alloc_ppat_entry(ppat, 7, CHV_PPAT_SNOOP); | |
ee0ce478 VS |
3264 | } |
3265 | ||
34c998b4 CW |
3266 | static void gen6_gmch_remove(struct i915_address_space *vm) |
3267 | { | |
3268 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); | |
3269 | ||
3270 | iounmap(ggtt->gsm); | |
8448661d | 3271 | cleanup_scratch_page(vm); |
34c998b4 CW |
3272 | } |
3273 | ||
36e16c49 ZW |
3274 | static void setup_private_pat(struct drm_i915_private *dev_priv) |
3275 | { | |
4395890a ZW |
3276 | struct intel_ppat *ppat = &dev_priv->ppat; |
3277 | int i; | |
3278 | ||
3279 | ppat->i915 = dev_priv; | |
3280 | ||
36e16c49 | 3281 | if (INTEL_GEN(dev_priv) >= 10) |
4395890a | 3282 | cnl_setup_private_ppat(ppat); |
36e16c49 | 3283 | else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv)) |
4395890a | 3284 | chv_setup_private_ppat(ppat); |
36e16c49 | 3285 | else |
4395890a ZW |
3286 | bdw_setup_private_ppat(ppat); |
3287 | ||
3288 | GEM_BUG_ON(ppat->max_entries > INTEL_MAX_PPAT_ENTRIES); | |
3289 | ||
3290 | for_each_clear_bit(i, ppat->used, ppat->max_entries) { | |
3291 | ppat->entries[i].value = ppat->clear_value; | |
3292 | ppat->entries[i].ppat = ppat; | |
3293 | set_bit(i, ppat->dirty); | |
3294 | } | |
3295 | ||
3296 | ppat->update_hw(dev_priv); | |
36e16c49 ZW |
3297 | } |
3298 | ||
d507d735 | 3299 | static int gen8_gmch_probe(struct i915_ggtt *ggtt) |
63340133 | 3300 | { |
82ad6443 | 3301 | struct drm_i915_private *dev_priv = ggtt->vm.i915; |
97d6d7ab | 3302 | struct pci_dev *pdev = dev_priv->drm.pdev; |
34c998b4 | 3303 | unsigned int size; |
63340133 | 3304 | u16 snb_gmch_ctl; |
4519290a | 3305 | int err; |
63340133 BW |
3306 | |
3307 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
73ebd503 MA |
3308 | ggtt->gmadr = |
3309 | (struct resource) DEFINE_RES_MEM(pci_resource_start(pdev, 2), | |
3310 | pci_resource_len(pdev, 2)); | |
3311 | ggtt->mappable_end = resource_size(&ggtt->gmadr); | |
63340133 | 3312 | |
4519290a ID |
3313 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(39)); |
3314 | if (!err) | |
3315 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(39)); | |
3316 | if (err) | |
3317 | DRM_ERROR("Can't set DMA mask/consistent mask (%d)\n", err); | |
63340133 | 3318 | |
97d6d7ab | 3319 | pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
c258f91d | 3320 | if (IS_CHERRYVIEW(dev_priv)) |
34c998b4 | 3321 | size = chv_get_total_gtt_size(snb_gmch_ctl); |
c258f91d | 3322 | else |
34c998b4 | 3323 | size = gen8_get_total_gtt_size(snb_gmch_ctl); |
63340133 | 3324 | |
82ad6443 CW |
3325 | ggtt->vm.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT; |
3326 | ggtt->vm.cleanup = gen6_gmch_remove; | |
82ad6443 CW |
3327 | ggtt->vm.insert_page = gen8_ggtt_insert_page; |
3328 | ggtt->vm.clear_range = nop_clear_range; | |
48f112fe | 3329 | if (!USES_FULL_PPGTT(dev_priv) || intel_scanout_needs_vtd_wa(dev_priv)) |
82ad6443 | 3330 | ggtt->vm.clear_range = gen8_ggtt_clear_range; |
f7770bfd | 3331 | |
82ad6443 | 3332 | ggtt->vm.insert_entries = gen8_ggtt_insert_entries; |
f7770bfd | 3333 | |
0ef34ad6 JB |
3334 | /* Serialize GTT updates with aperture access on BXT if VT-d is on. */ |
3335 | if (intel_ggtt_update_needs_vtd_wa(dev_priv)) { | |
82ad6443 CW |
3336 | ggtt->vm.insert_entries = bxt_vtd_ggtt_insert_entries__BKL; |
3337 | ggtt->vm.insert_page = bxt_vtd_ggtt_insert_page__BKL; | |
3338 | if (ggtt->vm.clear_range != nop_clear_range) | |
3339 | ggtt->vm.clear_range = bxt_vtd_ggtt_clear_range__BKL; | |
0ef34ad6 JB |
3340 | } |
3341 | ||
7c3f86b6 CW |
3342 | ggtt->invalidate = gen6_ggtt_invalidate; |
3343 | ||
93f2cde2 CW |
3344 | ggtt->vm.vma_ops.bind_vma = ggtt_bind_vma; |
3345 | ggtt->vm.vma_ops.unbind_vma = ggtt_unbind_vma; | |
3346 | ggtt->vm.vma_ops.set_pages = ggtt_set_pages; | |
3347 | ggtt->vm.vma_ops.clear_pages = clear_pages; | |
3348 | ||
36e16c49 ZW |
3349 | setup_private_pat(dev_priv); |
3350 | ||
34c998b4 | 3351 | return ggtt_probe_common(ggtt, size); |
63340133 BW |
3352 | } |
3353 | ||
d507d735 | 3354 | static int gen6_gmch_probe(struct i915_ggtt *ggtt) |
e76e9aeb | 3355 | { |
82ad6443 | 3356 | struct drm_i915_private *dev_priv = ggtt->vm.i915; |
97d6d7ab | 3357 | struct pci_dev *pdev = dev_priv->drm.pdev; |
34c998b4 | 3358 | unsigned int size; |
e76e9aeb | 3359 | u16 snb_gmch_ctl; |
4519290a | 3360 | int err; |
e76e9aeb | 3361 | |
73ebd503 MA |
3362 | ggtt->gmadr = |
3363 | (struct resource) DEFINE_RES_MEM(pci_resource_start(pdev, 2), | |
3364 | pci_resource_len(pdev, 2)); | |
3365 | ggtt->mappable_end = resource_size(&ggtt->gmadr); | |
41907ddc | 3366 | |
baa09f5f BW |
3367 | /* 64/512MB is the current min/max we actually know of, but this is just |
3368 | * a coarse sanity check. | |
e76e9aeb | 3369 | */ |
34c998b4 | 3370 | if (ggtt->mappable_end < (64<<20) || ggtt->mappable_end > (512<<20)) { |
b7128ef1 | 3371 | DRM_ERROR("Unknown GMADR size (%pa)\n", &ggtt->mappable_end); |
baa09f5f | 3372 | return -ENXIO; |
e76e9aeb BW |
3373 | } |
3374 | ||
4519290a ID |
3375 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(40)); |
3376 | if (!err) | |
3377 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)); | |
3378 | if (err) | |
3379 | DRM_ERROR("Can't set DMA mask/consistent mask (%d)\n", err); | |
97d6d7ab | 3380 | pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
e76e9aeb | 3381 | |
34c998b4 | 3382 | size = gen6_get_total_gtt_size(snb_gmch_ctl); |
82ad6443 | 3383 | ggtt->vm.total = (size / sizeof(gen6_pte_t)) << PAGE_SHIFT; |
e76e9aeb | 3384 | |
82ad6443 CW |
3385 | ggtt->vm.clear_range = gen6_ggtt_clear_range; |
3386 | ggtt->vm.insert_page = gen6_ggtt_insert_page; | |
3387 | ggtt->vm.insert_entries = gen6_ggtt_insert_entries; | |
82ad6443 | 3388 | ggtt->vm.cleanup = gen6_gmch_remove; |
34c998b4 | 3389 | |
7c3f86b6 CW |
3390 | ggtt->invalidate = gen6_ggtt_invalidate; |
3391 | ||
34c998b4 | 3392 | if (HAS_EDRAM(dev_priv)) |
82ad6443 | 3393 | ggtt->vm.pte_encode = iris_pte_encode; |
34c998b4 | 3394 | else if (IS_HASWELL(dev_priv)) |
82ad6443 | 3395 | ggtt->vm.pte_encode = hsw_pte_encode; |
34c998b4 | 3396 | else if (IS_VALLEYVIEW(dev_priv)) |
82ad6443 | 3397 | ggtt->vm.pte_encode = byt_pte_encode; |
34c998b4 | 3398 | else if (INTEL_GEN(dev_priv) >= 7) |
82ad6443 | 3399 | ggtt->vm.pte_encode = ivb_pte_encode; |
34c998b4 | 3400 | else |
82ad6443 | 3401 | ggtt->vm.pte_encode = snb_pte_encode; |
7faf1ab2 | 3402 | |
93f2cde2 CW |
3403 | ggtt->vm.vma_ops.bind_vma = ggtt_bind_vma; |
3404 | ggtt->vm.vma_ops.unbind_vma = ggtt_unbind_vma; | |
3405 | ggtt->vm.vma_ops.set_pages = ggtt_set_pages; | |
3406 | ggtt->vm.vma_ops.clear_pages = clear_pages; | |
3407 | ||
34c998b4 | 3408 | return ggtt_probe_common(ggtt, size); |
e76e9aeb BW |
3409 | } |
3410 | ||
34c998b4 | 3411 | static void i915_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 3412 | { |
34c998b4 | 3413 | intel_gmch_remove(); |
644ec02b | 3414 | } |
baa09f5f | 3415 | |
d507d735 | 3416 | static int i915_gmch_probe(struct i915_ggtt *ggtt) |
baa09f5f | 3417 | { |
82ad6443 | 3418 | struct drm_i915_private *dev_priv = ggtt->vm.i915; |
73ebd503 | 3419 | phys_addr_t gmadr_base; |
baa09f5f BW |
3420 | int ret; |
3421 | ||
91c8a326 | 3422 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->drm.pdev, NULL); |
baa09f5f BW |
3423 | if (!ret) { |
3424 | DRM_ERROR("failed to set up gmch\n"); | |
3425 | return -EIO; | |
3426 | } | |
3427 | ||
82ad6443 | 3428 | intel_gtt_get(&ggtt->vm.total, &gmadr_base, &ggtt->mappable_end); |
baa09f5f | 3429 | |
73ebd503 MA |
3430 | ggtt->gmadr = |
3431 | (struct resource) DEFINE_RES_MEM(gmadr_base, | |
3432 | ggtt->mappable_end); | |
3433 | ||
97d6d7ab | 3434 | ggtt->do_idle_maps = needs_idle_maps(dev_priv); |
82ad6443 CW |
3435 | ggtt->vm.insert_page = i915_ggtt_insert_page; |
3436 | ggtt->vm.insert_entries = i915_ggtt_insert_entries; | |
3437 | ggtt->vm.clear_range = i915_ggtt_clear_range; | |
82ad6443 | 3438 | ggtt->vm.cleanup = i915_gmch_remove; |
baa09f5f | 3439 | |
7c3f86b6 CW |
3440 | ggtt->invalidate = gmch_ggtt_invalidate; |
3441 | ||
93f2cde2 CW |
3442 | ggtt->vm.vma_ops.bind_vma = ggtt_bind_vma; |
3443 | ggtt->vm.vma_ops.unbind_vma = ggtt_unbind_vma; | |
3444 | ggtt->vm.vma_ops.set_pages = ggtt_set_pages; | |
3445 | ggtt->vm.vma_ops.clear_pages = clear_pages; | |
3446 | ||
d507d735 | 3447 | if (unlikely(ggtt->do_idle_maps)) |
c0a7f818 CW |
3448 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); |
3449 | ||
baa09f5f BW |
3450 | return 0; |
3451 | } | |
3452 | ||
d85489d3 | 3453 | /** |
0088e522 | 3454 | * i915_ggtt_probe_hw - Probe GGTT hardware location |
97d6d7ab | 3455 | * @dev_priv: i915 device |
d85489d3 | 3456 | */ |
97d6d7ab | 3457 | int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv) |
baa09f5f | 3458 | { |
62106b4f | 3459 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
baa09f5f BW |
3460 | int ret; |
3461 | ||
82ad6443 CW |
3462 | ggtt->vm.i915 = dev_priv; |
3463 | ggtt->vm.dma = &dev_priv->drm.pdev->dev; | |
c114f76a | 3464 | |
34c998b4 CW |
3465 | if (INTEL_GEN(dev_priv) <= 5) |
3466 | ret = i915_gmch_probe(ggtt); | |
3467 | else if (INTEL_GEN(dev_priv) < 8) | |
3468 | ret = gen6_gmch_probe(ggtt); | |
3469 | else | |
3470 | ret = gen8_gmch_probe(ggtt); | |
a54c0c27 | 3471 | if (ret) |
baa09f5f | 3472 | return ret; |
baa09f5f | 3473 | |
db9309a5 CW |
3474 | /* Trim the GGTT to fit the GuC mappable upper range (when enabled). |
3475 | * This is easier than doing range restriction on the fly, as we | |
3476 | * currently don't have any bits spare to pass in this upper | |
3477 | * restriction! | |
3478 | */ | |
93ffbe8e | 3479 | if (USES_GUC(dev_priv)) { |
82ad6443 CW |
3480 | ggtt->vm.total = min_t(u64, ggtt->vm.total, GUC_GGTT_TOP); |
3481 | ggtt->mappable_end = | |
3482 | min_t(u64, ggtt->mappable_end, ggtt->vm.total); | |
db9309a5 CW |
3483 | } |
3484 | ||
82ad6443 | 3485 | if ((ggtt->vm.total - 1) >> 32) { |
c890e2d5 | 3486 | DRM_ERROR("We never expected a Global GTT with more than 32bits" |
f6b9d5ca | 3487 | " of address space! Found %lldM!\n", |
82ad6443 CW |
3488 | ggtt->vm.total >> 20); |
3489 | ggtt->vm.total = 1ULL << 32; | |
3490 | ggtt->mappable_end = | |
3491 | min_t(u64, ggtt->mappable_end, ggtt->vm.total); | |
c890e2d5 CW |
3492 | } |
3493 | ||
82ad6443 | 3494 | if (ggtt->mappable_end > ggtt->vm.total) { |
f6b9d5ca | 3495 | DRM_ERROR("mappable aperture extends past end of GGTT," |
b7128ef1 | 3496 | " aperture=%pa, total=%llx\n", |
82ad6443 CW |
3497 | &ggtt->mappable_end, ggtt->vm.total); |
3498 | ggtt->mappable_end = ggtt->vm.total; | |
f6b9d5ca CW |
3499 | } |
3500 | ||
baa09f5f | 3501 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
82ad6443 | 3502 | DRM_DEBUG_DRIVER("GGTT size = %lluM\n", ggtt->vm.total >> 20); |
73ebd503 | 3503 | DRM_DEBUG_DRIVER("GMADR size = %lluM\n", (u64)ggtt->mappable_end >> 20); |
1875fe7b | 3504 | DRM_DEBUG_DRIVER("DSM size = %lluM\n", |
77894226 | 3505 | (u64)resource_size(&intel_graphics_stolen_res) >> 20); |
80debff8 | 3506 | if (intel_vtd_active()) |
5db6c735 | 3507 | DRM_INFO("VT-d active for gfx access\n"); |
baa09f5f BW |
3508 | |
3509 | return 0; | |
0088e522 CW |
3510 | } |
3511 | ||
3512 | /** | |
3513 | * i915_ggtt_init_hw - Initialize GGTT hardware | |
97d6d7ab | 3514 | * @dev_priv: i915 device |
0088e522 | 3515 | */ |
97d6d7ab | 3516 | int i915_ggtt_init_hw(struct drm_i915_private *dev_priv) |
0088e522 | 3517 | { |
0088e522 CW |
3518 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
3519 | int ret; | |
3520 | ||
f6b9d5ca CW |
3521 | INIT_LIST_HEAD(&dev_priv->vm_list); |
3522 | ||
a6508ded CW |
3523 | /* Note that we use page colouring to enforce a guard page at the |
3524 | * end of the address space. This is required as the CS may prefetch | |
3525 | * beyond the end of the batch buffer, across the page boundary, | |
3526 | * and beyond the end of the GTT if we do not provide a guard. | |
f6b9d5ca | 3527 | */ |
80b204bc | 3528 | mutex_lock(&dev_priv->drm.struct_mutex); |
82ad6443 | 3529 | i915_address_space_init(&ggtt->vm, dev_priv, "[global]"); |
a6508ded | 3530 | if (!HAS_LLC(dev_priv) && !USES_PPGTT(dev_priv)) |
82ad6443 | 3531 | ggtt->vm.mm.color_adjust = i915_gtt_color_adjust; |
80b204bc | 3532 | mutex_unlock(&dev_priv->drm.struct_mutex); |
f6b9d5ca | 3533 | |
73ebd503 MA |
3534 | if (!io_mapping_init_wc(&dev_priv->ggtt.iomap, |
3535 | dev_priv->ggtt.gmadr.start, | |
f7bbe788 | 3536 | dev_priv->ggtt.mappable_end)) { |
f6b9d5ca CW |
3537 | ret = -EIO; |
3538 | goto out_gtt_cleanup; | |
3539 | } | |
3540 | ||
73ebd503 | 3541 | ggtt->mtrr = arch_phys_wc_add(ggtt->gmadr.start, ggtt->mappable_end); |
f6b9d5ca | 3542 | |
0088e522 CW |
3543 | /* |
3544 | * Initialise stolen early so that we may reserve preallocated | |
3545 | * objects for the BIOS to KMS transition. | |
3546 | */ | |
7ace3d30 | 3547 | ret = i915_gem_init_stolen(dev_priv); |
0088e522 CW |
3548 | if (ret) |
3549 | goto out_gtt_cleanup; | |
3550 | ||
3551 | return 0; | |
a4eba47b ID |
3552 | |
3553 | out_gtt_cleanup: | |
82ad6443 | 3554 | ggtt->vm.cleanup(&ggtt->vm); |
a4eba47b | 3555 | return ret; |
baa09f5f | 3556 | } |
6f65e29a | 3557 | |
97d6d7ab | 3558 | int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv) |
ac840ae5 | 3559 | { |
97d6d7ab | 3560 | if (INTEL_GEN(dev_priv) < 6 && !intel_enable_gtt()) |
ac840ae5 VS |
3561 | return -EIO; |
3562 | ||
3563 | return 0; | |
3564 | } | |
3565 | ||
7c3f86b6 CW |
3566 | void i915_ggtt_enable_guc(struct drm_i915_private *i915) |
3567 | { | |
04f7b24e CW |
3568 | GEM_BUG_ON(i915->ggtt.invalidate != gen6_ggtt_invalidate); |
3569 | ||
7c3f86b6 | 3570 | i915->ggtt.invalidate = guc_ggtt_invalidate; |
aeb950bd MW |
3571 | |
3572 | i915_ggtt_invalidate(i915); | |
7c3f86b6 CW |
3573 | } |
3574 | ||
3575 | void i915_ggtt_disable_guc(struct drm_i915_private *i915) | |
3576 | { | |
04f7b24e CW |
3577 | /* We should only be called after i915_ggtt_enable_guc() */ |
3578 | GEM_BUG_ON(i915->ggtt.invalidate != guc_ggtt_invalidate); | |
3579 | ||
3580 | i915->ggtt.invalidate = gen6_ggtt_invalidate; | |
aeb950bd MW |
3581 | |
3582 | i915_ggtt_invalidate(i915); | |
7c3f86b6 CW |
3583 | } |
3584 | ||
275a991c | 3585 | void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv) |
fa42331b | 3586 | { |
72e96d64 | 3587 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
74479985 | 3588 | struct i915_vma *vma, *vn; |
fa42331b | 3589 | |
dc97997a | 3590 | i915_check_and_clear_faults(dev_priv); |
fa42331b DV |
3591 | |
3592 | /* First fill our portion of the GTT with scratch pages */ | |
82ad6443 | 3593 | ggtt->vm.clear_range(&ggtt->vm, 0, ggtt->vm.total); |
fa42331b | 3594 | |
82ad6443 | 3595 | ggtt->vm.closed = true; /* skip rewriting PTE on VMA unbind */ |
fbb30a5c CW |
3596 | |
3597 | /* clflush objects bound into the GGTT and rebind them. */ | |
82ad6443 CW |
3598 | GEM_BUG_ON(!list_empty(&ggtt->vm.active_list)); |
3599 | list_for_each_entry_safe(vma, vn, &ggtt->vm.inactive_list, vm_link) { | |
74479985 | 3600 | struct drm_i915_gem_object *obj = vma->obj; |
fbb30a5c | 3601 | |
74479985 CW |
3602 | if (!(vma->flags & I915_VMA_GLOBAL_BIND)) |
3603 | continue; | |
fbb30a5c | 3604 | |
74479985 CW |
3605 | if (!i915_vma_unbind(vma)) |
3606 | continue; | |
2c3d9984 | 3607 | |
520ea7c5 CW |
3608 | WARN_ON(i915_vma_bind(vma, |
3609 | obj ? obj->cache_level : 0, | |
3610 | PIN_UPDATE)); | |
3611 | if (obj) | |
3612 | WARN_ON(i915_gem_object_set_to_gtt_domain(obj, false)); | |
2c3d9984 | 3613 | } |
fa42331b | 3614 | |
82ad6443 | 3615 | ggtt->vm.closed = false; |
e9e7dc41 | 3616 | i915_ggtt_invalidate(dev_priv); |
fbb30a5c | 3617 | |
275a991c | 3618 | if (INTEL_GEN(dev_priv) >= 8) { |
4395890a | 3619 | struct intel_ppat *ppat = &dev_priv->ppat; |
fa42331b | 3620 | |
4395890a ZW |
3621 | bitmap_set(ppat->dirty, 0, ppat->max_entries); |
3622 | dev_priv->ppat.update_hw(dev_priv); | |
fa42331b DV |
3623 | return; |
3624 | } | |
fa42331b DV |
3625 | } |
3626 | ||
804beb4b | 3627 | static struct scatterlist * |
2d7f3bdb | 3628 | rotate_pages(const dma_addr_t *in, unsigned int offset, |
804beb4b | 3629 | unsigned int width, unsigned int height, |
87130255 | 3630 | unsigned int stride, |
804beb4b | 3631 | struct sg_table *st, struct scatterlist *sg) |
50470bb0 TU |
3632 | { |
3633 | unsigned int column, row; | |
3634 | unsigned int src_idx; | |
50470bb0 | 3635 | |
50470bb0 | 3636 | for (column = 0; column < width; column++) { |
87130255 | 3637 | src_idx = stride * (height - 1) + column; |
50470bb0 TU |
3638 | for (row = 0; row < height; row++) { |
3639 | st->nents++; | |
3640 | /* We don't need the pages, but need to initialize | |
3641 | * the entries so the sg list can be happily traversed. | |
3642 | * The only thing we need are DMA addresses. | |
3643 | */ | |
3644 | sg_set_page(sg, NULL, PAGE_SIZE, 0); | |
804beb4b | 3645 | sg_dma_address(sg) = in[offset + src_idx]; |
50470bb0 TU |
3646 | sg_dma_len(sg) = PAGE_SIZE; |
3647 | sg = sg_next(sg); | |
87130255 | 3648 | src_idx -= stride; |
50470bb0 TU |
3649 | } |
3650 | } | |
804beb4b TU |
3651 | |
3652 | return sg; | |
50470bb0 TU |
3653 | } |
3654 | ||
ba7a5741 CW |
3655 | static noinline struct sg_table * |
3656 | intel_rotate_pages(struct intel_rotation_info *rot_info, | |
3657 | struct drm_i915_gem_object *obj) | |
50470bb0 | 3658 | { |
75c7b0b8 | 3659 | const unsigned long n_pages = obj->base.size / PAGE_SIZE; |
6687c906 | 3660 | unsigned int size = intel_rotation_info_size(rot_info); |
85d1225e DG |
3661 | struct sgt_iter sgt_iter; |
3662 | dma_addr_t dma_addr; | |
50470bb0 TU |
3663 | unsigned long i; |
3664 | dma_addr_t *page_addr_list; | |
3665 | struct sg_table *st; | |
89e3e142 | 3666 | struct scatterlist *sg; |
1d00dad5 | 3667 | int ret = -ENOMEM; |
50470bb0 | 3668 | |
50470bb0 | 3669 | /* Allocate a temporary list of source pages for random access. */ |
2098105e | 3670 | page_addr_list = kvmalloc_array(n_pages, |
f2a85e19 | 3671 | sizeof(dma_addr_t), |
0ee931c4 | 3672 | GFP_KERNEL); |
50470bb0 TU |
3673 | if (!page_addr_list) |
3674 | return ERR_PTR(ret); | |
3675 | ||
3676 | /* Allocate target SG list. */ | |
3677 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
3678 | if (!st) | |
3679 | goto err_st_alloc; | |
3680 | ||
6687c906 | 3681 | ret = sg_alloc_table(st, size, GFP_KERNEL); |
50470bb0 TU |
3682 | if (ret) |
3683 | goto err_sg_alloc; | |
3684 | ||
3685 | /* Populate source page list from the object. */ | |
3686 | i = 0; | |
a4f5ea64 | 3687 | for_each_sgt_dma(dma_addr, sgt_iter, obj->mm.pages) |
85d1225e | 3688 | page_addr_list[i++] = dma_addr; |
50470bb0 | 3689 | |
85d1225e | 3690 | GEM_BUG_ON(i != n_pages); |
11f20322 VS |
3691 | st->nents = 0; |
3692 | sg = st->sgl; | |
3693 | ||
6687c906 VS |
3694 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) { |
3695 | sg = rotate_pages(page_addr_list, rot_info->plane[i].offset, | |
3696 | rot_info->plane[i].width, rot_info->plane[i].height, | |
3697 | rot_info->plane[i].stride, st, sg); | |
89e3e142 TU |
3698 | } |
3699 | ||
2098105e | 3700 | kvfree(page_addr_list); |
50470bb0 TU |
3701 | |
3702 | return st; | |
3703 | ||
3704 | err_sg_alloc: | |
3705 | kfree(st); | |
3706 | err_st_alloc: | |
2098105e | 3707 | kvfree(page_addr_list); |
50470bb0 | 3708 | |
62d0fe45 CW |
3709 | DRM_DEBUG_DRIVER("Failed to create rotated mapping for object size %zu! (%ux%u tiles, %u pages)\n", |
3710 | obj->base.size, rot_info->plane[0].width, rot_info->plane[0].height, size); | |
6687c906 | 3711 | |
50470bb0 TU |
3712 | return ERR_PTR(ret); |
3713 | } | |
ec7adb6e | 3714 | |
ba7a5741 | 3715 | static noinline struct sg_table * |
8bd7ef16 JL |
3716 | intel_partial_pages(const struct i915_ggtt_view *view, |
3717 | struct drm_i915_gem_object *obj) | |
3718 | { | |
3719 | struct sg_table *st; | |
d2a84a76 | 3720 | struct scatterlist *sg, *iter; |
8bab1193 | 3721 | unsigned int count = view->partial.size; |
d2a84a76 | 3722 | unsigned int offset; |
8bd7ef16 JL |
3723 | int ret = -ENOMEM; |
3724 | ||
3725 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
3726 | if (!st) | |
3727 | goto err_st_alloc; | |
3728 | ||
d2a84a76 | 3729 | ret = sg_alloc_table(st, count, GFP_KERNEL); |
8bd7ef16 JL |
3730 | if (ret) |
3731 | goto err_sg_alloc; | |
3732 | ||
8bab1193 | 3733 | iter = i915_gem_object_get_sg(obj, view->partial.offset, &offset); |
d2a84a76 CW |
3734 | GEM_BUG_ON(!iter); |
3735 | ||
8bd7ef16 JL |
3736 | sg = st->sgl; |
3737 | st->nents = 0; | |
d2a84a76 CW |
3738 | do { |
3739 | unsigned int len; | |
8bd7ef16 | 3740 | |
d2a84a76 CW |
3741 | len = min(iter->length - (offset << PAGE_SHIFT), |
3742 | count << PAGE_SHIFT); | |
3743 | sg_set_page(sg, NULL, len, 0); | |
3744 | sg_dma_address(sg) = | |
3745 | sg_dma_address(iter) + (offset << PAGE_SHIFT); | |
3746 | sg_dma_len(sg) = len; | |
8bd7ef16 | 3747 | |
8bd7ef16 | 3748 | st->nents++; |
d2a84a76 CW |
3749 | count -= len >> PAGE_SHIFT; |
3750 | if (count == 0) { | |
3751 | sg_mark_end(sg); | |
3752 | return st; | |
3753 | } | |
8bd7ef16 | 3754 | |
d2a84a76 CW |
3755 | sg = __sg_next(sg); |
3756 | iter = __sg_next(iter); | |
3757 | offset = 0; | |
3758 | } while (1); | |
8bd7ef16 JL |
3759 | |
3760 | err_sg_alloc: | |
3761 | kfree(st); | |
3762 | err_st_alloc: | |
3763 | return ERR_PTR(ret); | |
3764 | } | |
3765 | ||
70b9f6f8 | 3766 | static int |
50470bb0 | 3767 | i915_get_ggtt_vma_pages(struct i915_vma *vma) |
fe14d5f4 | 3768 | { |
ba7a5741 | 3769 | int ret; |
50470bb0 | 3770 | |
2c3a3f44 CW |
3771 | /* The vma->pages are only valid within the lifespan of the borrowed |
3772 | * obj->mm.pages. When the obj->mm.pages sg_table is regenerated, so | |
3773 | * must be the vma->pages. A simple rule is that vma->pages must only | |
3774 | * be accessed when the obj->mm.pages are pinned. | |
3775 | */ | |
3776 | GEM_BUG_ON(!i915_gem_object_has_pinned_pages(vma->obj)); | |
3777 | ||
ba7a5741 | 3778 | switch (vma->ggtt_view.type) { |
62d4028f CW |
3779 | default: |
3780 | GEM_BUG_ON(vma->ggtt_view.type); | |
3781 | /* fall through */ | |
ba7a5741 CW |
3782 | case I915_GGTT_VIEW_NORMAL: |
3783 | vma->pages = vma->obj->mm.pages; | |
fe14d5f4 TU |
3784 | return 0; |
3785 | ||
ba7a5741 | 3786 | case I915_GGTT_VIEW_ROTATED: |
247177dd | 3787 | vma->pages = |
ba7a5741 CW |
3788 | intel_rotate_pages(&vma->ggtt_view.rotated, vma->obj); |
3789 | break; | |
3790 | ||
3791 | case I915_GGTT_VIEW_PARTIAL: | |
247177dd | 3792 | vma->pages = intel_partial_pages(&vma->ggtt_view, vma->obj); |
ba7a5741 | 3793 | break; |
ba7a5741 | 3794 | } |
fe14d5f4 | 3795 | |
ba7a5741 CW |
3796 | ret = 0; |
3797 | if (unlikely(IS_ERR(vma->pages))) { | |
247177dd CW |
3798 | ret = PTR_ERR(vma->pages); |
3799 | vma->pages = NULL; | |
50470bb0 TU |
3800 | DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n", |
3801 | vma->ggtt_view.type, ret); | |
fe14d5f4 | 3802 | } |
50470bb0 | 3803 | return ret; |
fe14d5f4 TU |
3804 | } |
3805 | ||
625d988a CW |
3806 | /** |
3807 | * i915_gem_gtt_reserve - reserve a node in an address_space (GTT) | |
a4dbf7cf CW |
3808 | * @vm: the &struct i915_address_space |
3809 | * @node: the &struct drm_mm_node (typically i915_vma.mode) | |
3810 | * @size: how much space to allocate inside the GTT, | |
3811 | * must be #I915_GTT_PAGE_SIZE aligned | |
3812 | * @offset: where to insert inside the GTT, | |
3813 | * must be #I915_GTT_MIN_ALIGNMENT aligned, and the node | |
3814 | * (@offset + @size) must fit within the address space | |
3815 | * @color: color to apply to node, if this node is not from a VMA, | |
3816 | * color must be #I915_COLOR_UNEVICTABLE | |
3817 | * @flags: control search and eviction behaviour | |
625d988a CW |
3818 | * |
3819 | * i915_gem_gtt_reserve() tries to insert the @node at the exact @offset inside | |
3820 | * the address space (using @size and @color). If the @node does not fit, it | |
3821 | * tries to evict any overlapping nodes from the GTT, including any | |
3822 | * neighbouring nodes if the colors do not match (to ensure guard pages between | |
3823 | * differing domains). See i915_gem_evict_for_node() for the gory details | |
3824 | * on the eviction algorithm. #PIN_NONBLOCK may used to prevent waiting on | |
3825 | * evicting active overlapping objects, and any overlapping node that is pinned | |
3826 | * or marked as unevictable will also result in failure. | |
3827 | * | |
3828 | * Returns: 0 on success, -ENOSPC if no suitable hole is found, -EINTR if | |
3829 | * asked to wait for eviction and interrupted. | |
3830 | */ | |
3831 | int i915_gem_gtt_reserve(struct i915_address_space *vm, | |
3832 | struct drm_mm_node *node, | |
3833 | u64 size, u64 offset, unsigned long color, | |
3834 | unsigned int flags) | |
3835 | { | |
3836 | int err; | |
3837 | ||
3838 | GEM_BUG_ON(!size); | |
3839 | GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE)); | |
3840 | GEM_BUG_ON(!IS_ALIGNED(offset, I915_GTT_MIN_ALIGNMENT)); | |
3841 | GEM_BUG_ON(range_overflows(offset, size, vm->total)); | |
82ad6443 | 3842 | GEM_BUG_ON(vm == &vm->i915->mm.aliasing_ppgtt->vm); |
9734ad13 | 3843 | GEM_BUG_ON(drm_mm_node_allocated(node)); |
625d988a CW |
3844 | |
3845 | node->size = size; | |
3846 | node->start = offset; | |
3847 | node->color = color; | |
3848 | ||
3849 | err = drm_mm_reserve_node(&vm->mm, node); | |
3850 | if (err != -ENOSPC) | |
3851 | return err; | |
3852 | ||
616d9cee CW |
3853 | if (flags & PIN_NOEVICT) |
3854 | return -ENOSPC; | |
3855 | ||
625d988a CW |
3856 | err = i915_gem_evict_for_node(vm, node, flags); |
3857 | if (err == 0) | |
3858 | err = drm_mm_reserve_node(&vm->mm, node); | |
3859 | ||
3860 | return err; | |
3861 | } | |
3862 | ||
606fec95 CW |
3863 | static u64 random_offset(u64 start, u64 end, u64 len, u64 align) |
3864 | { | |
3865 | u64 range, addr; | |
3866 | ||
3867 | GEM_BUG_ON(range_overflows(start, len, end)); | |
3868 | GEM_BUG_ON(round_up(start, align) > round_down(end - len, align)); | |
3869 | ||
3870 | range = round_down(end - len, align) - round_up(start, align); | |
3871 | if (range) { | |
3872 | if (sizeof(unsigned long) == sizeof(u64)) { | |
3873 | addr = get_random_long(); | |
3874 | } else { | |
3875 | addr = get_random_int(); | |
3876 | if (range > U32_MAX) { | |
3877 | addr <<= 32; | |
3878 | addr |= get_random_int(); | |
3879 | } | |
3880 | } | |
3881 | div64_u64_rem(addr, range, &addr); | |
3882 | start += addr; | |
3883 | } | |
3884 | ||
3885 | return round_up(start, align); | |
3886 | } | |
3887 | ||
e007b19d CW |
3888 | /** |
3889 | * i915_gem_gtt_insert - insert a node into an address_space (GTT) | |
a4dbf7cf CW |
3890 | * @vm: the &struct i915_address_space |
3891 | * @node: the &struct drm_mm_node (typically i915_vma.node) | |
3892 | * @size: how much space to allocate inside the GTT, | |
3893 | * must be #I915_GTT_PAGE_SIZE aligned | |
3894 | * @alignment: required alignment of starting offset, may be 0 but | |
3895 | * if specified, this must be a power-of-two and at least | |
3896 | * #I915_GTT_MIN_ALIGNMENT | |
3897 | * @color: color to apply to node | |
3898 | * @start: start of any range restriction inside GTT (0 for all), | |
e007b19d | 3899 | * must be #I915_GTT_PAGE_SIZE aligned |
a4dbf7cf CW |
3900 | * @end: end of any range restriction inside GTT (U64_MAX for all), |
3901 | * must be #I915_GTT_PAGE_SIZE aligned if not U64_MAX | |
3902 | * @flags: control search and eviction behaviour | |
e007b19d CW |
3903 | * |
3904 | * i915_gem_gtt_insert() first searches for an available hole into which | |
3905 | * is can insert the node. The hole address is aligned to @alignment and | |
3906 | * its @size must then fit entirely within the [@start, @end] bounds. The | |
3907 | * nodes on either side of the hole must match @color, or else a guard page | |
3908 | * will be inserted between the two nodes (or the node evicted). If no | |
606fec95 CW |
3909 | * suitable hole is found, first a victim is randomly selected and tested |
3910 | * for eviction, otherwise then the LRU list of objects within the GTT | |
e007b19d CW |
3911 | * is scanned to find the first set of replacement nodes to create the hole. |
3912 | * Those old overlapping nodes are evicted from the GTT (and so must be | |
3913 | * rebound before any future use). Any node that is currently pinned cannot | |
3914 | * be evicted (see i915_vma_pin()). Similar if the node's VMA is currently | |
3915 | * active and #PIN_NONBLOCK is specified, that node is also skipped when | |
3916 | * searching for an eviction candidate. See i915_gem_evict_something() for | |
3917 | * the gory details on the eviction algorithm. | |
3918 | * | |
3919 | * Returns: 0 on success, -ENOSPC if no suitable hole is found, -EINTR if | |
3920 | * asked to wait for eviction and interrupted. | |
3921 | */ | |
3922 | int i915_gem_gtt_insert(struct i915_address_space *vm, | |
3923 | struct drm_mm_node *node, | |
3924 | u64 size, u64 alignment, unsigned long color, | |
3925 | u64 start, u64 end, unsigned int flags) | |
3926 | { | |
4e64e553 | 3927 | enum drm_mm_insert_mode mode; |
606fec95 | 3928 | u64 offset; |
e007b19d CW |
3929 | int err; |
3930 | ||
3931 | lockdep_assert_held(&vm->i915->drm.struct_mutex); | |
3932 | GEM_BUG_ON(!size); | |
3933 | GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE)); | |
3934 | GEM_BUG_ON(alignment && !is_power_of_2(alignment)); | |
3935 | GEM_BUG_ON(alignment && !IS_ALIGNED(alignment, I915_GTT_MIN_ALIGNMENT)); | |
3936 | GEM_BUG_ON(start >= end); | |
3937 | GEM_BUG_ON(start > 0 && !IS_ALIGNED(start, I915_GTT_PAGE_SIZE)); | |
3938 | GEM_BUG_ON(end < U64_MAX && !IS_ALIGNED(end, I915_GTT_PAGE_SIZE)); | |
82ad6443 | 3939 | GEM_BUG_ON(vm == &vm->i915->mm.aliasing_ppgtt->vm); |
9734ad13 | 3940 | GEM_BUG_ON(drm_mm_node_allocated(node)); |
e007b19d CW |
3941 | |
3942 | if (unlikely(range_overflows(start, size, end))) | |
3943 | return -ENOSPC; | |
3944 | ||
3945 | if (unlikely(round_up(start, alignment) > round_down(end - size, alignment))) | |
3946 | return -ENOSPC; | |
3947 | ||
4e64e553 CW |
3948 | mode = DRM_MM_INSERT_BEST; |
3949 | if (flags & PIN_HIGH) | |
3950 | mode = DRM_MM_INSERT_HIGH; | |
3951 | if (flags & PIN_MAPPABLE) | |
3952 | mode = DRM_MM_INSERT_LOW; | |
e007b19d CW |
3953 | |
3954 | /* We only allocate in PAGE_SIZE/GTT_PAGE_SIZE (4096) chunks, | |
3955 | * so we know that we always have a minimum alignment of 4096. | |
3956 | * The drm_mm range manager is optimised to return results | |
3957 | * with zero alignment, so where possible use the optimal | |
3958 | * path. | |
3959 | */ | |
3960 | BUILD_BUG_ON(I915_GTT_MIN_ALIGNMENT > I915_GTT_PAGE_SIZE); | |
3961 | if (alignment <= I915_GTT_MIN_ALIGNMENT) | |
3962 | alignment = 0; | |
3963 | ||
4e64e553 CW |
3964 | err = drm_mm_insert_node_in_range(&vm->mm, node, |
3965 | size, alignment, color, | |
3966 | start, end, mode); | |
e007b19d CW |
3967 | if (err != -ENOSPC) |
3968 | return err; | |
3969 | ||
616d9cee CW |
3970 | if (flags & PIN_NOEVICT) |
3971 | return -ENOSPC; | |
3972 | ||
606fec95 CW |
3973 | /* No free space, pick a slot at random. |
3974 | * | |
3975 | * There is a pathological case here using a GTT shared between | |
3976 | * mmap and GPU (i.e. ggtt/aliasing_ppgtt but not full-ppgtt): | |
3977 | * | |
3978 | * |<-- 256 MiB aperture -->||<-- 1792 MiB unmappable -->| | |
3979 | * (64k objects) (448k objects) | |
3980 | * | |
3981 | * Now imagine that the eviction LRU is ordered top-down (just because | |
3982 | * pathology meets real life), and that we need to evict an object to | |
3983 | * make room inside the aperture. The eviction scan then has to walk | |
3984 | * the 448k list before it finds one within range. And now imagine that | |
3985 | * it has to search for a new hole between every byte inside the memcpy, | |
3986 | * for several simultaneous clients. | |
3987 | * | |
3988 | * On a full-ppgtt system, if we have run out of available space, there | |
3989 | * will be lots and lots of objects in the eviction list! Again, | |
3990 | * searching that LRU list may be slow if we are also applying any | |
3991 | * range restrictions (e.g. restriction to low 4GiB) and so, for | |
3992 | * simplicity and similarilty between different GTT, try the single | |
3993 | * random replacement first. | |
3994 | */ | |
3995 | offset = random_offset(start, end, | |
3996 | size, alignment ?: I915_GTT_MIN_ALIGNMENT); | |
3997 | err = i915_gem_gtt_reserve(vm, node, size, offset, color, flags); | |
3998 | if (err != -ENOSPC) | |
3999 | return err; | |
4000 | ||
4001 | /* Randomly selected placement is pinned, do a search */ | |
e007b19d CW |
4002 | err = i915_gem_evict_something(vm, size, alignment, color, |
4003 | start, end, flags); | |
4004 | if (err) | |
4005 | return err; | |
4006 | ||
4e64e553 CW |
4007 | return drm_mm_insert_node_in_range(&vm->mm, node, |
4008 | size, alignment, color, | |
4009 | start, end, DRM_MM_INSERT_EVICT); | |
e007b19d | 4010 | } |
3b5bb0a3 CW |
4011 | |
4012 | #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) | |
4013 | #include "selftests/mock_gtt.c" | |
1c42819a | 4014 | #include "selftests/i915_gem_gtt.c" |
3b5bb0a3 | 4015 | #endif |