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drm/i915: force link training when requested by Sink
[linux-block.git] / drivers / gpu / drm / i915 / i915_gem_gtt.c
CommitLineData
76aaf220
DV		 1/*
2 * Copyright © 2010 Daniel Vetter
c4ac524c 3 * Copyright © 2011-2014 Intel Corporation
76aaf220
DV		 4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 *
24 */
25
0e46ce2e 26#include <linux/seq_file.h>
760285e7
DH		 27#include <drm/drmP.h>
28#include <drm/i915_drm.h>
76aaf220 29#include "i915_drv.h"
5dda8fa3 30#include "i915_vgpu.h"
76aaf220
DV		 31#include "i915_trace.h"
32#include "intel_drv.h"
33
45f8f69a
TU		 34/**
35 * DOC: Global GTT views
36 *
37 * Background and previous state
38 *
39 * Historically objects could exists (be bound) in global GTT space only as
40 * singular instances with a view representing all of the object's backing pages
41 * in a linear fashion. This view will be called a normal view.
42 *
43 * To support multiple views of the same object, where the number of mapped
44 * pages is not equal to the backing store, or where the layout of the pages
45 * is not linear, concept of a GGTT view was added.
46 *
47 * One example of an alternative view is a stereo display driven by a single
48 * image. In this case we would have a framebuffer looking like this
49 * (2x2 pages):
50 *
51 * 12
52 * 34
53 *
54 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
55 * rendering. In contrast, fed to the display engine would be an alternative
56 * view which could look something like this:
57 *
58 * 1212
59 * 3434
60 *
61 * In this example both the size and layout of pages in the alternative view is
62 * different from the normal view.
63 *
64 * Implementation and usage
65 *
66 * GGTT views are implemented using VMAs and are distinguished via enum
67 * i915_ggtt_view_type and struct i915_ggtt_view.
68 *
69 * A new flavour of core GEM functions which work with GGTT bound objects were
ec7adb6e
JL		 70 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
71 * renaming in large amounts of code. They take the struct i915_ggtt_view
72 * parameter encapsulating all metadata required to implement a view.
45f8f69a
TU		 73 *
74 * As a helper for callers which are only interested in the normal view,
75 * globally const i915_ggtt_view_normal singleton instance exists. All old core
76 * GEM API functions, the ones not taking the view parameter, are operating on,
77 * or with the normal GGTT view.
78 *
79 * Code wanting to add or use a new GGTT view needs to:
80 *
81 * 1. Add a new enum with a suitable name.
82 * 2. Extend the metadata in the i915_ggtt_view structure if required.
83 * 3. Add support to i915_get_vma_pages().
84 *
85 * New views are required to build a scatter-gather table from within the
86 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
87 * exists for the lifetime of an VMA.
88 *
89 * Core API is designed to have copy semantics which means that passed in
90 * struct i915_ggtt_view does not need to be persistent (left around after
91 * calling the core API functions).
92 *
93 */
94
70b9f6f8
DV		 95static int
96i915_get_ggtt_vma_pages(struct i915_vma *vma);
97
fe14d5f4 98const struct i915_ggtt_view i915_ggtt_view_normal;
9abc4648
JL		 99const struct i915_ggtt_view i915_ggtt_view_rotated = {
100 .type = I915_GGTT_VIEW_ROTATED
101};
fe14d5f4 102
cfa7c862
DV		 103static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
104{
1893a71b
CW		 105 bool has_aliasing_ppgtt;
106 bool has_full_ppgtt;
1f9a99e0 107 bool has_full_48bit_ppgtt;
1893a71b
CW		 108
109 has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
110 has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
1f9a99e0 111 has_full_48bit_ppgtt = IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9;
1893a71b 112
71ba2d64
YZ		 113 if (intel_vgpu_active(dev))
114 has_full_ppgtt = false; /* emulation is too hard */
115
70ee45e1
DL		 116 /*
117 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
118 * execlists, the sole mechanism available to submit work.
119 */
120 if (INTEL_INFO(dev)->gen < 9 &&
121 (enable_ppgtt == 0 || !has_aliasing_ppgtt))
cfa7c862
DV		 122 return 0;
123
124 if (enable_ppgtt == 1)
125 return 1;
126
1893a71b 127 if (enable_ppgtt == 2 && has_full_ppgtt)
cfa7c862
DV		 128 return 2;
129
1f9a99e0
MT		 130 if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
131 return 3;
132
93a25a9e
DV		 133#ifdef CONFIG_INTEL_IOMMU
134 /* Disable ppgtt on SNB if VT-d is on. */
135 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
136 DRM_INFO("Disabling PPGTT because VT-d is on\n");
cfa7c862 137 return 0;
93a25a9e
DV		 138 }
139#endif
140
62942ed7 141 /* Early VLV doesn't have this */
ca2aed6c
VS		 142 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
143 dev->pdev->revision < 0xb) {
62942ed7
JB		 144 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
145 return 0;
146 }
147
2f82bbdf 148 if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
1f9a99e0 149 return has_full_48bit_ppgtt ? 3 : 2;
2f82bbdf
MT		 150 else
151 return has_aliasing_ppgtt ? 1 : 0;
93a25a9e
DV		 152}
153
70b9f6f8
DV		 154static int ppgtt_bind_vma(struct i915_vma *vma,
155 enum i915_cache_level cache_level,
156 u32 unused)
47552659
DV		 157{
158 u32 pte_flags = 0;
159
160 /* Currently applicable only to VLV */
161 if (vma->obj->gt_ro)
162 pte_flags |= PTE_READ_ONLY;
163
164 vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
165 cache_level, pte_flags);
70b9f6f8
DV		 166
167 return 0;
47552659
DV		 168}
169
170static void ppgtt_unbind_vma(struct i915_vma *vma)
171{
172 vma->vm->clear_range(vma->vm,
173 vma->node.start,
174 vma->obj->base.size,
175 true);
176}
6f65e29a 177
2c642b07
DV		 178static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
179 enum i915_cache_level level,
180 bool valid)
94ec8f61 181{
07749ef3 182 gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
94ec8f61 183 pte |= addr;
63c42e56
BW		 184
185 switch (level) {
186 case I915_CACHE_NONE:
fbe5d36e 187 pte |= PPAT_UNCACHED_INDEX;
63c42e56
BW		 188 break;
189 case I915_CACHE_WT:
190 pte |= PPAT_DISPLAY_ELLC_INDEX;
191 break;
192 default:
193 pte |= PPAT_CACHED_INDEX;
194 break;
195 }
196
94ec8f61
BW		 197 return pte;
198}
199
fe36f55d
MK		 200static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
201 const enum i915_cache_level level)
b1fe6673 202{
07749ef3 203 gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
b1fe6673
BW		 204 pde |= addr;
205 if (level != I915_CACHE_NONE)
206 pde |= PPAT_CACHED_PDE_INDEX;
207 else
208 pde |= PPAT_UNCACHED_INDEX;
209 return pde;
210}
211
762d9936
MT		 212#define gen8_pdpe_encode gen8_pde_encode
213#define gen8_pml4e_encode gen8_pde_encode
214
07749ef3
MT		 215static gen6_pte_t snb_pte_encode(dma_addr_t addr,
216 enum i915_cache_level level,
217 bool valid, u32 unused)
54d12527 218{
07749ef3 219 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
54d12527 220 pte |= GEN6_PTE_ADDR_ENCODE(addr);
e7210c3c
BW		 221
222 switch (level) {
350ec881
CW		 223 case I915_CACHE_L3_LLC:
224 case I915_CACHE_LLC:
225 pte |= GEN6_PTE_CACHE_LLC;
226 break;
227 case I915_CACHE_NONE:
228 pte |= GEN6_PTE_UNCACHED;
229 break;
230 default:
5f77eeb0 231 MISSING_CASE(level);
350ec881
CW		 232 }
233
234 return pte;
235}
236
07749ef3
MT		 237static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
238 enum i915_cache_level level,
239 bool valid, u32 unused)
350ec881 240{
07749ef3 241 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
350ec881
CW		 242 pte |= GEN6_PTE_ADDR_ENCODE(addr);
243
244 switch (level) {
245 case I915_CACHE_L3_LLC:
246 pte |= GEN7_PTE_CACHE_L3_LLC;
e7210c3c
BW		 247 break;
248 case I915_CACHE_LLC:
249 pte |= GEN6_PTE_CACHE_LLC;
250 break;
251 case I915_CACHE_NONE:
9119708c 252 pte |= GEN6_PTE_UNCACHED;
e7210c3c
BW		 253 break;
254 default:
5f77eeb0 255 MISSING_CASE(level);
e7210c3c
BW		 256 }
257
54d12527
BW		 258 return pte;
259}
260
07749ef3
MT		 261static gen6_pte_t byt_pte_encode(dma_addr_t addr,
262 enum i915_cache_level level,
263 bool valid, u32 flags)
93c34e70 264{
07749ef3 265 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
93c34e70
KG		 266 pte |= GEN6_PTE_ADDR_ENCODE(addr);
267
24f3a8cf
AG		 268 if (!(flags & PTE_READ_ONLY))
269 pte |= BYT_PTE_WRITEABLE;
93c34e70
KG		 270
271 if (level != I915_CACHE_NONE)
272 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
273
274 return pte;
275}
276
07749ef3
MT		 277static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
278 enum i915_cache_level level,
279 bool valid, u32 unused)
9119708c 280{
07749ef3 281 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
0d8ff15e 282 pte |= HSW_PTE_ADDR_ENCODE(addr);
9119708c
KG		 283
284 if (level != I915_CACHE_NONE)
87a6b688 285 pte |= HSW_WB_LLC_AGE3;
9119708c
KG		 286
287 return pte;
288}
289
07749ef3
MT		 290static gen6_pte_t iris_pte_encode(dma_addr_t addr,
291 enum i915_cache_level level,
292 bool valid, u32 unused)
4d15c145 293{
07749ef3 294 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
4d15c145
BW		 295 pte |= HSW_PTE_ADDR_ENCODE(addr);
296
651d794f
CW		 297 switch (level) {
298 case I915_CACHE_NONE:
299 break;
300 case I915_CACHE_WT:
c51e9701 301 pte |= HSW_WT_ELLC_LLC_AGE3;
651d794f
CW		 302 break;
303 default:
c51e9701 304 pte |= HSW_WB_ELLC_LLC_AGE3;
651d794f
CW		 305 break;
306 }
4d15c145
BW		 307
308 return pte;
309}
310
c114f76a
MK		 311static int __setup_page_dma(struct drm_device *dev,
312 struct i915_page_dma *p, gfp_t flags)
678d96fb
BW		 313{
314 struct device *device = &dev->pdev->dev;
315
c114f76a 316 p->page = alloc_page(flags);
44159ddb
MK		 317 if (!p->page)
318 return -ENOMEM;
678d96fb 319
44159ddb
MK		 320 p->daddr = dma_map_page(device,
321 p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL);
678d96fb 322
44159ddb
MK		 323 if (dma_mapping_error(device, p->daddr)) {
324 __free_page(p->page);
325 return -EINVAL;
326 }
1266cdb1
MT		 327
328 return 0;
678d96fb
BW		 329}
330
c114f76a
MK		 331static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
332{
333 return __setup_page_dma(dev, p, GFP_KERNEL);
334}
335
44159ddb 336static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
06fda602 337{
44159ddb 338 if (WARN_ON(!p->page))
06fda602 339 return;
678d96fb 340
44159ddb
MK		 341 dma_unmap_page(&dev->pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL);
342 __free_page(p->page);
343 memset(p, 0, sizeof(*p));
344}
345
d1c54acd 346static void *kmap_page_dma(struct i915_page_dma *p)
73eeea53 347{
d1c54acd
MK		 348 return kmap_atomic(p->page);
349}
73eeea53 350
d1c54acd
MK		 351/* We use the flushing unmap only with ppgtt structures:
352 * page directories, page tables and scratch pages.
353 */
354static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
355{
73eeea53
MK		 356 /* There are only few exceptions for gen >=6. chv and bxt.
357 * And we are not sure about the latter so play safe for now.
358 */
359 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
360 drm_clflush_virt_range(vaddr, PAGE_SIZE);
361
362 kunmap_atomic(vaddr);
363}
364
567047be 365#define kmap_px(px) kmap_page_dma(px_base(px))
d1c54acd
MK		 366#define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
367
567047be
MK		 368#define setup_px(dev, px) setup_page_dma((dev), px_base(px))
369#define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
370#define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
371#define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
372
d1c54acd
MK		 373static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
374 const uint64_t val)
375{
376 int i;
377 uint64_t * const vaddr = kmap_page_dma(p);
378
379 for (i = 0; i < 512; i++)
380 vaddr[i] = val;
381
382 kunmap_page_dma(dev, vaddr);
383}
384
73eeea53
MK		 385static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p,
386 const uint32_t val32)
387{
388 uint64_t v = val32;
389
390 v = v << 32 | val32;
391
392 fill_page_dma(dev, p, v);
393}
394
4ad2af1e
MK		 395static struct i915_page_scratch *alloc_scratch_page(struct drm_device *dev)
396{
397 struct i915_page_scratch *sp;
398 int ret;
399
400 sp = kzalloc(sizeof(*sp), GFP_KERNEL);
401 if (sp == NULL)
402 return ERR_PTR(-ENOMEM);
403
404 ret = __setup_page_dma(dev, px_base(sp), GFP_DMA32 | __GFP_ZERO);
405 if (ret) {
406 kfree(sp);
407 return ERR_PTR(ret);
408 }
409
410 set_pages_uc(px_page(sp), 1);
411
412 return sp;
413}
414
415static void free_scratch_page(struct drm_device *dev,
416 struct i915_page_scratch *sp)
417{
418 set_pages_wb(px_page(sp), 1);
419
420 cleanup_px(dev, sp);
421 kfree(sp);
422}
423
8a1ebd74 424static struct i915_page_table *alloc_pt(struct drm_device *dev)
06fda602 425{
ec565b3c 426 struct i915_page_table *pt;
678d96fb
BW		 427 const size_t count = INTEL_INFO(dev)->gen >= 8 ?
428 GEN8_PTES : GEN6_PTES;
429 int ret = -ENOMEM;
06fda602
BW		 430
431 pt = kzalloc(sizeof(*pt), GFP_KERNEL);
432 if (!pt)
433 return ERR_PTR(-ENOMEM);
434
678d96fb
BW		 435 pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes),
436 GFP_KERNEL);
437
438 if (!pt->used_ptes)
439 goto fail_bitmap;
440
567047be 441 ret = setup_px(dev, pt);
678d96fb 442 if (ret)
44159ddb 443 goto fail_page_m;
06fda602
BW		 444
445 return pt;
678d96fb 446
44159ddb 447fail_page_m:
678d96fb
BW		 448 kfree(pt->used_ptes);
449fail_bitmap:
450 kfree(pt);
451
452 return ERR_PTR(ret);
06fda602
BW		 453}
454
2e906bea 455static void free_pt(struct drm_device *dev, struct i915_page_table *pt)
06fda602 456{
2e906bea
MK		 457 cleanup_px(dev, pt);
458 kfree(pt->used_ptes);
459 kfree(pt);
460}
461
462static void gen8_initialize_pt(struct i915_address_space *vm,
463 struct i915_page_table *pt)
464{
465 gen8_pte_t scratch_pte;
466
467 scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
468 I915_CACHE_LLC, true);
469
470 fill_px(vm->dev, pt, scratch_pte);
471}
472
473static void gen6_initialize_pt(struct i915_address_space *vm,
474 struct i915_page_table *pt)
475{
476 gen6_pte_t scratch_pte;
477
478 WARN_ON(px_dma(vm->scratch_page) == 0);
479
480 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
481 I915_CACHE_LLC, true, 0);
482
483 fill32_px(vm->dev, pt, scratch_pte);
06fda602
BW		 484}
485
8a1ebd74 486static struct i915_page_directory *alloc_pd(struct drm_device *dev)
06fda602 487{
ec565b3c 488 struct i915_page_directory *pd;
33c8819f 489 int ret = -ENOMEM;
06fda602
BW		 490
491 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
492 if (!pd)
493 return ERR_PTR(-ENOMEM);
494
33c8819f
MT		 495 pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES),
496 sizeof(*pd->used_pdes), GFP_KERNEL);
497 if (!pd->used_pdes)
a08e111a 498 goto fail_bitmap;
33c8819f 499
567047be 500 ret = setup_px(dev, pd);
33c8819f 501 if (ret)
a08e111a 502 goto fail_page_m;
e5815a2e 503
06fda602 504 return pd;
33c8819f 505
a08e111a 506fail_page_m:
33c8819f 507 kfree(pd->used_pdes);
a08e111a 508fail_bitmap:
33c8819f
MT		 509 kfree(pd);
510
511 return ERR_PTR(ret);
06fda602
BW		 512}
513
2e906bea
MK		 514static void free_pd(struct drm_device *dev, struct i915_page_directory *pd)
515{
516 if (px_page(pd)) {
517 cleanup_px(dev, pd);
518 kfree(pd->used_pdes);
519 kfree(pd);
520 }
521}
522
523static void gen8_initialize_pd(struct i915_address_space *vm,
524 struct i915_page_directory *pd)
525{
526 gen8_pde_t scratch_pde;
527
528 scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC);
529
530 fill_px(vm->dev, pd, scratch_pde);
531}
532
6ac18502
MT		 533static int __pdp_init(struct drm_device *dev,
534 struct i915_page_directory_pointer *pdp)
535{
536 size_t pdpes = I915_PDPES_PER_PDP(dev);
537
538 pdp->used_pdpes = kcalloc(BITS_TO_LONGS(pdpes),
539 sizeof(unsigned long),
540 GFP_KERNEL);
541 if (!pdp->used_pdpes)
542 return -ENOMEM;
543
544 pdp->page_directory = kcalloc(pdpes, sizeof(*pdp->page_directory),
545 GFP_KERNEL);
546 if (!pdp->page_directory) {
547 kfree(pdp->used_pdpes);
548 /* the PDP might be the statically allocated top level. Keep it
549 * as clean as possible */
550 pdp->used_pdpes = NULL;
551 return -ENOMEM;
552 }
553
554 return 0;
555}
556
557static void __pdp_fini(struct i915_page_directory_pointer *pdp)
558{
559 kfree(pdp->used_pdpes);
560 kfree(pdp->page_directory);
561 pdp->page_directory = NULL;
562}
563
762d9936
MT		 564static struct
565i915_page_directory_pointer *alloc_pdp(struct drm_device *dev)
566{
567 struct i915_page_directory_pointer *pdp;
568 int ret = -ENOMEM;
569
570 WARN_ON(!USES_FULL_48BIT_PPGTT(dev));
571
572 pdp = kzalloc(sizeof(*pdp), GFP_KERNEL);
573 if (!pdp)
574 return ERR_PTR(-ENOMEM);
575
576 ret = __pdp_init(dev, pdp);
577 if (ret)
578 goto fail_bitmap;
579
580 ret = setup_px(dev, pdp);
581 if (ret)
582 goto fail_page_m;
583
584 return pdp;
585
586fail_page_m:
587 __pdp_fini(pdp);
588fail_bitmap:
589 kfree(pdp);
590
591 return ERR_PTR(ret);
592}
593
6ac18502
MT		 594static void free_pdp(struct drm_device *dev,
595 struct i915_page_directory_pointer *pdp)
596{
597 __pdp_fini(pdp);
762d9936
MT		 598 if (USES_FULL_48BIT_PPGTT(dev)) {
599 cleanup_px(dev, pdp);
600 kfree(pdp);
601 }
602}
603
69ab76fd
MT		 604static void gen8_initialize_pdp(struct i915_address_space *vm,
605 struct i915_page_directory_pointer *pdp)
606{
607 gen8_ppgtt_pdpe_t scratch_pdpe;
608
609 scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC);
610
611 fill_px(vm->dev, pdp, scratch_pdpe);
612}
613
614static void gen8_initialize_pml4(struct i915_address_space *vm,
615 struct i915_pml4 *pml4)
616{
617 gen8_ppgtt_pml4e_t scratch_pml4e;
618
619 scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp),
620 I915_CACHE_LLC);
621
622 fill_px(vm->dev, pml4, scratch_pml4e);
623}
624
762d9936
MT		 625static void
626gen8_setup_page_directory(struct i915_hw_ppgtt *ppgtt,
627 struct i915_page_directory_pointer *pdp,
628 struct i915_page_directory *pd,
629 int index)
630{
631 gen8_ppgtt_pdpe_t *page_directorypo;
632
633 if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
634 return;
635
636 page_directorypo = kmap_px(pdp);
637 page_directorypo[index] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC);
638 kunmap_px(ppgtt, page_directorypo);
639}
640
641static void
642gen8_setup_page_directory_pointer(struct i915_hw_ppgtt *ppgtt,
643 struct i915_pml4 *pml4,
644 struct i915_page_directory_pointer *pdp,
645 int index)
646{
647 gen8_ppgtt_pml4e_t *pagemap = kmap_px(pml4);
648
649 WARN_ON(!USES_FULL_48BIT_PPGTT(ppgtt->base.dev));
650 pagemap[index] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC);
651 kunmap_px(ppgtt, pagemap);
6ac18502
MT		 652}
653
94e409c1 654/* Broadwell Page Directory Pointer Descriptors */
e85b26dc 655static int gen8_write_pdp(struct drm_i915_gem_request *req,
7cb6d7ac
MT		 656 unsigned entry,
657 dma_addr_t addr)
94e409c1 658{
e85b26dc 659 struct intel_engine_cs *ring = req->ring;
94e409c1
BW		 660 int ret;
661
662 BUG_ON(entry >= 4);
663
5fb9de1a 664 ret = intel_ring_begin(req, 6);
94e409c1
BW		 665 if (ret)
666 return ret;
667
668 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
669 intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
7cb6d7ac 670 intel_ring_emit(ring, upper_32_bits(addr));
94e409c1
BW		 671 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
672 intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
7cb6d7ac 673 intel_ring_emit(ring, lower_32_bits(addr));
94e409c1
BW		 674 intel_ring_advance(ring);
675
676 return 0;
677}
678
2dba3239
MT		 679static int gen8_legacy_mm_switch(struct i915_hw_ppgtt *ppgtt,
680 struct drm_i915_gem_request *req)
94e409c1 681{
eeb9488e 682 int i, ret;
94e409c1 683
7cb6d7ac 684 for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
d852c7bf
MK		 685 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
686
e85b26dc 687 ret = gen8_write_pdp(req, i, pd_daddr);
eeb9488e
BW		 688 if (ret)
689 return ret;
94e409c1 690 }
d595bd4b 691
eeb9488e 692 return 0;
94e409c1
BW		 693}
694
2dba3239
MT		 695static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
696 struct drm_i915_gem_request *req)
697{
698 return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4));
699}
700
f9b5b782
MT		 701static void gen8_ppgtt_clear_pte_range(struct i915_address_space *vm,
702 struct i915_page_directory_pointer *pdp,
703 uint64_t start,
704 uint64_t length,
705 gen8_pte_t scratch_pte)
459108b8
BW		 706{
707 struct i915_hw_ppgtt *ppgtt =
708 container_of(vm, struct i915_hw_ppgtt, base);
f9b5b782 709 gen8_pte_t *pt_vaddr;
de5ba8eb
MT		 710 unsigned pdpe = gen8_pdpe_index(start);
711 unsigned pde = gen8_pde_index(start);
712 unsigned pte = gen8_pte_index(start);
782f1495 713 unsigned num_entries = length >> PAGE_SHIFT;
459108b8
BW		 714 unsigned last_pte, i;
715
f9b5b782
MT		 716 if (WARN_ON(!pdp))
717 return;
459108b8
BW		 718
719 while (num_entries) {
ec565b3c
MT		 720 struct i915_page_directory *pd;
721 struct i915_page_table *pt;
06fda602 722
d4ec9da0 723 if (WARN_ON(!pdp->page_directory[pdpe]))
00245266 724 break;
06fda602 725
d4ec9da0 726 pd = pdp->page_directory[pdpe];
06fda602
BW		 727
728 if (WARN_ON(!pd->page_table[pde]))
00245266 729 break;
06fda602
BW		 730
731 pt = pd->page_table[pde];
732
567047be 733 if (WARN_ON(!px_page(pt)))
00245266 734 break;
06fda602 735
7ad47cf2 736 last_pte = pte + num_entries;
07749ef3
MT		 737 if (last_pte > GEN8_PTES)
738 last_pte = GEN8_PTES;
459108b8 739
d1c54acd 740 pt_vaddr = kmap_px(pt);
459108b8 741
7ad47cf2 742 for (i = pte; i < last_pte; i++) {
459108b8 743 pt_vaddr[i] = scratch_pte;
7ad47cf2
BW		 744 num_entries--;
745 }
459108b8 746
d1c54acd 747 kunmap_px(ppgtt, pt);
459108b8 748
7ad47cf2 749 pte = 0;
07749ef3 750 if (++pde == I915_PDES) {
de5ba8eb
MT		 751 if (++pdpe == I915_PDPES_PER_PDP(vm->dev))
752 break;
7ad47cf2
BW		 753 pde = 0;
754 }
459108b8
BW		 755 }
756}
757
f9b5b782
MT		 758static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
759 uint64_t start,
760 uint64_t length,
761 bool use_scratch)
9df15b49
BW		 762{
763 struct i915_hw_ppgtt *ppgtt =
764 container_of(vm, struct i915_hw_ppgtt, base);
f9b5b782
MT		 765 gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
766 I915_CACHE_LLC, use_scratch);
767
de5ba8eb
MT		 768 if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
769 gen8_ppgtt_clear_pte_range(vm, &ppgtt->pdp, start, length,
770 scratch_pte);
771 } else {
772 uint64_t templ4, pml4e;
773 struct i915_page_directory_pointer *pdp;
774
775 gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, templ4, pml4e) {
776 gen8_ppgtt_clear_pte_range(vm, pdp, start, length,
777 scratch_pte);
778 }
779 }
f9b5b782
MT		 780}
781
782static void
783gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm,
784 struct i915_page_directory_pointer *pdp,
3387d433 785 struct sg_page_iter *sg_iter,
f9b5b782
MT		 786 uint64_t start,
787 enum i915_cache_level cache_level)
788{
789 struct i915_hw_ppgtt *ppgtt =
790 container_of(vm, struct i915_hw_ppgtt, base);
07749ef3 791 gen8_pte_t *pt_vaddr;
de5ba8eb
MT		 792 unsigned pdpe = gen8_pdpe_index(start);
793 unsigned pde = gen8_pde_index(start);
794 unsigned pte = gen8_pte_index(start);
9df15b49 795
6f1cc993 796 pt_vaddr = NULL;
7ad47cf2 797
3387d433 798 while (__sg_page_iter_next(sg_iter)) {
d7b3de91 799 if (pt_vaddr == NULL) {
d4ec9da0 800 struct i915_page_directory *pd = pdp->page_directory[pdpe];
ec565b3c 801 struct i915_page_table *pt = pd->page_table[pde];
d1c54acd 802 pt_vaddr = kmap_px(pt);
d7b3de91 803 }
9df15b49 804
7ad47cf2 805 pt_vaddr[pte] =
3387d433 806 gen8_pte_encode(sg_page_iter_dma_address(sg_iter),
6f1cc993 807 cache_level, true);
07749ef3 808 if (++pte == GEN8_PTES) {
d1c54acd 809 kunmap_px(ppgtt, pt_vaddr);
6f1cc993 810 pt_vaddr = NULL;
07749ef3 811 if (++pde == I915_PDES) {
de5ba8eb
MT		 812 if (++pdpe == I915_PDPES_PER_PDP(vm->dev))
813 break;
7ad47cf2
BW		 814 pde = 0;
815 }
816 pte = 0;
9df15b49
BW		 817 }
818 }
d1c54acd
MK		 819
820 if (pt_vaddr)
821 kunmap_px(ppgtt, pt_vaddr);
9df15b49
BW		 822}
823
f9b5b782
MT		 824static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
825 struct sg_table *pages,
826 uint64_t start,
827 enum i915_cache_level cache_level,
828 u32 unused)
829{
830 struct i915_hw_ppgtt *ppgtt =
831 container_of(vm, struct i915_hw_ppgtt, base);
3387d433 832 struct sg_page_iter sg_iter;
f9b5b782 833
3387d433 834 __sg_page_iter_start(&sg_iter, pages->sgl, sg_nents(pages->sgl), 0);
de5ba8eb
MT		 835
836 if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
837 gen8_ppgtt_insert_pte_entries(vm, &ppgtt->pdp, &sg_iter, start,
838 cache_level);
839 } else {
840 struct i915_page_directory_pointer *pdp;
841 uint64_t templ4, pml4e;
842 uint64_t length = (uint64_t)pages->orig_nents << PAGE_SHIFT;
843
844 gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, templ4, pml4e) {
845 gen8_ppgtt_insert_pte_entries(vm, pdp, &sg_iter,
846 start, cache_level);
847 }
848 }
f9b5b782
MT		 849}
850
f37c0505
MT		 851static void gen8_free_page_tables(struct drm_device *dev,
852 struct i915_page_directory *pd)
7ad47cf2
BW		 853{
854 int i;
855
567047be 856 if (!px_page(pd))
7ad47cf2
BW		 857 return;
858
33c8819f 859 for_each_set_bit(i, pd->used_pdes, I915_PDES) {
06fda602
BW		 860 if (WARN_ON(!pd->page_table[i]))
861 continue;
7ad47cf2 862
a08e111a 863 free_pt(dev, pd->page_table[i]);
06fda602
BW		 864 pd->page_table[i] = NULL;
865 }
d7b3de91
BW		 866}
867
8776f02b
MK		 868static int gen8_init_scratch(struct i915_address_space *vm)
869{
870 struct drm_device *dev = vm->dev;
871
872 vm->scratch_page = alloc_scratch_page(dev);
873 if (IS_ERR(vm->scratch_page))
874 return PTR_ERR(vm->scratch_page);
875
876 vm->scratch_pt = alloc_pt(dev);
877 if (IS_ERR(vm->scratch_pt)) {
878 free_scratch_page(dev, vm->scratch_page);
879 return PTR_ERR(vm->scratch_pt);
880 }
881
882 vm->scratch_pd = alloc_pd(dev);
883 if (IS_ERR(vm->scratch_pd)) {
884 free_pt(dev, vm->scratch_pt);
885 free_scratch_page(dev, vm->scratch_page);
886 return PTR_ERR(vm->scratch_pd);
887 }
888
69ab76fd
MT		 889 if (USES_FULL_48BIT_PPGTT(dev)) {
890 vm->scratch_pdp = alloc_pdp(dev);
891 if (IS_ERR(vm->scratch_pdp)) {
892 free_pd(dev, vm->scratch_pd);
893 free_pt(dev, vm->scratch_pt);
894 free_scratch_page(dev, vm->scratch_page);
895 return PTR_ERR(vm->scratch_pdp);
896 }
897 }
898
8776f02b
MK		 899 gen8_initialize_pt(vm, vm->scratch_pt);
900 gen8_initialize_pd(vm, vm->scratch_pd);
69ab76fd
MT		 901 if (USES_FULL_48BIT_PPGTT(dev))
902 gen8_initialize_pdp(vm, vm->scratch_pdp);
8776f02b
MK		 903
904 return 0;
905}
906
650da34c
ZL		 907static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create)
908{
909 enum vgt_g2v_type msg;
910 struct drm_device *dev = ppgtt->base.dev;
911 struct drm_i915_private *dev_priv = dev->dev_private;
912 unsigned int offset = vgtif_reg(pdp0_lo);
913 int i;
914
915 if (USES_FULL_48BIT_PPGTT(dev)) {
916 u64 daddr = px_dma(&ppgtt->pml4);
917
918 I915_WRITE(offset, lower_32_bits(daddr));
919 I915_WRITE(offset + 4, upper_32_bits(daddr));
920
921 msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE :
922 VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY);
923 } else {
924 for (i = 0; i < GEN8_LEGACY_PDPES; i++) {
925 u64 daddr = i915_page_dir_dma_addr(ppgtt, i);
926
927 I915_WRITE(offset, lower_32_bits(daddr));
928 I915_WRITE(offset + 4, upper_32_bits(daddr));
929
930 offset += 8;
931 }
932
933 msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE :
934 VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY);
935 }
936
937 I915_WRITE(vgtif_reg(g2v_notify), msg);
938
939 return 0;
940}
941
8776f02b
MK		 942static void gen8_free_scratch(struct i915_address_space *vm)
943{
944 struct drm_device *dev = vm->dev;
945
69ab76fd
MT		 946 if (USES_FULL_48BIT_PPGTT(dev))
947 free_pdp(dev, vm->scratch_pdp);
8776f02b
MK		 948 free_pd(dev, vm->scratch_pd);
949 free_pt(dev, vm->scratch_pt);
950 free_scratch_page(dev, vm->scratch_page);
951}
952
762d9936
MT		 953static void gen8_ppgtt_cleanup_3lvl(struct drm_device *dev,
954 struct i915_page_directory_pointer *pdp)
b45a6715
BW		 955{
956 int i;
957
d4ec9da0
MT		 958 for_each_set_bit(i, pdp->used_pdpes, I915_PDPES_PER_PDP(dev)) {
959 if (WARN_ON(!pdp->page_directory[i]))
06fda602
BW		 960 continue;
961
d4ec9da0
MT		 962 gen8_free_page_tables(dev, pdp->page_directory[i]);
963 free_pd(dev, pdp->page_directory[i]);
7ad47cf2 964 }
69876bed 965
d4ec9da0 966 free_pdp(dev, pdp);
762d9936
MT		 967}
968
969static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt *ppgtt)
970{
971 int i;
972
973 for_each_set_bit(i, ppgtt->pml4.used_pml4es, GEN8_PML4ES_PER_PML4) {
974 if (WARN_ON(!ppgtt->pml4.pdps[i]))
975 continue;
976
977 gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, ppgtt->pml4.pdps[i]);
978 }
979
980 cleanup_px(ppgtt->base.dev, &ppgtt->pml4);
981}
982
983static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
984{
985 struct i915_hw_ppgtt *ppgtt =
986 container_of(vm, struct i915_hw_ppgtt, base);
987
650da34c
ZL		 988 if (intel_vgpu_active(vm->dev))
989 gen8_ppgtt_notify_vgt(ppgtt, false);
990
762d9936
MT		 991 if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
992 gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, &ppgtt->pdp);
993 else
994 gen8_ppgtt_cleanup_4lvl(ppgtt);
d4ec9da0 995
8776f02b 996 gen8_free_scratch(vm);
b45a6715
BW		 997}
998
d7b2633d
MT		 999/**
1000 * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
d4ec9da0
MT		 1001 * @vm: Master vm structure.
1002 * @pd: Page directory for this address range.
d7b2633d 1003 * @start: Starting virtual address to begin allocations.
d4ec9da0 1004 * @length: Size of the allocations.
d7b2633d
MT		 1005 * @new_pts: Bitmap set by function with new allocations. Likely used by the
1006 * caller to free on error.
1007 *
1008 * Allocate the required number of page tables. Extremely similar to
1009 * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
1010 * the page directory boundary (instead of the page directory pointer). That
1011 * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
1012 * possible, and likely that the caller will need to use multiple calls of this
1013 * function to achieve the appropriate allocation.
1014 *
1015 * Return: 0 if success; negative error code otherwise.
1016 */
d4ec9da0 1017static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space *vm,
e5815a2e 1018 struct i915_page_directory *pd,
5441f0cb 1019 uint64_t start,
d7b2633d
MT		 1020 uint64_t length,
1021 unsigned long *new_pts)
bf2b4ed2 1022{
d4ec9da0 1023 struct drm_device *dev = vm->dev;
d7b2633d 1024 struct i915_page_table *pt;
5441f0cb
MT		 1025 uint64_t temp;
1026 uint32_t pde;
bf2b4ed2 1027
d7b2633d
MT		 1028 gen8_for_each_pde(pt, pd, start, length, temp, pde) {
1029 /* Don't reallocate page tables */
6ac18502 1030 if (test_bit(pde, pd->used_pdes)) {
d7b2633d 1031 /* Scratch is never allocated this way */
d4ec9da0 1032 WARN_ON(pt == vm->scratch_pt);
d7b2633d
MT		 1033 continue;
1034 }
1035
8a1ebd74 1036 pt = alloc_pt(dev);
d7b2633d 1037 if (IS_ERR(pt))
5441f0cb
MT		 1038 goto unwind_out;
1039
d4ec9da0 1040 gen8_initialize_pt(vm, pt);
d7b2633d 1041 pd->page_table[pde] = pt;
966082c9 1042 __set_bit(pde, new_pts);
4c06ec8d 1043 trace_i915_page_table_entry_alloc(vm, pde, start, GEN8_PDE_SHIFT);
7ad47cf2
BW		 1044 }
1045
bf2b4ed2 1046 return 0;
7ad47cf2
BW		 1047
1048unwind_out:
d7b2633d 1049 for_each_set_bit(pde, new_pts, I915_PDES)
a08e111a 1050 free_pt(dev, pd->page_table[pde]);
7ad47cf2 1051
d7b3de91 1052 return -ENOMEM;
bf2b4ed2
BW		 1053}
1054
d7b2633d
MT		 1055/**
1056 * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
d4ec9da0 1057 * @vm: Master vm structure.
d7b2633d
MT		 1058 * @pdp: Page directory pointer for this address range.
1059 * @start: Starting virtual address to begin allocations.
d4ec9da0
MT		 1060 * @length: Size of the allocations.
1061 * @new_pds: Bitmap set by function with new allocations. Likely used by the
d7b2633d
MT		 1062 * caller to free on error.
1063 *
1064 * Allocate the required number of page directories starting at the pde index of
1065 * @start, and ending at the pde index @start + @length. This function will skip
1066 * over already allocated page directories within the range, and only allocate
1067 * new ones, setting the appropriate pointer within the pdp as well as the
1068 * correct position in the bitmap @new_pds.
1069 *
1070 * The function will only allocate the pages within the range for a give page
1071 * directory pointer. In other words, if @start + @length straddles a virtually
1072 * addressed PDP boundary (512GB for 4k pages), there will be more allocations
1073 * required by the caller, This is not currently possible, and the BUG in the
1074 * code will prevent it.
1075 *
1076 * Return: 0 if success; negative error code otherwise.
1077 */
d4ec9da0
MT		 1078static int
1079gen8_ppgtt_alloc_page_directories(struct i915_address_space *vm,
1080 struct i915_page_directory_pointer *pdp,
1081 uint64_t start,
1082 uint64_t length,
1083 unsigned long *new_pds)
bf2b4ed2 1084{
d4ec9da0 1085 struct drm_device *dev = vm->dev;
d7b2633d 1086 struct i915_page_directory *pd;
69876bed
MT		 1087 uint64_t temp;
1088 uint32_t pdpe;
6ac18502 1089 uint32_t pdpes = I915_PDPES_PER_PDP(dev);
69876bed 1090
6ac18502 1091 WARN_ON(!bitmap_empty(new_pds, pdpes));
d7b2633d 1092
d7b2633d 1093 gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
6ac18502 1094 if (test_bit(pdpe, pdp->used_pdpes))
d7b2633d 1095 continue;
33c8819f 1096
8a1ebd74 1097 pd = alloc_pd(dev);
d7b2633d 1098 if (IS_ERR(pd))
d7b3de91 1099 goto unwind_out;
69876bed 1100
d4ec9da0 1101 gen8_initialize_pd(vm, pd);
d7b2633d 1102 pdp->page_directory[pdpe] = pd;
966082c9 1103 __set_bit(pdpe, new_pds);
4c06ec8d 1104 trace_i915_page_directory_entry_alloc(vm, pdpe, start, GEN8_PDPE_SHIFT);
d7b3de91
BW		 1105 }
1106
bf2b4ed2 1107 return 0;
d7b3de91
BW		 1108
1109unwind_out:
6ac18502 1110 for_each_set_bit(pdpe, new_pds, pdpes)
a08e111a 1111 free_pd(dev, pdp->page_directory[pdpe]);
d7b3de91
BW		 1112
1113 return -ENOMEM;
bf2b4ed2
BW		 1114}
1115
762d9936
MT		 1116/**
1117 * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range.
1118 * @vm: Master vm structure.
1119 * @pml4: Page map level 4 for this address range.
1120 * @start: Starting virtual address to begin allocations.
1121 * @length: Size of the allocations.
1122 * @new_pdps: Bitmap set by function with new allocations. Likely used by the
1123 * caller to free on error.
1124 *
1125 * Allocate the required number of page directory pointers. Extremely similar to
1126 * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pagetabs().
1127 * The main difference is here we are limited by the pml4 boundary (instead of
1128 * the page directory pointer).
1129 *
1130 * Return: 0 if success; negative error code otherwise.
1131 */
1132static int
1133gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space *vm,
1134 struct i915_pml4 *pml4,
1135 uint64_t start,
1136 uint64_t length,
1137 unsigned long *new_pdps)
1138{
1139 struct drm_device *dev = vm->dev;
1140 struct i915_page_directory_pointer *pdp;
1141 uint64_t temp;
1142 uint32_t pml4e;
1143
1144 WARN_ON(!bitmap_empty(new_pdps, GEN8_PML4ES_PER_PML4));
1145
1146 gen8_for_each_pml4e(pdp, pml4, start, length, temp, pml4e) {
1147 if (!test_bit(pml4e, pml4->used_pml4es)) {
1148 pdp = alloc_pdp(dev);
1149 if (IS_ERR(pdp))
1150 goto unwind_out;
1151
69ab76fd 1152 gen8_initialize_pdp(vm, pdp);
762d9936
MT		 1153 pml4->pdps[pml4e] = pdp;
1154 __set_bit(pml4e, new_pdps);
1155 trace_i915_page_directory_pointer_entry_alloc(vm,
1156 pml4e,
1157 start,
1158 GEN8_PML4E_SHIFT);
1159 }
1160 }
1161
1162 return 0;
1163
1164unwind_out:
1165 for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4)
1166 free_pdp(dev, pml4->pdps[pml4e]);
1167
1168 return -ENOMEM;
1169}
1170
d7b2633d 1171static void
3a41a05d 1172free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long *new_pts)
d7b2633d 1173{
d7b2633d
MT		 1174 kfree(new_pts);
1175 kfree(new_pds);
1176}
1177
1178/* Fills in the page directory bitmap, and the array of page tables bitmap. Both
1179 * of these are based on the number of PDPEs in the system.
1180 */
1181static
1182int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds,
3a41a05d 1183 unsigned long **new_pts,
6ac18502 1184 uint32_t pdpes)
d7b2633d 1185{
d7b2633d 1186 unsigned long *pds;
3a41a05d 1187 unsigned long *pts;
d7b2633d 1188
3a41a05d 1189 pds = kcalloc(BITS_TO_LONGS(pdpes), sizeof(unsigned long), GFP_TEMPORARY);
d7b2633d
MT		 1190 if (!pds)
1191 return -ENOMEM;
1192
3a41a05d
MW		 1193 pts = kcalloc(pdpes, BITS_TO_LONGS(I915_PDES) * sizeof(unsigned long),
1194 GFP_TEMPORARY);
1195 if (!pts)
1196 goto err_out;
d7b2633d
MT		 1197
1198 *new_pds = pds;
1199 *new_pts = pts;
1200
1201 return 0;
1202
1203err_out:
3a41a05d 1204 free_gen8_temp_bitmaps(pds, pts);
d7b2633d
MT		 1205 return -ENOMEM;
1206}
1207
5b7e4c9c
MK		 1208/* PDE TLBs are a pain to invalidate on GEN8+. When we modify
1209 * the page table structures, we mark them dirty so that
1210 * context switching/execlist queuing code takes extra steps
1211 * to ensure that tlbs are flushed.
1212 */
1213static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
1214{
1215 ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
1216}
1217
762d9936
MT		 1218static int gen8_alloc_va_range_3lvl(struct i915_address_space *vm,
1219 struct i915_page_directory_pointer *pdp,
1220 uint64_t start,
1221 uint64_t length)
bf2b4ed2 1222{
e5815a2e
MT		 1223 struct i915_hw_ppgtt *ppgtt =
1224 container_of(vm, struct i915_hw_ppgtt, base);
3a41a05d 1225 unsigned long *new_page_dirs, *new_page_tables;
d4ec9da0 1226 struct drm_device *dev = vm->dev;
5441f0cb 1227 struct i915_page_directory *pd;
33c8819f
MT		 1228 const uint64_t orig_start = start;
1229 const uint64_t orig_length = length;
5441f0cb
MT		 1230 uint64_t temp;
1231 uint32_t pdpe;
d4ec9da0 1232 uint32_t pdpes = I915_PDPES_PER_PDP(dev);
bf2b4ed2
BW		 1233 int ret;
1234
d7b2633d
MT		 1235 /* Wrap is never okay since we can only represent 48b, and we don't
1236 * actually use the other side of the canonical address space.
1237 */
1238 if (WARN_ON(start + length < start))
a05d80ee
MK		 1239 return -ENODEV;
1240
d4ec9da0 1241 if (WARN_ON(start + length > vm->total))
a05d80ee 1242 return -ENODEV;
d7b2633d 1243
6ac18502 1244 ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
bf2b4ed2
BW		 1245 if (ret)
1246 return ret;
1247
d7b2633d 1248 /* Do the allocations first so we can easily bail out */
d4ec9da0
MT		 1249 ret = gen8_ppgtt_alloc_page_directories(vm, pdp, start, length,
1250 new_page_dirs);
d7b2633d 1251 if (ret) {
3a41a05d 1252 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
d7b2633d
MT		 1253 return ret;
1254 }
1255
1256 /* For every page directory referenced, allocate page tables */
d4ec9da0
MT		 1257 gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
1258 ret = gen8_ppgtt_alloc_pagetabs(vm, pd, start, length,
3a41a05d 1259 new_page_tables + pdpe * BITS_TO_LONGS(I915_PDES));
5441f0cb
MT		 1260 if (ret)
1261 goto err_out;
5441f0cb
MT		 1262 }
1263
33c8819f
MT		 1264 start = orig_start;
1265 length = orig_length;
1266
d7b2633d
MT		 1267 /* Allocations have completed successfully, so set the bitmaps, and do
1268 * the mappings. */
d4ec9da0 1269 gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
d1c54acd 1270 gen8_pde_t *const page_directory = kmap_px(pd);
33c8819f 1271 struct i915_page_table *pt;
09120d4e 1272 uint64_t pd_len = length;
33c8819f
MT		 1273 uint64_t pd_start = start;
1274 uint32_t pde;
1275
d7b2633d
MT		 1276 /* Every pd should be allocated, we just did that above. */
1277 WARN_ON(!pd);
1278
1279 gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) {
1280 /* Same reasoning as pd */
1281 WARN_ON(!pt);
1282 WARN_ON(!pd_len);
1283 WARN_ON(!gen8_pte_count(pd_start, pd_len));
1284
1285 /* Set our used ptes within the page table */
1286 bitmap_set(pt->used_ptes,
1287 gen8_pte_index(pd_start),
1288 gen8_pte_count(pd_start, pd_len));
1289
1290 /* Our pde is now pointing to the pagetable, pt */
966082c9 1291 __set_bit(pde, pd->used_pdes);
d7b2633d
MT		 1292
1293 /* Map the PDE to the page table */
fe36f55d
MK		 1294 page_directory[pde] = gen8_pde_encode(px_dma(pt),
1295 I915_CACHE_LLC);
4c06ec8d
MT		 1296 trace_i915_page_table_entry_map(&ppgtt->base, pde, pt,
1297 gen8_pte_index(start),
1298 gen8_pte_count(start, length),
1299 GEN8_PTES);
d7b2633d
MT		 1300
1301 /* NB: We haven't yet mapped ptes to pages. At this
1302 * point we're still relying on insert_entries() */
33c8819f 1303 }
d7b2633d 1304
d1c54acd 1305 kunmap_px(ppgtt, page_directory);
d4ec9da0 1306 __set_bit(pdpe, pdp->used_pdpes);
762d9936 1307 gen8_setup_page_directory(ppgtt, pdp, pd, pdpe);
33c8819f
MT		 1308 }
1309
3a41a05d 1310 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
5b7e4c9c 1311 mark_tlbs_dirty(ppgtt);
d7b3de91 1312 return 0;
bf2b4ed2 1313
d7b3de91 1314err_out:
d7b2633d 1315 while (pdpe--) {
3a41a05d
MW		 1316 for_each_set_bit(temp, new_page_tables + pdpe *
1317 BITS_TO_LONGS(I915_PDES), I915_PDES)
d4ec9da0 1318 free_pt(dev, pdp->page_directory[pdpe]->page_table[temp]);
d7b2633d
MT		 1319 }
1320
6ac18502 1321 for_each_set_bit(pdpe, new_page_dirs, pdpes)
d4ec9da0 1322 free_pd(dev, pdp->page_directory[pdpe]);
d7b2633d 1323
3a41a05d 1324 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
5b7e4c9c 1325 mark_tlbs_dirty(ppgtt);
bf2b4ed2
BW		 1326 return ret;
1327}
1328
762d9936
MT		 1329static int gen8_alloc_va_range_4lvl(struct i915_address_space *vm,
1330 struct i915_pml4 *pml4,
1331 uint64_t start,
1332 uint64_t length)
1333{
1334 DECLARE_BITMAP(new_pdps, GEN8_PML4ES_PER_PML4);
1335 struct i915_hw_ppgtt *ppgtt =
1336 container_of(vm, struct i915_hw_ppgtt, base);
1337 struct i915_page_directory_pointer *pdp;
1338 uint64_t temp, pml4e;
1339 int ret = 0;
1340
1341 /* Do the pml4 allocations first, so we don't need to track the newly
1342 * allocated tables below the pdp */
1343 bitmap_zero(new_pdps, GEN8_PML4ES_PER_PML4);
1344
1345 /* The pagedirectory and pagetable allocations are done in the shared 3
1346 * and 4 level code. Just allocate the pdps.
1347 */
1348 ret = gen8_ppgtt_alloc_page_dirpointers(vm, pml4, start, length,
1349 new_pdps);
1350 if (ret)
1351 return ret;
1352
1353 WARN(bitmap_weight(new_pdps, GEN8_PML4ES_PER_PML4) > 2,
1354 "The allocation has spanned more than 512GB. "
1355 "It is highly likely this is incorrect.");
1356
1357 gen8_for_each_pml4e(pdp, pml4, start, length, temp, pml4e) {
1358 WARN_ON(!pdp);
1359
1360 ret = gen8_alloc_va_range_3lvl(vm, pdp, start, length);
1361 if (ret)
1362 goto err_out;
1363
1364 gen8_setup_page_directory_pointer(ppgtt, pml4, pdp, pml4e);
1365 }
1366
1367 bitmap_or(pml4->used_pml4es, new_pdps, pml4->used_pml4es,
1368 GEN8_PML4ES_PER_PML4);
1369
1370 return 0;
1371
1372err_out:
1373 for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4)
1374 gen8_ppgtt_cleanup_3lvl(vm->dev, pml4->pdps[pml4e]);
1375
1376 return ret;
1377}
1378
1379static int gen8_alloc_va_range(struct i915_address_space *vm,
1380 uint64_t start, uint64_t length)
1381{
1382 struct i915_hw_ppgtt *ppgtt =
1383 container_of(vm, struct i915_hw_ppgtt, base);
1384
1385 if (USES_FULL_48BIT_PPGTT(vm->dev))
1386 return gen8_alloc_va_range_4lvl(vm, &ppgtt->pml4, start, length);
1387 else
1388 return gen8_alloc_va_range_3lvl(vm, &ppgtt->pdp, start, length);
1389}
1390
ea91e401
MT		 1391static void gen8_dump_pdp(struct i915_page_directory_pointer *pdp,
1392 uint64_t start, uint64_t length,
1393 gen8_pte_t scratch_pte,
1394 struct seq_file *m)
1395{
1396 struct i915_page_directory *pd;
1397 uint64_t temp;
1398 uint32_t pdpe;
1399
1400 gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
1401 struct i915_page_table *pt;
1402 uint64_t pd_len = length;
1403 uint64_t pd_start = start;
1404 uint32_t pde;
1405
1406 if (!test_bit(pdpe, pdp->used_pdpes))
1407 continue;
1408
1409 seq_printf(m, "\tPDPE #%d\n", pdpe);
1410 gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) {
1411 uint32_t pte;
1412 gen8_pte_t *pt_vaddr;
1413
1414 if (!test_bit(pde, pd->used_pdes))
1415 continue;
1416
1417 pt_vaddr = kmap_px(pt);
1418 for (pte = 0; pte < GEN8_PTES; pte += 4) {
1419 uint64_t va =
1420 (pdpe << GEN8_PDPE_SHIFT) |
1421 (pde << GEN8_PDE_SHIFT) |
1422 (pte << GEN8_PTE_SHIFT);
1423 int i;
1424 bool found = false;
1425
1426 for (i = 0; i < 4; i++)
1427 if (pt_vaddr[pte + i] != scratch_pte)
1428 found = true;
1429 if (!found)
1430 continue;
1431
1432 seq_printf(m, "\t\t0x%llx [%03d,%03d,%04d]: =", va, pdpe, pde, pte);
1433 for (i = 0; i < 4; i++) {
1434 if (pt_vaddr[pte + i] != scratch_pte)
1435 seq_printf(m, " %llx", pt_vaddr[pte + i]);
1436 else
1437 seq_puts(m, " SCRATCH ");
1438 }
1439 seq_puts(m, "\n");
1440 }
1441 /* don't use kunmap_px, it could trigger
1442 * an unnecessary flush.
1443 */
1444 kunmap_atomic(pt_vaddr);
1445 }
1446 }
1447}
1448
1449static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1450{
1451 struct i915_address_space *vm = &ppgtt->base;
1452 uint64_t start = ppgtt->base.start;
1453 uint64_t length = ppgtt->base.total;
1454 gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
1455 I915_CACHE_LLC, true);
1456
1457 if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
1458 gen8_dump_pdp(&ppgtt->pdp, start, length, scratch_pte, m);
1459 } else {
1460 uint64_t templ4, pml4e;
1461 struct i915_pml4 *pml4 = &ppgtt->pml4;
1462 struct i915_page_directory_pointer *pdp;
1463
1464 gen8_for_each_pml4e(pdp, pml4, start, length, templ4, pml4e) {
1465 if (!test_bit(pml4e, pml4->used_pml4es))
1466 continue;
1467
1468 seq_printf(m, " PML4E #%llu\n", pml4e);
1469 gen8_dump_pdp(pdp, start, length, scratch_pte, m);
1470 }
1471 }
1472}
1473
331f38e7
ZL		 1474static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt *ppgtt)
1475{
3a41a05d 1476 unsigned long *new_page_dirs, *new_page_tables;
331f38e7
ZL		 1477 uint32_t pdpes = I915_PDPES_PER_PDP(dev);
1478 int ret;
1479
1480 /* We allocate temp bitmap for page tables for no gain
1481 * but as this is for init only, lets keep the things simple
1482 */
1483 ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
1484 if (ret)
1485 return ret;
1486
1487 /* Allocate for all pdps regardless of how the ppgtt
1488 * was defined.
1489 */
1490 ret = gen8_ppgtt_alloc_page_directories(&ppgtt->base, &ppgtt->pdp,
1491 0, 1ULL << 32,
1492 new_page_dirs);
1493 if (!ret)
1494 *ppgtt->pdp.used_pdpes = *new_page_dirs;
1495
3a41a05d 1496 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
331f38e7
ZL		 1497
1498 return ret;
1499}
1500
eb0b44ad 1501/*
f3a964b9
BW		 1502 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1503 * with a net effect resembling a 2-level page table in normal x86 terms. Each
1504 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1505 * space.
37aca44a 1506 *
f3a964b9 1507 */
5c5f6457 1508static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
37aca44a 1509{
8776f02b 1510 int ret;
7cb6d7ac 1511
8776f02b
MK		 1512 ret = gen8_init_scratch(&ppgtt->base);
1513 if (ret)
1514 return ret;
69876bed 1515
d7b2633d 1516 ppgtt->base.start = 0;
d7b2633d 1517 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
5c5f6457 1518 ppgtt->base.allocate_va_range = gen8_alloc_va_range;
d7b2633d 1519 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
c7e16f22 1520 ppgtt->base.clear_range = gen8_ppgtt_clear_range;
777dc5bb
DV		 1521 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1522 ppgtt->base.bind_vma = ppgtt_bind_vma;
ea91e401 1523 ppgtt->debug_dump = gen8_dump_ppgtt;
d7b2633d 1524
762d9936
MT		 1525 if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
1526 ret = setup_px(ppgtt->base.dev, &ppgtt->pml4);
1527 if (ret)
1528 goto free_scratch;
6ac18502 1529
69ab76fd
MT		 1530 gen8_initialize_pml4(&ppgtt->base, &ppgtt->pml4);
1531
762d9936 1532 ppgtt->base.total = 1ULL << 48;
2dba3239 1533 ppgtt->switch_mm = gen8_48b_mm_switch;
762d9936 1534 } else {
25f50337 1535 ret = __pdp_init(ppgtt->base.dev, &ppgtt->pdp);
81ba8aef
MT		 1536 if (ret)
1537 goto free_scratch;
1538
1539 ppgtt->base.total = 1ULL << 32;
2dba3239 1540 ppgtt->switch_mm = gen8_legacy_mm_switch;
762d9936
MT		 1541 trace_i915_page_directory_pointer_entry_alloc(&ppgtt->base,
1542 0, 0,
1543 GEN8_PML4E_SHIFT);
331f38e7
ZL		 1544
1545 if (intel_vgpu_active(ppgtt->base.dev)) {
1546 ret = gen8_preallocate_top_level_pdps(ppgtt);
1547 if (ret)
1548 goto free_scratch;
1549 }
81ba8aef 1550 }
6ac18502 1551
650da34c
ZL		 1552 if (intel_vgpu_active(ppgtt->base.dev))
1553 gen8_ppgtt_notify_vgt(ppgtt, true);
1554
d7b2633d 1555 return 0;
6ac18502
MT		 1556
1557free_scratch:
1558 gen8_free_scratch(&ppgtt->base);
1559 return ret;
d7b2633d
MT		 1560}
1561
87d60b63
BW		 1562static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1563{
87d60b63 1564 struct i915_address_space *vm = &ppgtt->base;
09942c65 1565 struct i915_page_table *unused;
07749ef3 1566 gen6_pte_t scratch_pte;
87d60b63 1567 uint32_t pd_entry;
09942c65
MT		 1568 uint32_t pte, pde, temp;
1569 uint32_t start = ppgtt->base.start, length = ppgtt->base.total;
87d60b63 1570
79ab9370
MK		 1571 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1572 I915_CACHE_LLC, true, 0);
87d60b63 1573
09942c65 1574 gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) {
87d60b63 1575 u32 expected;
07749ef3 1576 gen6_pte_t *pt_vaddr;
567047be 1577 const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]);
09942c65 1578 pd_entry = readl(ppgtt->pd_addr + pde);
87d60b63
BW		 1579 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
1580
1581 if (pd_entry != expected)
1582 seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1583 pde,
1584 pd_entry,
1585 expected);
1586 seq_printf(m, "\tPDE: %x\n", pd_entry);
1587
d1c54acd
MK		 1588 pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]);
1589
07749ef3 1590 for (pte = 0; pte < GEN6_PTES; pte+=4) {
87d60b63 1591 unsigned long va =
07749ef3 1592 (pde * PAGE_SIZE * GEN6_PTES) +
87d60b63
BW		 1593 (pte * PAGE_SIZE);
1594 int i;
1595 bool found = false;
1596 for (i = 0; i < 4; i++)
1597 if (pt_vaddr[pte + i] != scratch_pte)
1598 found = true;
1599 if (!found)
1600 continue;
1601
1602 seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
1603 for (i = 0; i < 4; i++) {
1604 if (pt_vaddr[pte + i] != scratch_pte)
1605 seq_printf(m, " %08x", pt_vaddr[pte + i]);
1606 else
1607 seq_puts(m, " SCRATCH ");
1608 }
1609 seq_puts(m, "\n");
1610 }
d1c54acd 1611 kunmap_px(ppgtt, pt_vaddr);
87d60b63
BW		 1612 }
1613}
1614
678d96fb 1615/* Write pde (index) from the page directory @pd to the page table @pt */
ec565b3c
MT		 1616static void gen6_write_pde(struct i915_page_directory *pd,
1617 const int pde, struct i915_page_table *pt)
6197349b 1618{
678d96fb
BW		 1619 /* Caller needs to make sure the write completes if necessary */
1620 struct i915_hw_ppgtt *ppgtt =
1621 container_of(pd, struct i915_hw_ppgtt, pd);
1622 u32 pd_entry;
6197349b 1623
567047be 1624 pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt));
678d96fb 1625 pd_entry |= GEN6_PDE_VALID;
6197349b 1626
678d96fb
BW		 1627 writel(pd_entry, ppgtt->pd_addr + pde);
1628}
6197349b 1629
678d96fb
BW		 1630/* Write all the page tables found in the ppgtt structure to incrementing page
1631 * directories. */
1632static void gen6_write_page_range(struct drm_i915_private *dev_priv,
ec565b3c 1633 struct i915_page_directory *pd,
678d96fb
BW		 1634 uint32_t start, uint32_t length)
1635{
ec565b3c 1636 struct i915_page_table *pt;
678d96fb
BW		 1637 uint32_t pde, temp;
1638
1639 gen6_for_each_pde(pt, pd, start, length, temp, pde)
1640 gen6_write_pde(pd, pde, pt);
1641
1642 /* Make sure write is complete before other code can use this page
1643 * table. Also require for WC mapped PTEs */
1644 readl(dev_priv->gtt.gsm);
3e302542
BW		 1645}
1646
b4a74e3a 1647static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
3e302542 1648{
44159ddb 1649 BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f);
b4a74e3a 1650
44159ddb 1651 return (ppgtt->pd.base.ggtt_offset / 64) << 16;
b4a74e3a
BW		 1652}
1653
90252e5c 1654static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 1655 struct drm_i915_gem_request *req)
90252e5c 1656{
e85b26dc 1657 struct intel_engine_cs *ring = req->ring;
90252e5c
BW		 1658 int ret;
1659
90252e5c 1660 /* NB: TLBs must be flushed and invalidated before a switch */
a84c3ae1 1661 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
90252e5c
BW		 1662 if (ret)
1663 return ret;
1664
5fb9de1a 1665 ret = intel_ring_begin(req, 6);
90252e5c
BW		 1666 if (ret)
1667 return ret;
1668
1669 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1670 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1671 intel_ring_emit(ring, PP_DIR_DCLV_2G);
1672 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1673 intel_ring_emit(ring, get_pd_offset(ppgtt));
1674 intel_ring_emit(ring, MI_NOOP);
1675 intel_ring_advance(ring);
1676
1677 return 0;
1678}
1679
71ba2d64 1680static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 1681 struct drm_i915_gem_request *req)
71ba2d64 1682{
e85b26dc 1683 struct intel_engine_cs *ring = req->ring;
71ba2d64
YZ		 1684 struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
1685
1686 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1687 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1688 return 0;
1689}
1690
48a10389 1691static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 1692 struct drm_i915_gem_request *req)
48a10389 1693{
e85b26dc 1694 struct intel_engine_cs *ring = req->ring;
48a10389
BW		 1695 int ret;
1696
48a10389 1697 /* NB: TLBs must be flushed and invalidated before a switch */
a84c3ae1 1698 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
48a10389
BW		 1699 if (ret)
1700 return ret;
1701
5fb9de1a 1702 ret = intel_ring_begin(req, 6);
48a10389
BW		 1703 if (ret)
1704 return ret;
1705
1706 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1707 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1708 intel_ring_emit(ring, PP_DIR_DCLV_2G);
1709 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1710 intel_ring_emit(ring, get_pd_offset(ppgtt));
1711 intel_ring_emit(ring, MI_NOOP);
1712 intel_ring_advance(ring);
1713
90252e5c
BW		 1714 /* XXX: RCS is the only one to auto invalidate the TLBs? */
1715 if (ring->id != RCS) {
a84c3ae1 1716 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
90252e5c
BW		 1717 if (ret)
1718 return ret;
1719 }
1720
48a10389
BW		 1721 return 0;
1722}
1723
eeb9488e 1724static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 1725 struct drm_i915_gem_request *req)
eeb9488e 1726{
e85b26dc 1727 struct intel_engine_cs *ring = req->ring;
eeb9488e
BW		 1728 struct drm_device *dev = ppgtt->base.dev;
1729 struct drm_i915_private *dev_priv = dev->dev_private;
1730
48a10389 1731
eeb9488e
BW		 1732 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1733 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1734
1735 POSTING_READ(RING_PP_DIR_DCLV(ring));
1736
1737 return 0;
1738}
1739
82460d97 1740static void gen8_ppgtt_enable(struct drm_device *dev)
eeb9488e 1741{
eeb9488e 1742 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1743 struct intel_engine_cs *ring;
82460d97 1744 int j;
3e302542 1745
eeb9488e 1746 for_each_ring(ring, dev_priv, j) {
2dba3239 1747 u32 four_level = USES_FULL_48BIT_PPGTT(dev) ? GEN8_GFX_PPGTT_48B : 0;
eeb9488e 1748 I915_WRITE(RING_MODE_GEN7(ring),
2dba3239 1749 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
eeb9488e 1750 }
eeb9488e 1751}
6197349b 1752
82460d97 1753static void gen7_ppgtt_enable(struct drm_device *dev)
3e302542 1754{
50227e1c 1755 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1756 struct intel_engine_cs *ring;
b4a74e3a 1757 uint32_t ecochk, ecobits;
3e302542 1758 int i;
6197349b 1759
b4a74e3a
BW		 1760 ecobits = I915_READ(GAC_ECO_BITS);
1761 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
a65c2fcd 1762
b4a74e3a
BW		 1763 ecochk = I915_READ(GAM_ECOCHK);
1764 if (IS_HASWELL(dev)) {
1765 ecochk |= ECOCHK_PPGTT_WB_HSW;
1766 } else {
1767 ecochk |= ECOCHK_PPGTT_LLC_IVB;
1768 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
1769 }
1770 I915_WRITE(GAM_ECOCHK, ecochk);
a65c2fcd 1771
b4a74e3a 1772 for_each_ring(ring, dev_priv, i) {
6197349b 1773 /* GFX_MODE is per-ring on gen7+ */
b4a74e3a
BW		 1774 I915_WRITE(RING_MODE_GEN7(ring),
1775 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
6197349b 1776 }
b4a74e3a 1777}
6197349b 1778
82460d97 1779static void gen6_ppgtt_enable(struct drm_device *dev)
b4a74e3a 1780{
50227e1c 1781 struct drm_i915_private *dev_priv = dev->dev_private;
b4a74e3a 1782 uint32_t ecochk, gab_ctl, ecobits;
a65c2fcd 1783
b4a74e3a
BW		 1784 ecobits = I915_READ(GAC_ECO_BITS);
1785 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
1786 ECOBITS_PPGTT_CACHE64B);
6197349b 1787
b4a74e3a
BW		 1788 gab_ctl = I915_READ(GAB_CTL);
1789 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
1790
1791 ecochk = I915_READ(GAM_ECOCHK);
1792 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
1793
1794 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
6197349b
BW		 1795}
1796
1d2a314c 1797/* PPGTT support for Sandybdrige/Gen6 and later */
853ba5d2 1798static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 1799 uint64_t start,
1800 uint64_t length,
828c7908 1801 bool use_scratch)
1d2a314c 1802{
853ba5d2
BW		 1803 struct i915_hw_ppgtt *ppgtt =
1804 container_of(vm, struct i915_hw_ppgtt, base);
07749ef3 1805 gen6_pte_t *pt_vaddr, scratch_pte;
782f1495
BW		 1806 unsigned first_entry = start >> PAGE_SHIFT;
1807 unsigned num_entries = length >> PAGE_SHIFT;
07749ef3
MT		 1808 unsigned act_pt = first_entry / GEN6_PTES;
1809 unsigned first_pte = first_entry % GEN6_PTES;
7bddb01f 1810 unsigned last_pte, i;
1d2a314c 1811
c114f76a
MK		 1812 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1813 I915_CACHE_LLC, true, 0);
1d2a314c 1814
7bddb01f
DV		 1815 while (num_entries) {
1816 last_pte = first_pte + num_entries;
07749ef3
MT		 1817 if (last_pte > GEN6_PTES)
1818 last_pte = GEN6_PTES;
7bddb01f 1819
d1c54acd 1820 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
1d2a314c 1821
7bddb01f
DV		 1822 for (i = first_pte; i < last_pte; i++)
1823 pt_vaddr[i] = scratch_pte;
1d2a314c 1824
d1c54acd 1825 kunmap_px(ppgtt, pt_vaddr);
1d2a314c 1826
7bddb01f
DV		 1827 num_entries -= last_pte - first_pte;
1828 first_pte = 0;
a15326a5 1829 act_pt++;
7bddb01f 1830 }
1d2a314c
DV		 1831}
1832
853ba5d2 1833static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
def886c3 1834 struct sg_table *pages,
782f1495 1835 uint64_t start,
24f3a8cf 1836 enum i915_cache_level cache_level, u32 flags)
def886c3 1837{
853ba5d2
BW		 1838 struct i915_hw_ppgtt *ppgtt =
1839 container_of(vm, struct i915_hw_ppgtt, base);
07749ef3 1840 gen6_pte_t *pt_vaddr;
782f1495 1841 unsigned first_entry = start >> PAGE_SHIFT;
07749ef3
MT		 1842 unsigned act_pt = first_entry / GEN6_PTES;
1843 unsigned act_pte = first_entry % GEN6_PTES;
6e995e23
ID		 1844 struct sg_page_iter sg_iter;
1845
cc79714f 1846 pt_vaddr = NULL;
6e995e23 1847 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
cc79714f 1848 if (pt_vaddr == NULL)
d1c54acd 1849 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
6e995e23 1850
cc79714f
CW		 1851 pt_vaddr[act_pte] =
1852 vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
24f3a8cf
AG		 1853 cache_level, true, flags);
1854
07749ef3 1855 if (++act_pte == GEN6_PTES) {
d1c54acd 1856 kunmap_px(ppgtt, pt_vaddr);
cc79714f 1857 pt_vaddr = NULL;
a15326a5 1858 act_pt++;
6e995e23 1859 act_pte = 0;
def886c3 1860 }
def886c3 1861 }
cc79714f 1862 if (pt_vaddr)
d1c54acd 1863 kunmap_px(ppgtt, pt_vaddr);
def886c3
DV		 1864}
1865
678d96fb 1866static int gen6_alloc_va_range(struct i915_address_space *vm,
a05d80ee 1867 uint64_t start_in, uint64_t length_in)
678d96fb 1868{
4933d519
MT		 1869 DECLARE_BITMAP(new_page_tables, I915_PDES);
1870 struct drm_device *dev = vm->dev;
1871 struct drm_i915_private *dev_priv = dev->dev_private;
678d96fb
BW		 1872 struct i915_hw_ppgtt *ppgtt =
1873 container_of(vm, struct i915_hw_ppgtt, base);
ec565b3c 1874 struct i915_page_table *pt;
a05d80ee 1875 uint32_t start, length, start_save, length_save;
678d96fb 1876 uint32_t pde, temp;
4933d519
MT		 1877 int ret;
1878
a05d80ee
MK		 1879 if (WARN_ON(start_in + length_in > ppgtt->base.total))
1880 return -ENODEV;
1881
1882 start = start_save = start_in;
1883 length = length_save = length_in;
4933d519
MT		 1884
1885 bitmap_zero(new_page_tables, I915_PDES);
1886
1887 /* The allocation is done in two stages so that we can bail out with
1888 * minimal amount of pain. The first stage finds new page tables that
1889 * need allocation. The second stage marks use ptes within the page
1890 * tables.
1891 */
1892 gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
79ab9370 1893 if (pt != vm->scratch_pt) {
4933d519
MT		 1894 WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES));
1895 continue;
1896 }
1897
1898 /* We've already allocated a page table */
1899 WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES));
1900
8a1ebd74 1901 pt = alloc_pt(dev);
4933d519
MT		 1902 if (IS_ERR(pt)) {
1903 ret = PTR_ERR(pt);
1904 goto unwind_out;
1905 }
1906
1907 gen6_initialize_pt(vm, pt);
1908
1909 ppgtt->pd.page_table[pde] = pt;
966082c9 1910 __set_bit(pde, new_page_tables);
72744cb1 1911 trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT);
4933d519
MT		 1912 }
1913
1914 start = start_save;
1915 length = length_save;
678d96fb
BW		 1916
1917 gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1918 DECLARE_BITMAP(tmp_bitmap, GEN6_PTES);
1919
1920 bitmap_zero(tmp_bitmap, GEN6_PTES);
1921 bitmap_set(tmp_bitmap, gen6_pte_index(start),
1922 gen6_pte_count(start, length));
1923
966082c9 1924 if (__test_and_clear_bit(pde, new_page_tables))
4933d519
MT		 1925 gen6_write_pde(&ppgtt->pd, pde, pt);
1926
72744cb1
MT		 1927 trace_i915_page_table_entry_map(vm, pde, pt,
1928 gen6_pte_index(start),
1929 gen6_pte_count(start, length),
1930 GEN6_PTES);
4933d519 1931 bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes,
678d96fb
BW		 1932 GEN6_PTES);
1933 }
1934
4933d519
MT		 1935 WARN_ON(!bitmap_empty(new_page_tables, I915_PDES));
1936
1937 /* Make sure write is complete before other code can use this page
1938 * table. Also require for WC mapped PTEs */
1939 readl(dev_priv->gtt.gsm);
1940
563222a7 1941 mark_tlbs_dirty(ppgtt);
678d96fb 1942 return 0;
4933d519
MT		 1943
1944unwind_out:
1945 for_each_set_bit(pde, new_page_tables, I915_PDES) {
ec565b3c 1946 struct i915_page_table *pt = ppgtt->pd.page_table[pde];
4933d519 1947
79ab9370 1948 ppgtt->pd.page_table[pde] = vm->scratch_pt;
a08e111a 1949 free_pt(vm->dev, pt);
4933d519
MT		 1950 }
1951
1952 mark_tlbs_dirty(ppgtt);
1953 return ret;
678d96fb
BW		 1954}
1955
8776f02b
MK		 1956static int gen6_init_scratch(struct i915_address_space *vm)
1957{
1958 struct drm_device *dev = vm->dev;
1959
1960 vm->scratch_page = alloc_scratch_page(dev);
1961 if (IS_ERR(vm->scratch_page))
1962 return PTR_ERR(vm->scratch_page);
1963
1964 vm->scratch_pt = alloc_pt(dev);
1965 if (IS_ERR(vm->scratch_pt)) {
1966 free_scratch_page(dev, vm->scratch_page);
1967 return PTR_ERR(vm->scratch_pt);
1968 }
1969
1970 gen6_initialize_pt(vm, vm->scratch_pt);
1971
1972 return 0;
1973}
1974
1975static void gen6_free_scratch(struct i915_address_space *vm)
1976{
1977 struct drm_device *dev = vm->dev;
1978
1979 free_pt(dev, vm->scratch_pt);
1980 free_scratch_page(dev, vm->scratch_page);
1981}
1982
061dd493 1983static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
a00d825d 1984{
061dd493
DV		 1985 struct i915_hw_ppgtt *ppgtt =
1986 container_of(vm, struct i915_hw_ppgtt, base);
09942c65
MT		 1987 struct i915_page_table *pt;
1988 uint32_t pde;
4933d519 1989
061dd493
DV		 1990 drm_mm_remove_node(&ppgtt->node);
1991
09942c65 1992 gen6_for_all_pdes(pt, ppgtt, pde) {
79ab9370 1993 if (pt != vm->scratch_pt)
a08e111a 1994 free_pt(ppgtt->base.dev, pt);
4933d519 1995 }
06fda602 1996
8776f02b 1997 gen6_free_scratch(vm);
3440d265
DV		 1998}
1999
b146520f 2000static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
3440d265 2001{
8776f02b 2002 struct i915_address_space *vm = &ppgtt->base;
853ba5d2 2003 struct drm_device *dev = ppgtt->base.dev;
1d2a314c 2004 struct drm_i915_private *dev_priv = dev->dev_private;
e3cc1995 2005 bool retried = false;
b146520f 2006 int ret;
1d2a314c 2007
c8d4c0d6
BW		 2008 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
2009 * allocator works in address space sizes, so it's multiplied by page
2010 * size. We allocate at the top of the GTT to avoid fragmentation.
2011 */
2012 BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
4933d519 2013
8776f02b
MK		 2014 ret = gen6_init_scratch(vm);
2015 if (ret)
2016 return ret;
4933d519 2017
e3cc1995 2018alloc:
c8d4c0d6
BW		 2019 ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
2020 &ppgtt->node, GEN6_PD_SIZE,
2021 GEN6_PD_ALIGN, 0,
2022 0, dev_priv->gtt.base.total,
3e8b5ae9 2023 DRM_MM_TOPDOWN);
e3cc1995
BW		 2024 if (ret == -ENOSPC && !retried) {
2025 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
2026 GEN6_PD_SIZE, GEN6_PD_ALIGN,
d23db88c
CW		 2027 I915_CACHE_NONE,
2028 0, dev_priv->gtt.base.total,
2029 0);
e3cc1995 2030 if (ret)
678d96fb 2031 goto err_out;
e3cc1995
BW		 2032
2033 retried = true;
2034 goto alloc;
2035 }
c8d4c0d6 2036
c8c26622 2037 if (ret)
678d96fb
BW		 2038 goto err_out;
2039
c8c26622 2040
c8d4c0d6
BW		 2041 if (ppgtt->node.start < dev_priv->gtt.mappable_end)
2042 DRM_DEBUG("Forced to use aperture for PDEs\n");
1d2a314c 2043
c8c26622 2044 return 0;
678d96fb
BW		 2045
2046err_out:
8776f02b 2047 gen6_free_scratch(vm);
678d96fb 2048 return ret;
b146520f
BW		 2049}
2050
b146520f
BW		 2051static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
2052{
2f2cf682 2053 return gen6_ppgtt_allocate_page_directories(ppgtt);
4933d519 2054}
06dc68d6 2055
4933d519
MT		 2056static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt,
2057 uint64_t start, uint64_t length)
2058{
ec565b3c 2059 struct i915_page_table *unused;
4933d519 2060 uint32_t pde, temp;
1d2a314c 2061
4933d519 2062 gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde)
79ab9370 2063 ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt;
b146520f
BW		 2064}
2065
5c5f6457 2066static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
b146520f
BW		 2067{
2068 struct drm_device *dev = ppgtt->base.dev;
2069 struct drm_i915_private *dev_priv = dev->dev_private;
2070 int ret;
2071
2072 ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
2073 if (IS_GEN6(dev)) {
b146520f
BW		 2074 ppgtt->switch_mm = gen6_mm_switch;
2075 } else if (IS_HASWELL(dev)) {
b146520f
BW		 2076 ppgtt->switch_mm = hsw_mm_switch;
2077 } else if (IS_GEN7(dev)) {
b146520f
BW		 2078 ppgtt->switch_mm = gen7_mm_switch;
2079 } else
2080 BUG();
2081
71ba2d64
YZ		 2082 if (intel_vgpu_active(dev))
2083 ppgtt->switch_mm = vgpu_mm_switch;
2084
b146520f
BW		 2085 ret = gen6_ppgtt_alloc(ppgtt);
2086 if (ret)
2087 return ret;
2088
5c5f6457 2089 ppgtt->base.allocate_va_range = gen6_alloc_va_range;
b146520f
BW		 2090 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
2091 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
777dc5bb
DV		 2092 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
2093 ppgtt->base.bind_vma = ppgtt_bind_vma;
b146520f 2094 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
b146520f 2095 ppgtt->base.start = 0;
09942c65 2096 ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
87d60b63 2097 ppgtt->debug_dump = gen6_dump_ppgtt;
1d2a314c 2098
44159ddb 2099 ppgtt->pd.base.ggtt_offset =
07749ef3 2100 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t);
1d2a314c 2101
678d96fb 2102 ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm +
44159ddb 2103 ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t);
678d96fb 2104
5c5f6457 2105 gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total);
1d2a314c 2106
678d96fb
BW		 2107 gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total);
2108
440fd528 2109 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
b146520f
BW		 2110 ppgtt->node.size >> 20,
2111 ppgtt->node.start / PAGE_SIZE);
3440d265 2112
fa76da34 2113 DRM_DEBUG("Adding PPGTT at offset %x\n",
44159ddb 2114 ppgtt->pd.base.ggtt_offset << 10);
fa76da34 2115
b146520f 2116 return 0;
3440d265
DV		 2117}
2118
5c5f6457 2119static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
3440d265 2120{
853ba5d2 2121 ppgtt->base.dev = dev;
3440d265 2122
3ed124b2 2123 if (INTEL_INFO(dev)->gen < 8)
5c5f6457 2124 return gen6_ppgtt_init(ppgtt);
3ed124b2 2125 else
d7b2633d 2126 return gen8_ppgtt_init(ppgtt);
fa76da34 2127}
c114f76a 2128
a2cad9df
MW		 2129static void i915_address_space_init(struct i915_address_space *vm,
2130 struct drm_i915_private *dev_priv)
2131{
2132 drm_mm_init(&vm->mm, vm->start, vm->total);
2133 vm->dev = dev_priv->dev;
2134 INIT_LIST_HEAD(&vm->active_list);
2135 INIT_LIST_HEAD(&vm->inactive_list);
2136 list_add_tail(&vm->global_link, &dev_priv->vm_list);
2137}
2138
fa76da34
DV		 2139int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
2140{
2141 struct drm_i915_private *dev_priv = dev->dev_private;
2142 int ret = 0;
3ed124b2 2143
5c5f6457 2144 ret = __hw_ppgtt_init(dev, ppgtt);
fa76da34 2145 if (ret == 0) {
c7c48dfd 2146 kref_init(&ppgtt->ref);
a2cad9df 2147 i915_address_space_init(&ppgtt->base, dev_priv);
93bd8649 2148 }
1d2a314c
DV		 2149
2150 return ret;
2151}
2152
82460d97
DV		 2153int i915_ppgtt_init_hw(struct drm_device *dev)
2154{
671b5013
TD		 2155 /* In the case of execlists, PPGTT is enabled by the context descriptor
2156 * and the PDPs are contained within the context itself. We don't
2157 * need to do anything here. */
2158 if (i915.enable_execlists)
2159 return 0;
2160
82460d97
DV		 2161 if (!USES_PPGTT(dev))
2162 return 0;
2163
2164 if (IS_GEN6(dev))
2165 gen6_ppgtt_enable(dev);
2166 else if (IS_GEN7(dev))
2167 gen7_ppgtt_enable(dev);
2168 else if (INTEL_INFO(dev)->gen >= 8)
2169 gen8_ppgtt_enable(dev);
2170 else
5f77eeb0 2171 MISSING_CASE(INTEL_INFO(dev)->gen);
82460d97 2172
4ad2fd88
JH		 2173 return 0;
2174}
1d2a314c 2175
b3dd6b96 2176int i915_ppgtt_init_ring(struct drm_i915_gem_request *req)
4ad2fd88 2177{
b3dd6b96 2178 struct drm_i915_private *dev_priv = req->ring->dev->dev_private;
4ad2fd88
JH		 2179 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2180
2181 if (i915.enable_execlists)
2182 return 0;
2183
2184 if (!ppgtt)
2185 return 0;
2186
e85b26dc 2187 return ppgtt->switch_mm(ppgtt, req);
1d2a314c 2188}
4ad2fd88 2189
4d884705
DV		 2190struct i915_hw_ppgtt *
2191i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
2192{
2193 struct i915_hw_ppgtt *ppgtt;
2194 int ret;
2195
2196 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2197 if (!ppgtt)
2198 return ERR_PTR(-ENOMEM);
2199
2200 ret = i915_ppgtt_init(dev, ppgtt);
2201 if (ret) {
2202 kfree(ppgtt);
2203 return ERR_PTR(ret);
2204 }
2205
2206 ppgtt->file_priv = fpriv;
2207
198c974d
DCS		 2208 trace_i915_ppgtt_create(&ppgtt->base);
2209
4d884705
DV		 2210 return ppgtt;
2211}
2212
ee960be7
DV		 2213void i915_ppgtt_release(struct kref *kref)
2214{
2215 struct i915_hw_ppgtt *ppgtt =
2216 container_of(kref, struct i915_hw_ppgtt, ref);
2217
198c974d
DCS		 2218 trace_i915_ppgtt_release(&ppgtt->base);
2219
ee960be7
DV		 2220 /* vmas should already be unbound */
2221 WARN_ON(!list_empty(&ppgtt->base.active_list));
2222 WARN_ON(!list_empty(&ppgtt->base.inactive_list));
2223
19dd120c
DV		 2224 list_del(&ppgtt->base.global_link);
2225 drm_mm_takedown(&ppgtt->base.mm);
2226
ee960be7
DV		 2227 ppgtt->base.cleanup(&ppgtt->base);
2228 kfree(ppgtt);
2229}
1d2a314c 2230
a81cc00c
BW		 2231extern int intel_iommu_gfx_mapped;
2232/* Certain Gen5 chipsets require require idling the GPU before
2233 * unmapping anything from the GTT when VT-d is enabled.
2234 */
2c642b07 2235static bool needs_idle_maps(struct drm_device *dev)
a81cc00c
BW		 2236{
2237#ifdef CONFIG_INTEL_IOMMU
2238 /* Query intel_iommu to see if we need the workaround. Presumably that
2239 * was loaded first.
2240 */
2241 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
2242 return true;
2243#endif
2244 return false;
2245}
2246
5c042287
BW		 2247static bool do_idling(struct drm_i915_private *dev_priv)
2248{
2249 bool ret = dev_priv->mm.interruptible;
2250
a81cc00c 2251 if (unlikely(dev_priv->gtt.do_idle_maps)) {
5c042287 2252 dev_priv->mm.interruptible = false;
b2da9fe5 2253 if (i915_gpu_idle(dev_priv->dev)) {
5c042287
BW		 2254 DRM_ERROR("Couldn't idle GPU\n");
2255 /* Wait a bit, in hopes it avoids the hang */
2256 udelay(10);
2257 }
2258 }
2259
2260 return ret;
2261}
2262
2263static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
2264{
a81cc00c 2265 if (unlikely(dev_priv->gtt.do_idle_maps))
5c042287
BW		 2266 dev_priv->mm.interruptible = interruptible;
2267}
2268
828c7908
BW		 2269void i915_check_and_clear_faults(struct drm_device *dev)
2270{
2271 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2272 struct intel_engine_cs *ring;
828c7908
BW		 2273 int i;
2274
2275 if (INTEL_INFO(dev)->gen < 6)
2276 return;
2277
2278 for_each_ring(ring, dev_priv, i) {
2279 u32 fault_reg;
2280 fault_reg = I915_READ(RING_FAULT_REG(ring));
2281 if (fault_reg & RING_FAULT_VALID) {
2282 DRM_DEBUG_DRIVER("Unexpected fault\n"
59a5d290 2283 "\tAddr: 0x%08lx\n"
828c7908
BW		 2284 "\tAddress space: %s\n"
2285 "\tSource ID: %d\n"
2286 "\tType: %d\n",
2287 fault_reg & PAGE_MASK,
2288 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
2289 RING_FAULT_SRCID(fault_reg),
2290 RING_FAULT_FAULT_TYPE(fault_reg));
2291 I915_WRITE(RING_FAULT_REG(ring),
2292 fault_reg & ~RING_FAULT_VALID);
2293 }
2294 }
2295 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
2296}
2297
91e56499
CW		 2298static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
2299{
2300 if (INTEL_INFO(dev_priv->dev)->gen < 6) {
2301 intel_gtt_chipset_flush();
2302 } else {
2303 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2304 POSTING_READ(GFX_FLSH_CNTL_GEN6);
2305 }
2306}
2307
828c7908
BW		 2308void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
2309{
2310 struct drm_i915_private *dev_priv = dev->dev_private;
2311
2312 /* Don't bother messing with faults pre GEN6 as we have little
2313 * documentation supporting that it's a good idea.
2314 */
2315 if (INTEL_INFO(dev)->gen < 6)
2316 return;
2317
2318 i915_check_and_clear_faults(dev);
2319
2320 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
782f1495
BW		 2321 dev_priv->gtt.base.start,
2322 dev_priv->gtt.base.total,
e568af1c 2323 true);
91e56499
CW		 2324
2325 i915_ggtt_flush(dev_priv);
828c7908
BW		 2326}
2327
74163907 2328int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
7c2e6fdf 2329{
9da3da66
CW		 2330 if (!dma_map_sg(&obj->base.dev->pdev->dev,
2331 obj->pages->sgl, obj->pages->nents,
2332 PCI_DMA_BIDIRECTIONAL))
2333 return -ENOSPC;
2334
2335 return 0;
7c2e6fdf
DV		 2336}
2337
2c642b07 2338static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
94ec8f61
BW		 2339{
2340#ifdef writeq
2341 writeq(pte, addr);
2342#else
2343 iowrite32((u32)pte, addr);
2344 iowrite32(pte >> 32, addr + 4);
2345#endif
2346}
2347
2348static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
2349 struct sg_table *st,
782f1495 2350 uint64_t start,
24f3a8cf 2351 enum i915_cache_level level, u32 unused)
94ec8f61
BW		 2352{
2353 struct drm_i915_private *dev_priv = vm->dev->dev_private;
782f1495 2354 unsigned first_entry = start >> PAGE_SHIFT;
07749ef3
MT		 2355 gen8_pte_t __iomem *gtt_entries =
2356 (gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
94ec8f61
BW		 2357 int i = 0;
2358 struct sg_page_iter sg_iter;
57007df7 2359 dma_addr_t addr = 0; /* shut up gcc */
94ec8f61
BW		 2360
2361 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
2362 addr = sg_dma_address(sg_iter.sg) +
2363 (sg_iter.sg_pgoffset << PAGE_SHIFT);
2364 gen8_set_pte(&gtt_entries[i],
2365 gen8_pte_encode(addr, level, true));
2366 i++;
2367 }
2368
2369 /*
2370 * XXX: This serves as a posting read to make sure that the PTE has
2371 * actually been updated. There is some concern that even though
2372 * registers and PTEs are within the same BAR that they are potentially
2373 * of NUMA access patterns. Therefore, even with the way we assume
2374 * hardware should work, we must keep this posting read for paranoia.
2375 */
2376 if (i != 0)
2377 WARN_ON(readq(&gtt_entries[i-1])
2378 != gen8_pte_encode(addr, level, true));
2379
94ec8f61
BW		 2380 /* This next bit makes the above posting read even more important. We
2381 * want to flush the TLBs only after we're certain all the PTE updates
2382 * have finished.
2383 */
2384 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2385 POSTING_READ(GFX_FLSH_CNTL_GEN6);
94ec8f61
BW		 2386}
2387
e76e9aeb
BW		 2388/*
2389 * Binds an object into the global gtt with the specified cache level. The object
2390 * will be accessible to the GPU via commands whose operands reference offsets
2391 * within the global GTT as well as accessible by the GPU through the GMADR
2392 * mapped BAR (dev_priv->mm.gtt->gtt).
2393 */
853ba5d2 2394static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
7faf1ab2 2395 struct sg_table *st,
782f1495 2396 uint64_t start,
24f3a8cf 2397 enum i915_cache_level level, u32 flags)
e76e9aeb 2398{
853ba5d2 2399 struct drm_i915_private *dev_priv = vm->dev->dev_private;
782f1495 2400 unsigned first_entry = start >> PAGE_SHIFT;
07749ef3
MT		 2401 gen6_pte_t __iomem *gtt_entries =
2402 (gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
6e995e23
ID		 2403 int i = 0;
2404 struct sg_page_iter sg_iter;
57007df7 2405 dma_addr_t addr = 0;
e76e9aeb 2406
6e995e23 2407 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
2db76d7c 2408 addr = sg_page_iter_dma_address(&sg_iter);
24f3a8cf 2409 iowrite32(vm->pte_encode(addr, level, true, flags), &gtt_entries[i]);
6e995e23 2410 i++;
e76e9aeb
BW		 2411 }
2412
e76e9aeb
BW		 2413 /* XXX: This serves as a posting read to make sure that the PTE has
2414 * actually been updated. There is some concern that even though
2415 * registers and PTEs are within the same BAR that they are potentially
2416 * of NUMA access patterns. Therefore, even with the way we assume
2417 * hardware should work, we must keep this posting read for paranoia.
2418 */
57007df7
PM		 2419 if (i != 0) {
2420 unsigned long gtt = readl(&gtt_entries[i-1]);
2421 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
2422 }
0f9b91c7
BW		 2423
2424 /* This next bit makes the above posting read even more important. We
2425 * want to flush the TLBs only after we're certain all the PTE updates
2426 * have finished.
2427 */
2428 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2429 POSTING_READ(GFX_FLSH_CNTL_GEN6);
e76e9aeb
BW		 2430}
2431
94ec8f61 2432static void gen8_ggtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 2433 uint64_t start,
2434 uint64_t length,
94ec8f61
BW		 2435 bool use_scratch)
2436{
2437 struct drm_i915_private *dev_priv = vm->dev->dev_private;
782f1495
BW		 2438 unsigned first_entry = start >> PAGE_SHIFT;
2439 unsigned num_entries = length >> PAGE_SHIFT;
07749ef3
MT		 2440 gen8_pte_t scratch_pte, __iomem *gtt_base =
2441 (gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
94ec8f61
BW		 2442 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
2443 int i;
2444
2445 if (WARN(num_entries > max_entries,
2446 "First entry = %d; Num entries = %d (max=%d)\n",
2447 first_entry, num_entries, max_entries))
2448 num_entries = max_entries;
2449
c114f76a 2450 scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
94ec8f61
BW		 2451 I915_CACHE_LLC,
2452 use_scratch);
2453 for (i = 0; i < num_entries; i++)
2454 gen8_set_pte(&gtt_base[i], scratch_pte);
2455 readl(gtt_base);
2456}
2457
853ba5d2 2458static void gen6_ggtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 2459 uint64_t start,
2460 uint64_t length,
828c7908 2461 bool use_scratch)
7faf1ab2 2462{
853ba5d2 2463 struct drm_i915_private *dev_priv = vm->dev->dev_private;
782f1495
BW		 2464 unsigned first_entry = start >> PAGE_SHIFT;
2465 unsigned num_entries = length >> PAGE_SHIFT;
07749ef3
MT		 2466 gen6_pte_t scratch_pte, __iomem *gtt_base =
2467 (gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
a54c0c27 2468 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
7faf1ab2
DV		 2469 int i;
2470
2471 if (WARN(num_entries > max_entries,
2472 "First entry = %d; Num entries = %d (max=%d)\n",
2473 first_entry, num_entries, max_entries))
2474 num_entries = max_entries;
2475
c114f76a
MK		 2476 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
2477 I915_CACHE_LLC, use_scratch, 0);
828c7908 2478
7faf1ab2
DV		 2479 for (i = 0; i < num_entries; i++)
2480 iowrite32(scratch_pte, &gtt_base[i]);
2481 readl(gtt_base);
2482}
2483
d369d2d9
DV		 2484static void i915_ggtt_insert_entries(struct i915_address_space *vm,
2485 struct sg_table *pages,
2486 uint64_t start,
2487 enum i915_cache_level cache_level, u32 unused)
7faf1ab2
DV		 2488{
2489 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
2490 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
2491
d369d2d9 2492 intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags);
0875546c 2493
7faf1ab2
DV		 2494}
2495
853ba5d2 2496static void i915_ggtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 2497 uint64_t start,
2498 uint64_t length,
828c7908 2499 bool unused)
7faf1ab2 2500{
782f1495
BW		 2501 unsigned first_entry = start >> PAGE_SHIFT;
2502 unsigned num_entries = length >> PAGE_SHIFT;
7faf1ab2
DV		 2503 intel_gtt_clear_range(first_entry, num_entries);
2504}
2505
70b9f6f8
DV		 2506static int ggtt_bind_vma(struct i915_vma *vma,
2507 enum i915_cache_level cache_level,
2508 u32 flags)
0a878716
DV		 2509{
2510 struct drm_i915_gem_object *obj = vma->obj;
2511 u32 pte_flags = 0;
2512 int ret;
2513
2514 ret = i915_get_ggtt_vma_pages(vma);
2515 if (ret)
2516 return ret;
2517
2518 /* Currently applicable only to VLV */
2519 if (obj->gt_ro)
2520 pte_flags |= PTE_READ_ONLY;
2521
2522 vma->vm->insert_entries(vma->vm, vma->ggtt_view.pages,
2523 vma->node.start,
2524 cache_level, pte_flags);
2525
2526 /*
2527 * Without aliasing PPGTT there's no difference between
2528 * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
2529 * upgrade to both bound if we bind either to avoid double-binding.
2530 */
2531 vma->bound |= GLOBAL_BIND | LOCAL_BIND;
2532
2533 return 0;
2534}
2535
2536static int aliasing_gtt_bind_vma(struct i915_vma *vma,
2537 enum i915_cache_level cache_level,
2538 u32 flags)
d5bd1449 2539{
6f65e29a 2540 struct drm_device *dev = vma->vm->dev;
7faf1ab2 2541 struct drm_i915_private *dev_priv = dev->dev_private;
6f65e29a 2542 struct drm_i915_gem_object *obj = vma->obj;
ec7adb6e 2543 struct sg_table *pages = obj->pages;
f329f5f6 2544 u32 pte_flags = 0;
70b9f6f8
DV		 2545 int ret;
2546
2547 ret = i915_get_ggtt_vma_pages(vma);
2548 if (ret)
2549 return ret;
2550 pages = vma->ggtt_view.pages;
7faf1ab2 2551
24f3a8cf
AG		 2552 /* Currently applicable only to VLV */
2553 if (obj->gt_ro)
f329f5f6 2554 pte_flags |= PTE_READ_ONLY;
24f3a8cf 2555
ec7adb6e 2556
0a878716 2557 if (flags & GLOBAL_BIND) {
0875546c
DV		 2558 vma->vm->insert_entries(vma->vm, pages,
2559 vma->node.start,
2560 cache_level, pte_flags);
6f65e29a 2561 }
d5bd1449 2562
0a878716 2563 if (flags & LOCAL_BIND) {
6f65e29a 2564 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
ec7adb6e 2565 appgtt->base.insert_entries(&appgtt->base, pages,
782f1495 2566 vma->node.start,
f329f5f6 2567 cache_level, pte_flags);
6f65e29a 2568 }
70b9f6f8
DV		 2569
2570 return 0;
d5bd1449
CW		 2571}
2572
6f65e29a 2573static void ggtt_unbind_vma(struct i915_vma *vma)
74163907 2574{
6f65e29a 2575 struct drm_device *dev = vma->vm->dev;
7faf1ab2 2576 struct drm_i915_private *dev_priv = dev->dev_private;
6f65e29a 2577 struct drm_i915_gem_object *obj = vma->obj;
06615ee5
JL		 2578 const uint64_t size = min_t(uint64_t,
2579 obj->base.size,
2580 vma->node.size);
6f65e29a 2581
aff43766 2582 if (vma->bound & GLOBAL_BIND) {
782f1495
BW		 2583 vma->vm->clear_range(vma->vm,
2584 vma->node.start,
06615ee5 2585 size,
6f65e29a 2586 true);
6f65e29a 2587 }
74898d7e 2588
0875546c 2589 if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) {
6f65e29a 2590 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
06615ee5 2591
6f65e29a 2592 appgtt->base.clear_range(&appgtt->base,
782f1495 2593 vma->node.start,
06615ee5 2594 size,
6f65e29a 2595 true);
6f65e29a 2596 }
74163907
DV		 2597}
2598
2599void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
7c2e6fdf 2600{
5c042287
BW		 2601 struct drm_device *dev = obj->base.dev;
2602 struct drm_i915_private *dev_priv = dev->dev_private;
2603 bool interruptible;
2604
2605 interruptible = do_idling(dev_priv);
2606
5ec5b516
ID		 2607 dma_unmap_sg(&dev->pdev->dev, obj->pages->sgl, obj->pages->nents,
2608 PCI_DMA_BIDIRECTIONAL);
5c042287
BW		 2609
2610 undo_idling(dev_priv, interruptible);
7c2e6fdf 2611}
644ec02b 2612
42d6ab48
CW		 2613static void i915_gtt_color_adjust(struct drm_mm_node *node,
2614 unsigned long color,
440fd528
TR		 2615 u64 *start,
2616 u64 *end)
42d6ab48
CW		 2617{
2618 if (node->color != color)
2619 *start += 4096;
2620
2621 if (!list_empty(&node->node_list)) {
2622 node = list_entry(node->node_list.next,
2623 struct drm_mm_node,
2624 node_list);
2625 if (node->allocated && node->color != color)
2626 *end -= 4096;
2627 }
2628}
fbe5d36e 2629
f548c0e9 2630static int i915_gem_setup_global_gtt(struct drm_device *dev,
088e0df4
MT		 2631 u64 start,
2632 u64 mappable_end,
2633 u64 end)
644ec02b 2634{
e78891ca
BW		 2635 /* Let GEM Manage all of the aperture.
2636 *
2637 * However, leave one page at the end still bound to the scratch page.
2638 * There are a number of places where the hardware apparently prefetches
2639 * past the end of the object, and we've seen multiple hangs with the
2640 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2641 * aperture. One page should be enough to keep any prefetching inside
2642 * of the aperture.
2643 */
40d74980
BW		 2644 struct drm_i915_private *dev_priv = dev->dev_private;
2645 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
ed2f3452
CW		 2646 struct drm_mm_node *entry;
2647 struct drm_i915_gem_object *obj;
2648 unsigned long hole_start, hole_end;
fa76da34 2649 int ret;
644ec02b 2650
35451cb6
BW		 2651 BUG_ON(mappable_end > end);
2652
a2cad9df 2653 ggtt_vm->start = start;
5dda8fa3 2654
a2cad9df
MW		 2655 /* Subtract the guard page before address space initialization to
2656 * shrink the range used by drm_mm */
2657 ggtt_vm->total = end - start - PAGE_SIZE;
2658 i915_address_space_init(ggtt_vm, dev_priv);
2659 ggtt_vm->total += PAGE_SIZE;
5dda8fa3
YZ		 2660
2661 if (intel_vgpu_active(dev)) {
2662 ret = intel_vgt_balloon(dev);
2663 if (ret)
2664 return ret;
2665 }
2666
42d6ab48 2667 if (!HAS_LLC(dev))
a2cad9df 2668 ggtt_vm->mm.color_adjust = i915_gtt_color_adjust;
644ec02b 2669
ed2f3452 2670 /* Mark any preallocated objects as occupied */
35c20a60 2671 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
40d74980 2672 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
fa76da34 2673
088e0df4 2674 DRM_DEBUG_KMS("reserving preallocated space: %llx + %zx\n",
c6cfb325
BW		 2675 i915_gem_obj_ggtt_offset(obj), obj->base.size);
2676
2677 WARN_ON(i915_gem_obj_ggtt_bound(obj));
40d74980 2678 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
6c5566a8
DV		 2679 if (ret) {
2680 DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
2681 return ret;
2682 }
aff43766 2683 vma->bound |= GLOBAL_BIND;
7c4a7d60 2684 list_add_tail(&vma->mm_list, &ggtt_vm->inactive_list);
ed2f3452
CW		 2685 }
2686
ed2f3452 2687 /* Clear any non-preallocated blocks */
40d74980 2688 drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
ed2f3452
CW		 2689 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2690 hole_start, hole_end);
782f1495
BW		 2691 ggtt_vm->clear_range(ggtt_vm, hole_start,
2692 hole_end - hole_start, true);
ed2f3452
CW		 2693 }
2694
2695 /* And finally clear the reserved guard page */
782f1495 2696 ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
6c5566a8 2697
fa76da34
DV		 2698 if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
2699 struct i915_hw_ppgtt *ppgtt;
2700
2701 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2702 if (!ppgtt)
2703 return -ENOMEM;
2704
5c5f6457
DV		 2705 ret = __hw_ppgtt_init(dev, ppgtt);
2706 if (ret) {
2707 ppgtt->base.cleanup(&ppgtt->base);
2708 kfree(ppgtt);
2709 return ret;
2710 }
2711
2712 if (ppgtt->base.allocate_va_range)
2713 ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0,
2714 ppgtt->base.total);
4933d519 2715 if (ret) {
061dd493 2716 ppgtt->base.cleanup(&ppgtt->base);
4933d519 2717 kfree(ppgtt);
fa76da34 2718 return ret;
4933d519 2719 }
fa76da34 2720
5c5f6457
DV		 2721 ppgtt->base.clear_range(&ppgtt->base,
2722 ppgtt->base.start,
2723 ppgtt->base.total,
2724 true);
2725
fa76da34 2726 dev_priv->mm.aliasing_ppgtt = ppgtt;
0a878716
DV		 2727 WARN_ON(dev_priv->gtt.base.bind_vma != ggtt_bind_vma);
2728 dev_priv->gtt.base.bind_vma = aliasing_gtt_bind_vma;
fa76da34
DV		 2729 }
2730
6c5566a8 2731 return 0;
e76e9aeb
BW		 2732}
2733
d7e5008f
BW		 2734void i915_gem_init_global_gtt(struct drm_device *dev)
2735{
2736 struct drm_i915_private *dev_priv = dev->dev_private;
c44ef60e 2737 u64 gtt_size, mappable_size;
d7e5008f 2738
853ba5d2 2739 gtt_size = dev_priv->gtt.base.total;
93d18799 2740 mappable_size = dev_priv->gtt.mappable_end;
d7e5008f 2741
e78891ca 2742 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
e76e9aeb
BW		 2743}
2744
90d0a0e8
DV		 2745void i915_global_gtt_cleanup(struct drm_device *dev)
2746{
2747 struct drm_i915_private *dev_priv = dev->dev_private;
2748 struct i915_address_space *vm = &dev_priv->gtt.base;
2749
70e32544
DV		 2750 if (dev_priv->mm.aliasing_ppgtt) {
2751 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2752
2753 ppgtt->base.cleanup(&ppgtt->base);
2754 }
2755
90d0a0e8 2756 if (drm_mm_initialized(&vm->mm)) {
5dda8fa3
YZ		 2757 if (intel_vgpu_active(dev))
2758 intel_vgt_deballoon();
2759
90d0a0e8
DV		 2760 drm_mm_takedown(&vm->mm);
2761 list_del(&vm->global_link);
2762 }
2763
2764 vm->cleanup(vm);
2765}
70e32544 2766
2c642b07 2767static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
e76e9aeb
BW		 2768{
2769 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
2770 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
2771 return snb_gmch_ctl << 20;
2772}
2773
2c642b07 2774static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
9459d252
BW		 2775{
2776 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
2777 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
2778 if (bdw_gmch_ctl)
2779 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
562d55d9
BW		 2780
2781#ifdef CONFIG_X86_32
2782 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2783 if (bdw_gmch_ctl > 4)
2784 bdw_gmch_ctl = 4;
2785#endif
2786
9459d252
BW		 2787 return bdw_gmch_ctl << 20;
2788}
2789
2c642b07 2790static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
d7f25f23
DL		 2791{
2792 gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
2793 gmch_ctrl &= SNB_GMCH_GGMS_MASK;
2794
2795 if (gmch_ctrl)
2796 return 1 << (20 + gmch_ctrl);
2797
2798 return 0;
2799}
2800
2c642b07 2801static size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
e76e9aeb
BW		 2802{
2803 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
2804 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
2805 return snb_gmch_ctl << 25; /* 32 MB units */
2806}
2807
2c642b07 2808static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
9459d252
BW		 2809{
2810 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2811 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
2812 return bdw_gmch_ctl << 25; /* 32 MB units */
2813}
2814
d7f25f23
DL		 2815static size_t chv_get_stolen_size(u16 gmch_ctrl)
2816{
2817 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
2818 gmch_ctrl &= SNB_GMCH_GMS_MASK;
2819
2820 /*
2821 * 0x0 to 0x10: 32MB increments starting at 0MB
2822 * 0x11 to 0x16: 4MB increments starting at 8MB
2823 * 0x17 to 0x1d: 4MB increments start at 36MB
2824 */
2825 if (gmch_ctrl < 0x11)
2826 return gmch_ctrl << 25;
2827 else if (gmch_ctrl < 0x17)
2828 return (gmch_ctrl - 0x11 + 2) << 22;
2829 else
2830 return (gmch_ctrl - 0x17 + 9) << 22;
2831}
2832
66375014
DL		 2833static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
2834{
2835 gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2836 gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
2837
2838 if (gen9_gmch_ctl < 0xf0)
2839 return gen9_gmch_ctl << 25; /* 32 MB units */
2840 else
2841 /* 4MB increments starting at 0xf0 for 4MB */
2842 return (gen9_gmch_ctl - 0xf0 + 1) << 22;
2843}
2844
63340133
BW		 2845static int ggtt_probe_common(struct drm_device *dev,
2846 size_t gtt_size)
2847{
2848 struct drm_i915_private *dev_priv = dev->dev_private;
4ad2af1e 2849 struct i915_page_scratch *scratch_page;
21c34607 2850 phys_addr_t gtt_phys_addr;
63340133
BW		 2851
2852 /* For Modern GENs the PTEs and register space are split in the BAR */
21c34607 2853 gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
63340133
BW		 2854 (pci_resource_len(dev->pdev, 0) / 2);
2855
2a073f89
ID		 2856 /*
2857 * On BXT writes larger than 64 bit to the GTT pagetable range will be
2858 * dropped. For WC mappings in general we have 64 byte burst writes
2859 * when the WC buffer is flushed, so we can't use it, but have to
2860 * resort to an uncached mapping. The WC issue is easily caught by the
2861 * readback check when writing GTT PTE entries.
2862 */
2863 if (IS_BROXTON(dev))
2864 dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size);
2865 else
2866 dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
63340133
BW		 2867 if (!dev_priv->gtt.gsm) {
2868 DRM_ERROR("Failed to map the gtt page table\n");
2869 return -ENOMEM;
2870 }
2871
4ad2af1e
MK		 2872 scratch_page = alloc_scratch_page(dev);
2873 if (IS_ERR(scratch_page)) {
63340133
BW		 2874 DRM_ERROR("Scratch setup failed\n");
2875 /* iounmap will also get called at remove, but meh */
2876 iounmap(dev_priv->gtt.gsm);
4ad2af1e 2877 return PTR_ERR(scratch_page);
63340133
BW		 2878 }
2879
4ad2af1e
MK		 2880 dev_priv->gtt.base.scratch_page = scratch_page;
2881
2882 return 0;
63340133
BW		 2883}
2884
fbe5d36e
BW		 2885/* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2886 * bits. When using advanced contexts each context stores its own PAT, but
2887 * writing this data shouldn't be harmful even in those cases. */
ee0ce478 2888static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
fbe5d36e 2889{
fbe5d36e
BW		 2890 uint64_t pat;
2891
2892 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
2893 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
2894 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
2895 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
2896 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
2897 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
2898 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
2899 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
2900
d6a8b72e
RV		 2901 if (!USES_PPGTT(dev_priv->dev))
2902 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2903 * so RTL will always use the value corresponding to
2904 * pat_sel = 000".
2905 * So let's disable cache for GGTT to avoid screen corruptions.
2906 * MOCS still can be used though.
2907 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2908 * before this patch, i.e. the same uncached + snooping access
2909 * like on gen6/7 seems to be in effect.
2910 * - So this just fixes blitter/render access. Again it looks
2911 * like it's not just uncached access, but uncached + snooping.
2912 * So we can still hold onto all our assumptions wrt cpu
2913 * clflushing on LLC machines.
2914 */
2915 pat = GEN8_PPAT(0, GEN8_PPAT_UC);
2916
fbe5d36e
BW		 2917 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2918 * write would work. */
7e435ad2
VS		 2919 I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
2920 I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
fbe5d36e
BW		 2921}
2922
ee0ce478
VS		 2923static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
2924{
2925 uint64_t pat;
2926
2927 /*
2928 * Map WB on BDW to snooped on CHV.
2929 *
2930 * Only the snoop bit has meaning for CHV, the rest is
2931 * ignored.
2932 *
cf3d262e
VS		 2933 * The hardware will never snoop for certain types of accesses:
2934 * - CPU GTT (GMADR->GGTT->no snoop->memory)
2935 * - PPGTT page tables
2936 * - some other special cycles
2937 *
2938 * As with BDW, we also need to consider the following for GT accesses:
2939 * "For GGTT, there is NO pat_sel[2:0] from the entry,
2940 * so RTL will always use the value corresponding to
2941 * pat_sel = 000".
2942 * Which means we must set the snoop bit in PAT entry 0
2943 * in order to keep the global status page working.
ee0ce478
VS		 2944 */
2945 pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
2946 GEN8_PPAT(1, 0) |
2947 GEN8_PPAT(2, 0) |
2948 GEN8_PPAT(3, 0) |
2949 GEN8_PPAT(4, CHV_PPAT_SNOOP) |
2950 GEN8_PPAT(5, CHV_PPAT_SNOOP) |
2951 GEN8_PPAT(6, CHV_PPAT_SNOOP) |
2952 GEN8_PPAT(7, CHV_PPAT_SNOOP);
2953
7e435ad2
VS		 2954 I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
2955 I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
ee0ce478
VS		 2956}
2957
63340133 2958static int gen8_gmch_probe(struct drm_device *dev,
c44ef60e 2959 u64 *gtt_total,
63340133
BW		 2960 size_t *stolen,
2961 phys_addr_t *mappable_base,
c44ef60e 2962 u64 *mappable_end)
63340133
BW		 2963{
2964 struct drm_i915_private *dev_priv = dev->dev_private;
c44ef60e 2965 u64 gtt_size;
63340133
BW		 2966 u16 snb_gmch_ctl;
2967 int ret;
2968
2969 /* TODO: We're not aware of mappable constraints on gen8 yet */
2970 *mappable_base = pci_resource_start(dev->pdev, 2);
2971 *mappable_end = pci_resource_len(dev->pdev, 2);
2972
2973 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
2974 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
2975
2976 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2977
66375014
DL		 2978 if (INTEL_INFO(dev)->gen >= 9) {
2979 *stolen = gen9_get_stolen_size(snb_gmch_ctl);
2980 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2981 } else if (IS_CHERRYVIEW(dev)) {
d7f25f23
DL		 2982 *stolen = chv_get_stolen_size(snb_gmch_ctl);
2983 gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
2984 } else {
2985 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
2986 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2987 }
63340133 2988
07749ef3 2989 *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
63340133 2990
5a4e33a3 2991 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
ee0ce478
VS		 2992 chv_setup_private_ppat(dev_priv);
2993 else
2994 bdw_setup_private_ppat(dev_priv);
fbe5d36e 2995
63340133
BW		 2996 ret = ggtt_probe_common(dev, gtt_size);
2997
94ec8f61
BW		 2998 dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
2999 dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
777dc5bb
DV		 3000 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
3001 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
63340133
BW		 3002
3003 return ret;
3004}
3005
baa09f5f 3006static int gen6_gmch_probe(struct drm_device *dev,
c44ef60e 3007 u64 *gtt_total,
41907ddc
BW		 3008 size_t *stolen,
3009 phys_addr_t *mappable_base,
c44ef60e 3010 u64 *mappable_end)
e76e9aeb
BW		 3011{
3012 struct drm_i915_private *dev_priv = dev->dev_private;
baa09f5f 3013 unsigned int gtt_size;
e76e9aeb 3014 u16 snb_gmch_ctl;
e76e9aeb
BW		 3015 int ret;
3016
41907ddc
BW		 3017 *mappable_base = pci_resource_start(dev->pdev, 2);
3018 *mappable_end = pci_resource_len(dev->pdev, 2);
3019
baa09f5f
BW		 3020 /* 64/512MB is the current min/max we actually know of, but this is just
3021 * a coarse sanity check.
e76e9aeb 3022 */
41907ddc 3023 if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
c44ef60e 3024 DRM_ERROR("Unknown GMADR size (%llx)\n",
baa09f5f
BW		 3025 dev_priv->gtt.mappable_end);
3026 return -ENXIO;
e76e9aeb
BW		 3027 }
3028
e76e9aeb
BW		 3029 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
3030 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
e76e9aeb 3031 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
e76e9aeb 3032
c4ae25ec 3033 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
a93e4161 3034
63340133 3035 gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
07749ef3 3036 *gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
e76e9aeb 3037
63340133 3038 ret = ggtt_probe_common(dev, gtt_size);
e76e9aeb 3039
853ba5d2
BW		 3040 dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
3041 dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
777dc5bb
DV		 3042 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
3043 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
7faf1ab2 3044
e76e9aeb
BW		 3045 return ret;
3046}
3047
853ba5d2 3048static void gen6_gmch_remove(struct i915_address_space *vm)
e76e9aeb 3049{
853ba5d2
BW		 3050
3051 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
5ed16782 3052
853ba5d2 3053 iounmap(gtt->gsm);
4ad2af1e 3054 free_scratch_page(vm->dev, vm->scratch_page);
644ec02b 3055}
baa09f5f
BW		 3056
3057static int i915_gmch_probe(struct drm_device *dev,
c44ef60e 3058 u64 *gtt_total,
41907ddc
BW		 3059 size_t *stolen,
3060 phys_addr_t *mappable_base,
c44ef60e 3061 u64 *mappable_end)
baa09f5f
BW		 3062{
3063 struct drm_i915_private *dev_priv = dev->dev_private;
3064 int ret;
3065
baa09f5f
BW		 3066 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
3067 if (!ret) {
3068 DRM_ERROR("failed to set up gmch\n");
3069 return -EIO;
3070 }
3071
41907ddc 3072 intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
baa09f5f
BW		 3073
3074 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
d369d2d9 3075 dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries;
853ba5d2 3076 dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
d369d2d9
DV		 3077 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
3078 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
baa09f5f 3079
c0a7f818
CW		 3080 if (unlikely(dev_priv->gtt.do_idle_maps))
3081 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
3082
baa09f5f
BW		 3083 return 0;
3084}
3085
853ba5d2 3086static void i915_gmch_remove(struct i915_address_space *vm)
baa09f5f
BW		 3087{
3088 intel_gmch_remove();
3089}
3090
3091int i915_gem_gtt_init(struct drm_device *dev)
3092{
3093 struct drm_i915_private *dev_priv = dev->dev_private;
3094 struct i915_gtt *gtt = &dev_priv->gtt;
baa09f5f
BW		 3095 int ret;
3096
baa09f5f 3097 if (INTEL_INFO(dev)->gen <= 5) {
b2f21b4d 3098 gtt->gtt_probe = i915_gmch_probe;
853ba5d2 3099 gtt->base.cleanup = i915_gmch_remove;
63340133 3100 } else if (INTEL_INFO(dev)->gen < 8) {
b2f21b4d 3101 gtt->gtt_probe = gen6_gmch_probe;
853ba5d2 3102 gtt->base.cleanup = gen6_gmch_remove;
4d15c145 3103 if (IS_HASWELL(dev) && dev_priv->ellc_size)
853ba5d2 3104 gtt->base.pte_encode = iris_pte_encode;
4d15c145 3105 else if (IS_HASWELL(dev))
853ba5d2 3106 gtt->base.pte_encode = hsw_pte_encode;
b2f21b4d 3107 else if (IS_VALLEYVIEW(dev))
853ba5d2 3108 gtt->base.pte_encode = byt_pte_encode;
350ec881
CW		 3109 else if (INTEL_INFO(dev)->gen >= 7)
3110 gtt->base.pte_encode = ivb_pte_encode;
b2f21b4d 3111 else
350ec881 3112 gtt->base.pte_encode = snb_pte_encode;
63340133
BW		 3113 } else {
3114 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
3115 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
baa09f5f
BW		 3116 }
3117
c114f76a
MK		 3118 gtt->base.dev = dev;
3119
853ba5d2 3120 ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
b2f21b4d 3121 &gtt->mappable_base, &gtt->mappable_end);
a54c0c27 3122 if (ret)
baa09f5f 3123 return ret;
baa09f5f 3124
baa09f5f 3125 /* GMADR is the PCI mmio aperture into the global GTT. */
c44ef60e 3126 DRM_INFO("Memory usable by graphics device = %lluM\n",
853ba5d2 3127 gtt->base.total >> 20);
c44ef60e 3128 DRM_DEBUG_DRIVER("GMADR size = %lldM\n", gtt->mappable_end >> 20);
b2f21b4d 3129 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
5db6c735
DV		 3130#ifdef CONFIG_INTEL_IOMMU
3131 if (intel_iommu_gfx_mapped)
3132 DRM_INFO("VT-d active for gfx access\n");
3133#endif
cfa7c862
DV		 3134 /*
3135 * i915.enable_ppgtt is read-only, so do an early pass to validate the
3136 * user's requested state against the hardware/driver capabilities. We
3137 * do this now so that we can print out any log messages once rather
3138 * than every time we check intel_enable_ppgtt().
3139 */
3140 i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
3141 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
baa09f5f
BW		 3142
3143 return 0;
3144}
6f65e29a 3145
fa42331b
DV		 3146void i915_gem_restore_gtt_mappings(struct drm_device *dev)
3147{
3148 struct drm_i915_private *dev_priv = dev->dev_private;
3149 struct drm_i915_gem_object *obj;
3150 struct i915_address_space *vm;
2c3d9984
TU		 3151 struct i915_vma *vma;
3152 bool flush;
fa42331b
DV		 3153
3154 i915_check_and_clear_faults(dev);
3155
3156 /* First fill our portion of the GTT with scratch pages */
3157 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
3158 dev_priv->gtt.base.start,
3159 dev_priv->gtt.base.total,
3160 true);
3161
2c3d9984
TU		 3162 /* Cache flush objects bound into GGTT and rebind them. */
3163 vm = &dev_priv->gtt.base;
fa42331b 3164 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
2c3d9984
TU		 3165 flush = false;
3166 list_for_each_entry(vma, &obj->vma_list, vma_link) {
3167 if (vma->vm != vm)
3168 continue;
fa42331b 3169
2c3d9984
TU		 3170 WARN_ON(i915_vma_bind(vma, obj->cache_level,
3171 PIN_UPDATE));
fa42331b 3172
2c3d9984
TU		 3173 flush = true;
3174 }
3175
3176 if (flush)
3177 i915_gem_clflush_object(obj, obj->pin_display);
3178 }
fa42331b
DV		 3179
3180 if (INTEL_INFO(dev)->gen >= 8) {
3181 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
3182 chv_setup_private_ppat(dev_priv);
3183 else
3184 bdw_setup_private_ppat(dev_priv);
3185
3186 return;
3187 }
3188
3189 if (USES_PPGTT(dev)) {
3190 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
3191 /* TODO: Perhaps it shouldn't be gen6 specific */
3192
3193 struct i915_hw_ppgtt *ppgtt =
3194 container_of(vm, struct i915_hw_ppgtt,
3195 base);
3196
3197 if (i915_is_ggtt(vm))
3198 ppgtt = dev_priv->mm.aliasing_ppgtt;
3199
3200 gen6_write_page_range(dev_priv, &ppgtt->pd,
3201 0, ppgtt->base.total);
3202 }
3203 }
3204
3205 i915_ggtt_flush(dev_priv);
3206}
3207
ec7adb6e
JL		 3208static struct i915_vma *
3209__i915_gem_vma_create(struct drm_i915_gem_object *obj,
3210 struct i915_address_space *vm,
3211 const struct i915_ggtt_view *ggtt_view)
6f65e29a 3212{
dabde5c7 3213 struct i915_vma *vma;
6f65e29a 3214
ec7adb6e
JL		 3215 if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
3216 return ERR_PTR(-EINVAL);
e20d2ab7
CW		 3217
3218 vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL);
dabde5c7
DC		 3219 if (vma == NULL)
3220 return ERR_PTR(-ENOMEM);
ec7adb6e 3221
6f65e29a
BW		 3222 INIT_LIST_HEAD(&vma->vma_link);
3223 INIT_LIST_HEAD(&vma->mm_list);
3224 INIT_LIST_HEAD(&vma->exec_list);
3225 vma->vm = vm;
3226 vma->obj = obj;
3227
777dc5bb 3228 if (i915_is_ggtt(vm))
ec7adb6e 3229 vma->ggtt_view = *ggtt_view;
6f65e29a 3230
f7635669
TU		 3231 list_add_tail(&vma->vma_link, &obj->vma_list);
3232 if (!i915_is_ggtt(vm))
e07f0552 3233 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
6f65e29a
BW		 3234
3235 return vma;
3236}
3237
3238struct i915_vma *
ec7adb6e
JL		 3239i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3240 struct i915_address_space *vm)
3241{
3242 struct i915_vma *vma;
3243
3244 vma = i915_gem_obj_to_vma(obj, vm);
3245 if (!vma)
3246 vma = __i915_gem_vma_create(obj, vm,
3247 i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL);
3248
3249 return vma;
3250}
3251
3252struct i915_vma *
3253i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
fe14d5f4 3254 const struct i915_ggtt_view *view)
6f65e29a 3255{
ec7adb6e 3256 struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
6f65e29a
BW		 3257 struct i915_vma *vma;
3258
ec7adb6e
JL		 3259 if (WARN_ON(!view))
3260 return ERR_PTR(-EINVAL);
3261
3262 vma = i915_gem_obj_to_ggtt_view(obj, view);
3263
3264 if (IS_ERR(vma))
3265 return vma;
3266
6f65e29a 3267 if (!vma)
ec7adb6e 3268 vma = __i915_gem_vma_create(obj, ggtt, view);
6f65e29a
BW		 3269
3270 return vma;
ec7adb6e 3271
6f65e29a 3272}
fe14d5f4 3273
804beb4b
TU		 3274static struct scatterlist *
3275rotate_pages(dma_addr_t *in, unsigned int offset,
3276 unsigned int width, unsigned int height,
3277 struct sg_table *st, struct scatterlist *sg)
50470bb0
TU		 3278{
3279 unsigned int column, row;
3280 unsigned int src_idx;
50470bb0 3281
804beb4b
TU		 3282 if (!sg) {
3283 st->nents = 0;
3284 sg = st->sgl;
3285 }
50470bb0
TU		 3286
3287 for (column = 0; column < width; column++) {
3288 src_idx = width * (height - 1) + column;
3289 for (row = 0; row < height; row++) {
3290 st->nents++;
3291 /* We don't need the pages, but need to initialize
3292 * the entries so the sg list can be happily traversed.
3293 * The only thing we need are DMA addresses.
3294 */
3295 sg_set_page(sg, NULL, PAGE_SIZE, 0);
804beb4b 3296 sg_dma_address(sg) = in[offset + src_idx];
50470bb0
TU		 3297 sg_dma_len(sg) = PAGE_SIZE;
3298 sg = sg_next(sg);
3299 src_idx -= width;
3300 }
3301 }
804beb4b
TU		 3302
3303 return sg;
50470bb0
TU		 3304}
3305
3306static struct sg_table *
3307intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view,
3308 struct drm_i915_gem_object *obj)
3309{
50470bb0 3310 struct intel_rotation_info *rot_info = &ggtt_view->rotation_info;
84fe03f7 3311 unsigned int size_pages = rot_info->size >> PAGE_SHIFT;
89e3e142 3312 unsigned int size_pages_uv;
50470bb0
TU		 3313 struct sg_page_iter sg_iter;
3314 unsigned long i;
3315 dma_addr_t *page_addr_list;
3316 struct sg_table *st;
89e3e142
TU		 3317 unsigned int uv_start_page;
3318 struct scatterlist *sg;
1d00dad5 3319 int ret = -ENOMEM;
50470bb0 3320
50470bb0 3321 /* Allocate a temporary list of source pages for random access. */
84fe03f7
TU		 3322 page_addr_list = drm_malloc_ab(obj->base.size / PAGE_SIZE,
3323 sizeof(dma_addr_t));
50470bb0
TU		 3324 if (!page_addr_list)
3325 return ERR_PTR(ret);
3326
89e3e142
TU		 3327 /* Account for UV plane with NV12. */
3328 if (rot_info->pixel_format == DRM_FORMAT_NV12)
3329 size_pages_uv = rot_info->size_uv >> PAGE_SHIFT;
3330 else
3331 size_pages_uv = 0;
3332
50470bb0
TU		 3333 /* Allocate target SG list. */
3334 st = kmalloc(sizeof(*st), GFP_KERNEL);
3335 if (!st)
3336 goto err_st_alloc;
3337
89e3e142 3338 ret = sg_alloc_table(st, size_pages + size_pages_uv, GFP_KERNEL);
50470bb0
TU		 3339 if (ret)
3340 goto err_sg_alloc;
3341
3342 /* Populate source page list from the object. */
3343 i = 0;
3344 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
3345 page_addr_list[i] = sg_page_iter_dma_address(&sg_iter);
3346 i++;
3347 }
3348
3349 /* Rotate the pages. */
89e3e142 3350 sg = rotate_pages(page_addr_list, 0,
84fe03f7 3351 rot_info->width_pages, rot_info->height_pages,
804beb4b 3352 st, NULL);
50470bb0 3353
89e3e142
TU		 3354 /* Append the UV plane if NV12. */
3355 if (rot_info->pixel_format == DRM_FORMAT_NV12) {
3356 uv_start_page = size_pages;
3357
3358 /* Check for tile-row un-alignment. */
3359 if (offset_in_page(rot_info->uv_offset))
3360 uv_start_page--;
3361
dedf278c
TU		 3362 rot_info->uv_start_page = uv_start_page;
3363
89e3e142
TU		 3364 rotate_pages(page_addr_list, uv_start_page,
3365 rot_info->width_pages_uv,
3366 rot_info->height_pages_uv,
3367 st, sg);
3368 }
3369
50470bb0 3370 DRM_DEBUG_KMS(
89e3e142 3371 "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u plane 0)).\n",
c9f8fd2d 3372 obj->base.size, rot_info->pitch, rot_info->height,
84fe03f7 3373 rot_info->pixel_format, rot_info->width_pages,
89e3e142
TU		 3374 rot_info->height_pages, size_pages + size_pages_uv,
3375 size_pages);
50470bb0
TU		 3376
3377 drm_free_large(page_addr_list);
3378
3379 return st;
3380
3381err_sg_alloc:
3382 kfree(st);
3383err_st_alloc:
3384 drm_free_large(page_addr_list);
3385
3386 DRM_DEBUG_KMS(
89e3e142 3387 "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u plane 0))\n",
c9f8fd2d 3388 obj->base.size, ret, rot_info->pitch, rot_info->height,
84fe03f7 3389 rot_info->pixel_format, rot_info->width_pages,
89e3e142
TU		 3390 rot_info->height_pages, size_pages + size_pages_uv,
3391 size_pages);
50470bb0
TU		 3392 return ERR_PTR(ret);
3393}
ec7adb6e 3394
8bd7ef16
JL		 3395static struct sg_table *
3396intel_partial_pages(const struct i915_ggtt_view *view,
3397 struct drm_i915_gem_object *obj)
3398{
3399 struct sg_table *st;
3400 struct scatterlist *sg;
3401 struct sg_page_iter obj_sg_iter;
3402 int ret = -ENOMEM;
3403
3404 st = kmalloc(sizeof(*st), GFP_KERNEL);
3405 if (!st)
3406 goto err_st_alloc;
3407
3408 ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL);
3409 if (ret)
3410 goto err_sg_alloc;
3411
3412 sg = st->sgl;
3413 st->nents = 0;
3414 for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents,
3415 view->params.partial.offset)
3416 {
3417 if (st->nents >= view->params.partial.size)
3418 break;
3419
3420 sg_set_page(sg, NULL, PAGE_SIZE, 0);
3421 sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter);
3422 sg_dma_len(sg) = PAGE_SIZE;
3423
3424 sg = sg_next(sg);
3425 st->nents++;
3426 }
3427
3428 return st;
3429
3430err_sg_alloc:
3431 kfree(st);
3432err_st_alloc:
3433 return ERR_PTR(ret);
3434}
3435
70b9f6f8 3436static int
50470bb0 3437i915_get_ggtt_vma_pages(struct i915_vma *vma)
fe14d5f4 3438{
50470bb0
TU		 3439 int ret = 0;
3440
fe14d5f4
TU		 3441 if (vma->ggtt_view.pages)
3442 return 0;
3443
3444 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
3445 vma->ggtt_view.pages = vma->obj->pages;
50470bb0
TU		 3446 else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
3447 vma->ggtt_view.pages =
3448 intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj);
8bd7ef16
JL		 3449 else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL)
3450 vma->ggtt_view.pages =
3451 intel_partial_pages(&vma->ggtt_view, vma->obj);
fe14d5f4
TU		 3452 else
3453 WARN_ONCE(1, "GGTT view %u not implemented!\n",
3454 vma->ggtt_view.type);
3455
3456 if (!vma->ggtt_view.pages) {
ec7adb6e 3457 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
fe14d5f4 3458 vma->ggtt_view.type);
50470bb0
TU		 3459 ret = -EINVAL;
3460 } else if (IS_ERR(vma->ggtt_view.pages)) {
3461 ret = PTR_ERR(vma->ggtt_view.pages);
3462 vma->ggtt_view.pages = NULL;
3463 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
3464 vma->ggtt_view.type, ret);
fe14d5f4
TU		 3465 }
3466
50470bb0 3467 return ret;
fe14d5f4
TU		 3468}
3469
3470/**
3471 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
3472 * @vma: VMA to map
3473 * @cache_level: mapping cache level
3474 * @flags: flags like global or local mapping
3475 *
3476 * DMA addresses are taken from the scatter-gather table of this object (or of
3477 * this VMA in case of non-default GGTT views) and PTE entries set up.
3478 * Note that DMA addresses are also the only part of the SG table we care about.
3479 */
3480int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
3481 u32 flags)
3482{
75d04a37
MK		 3483 int ret;
3484 u32 bind_flags;
1d335d1b 3485
75d04a37
MK		 3486 if (WARN_ON(flags == 0))
3487 return -EINVAL;
1d335d1b 3488
75d04a37 3489 bind_flags = 0;
0875546c
DV		 3490 if (flags & PIN_GLOBAL)
3491 bind_flags |= GLOBAL_BIND;
3492 if (flags & PIN_USER)
3493 bind_flags |= LOCAL_BIND;
3494
3495 if (flags & PIN_UPDATE)
3496 bind_flags |= vma->bound;
3497 else
3498 bind_flags &= ~vma->bound;
3499
75d04a37
MK		 3500 if (bind_flags == 0)
3501 return 0;
3502
3503 if (vma->bound == 0 && vma->vm->allocate_va_range) {
3504 trace_i915_va_alloc(vma->vm,
3505 vma->node.start,
3506 vma->node.size,
3507 VM_TO_TRACE_NAME(vma->vm));
3508
b2dd4511
MK		 3509 /* XXX: i915_vma_pin() will fix this +- hack */
3510 vma->pin_count++;
75d04a37
MK		 3511 ret = vma->vm->allocate_va_range(vma->vm,
3512 vma->node.start,
3513 vma->node.size);
b2dd4511 3514 vma->pin_count--;
75d04a37
MK		 3515 if (ret)
3516 return ret;
3517 }
3518
3519 ret = vma->vm->bind_vma(vma, cache_level, bind_flags);
70b9f6f8
DV		 3520 if (ret)
3521 return ret;
0875546c
DV		 3522
3523 vma->bound |= bind_flags;
fe14d5f4
TU		 3524
3525 return 0;
3526}
91e6711e
JL		 3527
3528/**
3529 * i915_ggtt_view_size - Get the size of a GGTT view.
3530 * @obj: Object the view is of.
3531 * @view: The view in question.
3532 *
3533 * @return The size of the GGTT view in bytes.
3534 */
3535size_t
3536i915_ggtt_view_size(struct drm_i915_gem_object *obj,
3537 const struct i915_ggtt_view *view)
3538{
9e759ff1 3539 if (view->type == I915_GGTT_VIEW_NORMAL) {
91e6711e 3540 return obj->base.size;
9e759ff1
TU		 3541 } else if (view->type == I915_GGTT_VIEW_ROTATED) {
3542 return view->rotation_info.size;
8bd7ef16
JL		 3543 } else if (view->type == I915_GGTT_VIEW_PARTIAL) {
3544 return view->params.partial.size << PAGE_SHIFT;
91e6711e
JL		 3545 } else {
3546 WARN_ONCE(1, "GGTT view %u not implemented!\n", view->type);
3547 return obj->base.size;
3548 }
3549}
Linux 6.x block layer and io_uring tree(s)