Commit | Line | Data |
---|---|---|
54cf91dc CW |
1 | /* |
2 | * Copyright © 2008,2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Chris Wilson <chris@chris-wilson.co.uk> | |
26 | * | |
27 | */ | |
28 | ||
760285e7 DH |
29 | #include <drm/drmP.h> |
30 | #include <drm/i915_drm.h> | |
54cf91dc CW |
31 | #include "i915_drv.h" |
32 | #include "i915_trace.h" | |
33 | #include "intel_drv.h" | |
f45b5557 | 34 | #include <linux/dma_remapping.h> |
54cf91dc | 35 | |
67731b87 CW |
36 | struct eb_objects { |
37 | int and; | |
38 | struct hlist_head buckets[0]; | |
39 | }; | |
40 | ||
41 | static struct eb_objects * | |
42 | eb_create(int size) | |
43 | { | |
44 | struct eb_objects *eb; | |
45 | int count = PAGE_SIZE / sizeof(struct hlist_head) / 2; | |
41783eea | 46 | BUILD_BUG_ON(!is_power_of_2(PAGE_SIZE / sizeof(struct hlist_head))); |
67731b87 CW |
47 | while (count > size) |
48 | count >>= 1; | |
49 | eb = kzalloc(count*sizeof(struct hlist_head) + | |
50 | sizeof(struct eb_objects), | |
51 | GFP_KERNEL); | |
52 | if (eb == NULL) | |
53 | return eb; | |
54 | ||
55 | eb->and = count - 1; | |
56 | return eb; | |
57 | } | |
58 | ||
59 | static void | |
60 | eb_reset(struct eb_objects *eb) | |
61 | { | |
62 | memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head)); | |
63 | } | |
64 | ||
65 | static void | |
66 | eb_add_object(struct eb_objects *eb, struct drm_i915_gem_object *obj) | |
67 | { | |
68 | hlist_add_head(&obj->exec_node, | |
69 | &eb->buckets[obj->exec_handle & eb->and]); | |
70 | } | |
71 | ||
72 | static struct drm_i915_gem_object * | |
73 | eb_get_object(struct eb_objects *eb, unsigned long handle) | |
74 | { | |
75 | struct hlist_head *head; | |
76 | struct hlist_node *node; | |
77 | struct drm_i915_gem_object *obj; | |
78 | ||
79 | head = &eb->buckets[handle & eb->and]; | |
80 | hlist_for_each(node, head) { | |
81 | obj = hlist_entry(node, struct drm_i915_gem_object, exec_node); | |
82 | if (obj->exec_handle == handle) | |
83 | return obj; | |
84 | } | |
85 | ||
86 | return NULL; | |
87 | } | |
88 | ||
89 | static void | |
90 | eb_destroy(struct eb_objects *eb) | |
91 | { | |
92 | kfree(eb); | |
93 | } | |
94 | ||
dabdfe02 CW |
95 | static inline int use_cpu_reloc(struct drm_i915_gem_object *obj) |
96 | { | |
97 | return (obj->base.write_domain == I915_GEM_DOMAIN_CPU || | |
504c7267 | 98 | !obj->map_and_fenceable || |
dabdfe02 CW |
99 | obj->cache_level != I915_CACHE_NONE); |
100 | } | |
101 | ||
54cf91dc CW |
102 | static int |
103 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, | |
67731b87 | 104 | struct eb_objects *eb, |
54cf91dc CW |
105 | struct drm_i915_gem_relocation_entry *reloc) |
106 | { | |
107 | struct drm_device *dev = obj->base.dev; | |
108 | struct drm_gem_object *target_obj; | |
149c8407 | 109 | struct drm_i915_gem_object *target_i915_obj; |
54cf91dc CW |
110 | uint32_t target_offset; |
111 | int ret = -EINVAL; | |
112 | ||
67731b87 CW |
113 | /* we've already hold a reference to all valid objects */ |
114 | target_obj = &eb_get_object(eb, reloc->target_handle)->base; | |
115 | if (unlikely(target_obj == NULL)) | |
54cf91dc CW |
116 | return -ENOENT; |
117 | ||
149c8407 DV |
118 | target_i915_obj = to_intel_bo(target_obj); |
119 | target_offset = target_i915_obj->gtt_offset; | |
54cf91dc | 120 | |
e844b990 EA |
121 | /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and |
122 | * pipe_control writes because the gpu doesn't properly redirect them | |
123 | * through the ppgtt for non_secure batchbuffers. */ | |
124 | if (unlikely(IS_GEN6(dev) && | |
125 | reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION && | |
126 | !target_i915_obj->has_global_gtt_mapping)) { | |
127 | i915_gem_gtt_bind_object(target_i915_obj, | |
128 | target_i915_obj->cache_level); | |
129 | } | |
130 | ||
54cf91dc CW |
131 | /* The target buffer should have appeared before us in the |
132 | * exec_object list, so it should have a GTT space bound by now. | |
133 | */ | |
b8f7ab17 | 134 | if (unlikely(target_offset == 0)) { |
ff240199 | 135 | DRM_DEBUG("No GTT space found for object %d\n", |
54cf91dc | 136 | reloc->target_handle); |
67731b87 | 137 | return ret; |
54cf91dc CW |
138 | } |
139 | ||
140 | /* Validate that the target is in a valid r/w GPU domain */ | |
b8f7ab17 | 141 | if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { |
ff240199 | 142 | DRM_DEBUG("reloc with multiple write domains: " |
54cf91dc CW |
143 | "obj %p target %d offset %d " |
144 | "read %08x write %08x", | |
145 | obj, reloc->target_handle, | |
146 | (int) reloc->offset, | |
147 | reloc->read_domains, | |
148 | reloc->write_domain); | |
67731b87 | 149 | return ret; |
54cf91dc | 150 | } |
4ca4a250 DV |
151 | if (unlikely((reloc->write_domain | reloc->read_domains) |
152 | & ~I915_GEM_GPU_DOMAINS)) { | |
ff240199 | 153 | DRM_DEBUG("reloc with read/write non-GPU domains: " |
54cf91dc CW |
154 | "obj %p target %d offset %d " |
155 | "read %08x write %08x", | |
156 | obj, reloc->target_handle, | |
157 | (int) reloc->offset, | |
158 | reloc->read_domains, | |
159 | reloc->write_domain); | |
67731b87 | 160 | return ret; |
54cf91dc | 161 | } |
b8f7ab17 CW |
162 | if (unlikely(reloc->write_domain && target_obj->pending_write_domain && |
163 | reloc->write_domain != target_obj->pending_write_domain)) { | |
ff240199 | 164 | DRM_DEBUG("Write domain conflict: " |
54cf91dc CW |
165 | "obj %p target %d offset %d " |
166 | "new %08x old %08x\n", | |
167 | obj, reloc->target_handle, | |
168 | (int) reloc->offset, | |
169 | reloc->write_domain, | |
170 | target_obj->pending_write_domain); | |
67731b87 | 171 | return ret; |
54cf91dc CW |
172 | } |
173 | ||
174 | target_obj->pending_read_domains |= reloc->read_domains; | |
175 | target_obj->pending_write_domain |= reloc->write_domain; | |
176 | ||
177 | /* If the relocation already has the right value in it, no | |
178 | * more work needs to be done. | |
179 | */ | |
180 | if (target_offset == reloc->presumed_offset) | |
67731b87 | 181 | return 0; |
54cf91dc CW |
182 | |
183 | /* Check that the relocation address is valid... */ | |
b8f7ab17 | 184 | if (unlikely(reloc->offset > obj->base.size - 4)) { |
ff240199 | 185 | DRM_DEBUG("Relocation beyond object bounds: " |
54cf91dc CW |
186 | "obj %p target %d offset %d size %d.\n", |
187 | obj, reloc->target_handle, | |
188 | (int) reloc->offset, | |
189 | (int) obj->base.size); | |
67731b87 | 190 | return ret; |
54cf91dc | 191 | } |
b8f7ab17 | 192 | if (unlikely(reloc->offset & 3)) { |
ff240199 | 193 | DRM_DEBUG("Relocation not 4-byte aligned: " |
54cf91dc CW |
194 | "obj %p target %d offset %d.\n", |
195 | obj, reloc->target_handle, | |
196 | (int) reloc->offset); | |
67731b87 | 197 | return ret; |
54cf91dc CW |
198 | } |
199 | ||
dabdfe02 CW |
200 | /* We can't wait for rendering with pagefaults disabled */ |
201 | if (obj->active && in_atomic()) | |
202 | return -EFAULT; | |
203 | ||
54cf91dc | 204 | reloc->delta += target_offset; |
dabdfe02 | 205 | if (use_cpu_reloc(obj)) { |
54cf91dc CW |
206 | uint32_t page_offset = reloc->offset & ~PAGE_MASK; |
207 | char *vaddr; | |
208 | ||
dabdfe02 CW |
209 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
210 | if (ret) | |
211 | return ret; | |
212 | ||
9da3da66 CW |
213 | vaddr = kmap_atomic(i915_gem_object_get_page(obj, |
214 | reloc->offset >> PAGE_SHIFT)); | |
54cf91dc CW |
215 | *(uint32_t *)(vaddr + page_offset) = reloc->delta; |
216 | kunmap_atomic(vaddr); | |
217 | } else { | |
218 | struct drm_i915_private *dev_priv = dev->dev_private; | |
219 | uint32_t __iomem *reloc_entry; | |
220 | void __iomem *reloc_page; | |
221 | ||
7b09638f CW |
222 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
223 | if (ret) | |
224 | return ret; | |
225 | ||
226 | ret = i915_gem_object_put_fence(obj); | |
54cf91dc | 227 | if (ret) |
67731b87 | 228 | return ret; |
54cf91dc CW |
229 | |
230 | /* Map the page containing the relocation we're going to perform. */ | |
231 | reloc->offset += obj->gtt_offset; | |
232 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, | |
233 | reloc->offset & PAGE_MASK); | |
234 | reloc_entry = (uint32_t __iomem *) | |
235 | (reloc_page + (reloc->offset & ~PAGE_MASK)); | |
236 | iowrite32(reloc->delta, reloc_entry); | |
237 | io_mapping_unmap_atomic(reloc_page); | |
238 | } | |
239 | ||
240 | /* and update the user's relocation entry */ | |
241 | reloc->presumed_offset = target_offset; | |
242 | ||
67731b87 | 243 | return 0; |
54cf91dc CW |
244 | } |
245 | ||
246 | static int | |
247 | i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj, | |
6fe4f140 | 248 | struct eb_objects *eb) |
54cf91dc | 249 | { |
1d83f442 CW |
250 | #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) |
251 | struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)]; | |
54cf91dc | 252 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
6fe4f140 | 253 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
1d83f442 | 254 | int remain, ret; |
54cf91dc CW |
255 | |
256 | user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr; | |
54cf91dc | 257 | |
1d83f442 CW |
258 | remain = entry->relocation_count; |
259 | while (remain) { | |
260 | struct drm_i915_gem_relocation_entry *r = stack_reloc; | |
261 | int count = remain; | |
262 | if (count > ARRAY_SIZE(stack_reloc)) | |
263 | count = ARRAY_SIZE(stack_reloc); | |
264 | remain -= count; | |
265 | ||
266 | if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0]))) | |
54cf91dc CW |
267 | return -EFAULT; |
268 | ||
1d83f442 CW |
269 | do { |
270 | u64 offset = r->presumed_offset; | |
54cf91dc | 271 | |
1d83f442 CW |
272 | ret = i915_gem_execbuffer_relocate_entry(obj, eb, r); |
273 | if (ret) | |
274 | return ret; | |
275 | ||
276 | if (r->presumed_offset != offset && | |
277 | __copy_to_user_inatomic(&user_relocs->presumed_offset, | |
278 | &r->presumed_offset, | |
279 | sizeof(r->presumed_offset))) { | |
280 | return -EFAULT; | |
281 | } | |
282 | ||
283 | user_relocs++; | |
284 | r++; | |
285 | } while (--count); | |
54cf91dc CW |
286 | } |
287 | ||
288 | return 0; | |
1d83f442 | 289 | #undef N_RELOC |
54cf91dc CW |
290 | } |
291 | ||
292 | static int | |
293 | i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj, | |
67731b87 | 294 | struct eb_objects *eb, |
54cf91dc CW |
295 | struct drm_i915_gem_relocation_entry *relocs) |
296 | { | |
6fe4f140 | 297 | const struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
54cf91dc CW |
298 | int i, ret; |
299 | ||
300 | for (i = 0; i < entry->relocation_count; i++) { | |
6fe4f140 | 301 | ret = i915_gem_execbuffer_relocate_entry(obj, eb, &relocs[i]); |
54cf91dc CW |
302 | if (ret) |
303 | return ret; | |
304 | } | |
305 | ||
306 | return 0; | |
307 | } | |
308 | ||
309 | static int | |
310 | i915_gem_execbuffer_relocate(struct drm_device *dev, | |
67731b87 | 311 | struct eb_objects *eb, |
6fe4f140 | 312 | struct list_head *objects) |
54cf91dc | 313 | { |
432e58ed | 314 | struct drm_i915_gem_object *obj; |
d4aeee77 CW |
315 | int ret = 0; |
316 | ||
317 | /* This is the fast path and we cannot handle a pagefault whilst | |
318 | * holding the struct mutex lest the user pass in the relocations | |
319 | * contained within a mmaped bo. For in such a case we, the page | |
320 | * fault handler would call i915_gem_fault() and we would try to | |
321 | * acquire the struct mutex again. Obviously this is bad and so | |
322 | * lockdep complains vehemently. | |
323 | */ | |
324 | pagefault_disable(); | |
432e58ed | 325 | list_for_each_entry(obj, objects, exec_list) { |
6fe4f140 | 326 | ret = i915_gem_execbuffer_relocate_object(obj, eb); |
54cf91dc | 327 | if (ret) |
d4aeee77 | 328 | break; |
54cf91dc | 329 | } |
d4aeee77 | 330 | pagefault_enable(); |
54cf91dc | 331 | |
d4aeee77 | 332 | return ret; |
54cf91dc CW |
333 | } |
334 | ||
7788a765 CW |
335 | #define __EXEC_OBJECT_HAS_PIN (1<<31) |
336 | #define __EXEC_OBJECT_HAS_FENCE (1<<30) | |
1690e1eb | 337 | |
dabdfe02 CW |
338 | static int |
339 | need_reloc_mappable(struct drm_i915_gem_object *obj) | |
340 | { | |
341 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; | |
342 | return entry->relocation_count && !use_cpu_reloc(obj); | |
343 | } | |
344 | ||
1690e1eb | 345 | static int |
7788a765 CW |
346 | i915_gem_execbuffer_reserve_object(struct drm_i915_gem_object *obj, |
347 | struct intel_ring_buffer *ring) | |
1690e1eb | 348 | { |
7788a765 | 349 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
1690e1eb CW |
350 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
351 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; | |
352 | bool need_fence, need_mappable; | |
353 | int ret; | |
354 | ||
355 | need_fence = | |
356 | has_fenced_gpu_access && | |
357 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
358 | obj->tiling_mode != I915_TILING_NONE; | |
dabdfe02 | 359 | need_mappable = need_fence || need_reloc_mappable(obj); |
1690e1eb | 360 | |
86a1ee26 | 361 | ret = i915_gem_object_pin(obj, entry->alignment, need_mappable, false); |
1690e1eb CW |
362 | if (ret) |
363 | return ret; | |
364 | ||
7788a765 CW |
365 | entry->flags |= __EXEC_OBJECT_HAS_PIN; |
366 | ||
1690e1eb CW |
367 | if (has_fenced_gpu_access) { |
368 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { | |
06d98131 | 369 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 | 370 | if (ret) |
7788a765 | 371 | return ret; |
1690e1eb | 372 | |
9a5a53b3 | 373 | if (i915_gem_object_pin_fence(obj)) |
1690e1eb | 374 | entry->flags |= __EXEC_OBJECT_HAS_FENCE; |
9a5a53b3 | 375 | |
7dd49065 | 376 | obj->pending_fenced_gpu_access = true; |
1690e1eb | 377 | } |
1690e1eb CW |
378 | } |
379 | ||
7788a765 CW |
380 | /* Ensure ppgtt mapping exists if needed */ |
381 | if (dev_priv->mm.aliasing_ppgtt && !obj->has_aliasing_ppgtt_mapping) { | |
382 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
383 | obj, obj->cache_level); | |
384 | ||
385 | obj->has_aliasing_ppgtt_mapping = 1; | |
386 | } | |
387 | ||
1690e1eb CW |
388 | entry->offset = obj->gtt_offset; |
389 | return 0; | |
7788a765 | 390 | } |
1690e1eb | 391 | |
7788a765 CW |
392 | static void |
393 | i915_gem_execbuffer_unreserve_object(struct drm_i915_gem_object *obj) | |
394 | { | |
395 | struct drm_i915_gem_exec_object2 *entry; | |
396 | ||
397 | if (!obj->gtt_space) | |
398 | return; | |
399 | ||
400 | entry = obj->exec_entry; | |
401 | ||
402 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) | |
403 | i915_gem_object_unpin_fence(obj); | |
404 | ||
405 | if (entry->flags & __EXEC_OBJECT_HAS_PIN) | |
406 | i915_gem_object_unpin(obj); | |
407 | ||
408 | entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN); | |
1690e1eb CW |
409 | } |
410 | ||
54cf91dc | 411 | static int |
d9e86c0e | 412 | i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring, |
54cf91dc | 413 | struct drm_file *file, |
6fe4f140 | 414 | struct list_head *objects) |
54cf91dc | 415 | { |
432e58ed | 416 | struct drm_i915_gem_object *obj; |
6fe4f140 | 417 | struct list_head ordered_objects; |
7788a765 CW |
418 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; |
419 | int retry; | |
6fe4f140 CW |
420 | |
421 | INIT_LIST_HEAD(&ordered_objects); | |
422 | while (!list_empty(objects)) { | |
423 | struct drm_i915_gem_exec_object2 *entry; | |
424 | bool need_fence, need_mappable; | |
425 | ||
426 | obj = list_first_entry(objects, | |
427 | struct drm_i915_gem_object, | |
428 | exec_list); | |
429 | entry = obj->exec_entry; | |
430 | ||
431 | need_fence = | |
432 | has_fenced_gpu_access && | |
433 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
434 | obj->tiling_mode != I915_TILING_NONE; | |
dabdfe02 | 435 | need_mappable = need_fence || need_reloc_mappable(obj); |
6fe4f140 CW |
436 | |
437 | if (need_mappable) | |
438 | list_move(&obj->exec_list, &ordered_objects); | |
439 | else | |
440 | list_move_tail(&obj->exec_list, &ordered_objects); | |
595dad76 CW |
441 | |
442 | obj->base.pending_read_domains = 0; | |
443 | obj->base.pending_write_domain = 0; | |
016fd0c1 | 444 | obj->pending_fenced_gpu_access = false; |
6fe4f140 CW |
445 | } |
446 | list_splice(&ordered_objects, objects); | |
54cf91dc CW |
447 | |
448 | /* Attempt to pin all of the buffers into the GTT. | |
449 | * This is done in 3 phases: | |
450 | * | |
451 | * 1a. Unbind all objects that do not match the GTT constraints for | |
452 | * the execbuffer (fenceable, mappable, alignment etc). | |
453 | * 1b. Increment pin count for already bound objects. | |
454 | * 2. Bind new objects. | |
455 | * 3. Decrement pin count. | |
456 | * | |
7788a765 | 457 | * This avoid unnecessary unbinding of later objects in order to make |
54cf91dc CW |
458 | * room for the earlier objects *unless* we need to defragment. |
459 | */ | |
460 | retry = 0; | |
461 | do { | |
7788a765 | 462 | int ret = 0; |
54cf91dc CW |
463 | |
464 | /* Unbind any ill-fitting objects or pin. */ | |
432e58ed | 465 | list_for_each_entry(obj, objects, exec_list) { |
6fe4f140 | 466 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
54cf91dc | 467 | bool need_fence, need_mappable; |
1690e1eb | 468 | |
6fe4f140 | 469 | if (!obj->gtt_space) |
54cf91dc CW |
470 | continue; |
471 | ||
472 | need_fence = | |
9b3826bf | 473 | has_fenced_gpu_access && |
54cf91dc CW |
474 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
475 | obj->tiling_mode != I915_TILING_NONE; | |
dabdfe02 | 476 | need_mappable = need_fence || need_reloc_mappable(obj); |
54cf91dc CW |
477 | |
478 | if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) || | |
479 | (need_mappable && !obj->map_and_fenceable)) | |
480 | ret = i915_gem_object_unbind(obj); | |
481 | else | |
7788a765 | 482 | ret = i915_gem_execbuffer_reserve_object(obj, ring); |
432e58ed | 483 | if (ret) |
54cf91dc | 484 | goto err; |
54cf91dc CW |
485 | } |
486 | ||
487 | /* Bind fresh objects */ | |
432e58ed | 488 | list_for_each_entry(obj, objects, exec_list) { |
1690e1eb CW |
489 | if (obj->gtt_space) |
490 | continue; | |
54cf91dc | 491 | |
7788a765 CW |
492 | ret = i915_gem_execbuffer_reserve_object(obj, ring); |
493 | if (ret) | |
494 | goto err; | |
54cf91dc CW |
495 | } |
496 | ||
7788a765 CW |
497 | err: /* Decrement pin count for bound objects */ |
498 | list_for_each_entry(obj, objects, exec_list) | |
499 | i915_gem_execbuffer_unreserve_object(obj); | |
54cf91dc | 500 | |
6c085a72 | 501 | if (ret != -ENOSPC || retry++) |
54cf91dc CW |
502 | return ret; |
503 | ||
6c085a72 | 504 | ret = i915_gem_evict_everything(ring->dev); |
54cf91dc CW |
505 | if (ret) |
506 | return ret; | |
54cf91dc CW |
507 | } while (1); |
508 | } | |
509 | ||
510 | static int | |
511 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, | |
512 | struct drm_file *file, | |
d9e86c0e | 513 | struct intel_ring_buffer *ring, |
432e58ed | 514 | struct list_head *objects, |
67731b87 | 515 | struct eb_objects *eb, |
432e58ed | 516 | struct drm_i915_gem_exec_object2 *exec, |
54cf91dc CW |
517 | int count) |
518 | { | |
519 | struct drm_i915_gem_relocation_entry *reloc; | |
432e58ed | 520 | struct drm_i915_gem_object *obj; |
dd6864a4 | 521 | int *reloc_offset; |
54cf91dc CW |
522 | int i, total, ret; |
523 | ||
67731b87 | 524 | /* We may process another execbuffer during the unlock... */ |
36cf1742 | 525 | while (!list_empty(objects)) { |
67731b87 CW |
526 | obj = list_first_entry(objects, |
527 | struct drm_i915_gem_object, | |
528 | exec_list); | |
529 | list_del_init(&obj->exec_list); | |
530 | drm_gem_object_unreference(&obj->base); | |
531 | } | |
532 | ||
54cf91dc CW |
533 | mutex_unlock(&dev->struct_mutex); |
534 | ||
535 | total = 0; | |
536 | for (i = 0; i < count; i++) | |
432e58ed | 537 | total += exec[i].relocation_count; |
54cf91dc | 538 | |
dd6864a4 | 539 | reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset)); |
54cf91dc | 540 | reloc = drm_malloc_ab(total, sizeof(*reloc)); |
dd6864a4 CW |
541 | if (reloc == NULL || reloc_offset == NULL) { |
542 | drm_free_large(reloc); | |
543 | drm_free_large(reloc_offset); | |
54cf91dc CW |
544 | mutex_lock(&dev->struct_mutex); |
545 | return -ENOMEM; | |
546 | } | |
547 | ||
548 | total = 0; | |
549 | for (i = 0; i < count; i++) { | |
550 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
551 | ||
432e58ed | 552 | user_relocs = (void __user *)(uintptr_t)exec[i].relocs_ptr; |
54cf91dc CW |
553 | |
554 | if (copy_from_user(reloc+total, user_relocs, | |
432e58ed | 555 | exec[i].relocation_count * sizeof(*reloc))) { |
54cf91dc CW |
556 | ret = -EFAULT; |
557 | mutex_lock(&dev->struct_mutex); | |
558 | goto err; | |
559 | } | |
560 | ||
dd6864a4 | 561 | reloc_offset[i] = total; |
432e58ed | 562 | total += exec[i].relocation_count; |
54cf91dc CW |
563 | } |
564 | ||
565 | ret = i915_mutex_lock_interruptible(dev); | |
566 | if (ret) { | |
567 | mutex_lock(&dev->struct_mutex); | |
568 | goto err; | |
569 | } | |
570 | ||
67731b87 | 571 | /* reacquire the objects */ |
67731b87 CW |
572 | eb_reset(eb); |
573 | for (i = 0; i < count; i++) { | |
67731b87 CW |
574 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, |
575 | exec[i].handle)); | |
c8725226 | 576 | if (&obj->base == NULL) { |
ff240199 | 577 | DRM_DEBUG("Invalid object handle %d at index %d\n", |
67731b87 CW |
578 | exec[i].handle, i); |
579 | ret = -ENOENT; | |
580 | goto err; | |
581 | } | |
582 | ||
583 | list_add_tail(&obj->exec_list, objects); | |
584 | obj->exec_handle = exec[i].handle; | |
6fe4f140 | 585 | obj->exec_entry = &exec[i]; |
67731b87 CW |
586 | eb_add_object(eb, obj); |
587 | } | |
588 | ||
6fe4f140 | 589 | ret = i915_gem_execbuffer_reserve(ring, file, objects); |
54cf91dc CW |
590 | if (ret) |
591 | goto err; | |
592 | ||
432e58ed | 593 | list_for_each_entry(obj, objects, exec_list) { |
dd6864a4 | 594 | int offset = obj->exec_entry - exec; |
67731b87 | 595 | ret = i915_gem_execbuffer_relocate_object_slow(obj, eb, |
dd6864a4 | 596 | reloc + reloc_offset[offset]); |
54cf91dc CW |
597 | if (ret) |
598 | goto err; | |
54cf91dc CW |
599 | } |
600 | ||
601 | /* Leave the user relocations as are, this is the painfully slow path, | |
602 | * and we want to avoid the complication of dropping the lock whilst | |
603 | * having buffers reserved in the aperture and so causing spurious | |
604 | * ENOSPC for random operations. | |
605 | */ | |
606 | ||
607 | err: | |
608 | drm_free_large(reloc); | |
dd6864a4 | 609 | drm_free_large(reloc_offset); |
54cf91dc CW |
610 | return ret; |
611 | } | |
612 | ||
c59a333f CW |
613 | static int |
614 | i915_gem_execbuffer_wait_for_flips(struct intel_ring_buffer *ring, u32 flips) | |
615 | { | |
616 | u32 plane, flip_mask; | |
617 | int ret; | |
618 | ||
619 | /* Check for any pending flips. As we only maintain a flip queue depth | |
620 | * of 1, we can simply insert a WAIT for the next display flip prior | |
621 | * to executing the batch and avoid stalling the CPU. | |
622 | */ | |
623 | ||
624 | for (plane = 0; flips >> plane; plane++) { | |
625 | if (((flips >> plane) & 1) == 0) | |
626 | continue; | |
627 | ||
628 | if (plane) | |
629 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
630 | else | |
631 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
632 | ||
633 | ret = intel_ring_begin(ring, 2); | |
634 | if (ret) | |
635 | return ret; | |
636 | ||
637 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); | |
638 | intel_ring_emit(ring, MI_NOOP); | |
639 | intel_ring_advance(ring); | |
640 | } | |
641 | ||
642 | return 0; | |
643 | } | |
644 | ||
54cf91dc | 645 | static int |
432e58ed CW |
646 | i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring, |
647 | struct list_head *objects) | |
54cf91dc | 648 | { |
432e58ed | 649 | struct drm_i915_gem_object *obj; |
6ac42f41 DV |
650 | uint32_t flush_domains = 0; |
651 | uint32_t flips = 0; | |
432e58ed | 652 | int ret; |
54cf91dc | 653 | |
6ac42f41 DV |
654 | list_for_each_entry(obj, objects, exec_list) { |
655 | ret = i915_gem_object_sync(obj, ring); | |
c59a333f CW |
656 | if (ret) |
657 | return ret; | |
6ac42f41 DV |
658 | |
659 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) | |
660 | i915_gem_clflush_object(obj); | |
661 | ||
662 | if (obj->base.pending_write_domain) | |
663 | flips |= atomic_read(&obj->pending_flip); | |
664 | ||
665 | flush_domains |= obj->base.write_domain; | |
c59a333f CW |
666 | } |
667 | ||
6ac42f41 DV |
668 | if (flips) { |
669 | ret = i915_gem_execbuffer_wait_for_flips(ring, flips); | |
1ec14ad3 CW |
670 | if (ret) |
671 | return ret; | |
54cf91dc CW |
672 | } |
673 | ||
6ac42f41 DV |
674 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
675 | intel_gtt_chipset_flush(); | |
676 | ||
677 | if (flush_domains & I915_GEM_DOMAIN_GTT) | |
678 | wmb(); | |
679 | ||
09cf7c9a CW |
680 | /* Unconditionally invalidate gpu caches and ensure that we do flush |
681 | * any residual writes from the previous batch. | |
682 | */ | |
a7b9761d | 683 | return intel_ring_invalidate_all_caches(ring); |
54cf91dc CW |
684 | } |
685 | ||
432e58ed CW |
686 | static bool |
687 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) | |
54cf91dc | 688 | { |
432e58ed | 689 | return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0; |
54cf91dc CW |
690 | } |
691 | ||
692 | static int | |
693 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, | |
694 | int count) | |
695 | { | |
696 | int i; | |
697 | ||
698 | for (i = 0; i < count; i++) { | |
699 | char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr; | |
700 | int length; /* limited by fault_in_pages_readable() */ | |
701 | ||
702 | /* First check for malicious input causing overflow */ | |
703 | if (exec[i].relocation_count > | |
704 | INT_MAX / sizeof(struct drm_i915_gem_relocation_entry)) | |
705 | return -EINVAL; | |
706 | ||
707 | length = exec[i].relocation_count * | |
708 | sizeof(struct drm_i915_gem_relocation_entry); | |
709 | if (!access_ok(VERIFY_READ, ptr, length)) | |
710 | return -EFAULT; | |
711 | ||
712 | /* we may also need to update the presumed offsets */ | |
713 | if (!access_ok(VERIFY_WRITE, ptr, length)) | |
714 | return -EFAULT; | |
715 | ||
f56f821f | 716 | if (fault_in_multipages_readable(ptr, length)) |
54cf91dc CW |
717 | return -EFAULT; |
718 | } | |
719 | ||
720 | return 0; | |
721 | } | |
722 | ||
432e58ed CW |
723 | static void |
724 | i915_gem_execbuffer_move_to_active(struct list_head *objects, | |
1ec14ad3 CW |
725 | struct intel_ring_buffer *ring, |
726 | u32 seqno) | |
432e58ed CW |
727 | { |
728 | struct drm_i915_gem_object *obj; | |
729 | ||
730 | list_for_each_entry(obj, objects, exec_list) { | |
69c2fc89 CW |
731 | u32 old_read = obj->base.read_domains; |
732 | u32 old_write = obj->base.write_domain; | |
db53a302 | 733 | |
432e58ed CW |
734 | obj->base.read_domains = obj->base.pending_read_domains; |
735 | obj->base.write_domain = obj->base.pending_write_domain; | |
736 | obj->fenced_gpu_access = obj->pending_fenced_gpu_access; | |
737 | ||
1ec14ad3 | 738 | i915_gem_object_move_to_active(obj, ring, seqno); |
432e58ed CW |
739 | if (obj->base.write_domain) { |
740 | obj->dirty = 1; | |
0201f1ec | 741 | obj->last_write_seqno = seqno; |
acb87dfb | 742 | if (obj->pin_count) /* check for potential scanout */ |
f047e395 | 743 | intel_mark_fb_busy(obj); |
432e58ed CW |
744 | } |
745 | ||
db53a302 | 746 | trace_i915_gem_object_change_domain(obj, old_read, old_write); |
432e58ed CW |
747 | } |
748 | } | |
749 | ||
54cf91dc CW |
750 | static void |
751 | i915_gem_execbuffer_retire_commands(struct drm_device *dev, | |
432e58ed | 752 | struct drm_file *file, |
54cf91dc CW |
753 | struct intel_ring_buffer *ring) |
754 | { | |
cc889e0f DV |
755 | /* Unconditionally force add_request to emit a full flush. */ |
756 | ring->gpu_caches_dirty = true; | |
54cf91dc | 757 | |
432e58ed | 758 | /* Add a breadcrumb for the completion of the batch buffer */ |
3bb73aba | 759 | (void)i915_add_request(ring, file, NULL); |
432e58ed | 760 | } |
54cf91dc | 761 | |
ae662d31 EA |
762 | static int |
763 | i915_reset_gen7_sol_offsets(struct drm_device *dev, | |
764 | struct intel_ring_buffer *ring) | |
765 | { | |
766 | drm_i915_private_t *dev_priv = dev->dev_private; | |
767 | int ret, i; | |
768 | ||
769 | if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) | |
770 | return 0; | |
771 | ||
772 | ret = intel_ring_begin(ring, 4 * 3); | |
773 | if (ret) | |
774 | return ret; | |
775 | ||
776 | for (i = 0; i < 4; i++) { | |
777 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
778 | intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i)); | |
779 | intel_ring_emit(ring, 0); | |
780 | } | |
781 | ||
782 | intel_ring_advance(ring); | |
783 | ||
784 | return 0; | |
785 | } | |
786 | ||
54cf91dc CW |
787 | static int |
788 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, | |
789 | struct drm_file *file, | |
790 | struct drm_i915_gem_execbuffer2 *args, | |
432e58ed | 791 | struct drm_i915_gem_exec_object2 *exec) |
54cf91dc CW |
792 | { |
793 | drm_i915_private_t *dev_priv = dev->dev_private; | |
432e58ed | 794 | struct list_head objects; |
67731b87 | 795 | struct eb_objects *eb; |
54cf91dc CW |
796 | struct drm_i915_gem_object *batch_obj; |
797 | struct drm_clip_rect *cliprects = NULL; | |
54cf91dc | 798 | struct intel_ring_buffer *ring; |
6e0a69db | 799 | u32 ctx_id = i915_execbuffer2_get_context_id(*args); |
c4e7a414 | 800 | u32 exec_start, exec_len; |
1ec14ad3 | 801 | u32 seqno; |
84f9f938 | 802 | u32 mask; |
d7d4eedd | 803 | u32 flags; |
72bfa19c | 804 | int ret, mode, i; |
54cf91dc | 805 | |
432e58ed | 806 | if (!i915_gem_check_execbuffer(args)) { |
ff240199 | 807 | DRM_DEBUG("execbuf with invalid offset/length\n"); |
432e58ed CW |
808 | return -EINVAL; |
809 | } | |
810 | ||
811 | ret = validate_exec_list(exec, args->buffer_count); | |
54cf91dc CW |
812 | if (ret) |
813 | return ret; | |
814 | ||
d7d4eedd CW |
815 | flags = 0; |
816 | if (args->flags & I915_EXEC_SECURE) { | |
817 | if (!file->is_master || !capable(CAP_SYS_ADMIN)) | |
818 | return -EPERM; | |
819 | ||
820 | flags |= I915_DISPATCH_SECURE; | |
821 | } | |
822 | ||
54cf91dc CW |
823 | switch (args->flags & I915_EXEC_RING_MASK) { |
824 | case I915_EXEC_DEFAULT: | |
825 | case I915_EXEC_RENDER: | |
1ec14ad3 | 826 | ring = &dev_priv->ring[RCS]; |
54cf91dc CW |
827 | break; |
828 | case I915_EXEC_BSD: | |
1ec14ad3 | 829 | ring = &dev_priv->ring[VCS]; |
6e0a69db BW |
830 | if (ctx_id != 0) { |
831 | DRM_DEBUG("Ring %s doesn't support contexts\n", | |
832 | ring->name); | |
833 | return -EPERM; | |
834 | } | |
54cf91dc CW |
835 | break; |
836 | case I915_EXEC_BLT: | |
1ec14ad3 | 837 | ring = &dev_priv->ring[BCS]; |
6e0a69db BW |
838 | if (ctx_id != 0) { |
839 | DRM_DEBUG("Ring %s doesn't support contexts\n", | |
840 | ring->name); | |
841 | return -EPERM; | |
842 | } | |
54cf91dc CW |
843 | break; |
844 | default: | |
ff240199 | 845 | DRM_DEBUG("execbuf with unknown ring: %d\n", |
54cf91dc CW |
846 | (int)(args->flags & I915_EXEC_RING_MASK)); |
847 | return -EINVAL; | |
848 | } | |
a15817cf CW |
849 | if (!intel_ring_initialized(ring)) { |
850 | DRM_DEBUG("execbuf with invalid ring: %d\n", | |
851 | (int)(args->flags & I915_EXEC_RING_MASK)); | |
852 | return -EINVAL; | |
853 | } | |
54cf91dc | 854 | |
72bfa19c | 855 | mode = args->flags & I915_EXEC_CONSTANTS_MASK; |
84f9f938 | 856 | mask = I915_EXEC_CONSTANTS_MASK; |
72bfa19c CW |
857 | switch (mode) { |
858 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
859 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
860 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
861 | if (ring == &dev_priv->ring[RCS] && | |
862 | mode != dev_priv->relative_constants_mode) { | |
863 | if (INTEL_INFO(dev)->gen < 4) | |
864 | return -EINVAL; | |
865 | ||
866 | if (INTEL_INFO(dev)->gen > 5 && | |
867 | mode == I915_EXEC_CONSTANTS_REL_SURFACE) | |
868 | return -EINVAL; | |
84f9f938 BW |
869 | |
870 | /* The HW changed the meaning on this bit on gen6 */ | |
871 | if (INTEL_INFO(dev)->gen >= 6) | |
872 | mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
72bfa19c CW |
873 | } |
874 | break; | |
875 | default: | |
ff240199 | 876 | DRM_DEBUG("execbuf with unknown constants: %d\n", mode); |
72bfa19c CW |
877 | return -EINVAL; |
878 | } | |
879 | ||
54cf91dc | 880 | if (args->buffer_count < 1) { |
ff240199 | 881 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
882 | return -EINVAL; |
883 | } | |
54cf91dc CW |
884 | |
885 | if (args->num_cliprects != 0) { | |
1ec14ad3 | 886 | if (ring != &dev_priv->ring[RCS]) { |
ff240199 | 887 | DRM_DEBUG("clip rectangles are only valid with the render ring\n"); |
c4e7a414 CW |
888 | return -EINVAL; |
889 | } | |
890 | ||
6ebebc92 DV |
891 | if (INTEL_INFO(dev)->gen >= 5) { |
892 | DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); | |
893 | return -EINVAL; | |
894 | } | |
895 | ||
44afb3a0 XW |
896 | if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) { |
897 | DRM_DEBUG("execbuf with %u cliprects\n", | |
898 | args->num_cliprects); | |
899 | return -EINVAL; | |
900 | } | |
5e13a0c5 | 901 | |
432e58ed | 902 | cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects), |
54cf91dc CW |
903 | GFP_KERNEL); |
904 | if (cliprects == NULL) { | |
905 | ret = -ENOMEM; | |
906 | goto pre_mutex_err; | |
907 | } | |
908 | ||
432e58ed CW |
909 | if (copy_from_user(cliprects, |
910 | (struct drm_clip_rect __user *)(uintptr_t) | |
911 | args->cliprects_ptr, | |
912 | sizeof(*cliprects)*args->num_cliprects)) { | |
54cf91dc CW |
913 | ret = -EFAULT; |
914 | goto pre_mutex_err; | |
915 | } | |
916 | } | |
917 | ||
54cf91dc CW |
918 | ret = i915_mutex_lock_interruptible(dev); |
919 | if (ret) | |
920 | goto pre_mutex_err; | |
921 | ||
922 | if (dev_priv->mm.suspended) { | |
923 | mutex_unlock(&dev->struct_mutex); | |
924 | ret = -EBUSY; | |
925 | goto pre_mutex_err; | |
926 | } | |
927 | ||
67731b87 CW |
928 | eb = eb_create(args->buffer_count); |
929 | if (eb == NULL) { | |
930 | mutex_unlock(&dev->struct_mutex); | |
931 | ret = -ENOMEM; | |
932 | goto pre_mutex_err; | |
933 | } | |
934 | ||
54cf91dc | 935 | /* Look up object handles */ |
432e58ed | 936 | INIT_LIST_HEAD(&objects); |
54cf91dc CW |
937 | for (i = 0; i < args->buffer_count; i++) { |
938 | struct drm_i915_gem_object *obj; | |
939 | ||
432e58ed CW |
940 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, |
941 | exec[i].handle)); | |
c8725226 | 942 | if (&obj->base == NULL) { |
ff240199 | 943 | DRM_DEBUG("Invalid object handle %d at index %d\n", |
432e58ed | 944 | exec[i].handle, i); |
54cf91dc | 945 | /* prevent error path from reading uninitialized data */ |
54cf91dc CW |
946 | ret = -ENOENT; |
947 | goto err; | |
948 | } | |
54cf91dc | 949 | |
432e58ed | 950 | if (!list_empty(&obj->exec_list)) { |
ff240199 | 951 | DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n", |
432e58ed | 952 | obj, exec[i].handle, i); |
54cf91dc CW |
953 | ret = -EINVAL; |
954 | goto err; | |
955 | } | |
432e58ed CW |
956 | |
957 | list_add_tail(&obj->exec_list, &objects); | |
67731b87 | 958 | obj->exec_handle = exec[i].handle; |
6fe4f140 | 959 | obj->exec_entry = &exec[i]; |
67731b87 | 960 | eb_add_object(eb, obj); |
54cf91dc CW |
961 | } |
962 | ||
6fe4f140 CW |
963 | /* take note of the batch buffer before we might reorder the lists */ |
964 | batch_obj = list_entry(objects.prev, | |
965 | struct drm_i915_gem_object, | |
966 | exec_list); | |
967 | ||
54cf91dc | 968 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
6fe4f140 | 969 | ret = i915_gem_execbuffer_reserve(ring, file, &objects); |
54cf91dc CW |
970 | if (ret) |
971 | goto err; | |
972 | ||
973 | /* The objects are in their final locations, apply the relocations. */ | |
6fe4f140 | 974 | ret = i915_gem_execbuffer_relocate(dev, eb, &objects); |
54cf91dc CW |
975 | if (ret) { |
976 | if (ret == -EFAULT) { | |
d9e86c0e | 977 | ret = i915_gem_execbuffer_relocate_slow(dev, file, ring, |
67731b87 CW |
978 | &objects, eb, |
979 | exec, | |
54cf91dc CW |
980 | args->buffer_count); |
981 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
982 | } | |
983 | if (ret) | |
984 | goto err; | |
985 | } | |
986 | ||
987 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
54cf91dc | 988 | if (batch_obj->base.pending_write_domain) { |
ff240199 | 989 | DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); |
54cf91dc CW |
990 | ret = -EINVAL; |
991 | goto err; | |
992 | } | |
993 | batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
994 | ||
d7d4eedd CW |
995 | /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure |
996 | * batch" bit. Hence we need to pin secure batches into the global gtt. | |
997 | * hsw should have this fixed, but let's be paranoid and do it | |
998 | * unconditionally for now. */ | |
999 | if (flags & I915_DISPATCH_SECURE && !batch_obj->has_global_gtt_mapping) | |
1000 | i915_gem_gtt_bind_object(batch_obj, batch_obj->cache_level); | |
1001 | ||
432e58ed CW |
1002 | ret = i915_gem_execbuffer_move_to_gpu(ring, &objects); |
1003 | if (ret) | |
54cf91dc | 1004 | goto err; |
54cf91dc | 1005 | |
db53a302 | 1006 | seqno = i915_gem_next_request_seqno(ring); |
076e2c0e | 1007 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) { |
1ec14ad3 CW |
1008 | if (seqno < ring->sync_seqno[i]) { |
1009 | /* The GPU can not handle its semaphore value wrapping, | |
1010 | * so every billion or so execbuffers, we need to stall | |
1011 | * the GPU in order to reset the counters. | |
1012 | */ | |
b2da9fe5 | 1013 | ret = i915_gpu_idle(dev); |
1ec14ad3 CW |
1014 | if (ret) |
1015 | goto err; | |
b2da9fe5 | 1016 | i915_gem_retire_requests(dev); |
1ec14ad3 CW |
1017 | |
1018 | BUG_ON(ring->sync_seqno[i]); | |
1019 | } | |
1020 | } | |
1021 | ||
0da5cec1 EA |
1022 | ret = i915_switch_context(ring, file, ctx_id); |
1023 | if (ret) | |
1024 | goto err; | |
1025 | ||
e2971bda BW |
1026 | if (ring == &dev_priv->ring[RCS] && |
1027 | mode != dev_priv->relative_constants_mode) { | |
1028 | ret = intel_ring_begin(ring, 4); | |
1029 | if (ret) | |
1030 | goto err; | |
1031 | ||
1032 | intel_ring_emit(ring, MI_NOOP); | |
1033 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
1034 | intel_ring_emit(ring, INSTPM); | |
84f9f938 | 1035 | intel_ring_emit(ring, mask << 16 | mode); |
e2971bda BW |
1036 | intel_ring_advance(ring); |
1037 | ||
1038 | dev_priv->relative_constants_mode = mode; | |
1039 | } | |
1040 | ||
ae662d31 EA |
1041 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { |
1042 | ret = i915_reset_gen7_sol_offsets(dev, ring); | |
1043 | if (ret) | |
1044 | goto err; | |
1045 | } | |
1046 | ||
d7d4eedd | 1047 | trace_i915_gem_ring_dispatch(ring, seqno, flags); |
db53a302 | 1048 | |
c4e7a414 CW |
1049 | exec_start = batch_obj->gtt_offset + args->batch_start_offset; |
1050 | exec_len = args->batch_len; | |
1051 | if (cliprects) { | |
1052 | for (i = 0; i < args->num_cliprects; i++) { | |
1053 | ret = i915_emit_box(dev, &cliprects[i], | |
1054 | args->DR1, args->DR4); | |
1055 | if (ret) | |
1056 | goto err; | |
1057 | ||
1058 | ret = ring->dispatch_execbuffer(ring, | |
d7d4eedd CW |
1059 | exec_start, exec_len, |
1060 | flags); | |
c4e7a414 CW |
1061 | if (ret) |
1062 | goto err; | |
1063 | } | |
1064 | } else { | |
d7d4eedd CW |
1065 | ret = ring->dispatch_execbuffer(ring, |
1066 | exec_start, exec_len, | |
1067 | flags); | |
c4e7a414 CW |
1068 | if (ret) |
1069 | goto err; | |
1070 | } | |
54cf91dc | 1071 | |
1ec14ad3 | 1072 | i915_gem_execbuffer_move_to_active(&objects, ring, seqno); |
432e58ed | 1073 | i915_gem_execbuffer_retire_commands(dev, file, ring); |
54cf91dc CW |
1074 | |
1075 | err: | |
67731b87 | 1076 | eb_destroy(eb); |
432e58ed CW |
1077 | while (!list_empty(&objects)) { |
1078 | struct drm_i915_gem_object *obj; | |
1079 | ||
1080 | obj = list_first_entry(&objects, | |
1081 | struct drm_i915_gem_object, | |
1082 | exec_list); | |
1083 | list_del_init(&obj->exec_list); | |
1084 | drm_gem_object_unreference(&obj->base); | |
54cf91dc CW |
1085 | } |
1086 | ||
1087 | mutex_unlock(&dev->struct_mutex); | |
1088 | ||
1089 | pre_mutex_err: | |
54cf91dc | 1090 | kfree(cliprects); |
54cf91dc CW |
1091 | return ret; |
1092 | } | |
1093 | ||
1094 | /* | |
1095 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
1096 | * list array and passes it to the real function. | |
1097 | */ | |
1098 | int | |
1099 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1100 | struct drm_file *file) | |
1101 | { | |
1102 | struct drm_i915_gem_execbuffer *args = data; | |
1103 | struct drm_i915_gem_execbuffer2 exec2; | |
1104 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
1105 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1106 | int ret, i; | |
1107 | ||
54cf91dc | 1108 | if (args->buffer_count < 1) { |
ff240199 | 1109 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1110 | return -EINVAL; |
1111 | } | |
1112 | ||
1113 | /* Copy in the exec list from userland */ | |
1114 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
1115 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
1116 | if (exec_list == NULL || exec2_list == NULL) { | |
ff240199 | 1117 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1118 | args->buffer_count); |
1119 | drm_free_large(exec_list); | |
1120 | drm_free_large(exec2_list); | |
1121 | return -ENOMEM; | |
1122 | } | |
1123 | ret = copy_from_user(exec_list, | |
ba7a6458 | 1124 | (void __user *)(uintptr_t)args->buffers_ptr, |
54cf91dc CW |
1125 | sizeof(*exec_list) * args->buffer_count); |
1126 | if (ret != 0) { | |
ff240199 | 1127 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1128 | args->buffer_count, ret); |
1129 | drm_free_large(exec_list); | |
1130 | drm_free_large(exec2_list); | |
1131 | return -EFAULT; | |
1132 | } | |
1133 | ||
1134 | for (i = 0; i < args->buffer_count; i++) { | |
1135 | exec2_list[i].handle = exec_list[i].handle; | |
1136 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
1137 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
1138 | exec2_list[i].alignment = exec_list[i].alignment; | |
1139 | exec2_list[i].offset = exec_list[i].offset; | |
1140 | if (INTEL_INFO(dev)->gen < 4) | |
1141 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; | |
1142 | else | |
1143 | exec2_list[i].flags = 0; | |
1144 | } | |
1145 | ||
1146 | exec2.buffers_ptr = args->buffers_ptr; | |
1147 | exec2.buffer_count = args->buffer_count; | |
1148 | exec2.batch_start_offset = args->batch_start_offset; | |
1149 | exec2.batch_len = args->batch_len; | |
1150 | exec2.DR1 = args->DR1; | |
1151 | exec2.DR4 = args->DR4; | |
1152 | exec2.num_cliprects = args->num_cliprects; | |
1153 | exec2.cliprects_ptr = args->cliprects_ptr; | |
1154 | exec2.flags = I915_EXEC_RENDER; | |
6e0a69db | 1155 | i915_execbuffer2_set_context_id(exec2, 0); |
54cf91dc CW |
1156 | |
1157 | ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list); | |
1158 | if (!ret) { | |
1159 | /* Copy the new buffer offsets back to the user's exec list. */ | |
1160 | for (i = 0; i < args->buffer_count; i++) | |
1161 | exec_list[i].offset = exec2_list[i].offset; | |
1162 | /* ... and back out to userspace */ | |
ba7a6458 | 1163 | ret = copy_to_user((void __user *)(uintptr_t)args->buffers_ptr, |
54cf91dc CW |
1164 | exec_list, |
1165 | sizeof(*exec_list) * args->buffer_count); | |
1166 | if (ret) { | |
1167 | ret = -EFAULT; | |
ff240199 | 1168 | DRM_DEBUG("failed to copy %d exec entries " |
54cf91dc CW |
1169 | "back to user (%d)\n", |
1170 | args->buffer_count, ret); | |
1171 | } | |
1172 | } | |
1173 | ||
1174 | drm_free_large(exec_list); | |
1175 | drm_free_large(exec2_list); | |
1176 | return ret; | |
1177 | } | |
1178 | ||
1179 | int | |
1180 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
1181 | struct drm_file *file) | |
1182 | { | |
1183 | struct drm_i915_gem_execbuffer2 *args = data; | |
1184 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1185 | int ret; | |
1186 | ||
ed8cd3b2 XW |
1187 | if (args->buffer_count < 1 || |
1188 | args->buffer_count > UINT_MAX / sizeof(*exec2_list)) { | |
ff240199 | 1189 | DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1190 | return -EINVAL; |
1191 | } | |
1192 | ||
8408c282 CW |
1193 | exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count, |
1194 | GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY); | |
1195 | if (exec2_list == NULL) | |
1196 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), | |
1197 | args->buffer_count); | |
54cf91dc | 1198 | if (exec2_list == NULL) { |
ff240199 | 1199 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1200 | args->buffer_count); |
1201 | return -ENOMEM; | |
1202 | } | |
1203 | ret = copy_from_user(exec2_list, | |
1204 | (struct drm_i915_relocation_entry __user *) | |
1205 | (uintptr_t) args->buffers_ptr, | |
1206 | sizeof(*exec2_list) * args->buffer_count); | |
1207 | if (ret != 0) { | |
ff240199 | 1208 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1209 | args->buffer_count, ret); |
1210 | drm_free_large(exec2_list); | |
1211 | return -EFAULT; | |
1212 | } | |
1213 | ||
1214 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list); | |
1215 | if (!ret) { | |
1216 | /* Copy the new buffer offsets back to the user's exec list. */ | |
ba7a6458 | 1217 | ret = copy_to_user((void __user *)(uintptr_t)args->buffers_ptr, |
54cf91dc CW |
1218 | exec2_list, |
1219 | sizeof(*exec2_list) * args->buffer_count); | |
1220 | if (ret) { | |
1221 | ret = -EFAULT; | |
ff240199 | 1222 | DRM_DEBUG("failed to copy %d exec entries " |
54cf91dc CW |
1223 | "back to user (%d)\n", |
1224 | args->buffer_count, ret); | |
1225 | } | |
1226 | } | |
1227 | ||
1228 | drm_free_large(exec2_list); | |
1229 | return ret; | |
1230 | } |