Commit | Line | Data |
---|---|---|
54cf91dc CW |
1 | /* |
2 | * Copyright © 2008,2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Chris Wilson <chris@chris-wilson.co.uk> | |
26 | * | |
27 | */ | |
28 | ||
760285e7 DH |
29 | #include <drm/drmP.h> |
30 | #include <drm/i915_drm.h> | |
54cf91dc CW |
31 | #include "i915_drv.h" |
32 | #include "i915_trace.h" | |
33 | #include "intel_drv.h" | |
f45b5557 | 34 | #include <linux/dma_remapping.h> |
54cf91dc | 35 | |
a415d355 CW |
36 | #define __EXEC_OBJECT_HAS_PIN (1<<31) |
37 | #define __EXEC_OBJECT_HAS_FENCE (1<<30) | |
38 | ||
27173f1f BW |
39 | struct eb_vmas { |
40 | struct list_head vmas; | |
67731b87 | 41 | int and; |
eef90ccb | 42 | union { |
27173f1f | 43 | struct i915_vma *lut[0]; |
eef90ccb CW |
44 | struct hlist_head buckets[0]; |
45 | }; | |
67731b87 CW |
46 | }; |
47 | ||
27173f1f | 48 | static struct eb_vmas * |
17601cbc | 49 | eb_create(struct drm_i915_gem_execbuffer2 *args) |
67731b87 | 50 | { |
27173f1f | 51 | struct eb_vmas *eb = NULL; |
eef90ccb CW |
52 | |
53 | if (args->flags & I915_EXEC_HANDLE_LUT) { | |
b205ca57 | 54 | unsigned size = args->buffer_count; |
27173f1f BW |
55 | size *= sizeof(struct i915_vma *); |
56 | size += sizeof(struct eb_vmas); | |
eef90ccb CW |
57 | eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); |
58 | } | |
59 | ||
60 | if (eb == NULL) { | |
b205ca57 DV |
61 | unsigned size = args->buffer_count; |
62 | unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2; | |
27b7c63a | 63 | BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head)); |
eef90ccb CW |
64 | while (count > 2*size) |
65 | count >>= 1; | |
66 | eb = kzalloc(count*sizeof(struct hlist_head) + | |
27173f1f | 67 | sizeof(struct eb_vmas), |
eef90ccb CW |
68 | GFP_TEMPORARY); |
69 | if (eb == NULL) | |
70 | return eb; | |
71 | ||
72 | eb->and = count - 1; | |
73 | } else | |
74 | eb->and = -args->buffer_count; | |
75 | ||
27173f1f | 76 | INIT_LIST_HEAD(&eb->vmas); |
67731b87 CW |
77 | return eb; |
78 | } | |
79 | ||
80 | static void | |
27173f1f | 81 | eb_reset(struct eb_vmas *eb) |
67731b87 | 82 | { |
eef90ccb CW |
83 | if (eb->and >= 0) |
84 | memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head)); | |
67731b87 CW |
85 | } |
86 | ||
3b96eff4 | 87 | static int |
27173f1f BW |
88 | eb_lookup_vmas(struct eb_vmas *eb, |
89 | struct drm_i915_gem_exec_object2 *exec, | |
90 | const struct drm_i915_gem_execbuffer2 *args, | |
91 | struct i915_address_space *vm, | |
92 | struct drm_file *file) | |
3b96eff4 | 93 | { |
6f65e29a | 94 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
27173f1f BW |
95 | struct drm_i915_gem_object *obj; |
96 | struct list_head objects; | |
9ae9ab52 | 97 | int i, ret; |
3b96eff4 | 98 | |
27173f1f | 99 | INIT_LIST_HEAD(&objects); |
3b96eff4 | 100 | spin_lock(&file->table_lock); |
27173f1f BW |
101 | /* Grab a reference to the object and release the lock so we can lookup |
102 | * or create the VMA without using GFP_ATOMIC */ | |
eef90ccb | 103 | for (i = 0; i < args->buffer_count; i++) { |
3b96eff4 CW |
104 | obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle)); |
105 | if (obj == NULL) { | |
106 | spin_unlock(&file->table_lock); | |
107 | DRM_DEBUG("Invalid object handle %d at index %d\n", | |
108 | exec[i].handle, i); | |
27173f1f | 109 | ret = -ENOENT; |
9ae9ab52 | 110 | goto err; |
3b96eff4 CW |
111 | } |
112 | ||
27173f1f | 113 | if (!list_empty(&obj->obj_exec_link)) { |
3b96eff4 CW |
114 | spin_unlock(&file->table_lock); |
115 | DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n", | |
116 | obj, exec[i].handle, i); | |
27173f1f | 117 | ret = -EINVAL; |
9ae9ab52 | 118 | goto err; |
3b96eff4 CW |
119 | } |
120 | ||
121 | drm_gem_object_reference(&obj->base); | |
27173f1f BW |
122 | list_add_tail(&obj->obj_exec_link, &objects); |
123 | } | |
124 | spin_unlock(&file->table_lock); | |
3b96eff4 | 125 | |
27173f1f | 126 | i = 0; |
9ae9ab52 | 127 | while (!list_empty(&objects)) { |
27173f1f | 128 | struct i915_vma *vma; |
6f65e29a BW |
129 | struct i915_address_space *bind_vm = vm; |
130 | ||
2c9f8d56 DV |
131 | if (exec[i].flags & EXEC_OBJECT_NEEDS_GTT && |
132 | USES_FULL_PPGTT(vm->dev)) { | |
133 | ret = -EINVAL; | |
a25eebb0 | 134 | goto err; |
2c9f8d56 DV |
135 | } |
136 | ||
6f65e29a BW |
137 | /* If we have secure dispatch, or the userspace assures us that |
138 | * they know what they're doing, use the GGTT VM. | |
139 | */ | |
a7c1d426 | 140 | if (((args->flags & I915_EXEC_SECURE) && |
6f65e29a BW |
141 | (i == (args->buffer_count - 1)))) |
142 | bind_vm = &dev_priv->gtt.base; | |
27173f1f | 143 | |
9ae9ab52 CW |
144 | obj = list_first_entry(&objects, |
145 | struct drm_i915_gem_object, | |
146 | obj_exec_link); | |
147 | ||
e656a6cb DV |
148 | /* |
149 | * NOTE: We can leak any vmas created here when something fails | |
150 | * later on. But that's no issue since vma_unbind can deal with | |
151 | * vmas which are not actually bound. And since only | |
152 | * lookup_or_create exists as an interface to get at the vma | |
153 | * from the (obj, vm) we don't run the risk of creating | |
154 | * duplicated vmas for the same vm. | |
155 | */ | |
6f65e29a | 156 | vma = i915_gem_obj_lookup_or_create_vma(obj, bind_vm); |
27173f1f | 157 | if (IS_ERR(vma)) { |
27173f1f BW |
158 | DRM_DEBUG("Failed to lookup VMA\n"); |
159 | ret = PTR_ERR(vma); | |
9ae9ab52 | 160 | goto err; |
27173f1f BW |
161 | } |
162 | ||
9ae9ab52 | 163 | /* Transfer ownership from the objects list to the vmas list. */ |
27173f1f | 164 | list_add_tail(&vma->exec_list, &eb->vmas); |
9ae9ab52 | 165 | list_del_init(&obj->obj_exec_link); |
27173f1f BW |
166 | |
167 | vma->exec_entry = &exec[i]; | |
eef90ccb | 168 | if (eb->and < 0) { |
27173f1f | 169 | eb->lut[i] = vma; |
eef90ccb CW |
170 | } else { |
171 | uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle; | |
27173f1f BW |
172 | vma->exec_handle = handle; |
173 | hlist_add_head(&vma->exec_node, | |
eef90ccb CW |
174 | &eb->buckets[handle & eb->and]); |
175 | } | |
27173f1f | 176 | ++i; |
3b96eff4 | 177 | } |
3b96eff4 | 178 | |
9ae9ab52 | 179 | return 0; |
27173f1f | 180 | |
27173f1f | 181 | |
9ae9ab52 | 182 | err: |
27173f1f BW |
183 | while (!list_empty(&objects)) { |
184 | obj = list_first_entry(&objects, | |
185 | struct drm_i915_gem_object, | |
186 | obj_exec_link); | |
187 | list_del_init(&obj->obj_exec_link); | |
9ae9ab52 | 188 | drm_gem_object_unreference(&obj->base); |
27173f1f | 189 | } |
9ae9ab52 CW |
190 | /* |
191 | * Objects already transfered to the vmas list will be unreferenced by | |
192 | * eb_destroy. | |
193 | */ | |
194 | ||
27173f1f | 195 | return ret; |
3b96eff4 CW |
196 | } |
197 | ||
27173f1f | 198 | static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle) |
67731b87 | 199 | { |
eef90ccb CW |
200 | if (eb->and < 0) { |
201 | if (handle >= -eb->and) | |
202 | return NULL; | |
203 | return eb->lut[handle]; | |
204 | } else { | |
205 | struct hlist_head *head; | |
206 | struct hlist_node *node; | |
67731b87 | 207 | |
eef90ccb CW |
208 | head = &eb->buckets[handle & eb->and]; |
209 | hlist_for_each(node, head) { | |
27173f1f | 210 | struct i915_vma *vma; |
67731b87 | 211 | |
27173f1f BW |
212 | vma = hlist_entry(node, struct i915_vma, exec_node); |
213 | if (vma->exec_handle == handle) | |
214 | return vma; | |
eef90ccb CW |
215 | } |
216 | return NULL; | |
217 | } | |
67731b87 CW |
218 | } |
219 | ||
a415d355 CW |
220 | static void |
221 | i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma) | |
222 | { | |
223 | struct drm_i915_gem_exec_object2 *entry; | |
224 | struct drm_i915_gem_object *obj = vma->obj; | |
225 | ||
226 | if (!drm_mm_node_allocated(&vma->node)) | |
227 | return; | |
228 | ||
229 | entry = vma->exec_entry; | |
230 | ||
231 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) | |
232 | i915_gem_object_unpin_fence(obj); | |
233 | ||
234 | if (entry->flags & __EXEC_OBJECT_HAS_PIN) | |
3d7f0f9d | 235 | vma->pin_count--; |
a415d355 CW |
236 | |
237 | entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN); | |
238 | } | |
239 | ||
240 | static void eb_destroy(struct eb_vmas *eb) | |
241 | { | |
27173f1f BW |
242 | while (!list_empty(&eb->vmas)) { |
243 | struct i915_vma *vma; | |
bcffc3fa | 244 | |
27173f1f BW |
245 | vma = list_first_entry(&eb->vmas, |
246 | struct i915_vma, | |
bcffc3fa | 247 | exec_list); |
27173f1f | 248 | list_del_init(&vma->exec_list); |
a415d355 | 249 | i915_gem_execbuffer_unreserve_vma(vma); |
27173f1f | 250 | drm_gem_object_unreference(&vma->obj->base); |
bcffc3fa | 251 | } |
67731b87 CW |
252 | kfree(eb); |
253 | } | |
254 | ||
dabdfe02 CW |
255 | static inline int use_cpu_reloc(struct drm_i915_gem_object *obj) |
256 | { | |
2cc86b82 CW |
257 | return (HAS_LLC(obj->base.dev) || |
258 | obj->base.write_domain == I915_GEM_DOMAIN_CPU || | |
504c7267 | 259 | !obj->map_and_fenceable || |
dabdfe02 CW |
260 | obj->cache_level != I915_CACHE_NONE); |
261 | } | |
262 | ||
5032d871 RB |
263 | static int |
264 | relocate_entry_cpu(struct drm_i915_gem_object *obj, | |
d9ceb957 BW |
265 | struct drm_i915_gem_relocation_entry *reloc, |
266 | uint64_t target_offset) | |
5032d871 | 267 | { |
3c94ceee | 268 | struct drm_device *dev = obj->base.dev; |
5032d871 | 269 | uint32_t page_offset = offset_in_page(reloc->offset); |
d9ceb957 | 270 | uint64_t delta = reloc->delta + target_offset; |
5032d871 | 271 | char *vaddr; |
8b78f0e5 | 272 | int ret; |
5032d871 | 273 | |
2cc86b82 | 274 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
5032d871 RB |
275 | if (ret) |
276 | return ret; | |
277 | ||
278 | vaddr = kmap_atomic(i915_gem_object_get_page(obj, | |
279 | reloc->offset >> PAGE_SHIFT)); | |
d9ceb957 | 280 | *(uint32_t *)(vaddr + page_offset) = lower_32_bits(delta); |
3c94ceee BW |
281 | |
282 | if (INTEL_INFO(dev)->gen >= 8) { | |
283 | page_offset = offset_in_page(page_offset + sizeof(uint32_t)); | |
284 | ||
285 | if (page_offset == 0) { | |
286 | kunmap_atomic(vaddr); | |
287 | vaddr = kmap_atomic(i915_gem_object_get_page(obj, | |
288 | (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT)); | |
289 | } | |
290 | ||
d9ceb957 | 291 | *(uint32_t *)(vaddr + page_offset) = upper_32_bits(delta); |
3c94ceee BW |
292 | } |
293 | ||
5032d871 RB |
294 | kunmap_atomic(vaddr); |
295 | ||
296 | return 0; | |
297 | } | |
298 | ||
299 | static int | |
300 | relocate_entry_gtt(struct drm_i915_gem_object *obj, | |
d9ceb957 BW |
301 | struct drm_i915_gem_relocation_entry *reloc, |
302 | uint64_t target_offset) | |
5032d871 RB |
303 | { |
304 | struct drm_device *dev = obj->base.dev; | |
305 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d9ceb957 | 306 | uint64_t delta = reloc->delta + target_offset; |
5032d871 RB |
307 | uint32_t __iomem *reloc_entry; |
308 | void __iomem *reloc_page; | |
8b78f0e5 | 309 | int ret; |
5032d871 RB |
310 | |
311 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
312 | if (ret) | |
313 | return ret; | |
314 | ||
315 | ret = i915_gem_object_put_fence(obj); | |
316 | if (ret) | |
317 | return ret; | |
318 | ||
319 | /* Map the page containing the relocation we're going to perform. */ | |
320 | reloc->offset += i915_gem_obj_ggtt_offset(obj); | |
321 | reloc_page = io_mapping_map_atomic_wc(dev_priv->gtt.mappable, | |
322 | reloc->offset & PAGE_MASK); | |
323 | reloc_entry = (uint32_t __iomem *) | |
324 | (reloc_page + offset_in_page(reloc->offset)); | |
d9ceb957 | 325 | iowrite32(lower_32_bits(delta), reloc_entry); |
3c94ceee BW |
326 | |
327 | if (INTEL_INFO(dev)->gen >= 8) { | |
328 | reloc_entry += 1; | |
329 | ||
330 | if (offset_in_page(reloc->offset + sizeof(uint32_t)) == 0) { | |
331 | io_mapping_unmap_atomic(reloc_page); | |
332 | reloc_page = io_mapping_map_atomic_wc( | |
333 | dev_priv->gtt.mappable, | |
334 | reloc->offset + sizeof(uint32_t)); | |
335 | reloc_entry = reloc_page; | |
336 | } | |
337 | ||
d9ceb957 | 338 | iowrite32(upper_32_bits(delta), reloc_entry); |
3c94ceee BW |
339 | } |
340 | ||
5032d871 RB |
341 | io_mapping_unmap_atomic(reloc_page); |
342 | ||
343 | return 0; | |
344 | } | |
345 | ||
54cf91dc CW |
346 | static int |
347 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, | |
27173f1f | 348 | struct eb_vmas *eb, |
3e7a0322 | 349 | struct drm_i915_gem_relocation_entry *reloc) |
54cf91dc CW |
350 | { |
351 | struct drm_device *dev = obj->base.dev; | |
352 | struct drm_gem_object *target_obj; | |
149c8407 | 353 | struct drm_i915_gem_object *target_i915_obj; |
27173f1f | 354 | struct i915_vma *target_vma; |
d9ceb957 | 355 | uint64_t target_offset; |
8b78f0e5 | 356 | int ret; |
54cf91dc | 357 | |
67731b87 | 358 | /* we've already hold a reference to all valid objects */ |
27173f1f BW |
359 | target_vma = eb_get_vma(eb, reloc->target_handle); |
360 | if (unlikely(target_vma == NULL)) | |
54cf91dc | 361 | return -ENOENT; |
27173f1f BW |
362 | target_i915_obj = target_vma->obj; |
363 | target_obj = &target_vma->obj->base; | |
54cf91dc | 364 | |
5ce09725 | 365 | target_offset = target_vma->node.start; |
54cf91dc | 366 | |
e844b990 EA |
367 | /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and |
368 | * pipe_control writes because the gpu doesn't properly redirect them | |
369 | * through the ppgtt for non_secure batchbuffers. */ | |
370 | if (unlikely(IS_GEN6(dev) && | |
371 | reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION && | |
372 | !target_i915_obj->has_global_gtt_mapping)) { | |
3e7a0322 BW |
373 | struct i915_vma *vma = |
374 | list_first_entry(&target_i915_obj->vma_list, | |
375 | typeof(*vma), vma_link); | |
6f65e29a | 376 | vma->bind_vma(vma, target_i915_obj->cache_level, GLOBAL_BIND); |
e844b990 EA |
377 | } |
378 | ||
54cf91dc | 379 | /* Validate that the target is in a valid r/w GPU domain */ |
b8f7ab17 | 380 | if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { |
ff240199 | 381 | DRM_DEBUG("reloc with multiple write domains: " |
54cf91dc CW |
382 | "obj %p target %d offset %d " |
383 | "read %08x write %08x", | |
384 | obj, reloc->target_handle, | |
385 | (int) reloc->offset, | |
386 | reloc->read_domains, | |
387 | reloc->write_domain); | |
8b78f0e5 | 388 | return -EINVAL; |
54cf91dc | 389 | } |
4ca4a250 DV |
390 | if (unlikely((reloc->write_domain | reloc->read_domains) |
391 | & ~I915_GEM_GPU_DOMAINS)) { | |
ff240199 | 392 | DRM_DEBUG("reloc with read/write non-GPU domains: " |
54cf91dc CW |
393 | "obj %p target %d offset %d " |
394 | "read %08x write %08x", | |
395 | obj, reloc->target_handle, | |
396 | (int) reloc->offset, | |
397 | reloc->read_domains, | |
398 | reloc->write_domain); | |
8b78f0e5 | 399 | return -EINVAL; |
54cf91dc | 400 | } |
54cf91dc CW |
401 | |
402 | target_obj->pending_read_domains |= reloc->read_domains; | |
403 | target_obj->pending_write_domain |= reloc->write_domain; | |
404 | ||
405 | /* If the relocation already has the right value in it, no | |
406 | * more work needs to be done. | |
407 | */ | |
408 | if (target_offset == reloc->presumed_offset) | |
67731b87 | 409 | return 0; |
54cf91dc CW |
410 | |
411 | /* Check that the relocation address is valid... */ | |
3c94ceee BW |
412 | if (unlikely(reloc->offset > |
413 | obj->base.size - (INTEL_INFO(dev)->gen >= 8 ? 8 : 4))) { | |
ff240199 | 414 | DRM_DEBUG("Relocation beyond object bounds: " |
54cf91dc CW |
415 | "obj %p target %d offset %d size %d.\n", |
416 | obj, reloc->target_handle, | |
417 | (int) reloc->offset, | |
418 | (int) obj->base.size); | |
8b78f0e5 | 419 | return -EINVAL; |
54cf91dc | 420 | } |
b8f7ab17 | 421 | if (unlikely(reloc->offset & 3)) { |
ff240199 | 422 | DRM_DEBUG("Relocation not 4-byte aligned: " |
54cf91dc CW |
423 | "obj %p target %d offset %d.\n", |
424 | obj, reloc->target_handle, | |
425 | (int) reloc->offset); | |
8b78f0e5 | 426 | return -EINVAL; |
54cf91dc CW |
427 | } |
428 | ||
dabdfe02 CW |
429 | /* We can't wait for rendering with pagefaults disabled */ |
430 | if (obj->active && in_atomic()) | |
431 | return -EFAULT; | |
432 | ||
5032d871 | 433 | if (use_cpu_reloc(obj)) |
d9ceb957 | 434 | ret = relocate_entry_cpu(obj, reloc, target_offset); |
5032d871 | 435 | else |
d9ceb957 | 436 | ret = relocate_entry_gtt(obj, reloc, target_offset); |
54cf91dc | 437 | |
d4d36014 DV |
438 | if (ret) |
439 | return ret; | |
440 | ||
54cf91dc CW |
441 | /* and update the user's relocation entry */ |
442 | reloc->presumed_offset = target_offset; | |
443 | ||
67731b87 | 444 | return 0; |
54cf91dc CW |
445 | } |
446 | ||
447 | static int | |
27173f1f BW |
448 | i915_gem_execbuffer_relocate_vma(struct i915_vma *vma, |
449 | struct eb_vmas *eb) | |
54cf91dc | 450 | { |
1d83f442 CW |
451 | #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) |
452 | struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)]; | |
54cf91dc | 453 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
27173f1f | 454 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
1d83f442 | 455 | int remain, ret; |
54cf91dc | 456 | |
2bb4629a | 457 | user_relocs = to_user_ptr(entry->relocs_ptr); |
54cf91dc | 458 | |
1d83f442 CW |
459 | remain = entry->relocation_count; |
460 | while (remain) { | |
461 | struct drm_i915_gem_relocation_entry *r = stack_reloc; | |
462 | int count = remain; | |
463 | if (count > ARRAY_SIZE(stack_reloc)) | |
464 | count = ARRAY_SIZE(stack_reloc); | |
465 | remain -= count; | |
466 | ||
467 | if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0]))) | |
54cf91dc CW |
468 | return -EFAULT; |
469 | ||
1d83f442 CW |
470 | do { |
471 | u64 offset = r->presumed_offset; | |
54cf91dc | 472 | |
3e7a0322 | 473 | ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r); |
1d83f442 CW |
474 | if (ret) |
475 | return ret; | |
476 | ||
477 | if (r->presumed_offset != offset && | |
478 | __copy_to_user_inatomic(&user_relocs->presumed_offset, | |
479 | &r->presumed_offset, | |
480 | sizeof(r->presumed_offset))) { | |
481 | return -EFAULT; | |
482 | } | |
483 | ||
484 | user_relocs++; | |
485 | r++; | |
486 | } while (--count); | |
54cf91dc CW |
487 | } |
488 | ||
489 | return 0; | |
1d83f442 | 490 | #undef N_RELOC |
54cf91dc CW |
491 | } |
492 | ||
493 | static int | |
27173f1f BW |
494 | i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma, |
495 | struct eb_vmas *eb, | |
496 | struct drm_i915_gem_relocation_entry *relocs) | |
54cf91dc | 497 | { |
27173f1f | 498 | const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
54cf91dc CW |
499 | int i, ret; |
500 | ||
501 | for (i = 0; i < entry->relocation_count; i++) { | |
3e7a0322 | 502 | ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i]); |
54cf91dc CW |
503 | if (ret) |
504 | return ret; | |
505 | } | |
506 | ||
507 | return 0; | |
508 | } | |
509 | ||
510 | static int | |
17601cbc | 511 | i915_gem_execbuffer_relocate(struct eb_vmas *eb) |
54cf91dc | 512 | { |
27173f1f | 513 | struct i915_vma *vma; |
d4aeee77 CW |
514 | int ret = 0; |
515 | ||
516 | /* This is the fast path and we cannot handle a pagefault whilst | |
517 | * holding the struct mutex lest the user pass in the relocations | |
518 | * contained within a mmaped bo. For in such a case we, the page | |
519 | * fault handler would call i915_gem_fault() and we would try to | |
520 | * acquire the struct mutex again. Obviously this is bad and so | |
521 | * lockdep complains vehemently. | |
522 | */ | |
523 | pagefault_disable(); | |
27173f1f BW |
524 | list_for_each_entry(vma, &eb->vmas, exec_list) { |
525 | ret = i915_gem_execbuffer_relocate_vma(vma, eb); | |
54cf91dc | 526 | if (ret) |
d4aeee77 | 527 | break; |
54cf91dc | 528 | } |
d4aeee77 | 529 | pagefault_enable(); |
54cf91dc | 530 | |
d4aeee77 | 531 | return ret; |
54cf91dc CW |
532 | } |
533 | ||
dabdfe02 | 534 | static int |
27173f1f | 535 | need_reloc_mappable(struct i915_vma *vma) |
dabdfe02 | 536 | { |
27173f1f BW |
537 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
538 | return entry->relocation_count && !use_cpu_reloc(vma->obj) && | |
539 | i915_is_ggtt(vma->vm); | |
dabdfe02 CW |
540 | } |
541 | ||
1690e1eb | 542 | static int |
27173f1f | 543 | i915_gem_execbuffer_reserve_vma(struct i915_vma *vma, |
a4872ba6 | 544 | struct intel_engine_cs *ring, |
27173f1f | 545 | bool *need_reloc) |
1690e1eb | 546 | { |
6f65e29a | 547 | struct drm_i915_gem_object *obj = vma->obj; |
27173f1f | 548 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
1690e1eb | 549 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; |
1ec9e26d DV |
550 | bool need_fence; |
551 | unsigned flags; | |
1690e1eb CW |
552 | int ret; |
553 | ||
1ec9e26d DV |
554 | flags = 0; |
555 | ||
1690e1eb CW |
556 | need_fence = |
557 | has_fenced_gpu_access && | |
558 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
559 | obj->tiling_mode != I915_TILING_NONE; | |
1ec9e26d DV |
560 | if (need_fence || need_reloc_mappable(vma)) |
561 | flags |= PIN_MAPPABLE; | |
1690e1eb | 562 | |
1ec9e26d | 563 | if (entry->flags & EXEC_OBJECT_NEEDS_GTT) |
bf3d149b | 564 | flags |= PIN_GLOBAL; |
1ec9e26d DV |
565 | |
566 | ret = i915_gem_object_pin(obj, vma->vm, entry->alignment, flags); | |
1690e1eb CW |
567 | if (ret) |
568 | return ret; | |
569 | ||
7788a765 CW |
570 | entry->flags |= __EXEC_OBJECT_HAS_PIN; |
571 | ||
1690e1eb CW |
572 | if (has_fenced_gpu_access) { |
573 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { | |
06d98131 | 574 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 | 575 | if (ret) |
7788a765 | 576 | return ret; |
1690e1eb | 577 | |
9a5a53b3 | 578 | if (i915_gem_object_pin_fence(obj)) |
1690e1eb | 579 | entry->flags |= __EXEC_OBJECT_HAS_FENCE; |
9a5a53b3 | 580 | |
7dd49065 | 581 | obj->pending_fenced_gpu_access = true; |
1690e1eb | 582 | } |
1690e1eb CW |
583 | } |
584 | ||
27173f1f BW |
585 | if (entry->offset != vma->node.start) { |
586 | entry->offset = vma->node.start; | |
ed5982e6 DV |
587 | *need_reloc = true; |
588 | } | |
589 | ||
590 | if (entry->flags & EXEC_OBJECT_WRITE) { | |
591 | obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER; | |
592 | obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER; | |
593 | } | |
594 | ||
1690e1eb | 595 | return 0; |
7788a765 | 596 | } |
1690e1eb | 597 | |
54cf91dc | 598 | static int |
a4872ba6 | 599 | i915_gem_execbuffer_reserve(struct intel_engine_cs *ring, |
27173f1f | 600 | struct list_head *vmas, |
ed5982e6 | 601 | bool *need_relocs) |
54cf91dc | 602 | { |
432e58ed | 603 | struct drm_i915_gem_object *obj; |
27173f1f | 604 | struct i915_vma *vma; |
68c8c17f | 605 | struct i915_address_space *vm; |
27173f1f | 606 | struct list_head ordered_vmas; |
7788a765 CW |
607 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; |
608 | int retry; | |
6fe4f140 | 609 | |
68c8c17f BW |
610 | if (list_empty(vmas)) |
611 | return 0; | |
612 | ||
227f782e CW |
613 | i915_gem_retire_requests_ring(ring); |
614 | ||
68c8c17f BW |
615 | vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm; |
616 | ||
27173f1f BW |
617 | INIT_LIST_HEAD(&ordered_vmas); |
618 | while (!list_empty(vmas)) { | |
6fe4f140 CW |
619 | struct drm_i915_gem_exec_object2 *entry; |
620 | bool need_fence, need_mappable; | |
621 | ||
27173f1f BW |
622 | vma = list_first_entry(vmas, struct i915_vma, exec_list); |
623 | obj = vma->obj; | |
624 | entry = vma->exec_entry; | |
6fe4f140 CW |
625 | |
626 | need_fence = | |
627 | has_fenced_gpu_access && | |
628 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
629 | obj->tiling_mode != I915_TILING_NONE; | |
27173f1f | 630 | need_mappable = need_fence || need_reloc_mappable(vma); |
6fe4f140 CW |
631 | |
632 | if (need_mappable) | |
27173f1f | 633 | list_move(&vma->exec_list, &ordered_vmas); |
6fe4f140 | 634 | else |
27173f1f | 635 | list_move_tail(&vma->exec_list, &ordered_vmas); |
595dad76 | 636 | |
ed5982e6 | 637 | obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND; |
595dad76 | 638 | obj->base.pending_write_domain = 0; |
016fd0c1 | 639 | obj->pending_fenced_gpu_access = false; |
6fe4f140 | 640 | } |
27173f1f | 641 | list_splice(&ordered_vmas, vmas); |
54cf91dc CW |
642 | |
643 | /* Attempt to pin all of the buffers into the GTT. | |
644 | * This is done in 3 phases: | |
645 | * | |
646 | * 1a. Unbind all objects that do not match the GTT constraints for | |
647 | * the execbuffer (fenceable, mappable, alignment etc). | |
648 | * 1b. Increment pin count for already bound objects. | |
649 | * 2. Bind new objects. | |
650 | * 3. Decrement pin count. | |
651 | * | |
7788a765 | 652 | * This avoid unnecessary unbinding of later objects in order to make |
54cf91dc CW |
653 | * room for the earlier objects *unless* we need to defragment. |
654 | */ | |
655 | retry = 0; | |
656 | do { | |
7788a765 | 657 | int ret = 0; |
54cf91dc CW |
658 | |
659 | /* Unbind any ill-fitting objects or pin. */ | |
27173f1f BW |
660 | list_for_each_entry(vma, vmas, exec_list) { |
661 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; | |
54cf91dc | 662 | bool need_fence, need_mappable; |
1690e1eb | 663 | |
27173f1f BW |
664 | obj = vma->obj; |
665 | ||
666 | if (!drm_mm_node_allocated(&vma->node)) | |
54cf91dc CW |
667 | continue; |
668 | ||
669 | need_fence = | |
9b3826bf | 670 | has_fenced_gpu_access && |
54cf91dc CW |
671 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
672 | obj->tiling_mode != I915_TILING_NONE; | |
27173f1f | 673 | need_mappable = need_fence || need_reloc_mappable(vma); |
54cf91dc | 674 | |
28d6a7bf | 675 | WARN_ON((need_mappable || need_fence) && |
27173f1f | 676 | !i915_is_ggtt(vma->vm)); |
28d6a7bf | 677 | |
f343c5f6 | 678 | if ((entry->alignment && |
27173f1f | 679 | vma->node.start & (entry->alignment - 1)) || |
54cf91dc | 680 | (need_mappable && !obj->map_and_fenceable)) |
27173f1f | 681 | ret = i915_vma_unbind(vma); |
54cf91dc | 682 | else |
27173f1f | 683 | ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs); |
432e58ed | 684 | if (ret) |
54cf91dc | 685 | goto err; |
54cf91dc CW |
686 | } |
687 | ||
688 | /* Bind fresh objects */ | |
27173f1f BW |
689 | list_for_each_entry(vma, vmas, exec_list) { |
690 | if (drm_mm_node_allocated(&vma->node)) | |
1690e1eb | 691 | continue; |
54cf91dc | 692 | |
27173f1f | 693 | ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs); |
7788a765 CW |
694 | if (ret) |
695 | goto err; | |
54cf91dc CW |
696 | } |
697 | ||
a415d355 | 698 | err: |
6c085a72 | 699 | if (ret != -ENOSPC || retry++) |
54cf91dc CW |
700 | return ret; |
701 | ||
a415d355 CW |
702 | /* Decrement pin count for bound objects */ |
703 | list_for_each_entry(vma, vmas, exec_list) | |
704 | i915_gem_execbuffer_unreserve_vma(vma); | |
705 | ||
68c8c17f | 706 | ret = i915_gem_evict_vm(vm, true); |
54cf91dc CW |
707 | if (ret) |
708 | return ret; | |
54cf91dc CW |
709 | } while (1); |
710 | } | |
711 | ||
712 | static int | |
713 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, | |
ed5982e6 | 714 | struct drm_i915_gem_execbuffer2 *args, |
54cf91dc | 715 | struct drm_file *file, |
a4872ba6 | 716 | struct intel_engine_cs *ring, |
27173f1f BW |
717 | struct eb_vmas *eb, |
718 | struct drm_i915_gem_exec_object2 *exec) | |
54cf91dc CW |
719 | { |
720 | struct drm_i915_gem_relocation_entry *reloc; | |
27173f1f BW |
721 | struct i915_address_space *vm; |
722 | struct i915_vma *vma; | |
ed5982e6 | 723 | bool need_relocs; |
dd6864a4 | 724 | int *reloc_offset; |
54cf91dc | 725 | int i, total, ret; |
b205ca57 | 726 | unsigned count = args->buffer_count; |
54cf91dc | 727 | |
27173f1f BW |
728 | if (WARN_ON(list_empty(&eb->vmas))) |
729 | return 0; | |
730 | ||
731 | vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm; | |
732 | ||
67731b87 | 733 | /* We may process another execbuffer during the unlock... */ |
27173f1f BW |
734 | while (!list_empty(&eb->vmas)) { |
735 | vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list); | |
736 | list_del_init(&vma->exec_list); | |
a415d355 | 737 | i915_gem_execbuffer_unreserve_vma(vma); |
27173f1f | 738 | drm_gem_object_unreference(&vma->obj->base); |
67731b87 CW |
739 | } |
740 | ||
54cf91dc CW |
741 | mutex_unlock(&dev->struct_mutex); |
742 | ||
743 | total = 0; | |
744 | for (i = 0; i < count; i++) | |
432e58ed | 745 | total += exec[i].relocation_count; |
54cf91dc | 746 | |
dd6864a4 | 747 | reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset)); |
54cf91dc | 748 | reloc = drm_malloc_ab(total, sizeof(*reloc)); |
dd6864a4 CW |
749 | if (reloc == NULL || reloc_offset == NULL) { |
750 | drm_free_large(reloc); | |
751 | drm_free_large(reloc_offset); | |
54cf91dc CW |
752 | mutex_lock(&dev->struct_mutex); |
753 | return -ENOMEM; | |
754 | } | |
755 | ||
756 | total = 0; | |
757 | for (i = 0; i < count; i++) { | |
758 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
262b6d36 CW |
759 | u64 invalid_offset = (u64)-1; |
760 | int j; | |
54cf91dc | 761 | |
2bb4629a | 762 | user_relocs = to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
763 | |
764 | if (copy_from_user(reloc+total, user_relocs, | |
432e58ed | 765 | exec[i].relocation_count * sizeof(*reloc))) { |
54cf91dc CW |
766 | ret = -EFAULT; |
767 | mutex_lock(&dev->struct_mutex); | |
768 | goto err; | |
769 | } | |
770 | ||
262b6d36 CW |
771 | /* As we do not update the known relocation offsets after |
772 | * relocating (due to the complexities in lock handling), | |
773 | * we need to mark them as invalid now so that we force the | |
774 | * relocation processing next time. Just in case the target | |
775 | * object is evicted and then rebound into its old | |
776 | * presumed_offset before the next execbuffer - if that | |
777 | * happened we would make the mistake of assuming that the | |
778 | * relocations were valid. | |
779 | */ | |
780 | for (j = 0; j < exec[i].relocation_count; j++) { | |
781 | if (copy_to_user(&user_relocs[j].presumed_offset, | |
782 | &invalid_offset, | |
783 | sizeof(invalid_offset))) { | |
784 | ret = -EFAULT; | |
785 | mutex_lock(&dev->struct_mutex); | |
786 | goto err; | |
787 | } | |
788 | } | |
789 | ||
dd6864a4 | 790 | reloc_offset[i] = total; |
432e58ed | 791 | total += exec[i].relocation_count; |
54cf91dc CW |
792 | } |
793 | ||
794 | ret = i915_mutex_lock_interruptible(dev); | |
795 | if (ret) { | |
796 | mutex_lock(&dev->struct_mutex); | |
797 | goto err; | |
798 | } | |
799 | ||
67731b87 | 800 | /* reacquire the objects */ |
67731b87 | 801 | eb_reset(eb); |
27173f1f | 802 | ret = eb_lookup_vmas(eb, exec, args, vm, file); |
3b96eff4 CW |
803 | if (ret) |
804 | goto err; | |
67731b87 | 805 | |
ed5982e6 | 806 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
27173f1f | 807 | ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, &need_relocs); |
54cf91dc CW |
808 | if (ret) |
809 | goto err; | |
810 | ||
27173f1f BW |
811 | list_for_each_entry(vma, &eb->vmas, exec_list) { |
812 | int offset = vma->exec_entry - exec; | |
813 | ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb, | |
814 | reloc + reloc_offset[offset]); | |
54cf91dc CW |
815 | if (ret) |
816 | goto err; | |
54cf91dc CW |
817 | } |
818 | ||
819 | /* Leave the user relocations as are, this is the painfully slow path, | |
820 | * and we want to avoid the complication of dropping the lock whilst | |
821 | * having buffers reserved in the aperture and so causing spurious | |
822 | * ENOSPC for random operations. | |
823 | */ | |
824 | ||
825 | err: | |
826 | drm_free_large(reloc); | |
dd6864a4 | 827 | drm_free_large(reloc_offset); |
54cf91dc CW |
828 | return ret; |
829 | } | |
830 | ||
54cf91dc | 831 | static int |
a4872ba6 | 832 | i915_gem_execbuffer_move_to_gpu(struct intel_engine_cs *ring, |
27173f1f | 833 | struct list_head *vmas) |
54cf91dc | 834 | { |
27173f1f | 835 | struct i915_vma *vma; |
6ac42f41 | 836 | uint32_t flush_domains = 0; |
000433b6 | 837 | bool flush_chipset = false; |
432e58ed | 838 | int ret; |
54cf91dc | 839 | |
27173f1f BW |
840 | list_for_each_entry(vma, vmas, exec_list) { |
841 | struct drm_i915_gem_object *obj = vma->obj; | |
6ac42f41 | 842 | ret = i915_gem_object_sync(obj, ring); |
c59a333f CW |
843 | if (ret) |
844 | return ret; | |
6ac42f41 DV |
845 | |
846 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) | |
000433b6 | 847 | flush_chipset |= i915_gem_clflush_object(obj, false); |
6ac42f41 | 848 | |
6ac42f41 | 849 | flush_domains |= obj->base.write_domain; |
c59a333f CW |
850 | } |
851 | ||
000433b6 | 852 | if (flush_chipset) |
e76e9aeb | 853 | i915_gem_chipset_flush(ring->dev); |
6ac42f41 DV |
854 | |
855 | if (flush_domains & I915_GEM_DOMAIN_GTT) | |
856 | wmb(); | |
857 | ||
09cf7c9a CW |
858 | /* Unconditionally invalidate gpu caches and ensure that we do flush |
859 | * any residual writes from the previous batch. | |
860 | */ | |
a7b9761d | 861 | return intel_ring_invalidate_all_caches(ring); |
54cf91dc CW |
862 | } |
863 | ||
432e58ed CW |
864 | static bool |
865 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) | |
54cf91dc | 866 | { |
ed5982e6 DV |
867 | if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS) |
868 | return false; | |
869 | ||
432e58ed | 870 | return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0; |
54cf91dc CW |
871 | } |
872 | ||
873 | static int | |
874 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, | |
875 | int count) | |
876 | { | |
877 | int i; | |
b205ca57 DV |
878 | unsigned relocs_total = 0; |
879 | unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry); | |
54cf91dc CW |
880 | |
881 | for (i = 0; i < count; i++) { | |
2bb4629a | 882 | char __user *ptr = to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
883 | int length; /* limited by fault_in_pages_readable() */ |
884 | ||
ed5982e6 DV |
885 | if (exec[i].flags & __EXEC_OBJECT_UNKNOWN_FLAGS) |
886 | return -EINVAL; | |
887 | ||
3118a4f6 KC |
888 | /* First check for malicious input causing overflow in |
889 | * the worst case where we need to allocate the entire | |
890 | * relocation tree as a single array. | |
891 | */ | |
892 | if (exec[i].relocation_count > relocs_max - relocs_total) | |
54cf91dc | 893 | return -EINVAL; |
3118a4f6 | 894 | relocs_total += exec[i].relocation_count; |
54cf91dc CW |
895 | |
896 | length = exec[i].relocation_count * | |
897 | sizeof(struct drm_i915_gem_relocation_entry); | |
30587535 KC |
898 | /* |
899 | * We must check that the entire relocation array is safe | |
900 | * to read, but since we may need to update the presumed | |
901 | * offsets during execution, check for full write access. | |
902 | */ | |
54cf91dc CW |
903 | if (!access_ok(VERIFY_WRITE, ptr, length)) |
904 | return -EFAULT; | |
905 | ||
d330a953 | 906 | if (likely(!i915.prefault_disable)) { |
0b74b508 XZ |
907 | if (fault_in_multipages_readable(ptr, length)) |
908 | return -EFAULT; | |
909 | } | |
54cf91dc CW |
910 | } |
911 | ||
912 | return 0; | |
913 | } | |
914 | ||
41bde553 | 915 | static struct i915_hw_context * |
d299cce7 | 916 | i915_gem_validate_context(struct drm_device *dev, struct drm_file *file, |
a4872ba6 | 917 | struct intel_engine_cs *ring, const u32 ctx_id) |
d299cce7 | 918 | { |
41bde553 | 919 | struct i915_hw_context *ctx = NULL; |
d299cce7 MK |
920 | struct i915_ctx_hang_stats *hs; |
921 | ||
7c9c4b8f DV |
922 | if (ring->id != RCS && ctx_id != DEFAULT_CONTEXT_ID) |
923 | return ERR_PTR(-EINVAL); | |
924 | ||
41bde553 | 925 | ctx = i915_gem_context_get(file->driver_priv, ctx_id); |
72ad5c45 | 926 | if (IS_ERR(ctx)) |
41bde553 | 927 | return ctx; |
d299cce7 | 928 | |
41bde553 | 929 | hs = &ctx->hang_stats; |
d299cce7 MK |
930 | if (hs->banned) { |
931 | DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id); | |
41bde553 | 932 | return ERR_PTR(-EIO); |
d299cce7 MK |
933 | } |
934 | ||
41bde553 | 935 | return ctx; |
d299cce7 MK |
936 | } |
937 | ||
432e58ed | 938 | static void |
27173f1f | 939 | i915_gem_execbuffer_move_to_active(struct list_head *vmas, |
a4872ba6 | 940 | struct intel_engine_cs *ring) |
432e58ed | 941 | { |
27173f1f | 942 | struct i915_vma *vma; |
432e58ed | 943 | |
27173f1f BW |
944 | list_for_each_entry(vma, vmas, exec_list) { |
945 | struct drm_i915_gem_object *obj = vma->obj; | |
69c2fc89 CW |
946 | u32 old_read = obj->base.read_domains; |
947 | u32 old_write = obj->base.write_domain; | |
db53a302 | 948 | |
432e58ed | 949 | obj->base.write_domain = obj->base.pending_write_domain; |
ed5982e6 DV |
950 | if (obj->base.write_domain == 0) |
951 | obj->base.pending_read_domains |= obj->base.read_domains; | |
952 | obj->base.read_domains = obj->base.pending_read_domains; | |
432e58ed CW |
953 | obj->fenced_gpu_access = obj->pending_fenced_gpu_access; |
954 | ||
e2d05a8b | 955 | i915_vma_move_to_active(vma, ring); |
432e58ed CW |
956 | if (obj->base.write_domain) { |
957 | obj->dirty = 1; | |
9d773091 | 958 | obj->last_write_seqno = intel_ring_get_seqno(ring); |
d7f46fc4 BW |
959 | /* check for potential scanout */ |
960 | if (i915_gem_obj_ggtt_bound(obj) && | |
961 | i915_gem_obj_to_ggtt(obj)->pin_count) | |
c65355bb | 962 | intel_mark_fb_busy(obj, ring); |
c8725f3d CW |
963 | |
964 | /* update for the implicit flush after a batch */ | |
965 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
432e58ed CW |
966 | } |
967 | ||
db53a302 | 968 | trace_i915_gem_object_change_domain(obj, old_read, old_write); |
432e58ed CW |
969 | } |
970 | } | |
971 | ||
54cf91dc CW |
972 | static void |
973 | i915_gem_execbuffer_retire_commands(struct drm_device *dev, | |
432e58ed | 974 | struct drm_file *file, |
a4872ba6 | 975 | struct intel_engine_cs *ring, |
7d736f4f | 976 | struct drm_i915_gem_object *obj) |
54cf91dc | 977 | { |
cc889e0f DV |
978 | /* Unconditionally force add_request to emit a full flush. */ |
979 | ring->gpu_caches_dirty = true; | |
54cf91dc | 980 | |
432e58ed | 981 | /* Add a breadcrumb for the completion of the batch buffer */ |
7d736f4f | 982 | (void)__i915_add_request(ring, file, obj, NULL); |
432e58ed | 983 | } |
54cf91dc | 984 | |
ae662d31 EA |
985 | static int |
986 | i915_reset_gen7_sol_offsets(struct drm_device *dev, | |
a4872ba6 | 987 | struct intel_engine_cs *ring) |
ae662d31 | 988 | { |
50227e1c | 989 | struct drm_i915_private *dev_priv = dev->dev_private; |
ae662d31 EA |
990 | int ret, i; |
991 | ||
9d662da8 DV |
992 | if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) { |
993 | DRM_DEBUG("sol reset is gen7/rcs only\n"); | |
994 | return -EINVAL; | |
995 | } | |
ae662d31 EA |
996 | |
997 | ret = intel_ring_begin(ring, 4 * 3); | |
998 | if (ret) | |
999 | return ret; | |
1000 | ||
1001 | for (i = 0; i < 4; i++) { | |
1002 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
1003 | intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i)); | |
1004 | intel_ring_emit(ring, 0); | |
1005 | } | |
1006 | ||
1007 | intel_ring_advance(ring); | |
1008 | ||
1009 | return 0; | |
1010 | } | |
1011 | ||
a8ebba75 ZY |
1012 | /** |
1013 | * Find one BSD ring to dispatch the corresponding BSD command. | |
1014 | * The Ring ID is returned. | |
1015 | */ | |
1016 | static int gen8_dispatch_bsd_ring(struct drm_device *dev, | |
1017 | struct drm_file *file) | |
1018 | { | |
1019 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1020 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1021 | ||
1022 | /* Check whether the file_priv is using one ring */ | |
1023 | if (file_priv->bsd_ring) | |
1024 | return file_priv->bsd_ring->id; | |
1025 | else { | |
1026 | /* If no, use the ping-pong mechanism to select one ring */ | |
1027 | int ring_id; | |
1028 | ||
1029 | mutex_lock(&dev->struct_mutex); | |
bdf1e7e3 | 1030 | if (dev_priv->mm.bsd_ring_dispatch_index == 0) { |
a8ebba75 | 1031 | ring_id = VCS; |
bdf1e7e3 | 1032 | dev_priv->mm.bsd_ring_dispatch_index = 1; |
a8ebba75 ZY |
1033 | } else { |
1034 | ring_id = VCS2; | |
bdf1e7e3 | 1035 | dev_priv->mm.bsd_ring_dispatch_index = 0; |
a8ebba75 ZY |
1036 | } |
1037 | file_priv->bsd_ring = &dev_priv->ring[ring_id]; | |
1038 | mutex_unlock(&dev->struct_mutex); | |
1039 | return ring_id; | |
1040 | } | |
1041 | } | |
1042 | ||
54cf91dc CW |
1043 | static int |
1044 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, | |
1045 | struct drm_file *file, | |
1046 | struct drm_i915_gem_execbuffer2 *args, | |
41bde553 | 1047 | struct drm_i915_gem_exec_object2 *exec) |
54cf91dc | 1048 | { |
50227e1c | 1049 | struct drm_i915_private *dev_priv = dev->dev_private; |
27173f1f | 1050 | struct eb_vmas *eb; |
54cf91dc CW |
1051 | struct drm_i915_gem_object *batch_obj; |
1052 | struct drm_clip_rect *cliprects = NULL; | |
a4872ba6 | 1053 | struct intel_engine_cs *ring; |
41bde553 BW |
1054 | struct i915_hw_context *ctx; |
1055 | struct i915_address_space *vm; | |
d299cce7 | 1056 | const u32 ctx_id = i915_execbuffer2_get_context_id(*args); |
9bcb144c | 1057 | u64 exec_start = args->batch_start_offset, exec_len; |
ed5982e6 | 1058 | u32 mask, flags; |
72bfa19c | 1059 | int ret, mode, i; |
ed5982e6 | 1060 | bool need_relocs; |
54cf91dc | 1061 | |
ed5982e6 | 1062 | if (!i915_gem_check_execbuffer(args)) |
432e58ed | 1063 | return -EINVAL; |
432e58ed CW |
1064 | |
1065 | ret = validate_exec_list(exec, args->buffer_count); | |
54cf91dc CW |
1066 | if (ret) |
1067 | return ret; | |
1068 | ||
d7d4eedd CW |
1069 | flags = 0; |
1070 | if (args->flags & I915_EXEC_SECURE) { | |
1071 | if (!file->is_master || !capable(CAP_SYS_ADMIN)) | |
1072 | return -EPERM; | |
1073 | ||
1074 | flags |= I915_DISPATCH_SECURE; | |
1075 | } | |
b45305fc DV |
1076 | if (args->flags & I915_EXEC_IS_PINNED) |
1077 | flags |= I915_DISPATCH_PINNED; | |
d7d4eedd | 1078 | |
b1a93306 | 1079 | if ((args->flags & I915_EXEC_RING_MASK) > LAST_USER_RING) { |
ff240199 | 1080 | DRM_DEBUG("execbuf with unknown ring: %d\n", |
54cf91dc CW |
1081 | (int)(args->flags & I915_EXEC_RING_MASK)); |
1082 | return -EINVAL; | |
1083 | } | |
ca01b12b BW |
1084 | |
1085 | if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_DEFAULT) | |
1086 | ring = &dev_priv->ring[RCS]; | |
a8ebba75 ZY |
1087 | else if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_BSD) { |
1088 | if (HAS_BSD2(dev)) { | |
1089 | int ring_id; | |
1090 | ring_id = gen8_dispatch_bsd_ring(dev, file); | |
1091 | ring = &dev_priv->ring[ring_id]; | |
1092 | } else | |
1093 | ring = &dev_priv->ring[VCS]; | |
1094 | } else | |
ca01b12b BW |
1095 | ring = &dev_priv->ring[(args->flags & I915_EXEC_RING_MASK) - 1]; |
1096 | ||
a15817cf CW |
1097 | if (!intel_ring_initialized(ring)) { |
1098 | DRM_DEBUG("execbuf with invalid ring: %d\n", | |
1099 | (int)(args->flags & I915_EXEC_RING_MASK)); | |
1100 | return -EINVAL; | |
1101 | } | |
54cf91dc | 1102 | |
72bfa19c | 1103 | mode = args->flags & I915_EXEC_CONSTANTS_MASK; |
84f9f938 | 1104 | mask = I915_EXEC_CONSTANTS_MASK; |
72bfa19c CW |
1105 | switch (mode) { |
1106 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
1107 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
1108 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
c0f5b82c DV |
1109 | if (mode != 0 && ring != &dev_priv->ring[RCS]) { |
1110 | DRM_DEBUG("non-0 rel constants mode on non-RCS\n"); | |
1111 | return -EINVAL; | |
1112 | } | |
1113 | ||
1114 | if (mode != dev_priv->relative_constants_mode) { | |
1115 | if (INTEL_INFO(dev)->gen < 4) { | |
1116 | DRM_DEBUG("no rel constants on pre-gen4\n"); | |
72bfa19c | 1117 | return -EINVAL; |
c0f5b82c | 1118 | } |
72bfa19c CW |
1119 | |
1120 | if (INTEL_INFO(dev)->gen > 5 && | |
c0f5b82c DV |
1121 | mode == I915_EXEC_CONSTANTS_REL_SURFACE) { |
1122 | DRM_DEBUG("rel surface constants mode invalid on gen5+\n"); | |
72bfa19c | 1123 | return -EINVAL; |
c0f5b82c | 1124 | } |
84f9f938 BW |
1125 | |
1126 | /* The HW changed the meaning on this bit on gen6 */ | |
1127 | if (INTEL_INFO(dev)->gen >= 6) | |
1128 | mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
72bfa19c CW |
1129 | } |
1130 | break; | |
1131 | default: | |
ff240199 | 1132 | DRM_DEBUG("execbuf with unknown constants: %d\n", mode); |
72bfa19c CW |
1133 | return -EINVAL; |
1134 | } | |
1135 | ||
54cf91dc | 1136 | if (args->buffer_count < 1) { |
ff240199 | 1137 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1138 | return -EINVAL; |
1139 | } | |
54cf91dc CW |
1140 | |
1141 | if (args->num_cliprects != 0) { | |
1ec14ad3 | 1142 | if (ring != &dev_priv->ring[RCS]) { |
ff240199 | 1143 | DRM_DEBUG("clip rectangles are only valid with the render ring\n"); |
c4e7a414 CW |
1144 | return -EINVAL; |
1145 | } | |
1146 | ||
6ebebc92 DV |
1147 | if (INTEL_INFO(dev)->gen >= 5) { |
1148 | DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); | |
1149 | return -EINVAL; | |
1150 | } | |
1151 | ||
44afb3a0 XW |
1152 | if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) { |
1153 | DRM_DEBUG("execbuf with %u cliprects\n", | |
1154 | args->num_cliprects); | |
1155 | return -EINVAL; | |
1156 | } | |
5e13a0c5 | 1157 | |
a1e22653 DV |
1158 | cliprects = kcalloc(args->num_cliprects, |
1159 | sizeof(*cliprects), | |
54cf91dc CW |
1160 | GFP_KERNEL); |
1161 | if (cliprects == NULL) { | |
1162 | ret = -ENOMEM; | |
1163 | goto pre_mutex_err; | |
1164 | } | |
1165 | ||
432e58ed | 1166 | if (copy_from_user(cliprects, |
2bb4629a VS |
1167 | to_user_ptr(args->cliprects_ptr), |
1168 | sizeof(*cliprects)*args->num_cliprects)) { | |
54cf91dc CW |
1169 | ret = -EFAULT; |
1170 | goto pre_mutex_err; | |
1171 | } | |
9cb34664 | 1172 | } else { |
ffd93f24 DV |
1173 | if (args->DR4 == 0xffffffff) { |
1174 | DRM_DEBUG("UXA submitting garbage DR4, fixing up\n"); | |
1175 | args->DR4 = 0; | |
1176 | } | |
1177 | ||
9cb34664 DV |
1178 | if (args->DR1 || args->DR4 || args->cliprects_ptr) { |
1179 | DRM_DEBUG("0 cliprects but dirt in cliprects fields\n"); | |
1180 | return -EINVAL; | |
1181 | } | |
54cf91dc CW |
1182 | } |
1183 | ||
f65c9168 PZ |
1184 | intel_runtime_pm_get(dev_priv); |
1185 | ||
54cf91dc CW |
1186 | ret = i915_mutex_lock_interruptible(dev); |
1187 | if (ret) | |
1188 | goto pre_mutex_err; | |
1189 | ||
db1b76ca | 1190 | if (dev_priv->ums.mm_suspended) { |
54cf91dc CW |
1191 | mutex_unlock(&dev->struct_mutex); |
1192 | ret = -EBUSY; | |
1193 | goto pre_mutex_err; | |
1194 | } | |
1195 | ||
7c9c4b8f | 1196 | ctx = i915_gem_validate_context(dev, file, ring, ctx_id); |
72ad5c45 | 1197 | if (IS_ERR(ctx)) { |
d299cce7 | 1198 | mutex_unlock(&dev->struct_mutex); |
41bde553 | 1199 | ret = PTR_ERR(ctx); |
d299cce7 | 1200 | goto pre_mutex_err; |
935f38d6 | 1201 | } |
41bde553 BW |
1202 | |
1203 | i915_gem_context_reference(ctx); | |
1204 | ||
7e0d96bc BW |
1205 | vm = ctx->vm; |
1206 | if (!USES_FULL_PPGTT(dev)) | |
1207 | vm = &dev_priv->gtt.base; | |
d299cce7 | 1208 | |
17601cbc | 1209 | eb = eb_create(args); |
67731b87 | 1210 | if (eb == NULL) { |
935f38d6 | 1211 | i915_gem_context_unreference(ctx); |
67731b87 CW |
1212 | mutex_unlock(&dev->struct_mutex); |
1213 | ret = -ENOMEM; | |
1214 | goto pre_mutex_err; | |
1215 | } | |
1216 | ||
54cf91dc | 1217 | /* Look up object handles */ |
27173f1f | 1218 | ret = eb_lookup_vmas(eb, exec, args, vm, file); |
3b96eff4 CW |
1219 | if (ret) |
1220 | goto err; | |
54cf91dc | 1221 | |
6fe4f140 | 1222 | /* take note of the batch buffer before we might reorder the lists */ |
27173f1f | 1223 | batch_obj = list_entry(eb->vmas.prev, struct i915_vma, exec_list)->obj; |
6fe4f140 | 1224 | |
54cf91dc | 1225 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
ed5982e6 | 1226 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
27173f1f | 1227 | ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, &need_relocs); |
54cf91dc CW |
1228 | if (ret) |
1229 | goto err; | |
1230 | ||
1231 | /* The objects are in their final locations, apply the relocations. */ | |
ed5982e6 | 1232 | if (need_relocs) |
17601cbc | 1233 | ret = i915_gem_execbuffer_relocate(eb); |
54cf91dc CW |
1234 | if (ret) { |
1235 | if (ret == -EFAULT) { | |
ed5982e6 | 1236 | ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring, |
27173f1f | 1237 | eb, exec); |
54cf91dc CW |
1238 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
1239 | } | |
1240 | if (ret) | |
1241 | goto err; | |
1242 | } | |
1243 | ||
1244 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
54cf91dc | 1245 | if (batch_obj->base.pending_write_domain) { |
ff240199 | 1246 | DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); |
54cf91dc CW |
1247 | ret = -EINVAL; |
1248 | goto err; | |
1249 | } | |
1250 | batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
1251 | ||
351e3db2 BV |
1252 | if (i915_needs_cmd_parser(ring)) { |
1253 | ret = i915_parse_cmds(ring, | |
1254 | batch_obj, | |
1255 | args->batch_start_offset, | |
1256 | file->is_master); | |
1257 | if (ret) | |
1258 | goto err; | |
1259 | ||
1260 | /* | |
1261 | * XXX: Actually do this when enabling batch copy... | |
1262 | * | |
1263 | * Set the DISPATCH_SECURE bit to remove the NON_SECURE bit | |
1264 | * from MI_BATCH_BUFFER_START commands issued in the | |
1265 | * dispatch_execbuffer implementations. We specifically don't | |
1266 | * want that set when the command parser is enabled. | |
1267 | */ | |
1268 | } | |
1269 | ||
d7d4eedd CW |
1270 | /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure |
1271 | * batch" bit. Hence we need to pin secure batches into the global gtt. | |
28cf5415 | 1272 | * hsw should have this fixed, but bdw mucks it up again. */ |
6f65e29a BW |
1273 | if (flags & I915_DISPATCH_SECURE && |
1274 | !batch_obj->has_global_gtt_mapping) { | |
1275 | /* When we have multiple VMs, we'll need to make sure that we | |
1276 | * allocate space first */ | |
1277 | struct i915_vma *vma = i915_gem_obj_to_ggtt(batch_obj); | |
1278 | BUG_ON(!vma); | |
1279 | vma->bind_vma(vma, batch_obj->cache_level, GLOBAL_BIND); | |
1280 | } | |
d7d4eedd | 1281 | |
7e0d96bc BW |
1282 | if (flags & I915_DISPATCH_SECURE) |
1283 | exec_start += i915_gem_obj_ggtt_offset(batch_obj); | |
1284 | else | |
1285 | exec_start += i915_gem_obj_offset(batch_obj, vm); | |
d7d4eedd | 1286 | |
27173f1f | 1287 | ret = i915_gem_execbuffer_move_to_gpu(ring, &eb->vmas); |
432e58ed | 1288 | if (ret) |
54cf91dc | 1289 | goto err; |
54cf91dc | 1290 | |
691e6415 | 1291 | ret = i915_switch_context(ring, ctx); |
0da5cec1 EA |
1292 | if (ret) |
1293 | goto err; | |
1294 | ||
e2971bda BW |
1295 | if (ring == &dev_priv->ring[RCS] && |
1296 | mode != dev_priv->relative_constants_mode) { | |
1297 | ret = intel_ring_begin(ring, 4); | |
1298 | if (ret) | |
1299 | goto err; | |
1300 | ||
1301 | intel_ring_emit(ring, MI_NOOP); | |
1302 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
1303 | intel_ring_emit(ring, INSTPM); | |
84f9f938 | 1304 | intel_ring_emit(ring, mask << 16 | mode); |
e2971bda BW |
1305 | intel_ring_advance(ring); |
1306 | ||
1307 | dev_priv->relative_constants_mode = mode; | |
1308 | } | |
1309 | ||
ae662d31 EA |
1310 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { |
1311 | ret = i915_reset_gen7_sol_offsets(dev, ring); | |
1312 | if (ret) | |
1313 | goto err; | |
1314 | } | |
1315 | ||
7e0d96bc | 1316 | |
c4e7a414 CW |
1317 | exec_len = args->batch_len; |
1318 | if (cliprects) { | |
1319 | for (i = 0; i < args->num_cliprects; i++) { | |
1320 | ret = i915_emit_box(dev, &cliprects[i], | |
1321 | args->DR1, args->DR4); | |
1322 | if (ret) | |
1323 | goto err; | |
1324 | ||
1325 | ret = ring->dispatch_execbuffer(ring, | |
d7d4eedd CW |
1326 | exec_start, exec_len, |
1327 | flags); | |
c4e7a414 CW |
1328 | if (ret) |
1329 | goto err; | |
1330 | } | |
1331 | } else { | |
d7d4eedd CW |
1332 | ret = ring->dispatch_execbuffer(ring, |
1333 | exec_start, exec_len, | |
1334 | flags); | |
c4e7a414 CW |
1335 | if (ret) |
1336 | goto err; | |
1337 | } | |
54cf91dc | 1338 | |
9d773091 CW |
1339 | trace_i915_gem_ring_dispatch(ring, intel_ring_get_seqno(ring), flags); |
1340 | ||
27173f1f | 1341 | i915_gem_execbuffer_move_to_active(&eb->vmas, ring); |
7d736f4f | 1342 | i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj); |
54cf91dc CW |
1343 | |
1344 | err: | |
41bde553 BW |
1345 | /* the request owns the ref now */ |
1346 | i915_gem_context_unreference(ctx); | |
67731b87 | 1347 | eb_destroy(eb); |
54cf91dc CW |
1348 | |
1349 | mutex_unlock(&dev->struct_mutex); | |
1350 | ||
1351 | pre_mutex_err: | |
54cf91dc | 1352 | kfree(cliprects); |
f65c9168 PZ |
1353 | |
1354 | /* intel_gpu_busy should also get a ref, so it will free when the device | |
1355 | * is really idle. */ | |
1356 | intel_runtime_pm_put(dev_priv); | |
54cf91dc CW |
1357 | return ret; |
1358 | } | |
1359 | ||
1360 | /* | |
1361 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
1362 | * list array and passes it to the real function. | |
1363 | */ | |
1364 | int | |
1365 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1366 | struct drm_file *file) | |
1367 | { | |
1368 | struct drm_i915_gem_execbuffer *args = data; | |
1369 | struct drm_i915_gem_execbuffer2 exec2; | |
1370 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
1371 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1372 | int ret, i; | |
1373 | ||
54cf91dc | 1374 | if (args->buffer_count < 1) { |
ff240199 | 1375 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1376 | return -EINVAL; |
1377 | } | |
1378 | ||
1379 | /* Copy in the exec list from userland */ | |
1380 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
1381 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
1382 | if (exec_list == NULL || exec2_list == NULL) { | |
ff240199 | 1383 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1384 | args->buffer_count); |
1385 | drm_free_large(exec_list); | |
1386 | drm_free_large(exec2_list); | |
1387 | return -ENOMEM; | |
1388 | } | |
1389 | ret = copy_from_user(exec_list, | |
2bb4629a | 1390 | to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1391 | sizeof(*exec_list) * args->buffer_count); |
1392 | if (ret != 0) { | |
ff240199 | 1393 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1394 | args->buffer_count, ret); |
1395 | drm_free_large(exec_list); | |
1396 | drm_free_large(exec2_list); | |
1397 | return -EFAULT; | |
1398 | } | |
1399 | ||
1400 | for (i = 0; i < args->buffer_count; i++) { | |
1401 | exec2_list[i].handle = exec_list[i].handle; | |
1402 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
1403 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
1404 | exec2_list[i].alignment = exec_list[i].alignment; | |
1405 | exec2_list[i].offset = exec_list[i].offset; | |
1406 | if (INTEL_INFO(dev)->gen < 4) | |
1407 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; | |
1408 | else | |
1409 | exec2_list[i].flags = 0; | |
1410 | } | |
1411 | ||
1412 | exec2.buffers_ptr = args->buffers_ptr; | |
1413 | exec2.buffer_count = args->buffer_count; | |
1414 | exec2.batch_start_offset = args->batch_start_offset; | |
1415 | exec2.batch_len = args->batch_len; | |
1416 | exec2.DR1 = args->DR1; | |
1417 | exec2.DR4 = args->DR4; | |
1418 | exec2.num_cliprects = args->num_cliprects; | |
1419 | exec2.cliprects_ptr = args->cliprects_ptr; | |
1420 | exec2.flags = I915_EXEC_RENDER; | |
6e0a69db | 1421 | i915_execbuffer2_set_context_id(exec2, 0); |
54cf91dc | 1422 | |
41bde553 | 1423 | ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list); |
54cf91dc CW |
1424 | if (!ret) { |
1425 | /* Copy the new buffer offsets back to the user's exec list. */ | |
1426 | for (i = 0; i < args->buffer_count; i++) | |
1427 | exec_list[i].offset = exec2_list[i].offset; | |
1428 | /* ... and back out to userspace */ | |
2bb4629a | 1429 | ret = copy_to_user(to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1430 | exec_list, |
1431 | sizeof(*exec_list) * args->buffer_count); | |
1432 | if (ret) { | |
1433 | ret = -EFAULT; | |
ff240199 | 1434 | DRM_DEBUG("failed to copy %d exec entries " |
54cf91dc CW |
1435 | "back to user (%d)\n", |
1436 | args->buffer_count, ret); | |
1437 | } | |
1438 | } | |
1439 | ||
1440 | drm_free_large(exec_list); | |
1441 | drm_free_large(exec2_list); | |
1442 | return ret; | |
1443 | } | |
1444 | ||
1445 | int | |
1446 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
1447 | struct drm_file *file) | |
1448 | { | |
1449 | struct drm_i915_gem_execbuffer2 *args = data; | |
1450 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1451 | int ret; | |
1452 | ||
ed8cd3b2 XW |
1453 | if (args->buffer_count < 1 || |
1454 | args->buffer_count > UINT_MAX / sizeof(*exec2_list)) { | |
ff240199 | 1455 | DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1456 | return -EINVAL; |
1457 | } | |
1458 | ||
9cb34664 DV |
1459 | if (args->rsvd2 != 0) { |
1460 | DRM_DEBUG("dirty rvsd2 field\n"); | |
1461 | return -EINVAL; | |
1462 | } | |
1463 | ||
8408c282 | 1464 | exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count, |
419fa72a | 1465 | GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); |
8408c282 CW |
1466 | if (exec2_list == NULL) |
1467 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), | |
1468 | args->buffer_count); | |
54cf91dc | 1469 | if (exec2_list == NULL) { |
ff240199 | 1470 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1471 | args->buffer_count); |
1472 | return -ENOMEM; | |
1473 | } | |
1474 | ret = copy_from_user(exec2_list, | |
2bb4629a | 1475 | to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1476 | sizeof(*exec2_list) * args->buffer_count); |
1477 | if (ret != 0) { | |
ff240199 | 1478 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1479 | args->buffer_count, ret); |
1480 | drm_free_large(exec2_list); | |
1481 | return -EFAULT; | |
1482 | } | |
1483 | ||
41bde553 | 1484 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list); |
54cf91dc CW |
1485 | if (!ret) { |
1486 | /* Copy the new buffer offsets back to the user's exec list. */ | |
2bb4629a | 1487 | ret = copy_to_user(to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1488 | exec2_list, |
1489 | sizeof(*exec2_list) * args->buffer_count); | |
1490 | if (ret) { | |
1491 | ret = -EFAULT; | |
ff240199 | 1492 | DRM_DEBUG("failed to copy %d exec entries " |
54cf91dc CW |
1493 | "back to user (%d)\n", |
1494 | args->buffer_count, ret); | |
1495 | } | |
1496 | } | |
1497 | ||
1498 | drm_free_large(exec2_list); | |
1499 | return ret; | |
1500 | } |