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54cf91dc CW |
1 | /* |
2 | * Copyright © 2008,2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Chris Wilson <chris@chris-wilson.co.uk> | |
26 | * | |
27 | */ | |
28 | ||
760285e7 DH |
29 | #include <drm/drmP.h> |
30 | #include <drm/i915_drm.h> | |
54cf91dc CW |
31 | #include "i915_drv.h" |
32 | #include "i915_trace.h" | |
33 | #include "intel_drv.h" | |
f45b5557 | 34 | #include <linux/dma_remapping.h> |
54cf91dc CW |
35 | |
36 | struct change_domains { | |
37 | uint32_t invalidate_domains; | |
38 | uint32_t flush_domains; | |
39 | uint32_t flush_rings; | |
c59a333f | 40 | uint32_t flips; |
54cf91dc CW |
41 | }; |
42 | ||
43 | /* | |
44 | * Set the next domain for the specified object. This | |
45 | * may not actually perform the necessary flushing/invaliding though, | |
46 | * as that may want to be batched with other set_domain operations | |
47 | * | |
48 | * This is (we hope) the only really tricky part of gem. The goal | |
49 | * is fairly simple -- track which caches hold bits of the object | |
50 | * and make sure they remain coherent. A few concrete examples may | |
51 | * help to explain how it works. For shorthand, we use the notation | |
52 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the | |
53 | * a pair of read and write domain masks. | |
54 | * | |
55 | * Case 1: the batch buffer | |
56 | * | |
57 | * 1. Allocated | |
58 | * 2. Written by CPU | |
59 | * 3. Mapped to GTT | |
60 | * 4. Read by GPU | |
61 | * 5. Unmapped from GTT | |
62 | * 6. Freed | |
63 | * | |
64 | * Let's take these a step at a time | |
65 | * | |
66 | * 1. Allocated | |
67 | * Pages allocated from the kernel may still have | |
68 | * cache contents, so we set them to (CPU, CPU) always. | |
69 | * 2. Written by CPU (using pwrite) | |
70 | * The pwrite function calls set_domain (CPU, CPU) and | |
71 | * this function does nothing (as nothing changes) | |
72 | * 3. Mapped by GTT | |
73 | * This function asserts that the object is not | |
74 | * currently in any GPU-based read or write domains | |
75 | * 4. Read by GPU | |
76 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). | |
77 | * As write_domain is zero, this function adds in the | |
78 | * current read domains (CPU+COMMAND, 0). | |
79 | * flush_domains is set to CPU. | |
80 | * invalidate_domains is set to COMMAND | |
81 | * clflush is run to get data out of the CPU caches | |
82 | * then i915_dev_set_domain calls i915_gem_flush to | |
83 | * emit an MI_FLUSH and drm_agp_chipset_flush | |
84 | * 5. Unmapped from GTT | |
85 | * i915_gem_object_unbind calls set_domain (CPU, CPU) | |
86 | * flush_domains and invalidate_domains end up both zero | |
87 | * so no flushing/invalidating happens | |
88 | * 6. Freed | |
89 | * yay, done | |
90 | * | |
91 | * Case 2: The shared render buffer | |
92 | * | |
93 | * 1. Allocated | |
94 | * 2. Mapped to GTT | |
95 | * 3. Read/written by GPU | |
96 | * 4. set_domain to (CPU,CPU) | |
97 | * 5. Read/written by CPU | |
98 | * 6. Read/written by GPU | |
99 | * | |
100 | * 1. Allocated | |
101 | * Same as last example, (CPU, CPU) | |
102 | * 2. Mapped to GTT | |
103 | * Nothing changes (assertions find that it is not in the GPU) | |
104 | * 3. Read/written by GPU | |
105 | * execbuffer calls set_domain (RENDER, RENDER) | |
106 | * flush_domains gets CPU | |
107 | * invalidate_domains gets GPU | |
108 | * clflush (obj) | |
109 | * MI_FLUSH and drm_agp_chipset_flush | |
110 | * 4. set_domain (CPU, CPU) | |
111 | * flush_domains gets GPU | |
112 | * invalidate_domains gets CPU | |
113 | * wait_rendering (obj) to make sure all drawing is complete. | |
114 | * This will include an MI_FLUSH to get the data from GPU | |
115 | * to memory | |
116 | * clflush (obj) to invalidate the CPU cache | |
117 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) | |
118 | * 5. Read/written by CPU | |
119 | * cache lines are loaded and dirtied | |
120 | * 6. Read written by GPU | |
121 | * Same as last GPU access | |
122 | * | |
123 | * Case 3: The constant buffer | |
124 | * | |
125 | * 1. Allocated | |
126 | * 2. Written by CPU | |
127 | * 3. Read by GPU | |
128 | * 4. Updated (written) by CPU again | |
129 | * 5. Read by GPU | |
130 | * | |
131 | * 1. Allocated | |
132 | * (CPU, CPU) | |
133 | * 2. Written by CPU | |
134 | * (CPU, CPU) | |
135 | * 3. Read by GPU | |
136 | * (CPU+RENDER, 0) | |
137 | * flush_domains = CPU | |
138 | * invalidate_domains = RENDER | |
139 | * clflush (obj) | |
140 | * MI_FLUSH | |
141 | * drm_agp_chipset_flush | |
142 | * 4. Updated (written) by CPU again | |
143 | * (CPU, CPU) | |
144 | * flush_domains = 0 (no previous write domain) | |
145 | * invalidate_domains = 0 (no new read domains) | |
146 | * 5. Read by GPU | |
147 | * (CPU+RENDER, 0) | |
148 | * flush_domains = CPU | |
149 | * invalidate_domains = RENDER | |
150 | * clflush (obj) | |
151 | * MI_FLUSH | |
152 | * drm_agp_chipset_flush | |
153 | */ | |
154 | static void | |
155 | i915_gem_object_set_to_gpu_domain(struct drm_i915_gem_object *obj, | |
156 | struct intel_ring_buffer *ring, | |
157 | struct change_domains *cd) | |
158 | { | |
159 | uint32_t invalidate_domains = 0, flush_domains = 0; | |
160 | ||
161 | /* | |
162 | * If the object isn't moving to a new write domain, | |
163 | * let the object stay in multiple read domains | |
164 | */ | |
165 | if (obj->base.pending_write_domain == 0) | |
166 | obj->base.pending_read_domains |= obj->base.read_domains; | |
167 | ||
168 | /* | |
169 | * Flush the current write domain if | |
170 | * the new read domains don't match. Invalidate | |
171 | * any read domains which differ from the old | |
172 | * write domain | |
173 | */ | |
174 | if (obj->base.write_domain && | |
175 | (((obj->base.write_domain != obj->base.pending_read_domains || | |
176 | obj->ring != ring)) || | |
177 | (obj->fenced_gpu_access && !obj->pending_fenced_gpu_access))) { | |
178 | flush_domains |= obj->base.write_domain; | |
179 | invalidate_domains |= | |
180 | obj->base.pending_read_domains & ~obj->base.write_domain; | |
181 | } | |
182 | /* | |
183 | * Invalidate any read caches which may have | |
184 | * stale data. That is, any new read domains. | |
185 | */ | |
186 | invalidate_domains |= obj->base.pending_read_domains & ~obj->base.read_domains; | |
187 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) | |
188 | i915_gem_clflush_object(obj); | |
189 | ||
c59a333f CW |
190 | if (obj->base.pending_write_domain) |
191 | cd->flips |= atomic_read(&obj->pending_flip); | |
192 | ||
54cf91dc CW |
193 | /* The actual obj->write_domain will be updated with |
194 | * pending_write_domain after we emit the accumulated flush for all | |
195 | * of our domain changes in execbuffers (which clears objects' | |
196 | * write_domains). So if we have a current write domain that we | |
197 | * aren't changing, set pending_write_domain to that. | |
198 | */ | |
199 | if (flush_domains == 0 && obj->base.pending_write_domain == 0) | |
200 | obj->base.pending_write_domain = obj->base.write_domain; | |
201 | ||
202 | cd->invalidate_domains |= invalidate_domains; | |
203 | cd->flush_domains |= flush_domains; | |
204 | if (flush_domains & I915_GEM_GPU_DOMAINS) | |
96154f2f | 205 | cd->flush_rings |= intel_ring_flag(obj->ring); |
54cf91dc | 206 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) |
96154f2f | 207 | cd->flush_rings |= intel_ring_flag(ring); |
54cf91dc CW |
208 | } |
209 | ||
67731b87 CW |
210 | struct eb_objects { |
211 | int and; | |
212 | struct hlist_head buckets[0]; | |
213 | }; | |
214 | ||
215 | static struct eb_objects * | |
216 | eb_create(int size) | |
217 | { | |
218 | struct eb_objects *eb; | |
219 | int count = PAGE_SIZE / sizeof(struct hlist_head) / 2; | |
220 | while (count > size) | |
221 | count >>= 1; | |
222 | eb = kzalloc(count*sizeof(struct hlist_head) + | |
223 | sizeof(struct eb_objects), | |
224 | GFP_KERNEL); | |
225 | if (eb == NULL) | |
226 | return eb; | |
227 | ||
228 | eb->and = count - 1; | |
229 | return eb; | |
230 | } | |
231 | ||
232 | static void | |
233 | eb_reset(struct eb_objects *eb) | |
234 | { | |
235 | memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head)); | |
236 | } | |
237 | ||
238 | static void | |
239 | eb_add_object(struct eb_objects *eb, struct drm_i915_gem_object *obj) | |
240 | { | |
241 | hlist_add_head(&obj->exec_node, | |
242 | &eb->buckets[obj->exec_handle & eb->and]); | |
243 | } | |
244 | ||
245 | static struct drm_i915_gem_object * | |
246 | eb_get_object(struct eb_objects *eb, unsigned long handle) | |
247 | { | |
248 | struct hlist_head *head; | |
249 | struct hlist_node *node; | |
250 | struct drm_i915_gem_object *obj; | |
251 | ||
252 | head = &eb->buckets[handle & eb->and]; | |
253 | hlist_for_each(node, head) { | |
254 | obj = hlist_entry(node, struct drm_i915_gem_object, exec_node); | |
255 | if (obj->exec_handle == handle) | |
256 | return obj; | |
257 | } | |
258 | ||
259 | return NULL; | |
260 | } | |
261 | ||
262 | static void | |
263 | eb_destroy(struct eb_objects *eb) | |
264 | { | |
265 | kfree(eb); | |
266 | } | |
267 | ||
dabdfe02 CW |
268 | static inline int use_cpu_reloc(struct drm_i915_gem_object *obj) |
269 | { | |
270 | return (obj->base.write_domain == I915_GEM_DOMAIN_CPU || | |
271 | obj->cache_level != I915_CACHE_NONE); | |
272 | } | |
273 | ||
54cf91dc CW |
274 | static int |
275 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, | |
67731b87 | 276 | struct eb_objects *eb, |
54cf91dc CW |
277 | struct drm_i915_gem_relocation_entry *reloc) |
278 | { | |
279 | struct drm_device *dev = obj->base.dev; | |
280 | struct drm_gem_object *target_obj; | |
149c8407 | 281 | struct drm_i915_gem_object *target_i915_obj; |
54cf91dc CW |
282 | uint32_t target_offset; |
283 | int ret = -EINVAL; | |
284 | ||
67731b87 CW |
285 | /* we've already hold a reference to all valid objects */ |
286 | target_obj = &eb_get_object(eb, reloc->target_handle)->base; | |
287 | if (unlikely(target_obj == NULL)) | |
54cf91dc CW |
288 | return -ENOENT; |
289 | ||
149c8407 DV |
290 | target_i915_obj = to_intel_bo(target_obj); |
291 | target_offset = target_i915_obj->gtt_offset; | |
54cf91dc | 292 | |
e844b990 EA |
293 | /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and |
294 | * pipe_control writes because the gpu doesn't properly redirect them | |
295 | * through the ppgtt for non_secure batchbuffers. */ | |
296 | if (unlikely(IS_GEN6(dev) && | |
297 | reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION && | |
298 | !target_i915_obj->has_global_gtt_mapping)) { | |
299 | i915_gem_gtt_bind_object(target_i915_obj, | |
300 | target_i915_obj->cache_level); | |
301 | } | |
302 | ||
54cf91dc CW |
303 | /* The target buffer should have appeared before us in the |
304 | * exec_object list, so it should have a GTT space bound by now. | |
305 | */ | |
b8f7ab17 | 306 | if (unlikely(target_offset == 0)) { |
ff240199 | 307 | DRM_DEBUG("No GTT space found for object %d\n", |
54cf91dc | 308 | reloc->target_handle); |
67731b87 | 309 | return ret; |
54cf91dc CW |
310 | } |
311 | ||
312 | /* Validate that the target is in a valid r/w GPU domain */ | |
b8f7ab17 | 313 | if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { |
ff240199 | 314 | DRM_DEBUG("reloc with multiple write domains: " |
54cf91dc CW |
315 | "obj %p target %d offset %d " |
316 | "read %08x write %08x", | |
317 | obj, reloc->target_handle, | |
318 | (int) reloc->offset, | |
319 | reloc->read_domains, | |
320 | reloc->write_domain); | |
67731b87 | 321 | return ret; |
54cf91dc | 322 | } |
4ca4a250 DV |
323 | if (unlikely((reloc->write_domain | reloc->read_domains) |
324 | & ~I915_GEM_GPU_DOMAINS)) { | |
ff240199 | 325 | DRM_DEBUG("reloc with read/write non-GPU domains: " |
54cf91dc CW |
326 | "obj %p target %d offset %d " |
327 | "read %08x write %08x", | |
328 | obj, reloc->target_handle, | |
329 | (int) reloc->offset, | |
330 | reloc->read_domains, | |
331 | reloc->write_domain); | |
67731b87 | 332 | return ret; |
54cf91dc | 333 | } |
b8f7ab17 CW |
334 | if (unlikely(reloc->write_domain && target_obj->pending_write_domain && |
335 | reloc->write_domain != target_obj->pending_write_domain)) { | |
ff240199 | 336 | DRM_DEBUG("Write domain conflict: " |
54cf91dc CW |
337 | "obj %p target %d offset %d " |
338 | "new %08x old %08x\n", | |
339 | obj, reloc->target_handle, | |
340 | (int) reloc->offset, | |
341 | reloc->write_domain, | |
342 | target_obj->pending_write_domain); | |
67731b87 | 343 | return ret; |
54cf91dc CW |
344 | } |
345 | ||
346 | target_obj->pending_read_domains |= reloc->read_domains; | |
347 | target_obj->pending_write_domain |= reloc->write_domain; | |
348 | ||
349 | /* If the relocation already has the right value in it, no | |
350 | * more work needs to be done. | |
351 | */ | |
352 | if (target_offset == reloc->presumed_offset) | |
67731b87 | 353 | return 0; |
54cf91dc CW |
354 | |
355 | /* Check that the relocation address is valid... */ | |
b8f7ab17 | 356 | if (unlikely(reloc->offset > obj->base.size - 4)) { |
ff240199 | 357 | DRM_DEBUG("Relocation beyond object bounds: " |
54cf91dc CW |
358 | "obj %p target %d offset %d size %d.\n", |
359 | obj, reloc->target_handle, | |
360 | (int) reloc->offset, | |
361 | (int) obj->base.size); | |
67731b87 | 362 | return ret; |
54cf91dc | 363 | } |
b8f7ab17 | 364 | if (unlikely(reloc->offset & 3)) { |
ff240199 | 365 | DRM_DEBUG("Relocation not 4-byte aligned: " |
54cf91dc CW |
366 | "obj %p target %d offset %d.\n", |
367 | obj, reloc->target_handle, | |
368 | (int) reloc->offset); | |
67731b87 | 369 | return ret; |
54cf91dc CW |
370 | } |
371 | ||
dabdfe02 CW |
372 | /* We can't wait for rendering with pagefaults disabled */ |
373 | if (obj->active && in_atomic()) | |
374 | return -EFAULT; | |
375 | ||
54cf91dc | 376 | reloc->delta += target_offset; |
dabdfe02 | 377 | if (use_cpu_reloc(obj)) { |
54cf91dc CW |
378 | uint32_t page_offset = reloc->offset & ~PAGE_MASK; |
379 | char *vaddr; | |
380 | ||
dabdfe02 CW |
381 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
382 | if (ret) | |
383 | return ret; | |
384 | ||
54cf91dc CW |
385 | vaddr = kmap_atomic(obj->pages[reloc->offset >> PAGE_SHIFT]); |
386 | *(uint32_t *)(vaddr + page_offset) = reloc->delta; | |
387 | kunmap_atomic(vaddr); | |
388 | } else { | |
389 | struct drm_i915_private *dev_priv = dev->dev_private; | |
390 | uint32_t __iomem *reloc_entry; | |
391 | void __iomem *reloc_page; | |
392 | ||
7b09638f CW |
393 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
394 | if (ret) | |
395 | return ret; | |
396 | ||
397 | ret = i915_gem_object_put_fence(obj); | |
54cf91dc | 398 | if (ret) |
67731b87 | 399 | return ret; |
54cf91dc CW |
400 | |
401 | /* Map the page containing the relocation we're going to perform. */ | |
402 | reloc->offset += obj->gtt_offset; | |
403 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, | |
404 | reloc->offset & PAGE_MASK); | |
405 | reloc_entry = (uint32_t __iomem *) | |
406 | (reloc_page + (reloc->offset & ~PAGE_MASK)); | |
407 | iowrite32(reloc->delta, reloc_entry); | |
408 | io_mapping_unmap_atomic(reloc_page); | |
409 | } | |
410 | ||
411 | /* and update the user's relocation entry */ | |
412 | reloc->presumed_offset = target_offset; | |
413 | ||
67731b87 | 414 | return 0; |
54cf91dc CW |
415 | } |
416 | ||
417 | static int | |
418 | i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj, | |
6fe4f140 | 419 | struct eb_objects *eb) |
54cf91dc | 420 | { |
1d83f442 CW |
421 | #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) |
422 | struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)]; | |
54cf91dc | 423 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
6fe4f140 | 424 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
1d83f442 | 425 | int remain, ret; |
54cf91dc CW |
426 | |
427 | user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr; | |
54cf91dc | 428 | |
1d83f442 CW |
429 | remain = entry->relocation_count; |
430 | while (remain) { | |
431 | struct drm_i915_gem_relocation_entry *r = stack_reloc; | |
432 | int count = remain; | |
433 | if (count > ARRAY_SIZE(stack_reloc)) | |
434 | count = ARRAY_SIZE(stack_reloc); | |
435 | remain -= count; | |
436 | ||
437 | if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0]))) | |
54cf91dc CW |
438 | return -EFAULT; |
439 | ||
1d83f442 CW |
440 | do { |
441 | u64 offset = r->presumed_offset; | |
54cf91dc | 442 | |
1d83f442 CW |
443 | ret = i915_gem_execbuffer_relocate_entry(obj, eb, r); |
444 | if (ret) | |
445 | return ret; | |
446 | ||
447 | if (r->presumed_offset != offset && | |
448 | __copy_to_user_inatomic(&user_relocs->presumed_offset, | |
449 | &r->presumed_offset, | |
450 | sizeof(r->presumed_offset))) { | |
451 | return -EFAULT; | |
452 | } | |
453 | ||
454 | user_relocs++; | |
455 | r++; | |
456 | } while (--count); | |
54cf91dc CW |
457 | } |
458 | ||
459 | return 0; | |
1d83f442 | 460 | #undef N_RELOC |
54cf91dc CW |
461 | } |
462 | ||
463 | static int | |
464 | i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj, | |
67731b87 | 465 | struct eb_objects *eb, |
54cf91dc CW |
466 | struct drm_i915_gem_relocation_entry *relocs) |
467 | { | |
6fe4f140 | 468 | const struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
54cf91dc CW |
469 | int i, ret; |
470 | ||
471 | for (i = 0; i < entry->relocation_count; i++) { | |
6fe4f140 | 472 | ret = i915_gem_execbuffer_relocate_entry(obj, eb, &relocs[i]); |
54cf91dc CW |
473 | if (ret) |
474 | return ret; | |
475 | } | |
476 | ||
477 | return 0; | |
478 | } | |
479 | ||
480 | static int | |
481 | i915_gem_execbuffer_relocate(struct drm_device *dev, | |
67731b87 | 482 | struct eb_objects *eb, |
6fe4f140 | 483 | struct list_head *objects) |
54cf91dc | 484 | { |
432e58ed | 485 | struct drm_i915_gem_object *obj; |
d4aeee77 CW |
486 | int ret = 0; |
487 | ||
488 | /* This is the fast path and we cannot handle a pagefault whilst | |
489 | * holding the struct mutex lest the user pass in the relocations | |
490 | * contained within a mmaped bo. For in such a case we, the page | |
491 | * fault handler would call i915_gem_fault() and we would try to | |
492 | * acquire the struct mutex again. Obviously this is bad and so | |
493 | * lockdep complains vehemently. | |
494 | */ | |
495 | pagefault_disable(); | |
432e58ed | 496 | list_for_each_entry(obj, objects, exec_list) { |
6fe4f140 | 497 | ret = i915_gem_execbuffer_relocate_object(obj, eb); |
54cf91dc | 498 | if (ret) |
d4aeee77 | 499 | break; |
54cf91dc | 500 | } |
d4aeee77 | 501 | pagefault_enable(); |
54cf91dc | 502 | |
d4aeee77 | 503 | return ret; |
54cf91dc CW |
504 | } |
505 | ||
1690e1eb CW |
506 | #define __EXEC_OBJECT_HAS_FENCE (1<<31) |
507 | ||
dabdfe02 CW |
508 | static int |
509 | need_reloc_mappable(struct drm_i915_gem_object *obj) | |
510 | { | |
511 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; | |
512 | return entry->relocation_count && !use_cpu_reloc(obj); | |
513 | } | |
514 | ||
1690e1eb CW |
515 | static int |
516 | pin_and_fence_object(struct drm_i915_gem_object *obj, | |
517 | struct intel_ring_buffer *ring) | |
518 | { | |
519 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; | |
520 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; | |
521 | bool need_fence, need_mappable; | |
522 | int ret; | |
523 | ||
524 | need_fence = | |
525 | has_fenced_gpu_access && | |
526 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
527 | obj->tiling_mode != I915_TILING_NONE; | |
dabdfe02 | 528 | need_mappable = need_fence || need_reloc_mappable(obj); |
1690e1eb CW |
529 | |
530 | ret = i915_gem_object_pin(obj, entry->alignment, need_mappable); | |
531 | if (ret) | |
532 | return ret; | |
533 | ||
534 | if (has_fenced_gpu_access) { | |
535 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { | |
06d98131 | 536 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
537 | if (ret) |
538 | goto err_unpin; | |
1690e1eb | 539 | |
9a5a53b3 | 540 | if (i915_gem_object_pin_fence(obj)) |
1690e1eb | 541 | entry->flags |= __EXEC_OBJECT_HAS_FENCE; |
9a5a53b3 | 542 | |
7dd49065 | 543 | obj->pending_fenced_gpu_access = true; |
1690e1eb | 544 | } |
1690e1eb CW |
545 | } |
546 | ||
547 | entry->offset = obj->gtt_offset; | |
548 | return 0; | |
549 | ||
550 | err_unpin: | |
551 | i915_gem_object_unpin(obj); | |
552 | return ret; | |
553 | } | |
554 | ||
54cf91dc | 555 | static int |
d9e86c0e | 556 | i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring, |
54cf91dc | 557 | struct drm_file *file, |
6fe4f140 | 558 | struct list_head *objects) |
54cf91dc | 559 | { |
7bddb01f | 560 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
432e58ed | 561 | struct drm_i915_gem_object *obj; |
432e58ed | 562 | int ret, retry; |
9b3826bf | 563 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; |
6fe4f140 CW |
564 | struct list_head ordered_objects; |
565 | ||
566 | INIT_LIST_HEAD(&ordered_objects); | |
567 | while (!list_empty(objects)) { | |
568 | struct drm_i915_gem_exec_object2 *entry; | |
569 | bool need_fence, need_mappable; | |
570 | ||
571 | obj = list_first_entry(objects, | |
572 | struct drm_i915_gem_object, | |
573 | exec_list); | |
574 | entry = obj->exec_entry; | |
575 | ||
576 | need_fence = | |
577 | has_fenced_gpu_access && | |
578 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
579 | obj->tiling_mode != I915_TILING_NONE; | |
dabdfe02 | 580 | need_mappable = need_fence || need_reloc_mappable(obj); |
6fe4f140 CW |
581 | |
582 | if (need_mappable) | |
583 | list_move(&obj->exec_list, &ordered_objects); | |
584 | else | |
585 | list_move_tail(&obj->exec_list, &ordered_objects); | |
595dad76 CW |
586 | |
587 | obj->base.pending_read_domains = 0; | |
588 | obj->base.pending_write_domain = 0; | |
6fe4f140 CW |
589 | } |
590 | list_splice(&ordered_objects, objects); | |
54cf91dc CW |
591 | |
592 | /* Attempt to pin all of the buffers into the GTT. | |
593 | * This is done in 3 phases: | |
594 | * | |
595 | * 1a. Unbind all objects that do not match the GTT constraints for | |
596 | * the execbuffer (fenceable, mappable, alignment etc). | |
597 | * 1b. Increment pin count for already bound objects. | |
598 | * 2. Bind new objects. | |
599 | * 3. Decrement pin count. | |
600 | * | |
601 | * This avoid unnecessary unbinding of later objects in order to makr | |
602 | * room for the earlier objects *unless* we need to defragment. | |
603 | */ | |
604 | retry = 0; | |
605 | do { | |
606 | ret = 0; | |
607 | ||
608 | /* Unbind any ill-fitting objects or pin. */ | |
432e58ed | 609 | list_for_each_entry(obj, objects, exec_list) { |
6fe4f140 | 610 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
54cf91dc | 611 | bool need_fence, need_mappable; |
1690e1eb | 612 | |
6fe4f140 | 613 | if (!obj->gtt_space) |
54cf91dc CW |
614 | continue; |
615 | ||
616 | need_fence = | |
9b3826bf | 617 | has_fenced_gpu_access && |
54cf91dc CW |
618 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
619 | obj->tiling_mode != I915_TILING_NONE; | |
dabdfe02 | 620 | need_mappable = need_fence || need_reloc_mappable(obj); |
54cf91dc CW |
621 | |
622 | if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) || | |
623 | (need_mappable && !obj->map_and_fenceable)) | |
624 | ret = i915_gem_object_unbind(obj); | |
625 | else | |
1690e1eb | 626 | ret = pin_and_fence_object(obj, ring); |
432e58ed | 627 | if (ret) |
54cf91dc | 628 | goto err; |
54cf91dc CW |
629 | } |
630 | ||
631 | /* Bind fresh objects */ | |
432e58ed | 632 | list_for_each_entry(obj, objects, exec_list) { |
1690e1eb CW |
633 | if (obj->gtt_space) |
634 | continue; | |
54cf91dc | 635 | |
1690e1eb CW |
636 | ret = pin_and_fence_object(obj, ring); |
637 | if (ret) { | |
638 | int ret_ignore; | |
639 | ||
640 | /* This can potentially raise a harmless | |
641 | * -EINVAL if we failed to bind in the above | |
642 | * call. It cannot raise -EINTR since we know | |
643 | * that the bo is freshly bound and so will | |
644 | * not need to be flushed or waited upon. | |
645 | */ | |
646 | ret_ignore = i915_gem_object_unbind(obj); | |
647 | (void)ret_ignore; | |
648 | WARN_ON(obj->gtt_space); | |
649 | break; | |
54cf91dc | 650 | } |
54cf91dc CW |
651 | } |
652 | ||
432e58ed CW |
653 | /* Decrement pin count for bound objects */ |
654 | list_for_each_entry(obj, objects, exec_list) { | |
1690e1eb CW |
655 | struct drm_i915_gem_exec_object2 *entry; |
656 | ||
657 | if (!obj->gtt_space) | |
658 | continue; | |
659 | ||
660 | entry = obj->exec_entry; | |
661 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) { | |
662 | i915_gem_object_unpin_fence(obj); | |
663 | entry->flags &= ~__EXEC_OBJECT_HAS_FENCE; | |
664 | } | |
665 | ||
666 | i915_gem_object_unpin(obj); | |
7bddb01f DV |
667 | |
668 | /* ... and ensure ppgtt mapping exist if needed. */ | |
669 | if (dev_priv->mm.aliasing_ppgtt && !obj->has_aliasing_ppgtt_mapping) { | |
670 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
671 | obj, obj->cache_level); | |
672 | ||
673 | obj->has_aliasing_ppgtt_mapping = 1; | |
674 | } | |
54cf91dc CW |
675 | } |
676 | ||
677 | if (ret != -ENOSPC || retry > 1) | |
678 | return ret; | |
679 | ||
680 | /* First attempt, just clear anything that is purgeable. | |
681 | * Second attempt, clear the entire GTT. | |
682 | */ | |
d9e86c0e | 683 | ret = i915_gem_evict_everything(ring->dev, retry == 0); |
54cf91dc CW |
684 | if (ret) |
685 | return ret; | |
686 | ||
687 | retry++; | |
688 | } while (1); | |
432e58ed CW |
689 | |
690 | err: | |
1690e1eb CW |
691 | list_for_each_entry_continue_reverse(obj, objects, exec_list) { |
692 | struct drm_i915_gem_exec_object2 *entry; | |
693 | ||
694 | if (!obj->gtt_space) | |
695 | continue; | |
696 | ||
697 | entry = obj->exec_entry; | |
698 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) { | |
699 | i915_gem_object_unpin_fence(obj); | |
700 | entry->flags &= ~__EXEC_OBJECT_HAS_FENCE; | |
701 | } | |
432e58ed | 702 | |
1690e1eb | 703 | i915_gem_object_unpin(obj); |
432e58ed CW |
704 | } |
705 | ||
706 | return ret; | |
54cf91dc CW |
707 | } |
708 | ||
709 | static int | |
710 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, | |
711 | struct drm_file *file, | |
d9e86c0e | 712 | struct intel_ring_buffer *ring, |
432e58ed | 713 | struct list_head *objects, |
67731b87 | 714 | struct eb_objects *eb, |
432e58ed | 715 | struct drm_i915_gem_exec_object2 *exec, |
54cf91dc CW |
716 | int count) |
717 | { | |
718 | struct drm_i915_gem_relocation_entry *reloc; | |
432e58ed | 719 | struct drm_i915_gem_object *obj; |
dd6864a4 | 720 | int *reloc_offset; |
54cf91dc CW |
721 | int i, total, ret; |
722 | ||
67731b87 | 723 | /* We may process another execbuffer during the unlock... */ |
36cf1742 | 724 | while (!list_empty(objects)) { |
67731b87 CW |
725 | obj = list_first_entry(objects, |
726 | struct drm_i915_gem_object, | |
727 | exec_list); | |
728 | list_del_init(&obj->exec_list); | |
729 | drm_gem_object_unreference(&obj->base); | |
730 | } | |
731 | ||
54cf91dc CW |
732 | mutex_unlock(&dev->struct_mutex); |
733 | ||
734 | total = 0; | |
735 | for (i = 0; i < count; i++) | |
432e58ed | 736 | total += exec[i].relocation_count; |
54cf91dc | 737 | |
dd6864a4 | 738 | reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset)); |
54cf91dc | 739 | reloc = drm_malloc_ab(total, sizeof(*reloc)); |
dd6864a4 CW |
740 | if (reloc == NULL || reloc_offset == NULL) { |
741 | drm_free_large(reloc); | |
742 | drm_free_large(reloc_offset); | |
54cf91dc CW |
743 | mutex_lock(&dev->struct_mutex); |
744 | return -ENOMEM; | |
745 | } | |
746 | ||
747 | total = 0; | |
748 | for (i = 0; i < count; i++) { | |
749 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
750 | ||
432e58ed | 751 | user_relocs = (void __user *)(uintptr_t)exec[i].relocs_ptr; |
54cf91dc CW |
752 | |
753 | if (copy_from_user(reloc+total, user_relocs, | |
432e58ed | 754 | exec[i].relocation_count * sizeof(*reloc))) { |
54cf91dc CW |
755 | ret = -EFAULT; |
756 | mutex_lock(&dev->struct_mutex); | |
757 | goto err; | |
758 | } | |
759 | ||
dd6864a4 | 760 | reloc_offset[i] = total; |
432e58ed | 761 | total += exec[i].relocation_count; |
54cf91dc CW |
762 | } |
763 | ||
764 | ret = i915_mutex_lock_interruptible(dev); | |
765 | if (ret) { | |
766 | mutex_lock(&dev->struct_mutex); | |
767 | goto err; | |
768 | } | |
769 | ||
67731b87 | 770 | /* reacquire the objects */ |
67731b87 CW |
771 | eb_reset(eb); |
772 | for (i = 0; i < count; i++) { | |
67731b87 CW |
773 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, |
774 | exec[i].handle)); | |
c8725226 | 775 | if (&obj->base == NULL) { |
ff240199 | 776 | DRM_DEBUG("Invalid object handle %d at index %d\n", |
67731b87 CW |
777 | exec[i].handle, i); |
778 | ret = -ENOENT; | |
779 | goto err; | |
780 | } | |
781 | ||
782 | list_add_tail(&obj->exec_list, objects); | |
783 | obj->exec_handle = exec[i].handle; | |
6fe4f140 | 784 | obj->exec_entry = &exec[i]; |
67731b87 CW |
785 | eb_add_object(eb, obj); |
786 | } | |
787 | ||
6fe4f140 | 788 | ret = i915_gem_execbuffer_reserve(ring, file, objects); |
54cf91dc CW |
789 | if (ret) |
790 | goto err; | |
791 | ||
432e58ed | 792 | list_for_each_entry(obj, objects, exec_list) { |
dd6864a4 | 793 | int offset = obj->exec_entry - exec; |
67731b87 | 794 | ret = i915_gem_execbuffer_relocate_object_slow(obj, eb, |
dd6864a4 | 795 | reloc + reloc_offset[offset]); |
54cf91dc CW |
796 | if (ret) |
797 | goto err; | |
54cf91dc CW |
798 | } |
799 | ||
800 | /* Leave the user relocations as are, this is the painfully slow path, | |
801 | * and we want to avoid the complication of dropping the lock whilst | |
802 | * having buffers reserved in the aperture and so causing spurious | |
803 | * ENOSPC for random operations. | |
804 | */ | |
805 | ||
806 | err: | |
807 | drm_free_large(reloc); | |
dd6864a4 | 808 | drm_free_large(reloc_offset); |
54cf91dc CW |
809 | return ret; |
810 | } | |
811 | ||
cc889e0f | 812 | static void |
54cf91dc CW |
813 | i915_gem_execbuffer_flush(struct drm_device *dev, |
814 | uint32_t invalidate_domains, | |
cc889e0f | 815 | uint32_t flush_domains) |
54cf91dc | 816 | { |
54cf91dc CW |
817 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
818 | intel_gtt_chipset_flush(); | |
819 | ||
63256ec5 CW |
820 | if (flush_domains & I915_GEM_DOMAIN_GTT) |
821 | wmb(); | |
54cf91dc CW |
822 | } |
823 | ||
c59a333f CW |
824 | static int |
825 | i915_gem_execbuffer_wait_for_flips(struct intel_ring_buffer *ring, u32 flips) | |
826 | { | |
827 | u32 plane, flip_mask; | |
828 | int ret; | |
829 | ||
830 | /* Check for any pending flips. As we only maintain a flip queue depth | |
831 | * of 1, we can simply insert a WAIT for the next display flip prior | |
832 | * to executing the batch and avoid stalling the CPU. | |
833 | */ | |
834 | ||
835 | for (plane = 0; flips >> plane; plane++) { | |
836 | if (((flips >> plane) & 1) == 0) | |
837 | continue; | |
838 | ||
839 | if (plane) | |
840 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
841 | else | |
842 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
843 | ||
844 | ret = intel_ring_begin(ring, 2); | |
845 | if (ret) | |
846 | return ret; | |
847 | ||
848 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); | |
849 | intel_ring_emit(ring, MI_NOOP); | |
850 | intel_ring_advance(ring); | |
851 | } | |
852 | ||
853 | return 0; | |
854 | } | |
855 | ||
856 | ||
54cf91dc | 857 | static int |
432e58ed CW |
858 | i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring, |
859 | struct list_head *objects) | |
54cf91dc | 860 | { |
432e58ed | 861 | struct drm_i915_gem_object *obj; |
54cf91dc | 862 | struct change_domains cd; |
432e58ed | 863 | int ret; |
54cf91dc | 864 | |
c59a333f | 865 | memset(&cd, 0, sizeof(cd)); |
432e58ed CW |
866 | list_for_each_entry(obj, objects, exec_list) |
867 | i915_gem_object_set_to_gpu_domain(obj, ring, &cd); | |
54cf91dc CW |
868 | |
869 | if (cd.invalidate_domains | cd.flush_domains) { | |
cc889e0f DV |
870 | i915_gem_execbuffer_flush(ring->dev, |
871 | cd.invalidate_domains, | |
872 | cd.flush_domains); | |
54cf91dc CW |
873 | } |
874 | ||
c59a333f CW |
875 | if (cd.flips) { |
876 | ret = i915_gem_execbuffer_wait_for_flips(ring, cd.flips); | |
877 | if (ret) | |
878 | return ret; | |
879 | } | |
880 | ||
432e58ed | 881 | list_for_each_entry(obj, objects, exec_list) { |
2911a35b | 882 | ret = i915_gem_object_sync(obj, ring); |
1ec14ad3 CW |
883 | if (ret) |
884 | return ret; | |
54cf91dc CW |
885 | } |
886 | ||
09cf7c9a CW |
887 | /* Unconditionally invalidate gpu caches and ensure that we do flush |
888 | * any residual writes from the previous batch. | |
889 | */ | |
890 | ret = i915_gem_flush_ring(ring, | |
891 | I915_GEM_GPU_DOMAINS, | |
892 | ring->gpu_caches_dirty ? I915_GEM_GPU_DOMAINS : 0); | |
cc889e0f DV |
893 | if (ret) |
894 | return ret; | |
895 | ||
09cf7c9a | 896 | ring->gpu_caches_dirty = false; |
54cf91dc CW |
897 | return 0; |
898 | } | |
899 | ||
432e58ed CW |
900 | static bool |
901 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) | |
54cf91dc | 902 | { |
432e58ed | 903 | return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0; |
54cf91dc CW |
904 | } |
905 | ||
906 | static int | |
907 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, | |
908 | int count) | |
909 | { | |
910 | int i; | |
911 | ||
912 | for (i = 0; i < count; i++) { | |
913 | char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr; | |
914 | int length; /* limited by fault_in_pages_readable() */ | |
915 | ||
916 | /* First check for malicious input causing overflow */ | |
917 | if (exec[i].relocation_count > | |
918 | INT_MAX / sizeof(struct drm_i915_gem_relocation_entry)) | |
919 | return -EINVAL; | |
920 | ||
921 | length = exec[i].relocation_count * | |
922 | sizeof(struct drm_i915_gem_relocation_entry); | |
923 | if (!access_ok(VERIFY_READ, ptr, length)) | |
924 | return -EFAULT; | |
925 | ||
926 | /* we may also need to update the presumed offsets */ | |
927 | if (!access_ok(VERIFY_WRITE, ptr, length)) | |
928 | return -EFAULT; | |
929 | ||
f56f821f | 930 | if (fault_in_multipages_readable(ptr, length)) |
54cf91dc CW |
931 | return -EFAULT; |
932 | } | |
933 | ||
934 | return 0; | |
935 | } | |
936 | ||
432e58ed CW |
937 | static void |
938 | i915_gem_execbuffer_move_to_active(struct list_head *objects, | |
1ec14ad3 CW |
939 | struct intel_ring_buffer *ring, |
940 | u32 seqno) | |
432e58ed CW |
941 | { |
942 | struct drm_i915_gem_object *obj; | |
943 | ||
944 | list_for_each_entry(obj, objects, exec_list) { | |
db53a302 CW |
945 | u32 old_read = obj->base.read_domains; |
946 | u32 old_write = obj->base.write_domain; | |
947 | ||
948 | ||
432e58ed CW |
949 | obj->base.read_domains = obj->base.pending_read_domains; |
950 | obj->base.write_domain = obj->base.pending_write_domain; | |
951 | obj->fenced_gpu_access = obj->pending_fenced_gpu_access; | |
952 | ||
1ec14ad3 | 953 | i915_gem_object_move_to_active(obj, ring, seqno); |
432e58ed CW |
954 | if (obj->base.write_domain) { |
955 | obj->dirty = 1; | |
87ca9c8a | 956 | obj->pending_gpu_write = true; |
432e58ed CW |
957 | list_move_tail(&obj->gpu_write_list, |
958 | &ring->gpu_write_list); | |
acb87dfb CW |
959 | if (obj->pin_count) /* check for potential scanout */ |
960 | intel_mark_busy(ring->dev, obj); | |
432e58ed CW |
961 | } |
962 | ||
db53a302 | 963 | trace_i915_gem_object_change_domain(obj, old_read, old_write); |
432e58ed | 964 | } |
acb87dfb CW |
965 | |
966 | intel_mark_busy(ring->dev, NULL); | |
432e58ed CW |
967 | } |
968 | ||
54cf91dc CW |
969 | static void |
970 | i915_gem_execbuffer_retire_commands(struct drm_device *dev, | |
432e58ed | 971 | struct drm_file *file, |
54cf91dc CW |
972 | struct intel_ring_buffer *ring) |
973 | { | |
432e58ed | 974 | struct drm_i915_gem_request *request; |
54cf91dc | 975 | |
cc889e0f DV |
976 | /* Unconditionally force add_request to emit a full flush. */ |
977 | ring->gpu_caches_dirty = true; | |
54cf91dc | 978 | |
432e58ed CW |
979 | /* Add a breadcrumb for the completion of the batch buffer */ |
980 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
db53a302 | 981 | if (request == NULL || i915_add_request(ring, file, request)) { |
432e58ed CW |
982 | kfree(request); |
983 | } | |
984 | } | |
54cf91dc | 985 | |
ae662d31 EA |
986 | static int |
987 | i915_reset_gen7_sol_offsets(struct drm_device *dev, | |
988 | struct intel_ring_buffer *ring) | |
989 | { | |
990 | drm_i915_private_t *dev_priv = dev->dev_private; | |
991 | int ret, i; | |
992 | ||
993 | if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) | |
994 | return 0; | |
995 | ||
996 | ret = intel_ring_begin(ring, 4 * 3); | |
997 | if (ret) | |
998 | return ret; | |
999 | ||
1000 | for (i = 0; i < 4; i++) { | |
1001 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
1002 | intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i)); | |
1003 | intel_ring_emit(ring, 0); | |
1004 | } | |
1005 | ||
1006 | intel_ring_advance(ring); | |
1007 | ||
1008 | return 0; | |
1009 | } | |
1010 | ||
54cf91dc CW |
1011 | static int |
1012 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, | |
1013 | struct drm_file *file, | |
1014 | struct drm_i915_gem_execbuffer2 *args, | |
432e58ed | 1015 | struct drm_i915_gem_exec_object2 *exec) |
54cf91dc CW |
1016 | { |
1017 | drm_i915_private_t *dev_priv = dev->dev_private; | |
432e58ed | 1018 | struct list_head objects; |
67731b87 | 1019 | struct eb_objects *eb; |
54cf91dc CW |
1020 | struct drm_i915_gem_object *batch_obj; |
1021 | struct drm_clip_rect *cliprects = NULL; | |
54cf91dc | 1022 | struct intel_ring_buffer *ring; |
6e0a69db | 1023 | u32 ctx_id = i915_execbuffer2_get_context_id(*args); |
c4e7a414 | 1024 | u32 exec_start, exec_len; |
1ec14ad3 | 1025 | u32 seqno; |
84f9f938 | 1026 | u32 mask; |
72bfa19c | 1027 | int ret, mode, i; |
54cf91dc | 1028 | |
432e58ed | 1029 | if (!i915_gem_check_execbuffer(args)) { |
ff240199 | 1030 | DRM_DEBUG("execbuf with invalid offset/length\n"); |
432e58ed CW |
1031 | return -EINVAL; |
1032 | } | |
1033 | ||
1034 | ret = validate_exec_list(exec, args->buffer_count); | |
54cf91dc CW |
1035 | if (ret) |
1036 | return ret; | |
1037 | ||
54cf91dc CW |
1038 | switch (args->flags & I915_EXEC_RING_MASK) { |
1039 | case I915_EXEC_DEFAULT: | |
1040 | case I915_EXEC_RENDER: | |
1ec14ad3 | 1041 | ring = &dev_priv->ring[RCS]; |
54cf91dc CW |
1042 | break; |
1043 | case I915_EXEC_BSD: | |
1ec14ad3 | 1044 | ring = &dev_priv->ring[VCS]; |
6e0a69db BW |
1045 | if (ctx_id != 0) { |
1046 | DRM_DEBUG("Ring %s doesn't support contexts\n", | |
1047 | ring->name); | |
1048 | return -EPERM; | |
1049 | } | |
54cf91dc CW |
1050 | break; |
1051 | case I915_EXEC_BLT: | |
1ec14ad3 | 1052 | ring = &dev_priv->ring[BCS]; |
6e0a69db BW |
1053 | if (ctx_id != 0) { |
1054 | DRM_DEBUG("Ring %s doesn't support contexts\n", | |
1055 | ring->name); | |
1056 | return -EPERM; | |
1057 | } | |
54cf91dc CW |
1058 | break; |
1059 | default: | |
ff240199 | 1060 | DRM_DEBUG("execbuf with unknown ring: %d\n", |
54cf91dc CW |
1061 | (int)(args->flags & I915_EXEC_RING_MASK)); |
1062 | return -EINVAL; | |
1063 | } | |
a15817cf CW |
1064 | if (!intel_ring_initialized(ring)) { |
1065 | DRM_DEBUG("execbuf with invalid ring: %d\n", | |
1066 | (int)(args->flags & I915_EXEC_RING_MASK)); | |
1067 | return -EINVAL; | |
1068 | } | |
54cf91dc | 1069 | |
72bfa19c | 1070 | mode = args->flags & I915_EXEC_CONSTANTS_MASK; |
84f9f938 | 1071 | mask = I915_EXEC_CONSTANTS_MASK; |
72bfa19c CW |
1072 | switch (mode) { |
1073 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
1074 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
1075 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
1076 | if (ring == &dev_priv->ring[RCS] && | |
1077 | mode != dev_priv->relative_constants_mode) { | |
1078 | if (INTEL_INFO(dev)->gen < 4) | |
1079 | return -EINVAL; | |
1080 | ||
1081 | if (INTEL_INFO(dev)->gen > 5 && | |
1082 | mode == I915_EXEC_CONSTANTS_REL_SURFACE) | |
1083 | return -EINVAL; | |
84f9f938 BW |
1084 | |
1085 | /* The HW changed the meaning on this bit on gen6 */ | |
1086 | if (INTEL_INFO(dev)->gen >= 6) | |
1087 | mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
72bfa19c CW |
1088 | } |
1089 | break; | |
1090 | default: | |
ff240199 | 1091 | DRM_DEBUG("execbuf with unknown constants: %d\n", mode); |
72bfa19c CW |
1092 | return -EINVAL; |
1093 | } | |
1094 | ||
54cf91dc | 1095 | if (args->buffer_count < 1) { |
ff240199 | 1096 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1097 | return -EINVAL; |
1098 | } | |
54cf91dc CW |
1099 | |
1100 | if (args->num_cliprects != 0) { | |
1ec14ad3 | 1101 | if (ring != &dev_priv->ring[RCS]) { |
ff240199 | 1102 | DRM_DEBUG("clip rectangles are only valid with the render ring\n"); |
c4e7a414 CW |
1103 | return -EINVAL; |
1104 | } | |
1105 | ||
6ebebc92 DV |
1106 | if (INTEL_INFO(dev)->gen >= 5) { |
1107 | DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); | |
1108 | return -EINVAL; | |
1109 | } | |
1110 | ||
44afb3a0 XW |
1111 | if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) { |
1112 | DRM_DEBUG("execbuf with %u cliprects\n", | |
1113 | args->num_cliprects); | |
1114 | return -EINVAL; | |
1115 | } | |
5e13a0c5 | 1116 | |
432e58ed | 1117 | cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects), |
54cf91dc CW |
1118 | GFP_KERNEL); |
1119 | if (cliprects == NULL) { | |
1120 | ret = -ENOMEM; | |
1121 | goto pre_mutex_err; | |
1122 | } | |
1123 | ||
432e58ed CW |
1124 | if (copy_from_user(cliprects, |
1125 | (struct drm_clip_rect __user *)(uintptr_t) | |
1126 | args->cliprects_ptr, | |
1127 | sizeof(*cliprects)*args->num_cliprects)) { | |
54cf91dc CW |
1128 | ret = -EFAULT; |
1129 | goto pre_mutex_err; | |
1130 | } | |
1131 | } | |
1132 | ||
54cf91dc CW |
1133 | ret = i915_mutex_lock_interruptible(dev); |
1134 | if (ret) | |
1135 | goto pre_mutex_err; | |
1136 | ||
1137 | if (dev_priv->mm.suspended) { | |
1138 | mutex_unlock(&dev->struct_mutex); | |
1139 | ret = -EBUSY; | |
1140 | goto pre_mutex_err; | |
1141 | } | |
1142 | ||
67731b87 CW |
1143 | eb = eb_create(args->buffer_count); |
1144 | if (eb == NULL) { | |
1145 | mutex_unlock(&dev->struct_mutex); | |
1146 | ret = -ENOMEM; | |
1147 | goto pre_mutex_err; | |
1148 | } | |
1149 | ||
54cf91dc | 1150 | /* Look up object handles */ |
432e58ed | 1151 | INIT_LIST_HEAD(&objects); |
54cf91dc CW |
1152 | for (i = 0; i < args->buffer_count; i++) { |
1153 | struct drm_i915_gem_object *obj; | |
1154 | ||
432e58ed CW |
1155 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, |
1156 | exec[i].handle)); | |
c8725226 | 1157 | if (&obj->base == NULL) { |
ff240199 | 1158 | DRM_DEBUG("Invalid object handle %d at index %d\n", |
432e58ed | 1159 | exec[i].handle, i); |
54cf91dc | 1160 | /* prevent error path from reading uninitialized data */ |
54cf91dc CW |
1161 | ret = -ENOENT; |
1162 | goto err; | |
1163 | } | |
54cf91dc | 1164 | |
432e58ed | 1165 | if (!list_empty(&obj->exec_list)) { |
ff240199 | 1166 | DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n", |
432e58ed | 1167 | obj, exec[i].handle, i); |
54cf91dc CW |
1168 | ret = -EINVAL; |
1169 | goto err; | |
1170 | } | |
432e58ed CW |
1171 | |
1172 | list_add_tail(&obj->exec_list, &objects); | |
67731b87 | 1173 | obj->exec_handle = exec[i].handle; |
6fe4f140 | 1174 | obj->exec_entry = &exec[i]; |
67731b87 | 1175 | eb_add_object(eb, obj); |
54cf91dc CW |
1176 | } |
1177 | ||
6fe4f140 CW |
1178 | /* take note of the batch buffer before we might reorder the lists */ |
1179 | batch_obj = list_entry(objects.prev, | |
1180 | struct drm_i915_gem_object, | |
1181 | exec_list); | |
1182 | ||
54cf91dc | 1183 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
6fe4f140 | 1184 | ret = i915_gem_execbuffer_reserve(ring, file, &objects); |
54cf91dc CW |
1185 | if (ret) |
1186 | goto err; | |
1187 | ||
1188 | /* The objects are in their final locations, apply the relocations. */ | |
6fe4f140 | 1189 | ret = i915_gem_execbuffer_relocate(dev, eb, &objects); |
54cf91dc CW |
1190 | if (ret) { |
1191 | if (ret == -EFAULT) { | |
d9e86c0e | 1192 | ret = i915_gem_execbuffer_relocate_slow(dev, file, ring, |
67731b87 CW |
1193 | &objects, eb, |
1194 | exec, | |
54cf91dc CW |
1195 | args->buffer_count); |
1196 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1197 | } | |
1198 | if (ret) | |
1199 | goto err; | |
1200 | } | |
1201 | ||
1202 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
54cf91dc | 1203 | if (batch_obj->base.pending_write_domain) { |
ff240199 | 1204 | DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); |
54cf91dc CW |
1205 | ret = -EINVAL; |
1206 | goto err; | |
1207 | } | |
1208 | batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
1209 | ||
432e58ed CW |
1210 | ret = i915_gem_execbuffer_move_to_gpu(ring, &objects); |
1211 | if (ret) | |
54cf91dc | 1212 | goto err; |
54cf91dc | 1213 | |
db53a302 | 1214 | seqno = i915_gem_next_request_seqno(ring); |
076e2c0e | 1215 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) { |
1ec14ad3 CW |
1216 | if (seqno < ring->sync_seqno[i]) { |
1217 | /* The GPU can not handle its semaphore value wrapping, | |
1218 | * so every billion or so execbuffers, we need to stall | |
1219 | * the GPU in order to reset the counters. | |
1220 | */ | |
b2da9fe5 | 1221 | ret = i915_gpu_idle(dev); |
1ec14ad3 CW |
1222 | if (ret) |
1223 | goto err; | |
b2da9fe5 | 1224 | i915_gem_retire_requests(dev); |
1ec14ad3 CW |
1225 | |
1226 | BUG_ON(ring->sync_seqno[i]); | |
1227 | } | |
1228 | } | |
1229 | ||
0da5cec1 EA |
1230 | ret = i915_switch_context(ring, file, ctx_id); |
1231 | if (ret) | |
1232 | goto err; | |
1233 | ||
e2971bda BW |
1234 | if (ring == &dev_priv->ring[RCS] && |
1235 | mode != dev_priv->relative_constants_mode) { | |
1236 | ret = intel_ring_begin(ring, 4); | |
1237 | if (ret) | |
1238 | goto err; | |
1239 | ||
1240 | intel_ring_emit(ring, MI_NOOP); | |
1241 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
1242 | intel_ring_emit(ring, INSTPM); | |
84f9f938 | 1243 | intel_ring_emit(ring, mask << 16 | mode); |
e2971bda BW |
1244 | intel_ring_advance(ring); |
1245 | ||
1246 | dev_priv->relative_constants_mode = mode; | |
1247 | } | |
1248 | ||
ae662d31 EA |
1249 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { |
1250 | ret = i915_reset_gen7_sol_offsets(dev, ring); | |
1251 | if (ret) | |
1252 | goto err; | |
1253 | } | |
1254 | ||
db53a302 CW |
1255 | trace_i915_gem_ring_dispatch(ring, seqno); |
1256 | ||
c4e7a414 CW |
1257 | exec_start = batch_obj->gtt_offset + args->batch_start_offset; |
1258 | exec_len = args->batch_len; | |
1259 | if (cliprects) { | |
1260 | for (i = 0; i < args->num_cliprects; i++) { | |
1261 | ret = i915_emit_box(dev, &cliprects[i], | |
1262 | args->DR1, args->DR4); | |
1263 | if (ret) | |
1264 | goto err; | |
1265 | ||
1266 | ret = ring->dispatch_execbuffer(ring, | |
1267 | exec_start, exec_len); | |
1268 | if (ret) | |
1269 | goto err; | |
1270 | } | |
1271 | } else { | |
1272 | ret = ring->dispatch_execbuffer(ring, exec_start, exec_len); | |
1273 | if (ret) | |
1274 | goto err; | |
1275 | } | |
54cf91dc | 1276 | |
1ec14ad3 | 1277 | i915_gem_execbuffer_move_to_active(&objects, ring, seqno); |
432e58ed | 1278 | i915_gem_execbuffer_retire_commands(dev, file, ring); |
54cf91dc CW |
1279 | |
1280 | err: | |
67731b87 | 1281 | eb_destroy(eb); |
432e58ed CW |
1282 | while (!list_empty(&objects)) { |
1283 | struct drm_i915_gem_object *obj; | |
1284 | ||
1285 | obj = list_first_entry(&objects, | |
1286 | struct drm_i915_gem_object, | |
1287 | exec_list); | |
1288 | list_del_init(&obj->exec_list); | |
1289 | drm_gem_object_unreference(&obj->base); | |
54cf91dc CW |
1290 | } |
1291 | ||
1292 | mutex_unlock(&dev->struct_mutex); | |
1293 | ||
1294 | pre_mutex_err: | |
54cf91dc | 1295 | kfree(cliprects); |
54cf91dc CW |
1296 | return ret; |
1297 | } | |
1298 | ||
1299 | /* | |
1300 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
1301 | * list array and passes it to the real function. | |
1302 | */ | |
1303 | int | |
1304 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1305 | struct drm_file *file) | |
1306 | { | |
1307 | struct drm_i915_gem_execbuffer *args = data; | |
1308 | struct drm_i915_gem_execbuffer2 exec2; | |
1309 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
1310 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1311 | int ret, i; | |
1312 | ||
54cf91dc | 1313 | if (args->buffer_count < 1) { |
ff240199 | 1314 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1315 | return -EINVAL; |
1316 | } | |
1317 | ||
1318 | /* Copy in the exec list from userland */ | |
1319 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
1320 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
1321 | if (exec_list == NULL || exec2_list == NULL) { | |
ff240199 | 1322 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1323 | args->buffer_count); |
1324 | drm_free_large(exec_list); | |
1325 | drm_free_large(exec2_list); | |
1326 | return -ENOMEM; | |
1327 | } | |
1328 | ret = copy_from_user(exec_list, | |
1329 | (struct drm_i915_relocation_entry __user *) | |
1330 | (uintptr_t) args->buffers_ptr, | |
1331 | sizeof(*exec_list) * args->buffer_count); | |
1332 | if (ret != 0) { | |
ff240199 | 1333 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1334 | args->buffer_count, ret); |
1335 | drm_free_large(exec_list); | |
1336 | drm_free_large(exec2_list); | |
1337 | return -EFAULT; | |
1338 | } | |
1339 | ||
1340 | for (i = 0; i < args->buffer_count; i++) { | |
1341 | exec2_list[i].handle = exec_list[i].handle; | |
1342 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
1343 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
1344 | exec2_list[i].alignment = exec_list[i].alignment; | |
1345 | exec2_list[i].offset = exec_list[i].offset; | |
1346 | if (INTEL_INFO(dev)->gen < 4) | |
1347 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; | |
1348 | else | |
1349 | exec2_list[i].flags = 0; | |
1350 | } | |
1351 | ||
1352 | exec2.buffers_ptr = args->buffers_ptr; | |
1353 | exec2.buffer_count = args->buffer_count; | |
1354 | exec2.batch_start_offset = args->batch_start_offset; | |
1355 | exec2.batch_len = args->batch_len; | |
1356 | exec2.DR1 = args->DR1; | |
1357 | exec2.DR4 = args->DR4; | |
1358 | exec2.num_cliprects = args->num_cliprects; | |
1359 | exec2.cliprects_ptr = args->cliprects_ptr; | |
1360 | exec2.flags = I915_EXEC_RENDER; | |
6e0a69db | 1361 | i915_execbuffer2_set_context_id(exec2, 0); |
54cf91dc CW |
1362 | |
1363 | ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list); | |
1364 | if (!ret) { | |
1365 | /* Copy the new buffer offsets back to the user's exec list. */ | |
1366 | for (i = 0; i < args->buffer_count; i++) | |
1367 | exec_list[i].offset = exec2_list[i].offset; | |
1368 | /* ... and back out to userspace */ | |
1369 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
1370 | (uintptr_t) args->buffers_ptr, | |
1371 | exec_list, | |
1372 | sizeof(*exec_list) * args->buffer_count); | |
1373 | if (ret) { | |
1374 | ret = -EFAULT; | |
ff240199 | 1375 | DRM_DEBUG("failed to copy %d exec entries " |
54cf91dc CW |
1376 | "back to user (%d)\n", |
1377 | args->buffer_count, ret); | |
1378 | } | |
1379 | } | |
1380 | ||
1381 | drm_free_large(exec_list); | |
1382 | drm_free_large(exec2_list); | |
1383 | return ret; | |
1384 | } | |
1385 | ||
1386 | int | |
1387 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
1388 | struct drm_file *file) | |
1389 | { | |
1390 | struct drm_i915_gem_execbuffer2 *args = data; | |
1391 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1392 | int ret; | |
1393 | ||
ed8cd3b2 XW |
1394 | if (args->buffer_count < 1 || |
1395 | args->buffer_count > UINT_MAX / sizeof(*exec2_list)) { | |
ff240199 | 1396 | DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1397 | return -EINVAL; |
1398 | } | |
1399 | ||
8408c282 CW |
1400 | exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count, |
1401 | GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY); | |
1402 | if (exec2_list == NULL) | |
1403 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), | |
1404 | args->buffer_count); | |
54cf91dc | 1405 | if (exec2_list == NULL) { |
ff240199 | 1406 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1407 | args->buffer_count); |
1408 | return -ENOMEM; | |
1409 | } | |
1410 | ret = copy_from_user(exec2_list, | |
1411 | (struct drm_i915_relocation_entry __user *) | |
1412 | (uintptr_t) args->buffers_ptr, | |
1413 | sizeof(*exec2_list) * args->buffer_count); | |
1414 | if (ret != 0) { | |
ff240199 | 1415 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1416 | args->buffer_count, ret); |
1417 | drm_free_large(exec2_list); | |
1418 | return -EFAULT; | |
1419 | } | |
1420 | ||
1421 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list); | |
1422 | if (!ret) { | |
1423 | /* Copy the new buffer offsets back to the user's exec list. */ | |
1424 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
1425 | (uintptr_t) args->buffers_ptr, | |
1426 | exec2_list, | |
1427 | sizeof(*exec2_list) * args->buffer_count); | |
1428 | if (ret) { | |
1429 | ret = -EFAULT; | |
ff240199 | 1430 | DRM_DEBUG("failed to copy %d exec entries " |
54cf91dc CW |
1431 | "back to user (%d)\n", |
1432 | args->buffer_count, ret); | |
1433 | } | |
1434 | } | |
1435 | ||
1436 | drm_free_large(exec2_list); | |
1437 | return ret; | |
1438 | } |