Commit | Line | Data |
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54cf91dc CW |
1 | /* |
2 | * Copyright © 2008,2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Chris Wilson <chris@chris-wilson.co.uk> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include "drmP.h" | |
30 | #include "drm.h" | |
31 | #include "i915_drm.h" | |
32 | #include "i915_drv.h" | |
33 | #include "i915_trace.h" | |
34 | #include "intel_drv.h" | |
f45b5557 | 35 | #include <linux/dma_remapping.h> |
54cf91dc | 36 | |
67731b87 CW |
37 | struct eb_objects { |
38 | int and; | |
39 | struct hlist_head buckets[0]; | |
40 | }; | |
41 | ||
42 | static struct eb_objects * | |
43 | eb_create(int size) | |
44 | { | |
45 | struct eb_objects *eb; | |
46 | int count = PAGE_SIZE / sizeof(struct hlist_head) / 2; | |
47 | while (count > size) | |
48 | count >>= 1; | |
49 | eb = kzalloc(count*sizeof(struct hlist_head) + | |
50 | sizeof(struct eb_objects), | |
51 | GFP_KERNEL); | |
52 | if (eb == NULL) | |
53 | return eb; | |
54 | ||
55 | eb->and = count - 1; | |
56 | return eb; | |
57 | } | |
58 | ||
59 | static void | |
60 | eb_reset(struct eb_objects *eb) | |
61 | { | |
62 | memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head)); | |
63 | } | |
64 | ||
65 | static void | |
66 | eb_add_object(struct eb_objects *eb, struct drm_i915_gem_object *obj) | |
67 | { | |
68 | hlist_add_head(&obj->exec_node, | |
69 | &eb->buckets[obj->exec_handle & eb->and]); | |
70 | } | |
71 | ||
72 | static struct drm_i915_gem_object * | |
73 | eb_get_object(struct eb_objects *eb, unsigned long handle) | |
74 | { | |
75 | struct hlist_head *head; | |
76 | struct hlist_node *node; | |
77 | struct drm_i915_gem_object *obj; | |
78 | ||
79 | head = &eb->buckets[handle & eb->and]; | |
80 | hlist_for_each(node, head) { | |
81 | obj = hlist_entry(node, struct drm_i915_gem_object, exec_node); | |
82 | if (obj->exec_handle == handle) | |
83 | return obj; | |
84 | } | |
85 | ||
86 | return NULL; | |
87 | } | |
88 | ||
89 | static void | |
90 | eb_destroy(struct eb_objects *eb) | |
91 | { | |
92 | kfree(eb); | |
93 | } | |
94 | ||
dabdfe02 CW |
95 | static inline int use_cpu_reloc(struct drm_i915_gem_object *obj) |
96 | { | |
97 | return (obj->base.write_domain == I915_GEM_DOMAIN_CPU || | |
98 | obj->cache_level != I915_CACHE_NONE); | |
99 | } | |
100 | ||
54cf91dc CW |
101 | static int |
102 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, | |
67731b87 | 103 | struct eb_objects *eb, |
54cf91dc CW |
104 | struct drm_i915_gem_relocation_entry *reloc) |
105 | { | |
106 | struct drm_device *dev = obj->base.dev; | |
107 | struct drm_gem_object *target_obj; | |
149c8407 | 108 | struct drm_i915_gem_object *target_i915_obj; |
54cf91dc CW |
109 | uint32_t target_offset; |
110 | int ret = -EINVAL; | |
111 | ||
67731b87 CW |
112 | /* we've already hold a reference to all valid objects */ |
113 | target_obj = &eb_get_object(eb, reloc->target_handle)->base; | |
114 | if (unlikely(target_obj == NULL)) | |
54cf91dc CW |
115 | return -ENOENT; |
116 | ||
149c8407 DV |
117 | target_i915_obj = to_intel_bo(target_obj); |
118 | target_offset = target_i915_obj->gtt_offset; | |
54cf91dc | 119 | |
54cf91dc CW |
120 | /* The target buffer should have appeared before us in the |
121 | * exec_object list, so it should have a GTT space bound by now. | |
122 | */ | |
b8f7ab17 | 123 | if (unlikely(target_offset == 0)) { |
ff240199 | 124 | DRM_DEBUG("No GTT space found for object %d\n", |
54cf91dc | 125 | reloc->target_handle); |
67731b87 | 126 | return ret; |
54cf91dc CW |
127 | } |
128 | ||
129 | /* Validate that the target is in a valid r/w GPU domain */ | |
b8f7ab17 | 130 | if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { |
ff240199 | 131 | DRM_DEBUG("reloc with multiple write domains: " |
54cf91dc CW |
132 | "obj %p target %d offset %d " |
133 | "read %08x write %08x", | |
134 | obj, reloc->target_handle, | |
135 | (int) reloc->offset, | |
136 | reloc->read_domains, | |
137 | reloc->write_domain); | |
67731b87 | 138 | return ret; |
54cf91dc | 139 | } |
4ca4a250 DV |
140 | if (unlikely((reloc->write_domain | reloc->read_domains) |
141 | & ~I915_GEM_GPU_DOMAINS)) { | |
ff240199 | 142 | DRM_DEBUG("reloc with read/write non-GPU domains: " |
54cf91dc CW |
143 | "obj %p target %d offset %d " |
144 | "read %08x write %08x", | |
145 | obj, reloc->target_handle, | |
146 | (int) reloc->offset, | |
147 | reloc->read_domains, | |
148 | reloc->write_domain); | |
67731b87 | 149 | return ret; |
54cf91dc | 150 | } |
b8f7ab17 CW |
151 | if (unlikely(reloc->write_domain && target_obj->pending_write_domain && |
152 | reloc->write_domain != target_obj->pending_write_domain)) { | |
ff240199 | 153 | DRM_DEBUG("Write domain conflict: " |
54cf91dc CW |
154 | "obj %p target %d offset %d " |
155 | "new %08x old %08x\n", | |
156 | obj, reloc->target_handle, | |
157 | (int) reloc->offset, | |
158 | reloc->write_domain, | |
159 | target_obj->pending_write_domain); | |
67731b87 | 160 | return ret; |
54cf91dc CW |
161 | } |
162 | ||
163 | target_obj->pending_read_domains |= reloc->read_domains; | |
164 | target_obj->pending_write_domain |= reloc->write_domain; | |
165 | ||
166 | /* If the relocation already has the right value in it, no | |
167 | * more work needs to be done. | |
168 | */ | |
169 | if (target_offset == reloc->presumed_offset) | |
67731b87 | 170 | return 0; |
54cf91dc CW |
171 | |
172 | /* Check that the relocation address is valid... */ | |
b8f7ab17 | 173 | if (unlikely(reloc->offset > obj->base.size - 4)) { |
ff240199 | 174 | DRM_DEBUG("Relocation beyond object bounds: " |
54cf91dc CW |
175 | "obj %p target %d offset %d size %d.\n", |
176 | obj, reloc->target_handle, | |
177 | (int) reloc->offset, | |
178 | (int) obj->base.size); | |
67731b87 | 179 | return ret; |
54cf91dc | 180 | } |
b8f7ab17 | 181 | if (unlikely(reloc->offset & 3)) { |
ff240199 | 182 | DRM_DEBUG("Relocation not 4-byte aligned: " |
54cf91dc CW |
183 | "obj %p target %d offset %d.\n", |
184 | obj, reloc->target_handle, | |
185 | (int) reloc->offset); | |
67731b87 | 186 | return ret; |
54cf91dc CW |
187 | } |
188 | ||
dabdfe02 CW |
189 | /* We can't wait for rendering with pagefaults disabled */ |
190 | if (obj->active && in_atomic()) | |
191 | return -EFAULT; | |
192 | ||
54cf91dc | 193 | reloc->delta += target_offset; |
dabdfe02 | 194 | if (use_cpu_reloc(obj)) { |
54cf91dc CW |
195 | uint32_t page_offset = reloc->offset & ~PAGE_MASK; |
196 | char *vaddr; | |
197 | ||
dabdfe02 CW |
198 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
199 | if (ret) | |
200 | return ret; | |
201 | ||
54cf91dc CW |
202 | vaddr = kmap_atomic(obj->pages[reloc->offset >> PAGE_SHIFT]); |
203 | *(uint32_t *)(vaddr + page_offset) = reloc->delta; | |
204 | kunmap_atomic(vaddr); | |
205 | } else { | |
206 | struct drm_i915_private *dev_priv = dev->dev_private; | |
207 | uint32_t __iomem *reloc_entry; | |
208 | void __iomem *reloc_page; | |
209 | ||
7b09638f CW |
210 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
211 | if (ret) | |
212 | return ret; | |
213 | ||
214 | ret = i915_gem_object_put_fence(obj); | |
54cf91dc | 215 | if (ret) |
67731b87 | 216 | return ret; |
54cf91dc CW |
217 | |
218 | /* Map the page containing the relocation we're going to perform. */ | |
219 | reloc->offset += obj->gtt_offset; | |
220 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, | |
221 | reloc->offset & PAGE_MASK); | |
222 | reloc_entry = (uint32_t __iomem *) | |
223 | (reloc_page + (reloc->offset & ~PAGE_MASK)); | |
224 | iowrite32(reloc->delta, reloc_entry); | |
225 | io_mapping_unmap_atomic(reloc_page); | |
226 | } | |
227 | ||
149c8407 DV |
228 | /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and |
229 | * pipe_control writes because the gpu doesn't properly redirect them | |
230 | * through the ppgtt for non_secure batchbuffers. */ | |
231 | if (unlikely(IS_GEN6(dev) && | |
232 | reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION && | |
233 | !target_i915_obj->has_global_gtt_mapping)) { | |
234 | i915_gem_gtt_bind_object(target_i915_obj, | |
235 | target_i915_obj->cache_level); | |
236 | } | |
237 | ||
54cf91dc CW |
238 | /* and update the user's relocation entry */ |
239 | reloc->presumed_offset = target_offset; | |
240 | ||
67731b87 | 241 | return 0; |
54cf91dc CW |
242 | } |
243 | ||
244 | static int | |
245 | i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj, | |
6fe4f140 | 246 | struct eb_objects *eb) |
54cf91dc | 247 | { |
1d83f442 CW |
248 | #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) |
249 | struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)]; | |
54cf91dc | 250 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
6fe4f140 | 251 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
1d83f442 | 252 | int remain, ret; |
54cf91dc CW |
253 | |
254 | user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr; | |
54cf91dc | 255 | |
1d83f442 CW |
256 | remain = entry->relocation_count; |
257 | while (remain) { | |
258 | struct drm_i915_gem_relocation_entry *r = stack_reloc; | |
259 | int count = remain; | |
260 | if (count > ARRAY_SIZE(stack_reloc)) | |
261 | count = ARRAY_SIZE(stack_reloc); | |
262 | remain -= count; | |
263 | ||
264 | if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0]))) | |
54cf91dc CW |
265 | return -EFAULT; |
266 | ||
1d83f442 CW |
267 | do { |
268 | u64 offset = r->presumed_offset; | |
54cf91dc | 269 | |
1d83f442 CW |
270 | ret = i915_gem_execbuffer_relocate_entry(obj, eb, r); |
271 | if (ret) | |
272 | return ret; | |
273 | ||
274 | if (r->presumed_offset != offset && | |
275 | __copy_to_user_inatomic(&user_relocs->presumed_offset, | |
276 | &r->presumed_offset, | |
277 | sizeof(r->presumed_offset))) { | |
278 | return -EFAULT; | |
279 | } | |
280 | ||
281 | user_relocs++; | |
282 | r++; | |
283 | } while (--count); | |
54cf91dc CW |
284 | } |
285 | ||
286 | return 0; | |
1d83f442 | 287 | #undef N_RELOC |
54cf91dc CW |
288 | } |
289 | ||
290 | static int | |
291 | i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj, | |
67731b87 | 292 | struct eb_objects *eb, |
54cf91dc CW |
293 | struct drm_i915_gem_relocation_entry *relocs) |
294 | { | |
6fe4f140 | 295 | const struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
54cf91dc CW |
296 | int i, ret; |
297 | ||
298 | for (i = 0; i < entry->relocation_count; i++) { | |
6fe4f140 | 299 | ret = i915_gem_execbuffer_relocate_entry(obj, eb, &relocs[i]); |
54cf91dc CW |
300 | if (ret) |
301 | return ret; | |
302 | } | |
303 | ||
304 | return 0; | |
305 | } | |
306 | ||
307 | static int | |
308 | i915_gem_execbuffer_relocate(struct drm_device *dev, | |
67731b87 | 309 | struct eb_objects *eb, |
6fe4f140 | 310 | struct list_head *objects) |
54cf91dc | 311 | { |
432e58ed | 312 | struct drm_i915_gem_object *obj; |
d4aeee77 CW |
313 | int ret = 0; |
314 | ||
315 | /* This is the fast path and we cannot handle a pagefault whilst | |
316 | * holding the struct mutex lest the user pass in the relocations | |
317 | * contained within a mmaped bo. For in such a case we, the page | |
318 | * fault handler would call i915_gem_fault() and we would try to | |
319 | * acquire the struct mutex again. Obviously this is bad and so | |
320 | * lockdep complains vehemently. | |
321 | */ | |
322 | pagefault_disable(); | |
432e58ed | 323 | list_for_each_entry(obj, objects, exec_list) { |
6fe4f140 | 324 | ret = i915_gem_execbuffer_relocate_object(obj, eb); |
54cf91dc | 325 | if (ret) |
d4aeee77 | 326 | break; |
54cf91dc | 327 | } |
d4aeee77 | 328 | pagefault_enable(); |
54cf91dc | 329 | |
d4aeee77 | 330 | return ret; |
54cf91dc CW |
331 | } |
332 | ||
1690e1eb CW |
333 | #define __EXEC_OBJECT_HAS_FENCE (1<<31) |
334 | ||
dabdfe02 CW |
335 | static int |
336 | need_reloc_mappable(struct drm_i915_gem_object *obj) | |
337 | { | |
338 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; | |
339 | return entry->relocation_count && !use_cpu_reloc(obj); | |
340 | } | |
341 | ||
1690e1eb CW |
342 | static int |
343 | pin_and_fence_object(struct drm_i915_gem_object *obj, | |
344 | struct intel_ring_buffer *ring) | |
345 | { | |
346 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; | |
347 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; | |
348 | bool need_fence, need_mappable; | |
349 | int ret; | |
350 | ||
351 | need_fence = | |
352 | has_fenced_gpu_access && | |
353 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
354 | obj->tiling_mode != I915_TILING_NONE; | |
dabdfe02 | 355 | need_mappable = need_fence || need_reloc_mappable(obj); |
1690e1eb CW |
356 | |
357 | ret = i915_gem_object_pin(obj, entry->alignment, need_mappable); | |
358 | if (ret) | |
359 | return ret; | |
360 | ||
361 | if (has_fenced_gpu_access) { | |
362 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { | |
06d98131 | 363 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
364 | if (ret) |
365 | goto err_unpin; | |
1690e1eb | 366 | |
9a5a53b3 | 367 | if (i915_gem_object_pin_fence(obj)) |
1690e1eb | 368 | entry->flags |= __EXEC_OBJECT_HAS_FENCE; |
9a5a53b3 | 369 | |
7dd49065 | 370 | obj->pending_fenced_gpu_access = true; |
1690e1eb | 371 | } |
1690e1eb CW |
372 | } |
373 | ||
374 | entry->offset = obj->gtt_offset; | |
375 | return 0; | |
376 | ||
377 | err_unpin: | |
378 | i915_gem_object_unpin(obj); | |
379 | return ret; | |
380 | } | |
381 | ||
54cf91dc | 382 | static int |
d9e86c0e | 383 | i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring, |
54cf91dc | 384 | struct drm_file *file, |
6fe4f140 | 385 | struct list_head *objects) |
54cf91dc | 386 | { |
7bddb01f | 387 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
432e58ed | 388 | struct drm_i915_gem_object *obj; |
432e58ed | 389 | int ret, retry; |
9b3826bf | 390 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; |
6fe4f140 CW |
391 | struct list_head ordered_objects; |
392 | ||
393 | INIT_LIST_HEAD(&ordered_objects); | |
394 | while (!list_empty(objects)) { | |
395 | struct drm_i915_gem_exec_object2 *entry; | |
396 | bool need_fence, need_mappable; | |
397 | ||
398 | obj = list_first_entry(objects, | |
399 | struct drm_i915_gem_object, | |
400 | exec_list); | |
401 | entry = obj->exec_entry; | |
402 | ||
403 | need_fence = | |
404 | has_fenced_gpu_access && | |
405 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
406 | obj->tiling_mode != I915_TILING_NONE; | |
dabdfe02 | 407 | need_mappable = need_fence || need_reloc_mappable(obj); |
6fe4f140 CW |
408 | |
409 | if (need_mappable) | |
410 | list_move(&obj->exec_list, &ordered_objects); | |
411 | else | |
412 | list_move_tail(&obj->exec_list, &ordered_objects); | |
595dad76 CW |
413 | |
414 | obj->base.pending_read_domains = 0; | |
415 | obj->base.pending_write_domain = 0; | |
6fe4f140 CW |
416 | } |
417 | list_splice(&ordered_objects, objects); | |
54cf91dc CW |
418 | |
419 | /* Attempt to pin all of the buffers into the GTT. | |
420 | * This is done in 3 phases: | |
421 | * | |
422 | * 1a. Unbind all objects that do not match the GTT constraints for | |
423 | * the execbuffer (fenceable, mappable, alignment etc). | |
424 | * 1b. Increment pin count for already bound objects. | |
425 | * 2. Bind new objects. | |
426 | * 3. Decrement pin count. | |
427 | * | |
428 | * This avoid unnecessary unbinding of later objects in order to makr | |
429 | * room for the earlier objects *unless* we need to defragment. | |
430 | */ | |
431 | retry = 0; | |
432 | do { | |
433 | ret = 0; | |
434 | ||
435 | /* Unbind any ill-fitting objects or pin. */ | |
432e58ed | 436 | list_for_each_entry(obj, objects, exec_list) { |
6fe4f140 | 437 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
54cf91dc | 438 | bool need_fence, need_mappable; |
1690e1eb | 439 | |
6fe4f140 | 440 | if (!obj->gtt_space) |
54cf91dc CW |
441 | continue; |
442 | ||
443 | need_fence = | |
9b3826bf | 444 | has_fenced_gpu_access && |
54cf91dc CW |
445 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
446 | obj->tiling_mode != I915_TILING_NONE; | |
dabdfe02 | 447 | need_mappable = need_fence || need_reloc_mappable(obj); |
54cf91dc CW |
448 | |
449 | if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) || | |
450 | (need_mappable && !obj->map_and_fenceable)) | |
451 | ret = i915_gem_object_unbind(obj); | |
452 | else | |
1690e1eb | 453 | ret = pin_and_fence_object(obj, ring); |
432e58ed | 454 | if (ret) |
54cf91dc | 455 | goto err; |
54cf91dc CW |
456 | } |
457 | ||
458 | /* Bind fresh objects */ | |
432e58ed | 459 | list_for_each_entry(obj, objects, exec_list) { |
1690e1eb CW |
460 | if (obj->gtt_space) |
461 | continue; | |
54cf91dc | 462 | |
1690e1eb CW |
463 | ret = pin_and_fence_object(obj, ring); |
464 | if (ret) { | |
465 | int ret_ignore; | |
466 | ||
467 | /* This can potentially raise a harmless | |
468 | * -EINVAL if we failed to bind in the above | |
469 | * call. It cannot raise -EINTR since we know | |
470 | * that the bo is freshly bound and so will | |
471 | * not need to be flushed or waited upon. | |
472 | */ | |
473 | ret_ignore = i915_gem_object_unbind(obj); | |
474 | (void)ret_ignore; | |
475 | WARN_ON(obj->gtt_space); | |
476 | break; | |
54cf91dc | 477 | } |
54cf91dc CW |
478 | } |
479 | ||
432e58ed CW |
480 | /* Decrement pin count for bound objects */ |
481 | list_for_each_entry(obj, objects, exec_list) { | |
1690e1eb CW |
482 | struct drm_i915_gem_exec_object2 *entry; |
483 | ||
484 | if (!obj->gtt_space) | |
485 | continue; | |
486 | ||
487 | entry = obj->exec_entry; | |
488 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) { | |
489 | i915_gem_object_unpin_fence(obj); | |
490 | entry->flags &= ~__EXEC_OBJECT_HAS_FENCE; | |
491 | } | |
492 | ||
493 | i915_gem_object_unpin(obj); | |
7bddb01f DV |
494 | |
495 | /* ... and ensure ppgtt mapping exist if needed. */ | |
496 | if (dev_priv->mm.aliasing_ppgtt && !obj->has_aliasing_ppgtt_mapping) { | |
497 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
498 | obj, obj->cache_level); | |
499 | ||
500 | obj->has_aliasing_ppgtt_mapping = 1; | |
501 | } | |
54cf91dc CW |
502 | } |
503 | ||
504 | if (ret != -ENOSPC || retry > 1) | |
505 | return ret; | |
506 | ||
507 | /* First attempt, just clear anything that is purgeable. | |
508 | * Second attempt, clear the entire GTT. | |
509 | */ | |
d9e86c0e | 510 | ret = i915_gem_evict_everything(ring->dev, retry == 0); |
54cf91dc CW |
511 | if (ret) |
512 | return ret; | |
513 | ||
514 | retry++; | |
515 | } while (1); | |
432e58ed CW |
516 | |
517 | err: | |
1690e1eb CW |
518 | list_for_each_entry_continue_reverse(obj, objects, exec_list) { |
519 | struct drm_i915_gem_exec_object2 *entry; | |
520 | ||
521 | if (!obj->gtt_space) | |
522 | continue; | |
523 | ||
524 | entry = obj->exec_entry; | |
525 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) { | |
526 | i915_gem_object_unpin_fence(obj); | |
527 | entry->flags &= ~__EXEC_OBJECT_HAS_FENCE; | |
528 | } | |
432e58ed | 529 | |
1690e1eb | 530 | i915_gem_object_unpin(obj); |
432e58ed CW |
531 | } |
532 | ||
533 | return ret; | |
54cf91dc CW |
534 | } |
535 | ||
536 | static int | |
537 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, | |
538 | struct drm_file *file, | |
d9e86c0e | 539 | struct intel_ring_buffer *ring, |
432e58ed | 540 | struct list_head *objects, |
67731b87 | 541 | struct eb_objects *eb, |
432e58ed | 542 | struct drm_i915_gem_exec_object2 *exec, |
54cf91dc CW |
543 | int count) |
544 | { | |
545 | struct drm_i915_gem_relocation_entry *reloc; | |
432e58ed | 546 | struct drm_i915_gem_object *obj; |
dd6864a4 | 547 | int *reloc_offset; |
54cf91dc CW |
548 | int i, total, ret; |
549 | ||
67731b87 | 550 | /* We may process another execbuffer during the unlock... */ |
36cf1742 | 551 | while (!list_empty(objects)) { |
67731b87 CW |
552 | obj = list_first_entry(objects, |
553 | struct drm_i915_gem_object, | |
554 | exec_list); | |
555 | list_del_init(&obj->exec_list); | |
556 | drm_gem_object_unreference(&obj->base); | |
557 | } | |
558 | ||
54cf91dc CW |
559 | mutex_unlock(&dev->struct_mutex); |
560 | ||
561 | total = 0; | |
562 | for (i = 0; i < count; i++) | |
432e58ed | 563 | total += exec[i].relocation_count; |
54cf91dc | 564 | |
dd6864a4 | 565 | reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset)); |
54cf91dc | 566 | reloc = drm_malloc_ab(total, sizeof(*reloc)); |
dd6864a4 CW |
567 | if (reloc == NULL || reloc_offset == NULL) { |
568 | drm_free_large(reloc); | |
569 | drm_free_large(reloc_offset); | |
54cf91dc CW |
570 | mutex_lock(&dev->struct_mutex); |
571 | return -ENOMEM; | |
572 | } | |
573 | ||
574 | total = 0; | |
575 | for (i = 0; i < count; i++) { | |
576 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
577 | ||
432e58ed | 578 | user_relocs = (void __user *)(uintptr_t)exec[i].relocs_ptr; |
54cf91dc CW |
579 | |
580 | if (copy_from_user(reloc+total, user_relocs, | |
432e58ed | 581 | exec[i].relocation_count * sizeof(*reloc))) { |
54cf91dc CW |
582 | ret = -EFAULT; |
583 | mutex_lock(&dev->struct_mutex); | |
584 | goto err; | |
585 | } | |
586 | ||
dd6864a4 | 587 | reloc_offset[i] = total; |
432e58ed | 588 | total += exec[i].relocation_count; |
54cf91dc CW |
589 | } |
590 | ||
591 | ret = i915_mutex_lock_interruptible(dev); | |
592 | if (ret) { | |
593 | mutex_lock(&dev->struct_mutex); | |
594 | goto err; | |
595 | } | |
596 | ||
67731b87 | 597 | /* reacquire the objects */ |
67731b87 CW |
598 | eb_reset(eb); |
599 | for (i = 0; i < count; i++) { | |
67731b87 CW |
600 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, |
601 | exec[i].handle)); | |
c8725226 | 602 | if (&obj->base == NULL) { |
ff240199 | 603 | DRM_DEBUG("Invalid object handle %d at index %d\n", |
67731b87 CW |
604 | exec[i].handle, i); |
605 | ret = -ENOENT; | |
606 | goto err; | |
607 | } | |
608 | ||
609 | list_add_tail(&obj->exec_list, objects); | |
610 | obj->exec_handle = exec[i].handle; | |
6fe4f140 | 611 | obj->exec_entry = &exec[i]; |
67731b87 CW |
612 | eb_add_object(eb, obj); |
613 | } | |
614 | ||
6fe4f140 | 615 | ret = i915_gem_execbuffer_reserve(ring, file, objects); |
54cf91dc CW |
616 | if (ret) |
617 | goto err; | |
618 | ||
432e58ed | 619 | list_for_each_entry(obj, objects, exec_list) { |
dd6864a4 | 620 | int offset = obj->exec_entry - exec; |
67731b87 | 621 | ret = i915_gem_execbuffer_relocate_object_slow(obj, eb, |
dd6864a4 | 622 | reloc + reloc_offset[offset]); |
54cf91dc CW |
623 | if (ret) |
624 | goto err; | |
54cf91dc CW |
625 | } |
626 | ||
627 | /* Leave the user relocations as are, this is the painfully slow path, | |
628 | * and we want to avoid the complication of dropping the lock whilst | |
629 | * having buffers reserved in the aperture and so causing spurious | |
630 | * ENOSPC for random operations. | |
631 | */ | |
632 | ||
633 | err: | |
634 | drm_free_large(reloc); | |
dd6864a4 | 635 | drm_free_large(reloc_offset); |
54cf91dc CW |
636 | return ret; |
637 | } | |
638 | ||
c59a333f CW |
639 | static int |
640 | i915_gem_execbuffer_wait_for_flips(struct intel_ring_buffer *ring, u32 flips) | |
641 | { | |
642 | u32 plane, flip_mask; | |
643 | int ret; | |
644 | ||
645 | /* Check for any pending flips. As we only maintain a flip queue depth | |
646 | * of 1, we can simply insert a WAIT for the next display flip prior | |
647 | * to executing the batch and avoid stalling the CPU. | |
648 | */ | |
649 | ||
650 | for (plane = 0; flips >> plane; plane++) { | |
651 | if (((flips >> plane) & 1) == 0) | |
652 | continue; | |
653 | ||
654 | if (plane) | |
655 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
656 | else | |
657 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
658 | ||
659 | ret = intel_ring_begin(ring, 2); | |
660 | if (ret) | |
661 | return ret; | |
662 | ||
663 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); | |
664 | intel_ring_emit(ring, MI_NOOP); | |
665 | intel_ring_advance(ring); | |
666 | } | |
667 | ||
668 | return 0; | |
669 | } | |
670 | ||
54cf91dc | 671 | static int |
432e58ed CW |
672 | i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring, |
673 | struct list_head *objects) | |
54cf91dc | 674 | { |
432e58ed | 675 | struct drm_i915_gem_object *obj; |
6ac42f41 DV |
676 | uint32_t flush_domains = 0; |
677 | uint32_t flips = 0; | |
432e58ed | 678 | int ret; |
54cf91dc | 679 | |
6ac42f41 DV |
680 | list_for_each_entry(obj, objects, exec_list) { |
681 | ret = i915_gem_object_sync(obj, ring); | |
c59a333f CW |
682 | if (ret) |
683 | return ret; | |
6ac42f41 DV |
684 | |
685 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) | |
686 | i915_gem_clflush_object(obj); | |
687 | ||
688 | if (obj->base.pending_write_domain) | |
689 | flips |= atomic_read(&obj->pending_flip); | |
690 | ||
691 | flush_domains |= obj->base.write_domain; | |
c59a333f CW |
692 | } |
693 | ||
6ac42f41 DV |
694 | if (flips) { |
695 | ret = i915_gem_execbuffer_wait_for_flips(ring, flips); | |
1ec14ad3 CW |
696 | if (ret) |
697 | return ret; | |
54cf91dc CW |
698 | } |
699 | ||
6ac42f41 DV |
700 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
701 | intel_gtt_chipset_flush(); | |
702 | ||
703 | if (flush_domains & I915_GEM_DOMAIN_GTT) | |
704 | wmb(); | |
705 | ||
09cf7c9a CW |
706 | /* Unconditionally invalidate gpu caches and ensure that we do flush |
707 | * any residual writes from the previous batch. | |
708 | */ | |
709 | ret = i915_gem_flush_ring(ring, | |
710 | I915_GEM_GPU_DOMAINS, | |
711 | ring->gpu_caches_dirty ? I915_GEM_GPU_DOMAINS : 0); | |
cc889e0f DV |
712 | if (ret) |
713 | return ret; | |
714 | ||
09cf7c9a | 715 | ring->gpu_caches_dirty = false; |
54cf91dc CW |
716 | return 0; |
717 | } | |
718 | ||
432e58ed CW |
719 | static bool |
720 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) | |
54cf91dc | 721 | { |
432e58ed | 722 | return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0; |
54cf91dc CW |
723 | } |
724 | ||
725 | static int | |
726 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, | |
727 | int count) | |
728 | { | |
729 | int i; | |
730 | ||
731 | for (i = 0; i < count; i++) { | |
732 | char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr; | |
733 | int length; /* limited by fault_in_pages_readable() */ | |
734 | ||
735 | /* First check for malicious input causing overflow */ | |
736 | if (exec[i].relocation_count > | |
737 | INT_MAX / sizeof(struct drm_i915_gem_relocation_entry)) | |
738 | return -EINVAL; | |
739 | ||
740 | length = exec[i].relocation_count * | |
741 | sizeof(struct drm_i915_gem_relocation_entry); | |
742 | if (!access_ok(VERIFY_READ, ptr, length)) | |
743 | return -EFAULT; | |
744 | ||
745 | /* we may also need to update the presumed offsets */ | |
746 | if (!access_ok(VERIFY_WRITE, ptr, length)) | |
747 | return -EFAULT; | |
748 | ||
f56f821f | 749 | if (fault_in_multipages_readable(ptr, length)) |
54cf91dc CW |
750 | return -EFAULT; |
751 | } | |
752 | ||
753 | return 0; | |
754 | } | |
755 | ||
432e58ed CW |
756 | static void |
757 | i915_gem_execbuffer_move_to_active(struct list_head *objects, | |
1ec14ad3 CW |
758 | struct intel_ring_buffer *ring, |
759 | u32 seqno) | |
432e58ed CW |
760 | { |
761 | struct drm_i915_gem_object *obj; | |
762 | ||
763 | list_for_each_entry(obj, objects, exec_list) { | |
69c2fc89 CW |
764 | u32 old_read = obj->base.read_domains; |
765 | u32 old_write = obj->base.write_domain; | |
db53a302 | 766 | |
432e58ed CW |
767 | obj->base.read_domains = obj->base.pending_read_domains; |
768 | obj->base.write_domain = obj->base.pending_write_domain; | |
769 | obj->fenced_gpu_access = obj->pending_fenced_gpu_access; | |
770 | ||
1ec14ad3 | 771 | i915_gem_object_move_to_active(obj, ring, seqno); |
432e58ed CW |
772 | if (obj->base.write_domain) { |
773 | obj->dirty = 1; | |
0201f1ec | 774 | obj->last_write_seqno = seqno; |
acb87dfb CW |
775 | if (obj->pin_count) /* check for potential scanout */ |
776 | intel_mark_busy(ring->dev, obj); | |
432e58ed CW |
777 | } |
778 | ||
db53a302 | 779 | trace_i915_gem_object_change_domain(obj, old_read, old_write); |
432e58ed | 780 | } |
acb87dfb CW |
781 | |
782 | intel_mark_busy(ring->dev, NULL); | |
432e58ed CW |
783 | } |
784 | ||
54cf91dc CW |
785 | static void |
786 | i915_gem_execbuffer_retire_commands(struct drm_device *dev, | |
432e58ed | 787 | struct drm_file *file, |
54cf91dc CW |
788 | struct intel_ring_buffer *ring) |
789 | { | |
cc889e0f DV |
790 | /* Unconditionally force add_request to emit a full flush. */ |
791 | ring->gpu_caches_dirty = true; | |
54cf91dc | 792 | |
432e58ed | 793 | /* Add a breadcrumb for the completion of the batch buffer */ |
3bb73aba | 794 | (void)i915_add_request(ring, file, NULL); |
432e58ed | 795 | } |
54cf91dc | 796 | |
ae662d31 EA |
797 | static int |
798 | i915_reset_gen7_sol_offsets(struct drm_device *dev, | |
799 | struct intel_ring_buffer *ring) | |
800 | { | |
801 | drm_i915_private_t *dev_priv = dev->dev_private; | |
802 | int ret, i; | |
803 | ||
804 | if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) | |
805 | return 0; | |
806 | ||
807 | ret = intel_ring_begin(ring, 4 * 3); | |
808 | if (ret) | |
809 | return ret; | |
810 | ||
811 | for (i = 0; i < 4; i++) { | |
812 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
813 | intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i)); | |
814 | intel_ring_emit(ring, 0); | |
815 | } | |
816 | ||
817 | intel_ring_advance(ring); | |
818 | ||
819 | return 0; | |
820 | } | |
821 | ||
54cf91dc CW |
822 | static int |
823 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, | |
824 | struct drm_file *file, | |
825 | struct drm_i915_gem_execbuffer2 *args, | |
432e58ed | 826 | struct drm_i915_gem_exec_object2 *exec) |
54cf91dc CW |
827 | { |
828 | drm_i915_private_t *dev_priv = dev->dev_private; | |
432e58ed | 829 | struct list_head objects; |
67731b87 | 830 | struct eb_objects *eb; |
54cf91dc CW |
831 | struct drm_i915_gem_object *batch_obj; |
832 | struct drm_clip_rect *cliprects = NULL; | |
54cf91dc | 833 | struct intel_ring_buffer *ring; |
6e0a69db | 834 | u32 ctx_id = i915_execbuffer2_get_context_id(*args); |
c4e7a414 | 835 | u32 exec_start, exec_len; |
1ec14ad3 | 836 | u32 seqno; |
84f9f938 | 837 | u32 mask; |
72bfa19c | 838 | int ret, mode, i; |
54cf91dc | 839 | |
432e58ed | 840 | if (!i915_gem_check_execbuffer(args)) { |
ff240199 | 841 | DRM_DEBUG("execbuf with invalid offset/length\n"); |
432e58ed CW |
842 | return -EINVAL; |
843 | } | |
844 | ||
845 | ret = validate_exec_list(exec, args->buffer_count); | |
54cf91dc CW |
846 | if (ret) |
847 | return ret; | |
848 | ||
54cf91dc CW |
849 | switch (args->flags & I915_EXEC_RING_MASK) { |
850 | case I915_EXEC_DEFAULT: | |
851 | case I915_EXEC_RENDER: | |
1ec14ad3 | 852 | ring = &dev_priv->ring[RCS]; |
54cf91dc CW |
853 | break; |
854 | case I915_EXEC_BSD: | |
1ec14ad3 | 855 | ring = &dev_priv->ring[VCS]; |
6e0a69db BW |
856 | if (ctx_id != 0) { |
857 | DRM_DEBUG("Ring %s doesn't support contexts\n", | |
858 | ring->name); | |
859 | return -EPERM; | |
860 | } | |
54cf91dc CW |
861 | break; |
862 | case I915_EXEC_BLT: | |
1ec14ad3 | 863 | ring = &dev_priv->ring[BCS]; |
6e0a69db BW |
864 | if (ctx_id != 0) { |
865 | DRM_DEBUG("Ring %s doesn't support contexts\n", | |
866 | ring->name); | |
867 | return -EPERM; | |
868 | } | |
54cf91dc CW |
869 | break; |
870 | default: | |
ff240199 | 871 | DRM_DEBUG("execbuf with unknown ring: %d\n", |
54cf91dc CW |
872 | (int)(args->flags & I915_EXEC_RING_MASK)); |
873 | return -EINVAL; | |
874 | } | |
a15817cf CW |
875 | if (!intel_ring_initialized(ring)) { |
876 | DRM_DEBUG("execbuf with invalid ring: %d\n", | |
877 | (int)(args->flags & I915_EXEC_RING_MASK)); | |
878 | return -EINVAL; | |
879 | } | |
54cf91dc | 880 | |
72bfa19c | 881 | mode = args->flags & I915_EXEC_CONSTANTS_MASK; |
84f9f938 | 882 | mask = I915_EXEC_CONSTANTS_MASK; |
72bfa19c CW |
883 | switch (mode) { |
884 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
885 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
886 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
887 | if (ring == &dev_priv->ring[RCS] && | |
888 | mode != dev_priv->relative_constants_mode) { | |
889 | if (INTEL_INFO(dev)->gen < 4) | |
890 | return -EINVAL; | |
891 | ||
892 | if (INTEL_INFO(dev)->gen > 5 && | |
893 | mode == I915_EXEC_CONSTANTS_REL_SURFACE) | |
894 | return -EINVAL; | |
84f9f938 BW |
895 | |
896 | /* The HW changed the meaning on this bit on gen6 */ | |
897 | if (INTEL_INFO(dev)->gen >= 6) | |
898 | mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
72bfa19c CW |
899 | } |
900 | break; | |
901 | default: | |
ff240199 | 902 | DRM_DEBUG("execbuf with unknown constants: %d\n", mode); |
72bfa19c CW |
903 | return -EINVAL; |
904 | } | |
905 | ||
54cf91dc | 906 | if (args->buffer_count < 1) { |
ff240199 | 907 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
908 | return -EINVAL; |
909 | } | |
54cf91dc CW |
910 | |
911 | if (args->num_cliprects != 0) { | |
1ec14ad3 | 912 | if (ring != &dev_priv->ring[RCS]) { |
ff240199 | 913 | DRM_DEBUG("clip rectangles are only valid with the render ring\n"); |
c4e7a414 CW |
914 | return -EINVAL; |
915 | } | |
916 | ||
6ebebc92 DV |
917 | if (INTEL_INFO(dev)->gen >= 5) { |
918 | DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); | |
919 | return -EINVAL; | |
920 | } | |
921 | ||
44afb3a0 XW |
922 | if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) { |
923 | DRM_DEBUG("execbuf with %u cliprects\n", | |
924 | args->num_cliprects); | |
925 | return -EINVAL; | |
926 | } | |
5e13a0c5 | 927 | |
432e58ed | 928 | cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects), |
54cf91dc CW |
929 | GFP_KERNEL); |
930 | if (cliprects == NULL) { | |
931 | ret = -ENOMEM; | |
932 | goto pre_mutex_err; | |
933 | } | |
934 | ||
432e58ed CW |
935 | if (copy_from_user(cliprects, |
936 | (struct drm_clip_rect __user *)(uintptr_t) | |
937 | args->cliprects_ptr, | |
938 | sizeof(*cliprects)*args->num_cliprects)) { | |
54cf91dc CW |
939 | ret = -EFAULT; |
940 | goto pre_mutex_err; | |
941 | } | |
942 | } | |
943 | ||
54cf91dc CW |
944 | ret = i915_mutex_lock_interruptible(dev); |
945 | if (ret) | |
946 | goto pre_mutex_err; | |
947 | ||
948 | if (dev_priv->mm.suspended) { | |
949 | mutex_unlock(&dev->struct_mutex); | |
950 | ret = -EBUSY; | |
951 | goto pre_mutex_err; | |
952 | } | |
953 | ||
67731b87 CW |
954 | eb = eb_create(args->buffer_count); |
955 | if (eb == NULL) { | |
956 | mutex_unlock(&dev->struct_mutex); | |
957 | ret = -ENOMEM; | |
958 | goto pre_mutex_err; | |
959 | } | |
960 | ||
54cf91dc | 961 | /* Look up object handles */ |
432e58ed | 962 | INIT_LIST_HEAD(&objects); |
54cf91dc CW |
963 | for (i = 0; i < args->buffer_count; i++) { |
964 | struct drm_i915_gem_object *obj; | |
965 | ||
432e58ed CW |
966 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, |
967 | exec[i].handle)); | |
c8725226 | 968 | if (&obj->base == NULL) { |
ff240199 | 969 | DRM_DEBUG("Invalid object handle %d at index %d\n", |
432e58ed | 970 | exec[i].handle, i); |
54cf91dc | 971 | /* prevent error path from reading uninitialized data */ |
54cf91dc CW |
972 | ret = -ENOENT; |
973 | goto err; | |
974 | } | |
54cf91dc | 975 | |
432e58ed | 976 | if (!list_empty(&obj->exec_list)) { |
ff240199 | 977 | DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n", |
432e58ed | 978 | obj, exec[i].handle, i); |
54cf91dc CW |
979 | ret = -EINVAL; |
980 | goto err; | |
981 | } | |
432e58ed CW |
982 | |
983 | list_add_tail(&obj->exec_list, &objects); | |
67731b87 | 984 | obj->exec_handle = exec[i].handle; |
6fe4f140 | 985 | obj->exec_entry = &exec[i]; |
67731b87 | 986 | eb_add_object(eb, obj); |
54cf91dc CW |
987 | } |
988 | ||
6fe4f140 CW |
989 | /* take note of the batch buffer before we might reorder the lists */ |
990 | batch_obj = list_entry(objects.prev, | |
991 | struct drm_i915_gem_object, | |
992 | exec_list); | |
993 | ||
54cf91dc | 994 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
6fe4f140 | 995 | ret = i915_gem_execbuffer_reserve(ring, file, &objects); |
54cf91dc CW |
996 | if (ret) |
997 | goto err; | |
998 | ||
999 | /* The objects are in their final locations, apply the relocations. */ | |
6fe4f140 | 1000 | ret = i915_gem_execbuffer_relocate(dev, eb, &objects); |
54cf91dc CW |
1001 | if (ret) { |
1002 | if (ret == -EFAULT) { | |
d9e86c0e | 1003 | ret = i915_gem_execbuffer_relocate_slow(dev, file, ring, |
67731b87 CW |
1004 | &objects, eb, |
1005 | exec, | |
54cf91dc CW |
1006 | args->buffer_count); |
1007 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1008 | } | |
1009 | if (ret) | |
1010 | goto err; | |
1011 | } | |
1012 | ||
1013 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
54cf91dc | 1014 | if (batch_obj->base.pending_write_domain) { |
ff240199 | 1015 | DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); |
54cf91dc CW |
1016 | ret = -EINVAL; |
1017 | goto err; | |
1018 | } | |
1019 | batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
1020 | ||
432e58ed CW |
1021 | ret = i915_gem_execbuffer_move_to_gpu(ring, &objects); |
1022 | if (ret) | |
54cf91dc | 1023 | goto err; |
54cf91dc | 1024 | |
db53a302 | 1025 | seqno = i915_gem_next_request_seqno(ring); |
076e2c0e | 1026 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) { |
1ec14ad3 CW |
1027 | if (seqno < ring->sync_seqno[i]) { |
1028 | /* The GPU can not handle its semaphore value wrapping, | |
1029 | * so every billion or so execbuffers, we need to stall | |
1030 | * the GPU in order to reset the counters. | |
1031 | */ | |
b2da9fe5 | 1032 | ret = i915_gpu_idle(dev); |
1ec14ad3 CW |
1033 | if (ret) |
1034 | goto err; | |
b2da9fe5 | 1035 | i915_gem_retire_requests(dev); |
1ec14ad3 CW |
1036 | |
1037 | BUG_ON(ring->sync_seqno[i]); | |
1038 | } | |
1039 | } | |
1040 | ||
0da5cec1 EA |
1041 | ret = i915_switch_context(ring, file, ctx_id); |
1042 | if (ret) | |
1043 | goto err; | |
1044 | ||
e2971bda BW |
1045 | if (ring == &dev_priv->ring[RCS] && |
1046 | mode != dev_priv->relative_constants_mode) { | |
1047 | ret = intel_ring_begin(ring, 4); | |
1048 | if (ret) | |
1049 | goto err; | |
1050 | ||
1051 | intel_ring_emit(ring, MI_NOOP); | |
1052 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
1053 | intel_ring_emit(ring, INSTPM); | |
84f9f938 | 1054 | intel_ring_emit(ring, mask << 16 | mode); |
e2971bda BW |
1055 | intel_ring_advance(ring); |
1056 | ||
1057 | dev_priv->relative_constants_mode = mode; | |
1058 | } | |
1059 | ||
ae662d31 EA |
1060 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { |
1061 | ret = i915_reset_gen7_sol_offsets(dev, ring); | |
1062 | if (ret) | |
1063 | goto err; | |
1064 | } | |
1065 | ||
db53a302 CW |
1066 | trace_i915_gem_ring_dispatch(ring, seqno); |
1067 | ||
c4e7a414 CW |
1068 | exec_start = batch_obj->gtt_offset + args->batch_start_offset; |
1069 | exec_len = args->batch_len; | |
1070 | if (cliprects) { | |
1071 | for (i = 0; i < args->num_cliprects; i++) { | |
1072 | ret = i915_emit_box(dev, &cliprects[i], | |
1073 | args->DR1, args->DR4); | |
1074 | if (ret) | |
1075 | goto err; | |
1076 | ||
1077 | ret = ring->dispatch_execbuffer(ring, | |
1078 | exec_start, exec_len); | |
1079 | if (ret) | |
1080 | goto err; | |
1081 | } | |
1082 | } else { | |
1083 | ret = ring->dispatch_execbuffer(ring, exec_start, exec_len); | |
1084 | if (ret) | |
1085 | goto err; | |
1086 | } | |
54cf91dc | 1087 | |
1ec14ad3 | 1088 | i915_gem_execbuffer_move_to_active(&objects, ring, seqno); |
432e58ed | 1089 | i915_gem_execbuffer_retire_commands(dev, file, ring); |
54cf91dc CW |
1090 | |
1091 | err: | |
67731b87 | 1092 | eb_destroy(eb); |
432e58ed CW |
1093 | while (!list_empty(&objects)) { |
1094 | struct drm_i915_gem_object *obj; | |
1095 | ||
1096 | obj = list_first_entry(&objects, | |
1097 | struct drm_i915_gem_object, | |
1098 | exec_list); | |
1099 | list_del_init(&obj->exec_list); | |
1100 | drm_gem_object_unreference(&obj->base); | |
54cf91dc CW |
1101 | } |
1102 | ||
1103 | mutex_unlock(&dev->struct_mutex); | |
1104 | ||
1105 | pre_mutex_err: | |
54cf91dc | 1106 | kfree(cliprects); |
54cf91dc CW |
1107 | return ret; |
1108 | } | |
1109 | ||
1110 | /* | |
1111 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
1112 | * list array and passes it to the real function. | |
1113 | */ | |
1114 | int | |
1115 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1116 | struct drm_file *file) | |
1117 | { | |
1118 | struct drm_i915_gem_execbuffer *args = data; | |
1119 | struct drm_i915_gem_execbuffer2 exec2; | |
1120 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
1121 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1122 | int ret, i; | |
1123 | ||
54cf91dc | 1124 | if (args->buffer_count < 1) { |
ff240199 | 1125 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1126 | return -EINVAL; |
1127 | } | |
1128 | ||
1129 | /* Copy in the exec list from userland */ | |
1130 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
1131 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
1132 | if (exec_list == NULL || exec2_list == NULL) { | |
ff240199 | 1133 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1134 | args->buffer_count); |
1135 | drm_free_large(exec_list); | |
1136 | drm_free_large(exec2_list); | |
1137 | return -ENOMEM; | |
1138 | } | |
1139 | ret = copy_from_user(exec_list, | |
1140 | (struct drm_i915_relocation_entry __user *) | |
1141 | (uintptr_t) args->buffers_ptr, | |
1142 | sizeof(*exec_list) * args->buffer_count); | |
1143 | if (ret != 0) { | |
ff240199 | 1144 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1145 | args->buffer_count, ret); |
1146 | drm_free_large(exec_list); | |
1147 | drm_free_large(exec2_list); | |
1148 | return -EFAULT; | |
1149 | } | |
1150 | ||
1151 | for (i = 0; i < args->buffer_count; i++) { | |
1152 | exec2_list[i].handle = exec_list[i].handle; | |
1153 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
1154 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
1155 | exec2_list[i].alignment = exec_list[i].alignment; | |
1156 | exec2_list[i].offset = exec_list[i].offset; | |
1157 | if (INTEL_INFO(dev)->gen < 4) | |
1158 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; | |
1159 | else | |
1160 | exec2_list[i].flags = 0; | |
1161 | } | |
1162 | ||
1163 | exec2.buffers_ptr = args->buffers_ptr; | |
1164 | exec2.buffer_count = args->buffer_count; | |
1165 | exec2.batch_start_offset = args->batch_start_offset; | |
1166 | exec2.batch_len = args->batch_len; | |
1167 | exec2.DR1 = args->DR1; | |
1168 | exec2.DR4 = args->DR4; | |
1169 | exec2.num_cliprects = args->num_cliprects; | |
1170 | exec2.cliprects_ptr = args->cliprects_ptr; | |
1171 | exec2.flags = I915_EXEC_RENDER; | |
6e0a69db | 1172 | i915_execbuffer2_set_context_id(exec2, 0); |
54cf91dc CW |
1173 | |
1174 | ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list); | |
1175 | if (!ret) { | |
1176 | /* Copy the new buffer offsets back to the user's exec list. */ | |
1177 | for (i = 0; i < args->buffer_count; i++) | |
1178 | exec_list[i].offset = exec2_list[i].offset; | |
1179 | /* ... and back out to userspace */ | |
1180 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
1181 | (uintptr_t) args->buffers_ptr, | |
1182 | exec_list, | |
1183 | sizeof(*exec_list) * args->buffer_count); | |
1184 | if (ret) { | |
1185 | ret = -EFAULT; | |
ff240199 | 1186 | DRM_DEBUG("failed to copy %d exec entries " |
54cf91dc CW |
1187 | "back to user (%d)\n", |
1188 | args->buffer_count, ret); | |
1189 | } | |
1190 | } | |
1191 | ||
1192 | drm_free_large(exec_list); | |
1193 | drm_free_large(exec2_list); | |
1194 | return ret; | |
1195 | } | |
1196 | ||
1197 | int | |
1198 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
1199 | struct drm_file *file) | |
1200 | { | |
1201 | struct drm_i915_gem_execbuffer2 *args = data; | |
1202 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1203 | int ret; | |
1204 | ||
ed8cd3b2 XW |
1205 | if (args->buffer_count < 1 || |
1206 | args->buffer_count > UINT_MAX / sizeof(*exec2_list)) { | |
ff240199 | 1207 | DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1208 | return -EINVAL; |
1209 | } | |
1210 | ||
8408c282 CW |
1211 | exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count, |
1212 | GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY); | |
1213 | if (exec2_list == NULL) | |
1214 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), | |
1215 | args->buffer_count); | |
54cf91dc | 1216 | if (exec2_list == NULL) { |
ff240199 | 1217 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1218 | args->buffer_count); |
1219 | return -ENOMEM; | |
1220 | } | |
1221 | ret = copy_from_user(exec2_list, | |
1222 | (struct drm_i915_relocation_entry __user *) | |
1223 | (uintptr_t) args->buffers_ptr, | |
1224 | sizeof(*exec2_list) * args->buffer_count); | |
1225 | if (ret != 0) { | |
ff240199 | 1226 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1227 | args->buffer_count, ret); |
1228 | drm_free_large(exec2_list); | |
1229 | return -EFAULT; | |
1230 | } | |
1231 | ||
1232 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list); | |
1233 | if (!ret) { | |
1234 | /* Copy the new buffer offsets back to the user's exec list. */ | |
1235 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
1236 | (uintptr_t) args->buffers_ptr, | |
1237 | exec2_list, | |
1238 | sizeof(*exec2_list) * args->buffer_count); | |
1239 | if (ret) { | |
1240 | ret = -EFAULT; | |
ff240199 | 1241 | DRM_DEBUG("failed to copy %d exec entries " |
54cf91dc CW |
1242 | "back to user (%d)\n", |
1243 | args->buffer_count, ret); | |
1244 | } | |
1245 | } | |
1246 | ||
1247 | drm_free_large(exec2_list); | |
1248 | return ret; | |
1249 | } |