Commit | Line | Data |
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54cf91dc CW |
1 | /* |
2 | * Copyright © 2008,2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Chris Wilson <chris@chris-wilson.co.uk> | |
26 | * | |
27 | */ | |
28 | ||
760285e7 DH |
29 | #include <drm/drmP.h> |
30 | #include <drm/i915_drm.h> | |
54cf91dc CW |
31 | #include "i915_drv.h" |
32 | #include "i915_trace.h" | |
33 | #include "intel_drv.h" | |
f45b5557 | 34 | #include <linux/dma_remapping.h> |
54cf91dc | 35 | |
67731b87 | 36 | struct eb_objects { |
bcffc3fa | 37 | struct list_head objects; |
67731b87 | 38 | int and; |
eef90ccb CW |
39 | union { |
40 | struct drm_i915_gem_object *lut[0]; | |
41 | struct hlist_head buckets[0]; | |
42 | }; | |
67731b87 CW |
43 | }; |
44 | ||
45 | static struct eb_objects * | |
eef90ccb | 46 | eb_create(struct drm_i915_gem_execbuffer2 *args) |
67731b87 | 47 | { |
eef90ccb CW |
48 | struct eb_objects *eb = NULL; |
49 | ||
50 | if (args->flags & I915_EXEC_HANDLE_LUT) { | |
51 | int size = args->buffer_count; | |
52 | size *= sizeof(struct drm_i915_gem_object *); | |
53 | size += sizeof(struct eb_objects); | |
54 | eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); | |
55 | } | |
56 | ||
57 | if (eb == NULL) { | |
58 | int size = args->buffer_count; | |
59 | int count = PAGE_SIZE / sizeof(struct hlist_head) / 2; | |
60 | BUILD_BUG_ON(!is_power_of_2(PAGE_SIZE / sizeof(struct hlist_head))); | |
61 | while (count > 2*size) | |
62 | count >>= 1; | |
63 | eb = kzalloc(count*sizeof(struct hlist_head) + | |
64 | sizeof(struct eb_objects), | |
65 | GFP_TEMPORARY); | |
66 | if (eb == NULL) | |
67 | return eb; | |
68 | ||
69 | eb->and = count - 1; | |
70 | } else | |
71 | eb->and = -args->buffer_count; | |
72 | ||
bcffc3fa | 73 | INIT_LIST_HEAD(&eb->objects); |
67731b87 CW |
74 | return eb; |
75 | } | |
76 | ||
77 | static void | |
78 | eb_reset(struct eb_objects *eb) | |
79 | { | |
eef90ccb CW |
80 | if (eb->and >= 0) |
81 | memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head)); | |
67731b87 CW |
82 | } |
83 | ||
3b96eff4 CW |
84 | static int |
85 | eb_lookup_objects(struct eb_objects *eb, | |
86 | struct drm_i915_gem_exec_object2 *exec, | |
eef90ccb | 87 | const struct drm_i915_gem_execbuffer2 *args, |
bcffc3fa | 88 | struct drm_file *file) |
3b96eff4 CW |
89 | { |
90 | int i; | |
91 | ||
92 | spin_lock(&file->table_lock); | |
eef90ccb | 93 | for (i = 0; i < args->buffer_count; i++) { |
3b96eff4 CW |
94 | struct drm_i915_gem_object *obj; |
95 | ||
96 | obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle)); | |
97 | if (obj == NULL) { | |
98 | spin_unlock(&file->table_lock); | |
99 | DRM_DEBUG("Invalid object handle %d at index %d\n", | |
100 | exec[i].handle, i); | |
101 | return -ENOENT; | |
102 | } | |
103 | ||
104 | if (!list_empty(&obj->exec_list)) { | |
105 | spin_unlock(&file->table_lock); | |
106 | DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n", | |
107 | obj, exec[i].handle, i); | |
108 | return -EINVAL; | |
109 | } | |
110 | ||
111 | drm_gem_object_reference(&obj->base); | |
bcffc3fa | 112 | list_add_tail(&obj->exec_list, &eb->objects); |
3b96eff4 | 113 | |
3b96eff4 | 114 | obj->exec_entry = &exec[i]; |
eef90ccb CW |
115 | if (eb->and < 0) { |
116 | eb->lut[i] = obj; | |
117 | } else { | |
118 | uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle; | |
119 | obj->exec_handle = handle; | |
120 | hlist_add_head(&obj->exec_node, | |
121 | &eb->buckets[handle & eb->and]); | |
122 | } | |
3b96eff4 CW |
123 | } |
124 | spin_unlock(&file->table_lock); | |
125 | ||
126 | return 0; | |
127 | } | |
128 | ||
67731b87 CW |
129 | static struct drm_i915_gem_object * |
130 | eb_get_object(struct eb_objects *eb, unsigned long handle) | |
131 | { | |
eef90ccb CW |
132 | if (eb->and < 0) { |
133 | if (handle >= -eb->and) | |
134 | return NULL; | |
135 | return eb->lut[handle]; | |
136 | } else { | |
137 | struct hlist_head *head; | |
138 | struct hlist_node *node; | |
67731b87 | 139 | |
eef90ccb CW |
140 | head = &eb->buckets[handle & eb->and]; |
141 | hlist_for_each(node, head) { | |
142 | struct drm_i915_gem_object *obj; | |
67731b87 | 143 | |
eef90ccb CW |
144 | obj = hlist_entry(node, struct drm_i915_gem_object, exec_node); |
145 | if (obj->exec_handle == handle) | |
146 | return obj; | |
147 | } | |
148 | return NULL; | |
149 | } | |
67731b87 CW |
150 | } |
151 | ||
152 | static void | |
153 | eb_destroy(struct eb_objects *eb) | |
154 | { | |
bcffc3fa CW |
155 | while (!list_empty(&eb->objects)) { |
156 | struct drm_i915_gem_object *obj; | |
157 | ||
158 | obj = list_first_entry(&eb->objects, | |
159 | struct drm_i915_gem_object, | |
160 | exec_list); | |
161 | list_del_init(&obj->exec_list); | |
162 | drm_gem_object_unreference(&obj->base); | |
163 | } | |
67731b87 CW |
164 | kfree(eb); |
165 | } | |
166 | ||
dabdfe02 CW |
167 | static inline int use_cpu_reloc(struct drm_i915_gem_object *obj) |
168 | { | |
169 | return (obj->base.write_domain == I915_GEM_DOMAIN_CPU || | |
504c7267 | 170 | !obj->map_and_fenceable || |
dabdfe02 CW |
171 | obj->cache_level != I915_CACHE_NONE); |
172 | } | |
173 | ||
54cf91dc CW |
174 | static int |
175 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, | |
67731b87 | 176 | struct eb_objects *eb, |
54cf91dc CW |
177 | struct drm_i915_gem_relocation_entry *reloc) |
178 | { | |
179 | struct drm_device *dev = obj->base.dev; | |
180 | struct drm_gem_object *target_obj; | |
149c8407 | 181 | struct drm_i915_gem_object *target_i915_obj; |
54cf91dc CW |
182 | uint32_t target_offset; |
183 | int ret = -EINVAL; | |
184 | ||
67731b87 CW |
185 | /* we've already hold a reference to all valid objects */ |
186 | target_obj = &eb_get_object(eb, reloc->target_handle)->base; | |
187 | if (unlikely(target_obj == NULL)) | |
54cf91dc CW |
188 | return -ENOENT; |
189 | ||
149c8407 DV |
190 | target_i915_obj = to_intel_bo(target_obj); |
191 | target_offset = target_i915_obj->gtt_offset; | |
54cf91dc | 192 | |
e844b990 EA |
193 | /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and |
194 | * pipe_control writes because the gpu doesn't properly redirect them | |
195 | * through the ppgtt for non_secure batchbuffers. */ | |
196 | if (unlikely(IS_GEN6(dev) && | |
197 | reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION && | |
198 | !target_i915_obj->has_global_gtt_mapping)) { | |
199 | i915_gem_gtt_bind_object(target_i915_obj, | |
200 | target_i915_obj->cache_level); | |
201 | } | |
202 | ||
54cf91dc | 203 | /* Validate that the target is in a valid r/w GPU domain */ |
b8f7ab17 | 204 | if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { |
ff240199 | 205 | DRM_DEBUG("reloc with multiple write domains: " |
54cf91dc CW |
206 | "obj %p target %d offset %d " |
207 | "read %08x write %08x", | |
208 | obj, reloc->target_handle, | |
209 | (int) reloc->offset, | |
210 | reloc->read_domains, | |
211 | reloc->write_domain); | |
67731b87 | 212 | return ret; |
54cf91dc | 213 | } |
4ca4a250 DV |
214 | if (unlikely((reloc->write_domain | reloc->read_domains) |
215 | & ~I915_GEM_GPU_DOMAINS)) { | |
ff240199 | 216 | DRM_DEBUG("reloc with read/write non-GPU domains: " |
54cf91dc CW |
217 | "obj %p target %d offset %d " |
218 | "read %08x write %08x", | |
219 | obj, reloc->target_handle, | |
220 | (int) reloc->offset, | |
221 | reloc->read_domains, | |
222 | reloc->write_domain); | |
67731b87 | 223 | return ret; |
54cf91dc | 224 | } |
54cf91dc CW |
225 | |
226 | target_obj->pending_read_domains |= reloc->read_domains; | |
227 | target_obj->pending_write_domain |= reloc->write_domain; | |
228 | ||
229 | /* If the relocation already has the right value in it, no | |
230 | * more work needs to be done. | |
231 | */ | |
232 | if (target_offset == reloc->presumed_offset) | |
67731b87 | 233 | return 0; |
54cf91dc CW |
234 | |
235 | /* Check that the relocation address is valid... */ | |
b8f7ab17 | 236 | if (unlikely(reloc->offset > obj->base.size - 4)) { |
ff240199 | 237 | DRM_DEBUG("Relocation beyond object bounds: " |
54cf91dc CW |
238 | "obj %p target %d offset %d size %d.\n", |
239 | obj, reloc->target_handle, | |
240 | (int) reloc->offset, | |
241 | (int) obj->base.size); | |
67731b87 | 242 | return ret; |
54cf91dc | 243 | } |
b8f7ab17 | 244 | if (unlikely(reloc->offset & 3)) { |
ff240199 | 245 | DRM_DEBUG("Relocation not 4-byte aligned: " |
54cf91dc CW |
246 | "obj %p target %d offset %d.\n", |
247 | obj, reloc->target_handle, | |
248 | (int) reloc->offset); | |
67731b87 | 249 | return ret; |
54cf91dc CW |
250 | } |
251 | ||
dabdfe02 CW |
252 | /* We can't wait for rendering with pagefaults disabled */ |
253 | if (obj->active && in_atomic()) | |
254 | return -EFAULT; | |
255 | ||
54cf91dc | 256 | reloc->delta += target_offset; |
dabdfe02 | 257 | if (use_cpu_reloc(obj)) { |
54cf91dc CW |
258 | uint32_t page_offset = reloc->offset & ~PAGE_MASK; |
259 | char *vaddr; | |
260 | ||
dabdfe02 CW |
261 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
262 | if (ret) | |
263 | return ret; | |
264 | ||
9da3da66 CW |
265 | vaddr = kmap_atomic(i915_gem_object_get_page(obj, |
266 | reloc->offset >> PAGE_SHIFT)); | |
54cf91dc CW |
267 | *(uint32_t *)(vaddr + page_offset) = reloc->delta; |
268 | kunmap_atomic(vaddr); | |
269 | } else { | |
270 | struct drm_i915_private *dev_priv = dev->dev_private; | |
271 | uint32_t __iomem *reloc_entry; | |
272 | void __iomem *reloc_page; | |
273 | ||
7b09638f CW |
274 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
275 | if (ret) | |
276 | return ret; | |
277 | ||
278 | ret = i915_gem_object_put_fence(obj); | |
54cf91dc | 279 | if (ret) |
67731b87 | 280 | return ret; |
54cf91dc CW |
281 | |
282 | /* Map the page containing the relocation we're going to perform. */ | |
283 | reloc->offset += obj->gtt_offset; | |
5d4545ae | 284 | reloc_page = io_mapping_map_atomic_wc(dev_priv->gtt.mappable, |
54cf91dc CW |
285 | reloc->offset & PAGE_MASK); |
286 | reloc_entry = (uint32_t __iomem *) | |
287 | (reloc_page + (reloc->offset & ~PAGE_MASK)); | |
288 | iowrite32(reloc->delta, reloc_entry); | |
289 | io_mapping_unmap_atomic(reloc_page); | |
290 | } | |
291 | ||
292 | /* and update the user's relocation entry */ | |
293 | reloc->presumed_offset = target_offset; | |
294 | ||
67731b87 | 295 | return 0; |
54cf91dc CW |
296 | } |
297 | ||
298 | static int | |
299 | i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj, | |
6fe4f140 | 300 | struct eb_objects *eb) |
54cf91dc | 301 | { |
1d83f442 CW |
302 | #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) |
303 | struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)]; | |
54cf91dc | 304 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
6fe4f140 | 305 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
1d83f442 | 306 | int remain, ret; |
54cf91dc | 307 | |
2bb4629a | 308 | user_relocs = to_user_ptr(entry->relocs_ptr); |
54cf91dc | 309 | |
1d83f442 CW |
310 | remain = entry->relocation_count; |
311 | while (remain) { | |
312 | struct drm_i915_gem_relocation_entry *r = stack_reloc; | |
313 | int count = remain; | |
314 | if (count > ARRAY_SIZE(stack_reloc)) | |
315 | count = ARRAY_SIZE(stack_reloc); | |
316 | remain -= count; | |
317 | ||
318 | if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0]))) | |
54cf91dc CW |
319 | return -EFAULT; |
320 | ||
1d83f442 CW |
321 | do { |
322 | u64 offset = r->presumed_offset; | |
54cf91dc | 323 | |
1d83f442 CW |
324 | ret = i915_gem_execbuffer_relocate_entry(obj, eb, r); |
325 | if (ret) | |
326 | return ret; | |
327 | ||
328 | if (r->presumed_offset != offset && | |
329 | __copy_to_user_inatomic(&user_relocs->presumed_offset, | |
330 | &r->presumed_offset, | |
331 | sizeof(r->presumed_offset))) { | |
332 | return -EFAULT; | |
333 | } | |
334 | ||
335 | user_relocs++; | |
336 | r++; | |
337 | } while (--count); | |
54cf91dc CW |
338 | } |
339 | ||
340 | return 0; | |
1d83f442 | 341 | #undef N_RELOC |
54cf91dc CW |
342 | } |
343 | ||
344 | static int | |
345 | i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj, | |
67731b87 | 346 | struct eb_objects *eb, |
54cf91dc CW |
347 | struct drm_i915_gem_relocation_entry *relocs) |
348 | { | |
6fe4f140 | 349 | const struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
54cf91dc CW |
350 | int i, ret; |
351 | ||
352 | for (i = 0; i < entry->relocation_count; i++) { | |
6fe4f140 | 353 | ret = i915_gem_execbuffer_relocate_entry(obj, eb, &relocs[i]); |
54cf91dc CW |
354 | if (ret) |
355 | return ret; | |
356 | } | |
357 | ||
358 | return 0; | |
359 | } | |
360 | ||
361 | static int | |
362 | i915_gem_execbuffer_relocate(struct drm_device *dev, | |
bcffc3fa | 363 | struct eb_objects *eb) |
54cf91dc | 364 | { |
432e58ed | 365 | struct drm_i915_gem_object *obj; |
d4aeee77 CW |
366 | int ret = 0; |
367 | ||
368 | /* This is the fast path and we cannot handle a pagefault whilst | |
369 | * holding the struct mutex lest the user pass in the relocations | |
370 | * contained within a mmaped bo. For in such a case we, the page | |
371 | * fault handler would call i915_gem_fault() and we would try to | |
372 | * acquire the struct mutex again. Obviously this is bad and so | |
373 | * lockdep complains vehemently. | |
374 | */ | |
375 | pagefault_disable(); | |
bcffc3fa | 376 | list_for_each_entry(obj, &eb->objects, exec_list) { |
6fe4f140 | 377 | ret = i915_gem_execbuffer_relocate_object(obj, eb); |
54cf91dc | 378 | if (ret) |
d4aeee77 | 379 | break; |
54cf91dc | 380 | } |
d4aeee77 | 381 | pagefault_enable(); |
54cf91dc | 382 | |
d4aeee77 | 383 | return ret; |
54cf91dc CW |
384 | } |
385 | ||
7788a765 CW |
386 | #define __EXEC_OBJECT_HAS_PIN (1<<31) |
387 | #define __EXEC_OBJECT_HAS_FENCE (1<<30) | |
1690e1eb | 388 | |
dabdfe02 CW |
389 | static int |
390 | need_reloc_mappable(struct drm_i915_gem_object *obj) | |
391 | { | |
392 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; | |
393 | return entry->relocation_count && !use_cpu_reloc(obj); | |
394 | } | |
395 | ||
1690e1eb | 396 | static int |
7788a765 | 397 | i915_gem_execbuffer_reserve_object(struct drm_i915_gem_object *obj, |
ed5982e6 DV |
398 | struct intel_ring_buffer *ring, |
399 | bool *need_reloc) | |
1690e1eb | 400 | { |
7788a765 | 401 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
1690e1eb CW |
402 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
403 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; | |
404 | bool need_fence, need_mappable; | |
405 | int ret; | |
406 | ||
407 | need_fence = | |
408 | has_fenced_gpu_access && | |
409 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
410 | obj->tiling_mode != I915_TILING_NONE; | |
dabdfe02 | 411 | need_mappable = need_fence || need_reloc_mappable(obj); |
1690e1eb | 412 | |
86a1ee26 | 413 | ret = i915_gem_object_pin(obj, entry->alignment, need_mappable, false); |
1690e1eb CW |
414 | if (ret) |
415 | return ret; | |
416 | ||
7788a765 CW |
417 | entry->flags |= __EXEC_OBJECT_HAS_PIN; |
418 | ||
1690e1eb CW |
419 | if (has_fenced_gpu_access) { |
420 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { | |
06d98131 | 421 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 | 422 | if (ret) |
7788a765 | 423 | return ret; |
1690e1eb | 424 | |
9a5a53b3 | 425 | if (i915_gem_object_pin_fence(obj)) |
1690e1eb | 426 | entry->flags |= __EXEC_OBJECT_HAS_FENCE; |
9a5a53b3 | 427 | |
7dd49065 | 428 | obj->pending_fenced_gpu_access = true; |
1690e1eb | 429 | } |
1690e1eb CW |
430 | } |
431 | ||
7788a765 CW |
432 | /* Ensure ppgtt mapping exists if needed */ |
433 | if (dev_priv->mm.aliasing_ppgtt && !obj->has_aliasing_ppgtt_mapping) { | |
434 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
435 | obj, obj->cache_level); | |
436 | ||
437 | obj->has_aliasing_ppgtt_mapping = 1; | |
438 | } | |
439 | ||
ed5982e6 DV |
440 | if (entry->offset != obj->gtt_offset) { |
441 | entry->offset = obj->gtt_offset; | |
442 | *need_reloc = true; | |
443 | } | |
444 | ||
445 | if (entry->flags & EXEC_OBJECT_WRITE) { | |
446 | obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER; | |
447 | obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER; | |
448 | } | |
449 | ||
450 | if (entry->flags & EXEC_OBJECT_NEEDS_GTT && | |
451 | !obj->has_global_gtt_mapping) | |
452 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
453 | ||
1690e1eb | 454 | return 0; |
7788a765 | 455 | } |
1690e1eb | 456 | |
7788a765 CW |
457 | static void |
458 | i915_gem_execbuffer_unreserve_object(struct drm_i915_gem_object *obj) | |
459 | { | |
460 | struct drm_i915_gem_exec_object2 *entry; | |
461 | ||
462 | if (!obj->gtt_space) | |
463 | return; | |
464 | ||
465 | entry = obj->exec_entry; | |
466 | ||
467 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) | |
468 | i915_gem_object_unpin_fence(obj); | |
469 | ||
470 | if (entry->flags & __EXEC_OBJECT_HAS_PIN) | |
471 | i915_gem_object_unpin(obj); | |
472 | ||
473 | entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN); | |
1690e1eb CW |
474 | } |
475 | ||
54cf91dc | 476 | static int |
d9e86c0e | 477 | i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring, |
54cf91dc | 478 | struct drm_file *file, |
ed5982e6 DV |
479 | struct list_head *objects, |
480 | bool *need_relocs) | |
54cf91dc | 481 | { |
432e58ed | 482 | struct drm_i915_gem_object *obj; |
6fe4f140 | 483 | struct list_head ordered_objects; |
7788a765 CW |
484 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; |
485 | int retry; | |
6fe4f140 CW |
486 | |
487 | INIT_LIST_HEAD(&ordered_objects); | |
488 | while (!list_empty(objects)) { | |
489 | struct drm_i915_gem_exec_object2 *entry; | |
490 | bool need_fence, need_mappable; | |
491 | ||
492 | obj = list_first_entry(objects, | |
493 | struct drm_i915_gem_object, | |
494 | exec_list); | |
495 | entry = obj->exec_entry; | |
496 | ||
497 | need_fence = | |
498 | has_fenced_gpu_access && | |
499 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
500 | obj->tiling_mode != I915_TILING_NONE; | |
dabdfe02 | 501 | need_mappable = need_fence || need_reloc_mappable(obj); |
6fe4f140 CW |
502 | |
503 | if (need_mappable) | |
504 | list_move(&obj->exec_list, &ordered_objects); | |
505 | else | |
506 | list_move_tail(&obj->exec_list, &ordered_objects); | |
595dad76 | 507 | |
ed5982e6 | 508 | obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND; |
595dad76 | 509 | obj->base.pending_write_domain = 0; |
016fd0c1 | 510 | obj->pending_fenced_gpu_access = false; |
6fe4f140 CW |
511 | } |
512 | list_splice(&ordered_objects, objects); | |
54cf91dc CW |
513 | |
514 | /* Attempt to pin all of the buffers into the GTT. | |
515 | * This is done in 3 phases: | |
516 | * | |
517 | * 1a. Unbind all objects that do not match the GTT constraints for | |
518 | * the execbuffer (fenceable, mappable, alignment etc). | |
519 | * 1b. Increment pin count for already bound objects. | |
520 | * 2. Bind new objects. | |
521 | * 3. Decrement pin count. | |
522 | * | |
7788a765 | 523 | * This avoid unnecessary unbinding of later objects in order to make |
54cf91dc CW |
524 | * room for the earlier objects *unless* we need to defragment. |
525 | */ | |
526 | retry = 0; | |
527 | do { | |
7788a765 | 528 | int ret = 0; |
54cf91dc CW |
529 | |
530 | /* Unbind any ill-fitting objects or pin. */ | |
432e58ed | 531 | list_for_each_entry(obj, objects, exec_list) { |
6fe4f140 | 532 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
54cf91dc | 533 | bool need_fence, need_mappable; |
1690e1eb | 534 | |
6fe4f140 | 535 | if (!obj->gtt_space) |
54cf91dc CW |
536 | continue; |
537 | ||
538 | need_fence = | |
9b3826bf | 539 | has_fenced_gpu_access && |
54cf91dc CW |
540 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
541 | obj->tiling_mode != I915_TILING_NONE; | |
dabdfe02 | 542 | need_mappable = need_fence || need_reloc_mappable(obj); |
54cf91dc CW |
543 | |
544 | if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) || | |
545 | (need_mappable && !obj->map_and_fenceable)) | |
546 | ret = i915_gem_object_unbind(obj); | |
547 | else | |
ed5982e6 | 548 | ret = i915_gem_execbuffer_reserve_object(obj, ring, need_relocs); |
432e58ed | 549 | if (ret) |
54cf91dc | 550 | goto err; |
54cf91dc CW |
551 | } |
552 | ||
553 | /* Bind fresh objects */ | |
432e58ed | 554 | list_for_each_entry(obj, objects, exec_list) { |
1690e1eb CW |
555 | if (obj->gtt_space) |
556 | continue; | |
54cf91dc | 557 | |
ed5982e6 | 558 | ret = i915_gem_execbuffer_reserve_object(obj, ring, need_relocs); |
7788a765 CW |
559 | if (ret) |
560 | goto err; | |
54cf91dc CW |
561 | } |
562 | ||
7788a765 CW |
563 | err: /* Decrement pin count for bound objects */ |
564 | list_for_each_entry(obj, objects, exec_list) | |
565 | i915_gem_execbuffer_unreserve_object(obj); | |
54cf91dc | 566 | |
6c085a72 | 567 | if (ret != -ENOSPC || retry++) |
54cf91dc CW |
568 | return ret; |
569 | ||
6c085a72 | 570 | ret = i915_gem_evict_everything(ring->dev); |
54cf91dc CW |
571 | if (ret) |
572 | return ret; | |
54cf91dc CW |
573 | } while (1); |
574 | } | |
575 | ||
576 | static int | |
577 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, | |
ed5982e6 | 578 | struct drm_i915_gem_execbuffer2 *args, |
54cf91dc | 579 | struct drm_file *file, |
d9e86c0e | 580 | struct intel_ring_buffer *ring, |
67731b87 | 581 | struct eb_objects *eb, |
ed5982e6 | 582 | struct drm_i915_gem_exec_object2 *exec) |
54cf91dc CW |
583 | { |
584 | struct drm_i915_gem_relocation_entry *reloc; | |
432e58ed | 585 | struct drm_i915_gem_object *obj; |
ed5982e6 | 586 | bool need_relocs; |
dd6864a4 | 587 | int *reloc_offset; |
54cf91dc | 588 | int i, total, ret; |
ed5982e6 | 589 | int count = args->buffer_count; |
54cf91dc | 590 | |
67731b87 | 591 | /* We may process another execbuffer during the unlock... */ |
bcffc3fa CW |
592 | while (!list_empty(&eb->objects)) { |
593 | obj = list_first_entry(&eb->objects, | |
67731b87 CW |
594 | struct drm_i915_gem_object, |
595 | exec_list); | |
596 | list_del_init(&obj->exec_list); | |
597 | drm_gem_object_unreference(&obj->base); | |
598 | } | |
599 | ||
54cf91dc CW |
600 | mutex_unlock(&dev->struct_mutex); |
601 | ||
602 | total = 0; | |
603 | for (i = 0; i < count; i++) | |
432e58ed | 604 | total += exec[i].relocation_count; |
54cf91dc | 605 | |
dd6864a4 | 606 | reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset)); |
54cf91dc | 607 | reloc = drm_malloc_ab(total, sizeof(*reloc)); |
dd6864a4 CW |
608 | if (reloc == NULL || reloc_offset == NULL) { |
609 | drm_free_large(reloc); | |
610 | drm_free_large(reloc_offset); | |
54cf91dc CW |
611 | mutex_lock(&dev->struct_mutex); |
612 | return -ENOMEM; | |
613 | } | |
614 | ||
615 | total = 0; | |
616 | for (i = 0; i < count; i++) { | |
617 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
262b6d36 CW |
618 | u64 invalid_offset = (u64)-1; |
619 | int j; | |
54cf91dc | 620 | |
2bb4629a | 621 | user_relocs = to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
622 | |
623 | if (copy_from_user(reloc+total, user_relocs, | |
432e58ed | 624 | exec[i].relocation_count * sizeof(*reloc))) { |
54cf91dc CW |
625 | ret = -EFAULT; |
626 | mutex_lock(&dev->struct_mutex); | |
627 | goto err; | |
628 | } | |
629 | ||
262b6d36 CW |
630 | /* As we do not update the known relocation offsets after |
631 | * relocating (due to the complexities in lock handling), | |
632 | * we need to mark them as invalid now so that we force the | |
633 | * relocation processing next time. Just in case the target | |
634 | * object is evicted and then rebound into its old | |
635 | * presumed_offset before the next execbuffer - if that | |
636 | * happened we would make the mistake of assuming that the | |
637 | * relocations were valid. | |
638 | */ | |
639 | for (j = 0; j < exec[i].relocation_count; j++) { | |
640 | if (copy_to_user(&user_relocs[j].presumed_offset, | |
641 | &invalid_offset, | |
642 | sizeof(invalid_offset))) { | |
643 | ret = -EFAULT; | |
644 | mutex_lock(&dev->struct_mutex); | |
645 | goto err; | |
646 | } | |
647 | } | |
648 | ||
dd6864a4 | 649 | reloc_offset[i] = total; |
432e58ed | 650 | total += exec[i].relocation_count; |
54cf91dc CW |
651 | } |
652 | ||
653 | ret = i915_mutex_lock_interruptible(dev); | |
654 | if (ret) { | |
655 | mutex_lock(&dev->struct_mutex); | |
656 | goto err; | |
657 | } | |
658 | ||
67731b87 | 659 | /* reacquire the objects */ |
67731b87 | 660 | eb_reset(eb); |
eef90ccb | 661 | ret = eb_lookup_objects(eb, exec, args, file); |
3b96eff4 CW |
662 | if (ret) |
663 | goto err; | |
67731b87 | 664 | |
ed5982e6 DV |
665 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
666 | ret = i915_gem_execbuffer_reserve(ring, file, &eb->objects, &need_relocs); | |
54cf91dc CW |
667 | if (ret) |
668 | goto err; | |
669 | ||
bcffc3fa | 670 | list_for_each_entry(obj, &eb->objects, exec_list) { |
dd6864a4 | 671 | int offset = obj->exec_entry - exec; |
67731b87 | 672 | ret = i915_gem_execbuffer_relocate_object_slow(obj, eb, |
dd6864a4 | 673 | reloc + reloc_offset[offset]); |
54cf91dc CW |
674 | if (ret) |
675 | goto err; | |
54cf91dc CW |
676 | } |
677 | ||
678 | /* Leave the user relocations as are, this is the painfully slow path, | |
679 | * and we want to avoid the complication of dropping the lock whilst | |
680 | * having buffers reserved in the aperture and so causing spurious | |
681 | * ENOSPC for random operations. | |
682 | */ | |
683 | ||
684 | err: | |
685 | drm_free_large(reloc); | |
dd6864a4 | 686 | drm_free_large(reloc_offset); |
54cf91dc CW |
687 | return ret; |
688 | } | |
689 | ||
54cf91dc | 690 | static int |
432e58ed CW |
691 | i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring, |
692 | struct list_head *objects) | |
54cf91dc | 693 | { |
432e58ed | 694 | struct drm_i915_gem_object *obj; |
6ac42f41 | 695 | uint32_t flush_domains = 0; |
432e58ed | 696 | int ret; |
54cf91dc | 697 | |
6ac42f41 DV |
698 | list_for_each_entry(obj, objects, exec_list) { |
699 | ret = i915_gem_object_sync(obj, ring); | |
c59a333f CW |
700 | if (ret) |
701 | return ret; | |
6ac42f41 DV |
702 | |
703 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) | |
704 | i915_gem_clflush_object(obj); | |
705 | ||
6ac42f41 | 706 | flush_domains |= obj->base.write_domain; |
c59a333f CW |
707 | } |
708 | ||
6ac42f41 | 709 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
e76e9aeb | 710 | i915_gem_chipset_flush(ring->dev); |
6ac42f41 DV |
711 | |
712 | if (flush_domains & I915_GEM_DOMAIN_GTT) | |
713 | wmb(); | |
714 | ||
09cf7c9a CW |
715 | /* Unconditionally invalidate gpu caches and ensure that we do flush |
716 | * any residual writes from the previous batch. | |
717 | */ | |
a7b9761d | 718 | return intel_ring_invalidate_all_caches(ring); |
54cf91dc CW |
719 | } |
720 | ||
432e58ed CW |
721 | static bool |
722 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) | |
54cf91dc | 723 | { |
ed5982e6 DV |
724 | if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS) |
725 | return false; | |
726 | ||
432e58ed | 727 | return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0; |
54cf91dc CW |
728 | } |
729 | ||
730 | static int | |
731 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, | |
732 | int count) | |
733 | { | |
734 | int i; | |
735 | ||
736 | for (i = 0; i < count; i++) { | |
2bb4629a | 737 | char __user *ptr = to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
738 | int length; /* limited by fault_in_pages_readable() */ |
739 | ||
ed5982e6 DV |
740 | if (exec[i].flags & __EXEC_OBJECT_UNKNOWN_FLAGS) |
741 | return -EINVAL; | |
742 | ||
54cf91dc CW |
743 | /* First check for malicious input causing overflow */ |
744 | if (exec[i].relocation_count > | |
745 | INT_MAX / sizeof(struct drm_i915_gem_relocation_entry)) | |
746 | return -EINVAL; | |
747 | ||
748 | length = exec[i].relocation_count * | |
749 | sizeof(struct drm_i915_gem_relocation_entry); | |
54cf91dc CW |
750 | /* we may also need to update the presumed offsets */ |
751 | if (!access_ok(VERIFY_WRITE, ptr, length)) | |
752 | return -EFAULT; | |
753 | ||
f56f821f | 754 | if (fault_in_multipages_readable(ptr, length)) |
54cf91dc CW |
755 | return -EFAULT; |
756 | } | |
757 | ||
758 | return 0; | |
759 | } | |
760 | ||
432e58ed CW |
761 | static void |
762 | i915_gem_execbuffer_move_to_active(struct list_head *objects, | |
9d773091 | 763 | struct intel_ring_buffer *ring) |
432e58ed CW |
764 | { |
765 | struct drm_i915_gem_object *obj; | |
766 | ||
767 | list_for_each_entry(obj, objects, exec_list) { | |
69c2fc89 CW |
768 | u32 old_read = obj->base.read_domains; |
769 | u32 old_write = obj->base.write_domain; | |
db53a302 | 770 | |
432e58ed | 771 | obj->base.write_domain = obj->base.pending_write_domain; |
ed5982e6 DV |
772 | if (obj->base.write_domain == 0) |
773 | obj->base.pending_read_domains |= obj->base.read_domains; | |
774 | obj->base.read_domains = obj->base.pending_read_domains; | |
432e58ed CW |
775 | obj->fenced_gpu_access = obj->pending_fenced_gpu_access; |
776 | ||
9d773091 | 777 | i915_gem_object_move_to_active(obj, ring); |
432e58ed CW |
778 | if (obj->base.write_domain) { |
779 | obj->dirty = 1; | |
9d773091 | 780 | obj->last_write_seqno = intel_ring_get_seqno(ring); |
acb87dfb | 781 | if (obj->pin_count) /* check for potential scanout */ |
f047e395 | 782 | intel_mark_fb_busy(obj); |
432e58ed CW |
783 | } |
784 | ||
db53a302 | 785 | trace_i915_gem_object_change_domain(obj, old_read, old_write); |
432e58ed CW |
786 | } |
787 | } | |
788 | ||
54cf91dc CW |
789 | static void |
790 | i915_gem_execbuffer_retire_commands(struct drm_device *dev, | |
432e58ed | 791 | struct drm_file *file, |
54cf91dc CW |
792 | struct intel_ring_buffer *ring) |
793 | { | |
cc889e0f DV |
794 | /* Unconditionally force add_request to emit a full flush. */ |
795 | ring->gpu_caches_dirty = true; | |
54cf91dc | 796 | |
432e58ed | 797 | /* Add a breadcrumb for the completion of the batch buffer */ |
3bb73aba | 798 | (void)i915_add_request(ring, file, NULL); |
432e58ed | 799 | } |
54cf91dc | 800 | |
ae662d31 EA |
801 | static int |
802 | i915_reset_gen7_sol_offsets(struct drm_device *dev, | |
803 | struct intel_ring_buffer *ring) | |
804 | { | |
805 | drm_i915_private_t *dev_priv = dev->dev_private; | |
806 | int ret, i; | |
807 | ||
808 | if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) | |
809 | return 0; | |
810 | ||
811 | ret = intel_ring_begin(ring, 4 * 3); | |
812 | if (ret) | |
813 | return ret; | |
814 | ||
815 | for (i = 0; i < 4; i++) { | |
816 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
817 | intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i)); | |
818 | intel_ring_emit(ring, 0); | |
819 | } | |
820 | ||
821 | intel_ring_advance(ring); | |
822 | ||
823 | return 0; | |
824 | } | |
825 | ||
54cf91dc CW |
826 | static int |
827 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, | |
828 | struct drm_file *file, | |
829 | struct drm_i915_gem_execbuffer2 *args, | |
432e58ed | 830 | struct drm_i915_gem_exec_object2 *exec) |
54cf91dc CW |
831 | { |
832 | drm_i915_private_t *dev_priv = dev->dev_private; | |
67731b87 | 833 | struct eb_objects *eb; |
54cf91dc CW |
834 | struct drm_i915_gem_object *batch_obj; |
835 | struct drm_clip_rect *cliprects = NULL; | |
54cf91dc | 836 | struct intel_ring_buffer *ring; |
6e0a69db | 837 | u32 ctx_id = i915_execbuffer2_get_context_id(*args); |
c4e7a414 | 838 | u32 exec_start, exec_len; |
ed5982e6 | 839 | u32 mask, flags; |
72bfa19c | 840 | int ret, mode, i; |
ed5982e6 | 841 | bool need_relocs; |
54cf91dc | 842 | |
ed5982e6 | 843 | if (!i915_gem_check_execbuffer(args)) |
432e58ed | 844 | return -EINVAL; |
432e58ed CW |
845 | |
846 | ret = validate_exec_list(exec, args->buffer_count); | |
54cf91dc CW |
847 | if (ret) |
848 | return ret; | |
849 | ||
d7d4eedd CW |
850 | flags = 0; |
851 | if (args->flags & I915_EXEC_SECURE) { | |
852 | if (!file->is_master || !capable(CAP_SYS_ADMIN)) | |
853 | return -EPERM; | |
854 | ||
855 | flags |= I915_DISPATCH_SECURE; | |
856 | } | |
b45305fc DV |
857 | if (args->flags & I915_EXEC_IS_PINNED) |
858 | flags |= I915_DISPATCH_PINNED; | |
d7d4eedd | 859 | |
54cf91dc CW |
860 | switch (args->flags & I915_EXEC_RING_MASK) { |
861 | case I915_EXEC_DEFAULT: | |
862 | case I915_EXEC_RENDER: | |
1ec14ad3 | 863 | ring = &dev_priv->ring[RCS]; |
54cf91dc CW |
864 | break; |
865 | case I915_EXEC_BSD: | |
1ec14ad3 | 866 | ring = &dev_priv->ring[VCS]; |
6e0a69db BW |
867 | if (ctx_id != 0) { |
868 | DRM_DEBUG("Ring %s doesn't support contexts\n", | |
869 | ring->name); | |
870 | return -EPERM; | |
871 | } | |
54cf91dc CW |
872 | break; |
873 | case I915_EXEC_BLT: | |
1ec14ad3 | 874 | ring = &dev_priv->ring[BCS]; |
6e0a69db BW |
875 | if (ctx_id != 0) { |
876 | DRM_DEBUG("Ring %s doesn't support contexts\n", | |
877 | ring->name); | |
878 | return -EPERM; | |
879 | } | |
54cf91dc CW |
880 | break; |
881 | default: | |
ff240199 | 882 | DRM_DEBUG("execbuf with unknown ring: %d\n", |
54cf91dc CW |
883 | (int)(args->flags & I915_EXEC_RING_MASK)); |
884 | return -EINVAL; | |
885 | } | |
a15817cf CW |
886 | if (!intel_ring_initialized(ring)) { |
887 | DRM_DEBUG("execbuf with invalid ring: %d\n", | |
888 | (int)(args->flags & I915_EXEC_RING_MASK)); | |
889 | return -EINVAL; | |
890 | } | |
54cf91dc | 891 | |
72bfa19c | 892 | mode = args->flags & I915_EXEC_CONSTANTS_MASK; |
84f9f938 | 893 | mask = I915_EXEC_CONSTANTS_MASK; |
72bfa19c CW |
894 | switch (mode) { |
895 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
896 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
897 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
898 | if (ring == &dev_priv->ring[RCS] && | |
899 | mode != dev_priv->relative_constants_mode) { | |
900 | if (INTEL_INFO(dev)->gen < 4) | |
901 | return -EINVAL; | |
902 | ||
903 | if (INTEL_INFO(dev)->gen > 5 && | |
904 | mode == I915_EXEC_CONSTANTS_REL_SURFACE) | |
905 | return -EINVAL; | |
84f9f938 BW |
906 | |
907 | /* The HW changed the meaning on this bit on gen6 */ | |
908 | if (INTEL_INFO(dev)->gen >= 6) | |
909 | mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
72bfa19c CW |
910 | } |
911 | break; | |
912 | default: | |
ff240199 | 913 | DRM_DEBUG("execbuf with unknown constants: %d\n", mode); |
72bfa19c CW |
914 | return -EINVAL; |
915 | } | |
916 | ||
54cf91dc | 917 | if (args->buffer_count < 1) { |
ff240199 | 918 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
919 | return -EINVAL; |
920 | } | |
54cf91dc CW |
921 | |
922 | if (args->num_cliprects != 0) { | |
1ec14ad3 | 923 | if (ring != &dev_priv->ring[RCS]) { |
ff240199 | 924 | DRM_DEBUG("clip rectangles are only valid with the render ring\n"); |
c4e7a414 CW |
925 | return -EINVAL; |
926 | } | |
927 | ||
6ebebc92 DV |
928 | if (INTEL_INFO(dev)->gen >= 5) { |
929 | DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); | |
930 | return -EINVAL; | |
931 | } | |
932 | ||
44afb3a0 XW |
933 | if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) { |
934 | DRM_DEBUG("execbuf with %u cliprects\n", | |
935 | args->num_cliprects); | |
936 | return -EINVAL; | |
937 | } | |
5e13a0c5 | 938 | |
432e58ed | 939 | cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects), |
54cf91dc CW |
940 | GFP_KERNEL); |
941 | if (cliprects == NULL) { | |
942 | ret = -ENOMEM; | |
943 | goto pre_mutex_err; | |
944 | } | |
945 | ||
432e58ed | 946 | if (copy_from_user(cliprects, |
2bb4629a VS |
947 | to_user_ptr(args->cliprects_ptr), |
948 | sizeof(*cliprects)*args->num_cliprects)) { | |
54cf91dc CW |
949 | ret = -EFAULT; |
950 | goto pre_mutex_err; | |
951 | } | |
952 | } | |
953 | ||
54cf91dc CW |
954 | ret = i915_mutex_lock_interruptible(dev); |
955 | if (ret) | |
956 | goto pre_mutex_err; | |
957 | ||
958 | if (dev_priv->mm.suspended) { | |
959 | mutex_unlock(&dev->struct_mutex); | |
960 | ret = -EBUSY; | |
961 | goto pre_mutex_err; | |
962 | } | |
963 | ||
eef90ccb | 964 | eb = eb_create(args); |
67731b87 CW |
965 | if (eb == NULL) { |
966 | mutex_unlock(&dev->struct_mutex); | |
967 | ret = -ENOMEM; | |
968 | goto pre_mutex_err; | |
969 | } | |
970 | ||
54cf91dc | 971 | /* Look up object handles */ |
eef90ccb | 972 | ret = eb_lookup_objects(eb, exec, args, file); |
3b96eff4 CW |
973 | if (ret) |
974 | goto err; | |
54cf91dc | 975 | |
6fe4f140 | 976 | /* take note of the batch buffer before we might reorder the lists */ |
bcffc3fa | 977 | batch_obj = list_entry(eb->objects.prev, |
6fe4f140 CW |
978 | struct drm_i915_gem_object, |
979 | exec_list); | |
980 | ||
54cf91dc | 981 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
ed5982e6 DV |
982 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
983 | ret = i915_gem_execbuffer_reserve(ring, file, &eb->objects, &need_relocs); | |
54cf91dc CW |
984 | if (ret) |
985 | goto err; | |
986 | ||
987 | /* The objects are in their final locations, apply the relocations. */ | |
ed5982e6 DV |
988 | if (need_relocs) |
989 | ret = i915_gem_execbuffer_relocate(dev, eb); | |
54cf91dc CW |
990 | if (ret) { |
991 | if (ret == -EFAULT) { | |
ed5982e6 DV |
992 | ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring, |
993 | eb, exec); | |
54cf91dc CW |
994 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
995 | } | |
996 | if (ret) | |
997 | goto err; | |
998 | } | |
999 | ||
1000 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
54cf91dc | 1001 | if (batch_obj->base.pending_write_domain) { |
ff240199 | 1002 | DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); |
54cf91dc CW |
1003 | ret = -EINVAL; |
1004 | goto err; | |
1005 | } | |
1006 | batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
1007 | ||
d7d4eedd CW |
1008 | /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure |
1009 | * batch" bit. Hence we need to pin secure batches into the global gtt. | |
1010 | * hsw should have this fixed, but let's be paranoid and do it | |
1011 | * unconditionally for now. */ | |
1012 | if (flags & I915_DISPATCH_SECURE && !batch_obj->has_global_gtt_mapping) | |
1013 | i915_gem_gtt_bind_object(batch_obj, batch_obj->cache_level); | |
1014 | ||
bcffc3fa | 1015 | ret = i915_gem_execbuffer_move_to_gpu(ring, &eb->objects); |
432e58ed | 1016 | if (ret) |
54cf91dc | 1017 | goto err; |
54cf91dc | 1018 | |
0da5cec1 EA |
1019 | ret = i915_switch_context(ring, file, ctx_id); |
1020 | if (ret) | |
1021 | goto err; | |
1022 | ||
e2971bda BW |
1023 | if (ring == &dev_priv->ring[RCS] && |
1024 | mode != dev_priv->relative_constants_mode) { | |
1025 | ret = intel_ring_begin(ring, 4); | |
1026 | if (ret) | |
1027 | goto err; | |
1028 | ||
1029 | intel_ring_emit(ring, MI_NOOP); | |
1030 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
1031 | intel_ring_emit(ring, INSTPM); | |
84f9f938 | 1032 | intel_ring_emit(ring, mask << 16 | mode); |
e2971bda BW |
1033 | intel_ring_advance(ring); |
1034 | ||
1035 | dev_priv->relative_constants_mode = mode; | |
1036 | } | |
1037 | ||
ae662d31 EA |
1038 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { |
1039 | ret = i915_reset_gen7_sol_offsets(dev, ring); | |
1040 | if (ret) | |
1041 | goto err; | |
1042 | } | |
1043 | ||
c4e7a414 CW |
1044 | exec_start = batch_obj->gtt_offset + args->batch_start_offset; |
1045 | exec_len = args->batch_len; | |
1046 | if (cliprects) { | |
1047 | for (i = 0; i < args->num_cliprects; i++) { | |
1048 | ret = i915_emit_box(dev, &cliprects[i], | |
1049 | args->DR1, args->DR4); | |
1050 | if (ret) | |
1051 | goto err; | |
1052 | ||
1053 | ret = ring->dispatch_execbuffer(ring, | |
d7d4eedd CW |
1054 | exec_start, exec_len, |
1055 | flags); | |
c4e7a414 CW |
1056 | if (ret) |
1057 | goto err; | |
1058 | } | |
1059 | } else { | |
d7d4eedd CW |
1060 | ret = ring->dispatch_execbuffer(ring, |
1061 | exec_start, exec_len, | |
1062 | flags); | |
c4e7a414 CW |
1063 | if (ret) |
1064 | goto err; | |
1065 | } | |
54cf91dc | 1066 | |
9d773091 CW |
1067 | trace_i915_gem_ring_dispatch(ring, intel_ring_get_seqno(ring), flags); |
1068 | ||
bcffc3fa | 1069 | i915_gem_execbuffer_move_to_active(&eb->objects, ring); |
432e58ed | 1070 | i915_gem_execbuffer_retire_commands(dev, file, ring); |
54cf91dc CW |
1071 | |
1072 | err: | |
67731b87 | 1073 | eb_destroy(eb); |
54cf91dc CW |
1074 | |
1075 | mutex_unlock(&dev->struct_mutex); | |
1076 | ||
1077 | pre_mutex_err: | |
54cf91dc | 1078 | kfree(cliprects); |
54cf91dc CW |
1079 | return ret; |
1080 | } | |
1081 | ||
1082 | /* | |
1083 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
1084 | * list array and passes it to the real function. | |
1085 | */ | |
1086 | int | |
1087 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1088 | struct drm_file *file) | |
1089 | { | |
1090 | struct drm_i915_gem_execbuffer *args = data; | |
1091 | struct drm_i915_gem_execbuffer2 exec2; | |
1092 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
1093 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1094 | int ret, i; | |
1095 | ||
54cf91dc | 1096 | if (args->buffer_count < 1) { |
ff240199 | 1097 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1098 | return -EINVAL; |
1099 | } | |
1100 | ||
1101 | /* Copy in the exec list from userland */ | |
1102 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
1103 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
1104 | if (exec_list == NULL || exec2_list == NULL) { | |
ff240199 | 1105 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1106 | args->buffer_count); |
1107 | drm_free_large(exec_list); | |
1108 | drm_free_large(exec2_list); | |
1109 | return -ENOMEM; | |
1110 | } | |
1111 | ret = copy_from_user(exec_list, | |
2bb4629a | 1112 | to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1113 | sizeof(*exec_list) * args->buffer_count); |
1114 | if (ret != 0) { | |
ff240199 | 1115 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1116 | args->buffer_count, ret); |
1117 | drm_free_large(exec_list); | |
1118 | drm_free_large(exec2_list); | |
1119 | return -EFAULT; | |
1120 | } | |
1121 | ||
1122 | for (i = 0; i < args->buffer_count; i++) { | |
1123 | exec2_list[i].handle = exec_list[i].handle; | |
1124 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
1125 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
1126 | exec2_list[i].alignment = exec_list[i].alignment; | |
1127 | exec2_list[i].offset = exec_list[i].offset; | |
1128 | if (INTEL_INFO(dev)->gen < 4) | |
1129 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; | |
1130 | else | |
1131 | exec2_list[i].flags = 0; | |
1132 | } | |
1133 | ||
1134 | exec2.buffers_ptr = args->buffers_ptr; | |
1135 | exec2.buffer_count = args->buffer_count; | |
1136 | exec2.batch_start_offset = args->batch_start_offset; | |
1137 | exec2.batch_len = args->batch_len; | |
1138 | exec2.DR1 = args->DR1; | |
1139 | exec2.DR4 = args->DR4; | |
1140 | exec2.num_cliprects = args->num_cliprects; | |
1141 | exec2.cliprects_ptr = args->cliprects_ptr; | |
1142 | exec2.flags = I915_EXEC_RENDER; | |
6e0a69db | 1143 | i915_execbuffer2_set_context_id(exec2, 0); |
54cf91dc CW |
1144 | |
1145 | ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list); | |
1146 | if (!ret) { | |
1147 | /* Copy the new buffer offsets back to the user's exec list. */ | |
1148 | for (i = 0; i < args->buffer_count; i++) | |
1149 | exec_list[i].offset = exec2_list[i].offset; | |
1150 | /* ... and back out to userspace */ | |
2bb4629a | 1151 | ret = copy_to_user(to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1152 | exec_list, |
1153 | sizeof(*exec_list) * args->buffer_count); | |
1154 | if (ret) { | |
1155 | ret = -EFAULT; | |
ff240199 | 1156 | DRM_DEBUG("failed to copy %d exec entries " |
54cf91dc CW |
1157 | "back to user (%d)\n", |
1158 | args->buffer_count, ret); | |
1159 | } | |
1160 | } | |
1161 | ||
1162 | drm_free_large(exec_list); | |
1163 | drm_free_large(exec2_list); | |
1164 | return ret; | |
1165 | } | |
1166 | ||
1167 | int | |
1168 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
1169 | struct drm_file *file) | |
1170 | { | |
1171 | struct drm_i915_gem_execbuffer2 *args = data; | |
1172 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1173 | int ret; | |
1174 | ||
ed8cd3b2 XW |
1175 | if (args->buffer_count < 1 || |
1176 | args->buffer_count > UINT_MAX / sizeof(*exec2_list)) { | |
ff240199 | 1177 | DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1178 | return -EINVAL; |
1179 | } | |
1180 | ||
8408c282 | 1181 | exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count, |
419fa72a | 1182 | GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); |
8408c282 CW |
1183 | if (exec2_list == NULL) |
1184 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), | |
1185 | args->buffer_count); | |
54cf91dc | 1186 | if (exec2_list == NULL) { |
ff240199 | 1187 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1188 | args->buffer_count); |
1189 | return -ENOMEM; | |
1190 | } | |
1191 | ret = copy_from_user(exec2_list, | |
2bb4629a | 1192 | to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1193 | sizeof(*exec2_list) * args->buffer_count); |
1194 | if (ret != 0) { | |
ff240199 | 1195 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1196 | args->buffer_count, ret); |
1197 | drm_free_large(exec2_list); | |
1198 | return -EFAULT; | |
1199 | } | |
1200 | ||
1201 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list); | |
1202 | if (!ret) { | |
1203 | /* Copy the new buffer offsets back to the user's exec list. */ | |
2bb4629a | 1204 | ret = copy_to_user(to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1205 | exec2_list, |
1206 | sizeof(*exec2_list) * args->buffer_count); | |
1207 | if (ret) { | |
1208 | ret = -EFAULT; | |
ff240199 | 1209 | DRM_DEBUG("failed to copy %d exec entries " |
54cf91dc CW |
1210 | "back to user (%d)\n", |
1211 | args->buffer_count, ret); | |
1212 | } | |
1213 | } | |
1214 | ||
1215 | drm_free_large(exec2_list); | |
1216 | return ret; | |
1217 | } |