Commit | Line | Data |
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54cf91dc CW |
1 | /* |
2 | * Copyright © 2008,2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Chris Wilson <chris@chris-wilson.co.uk> | |
26 | * | |
27 | */ | |
28 | ||
760285e7 DH |
29 | #include <drm/drmP.h> |
30 | #include <drm/i915_drm.h> | |
54cf91dc CW |
31 | #include "i915_drv.h" |
32 | #include "i915_trace.h" | |
33 | #include "intel_drv.h" | |
f45b5557 | 34 | #include <linux/dma_remapping.h> |
54cf91dc | 35 | |
a415d355 CW |
36 | #define __EXEC_OBJECT_HAS_PIN (1<<31) |
37 | #define __EXEC_OBJECT_HAS_FENCE (1<<30) | |
38 | ||
27173f1f BW |
39 | struct eb_vmas { |
40 | struct list_head vmas; | |
67731b87 | 41 | int and; |
eef90ccb | 42 | union { |
27173f1f | 43 | struct i915_vma *lut[0]; |
eef90ccb CW |
44 | struct hlist_head buckets[0]; |
45 | }; | |
67731b87 CW |
46 | }; |
47 | ||
27173f1f | 48 | static struct eb_vmas * |
17601cbc | 49 | eb_create(struct drm_i915_gem_execbuffer2 *args) |
67731b87 | 50 | { |
27173f1f | 51 | struct eb_vmas *eb = NULL; |
eef90ccb CW |
52 | |
53 | if (args->flags & I915_EXEC_HANDLE_LUT) { | |
b205ca57 | 54 | unsigned size = args->buffer_count; |
27173f1f BW |
55 | size *= sizeof(struct i915_vma *); |
56 | size += sizeof(struct eb_vmas); | |
eef90ccb CW |
57 | eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); |
58 | } | |
59 | ||
60 | if (eb == NULL) { | |
b205ca57 DV |
61 | unsigned size = args->buffer_count; |
62 | unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2; | |
27b7c63a | 63 | BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head)); |
eef90ccb CW |
64 | while (count > 2*size) |
65 | count >>= 1; | |
66 | eb = kzalloc(count*sizeof(struct hlist_head) + | |
27173f1f | 67 | sizeof(struct eb_vmas), |
eef90ccb CW |
68 | GFP_TEMPORARY); |
69 | if (eb == NULL) | |
70 | return eb; | |
71 | ||
72 | eb->and = count - 1; | |
73 | } else | |
74 | eb->and = -args->buffer_count; | |
75 | ||
27173f1f | 76 | INIT_LIST_HEAD(&eb->vmas); |
67731b87 CW |
77 | return eb; |
78 | } | |
79 | ||
80 | static void | |
27173f1f | 81 | eb_reset(struct eb_vmas *eb) |
67731b87 | 82 | { |
eef90ccb CW |
83 | if (eb->and >= 0) |
84 | memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head)); | |
67731b87 CW |
85 | } |
86 | ||
3b96eff4 | 87 | static int |
27173f1f BW |
88 | eb_lookup_vmas(struct eb_vmas *eb, |
89 | struct drm_i915_gem_exec_object2 *exec, | |
90 | const struct drm_i915_gem_execbuffer2 *args, | |
91 | struct i915_address_space *vm, | |
92 | struct drm_file *file) | |
3b96eff4 | 93 | { |
6f65e29a | 94 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
27173f1f BW |
95 | struct drm_i915_gem_object *obj; |
96 | struct list_head objects; | |
97 | int i, ret = 0; | |
3b96eff4 | 98 | |
27173f1f | 99 | INIT_LIST_HEAD(&objects); |
3b96eff4 | 100 | spin_lock(&file->table_lock); |
27173f1f BW |
101 | /* Grab a reference to the object and release the lock so we can lookup |
102 | * or create the VMA without using GFP_ATOMIC */ | |
eef90ccb | 103 | for (i = 0; i < args->buffer_count; i++) { |
3b96eff4 CW |
104 | obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle)); |
105 | if (obj == NULL) { | |
106 | spin_unlock(&file->table_lock); | |
107 | DRM_DEBUG("Invalid object handle %d at index %d\n", | |
108 | exec[i].handle, i); | |
27173f1f BW |
109 | ret = -ENOENT; |
110 | goto out; | |
3b96eff4 CW |
111 | } |
112 | ||
27173f1f | 113 | if (!list_empty(&obj->obj_exec_link)) { |
3b96eff4 CW |
114 | spin_unlock(&file->table_lock); |
115 | DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n", | |
116 | obj, exec[i].handle, i); | |
27173f1f BW |
117 | ret = -EINVAL; |
118 | goto out; | |
3b96eff4 CW |
119 | } |
120 | ||
121 | drm_gem_object_reference(&obj->base); | |
27173f1f BW |
122 | list_add_tail(&obj->obj_exec_link, &objects); |
123 | } | |
124 | spin_unlock(&file->table_lock); | |
3b96eff4 | 125 | |
27173f1f BW |
126 | i = 0; |
127 | list_for_each_entry(obj, &objects, obj_exec_link) { | |
128 | struct i915_vma *vma; | |
6f65e29a BW |
129 | struct i915_address_space *bind_vm = vm; |
130 | ||
131 | /* If we have secure dispatch, or the userspace assures us that | |
132 | * they know what they're doing, use the GGTT VM. | |
133 | */ | |
134 | if (exec[i].flags & EXEC_OBJECT_NEEDS_GTT || | |
135 | ((args->flags & I915_EXEC_SECURE) && | |
136 | (i == (args->buffer_count - 1)))) | |
137 | bind_vm = &dev_priv->gtt.base; | |
27173f1f | 138 | |
e656a6cb DV |
139 | /* |
140 | * NOTE: We can leak any vmas created here when something fails | |
141 | * later on. But that's no issue since vma_unbind can deal with | |
142 | * vmas which are not actually bound. And since only | |
143 | * lookup_or_create exists as an interface to get at the vma | |
144 | * from the (obj, vm) we don't run the risk of creating | |
145 | * duplicated vmas for the same vm. | |
146 | */ | |
6f65e29a | 147 | vma = i915_gem_obj_lookup_or_create_vma(obj, bind_vm); |
27173f1f | 148 | if (IS_ERR(vma)) { |
27173f1f BW |
149 | DRM_DEBUG("Failed to lookup VMA\n"); |
150 | ret = PTR_ERR(vma); | |
151 | goto out; | |
152 | } | |
153 | ||
154 | list_add_tail(&vma->exec_list, &eb->vmas); | |
155 | ||
156 | vma->exec_entry = &exec[i]; | |
eef90ccb | 157 | if (eb->and < 0) { |
27173f1f | 158 | eb->lut[i] = vma; |
eef90ccb CW |
159 | } else { |
160 | uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle; | |
27173f1f BW |
161 | vma->exec_handle = handle; |
162 | hlist_add_head(&vma->exec_node, | |
eef90ccb CW |
163 | &eb->buckets[handle & eb->and]); |
164 | } | |
27173f1f | 165 | ++i; |
3b96eff4 | 166 | } |
3b96eff4 | 167 | |
27173f1f BW |
168 | |
169 | out: | |
170 | while (!list_empty(&objects)) { | |
171 | obj = list_first_entry(&objects, | |
172 | struct drm_i915_gem_object, | |
173 | obj_exec_link); | |
174 | list_del_init(&obj->obj_exec_link); | |
175 | if (ret) | |
176 | drm_gem_object_unreference(&obj->base); | |
177 | } | |
178 | return ret; | |
3b96eff4 CW |
179 | } |
180 | ||
27173f1f | 181 | static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle) |
67731b87 | 182 | { |
eef90ccb CW |
183 | if (eb->and < 0) { |
184 | if (handle >= -eb->and) | |
185 | return NULL; | |
186 | return eb->lut[handle]; | |
187 | } else { | |
188 | struct hlist_head *head; | |
189 | struct hlist_node *node; | |
67731b87 | 190 | |
eef90ccb CW |
191 | head = &eb->buckets[handle & eb->and]; |
192 | hlist_for_each(node, head) { | |
27173f1f | 193 | struct i915_vma *vma; |
67731b87 | 194 | |
27173f1f BW |
195 | vma = hlist_entry(node, struct i915_vma, exec_node); |
196 | if (vma->exec_handle == handle) | |
197 | return vma; | |
eef90ccb CW |
198 | } |
199 | return NULL; | |
200 | } | |
67731b87 CW |
201 | } |
202 | ||
a415d355 CW |
203 | static void |
204 | i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma) | |
205 | { | |
206 | struct drm_i915_gem_exec_object2 *entry; | |
207 | struct drm_i915_gem_object *obj = vma->obj; | |
208 | ||
209 | if (!drm_mm_node_allocated(&vma->node)) | |
210 | return; | |
211 | ||
212 | entry = vma->exec_entry; | |
213 | ||
214 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) | |
215 | i915_gem_object_unpin_fence(obj); | |
216 | ||
217 | if (entry->flags & __EXEC_OBJECT_HAS_PIN) | |
3d7f0f9d | 218 | vma->pin_count--; |
a415d355 CW |
219 | |
220 | entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN); | |
221 | } | |
222 | ||
223 | static void eb_destroy(struct eb_vmas *eb) | |
224 | { | |
27173f1f BW |
225 | while (!list_empty(&eb->vmas)) { |
226 | struct i915_vma *vma; | |
bcffc3fa | 227 | |
27173f1f BW |
228 | vma = list_first_entry(&eb->vmas, |
229 | struct i915_vma, | |
bcffc3fa | 230 | exec_list); |
27173f1f | 231 | list_del_init(&vma->exec_list); |
a415d355 | 232 | i915_gem_execbuffer_unreserve_vma(vma); |
27173f1f | 233 | drm_gem_object_unreference(&vma->obj->base); |
bcffc3fa | 234 | } |
67731b87 CW |
235 | kfree(eb); |
236 | } | |
237 | ||
dabdfe02 CW |
238 | static inline int use_cpu_reloc(struct drm_i915_gem_object *obj) |
239 | { | |
2cc86b82 CW |
240 | return (HAS_LLC(obj->base.dev) || |
241 | obj->base.write_domain == I915_GEM_DOMAIN_CPU || | |
504c7267 | 242 | !obj->map_and_fenceable || |
dabdfe02 CW |
243 | obj->cache_level != I915_CACHE_NONE); |
244 | } | |
245 | ||
5032d871 RB |
246 | static int |
247 | relocate_entry_cpu(struct drm_i915_gem_object *obj, | |
248 | struct drm_i915_gem_relocation_entry *reloc) | |
249 | { | |
3c94ceee | 250 | struct drm_device *dev = obj->base.dev; |
5032d871 RB |
251 | uint32_t page_offset = offset_in_page(reloc->offset); |
252 | char *vaddr; | |
253 | int ret = -EINVAL; | |
254 | ||
2cc86b82 | 255 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
5032d871 RB |
256 | if (ret) |
257 | return ret; | |
258 | ||
259 | vaddr = kmap_atomic(i915_gem_object_get_page(obj, | |
260 | reloc->offset >> PAGE_SHIFT)); | |
261 | *(uint32_t *)(vaddr + page_offset) = reloc->delta; | |
3c94ceee BW |
262 | |
263 | if (INTEL_INFO(dev)->gen >= 8) { | |
264 | page_offset = offset_in_page(page_offset + sizeof(uint32_t)); | |
265 | ||
266 | if (page_offset == 0) { | |
267 | kunmap_atomic(vaddr); | |
268 | vaddr = kmap_atomic(i915_gem_object_get_page(obj, | |
269 | (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT)); | |
270 | } | |
271 | ||
272 | *(uint32_t *)(vaddr + page_offset) = 0; | |
273 | } | |
274 | ||
5032d871 RB |
275 | kunmap_atomic(vaddr); |
276 | ||
277 | return 0; | |
278 | } | |
279 | ||
280 | static int | |
281 | relocate_entry_gtt(struct drm_i915_gem_object *obj, | |
282 | struct drm_i915_gem_relocation_entry *reloc) | |
283 | { | |
284 | struct drm_device *dev = obj->base.dev; | |
285 | struct drm_i915_private *dev_priv = dev->dev_private; | |
286 | uint32_t __iomem *reloc_entry; | |
287 | void __iomem *reloc_page; | |
288 | int ret = -EINVAL; | |
289 | ||
290 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
291 | if (ret) | |
292 | return ret; | |
293 | ||
294 | ret = i915_gem_object_put_fence(obj); | |
295 | if (ret) | |
296 | return ret; | |
297 | ||
298 | /* Map the page containing the relocation we're going to perform. */ | |
299 | reloc->offset += i915_gem_obj_ggtt_offset(obj); | |
300 | reloc_page = io_mapping_map_atomic_wc(dev_priv->gtt.mappable, | |
301 | reloc->offset & PAGE_MASK); | |
302 | reloc_entry = (uint32_t __iomem *) | |
303 | (reloc_page + offset_in_page(reloc->offset)); | |
304 | iowrite32(reloc->delta, reloc_entry); | |
3c94ceee BW |
305 | |
306 | if (INTEL_INFO(dev)->gen >= 8) { | |
307 | reloc_entry += 1; | |
308 | ||
309 | if (offset_in_page(reloc->offset + sizeof(uint32_t)) == 0) { | |
310 | io_mapping_unmap_atomic(reloc_page); | |
311 | reloc_page = io_mapping_map_atomic_wc( | |
312 | dev_priv->gtt.mappable, | |
313 | reloc->offset + sizeof(uint32_t)); | |
314 | reloc_entry = reloc_page; | |
315 | } | |
316 | ||
317 | iowrite32(0, reloc_entry); | |
318 | } | |
319 | ||
5032d871 RB |
320 | io_mapping_unmap_atomic(reloc_page); |
321 | ||
322 | return 0; | |
323 | } | |
324 | ||
54cf91dc CW |
325 | static int |
326 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, | |
27173f1f | 327 | struct eb_vmas *eb, |
3e7a0322 | 328 | struct drm_i915_gem_relocation_entry *reloc) |
54cf91dc CW |
329 | { |
330 | struct drm_device *dev = obj->base.dev; | |
331 | struct drm_gem_object *target_obj; | |
149c8407 | 332 | struct drm_i915_gem_object *target_i915_obj; |
27173f1f | 333 | struct i915_vma *target_vma; |
54cf91dc CW |
334 | uint32_t target_offset; |
335 | int ret = -EINVAL; | |
336 | ||
67731b87 | 337 | /* we've already hold a reference to all valid objects */ |
27173f1f BW |
338 | target_vma = eb_get_vma(eb, reloc->target_handle); |
339 | if (unlikely(target_vma == NULL)) | |
54cf91dc | 340 | return -ENOENT; |
27173f1f BW |
341 | target_i915_obj = target_vma->obj; |
342 | target_obj = &target_vma->obj->base; | |
54cf91dc | 343 | |
5ce09725 | 344 | target_offset = target_vma->node.start; |
54cf91dc | 345 | |
e844b990 EA |
346 | /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and |
347 | * pipe_control writes because the gpu doesn't properly redirect them | |
348 | * through the ppgtt for non_secure batchbuffers. */ | |
349 | if (unlikely(IS_GEN6(dev) && | |
350 | reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION && | |
351 | !target_i915_obj->has_global_gtt_mapping)) { | |
3e7a0322 BW |
352 | struct i915_vma *vma = |
353 | list_first_entry(&target_i915_obj->vma_list, | |
354 | typeof(*vma), vma_link); | |
6f65e29a | 355 | vma->bind_vma(vma, target_i915_obj->cache_level, GLOBAL_BIND); |
e844b990 EA |
356 | } |
357 | ||
54cf91dc | 358 | /* Validate that the target is in a valid r/w GPU domain */ |
b8f7ab17 | 359 | if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { |
ff240199 | 360 | DRM_DEBUG("reloc with multiple write domains: " |
54cf91dc CW |
361 | "obj %p target %d offset %d " |
362 | "read %08x write %08x", | |
363 | obj, reloc->target_handle, | |
364 | (int) reloc->offset, | |
365 | reloc->read_domains, | |
366 | reloc->write_domain); | |
67731b87 | 367 | return ret; |
54cf91dc | 368 | } |
4ca4a250 DV |
369 | if (unlikely((reloc->write_domain | reloc->read_domains) |
370 | & ~I915_GEM_GPU_DOMAINS)) { | |
ff240199 | 371 | DRM_DEBUG("reloc with read/write non-GPU domains: " |
54cf91dc CW |
372 | "obj %p target %d offset %d " |
373 | "read %08x write %08x", | |
374 | obj, reloc->target_handle, | |
375 | (int) reloc->offset, | |
376 | reloc->read_domains, | |
377 | reloc->write_domain); | |
67731b87 | 378 | return ret; |
54cf91dc | 379 | } |
54cf91dc CW |
380 | |
381 | target_obj->pending_read_domains |= reloc->read_domains; | |
382 | target_obj->pending_write_domain |= reloc->write_domain; | |
383 | ||
384 | /* If the relocation already has the right value in it, no | |
385 | * more work needs to be done. | |
386 | */ | |
387 | if (target_offset == reloc->presumed_offset) | |
67731b87 | 388 | return 0; |
54cf91dc CW |
389 | |
390 | /* Check that the relocation address is valid... */ | |
3c94ceee BW |
391 | if (unlikely(reloc->offset > |
392 | obj->base.size - (INTEL_INFO(dev)->gen >= 8 ? 8 : 4))) { | |
ff240199 | 393 | DRM_DEBUG("Relocation beyond object bounds: " |
54cf91dc CW |
394 | "obj %p target %d offset %d size %d.\n", |
395 | obj, reloc->target_handle, | |
396 | (int) reloc->offset, | |
397 | (int) obj->base.size); | |
67731b87 | 398 | return ret; |
54cf91dc | 399 | } |
b8f7ab17 | 400 | if (unlikely(reloc->offset & 3)) { |
ff240199 | 401 | DRM_DEBUG("Relocation not 4-byte aligned: " |
54cf91dc CW |
402 | "obj %p target %d offset %d.\n", |
403 | obj, reloc->target_handle, | |
404 | (int) reloc->offset); | |
67731b87 | 405 | return ret; |
54cf91dc CW |
406 | } |
407 | ||
dabdfe02 CW |
408 | /* We can't wait for rendering with pagefaults disabled */ |
409 | if (obj->active && in_atomic()) | |
410 | return -EFAULT; | |
411 | ||
54cf91dc | 412 | reloc->delta += target_offset; |
5032d871 RB |
413 | if (use_cpu_reloc(obj)) |
414 | ret = relocate_entry_cpu(obj, reloc); | |
415 | else | |
416 | ret = relocate_entry_gtt(obj, reloc); | |
54cf91dc | 417 | |
d4d36014 DV |
418 | if (ret) |
419 | return ret; | |
420 | ||
54cf91dc CW |
421 | /* and update the user's relocation entry */ |
422 | reloc->presumed_offset = target_offset; | |
423 | ||
67731b87 | 424 | return 0; |
54cf91dc CW |
425 | } |
426 | ||
427 | static int | |
27173f1f BW |
428 | i915_gem_execbuffer_relocate_vma(struct i915_vma *vma, |
429 | struct eb_vmas *eb) | |
54cf91dc | 430 | { |
1d83f442 CW |
431 | #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) |
432 | struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)]; | |
54cf91dc | 433 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
27173f1f | 434 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
1d83f442 | 435 | int remain, ret; |
54cf91dc | 436 | |
2bb4629a | 437 | user_relocs = to_user_ptr(entry->relocs_ptr); |
54cf91dc | 438 | |
1d83f442 CW |
439 | remain = entry->relocation_count; |
440 | while (remain) { | |
441 | struct drm_i915_gem_relocation_entry *r = stack_reloc; | |
442 | int count = remain; | |
443 | if (count > ARRAY_SIZE(stack_reloc)) | |
444 | count = ARRAY_SIZE(stack_reloc); | |
445 | remain -= count; | |
446 | ||
447 | if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0]))) | |
54cf91dc CW |
448 | return -EFAULT; |
449 | ||
1d83f442 CW |
450 | do { |
451 | u64 offset = r->presumed_offset; | |
54cf91dc | 452 | |
3e7a0322 | 453 | ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r); |
1d83f442 CW |
454 | if (ret) |
455 | return ret; | |
456 | ||
457 | if (r->presumed_offset != offset && | |
458 | __copy_to_user_inatomic(&user_relocs->presumed_offset, | |
459 | &r->presumed_offset, | |
460 | sizeof(r->presumed_offset))) { | |
461 | return -EFAULT; | |
462 | } | |
463 | ||
464 | user_relocs++; | |
465 | r++; | |
466 | } while (--count); | |
54cf91dc CW |
467 | } |
468 | ||
469 | return 0; | |
1d83f442 | 470 | #undef N_RELOC |
54cf91dc CW |
471 | } |
472 | ||
473 | static int | |
27173f1f BW |
474 | i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma, |
475 | struct eb_vmas *eb, | |
476 | struct drm_i915_gem_relocation_entry *relocs) | |
54cf91dc | 477 | { |
27173f1f | 478 | const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
54cf91dc CW |
479 | int i, ret; |
480 | ||
481 | for (i = 0; i < entry->relocation_count; i++) { | |
3e7a0322 | 482 | ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i]); |
54cf91dc CW |
483 | if (ret) |
484 | return ret; | |
485 | } | |
486 | ||
487 | return 0; | |
488 | } | |
489 | ||
490 | static int | |
17601cbc | 491 | i915_gem_execbuffer_relocate(struct eb_vmas *eb) |
54cf91dc | 492 | { |
27173f1f | 493 | struct i915_vma *vma; |
d4aeee77 CW |
494 | int ret = 0; |
495 | ||
496 | /* This is the fast path and we cannot handle a pagefault whilst | |
497 | * holding the struct mutex lest the user pass in the relocations | |
498 | * contained within a mmaped bo. For in such a case we, the page | |
499 | * fault handler would call i915_gem_fault() and we would try to | |
500 | * acquire the struct mutex again. Obviously this is bad and so | |
501 | * lockdep complains vehemently. | |
502 | */ | |
503 | pagefault_disable(); | |
27173f1f BW |
504 | list_for_each_entry(vma, &eb->vmas, exec_list) { |
505 | ret = i915_gem_execbuffer_relocate_vma(vma, eb); | |
54cf91dc | 506 | if (ret) |
d4aeee77 | 507 | break; |
54cf91dc | 508 | } |
d4aeee77 | 509 | pagefault_enable(); |
54cf91dc | 510 | |
d4aeee77 | 511 | return ret; |
54cf91dc CW |
512 | } |
513 | ||
dabdfe02 | 514 | static int |
27173f1f | 515 | need_reloc_mappable(struct i915_vma *vma) |
dabdfe02 | 516 | { |
27173f1f BW |
517 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
518 | return entry->relocation_count && !use_cpu_reloc(vma->obj) && | |
519 | i915_is_ggtt(vma->vm); | |
dabdfe02 CW |
520 | } |
521 | ||
1690e1eb | 522 | static int |
27173f1f BW |
523 | i915_gem_execbuffer_reserve_vma(struct i915_vma *vma, |
524 | struct intel_ring_buffer *ring, | |
525 | bool *need_reloc) | |
1690e1eb | 526 | { |
6f65e29a | 527 | struct drm_i915_gem_object *obj = vma->obj; |
27173f1f | 528 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
1690e1eb CW |
529 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; |
530 | bool need_fence, need_mappable; | |
6f65e29a BW |
531 | u32 flags = (entry->flags & EXEC_OBJECT_NEEDS_GTT) && |
532 | !vma->obj->has_global_gtt_mapping ? GLOBAL_BIND : 0; | |
1690e1eb CW |
533 | int ret; |
534 | ||
535 | need_fence = | |
536 | has_fenced_gpu_access && | |
537 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
538 | obj->tiling_mode != I915_TILING_NONE; | |
27173f1f | 539 | need_mappable = need_fence || need_reloc_mappable(vma); |
1690e1eb | 540 | |
27173f1f | 541 | ret = i915_gem_object_pin(obj, vma->vm, entry->alignment, need_mappable, |
28d6a7bf | 542 | false); |
1690e1eb CW |
543 | if (ret) |
544 | return ret; | |
545 | ||
7788a765 CW |
546 | entry->flags |= __EXEC_OBJECT_HAS_PIN; |
547 | ||
1690e1eb CW |
548 | if (has_fenced_gpu_access) { |
549 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { | |
06d98131 | 550 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 | 551 | if (ret) |
7788a765 | 552 | return ret; |
1690e1eb | 553 | |
9a5a53b3 | 554 | if (i915_gem_object_pin_fence(obj)) |
1690e1eb | 555 | entry->flags |= __EXEC_OBJECT_HAS_FENCE; |
9a5a53b3 | 556 | |
7dd49065 | 557 | obj->pending_fenced_gpu_access = true; |
1690e1eb | 558 | } |
1690e1eb CW |
559 | } |
560 | ||
27173f1f BW |
561 | if (entry->offset != vma->node.start) { |
562 | entry->offset = vma->node.start; | |
ed5982e6 DV |
563 | *need_reloc = true; |
564 | } | |
565 | ||
566 | if (entry->flags & EXEC_OBJECT_WRITE) { | |
567 | obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER; | |
568 | obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER; | |
569 | } | |
570 | ||
6f65e29a | 571 | vma->bind_vma(vma, obj->cache_level, flags); |
ed5982e6 | 572 | |
1690e1eb | 573 | return 0; |
7788a765 | 574 | } |
1690e1eb | 575 | |
54cf91dc | 576 | static int |
d9e86c0e | 577 | i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring, |
27173f1f | 578 | struct list_head *vmas, |
ed5982e6 | 579 | bool *need_relocs) |
54cf91dc | 580 | { |
432e58ed | 581 | struct drm_i915_gem_object *obj; |
27173f1f | 582 | struct i915_vma *vma; |
68c8c17f | 583 | struct i915_address_space *vm; |
27173f1f | 584 | struct list_head ordered_vmas; |
7788a765 CW |
585 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; |
586 | int retry; | |
6fe4f140 | 587 | |
68c8c17f BW |
588 | if (list_empty(vmas)) |
589 | return 0; | |
590 | ||
591 | vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm; | |
592 | ||
27173f1f BW |
593 | INIT_LIST_HEAD(&ordered_vmas); |
594 | while (!list_empty(vmas)) { | |
6fe4f140 CW |
595 | struct drm_i915_gem_exec_object2 *entry; |
596 | bool need_fence, need_mappable; | |
597 | ||
27173f1f BW |
598 | vma = list_first_entry(vmas, struct i915_vma, exec_list); |
599 | obj = vma->obj; | |
600 | entry = vma->exec_entry; | |
6fe4f140 CW |
601 | |
602 | need_fence = | |
603 | has_fenced_gpu_access && | |
604 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
605 | obj->tiling_mode != I915_TILING_NONE; | |
27173f1f | 606 | need_mappable = need_fence || need_reloc_mappable(vma); |
6fe4f140 CW |
607 | |
608 | if (need_mappable) | |
27173f1f | 609 | list_move(&vma->exec_list, &ordered_vmas); |
6fe4f140 | 610 | else |
27173f1f | 611 | list_move_tail(&vma->exec_list, &ordered_vmas); |
595dad76 | 612 | |
ed5982e6 | 613 | obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND; |
595dad76 | 614 | obj->base.pending_write_domain = 0; |
016fd0c1 | 615 | obj->pending_fenced_gpu_access = false; |
6fe4f140 | 616 | } |
27173f1f | 617 | list_splice(&ordered_vmas, vmas); |
54cf91dc CW |
618 | |
619 | /* Attempt to pin all of the buffers into the GTT. | |
620 | * This is done in 3 phases: | |
621 | * | |
622 | * 1a. Unbind all objects that do not match the GTT constraints for | |
623 | * the execbuffer (fenceable, mappable, alignment etc). | |
624 | * 1b. Increment pin count for already bound objects. | |
625 | * 2. Bind new objects. | |
626 | * 3. Decrement pin count. | |
627 | * | |
7788a765 | 628 | * This avoid unnecessary unbinding of later objects in order to make |
54cf91dc CW |
629 | * room for the earlier objects *unless* we need to defragment. |
630 | */ | |
631 | retry = 0; | |
632 | do { | |
7788a765 | 633 | int ret = 0; |
54cf91dc CW |
634 | |
635 | /* Unbind any ill-fitting objects or pin. */ | |
27173f1f BW |
636 | list_for_each_entry(vma, vmas, exec_list) { |
637 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; | |
54cf91dc | 638 | bool need_fence, need_mappable; |
1690e1eb | 639 | |
27173f1f BW |
640 | obj = vma->obj; |
641 | ||
642 | if (!drm_mm_node_allocated(&vma->node)) | |
54cf91dc CW |
643 | continue; |
644 | ||
645 | need_fence = | |
9b3826bf | 646 | has_fenced_gpu_access && |
54cf91dc CW |
647 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
648 | obj->tiling_mode != I915_TILING_NONE; | |
27173f1f | 649 | need_mappable = need_fence || need_reloc_mappable(vma); |
54cf91dc | 650 | |
28d6a7bf | 651 | WARN_ON((need_mappable || need_fence) && |
27173f1f | 652 | !i915_is_ggtt(vma->vm)); |
28d6a7bf | 653 | |
f343c5f6 | 654 | if ((entry->alignment && |
27173f1f | 655 | vma->node.start & (entry->alignment - 1)) || |
54cf91dc | 656 | (need_mappable && !obj->map_and_fenceable)) |
27173f1f | 657 | ret = i915_vma_unbind(vma); |
54cf91dc | 658 | else |
27173f1f | 659 | ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs); |
432e58ed | 660 | if (ret) |
54cf91dc | 661 | goto err; |
54cf91dc CW |
662 | } |
663 | ||
664 | /* Bind fresh objects */ | |
27173f1f BW |
665 | list_for_each_entry(vma, vmas, exec_list) { |
666 | if (drm_mm_node_allocated(&vma->node)) | |
1690e1eb | 667 | continue; |
54cf91dc | 668 | |
27173f1f | 669 | ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs); |
7788a765 CW |
670 | if (ret) |
671 | goto err; | |
54cf91dc CW |
672 | } |
673 | ||
a415d355 | 674 | err: |
6c085a72 | 675 | if (ret != -ENOSPC || retry++) |
54cf91dc CW |
676 | return ret; |
677 | ||
a415d355 CW |
678 | /* Decrement pin count for bound objects */ |
679 | list_for_each_entry(vma, vmas, exec_list) | |
680 | i915_gem_execbuffer_unreserve_vma(vma); | |
681 | ||
68c8c17f | 682 | ret = i915_gem_evict_vm(vm, true); |
54cf91dc CW |
683 | if (ret) |
684 | return ret; | |
54cf91dc CW |
685 | } while (1); |
686 | } | |
687 | ||
688 | static int | |
689 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, | |
ed5982e6 | 690 | struct drm_i915_gem_execbuffer2 *args, |
54cf91dc | 691 | struct drm_file *file, |
d9e86c0e | 692 | struct intel_ring_buffer *ring, |
27173f1f BW |
693 | struct eb_vmas *eb, |
694 | struct drm_i915_gem_exec_object2 *exec) | |
54cf91dc CW |
695 | { |
696 | struct drm_i915_gem_relocation_entry *reloc; | |
27173f1f BW |
697 | struct i915_address_space *vm; |
698 | struct i915_vma *vma; | |
ed5982e6 | 699 | bool need_relocs; |
dd6864a4 | 700 | int *reloc_offset; |
54cf91dc | 701 | int i, total, ret; |
b205ca57 | 702 | unsigned count = args->buffer_count; |
54cf91dc | 703 | |
27173f1f BW |
704 | if (WARN_ON(list_empty(&eb->vmas))) |
705 | return 0; | |
706 | ||
707 | vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm; | |
708 | ||
67731b87 | 709 | /* We may process another execbuffer during the unlock... */ |
27173f1f BW |
710 | while (!list_empty(&eb->vmas)) { |
711 | vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list); | |
712 | list_del_init(&vma->exec_list); | |
a415d355 | 713 | i915_gem_execbuffer_unreserve_vma(vma); |
27173f1f | 714 | drm_gem_object_unreference(&vma->obj->base); |
67731b87 CW |
715 | } |
716 | ||
54cf91dc CW |
717 | mutex_unlock(&dev->struct_mutex); |
718 | ||
719 | total = 0; | |
720 | for (i = 0; i < count; i++) | |
432e58ed | 721 | total += exec[i].relocation_count; |
54cf91dc | 722 | |
dd6864a4 | 723 | reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset)); |
54cf91dc | 724 | reloc = drm_malloc_ab(total, sizeof(*reloc)); |
dd6864a4 CW |
725 | if (reloc == NULL || reloc_offset == NULL) { |
726 | drm_free_large(reloc); | |
727 | drm_free_large(reloc_offset); | |
54cf91dc CW |
728 | mutex_lock(&dev->struct_mutex); |
729 | return -ENOMEM; | |
730 | } | |
731 | ||
732 | total = 0; | |
733 | for (i = 0; i < count; i++) { | |
734 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
262b6d36 CW |
735 | u64 invalid_offset = (u64)-1; |
736 | int j; | |
54cf91dc | 737 | |
2bb4629a | 738 | user_relocs = to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
739 | |
740 | if (copy_from_user(reloc+total, user_relocs, | |
432e58ed | 741 | exec[i].relocation_count * sizeof(*reloc))) { |
54cf91dc CW |
742 | ret = -EFAULT; |
743 | mutex_lock(&dev->struct_mutex); | |
744 | goto err; | |
745 | } | |
746 | ||
262b6d36 CW |
747 | /* As we do not update the known relocation offsets after |
748 | * relocating (due to the complexities in lock handling), | |
749 | * we need to mark them as invalid now so that we force the | |
750 | * relocation processing next time. Just in case the target | |
751 | * object is evicted and then rebound into its old | |
752 | * presumed_offset before the next execbuffer - if that | |
753 | * happened we would make the mistake of assuming that the | |
754 | * relocations were valid. | |
755 | */ | |
756 | for (j = 0; j < exec[i].relocation_count; j++) { | |
757 | if (copy_to_user(&user_relocs[j].presumed_offset, | |
758 | &invalid_offset, | |
759 | sizeof(invalid_offset))) { | |
760 | ret = -EFAULT; | |
761 | mutex_lock(&dev->struct_mutex); | |
762 | goto err; | |
763 | } | |
764 | } | |
765 | ||
dd6864a4 | 766 | reloc_offset[i] = total; |
432e58ed | 767 | total += exec[i].relocation_count; |
54cf91dc CW |
768 | } |
769 | ||
770 | ret = i915_mutex_lock_interruptible(dev); | |
771 | if (ret) { | |
772 | mutex_lock(&dev->struct_mutex); | |
773 | goto err; | |
774 | } | |
775 | ||
67731b87 | 776 | /* reacquire the objects */ |
67731b87 | 777 | eb_reset(eb); |
27173f1f | 778 | ret = eb_lookup_vmas(eb, exec, args, vm, file); |
3b96eff4 CW |
779 | if (ret) |
780 | goto err; | |
67731b87 | 781 | |
ed5982e6 | 782 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
27173f1f | 783 | ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, &need_relocs); |
54cf91dc CW |
784 | if (ret) |
785 | goto err; | |
786 | ||
27173f1f BW |
787 | list_for_each_entry(vma, &eb->vmas, exec_list) { |
788 | int offset = vma->exec_entry - exec; | |
789 | ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb, | |
790 | reloc + reloc_offset[offset]); | |
54cf91dc CW |
791 | if (ret) |
792 | goto err; | |
54cf91dc CW |
793 | } |
794 | ||
795 | /* Leave the user relocations as are, this is the painfully slow path, | |
796 | * and we want to avoid the complication of dropping the lock whilst | |
797 | * having buffers reserved in the aperture and so causing spurious | |
798 | * ENOSPC for random operations. | |
799 | */ | |
800 | ||
801 | err: | |
802 | drm_free_large(reloc); | |
dd6864a4 | 803 | drm_free_large(reloc_offset); |
54cf91dc CW |
804 | return ret; |
805 | } | |
806 | ||
54cf91dc | 807 | static int |
432e58ed | 808 | i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring, |
27173f1f | 809 | struct list_head *vmas) |
54cf91dc | 810 | { |
27173f1f | 811 | struct i915_vma *vma; |
6ac42f41 | 812 | uint32_t flush_domains = 0; |
000433b6 | 813 | bool flush_chipset = false; |
432e58ed | 814 | int ret; |
54cf91dc | 815 | |
27173f1f BW |
816 | list_for_each_entry(vma, vmas, exec_list) { |
817 | struct drm_i915_gem_object *obj = vma->obj; | |
6ac42f41 | 818 | ret = i915_gem_object_sync(obj, ring); |
c59a333f CW |
819 | if (ret) |
820 | return ret; | |
6ac42f41 DV |
821 | |
822 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) | |
000433b6 | 823 | flush_chipset |= i915_gem_clflush_object(obj, false); |
6ac42f41 | 824 | |
6ac42f41 | 825 | flush_domains |= obj->base.write_domain; |
c59a333f CW |
826 | } |
827 | ||
000433b6 | 828 | if (flush_chipset) |
e76e9aeb | 829 | i915_gem_chipset_flush(ring->dev); |
6ac42f41 DV |
830 | |
831 | if (flush_domains & I915_GEM_DOMAIN_GTT) | |
832 | wmb(); | |
833 | ||
09cf7c9a CW |
834 | /* Unconditionally invalidate gpu caches and ensure that we do flush |
835 | * any residual writes from the previous batch. | |
836 | */ | |
a7b9761d | 837 | return intel_ring_invalidate_all_caches(ring); |
54cf91dc CW |
838 | } |
839 | ||
432e58ed CW |
840 | static bool |
841 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) | |
54cf91dc | 842 | { |
ed5982e6 DV |
843 | if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS) |
844 | return false; | |
845 | ||
432e58ed | 846 | return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0; |
54cf91dc CW |
847 | } |
848 | ||
849 | static int | |
850 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, | |
851 | int count) | |
852 | { | |
853 | int i; | |
b205ca57 DV |
854 | unsigned relocs_total = 0; |
855 | unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry); | |
54cf91dc CW |
856 | |
857 | for (i = 0; i < count; i++) { | |
2bb4629a | 858 | char __user *ptr = to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
859 | int length; /* limited by fault_in_pages_readable() */ |
860 | ||
ed5982e6 DV |
861 | if (exec[i].flags & __EXEC_OBJECT_UNKNOWN_FLAGS) |
862 | return -EINVAL; | |
863 | ||
3118a4f6 KC |
864 | /* First check for malicious input causing overflow in |
865 | * the worst case where we need to allocate the entire | |
866 | * relocation tree as a single array. | |
867 | */ | |
868 | if (exec[i].relocation_count > relocs_max - relocs_total) | |
54cf91dc | 869 | return -EINVAL; |
3118a4f6 | 870 | relocs_total += exec[i].relocation_count; |
54cf91dc CW |
871 | |
872 | length = exec[i].relocation_count * | |
873 | sizeof(struct drm_i915_gem_relocation_entry); | |
30587535 KC |
874 | /* |
875 | * We must check that the entire relocation array is safe | |
876 | * to read, but since we may need to update the presumed | |
877 | * offsets during execution, check for full write access. | |
878 | */ | |
54cf91dc CW |
879 | if (!access_ok(VERIFY_WRITE, ptr, length)) |
880 | return -EFAULT; | |
881 | ||
0b74b508 XZ |
882 | if (likely(!i915_prefault_disable)) { |
883 | if (fault_in_multipages_readable(ptr, length)) | |
884 | return -EFAULT; | |
885 | } | |
54cf91dc CW |
886 | } |
887 | ||
888 | return 0; | |
889 | } | |
890 | ||
41bde553 | 891 | static struct i915_hw_context * |
d299cce7 MK |
892 | i915_gem_validate_context(struct drm_device *dev, struct drm_file *file, |
893 | const u32 ctx_id) | |
894 | { | |
41bde553 | 895 | struct i915_hw_context *ctx = NULL; |
d299cce7 MK |
896 | struct i915_ctx_hang_stats *hs; |
897 | ||
41bde553 BW |
898 | ctx = i915_gem_context_get(file->driver_priv, ctx_id); |
899 | if (IS_ERR_OR_NULL(ctx)) | |
900 | return ctx; | |
d299cce7 | 901 | |
41bde553 | 902 | hs = &ctx->hang_stats; |
d299cce7 MK |
903 | if (hs->banned) { |
904 | DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id); | |
41bde553 | 905 | return ERR_PTR(-EIO); |
d299cce7 MK |
906 | } |
907 | ||
41bde553 | 908 | return ctx; |
d299cce7 MK |
909 | } |
910 | ||
432e58ed | 911 | static void |
27173f1f | 912 | i915_gem_execbuffer_move_to_active(struct list_head *vmas, |
9d773091 | 913 | struct intel_ring_buffer *ring) |
432e58ed | 914 | { |
27173f1f | 915 | struct i915_vma *vma; |
432e58ed | 916 | |
27173f1f BW |
917 | list_for_each_entry(vma, vmas, exec_list) { |
918 | struct drm_i915_gem_object *obj = vma->obj; | |
69c2fc89 CW |
919 | u32 old_read = obj->base.read_domains; |
920 | u32 old_write = obj->base.write_domain; | |
db53a302 | 921 | |
432e58ed | 922 | obj->base.write_domain = obj->base.pending_write_domain; |
ed5982e6 DV |
923 | if (obj->base.write_domain == 0) |
924 | obj->base.pending_read_domains |= obj->base.read_domains; | |
925 | obj->base.read_domains = obj->base.pending_read_domains; | |
432e58ed CW |
926 | obj->fenced_gpu_access = obj->pending_fenced_gpu_access; |
927 | ||
e2d05a8b | 928 | i915_vma_move_to_active(vma, ring); |
432e58ed CW |
929 | if (obj->base.write_domain) { |
930 | obj->dirty = 1; | |
9d773091 | 931 | obj->last_write_seqno = intel_ring_get_seqno(ring); |
d7f46fc4 BW |
932 | /* check for potential scanout */ |
933 | if (i915_gem_obj_ggtt_bound(obj) && | |
934 | i915_gem_obj_to_ggtt(obj)->pin_count) | |
c65355bb | 935 | intel_mark_fb_busy(obj, ring); |
432e58ed CW |
936 | } |
937 | ||
db53a302 | 938 | trace_i915_gem_object_change_domain(obj, old_read, old_write); |
432e58ed CW |
939 | } |
940 | } | |
941 | ||
54cf91dc CW |
942 | static void |
943 | i915_gem_execbuffer_retire_commands(struct drm_device *dev, | |
432e58ed | 944 | struct drm_file *file, |
7d736f4f MK |
945 | struct intel_ring_buffer *ring, |
946 | struct drm_i915_gem_object *obj) | |
54cf91dc | 947 | { |
cc889e0f DV |
948 | /* Unconditionally force add_request to emit a full flush. */ |
949 | ring->gpu_caches_dirty = true; | |
54cf91dc | 950 | |
432e58ed | 951 | /* Add a breadcrumb for the completion of the batch buffer */ |
7d736f4f | 952 | (void)__i915_add_request(ring, file, obj, NULL); |
432e58ed | 953 | } |
54cf91dc | 954 | |
ae662d31 EA |
955 | static int |
956 | i915_reset_gen7_sol_offsets(struct drm_device *dev, | |
957 | struct intel_ring_buffer *ring) | |
958 | { | |
959 | drm_i915_private_t *dev_priv = dev->dev_private; | |
960 | int ret, i; | |
961 | ||
962 | if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) | |
963 | return 0; | |
964 | ||
965 | ret = intel_ring_begin(ring, 4 * 3); | |
966 | if (ret) | |
967 | return ret; | |
968 | ||
969 | for (i = 0; i < 4; i++) { | |
970 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
971 | intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i)); | |
972 | intel_ring_emit(ring, 0); | |
973 | } | |
974 | ||
975 | intel_ring_advance(ring); | |
976 | ||
977 | return 0; | |
978 | } | |
979 | ||
54cf91dc CW |
980 | static int |
981 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, | |
982 | struct drm_file *file, | |
983 | struct drm_i915_gem_execbuffer2 *args, | |
41bde553 | 984 | struct drm_i915_gem_exec_object2 *exec) |
54cf91dc CW |
985 | { |
986 | drm_i915_private_t *dev_priv = dev->dev_private; | |
27173f1f | 987 | struct eb_vmas *eb; |
54cf91dc CW |
988 | struct drm_i915_gem_object *batch_obj; |
989 | struct drm_clip_rect *cliprects = NULL; | |
54cf91dc | 990 | struct intel_ring_buffer *ring; |
41bde553 BW |
991 | struct i915_hw_context *ctx; |
992 | struct i915_address_space *vm; | |
d299cce7 | 993 | const u32 ctx_id = i915_execbuffer2_get_context_id(*args); |
c4e7a414 | 994 | u32 exec_start, exec_len; |
ed5982e6 | 995 | u32 mask, flags; |
72bfa19c | 996 | int ret, mode, i; |
ed5982e6 | 997 | bool need_relocs; |
54cf91dc | 998 | |
ed5982e6 | 999 | if (!i915_gem_check_execbuffer(args)) |
432e58ed | 1000 | return -EINVAL; |
432e58ed CW |
1001 | |
1002 | ret = validate_exec_list(exec, args->buffer_count); | |
54cf91dc CW |
1003 | if (ret) |
1004 | return ret; | |
1005 | ||
d7d4eedd CW |
1006 | flags = 0; |
1007 | if (args->flags & I915_EXEC_SECURE) { | |
1008 | if (!file->is_master || !capable(CAP_SYS_ADMIN)) | |
1009 | return -EPERM; | |
1010 | ||
1011 | flags |= I915_DISPATCH_SECURE; | |
1012 | } | |
b45305fc DV |
1013 | if (args->flags & I915_EXEC_IS_PINNED) |
1014 | flags |= I915_DISPATCH_PINNED; | |
d7d4eedd | 1015 | |
ca01b12b | 1016 | if ((args->flags & I915_EXEC_RING_MASK) > I915_NUM_RINGS) { |
ff240199 | 1017 | DRM_DEBUG("execbuf with unknown ring: %d\n", |
54cf91dc CW |
1018 | (int)(args->flags & I915_EXEC_RING_MASK)); |
1019 | return -EINVAL; | |
1020 | } | |
ca01b12b BW |
1021 | |
1022 | if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_DEFAULT) | |
1023 | ring = &dev_priv->ring[RCS]; | |
1024 | else | |
1025 | ring = &dev_priv->ring[(args->flags & I915_EXEC_RING_MASK) - 1]; | |
1026 | ||
a15817cf CW |
1027 | if (!intel_ring_initialized(ring)) { |
1028 | DRM_DEBUG("execbuf with invalid ring: %d\n", | |
1029 | (int)(args->flags & I915_EXEC_RING_MASK)); | |
1030 | return -EINVAL; | |
1031 | } | |
54cf91dc | 1032 | |
72bfa19c | 1033 | mode = args->flags & I915_EXEC_CONSTANTS_MASK; |
84f9f938 | 1034 | mask = I915_EXEC_CONSTANTS_MASK; |
72bfa19c CW |
1035 | switch (mode) { |
1036 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
1037 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
1038 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
1039 | if (ring == &dev_priv->ring[RCS] && | |
1040 | mode != dev_priv->relative_constants_mode) { | |
1041 | if (INTEL_INFO(dev)->gen < 4) | |
1042 | return -EINVAL; | |
1043 | ||
1044 | if (INTEL_INFO(dev)->gen > 5 && | |
1045 | mode == I915_EXEC_CONSTANTS_REL_SURFACE) | |
1046 | return -EINVAL; | |
84f9f938 BW |
1047 | |
1048 | /* The HW changed the meaning on this bit on gen6 */ | |
1049 | if (INTEL_INFO(dev)->gen >= 6) | |
1050 | mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
72bfa19c CW |
1051 | } |
1052 | break; | |
1053 | default: | |
ff240199 | 1054 | DRM_DEBUG("execbuf with unknown constants: %d\n", mode); |
72bfa19c CW |
1055 | return -EINVAL; |
1056 | } | |
1057 | ||
54cf91dc | 1058 | if (args->buffer_count < 1) { |
ff240199 | 1059 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1060 | return -EINVAL; |
1061 | } | |
54cf91dc CW |
1062 | |
1063 | if (args->num_cliprects != 0) { | |
1ec14ad3 | 1064 | if (ring != &dev_priv->ring[RCS]) { |
ff240199 | 1065 | DRM_DEBUG("clip rectangles are only valid with the render ring\n"); |
c4e7a414 CW |
1066 | return -EINVAL; |
1067 | } | |
1068 | ||
6ebebc92 DV |
1069 | if (INTEL_INFO(dev)->gen >= 5) { |
1070 | DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); | |
1071 | return -EINVAL; | |
1072 | } | |
1073 | ||
44afb3a0 XW |
1074 | if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) { |
1075 | DRM_DEBUG("execbuf with %u cliprects\n", | |
1076 | args->num_cliprects); | |
1077 | return -EINVAL; | |
1078 | } | |
5e13a0c5 | 1079 | |
a1e22653 DV |
1080 | cliprects = kcalloc(args->num_cliprects, |
1081 | sizeof(*cliprects), | |
54cf91dc CW |
1082 | GFP_KERNEL); |
1083 | if (cliprects == NULL) { | |
1084 | ret = -ENOMEM; | |
1085 | goto pre_mutex_err; | |
1086 | } | |
1087 | ||
432e58ed | 1088 | if (copy_from_user(cliprects, |
2bb4629a VS |
1089 | to_user_ptr(args->cliprects_ptr), |
1090 | sizeof(*cliprects)*args->num_cliprects)) { | |
54cf91dc CW |
1091 | ret = -EFAULT; |
1092 | goto pre_mutex_err; | |
1093 | } | |
1094 | } | |
1095 | ||
54cf91dc CW |
1096 | ret = i915_mutex_lock_interruptible(dev); |
1097 | if (ret) | |
1098 | goto pre_mutex_err; | |
1099 | ||
db1b76ca | 1100 | if (dev_priv->ums.mm_suspended) { |
54cf91dc CW |
1101 | mutex_unlock(&dev->struct_mutex); |
1102 | ret = -EBUSY; | |
1103 | goto pre_mutex_err; | |
1104 | } | |
1105 | ||
41bde553 BW |
1106 | ctx = i915_gem_validate_context(dev, file, ctx_id); |
1107 | if (IS_ERR_OR_NULL(ctx)) { | |
d299cce7 | 1108 | mutex_unlock(&dev->struct_mutex); |
41bde553 | 1109 | ret = PTR_ERR(ctx); |
d299cce7 | 1110 | goto pre_mutex_err; |
41bde553 BW |
1111 | } |
1112 | ||
1113 | i915_gem_context_reference(ctx); | |
1114 | ||
1115 | /* HACK until we have full PPGTT */ | |
1116 | /* vm = ctx->vm; */ | |
1117 | vm = &dev_priv->gtt.base; | |
d299cce7 | 1118 | |
17601cbc | 1119 | eb = eb_create(args); |
67731b87 CW |
1120 | if (eb == NULL) { |
1121 | mutex_unlock(&dev->struct_mutex); | |
1122 | ret = -ENOMEM; | |
1123 | goto pre_mutex_err; | |
1124 | } | |
1125 | ||
54cf91dc | 1126 | /* Look up object handles */ |
27173f1f | 1127 | ret = eb_lookup_vmas(eb, exec, args, vm, file); |
3b96eff4 CW |
1128 | if (ret) |
1129 | goto err; | |
54cf91dc | 1130 | |
6fe4f140 | 1131 | /* take note of the batch buffer before we might reorder the lists */ |
27173f1f | 1132 | batch_obj = list_entry(eb->vmas.prev, struct i915_vma, exec_list)->obj; |
6fe4f140 | 1133 | |
54cf91dc | 1134 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
ed5982e6 | 1135 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
27173f1f | 1136 | ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, &need_relocs); |
54cf91dc CW |
1137 | if (ret) |
1138 | goto err; | |
1139 | ||
1140 | /* The objects are in their final locations, apply the relocations. */ | |
ed5982e6 | 1141 | if (need_relocs) |
17601cbc | 1142 | ret = i915_gem_execbuffer_relocate(eb); |
54cf91dc CW |
1143 | if (ret) { |
1144 | if (ret == -EFAULT) { | |
ed5982e6 | 1145 | ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring, |
27173f1f | 1146 | eb, exec); |
54cf91dc CW |
1147 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
1148 | } | |
1149 | if (ret) | |
1150 | goto err; | |
1151 | } | |
1152 | ||
1153 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
54cf91dc | 1154 | if (batch_obj->base.pending_write_domain) { |
ff240199 | 1155 | DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); |
54cf91dc CW |
1156 | ret = -EINVAL; |
1157 | goto err; | |
1158 | } | |
1159 | batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
1160 | ||
d7d4eedd CW |
1161 | /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure |
1162 | * batch" bit. Hence we need to pin secure batches into the global gtt. | |
28cf5415 | 1163 | * hsw should have this fixed, but bdw mucks it up again. */ |
6f65e29a BW |
1164 | if (flags & I915_DISPATCH_SECURE && |
1165 | !batch_obj->has_global_gtt_mapping) { | |
1166 | /* When we have multiple VMs, we'll need to make sure that we | |
1167 | * allocate space first */ | |
1168 | struct i915_vma *vma = i915_gem_obj_to_ggtt(batch_obj); | |
1169 | BUG_ON(!vma); | |
1170 | vma->bind_vma(vma, batch_obj->cache_level, GLOBAL_BIND); | |
1171 | } | |
d7d4eedd | 1172 | |
27173f1f | 1173 | ret = i915_gem_execbuffer_move_to_gpu(ring, &eb->vmas); |
432e58ed | 1174 | if (ret) |
54cf91dc | 1175 | goto err; |
54cf91dc | 1176 | |
41bde553 | 1177 | ret = i915_switch_context(ring, file, ctx); |
0da5cec1 EA |
1178 | if (ret) |
1179 | goto err; | |
1180 | ||
e2971bda BW |
1181 | if (ring == &dev_priv->ring[RCS] && |
1182 | mode != dev_priv->relative_constants_mode) { | |
1183 | ret = intel_ring_begin(ring, 4); | |
1184 | if (ret) | |
1185 | goto err; | |
1186 | ||
1187 | intel_ring_emit(ring, MI_NOOP); | |
1188 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
1189 | intel_ring_emit(ring, INSTPM); | |
84f9f938 | 1190 | intel_ring_emit(ring, mask << 16 | mode); |
e2971bda BW |
1191 | intel_ring_advance(ring); |
1192 | ||
1193 | dev_priv->relative_constants_mode = mode; | |
1194 | } | |
1195 | ||
ae662d31 EA |
1196 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { |
1197 | ret = i915_reset_gen7_sol_offsets(dev, ring); | |
1198 | if (ret) | |
1199 | goto err; | |
1200 | } | |
1201 | ||
28d6a7bf BW |
1202 | exec_start = i915_gem_obj_offset(batch_obj, vm) + |
1203 | args->batch_start_offset; | |
c4e7a414 CW |
1204 | exec_len = args->batch_len; |
1205 | if (cliprects) { | |
1206 | for (i = 0; i < args->num_cliprects; i++) { | |
1207 | ret = i915_emit_box(dev, &cliprects[i], | |
1208 | args->DR1, args->DR4); | |
1209 | if (ret) | |
1210 | goto err; | |
1211 | ||
1212 | ret = ring->dispatch_execbuffer(ring, | |
d7d4eedd CW |
1213 | exec_start, exec_len, |
1214 | flags); | |
c4e7a414 CW |
1215 | if (ret) |
1216 | goto err; | |
1217 | } | |
1218 | } else { | |
d7d4eedd CW |
1219 | ret = ring->dispatch_execbuffer(ring, |
1220 | exec_start, exec_len, | |
1221 | flags); | |
c4e7a414 CW |
1222 | if (ret) |
1223 | goto err; | |
1224 | } | |
54cf91dc | 1225 | |
9d773091 CW |
1226 | trace_i915_gem_ring_dispatch(ring, intel_ring_get_seqno(ring), flags); |
1227 | ||
27173f1f | 1228 | i915_gem_execbuffer_move_to_active(&eb->vmas, ring); |
7d736f4f | 1229 | i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj); |
54cf91dc CW |
1230 | |
1231 | err: | |
41bde553 BW |
1232 | /* the request owns the ref now */ |
1233 | i915_gem_context_unreference(ctx); | |
67731b87 | 1234 | eb_destroy(eb); |
54cf91dc CW |
1235 | |
1236 | mutex_unlock(&dev->struct_mutex); | |
1237 | ||
1238 | pre_mutex_err: | |
54cf91dc | 1239 | kfree(cliprects); |
54cf91dc CW |
1240 | return ret; |
1241 | } | |
1242 | ||
1243 | /* | |
1244 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
1245 | * list array and passes it to the real function. | |
1246 | */ | |
1247 | int | |
1248 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1249 | struct drm_file *file) | |
1250 | { | |
1251 | struct drm_i915_gem_execbuffer *args = data; | |
1252 | struct drm_i915_gem_execbuffer2 exec2; | |
1253 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
1254 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1255 | int ret, i; | |
1256 | ||
54cf91dc | 1257 | if (args->buffer_count < 1) { |
ff240199 | 1258 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1259 | return -EINVAL; |
1260 | } | |
1261 | ||
1262 | /* Copy in the exec list from userland */ | |
1263 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
1264 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
1265 | if (exec_list == NULL || exec2_list == NULL) { | |
ff240199 | 1266 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1267 | args->buffer_count); |
1268 | drm_free_large(exec_list); | |
1269 | drm_free_large(exec2_list); | |
1270 | return -ENOMEM; | |
1271 | } | |
1272 | ret = copy_from_user(exec_list, | |
2bb4629a | 1273 | to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1274 | sizeof(*exec_list) * args->buffer_count); |
1275 | if (ret != 0) { | |
ff240199 | 1276 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1277 | args->buffer_count, ret); |
1278 | drm_free_large(exec_list); | |
1279 | drm_free_large(exec2_list); | |
1280 | return -EFAULT; | |
1281 | } | |
1282 | ||
1283 | for (i = 0; i < args->buffer_count; i++) { | |
1284 | exec2_list[i].handle = exec_list[i].handle; | |
1285 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
1286 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
1287 | exec2_list[i].alignment = exec_list[i].alignment; | |
1288 | exec2_list[i].offset = exec_list[i].offset; | |
1289 | if (INTEL_INFO(dev)->gen < 4) | |
1290 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; | |
1291 | else | |
1292 | exec2_list[i].flags = 0; | |
1293 | } | |
1294 | ||
1295 | exec2.buffers_ptr = args->buffers_ptr; | |
1296 | exec2.buffer_count = args->buffer_count; | |
1297 | exec2.batch_start_offset = args->batch_start_offset; | |
1298 | exec2.batch_len = args->batch_len; | |
1299 | exec2.DR1 = args->DR1; | |
1300 | exec2.DR4 = args->DR4; | |
1301 | exec2.num_cliprects = args->num_cliprects; | |
1302 | exec2.cliprects_ptr = args->cliprects_ptr; | |
1303 | exec2.flags = I915_EXEC_RENDER; | |
6e0a69db | 1304 | i915_execbuffer2_set_context_id(exec2, 0); |
54cf91dc | 1305 | |
41bde553 | 1306 | ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list); |
54cf91dc CW |
1307 | if (!ret) { |
1308 | /* Copy the new buffer offsets back to the user's exec list. */ | |
1309 | for (i = 0; i < args->buffer_count; i++) | |
1310 | exec_list[i].offset = exec2_list[i].offset; | |
1311 | /* ... and back out to userspace */ | |
2bb4629a | 1312 | ret = copy_to_user(to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1313 | exec_list, |
1314 | sizeof(*exec_list) * args->buffer_count); | |
1315 | if (ret) { | |
1316 | ret = -EFAULT; | |
ff240199 | 1317 | DRM_DEBUG("failed to copy %d exec entries " |
54cf91dc CW |
1318 | "back to user (%d)\n", |
1319 | args->buffer_count, ret); | |
1320 | } | |
1321 | } | |
1322 | ||
1323 | drm_free_large(exec_list); | |
1324 | drm_free_large(exec2_list); | |
1325 | return ret; | |
1326 | } | |
1327 | ||
1328 | int | |
1329 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
1330 | struct drm_file *file) | |
1331 | { | |
1332 | struct drm_i915_gem_execbuffer2 *args = data; | |
1333 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1334 | int ret; | |
1335 | ||
ed8cd3b2 XW |
1336 | if (args->buffer_count < 1 || |
1337 | args->buffer_count > UINT_MAX / sizeof(*exec2_list)) { | |
ff240199 | 1338 | DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1339 | return -EINVAL; |
1340 | } | |
1341 | ||
8408c282 | 1342 | exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count, |
419fa72a | 1343 | GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); |
8408c282 CW |
1344 | if (exec2_list == NULL) |
1345 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), | |
1346 | args->buffer_count); | |
54cf91dc | 1347 | if (exec2_list == NULL) { |
ff240199 | 1348 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1349 | args->buffer_count); |
1350 | return -ENOMEM; | |
1351 | } | |
1352 | ret = copy_from_user(exec2_list, | |
2bb4629a | 1353 | to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1354 | sizeof(*exec2_list) * args->buffer_count); |
1355 | if (ret != 0) { | |
ff240199 | 1356 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1357 | args->buffer_count, ret); |
1358 | drm_free_large(exec2_list); | |
1359 | return -EFAULT; | |
1360 | } | |
1361 | ||
41bde553 | 1362 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list); |
54cf91dc CW |
1363 | if (!ret) { |
1364 | /* Copy the new buffer offsets back to the user's exec list. */ | |
2bb4629a | 1365 | ret = copy_to_user(to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1366 | exec2_list, |
1367 | sizeof(*exec2_list) * args->buffer_count); | |
1368 | if (ret) { | |
1369 | ret = -EFAULT; | |
ff240199 | 1370 | DRM_DEBUG("failed to copy %d exec entries " |
54cf91dc CW |
1371 | "back to user (%d)\n", |
1372 | args->buffer_count, ret); | |
1373 | } | |
1374 | } | |
1375 | ||
1376 | drm_free_large(exec2_list); | |
1377 | return ret; | |
1378 | } |