Commit | Line | Data |
---|---|---|
54cf91dc CW |
1 | /* |
2 | * Copyright © 2008,2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Chris Wilson <chris@chris-wilson.co.uk> | |
26 | * | |
27 | */ | |
28 | ||
760285e7 DH |
29 | #include <drm/drmP.h> |
30 | #include <drm/i915_drm.h> | |
54cf91dc CW |
31 | #include "i915_drv.h" |
32 | #include "i915_trace.h" | |
33 | #include "intel_drv.h" | |
f45b5557 | 34 | #include <linux/dma_remapping.h> |
54cf91dc | 35 | |
27173f1f BW |
36 | struct eb_vmas { |
37 | struct list_head vmas; | |
67731b87 | 38 | int and; |
eef90ccb | 39 | union { |
27173f1f | 40 | struct i915_vma *lut[0]; |
eef90ccb CW |
41 | struct hlist_head buckets[0]; |
42 | }; | |
67731b87 CW |
43 | }; |
44 | ||
27173f1f BW |
45 | static struct eb_vmas * |
46 | eb_create(struct drm_i915_gem_execbuffer2 *args, struct i915_address_space *vm) | |
67731b87 | 47 | { |
27173f1f | 48 | struct eb_vmas *eb = NULL; |
eef90ccb CW |
49 | |
50 | if (args->flags & I915_EXEC_HANDLE_LUT) { | |
51 | int size = args->buffer_count; | |
27173f1f BW |
52 | size *= sizeof(struct i915_vma *); |
53 | size += sizeof(struct eb_vmas); | |
eef90ccb CW |
54 | eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); |
55 | } | |
56 | ||
57 | if (eb == NULL) { | |
58 | int size = args->buffer_count; | |
59 | int count = PAGE_SIZE / sizeof(struct hlist_head) / 2; | |
27b7c63a | 60 | BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head)); |
eef90ccb CW |
61 | while (count > 2*size) |
62 | count >>= 1; | |
63 | eb = kzalloc(count*sizeof(struct hlist_head) + | |
27173f1f | 64 | sizeof(struct eb_vmas), |
eef90ccb CW |
65 | GFP_TEMPORARY); |
66 | if (eb == NULL) | |
67 | return eb; | |
68 | ||
69 | eb->and = count - 1; | |
70 | } else | |
71 | eb->and = -args->buffer_count; | |
72 | ||
27173f1f | 73 | INIT_LIST_HEAD(&eb->vmas); |
67731b87 CW |
74 | return eb; |
75 | } | |
76 | ||
77 | static void | |
27173f1f | 78 | eb_reset(struct eb_vmas *eb) |
67731b87 | 79 | { |
eef90ccb CW |
80 | if (eb->and >= 0) |
81 | memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head)); | |
67731b87 CW |
82 | } |
83 | ||
3b96eff4 | 84 | static int |
27173f1f BW |
85 | eb_lookup_vmas(struct eb_vmas *eb, |
86 | struct drm_i915_gem_exec_object2 *exec, | |
87 | const struct drm_i915_gem_execbuffer2 *args, | |
88 | struct i915_address_space *vm, | |
89 | struct drm_file *file) | |
3b96eff4 | 90 | { |
27173f1f BW |
91 | struct drm_i915_gem_object *obj; |
92 | struct list_head objects; | |
93 | int i, ret = 0; | |
3b96eff4 | 94 | |
27173f1f | 95 | INIT_LIST_HEAD(&objects); |
3b96eff4 | 96 | spin_lock(&file->table_lock); |
27173f1f BW |
97 | /* Grab a reference to the object and release the lock so we can lookup |
98 | * or create the VMA without using GFP_ATOMIC */ | |
eef90ccb | 99 | for (i = 0; i < args->buffer_count; i++) { |
3b96eff4 CW |
100 | obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle)); |
101 | if (obj == NULL) { | |
102 | spin_unlock(&file->table_lock); | |
103 | DRM_DEBUG("Invalid object handle %d at index %d\n", | |
104 | exec[i].handle, i); | |
27173f1f BW |
105 | ret = -ENOENT; |
106 | goto out; | |
3b96eff4 CW |
107 | } |
108 | ||
27173f1f | 109 | if (!list_empty(&obj->obj_exec_link)) { |
3b96eff4 CW |
110 | spin_unlock(&file->table_lock); |
111 | DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n", | |
112 | obj, exec[i].handle, i); | |
27173f1f BW |
113 | ret = -EINVAL; |
114 | goto out; | |
3b96eff4 CW |
115 | } |
116 | ||
117 | drm_gem_object_reference(&obj->base); | |
27173f1f BW |
118 | list_add_tail(&obj->obj_exec_link, &objects); |
119 | } | |
120 | spin_unlock(&file->table_lock); | |
3b96eff4 | 121 | |
27173f1f BW |
122 | i = 0; |
123 | list_for_each_entry(obj, &objects, obj_exec_link) { | |
124 | struct i915_vma *vma; | |
125 | ||
126 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm); | |
127 | if (IS_ERR(vma)) { | |
128 | /* XXX: We don't need an error path fro vma because if | |
129 | * the vma was created just for this execbuf, object | |
130 | * unreference should kill it off.*/ | |
131 | DRM_DEBUG("Failed to lookup VMA\n"); | |
132 | ret = PTR_ERR(vma); | |
133 | goto out; | |
134 | } | |
135 | ||
136 | list_add_tail(&vma->exec_list, &eb->vmas); | |
137 | ||
138 | vma->exec_entry = &exec[i]; | |
eef90ccb | 139 | if (eb->and < 0) { |
27173f1f | 140 | eb->lut[i] = vma; |
eef90ccb CW |
141 | } else { |
142 | uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle; | |
27173f1f BW |
143 | vma->exec_handle = handle; |
144 | hlist_add_head(&vma->exec_node, | |
eef90ccb CW |
145 | &eb->buckets[handle & eb->and]); |
146 | } | |
27173f1f | 147 | ++i; |
3b96eff4 | 148 | } |
3b96eff4 | 149 | |
27173f1f BW |
150 | |
151 | out: | |
152 | while (!list_empty(&objects)) { | |
153 | obj = list_first_entry(&objects, | |
154 | struct drm_i915_gem_object, | |
155 | obj_exec_link); | |
156 | list_del_init(&obj->obj_exec_link); | |
157 | if (ret) | |
158 | drm_gem_object_unreference(&obj->base); | |
159 | } | |
160 | return ret; | |
3b96eff4 CW |
161 | } |
162 | ||
27173f1f | 163 | static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle) |
67731b87 | 164 | { |
eef90ccb CW |
165 | if (eb->and < 0) { |
166 | if (handle >= -eb->and) | |
167 | return NULL; | |
168 | return eb->lut[handle]; | |
169 | } else { | |
170 | struct hlist_head *head; | |
171 | struct hlist_node *node; | |
67731b87 | 172 | |
eef90ccb CW |
173 | head = &eb->buckets[handle & eb->and]; |
174 | hlist_for_each(node, head) { | |
27173f1f | 175 | struct i915_vma *vma; |
67731b87 | 176 | |
27173f1f BW |
177 | vma = hlist_entry(node, struct i915_vma, exec_node); |
178 | if (vma->exec_handle == handle) | |
179 | return vma; | |
eef90ccb CW |
180 | } |
181 | return NULL; | |
182 | } | |
67731b87 CW |
183 | } |
184 | ||
27173f1f BW |
185 | static void eb_destroy(struct eb_vmas *eb) { |
186 | while (!list_empty(&eb->vmas)) { | |
187 | struct i915_vma *vma; | |
bcffc3fa | 188 | |
27173f1f BW |
189 | vma = list_first_entry(&eb->vmas, |
190 | struct i915_vma, | |
bcffc3fa | 191 | exec_list); |
27173f1f BW |
192 | list_del_init(&vma->exec_list); |
193 | drm_gem_object_unreference(&vma->obj->base); | |
bcffc3fa | 194 | } |
67731b87 CW |
195 | kfree(eb); |
196 | } | |
197 | ||
dabdfe02 CW |
198 | static inline int use_cpu_reloc(struct drm_i915_gem_object *obj) |
199 | { | |
200 | return (obj->base.write_domain == I915_GEM_DOMAIN_CPU || | |
504c7267 | 201 | !obj->map_and_fenceable || |
dabdfe02 CW |
202 | obj->cache_level != I915_CACHE_NONE); |
203 | } | |
204 | ||
5032d871 RB |
205 | static int |
206 | relocate_entry_cpu(struct drm_i915_gem_object *obj, | |
207 | struct drm_i915_gem_relocation_entry *reloc) | |
208 | { | |
209 | uint32_t page_offset = offset_in_page(reloc->offset); | |
210 | char *vaddr; | |
211 | int ret = -EINVAL; | |
212 | ||
213 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); | |
214 | if (ret) | |
215 | return ret; | |
216 | ||
217 | vaddr = kmap_atomic(i915_gem_object_get_page(obj, | |
218 | reloc->offset >> PAGE_SHIFT)); | |
219 | *(uint32_t *)(vaddr + page_offset) = reloc->delta; | |
220 | kunmap_atomic(vaddr); | |
221 | ||
222 | return 0; | |
223 | } | |
224 | ||
225 | static int | |
226 | relocate_entry_gtt(struct drm_i915_gem_object *obj, | |
227 | struct drm_i915_gem_relocation_entry *reloc) | |
228 | { | |
229 | struct drm_device *dev = obj->base.dev; | |
230 | struct drm_i915_private *dev_priv = dev->dev_private; | |
231 | uint32_t __iomem *reloc_entry; | |
232 | void __iomem *reloc_page; | |
233 | int ret = -EINVAL; | |
234 | ||
235 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
236 | if (ret) | |
237 | return ret; | |
238 | ||
239 | ret = i915_gem_object_put_fence(obj); | |
240 | if (ret) | |
241 | return ret; | |
242 | ||
243 | /* Map the page containing the relocation we're going to perform. */ | |
244 | reloc->offset += i915_gem_obj_ggtt_offset(obj); | |
245 | reloc_page = io_mapping_map_atomic_wc(dev_priv->gtt.mappable, | |
246 | reloc->offset & PAGE_MASK); | |
247 | reloc_entry = (uint32_t __iomem *) | |
248 | (reloc_page + offset_in_page(reloc->offset)); | |
249 | iowrite32(reloc->delta, reloc_entry); | |
250 | io_mapping_unmap_atomic(reloc_page); | |
251 | ||
252 | return 0; | |
253 | } | |
254 | ||
54cf91dc CW |
255 | static int |
256 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, | |
27173f1f | 257 | struct eb_vmas *eb, |
28d6a7bf BW |
258 | struct drm_i915_gem_relocation_entry *reloc, |
259 | struct i915_address_space *vm) | |
54cf91dc CW |
260 | { |
261 | struct drm_device *dev = obj->base.dev; | |
262 | struct drm_gem_object *target_obj; | |
149c8407 | 263 | struct drm_i915_gem_object *target_i915_obj; |
27173f1f | 264 | struct i915_vma *target_vma; |
54cf91dc CW |
265 | uint32_t target_offset; |
266 | int ret = -EINVAL; | |
267 | ||
67731b87 | 268 | /* we've already hold a reference to all valid objects */ |
27173f1f BW |
269 | target_vma = eb_get_vma(eb, reloc->target_handle); |
270 | if (unlikely(target_vma == NULL)) | |
54cf91dc | 271 | return -ENOENT; |
27173f1f BW |
272 | target_i915_obj = target_vma->obj; |
273 | target_obj = &target_vma->obj->base; | |
54cf91dc | 274 | |
f343c5f6 | 275 | target_offset = i915_gem_obj_ggtt_offset(target_i915_obj); |
54cf91dc | 276 | |
e844b990 EA |
277 | /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and |
278 | * pipe_control writes because the gpu doesn't properly redirect them | |
279 | * through the ppgtt for non_secure batchbuffers. */ | |
280 | if (unlikely(IS_GEN6(dev) && | |
281 | reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION && | |
282 | !target_i915_obj->has_global_gtt_mapping)) { | |
283 | i915_gem_gtt_bind_object(target_i915_obj, | |
284 | target_i915_obj->cache_level); | |
285 | } | |
286 | ||
54cf91dc | 287 | /* Validate that the target is in a valid r/w GPU domain */ |
b8f7ab17 | 288 | if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { |
ff240199 | 289 | DRM_DEBUG("reloc with multiple write domains: " |
54cf91dc CW |
290 | "obj %p target %d offset %d " |
291 | "read %08x write %08x", | |
292 | obj, reloc->target_handle, | |
293 | (int) reloc->offset, | |
294 | reloc->read_domains, | |
295 | reloc->write_domain); | |
67731b87 | 296 | return ret; |
54cf91dc | 297 | } |
4ca4a250 DV |
298 | if (unlikely((reloc->write_domain | reloc->read_domains) |
299 | & ~I915_GEM_GPU_DOMAINS)) { | |
ff240199 | 300 | DRM_DEBUG("reloc with read/write non-GPU domains: " |
54cf91dc CW |
301 | "obj %p target %d offset %d " |
302 | "read %08x write %08x", | |
303 | obj, reloc->target_handle, | |
304 | (int) reloc->offset, | |
305 | reloc->read_domains, | |
306 | reloc->write_domain); | |
67731b87 | 307 | return ret; |
54cf91dc | 308 | } |
54cf91dc CW |
309 | |
310 | target_obj->pending_read_domains |= reloc->read_domains; | |
311 | target_obj->pending_write_domain |= reloc->write_domain; | |
312 | ||
313 | /* If the relocation already has the right value in it, no | |
314 | * more work needs to be done. | |
315 | */ | |
316 | if (target_offset == reloc->presumed_offset) | |
67731b87 | 317 | return 0; |
54cf91dc CW |
318 | |
319 | /* Check that the relocation address is valid... */ | |
b8f7ab17 | 320 | if (unlikely(reloc->offset > obj->base.size - 4)) { |
ff240199 | 321 | DRM_DEBUG("Relocation beyond object bounds: " |
54cf91dc CW |
322 | "obj %p target %d offset %d size %d.\n", |
323 | obj, reloc->target_handle, | |
324 | (int) reloc->offset, | |
325 | (int) obj->base.size); | |
67731b87 | 326 | return ret; |
54cf91dc | 327 | } |
b8f7ab17 | 328 | if (unlikely(reloc->offset & 3)) { |
ff240199 | 329 | DRM_DEBUG("Relocation not 4-byte aligned: " |
54cf91dc CW |
330 | "obj %p target %d offset %d.\n", |
331 | obj, reloc->target_handle, | |
332 | (int) reloc->offset); | |
67731b87 | 333 | return ret; |
54cf91dc CW |
334 | } |
335 | ||
dabdfe02 CW |
336 | /* We can't wait for rendering with pagefaults disabled */ |
337 | if (obj->active && in_atomic()) | |
338 | return -EFAULT; | |
339 | ||
54cf91dc | 340 | reloc->delta += target_offset; |
5032d871 RB |
341 | if (use_cpu_reloc(obj)) |
342 | ret = relocate_entry_cpu(obj, reloc); | |
343 | else | |
344 | ret = relocate_entry_gtt(obj, reloc); | |
54cf91dc | 345 | |
d4d36014 DV |
346 | if (ret) |
347 | return ret; | |
348 | ||
54cf91dc CW |
349 | /* and update the user's relocation entry */ |
350 | reloc->presumed_offset = target_offset; | |
351 | ||
67731b87 | 352 | return 0; |
54cf91dc CW |
353 | } |
354 | ||
355 | static int | |
27173f1f BW |
356 | i915_gem_execbuffer_relocate_vma(struct i915_vma *vma, |
357 | struct eb_vmas *eb) | |
54cf91dc | 358 | { |
1d83f442 CW |
359 | #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) |
360 | struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)]; | |
54cf91dc | 361 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
27173f1f | 362 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
1d83f442 | 363 | int remain, ret; |
54cf91dc | 364 | |
2bb4629a | 365 | user_relocs = to_user_ptr(entry->relocs_ptr); |
54cf91dc | 366 | |
1d83f442 CW |
367 | remain = entry->relocation_count; |
368 | while (remain) { | |
369 | struct drm_i915_gem_relocation_entry *r = stack_reloc; | |
370 | int count = remain; | |
371 | if (count > ARRAY_SIZE(stack_reloc)) | |
372 | count = ARRAY_SIZE(stack_reloc); | |
373 | remain -= count; | |
374 | ||
375 | if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0]))) | |
54cf91dc CW |
376 | return -EFAULT; |
377 | ||
1d83f442 CW |
378 | do { |
379 | u64 offset = r->presumed_offset; | |
54cf91dc | 380 | |
27173f1f BW |
381 | ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r, |
382 | vma->vm); | |
1d83f442 CW |
383 | if (ret) |
384 | return ret; | |
385 | ||
386 | if (r->presumed_offset != offset && | |
387 | __copy_to_user_inatomic(&user_relocs->presumed_offset, | |
388 | &r->presumed_offset, | |
389 | sizeof(r->presumed_offset))) { | |
390 | return -EFAULT; | |
391 | } | |
392 | ||
393 | user_relocs++; | |
394 | r++; | |
395 | } while (--count); | |
54cf91dc CW |
396 | } |
397 | ||
398 | return 0; | |
1d83f442 | 399 | #undef N_RELOC |
54cf91dc CW |
400 | } |
401 | ||
402 | static int | |
27173f1f BW |
403 | i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma, |
404 | struct eb_vmas *eb, | |
405 | struct drm_i915_gem_relocation_entry *relocs) | |
54cf91dc | 406 | { |
27173f1f | 407 | const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
54cf91dc CW |
408 | int i, ret; |
409 | ||
410 | for (i = 0; i < entry->relocation_count; i++) { | |
27173f1f BW |
411 | ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i], |
412 | vma->vm); | |
54cf91dc CW |
413 | if (ret) |
414 | return ret; | |
415 | } | |
416 | ||
417 | return 0; | |
418 | } | |
419 | ||
420 | static int | |
27173f1f | 421 | i915_gem_execbuffer_relocate(struct eb_vmas *eb, |
28d6a7bf | 422 | struct i915_address_space *vm) |
54cf91dc | 423 | { |
27173f1f | 424 | struct i915_vma *vma; |
d4aeee77 CW |
425 | int ret = 0; |
426 | ||
427 | /* This is the fast path and we cannot handle a pagefault whilst | |
428 | * holding the struct mutex lest the user pass in the relocations | |
429 | * contained within a mmaped bo. For in such a case we, the page | |
430 | * fault handler would call i915_gem_fault() and we would try to | |
431 | * acquire the struct mutex again. Obviously this is bad and so | |
432 | * lockdep complains vehemently. | |
433 | */ | |
434 | pagefault_disable(); | |
27173f1f BW |
435 | list_for_each_entry(vma, &eb->vmas, exec_list) { |
436 | ret = i915_gem_execbuffer_relocate_vma(vma, eb); | |
54cf91dc | 437 | if (ret) |
d4aeee77 | 438 | break; |
54cf91dc | 439 | } |
d4aeee77 | 440 | pagefault_enable(); |
54cf91dc | 441 | |
d4aeee77 | 442 | return ret; |
54cf91dc CW |
443 | } |
444 | ||
7788a765 CW |
445 | #define __EXEC_OBJECT_HAS_PIN (1<<31) |
446 | #define __EXEC_OBJECT_HAS_FENCE (1<<30) | |
1690e1eb | 447 | |
dabdfe02 | 448 | static int |
27173f1f | 449 | need_reloc_mappable(struct i915_vma *vma) |
dabdfe02 | 450 | { |
27173f1f BW |
451 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
452 | return entry->relocation_count && !use_cpu_reloc(vma->obj) && | |
453 | i915_is_ggtt(vma->vm); | |
dabdfe02 CW |
454 | } |
455 | ||
1690e1eb | 456 | static int |
27173f1f BW |
457 | i915_gem_execbuffer_reserve_vma(struct i915_vma *vma, |
458 | struct intel_ring_buffer *ring, | |
459 | bool *need_reloc) | |
1690e1eb | 460 | { |
27173f1f BW |
461 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
462 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; | |
1690e1eb CW |
463 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; |
464 | bool need_fence, need_mappable; | |
27173f1f | 465 | struct drm_i915_gem_object *obj = vma->obj; |
1690e1eb CW |
466 | int ret; |
467 | ||
468 | need_fence = | |
469 | has_fenced_gpu_access && | |
470 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
471 | obj->tiling_mode != I915_TILING_NONE; | |
27173f1f | 472 | need_mappable = need_fence || need_reloc_mappable(vma); |
1690e1eb | 473 | |
27173f1f | 474 | ret = i915_gem_object_pin(obj, vma->vm, entry->alignment, need_mappable, |
28d6a7bf | 475 | false); |
1690e1eb CW |
476 | if (ret) |
477 | return ret; | |
478 | ||
7788a765 CW |
479 | entry->flags |= __EXEC_OBJECT_HAS_PIN; |
480 | ||
1690e1eb CW |
481 | if (has_fenced_gpu_access) { |
482 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { | |
06d98131 | 483 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 | 484 | if (ret) |
7788a765 | 485 | return ret; |
1690e1eb | 486 | |
9a5a53b3 | 487 | if (i915_gem_object_pin_fence(obj)) |
1690e1eb | 488 | entry->flags |= __EXEC_OBJECT_HAS_FENCE; |
9a5a53b3 | 489 | |
7dd49065 | 490 | obj->pending_fenced_gpu_access = true; |
1690e1eb | 491 | } |
1690e1eb CW |
492 | } |
493 | ||
7788a765 CW |
494 | /* Ensure ppgtt mapping exists if needed */ |
495 | if (dev_priv->mm.aliasing_ppgtt && !obj->has_aliasing_ppgtt_mapping) { | |
496 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
497 | obj, obj->cache_level); | |
498 | ||
499 | obj->has_aliasing_ppgtt_mapping = 1; | |
500 | } | |
501 | ||
27173f1f BW |
502 | if (entry->offset != vma->node.start) { |
503 | entry->offset = vma->node.start; | |
ed5982e6 DV |
504 | *need_reloc = true; |
505 | } | |
506 | ||
507 | if (entry->flags & EXEC_OBJECT_WRITE) { | |
508 | obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER; | |
509 | obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER; | |
510 | } | |
511 | ||
512 | if (entry->flags & EXEC_OBJECT_NEEDS_GTT && | |
513 | !obj->has_global_gtt_mapping) | |
514 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
515 | ||
1690e1eb | 516 | return 0; |
7788a765 | 517 | } |
1690e1eb | 518 | |
7788a765 | 519 | static void |
27173f1f | 520 | i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma) |
7788a765 CW |
521 | { |
522 | struct drm_i915_gem_exec_object2 *entry; | |
27173f1f | 523 | struct drm_i915_gem_object *obj = vma->obj; |
7788a765 | 524 | |
27173f1f | 525 | if (!drm_mm_node_allocated(&vma->node)) |
7788a765 CW |
526 | return; |
527 | ||
27173f1f | 528 | entry = vma->exec_entry; |
7788a765 CW |
529 | |
530 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) | |
531 | i915_gem_object_unpin_fence(obj); | |
532 | ||
533 | if (entry->flags & __EXEC_OBJECT_HAS_PIN) | |
534 | i915_gem_object_unpin(obj); | |
535 | ||
536 | entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN); | |
1690e1eb CW |
537 | } |
538 | ||
54cf91dc | 539 | static int |
d9e86c0e | 540 | i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring, |
27173f1f | 541 | struct list_head *vmas, |
ed5982e6 | 542 | bool *need_relocs) |
54cf91dc | 543 | { |
432e58ed | 544 | struct drm_i915_gem_object *obj; |
27173f1f BW |
545 | struct i915_vma *vma; |
546 | struct list_head ordered_vmas; | |
7788a765 CW |
547 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; |
548 | int retry; | |
6fe4f140 | 549 | |
27173f1f BW |
550 | INIT_LIST_HEAD(&ordered_vmas); |
551 | while (!list_empty(vmas)) { | |
6fe4f140 CW |
552 | struct drm_i915_gem_exec_object2 *entry; |
553 | bool need_fence, need_mappable; | |
554 | ||
27173f1f BW |
555 | vma = list_first_entry(vmas, struct i915_vma, exec_list); |
556 | obj = vma->obj; | |
557 | entry = vma->exec_entry; | |
6fe4f140 CW |
558 | |
559 | need_fence = | |
560 | has_fenced_gpu_access && | |
561 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
562 | obj->tiling_mode != I915_TILING_NONE; | |
27173f1f | 563 | need_mappable = need_fence || need_reloc_mappable(vma); |
6fe4f140 CW |
564 | |
565 | if (need_mappable) | |
27173f1f | 566 | list_move(&vma->exec_list, &ordered_vmas); |
6fe4f140 | 567 | else |
27173f1f | 568 | list_move_tail(&vma->exec_list, &ordered_vmas); |
595dad76 | 569 | |
ed5982e6 | 570 | obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND; |
595dad76 | 571 | obj->base.pending_write_domain = 0; |
016fd0c1 | 572 | obj->pending_fenced_gpu_access = false; |
6fe4f140 | 573 | } |
27173f1f | 574 | list_splice(&ordered_vmas, vmas); |
54cf91dc CW |
575 | |
576 | /* Attempt to pin all of the buffers into the GTT. | |
577 | * This is done in 3 phases: | |
578 | * | |
579 | * 1a. Unbind all objects that do not match the GTT constraints for | |
580 | * the execbuffer (fenceable, mappable, alignment etc). | |
581 | * 1b. Increment pin count for already bound objects. | |
582 | * 2. Bind new objects. | |
583 | * 3. Decrement pin count. | |
584 | * | |
7788a765 | 585 | * This avoid unnecessary unbinding of later objects in order to make |
54cf91dc CW |
586 | * room for the earlier objects *unless* we need to defragment. |
587 | */ | |
588 | retry = 0; | |
589 | do { | |
7788a765 | 590 | int ret = 0; |
54cf91dc CW |
591 | |
592 | /* Unbind any ill-fitting objects or pin. */ | |
27173f1f BW |
593 | list_for_each_entry(vma, vmas, exec_list) { |
594 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; | |
54cf91dc | 595 | bool need_fence, need_mappable; |
1690e1eb | 596 | |
27173f1f BW |
597 | obj = vma->obj; |
598 | ||
599 | if (!drm_mm_node_allocated(&vma->node)) | |
54cf91dc CW |
600 | continue; |
601 | ||
602 | need_fence = | |
9b3826bf | 603 | has_fenced_gpu_access && |
54cf91dc CW |
604 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
605 | obj->tiling_mode != I915_TILING_NONE; | |
27173f1f | 606 | need_mappable = need_fence || need_reloc_mappable(vma); |
54cf91dc | 607 | |
28d6a7bf | 608 | WARN_ON((need_mappable || need_fence) && |
27173f1f | 609 | !i915_is_ggtt(vma->vm)); |
28d6a7bf | 610 | |
f343c5f6 | 611 | if ((entry->alignment && |
27173f1f | 612 | vma->node.start & (entry->alignment - 1)) || |
54cf91dc | 613 | (need_mappable && !obj->map_and_fenceable)) |
27173f1f | 614 | ret = i915_vma_unbind(vma); |
54cf91dc | 615 | else |
27173f1f | 616 | ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs); |
432e58ed | 617 | if (ret) |
54cf91dc | 618 | goto err; |
54cf91dc CW |
619 | } |
620 | ||
621 | /* Bind fresh objects */ | |
27173f1f BW |
622 | list_for_each_entry(vma, vmas, exec_list) { |
623 | if (drm_mm_node_allocated(&vma->node)) | |
1690e1eb | 624 | continue; |
54cf91dc | 625 | |
27173f1f | 626 | ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs); |
7788a765 CW |
627 | if (ret) |
628 | goto err; | |
54cf91dc CW |
629 | } |
630 | ||
7788a765 | 631 | err: /* Decrement pin count for bound objects */ |
27173f1f BW |
632 | list_for_each_entry(vma, vmas, exec_list) |
633 | i915_gem_execbuffer_unreserve_vma(vma); | |
54cf91dc | 634 | |
6c085a72 | 635 | if (ret != -ENOSPC || retry++) |
54cf91dc CW |
636 | return ret; |
637 | ||
6c085a72 | 638 | ret = i915_gem_evict_everything(ring->dev); |
54cf91dc CW |
639 | if (ret) |
640 | return ret; | |
54cf91dc CW |
641 | } while (1); |
642 | } | |
643 | ||
644 | static int | |
645 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, | |
ed5982e6 | 646 | struct drm_i915_gem_execbuffer2 *args, |
54cf91dc | 647 | struct drm_file *file, |
d9e86c0e | 648 | struct intel_ring_buffer *ring, |
27173f1f BW |
649 | struct eb_vmas *eb, |
650 | struct drm_i915_gem_exec_object2 *exec) | |
54cf91dc CW |
651 | { |
652 | struct drm_i915_gem_relocation_entry *reloc; | |
27173f1f BW |
653 | struct i915_address_space *vm; |
654 | struct i915_vma *vma; | |
ed5982e6 | 655 | bool need_relocs; |
dd6864a4 | 656 | int *reloc_offset; |
54cf91dc | 657 | int i, total, ret; |
ed5982e6 | 658 | int count = args->buffer_count; |
54cf91dc | 659 | |
27173f1f BW |
660 | if (WARN_ON(list_empty(&eb->vmas))) |
661 | return 0; | |
662 | ||
663 | vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm; | |
664 | ||
67731b87 | 665 | /* We may process another execbuffer during the unlock... */ |
27173f1f BW |
666 | while (!list_empty(&eb->vmas)) { |
667 | vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list); | |
668 | list_del_init(&vma->exec_list); | |
669 | drm_gem_object_unreference(&vma->obj->base); | |
67731b87 CW |
670 | } |
671 | ||
54cf91dc CW |
672 | mutex_unlock(&dev->struct_mutex); |
673 | ||
674 | total = 0; | |
675 | for (i = 0; i < count; i++) | |
432e58ed | 676 | total += exec[i].relocation_count; |
54cf91dc | 677 | |
dd6864a4 | 678 | reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset)); |
54cf91dc | 679 | reloc = drm_malloc_ab(total, sizeof(*reloc)); |
dd6864a4 CW |
680 | if (reloc == NULL || reloc_offset == NULL) { |
681 | drm_free_large(reloc); | |
682 | drm_free_large(reloc_offset); | |
54cf91dc CW |
683 | mutex_lock(&dev->struct_mutex); |
684 | return -ENOMEM; | |
685 | } | |
686 | ||
687 | total = 0; | |
688 | for (i = 0; i < count; i++) { | |
689 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
262b6d36 CW |
690 | u64 invalid_offset = (u64)-1; |
691 | int j; | |
54cf91dc | 692 | |
2bb4629a | 693 | user_relocs = to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
694 | |
695 | if (copy_from_user(reloc+total, user_relocs, | |
432e58ed | 696 | exec[i].relocation_count * sizeof(*reloc))) { |
54cf91dc CW |
697 | ret = -EFAULT; |
698 | mutex_lock(&dev->struct_mutex); | |
699 | goto err; | |
700 | } | |
701 | ||
262b6d36 CW |
702 | /* As we do not update the known relocation offsets after |
703 | * relocating (due to the complexities in lock handling), | |
704 | * we need to mark them as invalid now so that we force the | |
705 | * relocation processing next time. Just in case the target | |
706 | * object is evicted and then rebound into its old | |
707 | * presumed_offset before the next execbuffer - if that | |
708 | * happened we would make the mistake of assuming that the | |
709 | * relocations were valid. | |
710 | */ | |
711 | for (j = 0; j < exec[i].relocation_count; j++) { | |
712 | if (copy_to_user(&user_relocs[j].presumed_offset, | |
713 | &invalid_offset, | |
714 | sizeof(invalid_offset))) { | |
715 | ret = -EFAULT; | |
716 | mutex_lock(&dev->struct_mutex); | |
717 | goto err; | |
718 | } | |
719 | } | |
720 | ||
dd6864a4 | 721 | reloc_offset[i] = total; |
432e58ed | 722 | total += exec[i].relocation_count; |
54cf91dc CW |
723 | } |
724 | ||
725 | ret = i915_mutex_lock_interruptible(dev); | |
726 | if (ret) { | |
727 | mutex_lock(&dev->struct_mutex); | |
728 | goto err; | |
729 | } | |
730 | ||
67731b87 | 731 | /* reacquire the objects */ |
67731b87 | 732 | eb_reset(eb); |
27173f1f | 733 | ret = eb_lookup_vmas(eb, exec, args, vm, file); |
3b96eff4 CW |
734 | if (ret) |
735 | goto err; | |
67731b87 | 736 | |
ed5982e6 | 737 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
27173f1f | 738 | ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, &need_relocs); |
54cf91dc CW |
739 | if (ret) |
740 | goto err; | |
741 | ||
27173f1f BW |
742 | list_for_each_entry(vma, &eb->vmas, exec_list) { |
743 | int offset = vma->exec_entry - exec; | |
744 | ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb, | |
745 | reloc + reloc_offset[offset]); | |
54cf91dc CW |
746 | if (ret) |
747 | goto err; | |
54cf91dc CW |
748 | } |
749 | ||
750 | /* Leave the user relocations as are, this is the painfully slow path, | |
751 | * and we want to avoid the complication of dropping the lock whilst | |
752 | * having buffers reserved in the aperture and so causing spurious | |
753 | * ENOSPC for random operations. | |
754 | */ | |
755 | ||
756 | err: | |
757 | drm_free_large(reloc); | |
dd6864a4 | 758 | drm_free_large(reloc_offset); |
54cf91dc CW |
759 | return ret; |
760 | } | |
761 | ||
54cf91dc | 762 | static int |
432e58ed | 763 | i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring, |
27173f1f | 764 | struct list_head *vmas) |
54cf91dc | 765 | { |
27173f1f | 766 | struct i915_vma *vma; |
6ac42f41 | 767 | uint32_t flush_domains = 0; |
000433b6 | 768 | bool flush_chipset = false; |
432e58ed | 769 | int ret; |
54cf91dc | 770 | |
27173f1f BW |
771 | list_for_each_entry(vma, vmas, exec_list) { |
772 | struct drm_i915_gem_object *obj = vma->obj; | |
6ac42f41 | 773 | ret = i915_gem_object_sync(obj, ring); |
c59a333f CW |
774 | if (ret) |
775 | return ret; | |
6ac42f41 DV |
776 | |
777 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) | |
000433b6 | 778 | flush_chipset |= i915_gem_clflush_object(obj, false); |
6ac42f41 | 779 | |
6ac42f41 | 780 | flush_domains |= obj->base.write_domain; |
c59a333f CW |
781 | } |
782 | ||
000433b6 | 783 | if (flush_chipset) |
e76e9aeb | 784 | i915_gem_chipset_flush(ring->dev); |
6ac42f41 DV |
785 | |
786 | if (flush_domains & I915_GEM_DOMAIN_GTT) | |
787 | wmb(); | |
788 | ||
09cf7c9a CW |
789 | /* Unconditionally invalidate gpu caches and ensure that we do flush |
790 | * any residual writes from the previous batch. | |
791 | */ | |
a7b9761d | 792 | return intel_ring_invalidate_all_caches(ring); |
54cf91dc CW |
793 | } |
794 | ||
432e58ed CW |
795 | static bool |
796 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) | |
54cf91dc | 797 | { |
ed5982e6 DV |
798 | if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS) |
799 | return false; | |
800 | ||
432e58ed | 801 | return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0; |
54cf91dc CW |
802 | } |
803 | ||
804 | static int | |
805 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, | |
806 | int count) | |
807 | { | |
808 | int i; | |
3118a4f6 KC |
809 | int relocs_total = 0; |
810 | int relocs_max = INT_MAX / sizeof(struct drm_i915_gem_relocation_entry); | |
54cf91dc CW |
811 | |
812 | for (i = 0; i < count; i++) { | |
2bb4629a | 813 | char __user *ptr = to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
814 | int length; /* limited by fault_in_pages_readable() */ |
815 | ||
ed5982e6 DV |
816 | if (exec[i].flags & __EXEC_OBJECT_UNKNOWN_FLAGS) |
817 | return -EINVAL; | |
818 | ||
3118a4f6 KC |
819 | /* First check for malicious input causing overflow in |
820 | * the worst case where we need to allocate the entire | |
821 | * relocation tree as a single array. | |
822 | */ | |
823 | if (exec[i].relocation_count > relocs_max - relocs_total) | |
54cf91dc | 824 | return -EINVAL; |
3118a4f6 | 825 | relocs_total += exec[i].relocation_count; |
54cf91dc CW |
826 | |
827 | length = exec[i].relocation_count * | |
828 | sizeof(struct drm_i915_gem_relocation_entry); | |
30587535 KC |
829 | /* |
830 | * We must check that the entire relocation array is safe | |
831 | * to read, but since we may need to update the presumed | |
832 | * offsets during execution, check for full write access. | |
833 | */ | |
54cf91dc CW |
834 | if (!access_ok(VERIFY_WRITE, ptr, length)) |
835 | return -EFAULT; | |
836 | ||
0b74b508 XZ |
837 | if (likely(!i915_prefault_disable)) { |
838 | if (fault_in_multipages_readable(ptr, length)) | |
839 | return -EFAULT; | |
840 | } | |
54cf91dc CW |
841 | } |
842 | ||
843 | return 0; | |
844 | } | |
845 | ||
432e58ed | 846 | static void |
27173f1f | 847 | i915_gem_execbuffer_move_to_active(struct list_head *vmas, |
9d773091 | 848 | struct intel_ring_buffer *ring) |
432e58ed | 849 | { |
27173f1f | 850 | struct i915_vma *vma; |
432e58ed | 851 | |
27173f1f BW |
852 | list_for_each_entry(vma, vmas, exec_list) { |
853 | struct drm_i915_gem_object *obj = vma->obj; | |
69c2fc89 CW |
854 | u32 old_read = obj->base.read_domains; |
855 | u32 old_write = obj->base.write_domain; | |
db53a302 | 856 | |
432e58ed | 857 | obj->base.write_domain = obj->base.pending_write_domain; |
ed5982e6 DV |
858 | if (obj->base.write_domain == 0) |
859 | obj->base.pending_read_domains |= obj->base.read_domains; | |
860 | obj->base.read_domains = obj->base.pending_read_domains; | |
432e58ed CW |
861 | obj->fenced_gpu_access = obj->pending_fenced_gpu_access; |
862 | ||
27173f1f | 863 | list_move_tail(&vma->mm_list, &vma->vm->active_list); |
9d773091 | 864 | i915_gem_object_move_to_active(obj, ring); |
432e58ed CW |
865 | if (obj->base.write_domain) { |
866 | obj->dirty = 1; | |
9d773091 | 867 | obj->last_write_seqno = intel_ring_get_seqno(ring); |
acb87dfb | 868 | if (obj->pin_count) /* check for potential scanout */ |
c65355bb | 869 | intel_mark_fb_busy(obj, ring); |
432e58ed CW |
870 | } |
871 | ||
db53a302 | 872 | trace_i915_gem_object_change_domain(obj, old_read, old_write); |
432e58ed CW |
873 | } |
874 | } | |
875 | ||
54cf91dc CW |
876 | static void |
877 | i915_gem_execbuffer_retire_commands(struct drm_device *dev, | |
432e58ed | 878 | struct drm_file *file, |
7d736f4f MK |
879 | struct intel_ring_buffer *ring, |
880 | struct drm_i915_gem_object *obj) | |
54cf91dc | 881 | { |
cc889e0f DV |
882 | /* Unconditionally force add_request to emit a full flush. */ |
883 | ring->gpu_caches_dirty = true; | |
54cf91dc | 884 | |
432e58ed | 885 | /* Add a breadcrumb for the completion of the batch buffer */ |
7d736f4f | 886 | (void)__i915_add_request(ring, file, obj, NULL); |
432e58ed | 887 | } |
54cf91dc | 888 | |
ae662d31 EA |
889 | static int |
890 | i915_reset_gen7_sol_offsets(struct drm_device *dev, | |
891 | struct intel_ring_buffer *ring) | |
892 | { | |
893 | drm_i915_private_t *dev_priv = dev->dev_private; | |
894 | int ret, i; | |
895 | ||
896 | if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) | |
897 | return 0; | |
898 | ||
899 | ret = intel_ring_begin(ring, 4 * 3); | |
900 | if (ret) | |
901 | return ret; | |
902 | ||
903 | for (i = 0; i < 4; i++) { | |
904 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
905 | intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i)); | |
906 | intel_ring_emit(ring, 0); | |
907 | } | |
908 | ||
909 | intel_ring_advance(ring); | |
910 | ||
911 | return 0; | |
912 | } | |
913 | ||
54cf91dc CW |
914 | static int |
915 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, | |
916 | struct drm_file *file, | |
917 | struct drm_i915_gem_execbuffer2 *args, | |
28d6a7bf BW |
918 | struct drm_i915_gem_exec_object2 *exec, |
919 | struct i915_address_space *vm) | |
54cf91dc CW |
920 | { |
921 | drm_i915_private_t *dev_priv = dev->dev_private; | |
27173f1f | 922 | struct eb_vmas *eb; |
54cf91dc CW |
923 | struct drm_i915_gem_object *batch_obj; |
924 | struct drm_clip_rect *cliprects = NULL; | |
54cf91dc | 925 | struct intel_ring_buffer *ring; |
6e0a69db | 926 | u32 ctx_id = i915_execbuffer2_get_context_id(*args); |
c4e7a414 | 927 | u32 exec_start, exec_len; |
ed5982e6 | 928 | u32 mask, flags; |
72bfa19c | 929 | int ret, mode, i; |
ed5982e6 | 930 | bool need_relocs; |
54cf91dc | 931 | |
ed5982e6 | 932 | if (!i915_gem_check_execbuffer(args)) |
432e58ed | 933 | return -EINVAL; |
432e58ed CW |
934 | |
935 | ret = validate_exec_list(exec, args->buffer_count); | |
54cf91dc CW |
936 | if (ret) |
937 | return ret; | |
938 | ||
d7d4eedd CW |
939 | flags = 0; |
940 | if (args->flags & I915_EXEC_SECURE) { | |
941 | if (!file->is_master || !capable(CAP_SYS_ADMIN)) | |
942 | return -EPERM; | |
943 | ||
944 | flags |= I915_DISPATCH_SECURE; | |
945 | } | |
b45305fc DV |
946 | if (args->flags & I915_EXEC_IS_PINNED) |
947 | flags |= I915_DISPATCH_PINNED; | |
d7d4eedd | 948 | |
54cf91dc CW |
949 | switch (args->flags & I915_EXEC_RING_MASK) { |
950 | case I915_EXEC_DEFAULT: | |
951 | case I915_EXEC_RENDER: | |
1ec14ad3 | 952 | ring = &dev_priv->ring[RCS]; |
54cf91dc CW |
953 | break; |
954 | case I915_EXEC_BSD: | |
1ec14ad3 | 955 | ring = &dev_priv->ring[VCS]; |
e8520969 | 956 | if (ctx_id != DEFAULT_CONTEXT_ID) { |
6e0a69db BW |
957 | DRM_DEBUG("Ring %s doesn't support contexts\n", |
958 | ring->name); | |
959 | return -EPERM; | |
960 | } | |
54cf91dc CW |
961 | break; |
962 | case I915_EXEC_BLT: | |
1ec14ad3 | 963 | ring = &dev_priv->ring[BCS]; |
e8520969 | 964 | if (ctx_id != DEFAULT_CONTEXT_ID) { |
6e0a69db BW |
965 | DRM_DEBUG("Ring %s doesn't support contexts\n", |
966 | ring->name); | |
967 | return -EPERM; | |
968 | } | |
54cf91dc | 969 | break; |
82f91b6e XH |
970 | case I915_EXEC_VEBOX: |
971 | ring = &dev_priv->ring[VECS]; | |
e8520969 | 972 | if (ctx_id != DEFAULT_CONTEXT_ID) { |
82f91b6e XH |
973 | DRM_DEBUG("Ring %s doesn't support contexts\n", |
974 | ring->name); | |
975 | return -EPERM; | |
976 | } | |
977 | break; | |
978 | ||
54cf91dc | 979 | default: |
ff240199 | 980 | DRM_DEBUG("execbuf with unknown ring: %d\n", |
54cf91dc CW |
981 | (int)(args->flags & I915_EXEC_RING_MASK)); |
982 | return -EINVAL; | |
983 | } | |
a15817cf CW |
984 | if (!intel_ring_initialized(ring)) { |
985 | DRM_DEBUG("execbuf with invalid ring: %d\n", | |
986 | (int)(args->flags & I915_EXEC_RING_MASK)); | |
987 | return -EINVAL; | |
988 | } | |
54cf91dc | 989 | |
72bfa19c | 990 | mode = args->flags & I915_EXEC_CONSTANTS_MASK; |
84f9f938 | 991 | mask = I915_EXEC_CONSTANTS_MASK; |
72bfa19c CW |
992 | switch (mode) { |
993 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
994 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
995 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
996 | if (ring == &dev_priv->ring[RCS] && | |
997 | mode != dev_priv->relative_constants_mode) { | |
998 | if (INTEL_INFO(dev)->gen < 4) | |
999 | return -EINVAL; | |
1000 | ||
1001 | if (INTEL_INFO(dev)->gen > 5 && | |
1002 | mode == I915_EXEC_CONSTANTS_REL_SURFACE) | |
1003 | return -EINVAL; | |
84f9f938 BW |
1004 | |
1005 | /* The HW changed the meaning on this bit on gen6 */ | |
1006 | if (INTEL_INFO(dev)->gen >= 6) | |
1007 | mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
72bfa19c CW |
1008 | } |
1009 | break; | |
1010 | default: | |
ff240199 | 1011 | DRM_DEBUG("execbuf with unknown constants: %d\n", mode); |
72bfa19c CW |
1012 | return -EINVAL; |
1013 | } | |
1014 | ||
54cf91dc | 1015 | if (args->buffer_count < 1) { |
ff240199 | 1016 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1017 | return -EINVAL; |
1018 | } | |
54cf91dc CW |
1019 | |
1020 | if (args->num_cliprects != 0) { | |
1ec14ad3 | 1021 | if (ring != &dev_priv->ring[RCS]) { |
ff240199 | 1022 | DRM_DEBUG("clip rectangles are only valid with the render ring\n"); |
c4e7a414 CW |
1023 | return -EINVAL; |
1024 | } | |
1025 | ||
6ebebc92 DV |
1026 | if (INTEL_INFO(dev)->gen >= 5) { |
1027 | DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); | |
1028 | return -EINVAL; | |
1029 | } | |
1030 | ||
44afb3a0 XW |
1031 | if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) { |
1032 | DRM_DEBUG("execbuf with %u cliprects\n", | |
1033 | args->num_cliprects); | |
1034 | return -EINVAL; | |
1035 | } | |
5e13a0c5 | 1036 | |
432e58ed | 1037 | cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects), |
54cf91dc CW |
1038 | GFP_KERNEL); |
1039 | if (cliprects == NULL) { | |
1040 | ret = -ENOMEM; | |
1041 | goto pre_mutex_err; | |
1042 | } | |
1043 | ||
432e58ed | 1044 | if (copy_from_user(cliprects, |
2bb4629a VS |
1045 | to_user_ptr(args->cliprects_ptr), |
1046 | sizeof(*cliprects)*args->num_cliprects)) { | |
54cf91dc CW |
1047 | ret = -EFAULT; |
1048 | goto pre_mutex_err; | |
1049 | } | |
1050 | } | |
1051 | ||
54cf91dc CW |
1052 | ret = i915_mutex_lock_interruptible(dev); |
1053 | if (ret) | |
1054 | goto pre_mutex_err; | |
1055 | ||
db1b76ca | 1056 | if (dev_priv->ums.mm_suspended) { |
54cf91dc CW |
1057 | mutex_unlock(&dev->struct_mutex); |
1058 | ret = -EBUSY; | |
1059 | goto pre_mutex_err; | |
1060 | } | |
1061 | ||
27173f1f | 1062 | eb = eb_create(args, vm); |
67731b87 CW |
1063 | if (eb == NULL) { |
1064 | mutex_unlock(&dev->struct_mutex); | |
1065 | ret = -ENOMEM; | |
1066 | goto pre_mutex_err; | |
1067 | } | |
1068 | ||
54cf91dc | 1069 | /* Look up object handles */ |
27173f1f | 1070 | ret = eb_lookup_vmas(eb, exec, args, vm, file); |
3b96eff4 CW |
1071 | if (ret) |
1072 | goto err; | |
54cf91dc | 1073 | |
6fe4f140 | 1074 | /* take note of the batch buffer before we might reorder the lists */ |
27173f1f | 1075 | batch_obj = list_entry(eb->vmas.prev, struct i915_vma, exec_list)->obj; |
6fe4f140 | 1076 | |
54cf91dc | 1077 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
ed5982e6 | 1078 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
27173f1f | 1079 | ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, &need_relocs); |
54cf91dc CW |
1080 | if (ret) |
1081 | goto err; | |
1082 | ||
1083 | /* The objects are in their final locations, apply the relocations. */ | |
ed5982e6 | 1084 | if (need_relocs) |
28d6a7bf | 1085 | ret = i915_gem_execbuffer_relocate(eb, vm); |
54cf91dc CW |
1086 | if (ret) { |
1087 | if (ret == -EFAULT) { | |
ed5982e6 | 1088 | ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring, |
27173f1f | 1089 | eb, exec); |
54cf91dc CW |
1090 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
1091 | } | |
1092 | if (ret) | |
1093 | goto err; | |
1094 | } | |
1095 | ||
1096 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
54cf91dc | 1097 | if (batch_obj->base.pending_write_domain) { |
ff240199 | 1098 | DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); |
54cf91dc CW |
1099 | ret = -EINVAL; |
1100 | goto err; | |
1101 | } | |
1102 | batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
1103 | ||
d7d4eedd CW |
1104 | /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure |
1105 | * batch" bit. Hence we need to pin secure batches into the global gtt. | |
1106 | * hsw should have this fixed, but let's be paranoid and do it | |
1107 | * unconditionally for now. */ | |
1108 | if (flags & I915_DISPATCH_SECURE && !batch_obj->has_global_gtt_mapping) | |
1109 | i915_gem_gtt_bind_object(batch_obj, batch_obj->cache_level); | |
1110 | ||
27173f1f | 1111 | ret = i915_gem_execbuffer_move_to_gpu(ring, &eb->vmas); |
432e58ed | 1112 | if (ret) |
54cf91dc | 1113 | goto err; |
54cf91dc | 1114 | |
0da5cec1 EA |
1115 | ret = i915_switch_context(ring, file, ctx_id); |
1116 | if (ret) | |
1117 | goto err; | |
1118 | ||
e2971bda BW |
1119 | if (ring == &dev_priv->ring[RCS] && |
1120 | mode != dev_priv->relative_constants_mode) { | |
1121 | ret = intel_ring_begin(ring, 4); | |
1122 | if (ret) | |
1123 | goto err; | |
1124 | ||
1125 | intel_ring_emit(ring, MI_NOOP); | |
1126 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
1127 | intel_ring_emit(ring, INSTPM); | |
84f9f938 | 1128 | intel_ring_emit(ring, mask << 16 | mode); |
e2971bda BW |
1129 | intel_ring_advance(ring); |
1130 | ||
1131 | dev_priv->relative_constants_mode = mode; | |
1132 | } | |
1133 | ||
ae662d31 EA |
1134 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { |
1135 | ret = i915_reset_gen7_sol_offsets(dev, ring); | |
1136 | if (ret) | |
1137 | goto err; | |
1138 | } | |
1139 | ||
28d6a7bf BW |
1140 | exec_start = i915_gem_obj_offset(batch_obj, vm) + |
1141 | args->batch_start_offset; | |
c4e7a414 CW |
1142 | exec_len = args->batch_len; |
1143 | if (cliprects) { | |
1144 | for (i = 0; i < args->num_cliprects; i++) { | |
1145 | ret = i915_emit_box(dev, &cliprects[i], | |
1146 | args->DR1, args->DR4); | |
1147 | if (ret) | |
1148 | goto err; | |
1149 | ||
1150 | ret = ring->dispatch_execbuffer(ring, | |
d7d4eedd CW |
1151 | exec_start, exec_len, |
1152 | flags); | |
c4e7a414 CW |
1153 | if (ret) |
1154 | goto err; | |
1155 | } | |
1156 | } else { | |
d7d4eedd CW |
1157 | ret = ring->dispatch_execbuffer(ring, |
1158 | exec_start, exec_len, | |
1159 | flags); | |
c4e7a414 CW |
1160 | if (ret) |
1161 | goto err; | |
1162 | } | |
54cf91dc | 1163 | |
9d773091 CW |
1164 | trace_i915_gem_ring_dispatch(ring, intel_ring_get_seqno(ring), flags); |
1165 | ||
27173f1f | 1166 | i915_gem_execbuffer_move_to_active(&eb->vmas, ring); |
7d736f4f | 1167 | i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj); |
54cf91dc CW |
1168 | |
1169 | err: | |
67731b87 | 1170 | eb_destroy(eb); |
54cf91dc CW |
1171 | |
1172 | mutex_unlock(&dev->struct_mutex); | |
1173 | ||
1174 | pre_mutex_err: | |
54cf91dc | 1175 | kfree(cliprects); |
54cf91dc CW |
1176 | return ret; |
1177 | } | |
1178 | ||
1179 | /* | |
1180 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
1181 | * list array and passes it to the real function. | |
1182 | */ | |
1183 | int | |
1184 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1185 | struct drm_file *file) | |
1186 | { | |
28d6a7bf | 1187 | struct drm_i915_private *dev_priv = dev->dev_private; |
54cf91dc CW |
1188 | struct drm_i915_gem_execbuffer *args = data; |
1189 | struct drm_i915_gem_execbuffer2 exec2; | |
1190 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
1191 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1192 | int ret, i; | |
1193 | ||
54cf91dc | 1194 | if (args->buffer_count < 1) { |
ff240199 | 1195 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1196 | return -EINVAL; |
1197 | } | |
1198 | ||
1199 | /* Copy in the exec list from userland */ | |
1200 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
1201 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
1202 | if (exec_list == NULL || exec2_list == NULL) { | |
ff240199 | 1203 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1204 | args->buffer_count); |
1205 | drm_free_large(exec_list); | |
1206 | drm_free_large(exec2_list); | |
1207 | return -ENOMEM; | |
1208 | } | |
1209 | ret = copy_from_user(exec_list, | |
2bb4629a | 1210 | to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1211 | sizeof(*exec_list) * args->buffer_count); |
1212 | if (ret != 0) { | |
ff240199 | 1213 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1214 | args->buffer_count, ret); |
1215 | drm_free_large(exec_list); | |
1216 | drm_free_large(exec2_list); | |
1217 | return -EFAULT; | |
1218 | } | |
1219 | ||
1220 | for (i = 0; i < args->buffer_count; i++) { | |
1221 | exec2_list[i].handle = exec_list[i].handle; | |
1222 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
1223 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
1224 | exec2_list[i].alignment = exec_list[i].alignment; | |
1225 | exec2_list[i].offset = exec_list[i].offset; | |
1226 | if (INTEL_INFO(dev)->gen < 4) | |
1227 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; | |
1228 | else | |
1229 | exec2_list[i].flags = 0; | |
1230 | } | |
1231 | ||
1232 | exec2.buffers_ptr = args->buffers_ptr; | |
1233 | exec2.buffer_count = args->buffer_count; | |
1234 | exec2.batch_start_offset = args->batch_start_offset; | |
1235 | exec2.batch_len = args->batch_len; | |
1236 | exec2.DR1 = args->DR1; | |
1237 | exec2.DR4 = args->DR4; | |
1238 | exec2.num_cliprects = args->num_cliprects; | |
1239 | exec2.cliprects_ptr = args->cliprects_ptr; | |
1240 | exec2.flags = I915_EXEC_RENDER; | |
6e0a69db | 1241 | i915_execbuffer2_set_context_id(exec2, 0); |
54cf91dc | 1242 | |
28d6a7bf BW |
1243 | ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list, |
1244 | &dev_priv->gtt.base); | |
54cf91dc CW |
1245 | if (!ret) { |
1246 | /* Copy the new buffer offsets back to the user's exec list. */ | |
1247 | for (i = 0; i < args->buffer_count; i++) | |
1248 | exec_list[i].offset = exec2_list[i].offset; | |
1249 | /* ... and back out to userspace */ | |
2bb4629a | 1250 | ret = copy_to_user(to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1251 | exec_list, |
1252 | sizeof(*exec_list) * args->buffer_count); | |
1253 | if (ret) { | |
1254 | ret = -EFAULT; | |
ff240199 | 1255 | DRM_DEBUG("failed to copy %d exec entries " |
54cf91dc CW |
1256 | "back to user (%d)\n", |
1257 | args->buffer_count, ret); | |
1258 | } | |
1259 | } | |
1260 | ||
1261 | drm_free_large(exec_list); | |
1262 | drm_free_large(exec2_list); | |
1263 | return ret; | |
1264 | } | |
1265 | ||
1266 | int | |
1267 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
1268 | struct drm_file *file) | |
1269 | { | |
28d6a7bf | 1270 | struct drm_i915_private *dev_priv = dev->dev_private; |
54cf91dc CW |
1271 | struct drm_i915_gem_execbuffer2 *args = data; |
1272 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1273 | int ret; | |
1274 | ||
ed8cd3b2 XW |
1275 | if (args->buffer_count < 1 || |
1276 | args->buffer_count > UINT_MAX / sizeof(*exec2_list)) { | |
ff240199 | 1277 | DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1278 | return -EINVAL; |
1279 | } | |
1280 | ||
8408c282 | 1281 | exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count, |
419fa72a | 1282 | GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); |
8408c282 CW |
1283 | if (exec2_list == NULL) |
1284 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), | |
1285 | args->buffer_count); | |
54cf91dc | 1286 | if (exec2_list == NULL) { |
ff240199 | 1287 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1288 | args->buffer_count); |
1289 | return -ENOMEM; | |
1290 | } | |
1291 | ret = copy_from_user(exec2_list, | |
2bb4629a | 1292 | to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1293 | sizeof(*exec2_list) * args->buffer_count); |
1294 | if (ret != 0) { | |
ff240199 | 1295 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1296 | args->buffer_count, ret); |
1297 | drm_free_large(exec2_list); | |
1298 | return -EFAULT; | |
1299 | } | |
1300 | ||
28d6a7bf BW |
1301 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list, |
1302 | &dev_priv->gtt.base); | |
54cf91dc CW |
1303 | if (!ret) { |
1304 | /* Copy the new buffer offsets back to the user's exec list. */ | |
2bb4629a | 1305 | ret = copy_to_user(to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1306 | exec2_list, |
1307 | sizeof(*exec2_list) * args->buffer_count); | |
1308 | if (ret) { | |
1309 | ret = -EFAULT; | |
ff240199 | 1310 | DRM_DEBUG("failed to copy %d exec entries " |
54cf91dc CW |
1311 | "back to user (%d)\n", |
1312 | args->buffer_count, ret); | |
1313 | } | |
1314 | } | |
1315 | ||
1316 | drm_free_large(exec2_list); | |
1317 | return ret; | |
1318 | } |