Commit | Line | Data |
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54cf91dc CW |
1 | /* |
2 | * Copyright © 2008,2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Chris Wilson <chris@chris-wilson.co.uk> | |
26 | * | |
27 | */ | |
28 | ||
ad778f89 CW |
29 | #include <linux/dma_remapping.h> |
30 | #include <linux/reservation.h> | |
31 | #include <linux/uaccess.h> | |
32 | ||
760285e7 DH |
33 | #include <drm/drmP.h> |
34 | #include <drm/i915_drm.h> | |
ad778f89 | 35 | |
54cf91dc CW |
36 | #include "i915_drv.h" |
37 | #include "i915_trace.h" | |
38 | #include "intel_drv.h" | |
5d723d7a | 39 | #include "intel_frontbuffer.h" |
54cf91dc | 40 | |
d50415cc CW |
41 | #define DBG_USE_CPU_RELOC 0 /* -1 force GTT relocs; 1 force CPU relocs */ |
42 | ||
9e2793f6 DG |
43 | #define __EXEC_OBJECT_HAS_PIN (1<<31) |
44 | #define __EXEC_OBJECT_HAS_FENCE (1<<30) | |
45 | #define __EXEC_OBJECT_NEEDS_MAP (1<<29) | |
46 | #define __EXEC_OBJECT_NEEDS_BIAS (1<<28) | |
47 | #define __EXEC_OBJECT_INTERNAL_FLAGS (0xf<<28) /* all of the above */ | |
d23db88c CW |
48 | |
49 | #define BATCH_OFFSET_BIAS (256*1024) | |
a415d355 | 50 | |
5b043f4e CW |
51 | struct i915_execbuffer_params { |
52 | struct drm_device *dev; | |
53 | struct drm_file *file; | |
59bfa124 CW |
54 | struct i915_vma *batch; |
55 | u32 dispatch_flags; | |
56 | u32 args_batch_start_offset; | |
5b043f4e | 57 | struct intel_engine_cs *engine; |
5b043f4e CW |
58 | struct i915_gem_context *ctx; |
59 | struct drm_i915_gem_request *request; | |
60 | }; | |
61 | ||
27173f1f | 62 | struct eb_vmas { |
d50415cc | 63 | struct drm_i915_private *i915; |
27173f1f | 64 | struct list_head vmas; |
67731b87 | 65 | int and; |
eef90ccb | 66 | union { |
27173f1f | 67 | struct i915_vma *lut[0]; |
eef90ccb CW |
68 | struct hlist_head buckets[0]; |
69 | }; | |
67731b87 CW |
70 | }; |
71 | ||
27173f1f | 72 | static struct eb_vmas * |
d50415cc CW |
73 | eb_create(struct drm_i915_private *i915, |
74 | struct drm_i915_gem_execbuffer2 *args) | |
67731b87 | 75 | { |
27173f1f | 76 | struct eb_vmas *eb = NULL; |
eef90ccb CW |
77 | |
78 | if (args->flags & I915_EXEC_HANDLE_LUT) { | |
b205ca57 | 79 | unsigned size = args->buffer_count; |
27173f1f BW |
80 | size *= sizeof(struct i915_vma *); |
81 | size += sizeof(struct eb_vmas); | |
eef90ccb CW |
82 | eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); |
83 | } | |
84 | ||
85 | if (eb == NULL) { | |
b205ca57 DV |
86 | unsigned size = args->buffer_count; |
87 | unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2; | |
27b7c63a | 88 | BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head)); |
eef90ccb CW |
89 | while (count > 2*size) |
90 | count >>= 1; | |
91 | eb = kzalloc(count*sizeof(struct hlist_head) + | |
27173f1f | 92 | sizeof(struct eb_vmas), |
eef90ccb CW |
93 | GFP_TEMPORARY); |
94 | if (eb == NULL) | |
95 | return eb; | |
96 | ||
97 | eb->and = count - 1; | |
98 | } else | |
99 | eb->and = -args->buffer_count; | |
100 | ||
d50415cc | 101 | eb->i915 = i915; |
27173f1f | 102 | INIT_LIST_HEAD(&eb->vmas); |
67731b87 CW |
103 | return eb; |
104 | } | |
105 | ||
106 | static void | |
27173f1f | 107 | eb_reset(struct eb_vmas *eb) |
67731b87 | 108 | { |
eef90ccb CW |
109 | if (eb->and >= 0) |
110 | memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head)); | |
67731b87 CW |
111 | } |
112 | ||
59bfa124 CW |
113 | static struct i915_vma * |
114 | eb_get_batch(struct eb_vmas *eb) | |
115 | { | |
116 | struct i915_vma *vma = list_entry(eb->vmas.prev, typeof(*vma), exec_list); | |
117 | ||
118 | /* | |
119 | * SNA is doing fancy tricks with compressing batch buffers, which leads | |
120 | * to negative relocation deltas. Usually that works out ok since the | |
121 | * relocate address is still positive, except when the batch is placed | |
122 | * very low in the GTT. Ensure this doesn't happen. | |
123 | * | |
124 | * Note that actual hangs have only been observed on gen7, but for | |
125 | * paranoia do it everywhere. | |
126 | */ | |
127 | if ((vma->exec_entry->flags & EXEC_OBJECT_PINNED) == 0) | |
128 | vma->exec_entry->flags |= __EXEC_OBJECT_NEEDS_BIAS; | |
129 | ||
130 | return vma; | |
131 | } | |
132 | ||
3b96eff4 | 133 | static int |
27173f1f BW |
134 | eb_lookup_vmas(struct eb_vmas *eb, |
135 | struct drm_i915_gem_exec_object2 *exec, | |
136 | const struct drm_i915_gem_execbuffer2 *args, | |
137 | struct i915_address_space *vm, | |
138 | struct drm_file *file) | |
3b96eff4 | 139 | { |
27173f1f BW |
140 | struct drm_i915_gem_object *obj; |
141 | struct list_head objects; | |
9ae9ab52 | 142 | int i, ret; |
3b96eff4 | 143 | |
27173f1f | 144 | INIT_LIST_HEAD(&objects); |
3b96eff4 | 145 | spin_lock(&file->table_lock); |
27173f1f BW |
146 | /* Grab a reference to the object and release the lock so we can lookup |
147 | * or create the VMA without using GFP_ATOMIC */ | |
eef90ccb | 148 | for (i = 0; i < args->buffer_count; i++) { |
3b96eff4 CW |
149 | obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle)); |
150 | if (obj == NULL) { | |
151 | spin_unlock(&file->table_lock); | |
152 | DRM_DEBUG("Invalid object handle %d at index %d\n", | |
153 | exec[i].handle, i); | |
27173f1f | 154 | ret = -ENOENT; |
9ae9ab52 | 155 | goto err; |
3b96eff4 CW |
156 | } |
157 | ||
27173f1f | 158 | if (!list_empty(&obj->obj_exec_link)) { |
3b96eff4 CW |
159 | spin_unlock(&file->table_lock); |
160 | DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n", | |
161 | obj, exec[i].handle, i); | |
27173f1f | 162 | ret = -EINVAL; |
9ae9ab52 | 163 | goto err; |
3b96eff4 CW |
164 | } |
165 | ||
25dc556a | 166 | i915_gem_object_get(obj); |
27173f1f BW |
167 | list_add_tail(&obj->obj_exec_link, &objects); |
168 | } | |
169 | spin_unlock(&file->table_lock); | |
3b96eff4 | 170 | |
27173f1f | 171 | i = 0; |
9ae9ab52 | 172 | while (!list_empty(&objects)) { |
27173f1f | 173 | struct i915_vma *vma; |
6f65e29a | 174 | |
9ae9ab52 CW |
175 | obj = list_first_entry(&objects, |
176 | struct drm_i915_gem_object, | |
177 | obj_exec_link); | |
178 | ||
e656a6cb DV |
179 | /* |
180 | * NOTE: We can leak any vmas created here when something fails | |
181 | * later on. But that's no issue since vma_unbind can deal with | |
182 | * vmas which are not actually bound. And since only | |
183 | * lookup_or_create exists as an interface to get at the vma | |
184 | * from the (obj, vm) we don't run the risk of creating | |
185 | * duplicated vmas for the same vm. | |
186 | */ | |
718659a6 | 187 | vma = i915_vma_instance(obj, vm, NULL); |
058d88c4 | 188 | if (unlikely(IS_ERR(vma))) { |
27173f1f BW |
189 | DRM_DEBUG("Failed to lookup VMA\n"); |
190 | ret = PTR_ERR(vma); | |
9ae9ab52 | 191 | goto err; |
27173f1f BW |
192 | } |
193 | ||
9ae9ab52 | 194 | /* Transfer ownership from the objects list to the vmas list. */ |
27173f1f | 195 | list_add_tail(&vma->exec_list, &eb->vmas); |
9ae9ab52 | 196 | list_del_init(&obj->obj_exec_link); |
27173f1f BW |
197 | |
198 | vma->exec_entry = &exec[i]; | |
eef90ccb | 199 | if (eb->and < 0) { |
27173f1f | 200 | eb->lut[i] = vma; |
eef90ccb CW |
201 | } else { |
202 | uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle; | |
27173f1f BW |
203 | vma->exec_handle = handle; |
204 | hlist_add_head(&vma->exec_node, | |
eef90ccb CW |
205 | &eb->buckets[handle & eb->and]); |
206 | } | |
27173f1f | 207 | ++i; |
3b96eff4 | 208 | } |
3b96eff4 | 209 | |
9ae9ab52 | 210 | return 0; |
27173f1f | 211 | |
27173f1f | 212 | |
9ae9ab52 | 213 | err: |
27173f1f BW |
214 | while (!list_empty(&objects)) { |
215 | obj = list_first_entry(&objects, | |
216 | struct drm_i915_gem_object, | |
217 | obj_exec_link); | |
218 | list_del_init(&obj->obj_exec_link); | |
f8c417cd | 219 | i915_gem_object_put(obj); |
27173f1f | 220 | } |
9ae9ab52 CW |
221 | /* |
222 | * Objects already transfered to the vmas list will be unreferenced by | |
223 | * eb_destroy. | |
224 | */ | |
225 | ||
27173f1f | 226 | return ret; |
3b96eff4 CW |
227 | } |
228 | ||
27173f1f | 229 | static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle) |
67731b87 | 230 | { |
eef90ccb CW |
231 | if (eb->and < 0) { |
232 | if (handle >= -eb->and) | |
233 | return NULL; | |
234 | return eb->lut[handle]; | |
235 | } else { | |
236 | struct hlist_head *head; | |
aa45950b | 237 | struct i915_vma *vma; |
67731b87 | 238 | |
eef90ccb | 239 | head = &eb->buckets[handle & eb->and]; |
aa45950b | 240 | hlist_for_each_entry(vma, head, exec_node) { |
27173f1f BW |
241 | if (vma->exec_handle == handle) |
242 | return vma; | |
eef90ccb CW |
243 | } |
244 | return NULL; | |
245 | } | |
67731b87 CW |
246 | } |
247 | ||
a415d355 CW |
248 | static void |
249 | i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma) | |
250 | { | |
251 | struct drm_i915_gem_exec_object2 *entry; | |
a415d355 CW |
252 | |
253 | if (!drm_mm_node_allocated(&vma->node)) | |
254 | return; | |
255 | ||
256 | entry = vma->exec_entry; | |
257 | ||
258 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) | |
49ef5294 | 259 | i915_vma_unpin_fence(vma); |
a415d355 CW |
260 | |
261 | if (entry->flags & __EXEC_OBJECT_HAS_PIN) | |
20dfbde4 | 262 | __i915_vma_unpin(vma); |
a415d355 | 263 | |
de4e783a | 264 | entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN); |
a415d355 CW |
265 | } |
266 | ||
267 | static void eb_destroy(struct eb_vmas *eb) | |
268 | { | |
27173f1f BW |
269 | while (!list_empty(&eb->vmas)) { |
270 | struct i915_vma *vma; | |
bcffc3fa | 271 | |
27173f1f BW |
272 | vma = list_first_entry(&eb->vmas, |
273 | struct i915_vma, | |
bcffc3fa | 274 | exec_list); |
27173f1f | 275 | list_del_init(&vma->exec_list); |
a415d355 | 276 | i915_gem_execbuffer_unreserve_vma(vma); |
172ae5b4 | 277 | vma->exec_entry = NULL; |
624192cf | 278 | i915_vma_put(vma); |
bcffc3fa | 279 | } |
67731b87 CW |
280 | kfree(eb); |
281 | } | |
282 | ||
dabdfe02 CW |
283 | static inline int use_cpu_reloc(struct drm_i915_gem_object *obj) |
284 | { | |
9e53d9be CW |
285 | if (!i915_gem_object_has_struct_page(obj)) |
286 | return false; | |
287 | ||
d50415cc CW |
288 | if (DBG_USE_CPU_RELOC) |
289 | return DBG_USE_CPU_RELOC > 0; | |
290 | ||
0031fb96 | 291 | return (HAS_LLC(to_i915(obj->base.dev)) || |
2cc86b82 | 292 | obj->base.write_domain == I915_GEM_DOMAIN_CPU || |
dabdfe02 CW |
293 | obj->cache_level != I915_CACHE_NONE); |
294 | } | |
295 | ||
934acce3 MW |
296 | /* Used to convert any address to canonical form. |
297 | * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS, | |
298 | * MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the | |
299 | * addresses to be in a canonical form: | |
300 | * "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct | |
301 | * canonical form [63:48] == [47]." | |
302 | */ | |
303 | #define GEN8_HIGH_ADDRESS_BIT 47 | |
304 | static inline uint64_t gen8_canonical_addr(uint64_t address) | |
305 | { | |
306 | return sign_extend64(address, GEN8_HIGH_ADDRESS_BIT); | |
307 | } | |
308 | ||
309 | static inline uint64_t gen8_noncanonical_addr(uint64_t address) | |
310 | { | |
311 | return address & ((1ULL << (GEN8_HIGH_ADDRESS_BIT + 1)) - 1); | |
312 | } | |
313 | ||
314 | static inline uint64_t | |
d50415cc | 315 | relocation_target(const struct drm_i915_gem_relocation_entry *reloc, |
934acce3 MW |
316 | uint64_t target_offset) |
317 | { | |
318 | return gen8_canonical_addr((int)reloc->delta + target_offset); | |
319 | } | |
320 | ||
31a39207 | 321 | struct reloc_cache { |
d50415cc CW |
322 | struct drm_i915_private *i915; |
323 | struct drm_mm_node node; | |
324 | unsigned long vaddr; | |
31a39207 | 325 | unsigned int page; |
d50415cc | 326 | bool use_64bit_reloc; |
31a39207 CW |
327 | }; |
328 | ||
d50415cc CW |
329 | static void reloc_cache_init(struct reloc_cache *cache, |
330 | struct drm_i915_private *i915) | |
5032d871 | 331 | { |
31a39207 | 332 | cache->page = -1; |
d50415cc CW |
333 | cache->vaddr = 0; |
334 | cache->i915 = i915; | |
dfc5148f JL |
335 | /* Must be a variable in the struct to allow GCC to unroll. */ |
336 | cache->use_64bit_reloc = HAS_64BIT_RELOC(i915); | |
e8cb909a | 337 | cache->node.allocated = false; |
d50415cc | 338 | } |
5032d871 | 339 | |
d50415cc CW |
340 | static inline void *unmask_page(unsigned long p) |
341 | { | |
342 | return (void *)(uintptr_t)(p & PAGE_MASK); | |
343 | } | |
344 | ||
345 | static inline unsigned int unmask_flags(unsigned long p) | |
346 | { | |
347 | return p & ~PAGE_MASK; | |
31a39207 CW |
348 | } |
349 | ||
d50415cc CW |
350 | #define KMAP 0x4 /* after CLFLUSH_FLAGS */ |
351 | ||
31a39207 CW |
352 | static void reloc_cache_fini(struct reloc_cache *cache) |
353 | { | |
d50415cc | 354 | void *vaddr; |
5032d871 | 355 | |
31a39207 CW |
356 | if (!cache->vaddr) |
357 | return; | |
3c94ceee | 358 | |
d50415cc CW |
359 | vaddr = unmask_page(cache->vaddr); |
360 | if (cache->vaddr & KMAP) { | |
361 | if (cache->vaddr & CLFLUSH_AFTER) | |
362 | mb(); | |
3c94ceee | 363 | |
d50415cc CW |
364 | kunmap_atomic(vaddr); |
365 | i915_gem_obj_finish_shmem_access((struct drm_i915_gem_object *)cache->node.mm); | |
366 | } else { | |
e8cb909a | 367 | wmb(); |
d50415cc | 368 | io_mapping_unmap_atomic((void __iomem *)vaddr); |
e8cb909a CW |
369 | if (cache->node.allocated) { |
370 | struct i915_ggtt *ggtt = &cache->i915->ggtt; | |
371 | ||
372 | ggtt->base.clear_range(&ggtt->base, | |
373 | cache->node.start, | |
4fb84d99 | 374 | cache->node.size); |
e8cb909a CW |
375 | drm_mm_remove_node(&cache->node); |
376 | } else { | |
377 | i915_vma_unpin((struct i915_vma *)cache->node.mm); | |
3c94ceee | 378 | } |
31a39207 CW |
379 | } |
380 | } | |
381 | ||
382 | static void *reloc_kmap(struct drm_i915_gem_object *obj, | |
383 | struct reloc_cache *cache, | |
384 | int page) | |
385 | { | |
d50415cc CW |
386 | void *vaddr; |
387 | ||
388 | if (cache->vaddr) { | |
389 | kunmap_atomic(unmask_page(cache->vaddr)); | |
390 | } else { | |
391 | unsigned int flushes; | |
392 | int ret; | |
31a39207 | 393 | |
d50415cc CW |
394 | ret = i915_gem_obj_prepare_shmem_write(obj, &flushes); |
395 | if (ret) | |
396 | return ERR_PTR(ret); | |
397 | ||
398 | BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS); | |
399 | BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK); | |
3c94ceee | 400 | |
d50415cc CW |
401 | cache->vaddr = flushes | KMAP; |
402 | cache->node.mm = (void *)obj; | |
403 | if (flushes) | |
404 | mb(); | |
3c94ceee BW |
405 | } |
406 | ||
d50415cc CW |
407 | vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, page)); |
408 | cache->vaddr = unmask_flags(cache->vaddr) | (unsigned long)vaddr; | |
31a39207 | 409 | cache->page = page; |
5032d871 | 410 | |
d50415cc | 411 | return vaddr; |
5032d871 RB |
412 | } |
413 | ||
d50415cc CW |
414 | static void *reloc_iomap(struct drm_i915_gem_object *obj, |
415 | struct reloc_cache *cache, | |
416 | int page) | |
5032d871 | 417 | { |
e8cb909a CW |
418 | struct i915_ggtt *ggtt = &cache->i915->ggtt; |
419 | unsigned long offset; | |
d50415cc | 420 | void *vaddr; |
5032d871 | 421 | |
d50415cc | 422 | if (cache->vaddr) { |
615e5000 | 423 | io_mapping_unmap_atomic((void __force __iomem *) unmask_page(cache->vaddr)); |
d50415cc CW |
424 | } else { |
425 | struct i915_vma *vma; | |
426 | int ret; | |
5032d871 | 427 | |
d50415cc CW |
428 | if (use_cpu_reloc(obj)) |
429 | return NULL; | |
3c94ceee | 430 | |
d50415cc CW |
431 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
432 | if (ret) | |
433 | return ERR_PTR(ret); | |
3c94ceee | 434 | |
d50415cc CW |
435 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, |
436 | PIN_MAPPABLE | PIN_NONBLOCK); | |
e8cb909a CW |
437 | if (IS_ERR(vma)) { |
438 | memset(&cache->node, 0, sizeof(cache->node)); | |
439 | ret = drm_mm_insert_node_in_range_generic | |
440 | (&ggtt->base.mm, &cache->node, | |
f51455d4 | 441 | PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE, |
e8cb909a CW |
442 | 0, ggtt->mappable_end, |
443 | DRM_MM_SEARCH_DEFAULT, | |
444 | DRM_MM_CREATE_DEFAULT); | |
c92fa4fe CW |
445 | if (ret) /* no inactive aperture space, use cpu reloc */ |
446 | return NULL; | |
e8cb909a | 447 | } else { |
49ef5294 | 448 | ret = i915_vma_put_fence(vma); |
e8cb909a CW |
449 | if (ret) { |
450 | i915_vma_unpin(vma); | |
451 | return ERR_PTR(ret); | |
452 | } | |
5032d871 | 453 | |
e8cb909a CW |
454 | cache->node.start = vma->node.start; |
455 | cache->node.mm = (void *)vma; | |
3c94ceee | 456 | } |
e8cb909a | 457 | } |
3c94ceee | 458 | |
e8cb909a CW |
459 | offset = cache->node.start; |
460 | if (cache->node.allocated) { | |
fc099090 | 461 | wmb(); |
e8cb909a CW |
462 | ggtt->base.insert_page(&ggtt->base, |
463 | i915_gem_object_get_dma_address(obj, page), | |
464 | offset, I915_CACHE_NONE, 0); | |
465 | } else { | |
466 | offset += page << PAGE_SHIFT; | |
3c94ceee BW |
467 | } |
468 | ||
615e5000 | 469 | vaddr = (void __force *) io_mapping_map_atomic_wc(&cache->i915->ggtt.mappable, offset); |
d50415cc CW |
470 | cache->page = page; |
471 | cache->vaddr = (unsigned long)vaddr; | |
5032d871 | 472 | |
d50415cc | 473 | return vaddr; |
5032d871 RB |
474 | } |
475 | ||
d50415cc CW |
476 | static void *reloc_vaddr(struct drm_i915_gem_object *obj, |
477 | struct reloc_cache *cache, | |
478 | int page) | |
edf4427b | 479 | { |
d50415cc | 480 | void *vaddr; |
5032d871 | 481 | |
d50415cc CW |
482 | if (cache->page == page) { |
483 | vaddr = unmask_page(cache->vaddr); | |
484 | } else { | |
485 | vaddr = NULL; | |
486 | if ((cache->vaddr & KMAP) == 0) | |
487 | vaddr = reloc_iomap(obj, cache, page); | |
488 | if (!vaddr) | |
489 | vaddr = reloc_kmap(obj, cache, page); | |
3c94ceee BW |
490 | } |
491 | ||
d50415cc | 492 | return vaddr; |
edf4427b CW |
493 | } |
494 | ||
d50415cc | 495 | static void clflush_write32(u32 *addr, u32 value, unsigned int flushes) |
edf4427b | 496 | { |
d50415cc CW |
497 | if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) { |
498 | if (flushes & CLFLUSH_BEFORE) { | |
499 | clflushopt(addr); | |
500 | mb(); | |
501 | } | |
edf4427b | 502 | |
d50415cc | 503 | *addr = value; |
edf4427b | 504 | |
d50415cc CW |
505 | /* Writes to the same cacheline are serialised by the CPU |
506 | * (including clflush). On the write path, we only require | |
507 | * that it hits memory in an orderly fashion and place | |
508 | * mb barriers at the start and end of the relocation phase | |
509 | * to ensure ordering of clflush wrt to the system. | |
510 | */ | |
511 | if (flushes & CLFLUSH_AFTER) | |
512 | clflushopt(addr); | |
513 | } else | |
514 | *addr = value; | |
edf4427b | 515 | } |
edf4427b | 516 | |
edf4427b | 517 | static int |
d50415cc CW |
518 | relocate_entry(struct drm_i915_gem_object *obj, |
519 | const struct drm_i915_gem_relocation_entry *reloc, | |
520 | struct reloc_cache *cache, | |
521 | u64 target_offset) | |
edf4427b | 522 | { |
d50415cc CW |
523 | u64 offset = reloc->offset; |
524 | bool wide = cache->use_64bit_reloc; | |
525 | void *vaddr; | |
edf4427b | 526 | |
d50415cc CW |
527 | target_offset = relocation_target(reloc, target_offset); |
528 | repeat: | |
529 | vaddr = reloc_vaddr(obj, cache, offset >> PAGE_SHIFT); | |
530 | if (IS_ERR(vaddr)) | |
531 | return PTR_ERR(vaddr); | |
532 | ||
533 | clflush_write32(vaddr + offset_in_page(offset), | |
534 | lower_32_bits(target_offset), | |
535 | cache->vaddr); | |
536 | ||
537 | if (wide) { | |
538 | offset += sizeof(u32); | |
539 | target_offset >>= 32; | |
540 | wide = false; | |
541 | goto repeat; | |
edf4427b | 542 | } |
edf4427b | 543 | |
edf4427b CW |
544 | return 0; |
545 | } | |
edf4427b | 546 | |
54cf91dc CW |
547 | static int |
548 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, | |
27173f1f | 549 | struct eb_vmas *eb, |
31a39207 CW |
550 | struct drm_i915_gem_relocation_entry *reloc, |
551 | struct reloc_cache *cache) | |
54cf91dc | 552 | { |
5db94019 | 553 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
54cf91dc | 554 | struct drm_gem_object *target_obj; |
149c8407 | 555 | struct drm_i915_gem_object *target_i915_obj; |
27173f1f | 556 | struct i915_vma *target_vma; |
d9ceb957 | 557 | uint64_t target_offset; |
8b78f0e5 | 558 | int ret; |
54cf91dc | 559 | |
67731b87 | 560 | /* we've already hold a reference to all valid objects */ |
27173f1f BW |
561 | target_vma = eb_get_vma(eb, reloc->target_handle); |
562 | if (unlikely(target_vma == NULL)) | |
54cf91dc | 563 | return -ENOENT; |
27173f1f BW |
564 | target_i915_obj = target_vma->obj; |
565 | target_obj = &target_vma->obj->base; | |
54cf91dc | 566 | |
934acce3 | 567 | target_offset = gen8_canonical_addr(target_vma->node.start); |
54cf91dc | 568 | |
e844b990 EA |
569 | /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and |
570 | * pipe_control writes because the gpu doesn't properly redirect them | |
571 | * through the ppgtt for non_secure batchbuffers. */ | |
5db94019 | 572 | if (unlikely(IS_GEN6(dev_priv) && |
0875546c | 573 | reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) { |
fe14d5f4 | 574 | ret = i915_vma_bind(target_vma, target_i915_obj->cache_level, |
0875546c | 575 | PIN_GLOBAL); |
fe14d5f4 TU |
576 | if (WARN_ONCE(ret, "Unexpected failure to bind target VMA!")) |
577 | return ret; | |
578 | } | |
e844b990 | 579 | |
54cf91dc | 580 | /* Validate that the target is in a valid r/w GPU domain */ |
b8f7ab17 | 581 | if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { |
ff240199 | 582 | DRM_DEBUG("reloc with multiple write domains: " |
54cf91dc CW |
583 | "obj %p target %d offset %d " |
584 | "read %08x write %08x", | |
585 | obj, reloc->target_handle, | |
586 | (int) reloc->offset, | |
587 | reloc->read_domains, | |
588 | reloc->write_domain); | |
8b78f0e5 | 589 | return -EINVAL; |
54cf91dc | 590 | } |
4ca4a250 DV |
591 | if (unlikely((reloc->write_domain | reloc->read_domains) |
592 | & ~I915_GEM_GPU_DOMAINS)) { | |
ff240199 | 593 | DRM_DEBUG("reloc with read/write non-GPU domains: " |
54cf91dc CW |
594 | "obj %p target %d offset %d " |
595 | "read %08x write %08x", | |
596 | obj, reloc->target_handle, | |
597 | (int) reloc->offset, | |
598 | reloc->read_domains, | |
599 | reloc->write_domain); | |
8b78f0e5 | 600 | return -EINVAL; |
54cf91dc | 601 | } |
54cf91dc CW |
602 | |
603 | target_obj->pending_read_domains |= reloc->read_domains; | |
604 | target_obj->pending_write_domain |= reloc->write_domain; | |
605 | ||
606 | /* If the relocation already has the right value in it, no | |
607 | * more work needs to be done. | |
608 | */ | |
609 | if (target_offset == reloc->presumed_offset) | |
67731b87 | 610 | return 0; |
54cf91dc CW |
611 | |
612 | /* Check that the relocation address is valid... */ | |
3c94ceee | 613 | if (unlikely(reloc->offset > |
d50415cc | 614 | obj->base.size - (cache->use_64bit_reloc ? 8 : 4))) { |
ff240199 | 615 | DRM_DEBUG("Relocation beyond object bounds: " |
54cf91dc CW |
616 | "obj %p target %d offset %d size %d.\n", |
617 | obj, reloc->target_handle, | |
618 | (int) reloc->offset, | |
619 | (int) obj->base.size); | |
8b78f0e5 | 620 | return -EINVAL; |
54cf91dc | 621 | } |
b8f7ab17 | 622 | if (unlikely(reloc->offset & 3)) { |
ff240199 | 623 | DRM_DEBUG("Relocation not 4-byte aligned: " |
54cf91dc CW |
624 | "obj %p target %d offset %d.\n", |
625 | obj, reloc->target_handle, | |
626 | (int) reloc->offset); | |
8b78f0e5 | 627 | return -EINVAL; |
54cf91dc CW |
628 | } |
629 | ||
d50415cc | 630 | ret = relocate_entry(obj, reloc, cache, target_offset); |
d4d36014 DV |
631 | if (ret) |
632 | return ret; | |
633 | ||
54cf91dc CW |
634 | /* and update the user's relocation entry */ |
635 | reloc->presumed_offset = target_offset; | |
67731b87 | 636 | return 0; |
54cf91dc CW |
637 | } |
638 | ||
639 | static int | |
27173f1f BW |
640 | i915_gem_execbuffer_relocate_vma(struct i915_vma *vma, |
641 | struct eb_vmas *eb) | |
54cf91dc | 642 | { |
1d83f442 CW |
643 | #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) |
644 | struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)]; | |
54cf91dc | 645 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
27173f1f | 646 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
31a39207 CW |
647 | struct reloc_cache cache; |
648 | int remain, ret = 0; | |
54cf91dc | 649 | |
3ed605bc | 650 | user_relocs = u64_to_user_ptr(entry->relocs_ptr); |
d50415cc | 651 | reloc_cache_init(&cache, eb->i915); |
54cf91dc | 652 | |
1d83f442 CW |
653 | remain = entry->relocation_count; |
654 | while (remain) { | |
655 | struct drm_i915_gem_relocation_entry *r = stack_reloc; | |
ebc0808f CW |
656 | unsigned long unwritten; |
657 | unsigned int count; | |
658 | ||
659 | count = min_t(unsigned int, remain, ARRAY_SIZE(stack_reloc)); | |
1d83f442 CW |
660 | remain -= count; |
661 | ||
ebc0808f CW |
662 | /* This is the fast path and we cannot handle a pagefault |
663 | * whilst holding the struct mutex lest the user pass in the | |
664 | * relocations contained within a mmaped bo. For in such a case | |
665 | * we, the page fault handler would call i915_gem_fault() and | |
666 | * we would try to acquire the struct mutex again. Obviously | |
667 | * this is bad and so lockdep complains vehemently. | |
668 | */ | |
669 | pagefault_disable(); | |
670 | unwritten = __copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0])); | |
671 | pagefault_enable(); | |
672 | if (unlikely(unwritten)) { | |
31a39207 CW |
673 | ret = -EFAULT; |
674 | goto out; | |
675 | } | |
54cf91dc | 676 | |
1d83f442 CW |
677 | do { |
678 | u64 offset = r->presumed_offset; | |
54cf91dc | 679 | |
31a39207 | 680 | ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r, &cache); |
1d83f442 | 681 | if (ret) |
31a39207 | 682 | goto out; |
1d83f442 | 683 | |
ebc0808f CW |
684 | if (r->presumed_offset != offset) { |
685 | pagefault_disable(); | |
686 | unwritten = __put_user(r->presumed_offset, | |
687 | &user_relocs->presumed_offset); | |
688 | pagefault_enable(); | |
689 | if (unlikely(unwritten)) { | |
690 | /* Note that reporting an error now | |
691 | * leaves everything in an inconsistent | |
692 | * state as we have *already* changed | |
693 | * the relocation value inside the | |
694 | * object. As we have not changed the | |
695 | * reloc.presumed_offset or will not | |
696 | * change the execobject.offset, on the | |
697 | * call we may not rewrite the value | |
698 | * inside the object, leaving it | |
699 | * dangling and causing a GPU hang. | |
700 | */ | |
701 | ret = -EFAULT; | |
702 | goto out; | |
703 | } | |
1d83f442 CW |
704 | } |
705 | ||
706 | user_relocs++; | |
707 | r++; | |
708 | } while (--count); | |
54cf91dc CW |
709 | } |
710 | ||
31a39207 CW |
711 | out: |
712 | reloc_cache_fini(&cache); | |
713 | return ret; | |
1d83f442 | 714 | #undef N_RELOC |
54cf91dc CW |
715 | } |
716 | ||
717 | static int | |
27173f1f BW |
718 | i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma, |
719 | struct eb_vmas *eb, | |
720 | struct drm_i915_gem_relocation_entry *relocs) | |
54cf91dc | 721 | { |
27173f1f | 722 | const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
31a39207 CW |
723 | struct reloc_cache cache; |
724 | int i, ret = 0; | |
54cf91dc | 725 | |
d50415cc | 726 | reloc_cache_init(&cache, eb->i915); |
54cf91dc | 727 | for (i = 0; i < entry->relocation_count; i++) { |
31a39207 | 728 | ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i], &cache); |
54cf91dc | 729 | if (ret) |
31a39207 | 730 | break; |
54cf91dc | 731 | } |
31a39207 | 732 | reloc_cache_fini(&cache); |
54cf91dc | 733 | |
31a39207 | 734 | return ret; |
54cf91dc CW |
735 | } |
736 | ||
737 | static int | |
17601cbc | 738 | i915_gem_execbuffer_relocate(struct eb_vmas *eb) |
54cf91dc | 739 | { |
27173f1f | 740 | struct i915_vma *vma; |
d4aeee77 CW |
741 | int ret = 0; |
742 | ||
27173f1f BW |
743 | list_for_each_entry(vma, &eb->vmas, exec_list) { |
744 | ret = i915_gem_execbuffer_relocate_vma(vma, eb); | |
54cf91dc | 745 | if (ret) |
d4aeee77 | 746 | break; |
54cf91dc CW |
747 | } |
748 | ||
d4aeee77 | 749 | return ret; |
54cf91dc CW |
750 | } |
751 | ||
edf4427b CW |
752 | static bool only_mappable_for_reloc(unsigned int flags) |
753 | { | |
754 | return (flags & (EXEC_OBJECT_NEEDS_FENCE | __EXEC_OBJECT_NEEDS_MAP)) == | |
755 | __EXEC_OBJECT_NEEDS_MAP; | |
756 | } | |
757 | ||
1690e1eb | 758 | static int |
27173f1f | 759 | i915_gem_execbuffer_reserve_vma(struct i915_vma *vma, |
0bc40be8 | 760 | struct intel_engine_cs *engine, |
27173f1f | 761 | bool *need_reloc) |
1690e1eb | 762 | { |
6f65e29a | 763 | struct drm_i915_gem_object *obj = vma->obj; |
27173f1f | 764 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
d23db88c | 765 | uint64_t flags; |
1690e1eb CW |
766 | int ret; |
767 | ||
0875546c | 768 | flags = PIN_USER; |
0229da32 DV |
769 | if (entry->flags & EXEC_OBJECT_NEEDS_GTT) |
770 | flags |= PIN_GLOBAL; | |
771 | ||
edf4427b | 772 | if (!drm_mm_node_allocated(&vma->node)) { |
101b506a MT |
773 | /* Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset, |
774 | * limit address to the first 4GBs for unflagged objects. | |
775 | */ | |
776 | if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0) | |
777 | flags |= PIN_ZONE_4G; | |
edf4427b CW |
778 | if (entry->flags & __EXEC_OBJECT_NEEDS_MAP) |
779 | flags |= PIN_GLOBAL | PIN_MAPPABLE; | |
edf4427b CW |
780 | if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS) |
781 | flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS; | |
506a8e87 CW |
782 | if (entry->flags & EXEC_OBJECT_PINNED) |
783 | flags |= entry->offset | PIN_OFFSET_FIXED; | |
101b506a MT |
784 | if ((flags & PIN_MAPPABLE) == 0) |
785 | flags |= PIN_HIGH; | |
edf4427b | 786 | } |
1ec9e26d | 787 | |
59bfa124 CW |
788 | ret = i915_vma_pin(vma, |
789 | entry->pad_to_size, | |
790 | entry->alignment, | |
791 | flags); | |
792 | if ((ret == -ENOSPC || ret == -E2BIG) && | |
edf4427b | 793 | only_mappable_for_reloc(entry->flags)) |
59bfa124 CW |
794 | ret = i915_vma_pin(vma, |
795 | entry->pad_to_size, | |
796 | entry->alignment, | |
797 | flags & ~PIN_MAPPABLE); | |
1690e1eb CW |
798 | if (ret) |
799 | return ret; | |
800 | ||
7788a765 CW |
801 | entry->flags |= __EXEC_OBJECT_HAS_PIN; |
802 | ||
82b6b6d7 | 803 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { |
49ef5294 | 804 | ret = i915_vma_get_fence(vma); |
82b6b6d7 CW |
805 | if (ret) |
806 | return ret; | |
9a5a53b3 | 807 | |
49ef5294 | 808 | if (i915_vma_pin_fence(vma)) |
82b6b6d7 | 809 | entry->flags |= __EXEC_OBJECT_HAS_FENCE; |
1690e1eb CW |
810 | } |
811 | ||
27173f1f BW |
812 | if (entry->offset != vma->node.start) { |
813 | entry->offset = vma->node.start; | |
ed5982e6 DV |
814 | *need_reloc = true; |
815 | } | |
816 | ||
817 | if (entry->flags & EXEC_OBJECT_WRITE) { | |
818 | obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER; | |
819 | obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER; | |
820 | } | |
821 | ||
1690e1eb | 822 | return 0; |
7788a765 | 823 | } |
1690e1eb | 824 | |
d23db88c | 825 | static bool |
e6a84468 | 826 | need_reloc_mappable(struct i915_vma *vma) |
d23db88c CW |
827 | { |
828 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; | |
d23db88c | 829 | |
e6a84468 CW |
830 | if (entry->relocation_count == 0) |
831 | return false; | |
832 | ||
3272db53 | 833 | if (!i915_vma_is_ggtt(vma)) |
e6a84468 CW |
834 | return false; |
835 | ||
836 | /* See also use_cpu_reloc() */ | |
0031fb96 | 837 | if (HAS_LLC(to_i915(vma->obj->base.dev))) |
e6a84468 CW |
838 | return false; |
839 | ||
840 | if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU) | |
841 | return false; | |
842 | ||
843 | return true; | |
844 | } | |
845 | ||
846 | static bool | |
847 | eb_vma_misplaced(struct i915_vma *vma) | |
848 | { | |
849 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; | |
d23db88c | 850 | |
3272db53 CW |
851 | WARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP && |
852 | !i915_vma_is_ggtt(vma)); | |
d23db88c | 853 | |
f51455d4 | 854 | if (entry->alignment && !IS_ALIGNED(vma->node.start, entry->alignment)) |
d23db88c CW |
855 | return true; |
856 | ||
91b2db6f CW |
857 | if (vma->node.size < entry->pad_to_size) |
858 | return true; | |
859 | ||
506a8e87 CW |
860 | if (entry->flags & EXEC_OBJECT_PINNED && |
861 | vma->node.start != entry->offset) | |
862 | return true; | |
863 | ||
d23db88c CW |
864 | if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS && |
865 | vma->node.start < BATCH_OFFSET_BIAS) | |
866 | return true; | |
867 | ||
edf4427b | 868 | /* avoid costly ping-pong once a batch bo ended up non-mappable */ |
05a20d09 CW |
869 | if (entry->flags & __EXEC_OBJECT_NEEDS_MAP && |
870 | !i915_vma_is_map_and_fenceable(vma)) | |
edf4427b CW |
871 | return !only_mappable_for_reloc(entry->flags); |
872 | ||
101b506a MT |
873 | if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0 && |
874 | (vma->node.start + vma->node.size - 1) >> 32) | |
875 | return true; | |
876 | ||
d23db88c CW |
877 | return false; |
878 | } | |
879 | ||
54cf91dc | 880 | static int |
0bc40be8 | 881 | i915_gem_execbuffer_reserve(struct intel_engine_cs *engine, |
27173f1f | 882 | struct list_head *vmas, |
e2efd130 | 883 | struct i915_gem_context *ctx, |
ed5982e6 | 884 | bool *need_relocs) |
54cf91dc | 885 | { |
432e58ed | 886 | struct drm_i915_gem_object *obj; |
27173f1f | 887 | struct i915_vma *vma; |
68c8c17f | 888 | struct i915_address_space *vm; |
27173f1f | 889 | struct list_head ordered_vmas; |
506a8e87 | 890 | struct list_head pinned_vmas; |
c033666a | 891 | bool has_fenced_gpu_access = INTEL_GEN(engine->i915) < 4; |
7788a765 | 892 | int retry; |
6fe4f140 | 893 | |
68c8c17f BW |
894 | vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm; |
895 | ||
27173f1f | 896 | INIT_LIST_HEAD(&ordered_vmas); |
506a8e87 | 897 | INIT_LIST_HEAD(&pinned_vmas); |
27173f1f | 898 | while (!list_empty(vmas)) { |
6fe4f140 CW |
899 | struct drm_i915_gem_exec_object2 *entry; |
900 | bool need_fence, need_mappable; | |
901 | ||
27173f1f BW |
902 | vma = list_first_entry(vmas, struct i915_vma, exec_list); |
903 | obj = vma->obj; | |
904 | entry = vma->exec_entry; | |
6fe4f140 | 905 | |
b1b38278 DW |
906 | if (ctx->flags & CONTEXT_NO_ZEROMAP) |
907 | entry->flags |= __EXEC_OBJECT_NEEDS_BIAS; | |
908 | ||
82b6b6d7 CW |
909 | if (!has_fenced_gpu_access) |
910 | entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE; | |
6fe4f140 | 911 | need_fence = |
6fe4f140 | 912 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
3e510a8e | 913 | i915_gem_object_is_tiled(obj); |
27173f1f | 914 | need_mappable = need_fence || need_reloc_mappable(vma); |
6fe4f140 | 915 | |
506a8e87 CW |
916 | if (entry->flags & EXEC_OBJECT_PINNED) |
917 | list_move_tail(&vma->exec_list, &pinned_vmas); | |
918 | else if (need_mappable) { | |
e6a84468 | 919 | entry->flags |= __EXEC_OBJECT_NEEDS_MAP; |
27173f1f | 920 | list_move(&vma->exec_list, &ordered_vmas); |
e6a84468 | 921 | } else |
27173f1f | 922 | list_move_tail(&vma->exec_list, &ordered_vmas); |
595dad76 | 923 | |
ed5982e6 | 924 | obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND; |
595dad76 | 925 | obj->base.pending_write_domain = 0; |
6fe4f140 | 926 | } |
27173f1f | 927 | list_splice(&ordered_vmas, vmas); |
506a8e87 | 928 | list_splice(&pinned_vmas, vmas); |
54cf91dc CW |
929 | |
930 | /* Attempt to pin all of the buffers into the GTT. | |
931 | * This is done in 3 phases: | |
932 | * | |
933 | * 1a. Unbind all objects that do not match the GTT constraints for | |
934 | * the execbuffer (fenceable, mappable, alignment etc). | |
935 | * 1b. Increment pin count for already bound objects. | |
936 | * 2. Bind new objects. | |
937 | * 3. Decrement pin count. | |
938 | * | |
7788a765 | 939 | * This avoid unnecessary unbinding of later objects in order to make |
54cf91dc CW |
940 | * room for the earlier objects *unless* we need to defragment. |
941 | */ | |
942 | retry = 0; | |
943 | do { | |
7788a765 | 944 | int ret = 0; |
54cf91dc CW |
945 | |
946 | /* Unbind any ill-fitting objects or pin. */ | |
27173f1f | 947 | list_for_each_entry(vma, vmas, exec_list) { |
27173f1f | 948 | if (!drm_mm_node_allocated(&vma->node)) |
54cf91dc CW |
949 | continue; |
950 | ||
e6a84468 | 951 | if (eb_vma_misplaced(vma)) |
27173f1f | 952 | ret = i915_vma_unbind(vma); |
54cf91dc | 953 | else |
0bc40be8 TU |
954 | ret = i915_gem_execbuffer_reserve_vma(vma, |
955 | engine, | |
956 | need_relocs); | |
432e58ed | 957 | if (ret) |
54cf91dc | 958 | goto err; |
54cf91dc CW |
959 | } |
960 | ||
961 | /* Bind fresh objects */ | |
27173f1f BW |
962 | list_for_each_entry(vma, vmas, exec_list) { |
963 | if (drm_mm_node_allocated(&vma->node)) | |
1690e1eb | 964 | continue; |
54cf91dc | 965 | |
0bc40be8 TU |
966 | ret = i915_gem_execbuffer_reserve_vma(vma, engine, |
967 | need_relocs); | |
7788a765 CW |
968 | if (ret) |
969 | goto err; | |
54cf91dc CW |
970 | } |
971 | ||
a415d355 | 972 | err: |
6c085a72 | 973 | if (ret != -ENOSPC || retry++) |
54cf91dc CW |
974 | return ret; |
975 | ||
a415d355 CW |
976 | /* Decrement pin count for bound objects */ |
977 | list_for_each_entry(vma, vmas, exec_list) | |
978 | i915_gem_execbuffer_unreserve_vma(vma); | |
979 | ||
68c8c17f | 980 | ret = i915_gem_evict_vm(vm, true); |
54cf91dc CW |
981 | if (ret) |
982 | return ret; | |
54cf91dc CW |
983 | } while (1); |
984 | } | |
985 | ||
986 | static int | |
987 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, | |
ed5982e6 | 988 | struct drm_i915_gem_execbuffer2 *args, |
54cf91dc | 989 | struct drm_file *file, |
0bc40be8 | 990 | struct intel_engine_cs *engine, |
27173f1f | 991 | struct eb_vmas *eb, |
b1b38278 | 992 | struct drm_i915_gem_exec_object2 *exec, |
e2efd130 | 993 | struct i915_gem_context *ctx) |
54cf91dc CW |
994 | { |
995 | struct drm_i915_gem_relocation_entry *reloc; | |
27173f1f BW |
996 | struct i915_address_space *vm; |
997 | struct i915_vma *vma; | |
ed5982e6 | 998 | bool need_relocs; |
dd6864a4 | 999 | int *reloc_offset; |
54cf91dc | 1000 | int i, total, ret; |
b205ca57 | 1001 | unsigned count = args->buffer_count; |
54cf91dc | 1002 | |
27173f1f BW |
1003 | vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm; |
1004 | ||
67731b87 | 1005 | /* We may process another execbuffer during the unlock... */ |
27173f1f BW |
1006 | while (!list_empty(&eb->vmas)) { |
1007 | vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list); | |
1008 | list_del_init(&vma->exec_list); | |
a415d355 | 1009 | i915_gem_execbuffer_unreserve_vma(vma); |
624192cf | 1010 | i915_vma_put(vma); |
67731b87 CW |
1011 | } |
1012 | ||
54cf91dc CW |
1013 | mutex_unlock(&dev->struct_mutex); |
1014 | ||
1015 | total = 0; | |
1016 | for (i = 0; i < count; i++) | |
432e58ed | 1017 | total += exec[i].relocation_count; |
54cf91dc | 1018 | |
dd6864a4 | 1019 | reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset)); |
54cf91dc | 1020 | reloc = drm_malloc_ab(total, sizeof(*reloc)); |
dd6864a4 CW |
1021 | if (reloc == NULL || reloc_offset == NULL) { |
1022 | drm_free_large(reloc); | |
1023 | drm_free_large(reloc_offset); | |
54cf91dc CW |
1024 | mutex_lock(&dev->struct_mutex); |
1025 | return -ENOMEM; | |
1026 | } | |
1027 | ||
1028 | total = 0; | |
1029 | for (i = 0; i < count; i++) { | |
1030 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
262b6d36 CW |
1031 | u64 invalid_offset = (u64)-1; |
1032 | int j; | |
54cf91dc | 1033 | |
3ed605bc | 1034 | user_relocs = u64_to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
1035 | |
1036 | if (copy_from_user(reloc+total, user_relocs, | |
432e58ed | 1037 | exec[i].relocation_count * sizeof(*reloc))) { |
54cf91dc CW |
1038 | ret = -EFAULT; |
1039 | mutex_lock(&dev->struct_mutex); | |
1040 | goto err; | |
1041 | } | |
1042 | ||
262b6d36 CW |
1043 | /* As we do not update the known relocation offsets after |
1044 | * relocating (due to the complexities in lock handling), | |
1045 | * we need to mark them as invalid now so that we force the | |
1046 | * relocation processing next time. Just in case the target | |
1047 | * object is evicted and then rebound into its old | |
1048 | * presumed_offset before the next execbuffer - if that | |
1049 | * happened we would make the mistake of assuming that the | |
1050 | * relocations were valid. | |
1051 | */ | |
1052 | for (j = 0; j < exec[i].relocation_count; j++) { | |
9aab8bff CW |
1053 | if (__copy_to_user(&user_relocs[j].presumed_offset, |
1054 | &invalid_offset, | |
1055 | sizeof(invalid_offset))) { | |
262b6d36 CW |
1056 | ret = -EFAULT; |
1057 | mutex_lock(&dev->struct_mutex); | |
1058 | goto err; | |
1059 | } | |
1060 | } | |
1061 | ||
dd6864a4 | 1062 | reloc_offset[i] = total; |
432e58ed | 1063 | total += exec[i].relocation_count; |
54cf91dc CW |
1064 | } |
1065 | ||
1066 | ret = i915_mutex_lock_interruptible(dev); | |
1067 | if (ret) { | |
1068 | mutex_lock(&dev->struct_mutex); | |
1069 | goto err; | |
1070 | } | |
1071 | ||
67731b87 | 1072 | /* reacquire the objects */ |
67731b87 | 1073 | eb_reset(eb); |
27173f1f | 1074 | ret = eb_lookup_vmas(eb, exec, args, vm, file); |
3b96eff4 CW |
1075 | if (ret) |
1076 | goto err; | |
67731b87 | 1077 | |
ed5982e6 | 1078 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
0bc40be8 TU |
1079 | ret = i915_gem_execbuffer_reserve(engine, &eb->vmas, ctx, |
1080 | &need_relocs); | |
54cf91dc CW |
1081 | if (ret) |
1082 | goto err; | |
1083 | ||
27173f1f BW |
1084 | list_for_each_entry(vma, &eb->vmas, exec_list) { |
1085 | int offset = vma->exec_entry - exec; | |
1086 | ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb, | |
1087 | reloc + reloc_offset[offset]); | |
54cf91dc CW |
1088 | if (ret) |
1089 | goto err; | |
54cf91dc CW |
1090 | } |
1091 | ||
1092 | /* Leave the user relocations as are, this is the painfully slow path, | |
1093 | * and we want to avoid the complication of dropping the lock whilst | |
1094 | * having buffers reserved in the aperture and so causing spurious | |
1095 | * ENOSPC for random operations. | |
1096 | */ | |
1097 | ||
1098 | err: | |
1099 | drm_free_large(reloc); | |
dd6864a4 | 1100 | drm_free_large(reloc_offset); |
54cf91dc CW |
1101 | return ret; |
1102 | } | |
1103 | ||
54cf91dc | 1104 | static int |
535fbe82 | 1105 | i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req, |
27173f1f | 1106 | struct list_head *vmas) |
54cf91dc | 1107 | { |
27173f1f | 1108 | struct i915_vma *vma; |
432e58ed | 1109 | int ret; |
54cf91dc | 1110 | |
27173f1f BW |
1111 | list_for_each_entry(vma, vmas, exec_list) { |
1112 | struct drm_i915_gem_object *obj = vma->obj; | |
03ade511 | 1113 | |
d07f0e59 CW |
1114 | ret = i915_gem_request_await_object |
1115 | (req, obj, obj->base.pending_write_domain); | |
1116 | if (ret) | |
1117 | return ret; | |
851ba2d6 | 1118 | |
6ac42f41 | 1119 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) |
dcd79934 | 1120 | i915_gem_clflush_object(obj, false); |
c59a333f CW |
1121 | } |
1122 | ||
dcd79934 CW |
1123 | /* Unconditionally flush any chipset caches (for streaming writes). */ |
1124 | i915_gem_chipset_flush(req->engine->i915); | |
6ac42f41 | 1125 | |
c7fe7d25 | 1126 | /* Unconditionally invalidate GPU caches and TLBs. */ |
7c9cf4e3 | 1127 | return req->engine->emit_flush(req, EMIT_INVALIDATE); |
54cf91dc CW |
1128 | } |
1129 | ||
432e58ed CW |
1130 | static bool |
1131 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) | |
54cf91dc | 1132 | { |
ed5982e6 DV |
1133 | if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS) |
1134 | return false; | |
1135 | ||
2f5945bc CW |
1136 | /* Kernel clipping was a DRI1 misfeature */ |
1137 | if (exec->num_cliprects || exec->cliprects_ptr) | |
1138 | return false; | |
1139 | ||
1140 | if (exec->DR4 == 0xffffffff) { | |
1141 | DRM_DEBUG("UXA submitting garbage DR4, fixing up\n"); | |
1142 | exec->DR4 = 0; | |
1143 | } | |
1144 | if (exec->DR1 || exec->DR4) | |
1145 | return false; | |
1146 | ||
1147 | if ((exec->batch_start_offset | exec->batch_len) & 0x7) | |
1148 | return false; | |
1149 | ||
1150 | return true; | |
54cf91dc CW |
1151 | } |
1152 | ||
1153 | static int | |
ad19f10b CW |
1154 | validate_exec_list(struct drm_device *dev, |
1155 | struct drm_i915_gem_exec_object2 *exec, | |
54cf91dc CW |
1156 | int count) |
1157 | { | |
b205ca57 DV |
1158 | unsigned relocs_total = 0; |
1159 | unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry); | |
ad19f10b CW |
1160 | unsigned invalid_flags; |
1161 | int i; | |
1162 | ||
9e2793f6 DG |
1163 | /* INTERNAL flags must not overlap with external ones */ |
1164 | BUILD_BUG_ON(__EXEC_OBJECT_INTERNAL_FLAGS & ~__EXEC_OBJECT_UNKNOWN_FLAGS); | |
1165 | ||
ad19f10b CW |
1166 | invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS; |
1167 | if (USES_FULL_PPGTT(dev)) | |
1168 | invalid_flags |= EXEC_OBJECT_NEEDS_GTT; | |
54cf91dc CW |
1169 | |
1170 | for (i = 0; i < count; i++) { | |
3ed605bc | 1171 | char __user *ptr = u64_to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
1172 | int length; /* limited by fault_in_pages_readable() */ |
1173 | ||
ad19f10b | 1174 | if (exec[i].flags & invalid_flags) |
ed5982e6 DV |
1175 | return -EINVAL; |
1176 | ||
934acce3 MW |
1177 | /* Offset can be used as input (EXEC_OBJECT_PINNED), reject |
1178 | * any non-page-aligned or non-canonical addresses. | |
1179 | */ | |
1180 | if (exec[i].flags & EXEC_OBJECT_PINNED) { | |
1181 | if (exec[i].offset != | |
1182 | gen8_canonical_addr(exec[i].offset & PAGE_MASK)) | |
1183 | return -EINVAL; | |
1184 | ||
1185 | /* From drm_mm perspective address space is continuous, | |
1186 | * so from this point we're always using non-canonical | |
1187 | * form internally. | |
1188 | */ | |
1189 | exec[i].offset = gen8_noncanonical_addr(exec[i].offset); | |
1190 | } | |
1191 | ||
55a9785d CW |
1192 | if (exec[i].alignment && !is_power_of_2(exec[i].alignment)) |
1193 | return -EINVAL; | |
1194 | ||
91b2db6f CW |
1195 | /* pad_to_size was once a reserved field, so sanitize it */ |
1196 | if (exec[i].flags & EXEC_OBJECT_PAD_TO_SIZE) { | |
1197 | if (offset_in_page(exec[i].pad_to_size)) | |
1198 | return -EINVAL; | |
1199 | } else { | |
1200 | exec[i].pad_to_size = 0; | |
1201 | } | |
1202 | ||
3118a4f6 KC |
1203 | /* First check for malicious input causing overflow in |
1204 | * the worst case where we need to allocate the entire | |
1205 | * relocation tree as a single array. | |
1206 | */ | |
1207 | if (exec[i].relocation_count > relocs_max - relocs_total) | |
54cf91dc | 1208 | return -EINVAL; |
3118a4f6 | 1209 | relocs_total += exec[i].relocation_count; |
54cf91dc CW |
1210 | |
1211 | length = exec[i].relocation_count * | |
1212 | sizeof(struct drm_i915_gem_relocation_entry); | |
30587535 KC |
1213 | /* |
1214 | * We must check that the entire relocation array is safe | |
1215 | * to read, but since we may need to update the presumed | |
1216 | * offsets during execution, check for full write access. | |
1217 | */ | |
54cf91dc CW |
1218 | if (!access_ok(VERIFY_WRITE, ptr, length)) |
1219 | return -EFAULT; | |
1220 | ||
d330a953 | 1221 | if (likely(!i915.prefault_disable)) { |
4bce9f6e | 1222 | if (fault_in_pages_readable(ptr, length)) |
0b74b508 XZ |
1223 | return -EFAULT; |
1224 | } | |
54cf91dc CW |
1225 | } |
1226 | ||
1227 | return 0; | |
1228 | } | |
1229 | ||
e2efd130 | 1230 | static struct i915_gem_context * |
d299cce7 | 1231 | i915_gem_validate_context(struct drm_device *dev, struct drm_file *file, |
0bc40be8 | 1232 | struct intel_engine_cs *engine, const u32 ctx_id) |
d299cce7 | 1233 | { |
f7978a0c | 1234 | struct i915_gem_context *ctx; |
d299cce7 | 1235 | |
ca585b5d | 1236 | ctx = i915_gem_context_lookup(file->driver_priv, ctx_id); |
72ad5c45 | 1237 | if (IS_ERR(ctx)) |
41bde553 | 1238 | return ctx; |
d299cce7 | 1239 | |
6095868a | 1240 | if (i915_gem_context_is_banned(ctx)) { |
d299cce7 | 1241 | DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id); |
41bde553 | 1242 | return ERR_PTR(-EIO); |
d299cce7 MK |
1243 | } |
1244 | ||
41bde553 | 1245 | return ctx; |
d299cce7 MK |
1246 | } |
1247 | ||
7aa6ca61 CW |
1248 | static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
1249 | { | |
1250 | return !(obj->cache_level == I915_CACHE_NONE || | |
1251 | obj->cache_level == I915_CACHE_WT); | |
1252 | } | |
1253 | ||
5cf3d280 CW |
1254 | void i915_vma_move_to_active(struct i915_vma *vma, |
1255 | struct drm_i915_gem_request *req, | |
1256 | unsigned int flags) | |
1257 | { | |
1258 | struct drm_i915_gem_object *obj = vma->obj; | |
1259 | const unsigned int idx = req->engine->id; | |
1260 | ||
81147b07 | 1261 | lockdep_assert_held(&req->i915->drm.struct_mutex); |
5cf3d280 CW |
1262 | GEM_BUG_ON(!drm_mm_node_allocated(&vma->node)); |
1263 | ||
b0decaf7 CW |
1264 | /* Add a reference if we're newly entering the active list. |
1265 | * The order in which we add operations to the retirement queue is | |
1266 | * vital here: mark_active adds to the start of the callback list, | |
1267 | * such that subsequent callbacks are called first. Therefore we | |
1268 | * add the active reference first and queue for it to be dropped | |
1269 | * *last*. | |
1270 | */ | |
d07f0e59 CW |
1271 | if (!i915_vma_is_active(vma)) |
1272 | obj->active_count++; | |
1273 | i915_vma_set_active(vma, idx); | |
1274 | i915_gem_active_set(&vma->last_read[idx], req); | |
1275 | list_move_tail(&vma->vm_link, &vma->vm->active_list); | |
5cf3d280 CW |
1276 | |
1277 | if (flags & EXEC_OBJECT_WRITE) { | |
5b8c8aec CW |
1278 | if (intel_fb_obj_invalidate(obj, ORIGIN_CS)) |
1279 | i915_gem_active_set(&obj->frontbuffer_write, req); | |
5cf3d280 CW |
1280 | |
1281 | /* update for the implicit flush after a batch */ | |
1282 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
7aa6ca61 CW |
1283 | if (!obj->cache_dirty && gpu_write_needs_clflush(obj)) |
1284 | obj->cache_dirty = true; | |
5cf3d280 CW |
1285 | } |
1286 | ||
49ef5294 CW |
1287 | if (flags & EXEC_OBJECT_NEEDS_FENCE) |
1288 | i915_gem_active_set(&vma->last_fence, req); | |
5cf3d280 CW |
1289 | } |
1290 | ||
ad778f89 CW |
1291 | static void eb_export_fence(struct drm_i915_gem_object *obj, |
1292 | struct drm_i915_gem_request *req, | |
1293 | unsigned int flags) | |
1294 | { | |
d07f0e59 | 1295 | struct reservation_object *resv = obj->resv; |
ad778f89 CW |
1296 | |
1297 | /* Ignore errors from failing to allocate the new fence, we can't | |
1298 | * handle an error right now. Worst case should be missed | |
1299 | * synchronisation leading to rendering corruption. | |
1300 | */ | |
1301 | ww_mutex_lock(&resv->lock, NULL); | |
1302 | if (flags & EXEC_OBJECT_WRITE) | |
1303 | reservation_object_add_excl_fence(resv, &req->fence); | |
1304 | else if (reservation_object_reserve_shared(resv) == 0) | |
1305 | reservation_object_add_shared_fence(resv, &req->fence); | |
1306 | ww_mutex_unlock(&resv->lock); | |
1307 | } | |
1308 | ||
5b043f4e | 1309 | static void |
27173f1f | 1310 | i915_gem_execbuffer_move_to_active(struct list_head *vmas, |
8a8edb59 | 1311 | struct drm_i915_gem_request *req) |
432e58ed | 1312 | { |
27173f1f | 1313 | struct i915_vma *vma; |
432e58ed | 1314 | |
27173f1f BW |
1315 | list_for_each_entry(vma, vmas, exec_list) { |
1316 | struct drm_i915_gem_object *obj = vma->obj; | |
69c2fc89 CW |
1317 | u32 old_read = obj->base.read_domains; |
1318 | u32 old_write = obj->base.write_domain; | |
db53a302 | 1319 | |
432e58ed | 1320 | obj->base.write_domain = obj->base.pending_write_domain; |
5cf3d280 CW |
1321 | if (obj->base.write_domain) |
1322 | vma->exec_entry->flags |= EXEC_OBJECT_WRITE; | |
1323 | else | |
ed5982e6 DV |
1324 | obj->base.pending_read_domains |= obj->base.read_domains; |
1325 | obj->base.read_domains = obj->base.pending_read_domains; | |
432e58ed | 1326 | |
5cf3d280 | 1327 | i915_vma_move_to_active(vma, req, vma->exec_entry->flags); |
ad778f89 | 1328 | eb_export_fence(obj, req, vma->exec_entry->flags); |
db53a302 | 1329 | trace_i915_gem_object_change_domain(obj, old_read, old_write); |
432e58ed CW |
1330 | } |
1331 | } | |
1332 | ||
ae662d31 | 1333 | static int |
b5321f30 | 1334 | i915_reset_gen7_sol_offsets(struct drm_i915_gem_request *req) |
ae662d31 | 1335 | { |
7e37f889 | 1336 | struct intel_ring *ring = req->ring; |
ae662d31 EA |
1337 | int ret, i; |
1338 | ||
b5321f30 | 1339 | if (!IS_GEN7(req->i915) || req->engine->id != RCS) { |
9d662da8 DV |
1340 | DRM_DEBUG("sol reset is gen7/rcs only\n"); |
1341 | return -EINVAL; | |
1342 | } | |
ae662d31 | 1343 | |
5fb9de1a | 1344 | ret = intel_ring_begin(req, 4 * 3); |
ae662d31 EA |
1345 | if (ret) |
1346 | return ret; | |
1347 | ||
1348 | for (i = 0; i < 4; i++) { | |
b5321f30 CW |
1349 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
1350 | intel_ring_emit_reg(ring, GEN7_SO_WRITE_OFFSET(i)); | |
1351 | intel_ring_emit(ring, 0); | |
ae662d31 EA |
1352 | } |
1353 | ||
b5321f30 | 1354 | intel_ring_advance(ring); |
ae662d31 EA |
1355 | |
1356 | return 0; | |
1357 | } | |
1358 | ||
058d88c4 | 1359 | static struct i915_vma * |
0bc40be8 | 1360 | i915_gem_execbuffer_parse(struct intel_engine_cs *engine, |
71745376 | 1361 | struct drm_i915_gem_exec_object2 *shadow_exec_entry, |
71745376 | 1362 | struct drm_i915_gem_object *batch_obj, |
59bfa124 | 1363 | struct eb_vmas *eb, |
71745376 BV |
1364 | u32 batch_start_offset, |
1365 | u32 batch_len, | |
17cabf57 | 1366 | bool is_master) |
71745376 | 1367 | { |
71745376 | 1368 | struct drm_i915_gem_object *shadow_batch_obj; |
17cabf57 | 1369 | struct i915_vma *vma; |
71745376 BV |
1370 | int ret; |
1371 | ||
0bc40be8 | 1372 | shadow_batch_obj = i915_gem_batch_pool_get(&engine->batch_pool, |
17cabf57 | 1373 | PAGE_ALIGN(batch_len)); |
71745376 | 1374 | if (IS_ERR(shadow_batch_obj)) |
59bfa124 | 1375 | return ERR_CAST(shadow_batch_obj); |
71745376 | 1376 | |
33a051a5 CW |
1377 | ret = intel_engine_cmd_parser(engine, |
1378 | batch_obj, | |
1379 | shadow_batch_obj, | |
1380 | batch_start_offset, | |
1381 | batch_len, | |
1382 | is_master); | |
058d88c4 CW |
1383 | if (ret) { |
1384 | if (ret == -EACCES) /* unhandled chained batch */ | |
1385 | vma = NULL; | |
1386 | else | |
1387 | vma = ERR_PTR(ret); | |
1388 | goto out; | |
1389 | } | |
71745376 | 1390 | |
058d88c4 CW |
1391 | vma = i915_gem_object_ggtt_pin(shadow_batch_obj, NULL, 0, 0, 0); |
1392 | if (IS_ERR(vma)) | |
1393 | goto out; | |
de4e783a | 1394 | |
17cabf57 | 1395 | memset(shadow_exec_entry, 0, sizeof(*shadow_exec_entry)); |
71745376 | 1396 | |
17cabf57 | 1397 | vma->exec_entry = shadow_exec_entry; |
de4e783a | 1398 | vma->exec_entry->flags = __EXEC_OBJECT_HAS_PIN; |
25dc556a | 1399 | i915_gem_object_get(shadow_batch_obj); |
17cabf57 | 1400 | list_add_tail(&vma->exec_list, &eb->vmas); |
71745376 | 1401 | |
058d88c4 | 1402 | out: |
de4e783a | 1403 | i915_gem_object_unpin_pages(shadow_batch_obj); |
058d88c4 | 1404 | return vma; |
71745376 | 1405 | } |
5c6c6003 | 1406 | |
5b043f4e CW |
1407 | static int |
1408 | execbuf_submit(struct i915_execbuffer_params *params, | |
1409 | struct drm_i915_gem_execbuffer2 *args, | |
1410 | struct list_head *vmas) | |
78382593 | 1411 | { |
b5321f30 | 1412 | struct drm_i915_private *dev_priv = params->request->i915; |
5f19e2bf | 1413 | u64 exec_start, exec_len; |
78382593 OM |
1414 | int instp_mode; |
1415 | u32 instp_mask; | |
2f5945bc | 1416 | int ret; |
78382593 | 1417 | |
535fbe82 | 1418 | ret = i915_gem_execbuffer_move_to_gpu(params->request, vmas); |
78382593 | 1419 | if (ret) |
2f5945bc | 1420 | return ret; |
78382593 | 1421 | |
ba01cc93 | 1422 | ret = i915_switch_context(params->request); |
78382593 | 1423 | if (ret) |
2f5945bc | 1424 | return ret; |
78382593 OM |
1425 | |
1426 | instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK; | |
1427 | instp_mask = I915_EXEC_CONSTANTS_MASK; | |
1428 | switch (instp_mode) { | |
1429 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
1430 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
1431 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
b5321f30 | 1432 | if (instp_mode != 0 && params->engine->id != RCS) { |
78382593 | 1433 | DRM_DEBUG("non-0 rel constants mode on non-RCS\n"); |
2f5945bc | 1434 | return -EINVAL; |
78382593 OM |
1435 | } |
1436 | ||
1437 | if (instp_mode != dev_priv->relative_constants_mode) { | |
b5321f30 | 1438 | if (INTEL_INFO(dev_priv)->gen < 4) { |
78382593 | 1439 | DRM_DEBUG("no rel constants on pre-gen4\n"); |
2f5945bc | 1440 | return -EINVAL; |
78382593 OM |
1441 | } |
1442 | ||
b5321f30 | 1443 | if (INTEL_INFO(dev_priv)->gen > 5 && |
78382593 OM |
1444 | instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) { |
1445 | DRM_DEBUG("rel surface constants mode invalid on gen5+\n"); | |
2f5945bc | 1446 | return -EINVAL; |
78382593 OM |
1447 | } |
1448 | ||
1449 | /* The HW changed the meaning on this bit on gen6 */ | |
b5321f30 | 1450 | if (INTEL_INFO(dev_priv)->gen >= 6) |
78382593 OM |
1451 | instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; |
1452 | } | |
1453 | break; | |
1454 | default: | |
1455 | DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode); | |
2f5945bc | 1456 | return -EINVAL; |
78382593 OM |
1457 | } |
1458 | ||
b5321f30 | 1459 | if (params->engine->id == RCS && |
2f5945bc | 1460 | instp_mode != dev_priv->relative_constants_mode) { |
7e37f889 | 1461 | struct intel_ring *ring = params->request->ring; |
b5321f30 | 1462 | |
5fb9de1a | 1463 | ret = intel_ring_begin(params->request, 4); |
78382593 | 1464 | if (ret) |
2f5945bc | 1465 | return ret; |
78382593 | 1466 | |
b5321f30 CW |
1467 | intel_ring_emit(ring, MI_NOOP); |
1468 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
1469 | intel_ring_emit_reg(ring, INSTPM); | |
1470 | intel_ring_emit(ring, instp_mask << 16 | instp_mode); | |
1471 | intel_ring_advance(ring); | |
78382593 OM |
1472 | |
1473 | dev_priv->relative_constants_mode = instp_mode; | |
1474 | } | |
1475 | ||
1476 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { | |
b5321f30 | 1477 | ret = i915_reset_gen7_sol_offsets(params->request); |
78382593 | 1478 | if (ret) |
2f5945bc | 1479 | return ret; |
78382593 OM |
1480 | } |
1481 | ||
5f19e2bf | 1482 | exec_len = args->batch_len; |
59bfa124 | 1483 | exec_start = params->batch->node.start + |
5f19e2bf JH |
1484 | params->args_batch_start_offset; |
1485 | ||
9d611c03 | 1486 | if (exec_len == 0) |
0b537272 | 1487 | exec_len = params->batch->size - params->args_batch_start_offset; |
9d611c03 | 1488 | |
803688ba CW |
1489 | ret = params->engine->emit_bb_start(params->request, |
1490 | exec_start, exec_len, | |
1491 | params->dispatch_flags); | |
2f5945bc CW |
1492 | if (ret) |
1493 | return ret; | |
78382593 | 1494 | |
95c24161 | 1495 | trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags); |
78382593 | 1496 | |
8a8edb59 | 1497 | i915_gem_execbuffer_move_to_active(vmas, params->request); |
78382593 | 1498 | |
2f5945bc | 1499 | return 0; |
78382593 OM |
1500 | } |
1501 | ||
a8ebba75 ZY |
1502 | /** |
1503 | * Find one BSD ring to dispatch the corresponding BSD command. | |
c80ff16e | 1504 | * The engine index is returned. |
a8ebba75 | 1505 | */ |
de1add36 | 1506 | static unsigned int |
c80ff16e CW |
1507 | gen8_dispatch_bsd_engine(struct drm_i915_private *dev_priv, |
1508 | struct drm_file *file) | |
a8ebba75 | 1509 | { |
a8ebba75 ZY |
1510 | struct drm_i915_file_private *file_priv = file->driver_priv; |
1511 | ||
de1add36 | 1512 | /* Check whether the file_priv has already selected one ring. */ |
6f633402 JL |
1513 | if ((int)file_priv->bsd_engine < 0) |
1514 | file_priv->bsd_engine = atomic_fetch_xor(1, | |
1515 | &dev_priv->mm.bsd_engine_dispatch_index); | |
d23db88c | 1516 | |
c80ff16e | 1517 | return file_priv->bsd_engine; |
d23db88c CW |
1518 | } |
1519 | ||
de1add36 TU |
1520 | #define I915_USER_RINGS (4) |
1521 | ||
117897f4 | 1522 | static const enum intel_engine_id user_ring_map[I915_USER_RINGS + 1] = { |
de1add36 TU |
1523 | [I915_EXEC_DEFAULT] = RCS, |
1524 | [I915_EXEC_RENDER] = RCS, | |
1525 | [I915_EXEC_BLT] = BCS, | |
1526 | [I915_EXEC_BSD] = VCS, | |
1527 | [I915_EXEC_VEBOX] = VECS | |
1528 | }; | |
1529 | ||
f8ca0c07 DG |
1530 | static struct intel_engine_cs * |
1531 | eb_select_engine(struct drm_i915_private *dev_priv, | |
1532 | struct drm_file *file, | |
1533 | struct drm_i915_gem_execbuffer2 *args) | |
de1add36 TU |
1534 | { |
1535 | unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK; | |
f8ca0c07 | 1536 | struct intel_engine_cs *engine; |
de1add36 TU |
1537 | |
1538 | if (user_ring_id > I915_USER_RINGS) { | |
1539 | DRM_DEBUG("execbuf with unknown ring: %u\n", user_ring_id); | |
f8ca0c07 | 1540 | return NULL; |
de1add36 TU |
1541 | } |
1542 | ||
1543 | if ((user_ring_id != I915_EXEC_BSD) && | |
1544 | ((args->flags & I915_EXEC_BSD_MASK) != 0)) { | |
1545 | DRM_DEBUG("execbuf with non bsd ring but with invalid " | |
1546 | "bsd dispatch flags: %d\n", (int)(args->flags)); | |
f8ca0c07 | 1547 | return NULL; |
de1add36 TU |
1548 | } |
1549 | ||
1550 | if (user_ring_id == I915_EXEC_BSD && HAS_BSD2(dev_priv)) { | |
1551 | unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK; | |
1552 | ||
1553 | if (bsd_idx == I915_EXEC_BSD_DEFAULT) { | |
c80ff16e | 1554 | bsd_idx = gen8_dispatch_bsd_engine(dev_priv, file); |
de1add36 TU |
1555 | } else if (bsd_idx >= I915_EXEC_BSD_RING1 && |
1556 | bsd_idx <= I915_EXEC_BSD_RING2) { | |
d9da6aa0 | 1557 | bsd_idx >>= I915_EXEC_BSD_SHIFT; |
de1add36 TU |
1558 | bsd_idx--; |
1559 | } else { | |
1560 | DRM_DEBUG("execbuf with unknown bsd ring: %u\n", | |
1561 | bsd_idx); | |
f8ca0c07 | 1562 | return NULL; |
de1add36 TU |
1563 | } |
1564 | ||
3b3f1650 | 1565 | engine = dev_priv->engine[_VCS(bsd_idx)]; |
de1add36 | 1566 | } else { |
3b3f1650 | 1567 | engine = dev_priv->engine[user_ring_map[user_ring_id]]; |
de1add36 TU |
1568 | } |
1569 | ||
3b3f1650 | 1570 | if (!engine) { |
de1add36 | 1571 | DRM_DEBUG("execbuf with invalid ring: %u\n", user_ring_id); |
f8ca0c07 | 1572 | return NULL; |
de1add36 TU |
1573 | } |
1574 | ||
f8ca0c07 | 1575 | return engine; |
de1add36 TU |
1576 | } |
1577 | ||
54cf91dc CW |
1578 | static int |
1579 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, | |
1580 | struct drm_file *file, | |
1581 | struct drm_i915_gem_execbuffer2 *args, | |
41bde553 | 1582 | struct drm_i915_gem_exec_object2 *exec) |
54cf91dc | 1583 | { |
72e96d64 JL |
1584 | struct drm_i915_private *dev_priv = to_i915(dev); |
1585 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
27173f1f | 1586 | struct eb_vmas *eb; |
78a42377 | 1587 | struct drm_i915_gem_exec_object2 shadow_exec_entry; |
e2f80391 | 1588 | struct intel_engine_cs *engine; |
e2efd130 | 1589 | struct i915_gem_context *ctx; |
41bde553 | 1590 | struct i915_address_space *vm; |
5f19e2bf JH |
1591 | struct i915_execbuffer_params params_master; /* XXX: will be removed later */ |
1592 | struct i915_execbuffer_params *params = ¶ms_master; | |
d299cce7 | 1593 | const u32 ctx_id = i915_execbuffer2_get_context_id(*args); |
8e004efc | 1594 | u32 dispatch_flags; |
78382593 | 1595 | int ret; |
ed5982e6 | 1596 | bool need_relocs; |
54cf91dc | 1597 | |
ed5982e6 | 1598 | if (!i915_gem_check_execbuffer(args)) |
432e58ed | 1599 | return -EINVAL; |
432e58ed | 1600 | |
ad19f10b | 1601 | ret = validate_exec_list(dev, exec, args->buffer_count); |
54cf91dc CW |
1602 | if (ret) |
1603 | return ret; | |
1604 | ||
8e004efc | 1605 | dispatch_flags = 0; |
d7d4eedd | 1606 | if (args->flags & I915_EXEC_SECURE) { |
b3ac9f25 | 1607 | if (!drm_is_current_master(file) || !capable(CAP_SYS_ADMIN)) |
d7d4eedd CW |
1608 | return -EPERM; |
1609 | ||
8e004efc | 1610 | dispatch_flags |= I915_DISPATCH_SECURE; |
d7d4eedd | 1611 | } |
b45305fc | 1612 | if (args->flags & I915_EXEC_IS_PINNED) |
8e004efc | 1613 | dispatch_flags |= I915_DISPATCH_PINNED; |
d7d4eedd | 1614 | |
f8ca0c07 DG |
1615 | engine = eb_select_engine(dev_priv, file, args); |
1616 | if (!engine) | |
1617 | return -EINVAL; | |
54cf91dc CW |
1618 | |
1619 | if (args->buffer_count < 1) { | |
ff240199 | 1620 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1621 | return -EINVAL; |
1622 | } | |
54cf91dc | 1623 | |
a9ed33ca | 1624 | if (args->flags & I915_EXEC_RESOURCE_STREAMER) { |
4805fe82 | 1625 | if (!HAS_RESOURCE_STREAMER(dev_priv)) { |
a9ed33ca AJ |
1626 | DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n"); |
1627 | return -EINVAL; | |
1628 | } | |
e2f80391 | 1629 | if (engine->id != RCS) { |
a9ed33ca | 1630 | DRM_DEBUG("RS is not available on %s\n", |
e2f80391 | 1631 | engine->name); |
a9ed33ca AJ |
1632 | return -EINVAL; |
1633 | } | |
1634 | ||
1635 | dispatch_flags |= I915_DISPATCH_RS; | |
1636 | } | |
1637 | ||
67d97da3 CW |
1638 | /* Take a local wakeref for preparing to dispatch the execbuf as |
1639 | * we expect to access the hardware fairly frequently in the | |
1640 | * process. Upon first dispatch, we acquire another prolonged | |
1641 | * wakeref that we hold until the GPU has been idle for at least | |
1642 | * 100ms. | |
1643 | */ | |
f65c9168 PZ |
1644 | intel_runtime_pm_get(dev_priv); |
1645 | ||
54cf91dc CW |
1646 | ret = i915_mutex_lock_interruptible(dev); |
1647 | if (ret) | |
1648 | goto pre_mutex_err; | |
1649 | ||
e2f80391 | 1650 | ctx = i915_gem_validate_context(dev, file, engine, ctx_id); |
72ad5c45 | 1651 | if (IS_ERR(ctx)) { |
d299cce7 | 1652 | mutex_unlock(&dev->struct_mutex); |
41bde553 | 1653 | ret = PTR_ERR(ctx); |
d299cce7 | 1654 | goto pre_mutex_err; |
935f38d6 | 1655 | } |
41bde553 | 1656 | |
9a6feaf0 | 1657 | i915_gem_context_get(ctx); |
41bde553 | 1658 | |
ae6c4806 DV |
1659 | if (ctx->ppgtt) |
1660 | vm = &ctx->ppgtt->base; | |
1661 | else | |
72e96d64 | 1662 | vm = &ggtt->base; |
d299cce7 | 1663 | |
5f19e2bf JH |
1664 | memset(¶ms_master, 0x00, sizeof(params_master)); |
1665 | ||
d50415cc | 1666 | eb = eb_create(dev_priv, args); |
67731b87 | 1667 | if (eb == NULL) { |
9a6feaf0 | 1668 | i915_gem_context_put(ctx); |
67731b87 CW |
1669 | mutex_unlock(&dev->struct_mutex); |
1670 | ret = -ENOMEM; | |
1671 | goto pre_mutex_err; | |
1672 | } | |
1673 | ||
54cf91dc | 1674 | /* Look up object handles */ |
27173f1f | 1675 | ret = eb_lookup_vmas(eb, exec, args, vm, file); |
3b96eff4 CW |
1676 | if (ret) |
1677 | goto err; | |
54cf91dc | 1678 | |
6fe4f140 | 1679 | /* take note of the batch buffer before we might reorder the lists */ |
59bfa124 | 1680 | params->batch = eb_get_batch(eb); |
6fe4f140 | 1681 | |
54cf91dc | 1682 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
ed5982e6 | 1683 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
e2f80391 TU |
1684 | ret = i915_gem_execbuffer_reserve(engine, &eb->vmas, ctx, |
1685 | &need_relocs); | |
54cf91dc CW |
1686 | if (ret) |
1687 | goto err; | |
1688 | ||
1689 | /* The objects are in their final locations, apply the relocations. */ | |
ed5982e6 | 1690 | if (need_relocs) |
17601cbc | 1691 | ret = i915_gem_execbuffer_relocate(eb); |
54cf91dc CW |
1692 | if (ret) { |
1693 | if (ret == -EFAULT) { | |
e2f80391 TU |
1694 | ret = i915_gem_execbuffer_relocate_slow(dev, args, file, |
1695 | engine, | |
b1b38278 | 1696 | eb, exec, ctx); |
54cf91dc CW |
1697 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
1698 | } | |
1699 | if (ret) | |
1700 | goto err; | |
1701 | } | |
1702 | ||
1703 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
59bfa124 | 1704 | if (params->batch->obj->base.pending_write_domain) { |
ff240199 | 1705 | DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); |
54cf91dc CW |
1706 | ret = -EINVAL; |
1707 | goto err; | |
1708 | } | |
0b537272 CW |
1709 | if (args->batch_start_offset > params->batch->size || |
1710 | args->batch_len > params->batch->size - args->batch_start_offset) { | |
1711 | DRM_DEBUG("Attempting to use out-of-bounds batch\n"); | |
1712 | ret = -EINVAL; | |
1713 | goto err; | |
1714 | } | |
54cf91dc | 1715 | |
5f19e2bf | 1716 | params->args_batch_start_offset = args->batch_start_offset; |
41736a8e | 1717 | if (engine->needs_cmd_parser && args->batch_len) { |
59bfa124 CW |
1718 | struct i915_vma *vma; |
1719 | ||
1720 | vma = i915_gem_execbuffer_parse(engine, &shadow_exec_entry, | |
1721 | params->batch->obj, | |
1722 | eb, | |
1723 | args->batch_start_offset, | |
1724 | args->batch_len, | |
1725 | drm_is_current_master(file)); | |
1726 | if (IS_ERR(vma)) { | |
1727 | ret = PTR_ERR(vma); | |
78a42377 BV |
1728 | goto err; |
1729 | } | |
17cabf57 | 1730 | |
59bfa124 | 1731 | if (vma) { |
c7c7372e RP |
1732 | /* |
1733 | * Batch parsed and accepted: | |
1734 | * | |
1735 | * Set the DISPATCH_SECURE bit to remove the NON_SECURE | |
1736 | * bit from MI_BATCH_BUFFER_START commands issued in | |
1737 | * the dispatch_execbuffer implementations. We | |
1738 | * specifically don't want that set on batches the | |
1739 | * command parser has accepted. | |
1740 | */ | |
1741 | dispatch_flags |= I915_DISPATCH_SECURE; | |
5f19e2bf | 1742 | params->args_batch_start_offset = 0; |
59bfa124 | 1743 | params->batch = vma; |
c7c7372e | 1744 | } |
351e3db2 BV |
1745 | } |
1746 | ||
59bfa124 | 1747 | params->batch->obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; |
78a42377 | 1748 | |
d7d4eedd CW |
1749 | /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure |
1750 | * batch" bit. Hence we need to pin secure batches into the global gtt. | |
28cf5415 | 1751 | * hsw should have this fixed, but bdw mucks it up again. */ |
8e004efc | 1752 | if (dispatch_flags & I915_DISPATCH_SECURE) { |
59bfa124 | 1753 | struct drm_i915_gem_object *obj = params->batch->obj; |
058d88c4 | 1754 | struct i915_vma *vma; |
59bfa124 | 1755 | |
da51a1e7 DV |
1756 | /* |
1757 | * So on first glance it looks freaky that we pin the batch here | |
1758 | * outside of the reservation loop. But: | |
1759 | * - The batch is already pinned into the relevant ppgtt, so we | |
1760 | * already have the backing storage fully allocated. | |
1761 | * - No other BO uses the global gtt (well contexts, but meh), | |
fd0753cf | 1762 | * so we don't really have issues with multiple objects not |
da51a1e7 DV |
1763 | * fitting due to fragmentation. |
1764 | * So this is actually safe. | |
1765 | */ | |
058d88c4 CW |
1766 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0); |
1767 | if (IS_ERR(vma)) { | |
1768 | ret = PTR_ERR(vma); | |
da51a1e7 | 1769 | goto err; |
058d88c4 | 1770 | } |
d7d4eedd | 1771 | |
058d88c4 | 1772 | params->batch = vma; |
59bfa124 | 1773 | } |
d7d4eedd | 1774 | |
0c8dac88 | 1775 | /* Allocate a request for this batch buffer nice and early. */ |
8e637178 CW |
1776 | params->request = i915_gem_request_alloc(engine, ctx); |
1777 | if (IS_ERR(params->request)) { | |
1778 | ret = PTR_ERR(params->request); | |
0c8dac88 | 1779 | goto err_batch_unpin; |
26827088 | 1780 | } |
0c8dac88 | 1781 | |
17f298cf CW |
1782 | /* Whilst this request exists, batch_obj will be on the |
1783 | * active_list, and so will hold the active reference. Only when this | |
1784 | * request is retired will the the batch_obj be moved onto the | |
1785 | * inactive_list and lose its active reference. Hence we do not need | |
1786 | * to explicitly hold another reference here. | |
1787 | */ | |
058d88c4 | 1788 | params->request->batch = params->batch; |
17f298cf | 1789 | |
8e637178 | 1790 | ret = i915_gem_request_add_to_client(params->request, file); |
fcfa423c | 1791 | if (ret) |
aa9b7810 | 1792 | goto err_request; |
fcfa423c | 1793 | |
5f19e2bf JH |
1794 | /* |
1795 | * Save assorted stuff away to pass through to *_submission(). | |
1796 | * NB: This data should be 'persistent' and not local as it will | |
1797 | * kept around beyond the duration of the IOCTL once the GPU | |
1798 | * scheduler arrives. | |
1799 | */ | |
1800 | params->dev = dev; | |
1801 | params->file = file; | |
4a570db5 | 1802 | params->engine = engine; |
5f19e2bf | 1803 | params->dispatch_flags = dispatch_flags; |
5f19e2bf JH |
1804 | params->ctx = ctx; |
1805 | ||
5b043f4e | 1806 | ret = execbuf_submit(params, args, &eb->vmas); |
aa9b7810 | 1807 | err_request: |
17f298cf | 1808 | __i915_add_request(params->request, ret == 0); |
54cf91dc | 1809 | |
0c8dac88 | 1810 | err_batch_unpin: |
da51a1e7 DV |
1811 | /* |
1812 | * FIXME: We crucially rely upon the active tracking for the (ppgtt) | |
1813 | * batch vma for correctness. For less ugly and less fragility this | |
1814 | * needs to be adjusted to also track the ggtt batch vma properly as | |
1815 | * active. | |
1816 | */ | |
8e004efc | 1817 | if (dispatch_flags & I915_DISPATCH_SECURE) |
59bfa124 | 1818 | i915_vma_unpin(params->batch); |
54cf91dc | 1819 | err: |
41bde553 | 1820 | /* the request owns the ref now */ |
9a6feaf0 | 1821 | i915_gem_context_put(ctx); |
67731b87 | 1822 | eb_destroy(eb); |
54cf91dc CW |
1823 | |
1824 | mutex_unlock(&dev->struct_mutex); | |
1825 | ||
1826 | pre_mutex_err: | |
f65c9168 PZ |
1827 | /* intel_gpu_busy should also get a ref, so it will free when the device |
1828 | * is really idle. */ | |
1829 | intel_runtime_pm_put(dev_priv); | |
54cf91dc CW |
1830 | return ret; |
1831 | } | |
1832 | ||
1833 | /* | |
1834 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
1835 | * list array and passes it to the real function. | |
1836 | */ | |
1837 | int | |
1838 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1839 | struct drm_file *file) | |
1840 | { | |
1841 | struct drm_i915_gem_execbuffer *args = data; | |
1842 | struct drm_i915_gem_execbuffer2 exec2; | |
1843 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
1844 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1845 | int ret, i; | |
1846 | ||
54cf91dc | 1847 | if (args->buffer_count < 1) { |
ff240199 | 1848 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1849 | return -EINVAL; |
1850 | } | |
1851 | ||
1852 | /* Copy in the exec list from userland */ | |
1853 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
1854 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
1855 | if (exec_list == NULL || exec2_list == NULL) { | |
ff240199 | 1856 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1857 | args->buffer_count); |
1858 | drm_free_large(exec_list); | |
1859 | drm_free_large(exec2_list); | |
1860 | return -ENOMEM; | |
1861 | } | |
1862 | ret = copy_from_user(exec_list, | |
3ed605bc | 1863 | u64_to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1864 | sizeof(*exec_list) * args->buffer_count); |
1865 | if (ret != 0) { | |
ff240199 | 1866 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1867 | args->buffer_count, ret); |
1868 | drm_free_large(exec_list); | |
1869 | drm_free_large(exec2_list); | |
1870 | return -EFAULT; | |
1871 | } | |
1872 | ||
1873 | for (i = 0; i < args->buffer_count; i++) { | |
1874 | exec2_list[i].handle = exec_list[i].handle; | |
1875 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
1876 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
1877 | exec2_list[i].alignment = exec_list[i].alignment; | |
1878 | exec2_list[i].offset = exec_list[i].offset; | |
f0836b72 | 1879 | if (INTEL_GEN(to_i915(dev)) < 4) |
54cf91dc CW |
1880 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; |
1881 | else | |
1882 | exec2_list[i].flags = 0; | |
1883 | } | |
1884 | ||
1885 | exec2.buffers_ptr = args->buffers_ptr; | |
1886 | exec2.buffer_count = args->buffer_count; | |
1887 | exec2.batch_start_offset = args->batch_start_offset; | |
1888 | exec2.batch_len = args->batch_len; | |
1889 | exec2.DR1 = args->DR1; | |
1890 | exec2.DR4 = args->DR4; | |
1891 | exec2.num_cliprects = args->num_cliprects; | |
1892 | exec2.cliprects_ptr = args->cliprects_ptr; | |
1893 | exec2.flags = I915_EXEC_RENDER; | |
6e0a69db | 1894 | i915_execbuffer2_set_context_id(exec2, 0); |
54cf91dc | 1895 | |
41bde553 | 1896 | ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list); |
54cf91dc | 1897 | if (!ret) { |
9aab8bff | 1898 | struct drm_i915_gem_exec_object __user *user_exec_list = |
3ed605bc | 1899 | u64_to_user_ptr(args->buffers_ptr); |
9aab8bff | 1900 | |
54cf91dc | 1901 | /* Copy the new buffer offsets back to the user's exec list. */ |
9aab8bff | 1902 | for (i = 0; i < args->buffer_count; i++) { |
934acce3 MW |
1903 | exec2_list[i].offset = |
1904 | gen8_canonical_addr(exec2_list[i].offset); | |
9aab8bff CW |
1905 | ret = __copy_to_user(&user_exec_list[i].offset, |
1906 | &exec2_list[i].offset, | |
1907 | sizeof(user_exec_list[i].offset)); | |
1908 | if (ret) { | |
1909 | ret = -EFAULT; | |
1910 | DRM_DEBUG("failed to copy %d exec entries " | |
1911 | "back to user (%d)\n", | |
1912 | args->buffer_count, ret); | |
1913 | break; | |
1914 | } | |
54cf91dc CW |
1915 | } |
1916 | } | |
1917 | ||
1918 | drm_free_large(exec_list); | |
1919 | drm_free_large(exec2_list); | |
1920 | return ret; | |
1921 | } | |
1922 | ||
1923 | int | |
1924 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
1925 | struct drm_file *file) | |
1926 | { | |
1927 | struct drm_i915_gem_execbuffer2 *args = data; | |
1928 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1929 | int ret; | |
1930 | ||
ed8cd3b2 XW |
1931 | if (args->buffer_count < 1 || |
1932 | args->buffer_count > UINT_MAX / sizeof(*exec2_list)) { | |
ff240199 | 1933 | DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1934 | return -EINVAL; |
1935 | } | |
1936 | ||
9cb34664 DV |
1937 | if (args->rsvd2 != 0) { |
1938 | DRM_DEBUG("dirty rvsd2 field\n"); | |
1939 | return -EINVAL; | |
1940 | } | |
1941 | ||
f2a85e19 CW |
1942 | exec2_list = drm_malloc_gfp(args->buffer_count, |
1943 | sizeof(*exec2_list), | |
1944 | GFP_TEMPORARY); | |
54cf91dc | 1945 | if (exec2_list == NULL) { |
ff240199 | 1946 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1947 | args->buffer_count); |
1948 | return -ENOMEM; | |
1949 | } | |
1950 | ret = copy_from_user(exec2_list, | |
3ed605bc | 1951 | u64_to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1952 | sizeof(*exec2_list) * args->buffer_count); |
1953 | if (ret != 0) { | |
ff240199 | 1954 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1955 | args->buffer_count, ret); |
1956 | drm_free_large(exec2_list); | |
1957 | return -EFAULT; | |
1958 | } | |
1959 | ||
41bde553 | 1960 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list); |
54cf91dc CW |
1961 | if (!ret) { |
1962 | /* Copy the new buffer offsets back to the user's exec list. */ | |
d593d992 | 1963 | struct drm_i915_gem_exec_object2 __user *user_exec_list = |
3ed605bc | 1964 | u64_to_user_ptr(args->buffers_ptr); |
9aab8bff CW |
1965 | int i; |
1966 | ||
1967 | for (i = 0; i < args->buffer_count; i++) { | |
934acce3 MW |
1968 | exec2_list[i].offset = |
1969 | gen8_canonical_addr(exec2_list[i].offset); | |
9aab8bff CW |
1970 | ret = __copy_to_user(&user_exec_list[i].offset, |
1971 | &exec2_list[i].offset, | |
1972 | sizeof(user_exec_list[i].offset)); | |
1973 | if (ret) { | |
1974 | ret = -EFAULT; | |
1975 | DRM_DEBUG("failed to copy %d exec entries " | |
1976 | "back to user\n", | |
1977 | args->buffer_count); | |
1978 | break; | |
1979 | } | |
54cf91dc CW |
1980 | } |
1981 | } | |
1982 | ||
1983 | drm_free_large(exec2_list); | |
1984 | return ret; | |
1985 | } |