Commit | Line | Data |
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54cf91dc CW |
1 | /* |
2 | * Copyright © 2008,2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Chris Wilson <chris@chris-wilson.co.uk> | |
26 | * | |
27 | */ | |
28 | ||
760285e7 DH |
29 | #include <drm/drmP.h> |
30 | #include <drm/i915_drm.h> | |
54cf91dc CW |
31 | #include "i915_drv.h" |
32 | #include "i915_trace.h" | |
33 | #include "intel_drv.h" | |
5d723d7a | 34 | #include "intel_frontbuffer.h" |
f45b5557 | 35 | #include <linux/dma_remapping.h> |
32d82067 | 36 | #include <linux/uaccess.h> |
54cf91dc | 37 | |
9e2793f6 DG |
38 | #define __EXEC_OBJECT_HAS_PIN (1<<31) |
39 | #define __EXEC_OBJECT_HAS_FENCE (1<<30) | |
40 | #define __EXEC_OBJECT_NEEDS_MAP (1<<29) | |
41 | #define __EXEC_OBJECT_NEEDS_BIAS (1<<28) | |
42 | #define __EXEC_OBJECT_INTERNAL_FLAGS (0xf<<28) /* all of the above */ | |
d23db88c CW |
43 | |
44 | #define BATCH_OFFSET_BIAS (256*1024) | |
a415d355 | 45 | |
5b043f4e CW |
46 | struct i915_execbuffer_params { |
47 | struct drm_device *dev; | |
48 | struct drm_file *file; | |
59bfa124 CW |
49 | struct i915_vma *batch; |
50 | u32 dispatch_flags; | |
51 | u32 args_batch_start_offset; | |
5b043f4e | 52 | struct intel_engine_cs *engine; |
5b043f4e CW |
53 | struct i915_gem_context *ctx; |
54 | struct drm_i915_gem_request *request; | |
55 | }; | |
56 | ||
27173f1f BW |
57 | struct eb_vmas { |
58 | struct list_head vmas; | |
67731b87 | 59 | int and; |
eef90ccb | 60 | union { |
27173f1f | 61 | struct i915_vma *lut[0]; |
eef90ccb CW |
62 | struct hlist_head buckets[0]; |
63 | }; | |
67731b87 CW |
64 | }; |
65 | ||
27173f1f | 66 | static struct eb_vmas * |
17601cbc | 67 | eb_create(struct drm_i915_gem_execbuffer2 *args) |
67731b87 | 68 | { |
27173f1f | 69 | struct eb_vmas *eb = NULL; |
eef90ccb CW |
70 | |
71 | if (args->flags & I915_EXEC_HANDLE_LUT) { | |
b205ca57 | 72 | unsigned size = args->buffer_count; |
27173f1f BW |
73 | size *= sizeof(struct i915_vma *); |
74 | size += sizeof(struct eb_vmas); | |
eef90ccb CW |
75 | eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); |
76 | } | |
77 | ||
78 | if (eb == NULL) { | |
b205ca57 DV |
79 | unsigned size = args->buffer_count; |
80 | unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2; | |
27b7c63a | 81 | BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head)); |
eef90ccb CW |
82 | while (count > 2*size) |
83 | count >>= 1; | |
84 | eb = kzalloc(count*sizeof(struct hlist_head) + | |
27173f1f | 85 | sizeof(struct eb_vmas), |
eef90ccb CW |
86 | GFP_TEMPORARY); |
87 | if (eb == NULL) | |
88 | return eb; | |
89 | ||
90 | eb->and = count - 1; | |
91 | } else | |
92 | eb->and = -args->buffer_count; | |
93 | ||
27173f1f | 94 | INIT_LIST_HEAD(&eb->vmas); |
67731b87 CW |
95 | return eb; |
96 | } | |
97 | ||
98 | static void | |
27173f1f | 99 | eb_reset(struct eb_vmas *eb) |
67731b87 | 100 | { |
eef90ccb CW |
101 | if (eb->and >= 0) |
102 | memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head)); | |
67731b87 CW |
103 | } |
104 | ||
59bfa124 CW |
105 | static struct i915_vma * |
106 | eb_get_batch(struct eb_vmas *eb) | |
107 | { | |
108 | struct i915_vma *vma = list_entry(eb->vmas.prev, typeof(*vma), exec_list); | |
109 | ||
110 | /* | |
111 | * SNA is doing fancy tricks with compressing batch buffers, which leads | |
112 | * to negative relocation deltas. Usually that works out ok since the | |
113 | * relocate address is still positive, except when the batch is placed | |
114 | * very low in the GTT. Ensure this doesn't happen. | |
115 | * | |
116 | * Note that actual hangs have only been observed on gen7, but for | |
117 | * paranoia do it everywhere. | |
118 | */ | |
119 | if ((vma->exec_entry->flags & EXEC_OBJECT_PINNED) == 0) | |
120 | vma->exec_entry->flags |= __EXEC_OBJECT_NEEDS_BIAS; | |
121 | ||
122 | return vma; | |
123 | } | |
124 | ||
3b96eff4 | 125 | static int |
27173f1f BW |
126 | eb_lookup_vmas(struct eb_vmas *eb, |
127 | struct drm_i915_gem_exec_object2 *exec, | |
128 | const struct drm_i915_gem_execbuffer2 *args, | |
129 | struct i915_address_space *vm, | |
130 | struct drm_file *file) | |
3b96eff4 | 131 | { |
27173f1f BW |
132 | struct drm_i915_gem_object *obj; |
133 | struct list_head objects; | |
9ae9ab52 | 134 | int i, ret; |
3b96eff4 | 135 | |
27173f1f | 136 | INIT_LIST_HEAD(&objects); |
3b96eff4 | 137 | spin_lock(&file->table_lock); |
27173f1f BW |
138 | /* Grab a reference to the object and release the lock so we can lookup |
139 | * or create the VMA without using GFP_ATOMIC */ | |
eef90ccb | 140 | for (i = 0; i < args->buffer_count; i++) { |
3b96eff4 CW |
141 | obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle)); |
142 | if (obj == NULL) { | |
143 | spin_unlock(&file->table_lock); | |
144 | DRM_DEBUG("Invalid object handle %d at index %d\n", | |
145 | exec[i].handle, i); | |
27173f1f | 146 | ret = -ENOENT; |
9ae9ab52 | 147 | goto err; |
3b96eff4 CW |
148 | } |
149 | ||
27173f1f | 150 | if (!list_empty(&obj->obj_exec_link)) { |
3b96eff4 CW |
151 | spin_unlock(&file->table_lock); |
152 | DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n", | |
153 | obj, exec[i].handle, i); | |
27173f1f | 154 | ret = -EINVAL; |
9ae9ab52 | 155 | goto err; |
3b96eff4 CW |
156 | } |
157 | ||
25dc556a | 158 | i915_gem_object_get(obj); |
27173f1f BW |
159 | list_add_tail(&obj->obj_exec_link, &objects); |
160 | } | |
161 | spin_unlock(&file->table_lock); | |
3b96eff4 | 162 | |
27173f1f | 163 | i = 0; |
9ae9ab52 | 164 | while (!list_empty(&objects)) { |
27173f1f | 165 | struct i915_vma *vma; |
6f65e29a | 166 | |
9ae9ab52 CW |
167 | obj = list_first_entry(&objects, |
168 | struct drm_i915_gem_object, | |
169 | obj_exec_link); | |
170 | ||
e656a6cb DV |
171 | /* |
172 | * NOTE: We can leak any vmas created here when something fails | |
173 | * later on. But that's no issue since vma_unbind can deal with | |
174 | * vmas which are not actually bound. And since only | |
175 | * lookup_or_create exists as an interface to get at the vma | |
176 | * from the (obj, vm) we don't run the risk of creating | |
177 | * duplicated vmas for the same vm. | |
178 | */ | |
da51a1e7 | 179 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm); |
27173f1f | 180 | if (IS_ERR(vma)) { |
27173f1f BW |
181 | DRM_DEBUG("Failed to lookup VMA\n"); |
182 | ret = PTR_ERR(vma); | |
9ae9ab52 | 183 | goto err; |
27173f1f BW |
184 | } |
185 | ||
9ae9ab52 | 186 | /* Transfer ownership from the objects list to the vmas list. */ |
27173f1f | 187 | list_add_tail(&vma->exec_list, &eb->vmas); |
9ae9ab52 | 188 | list_del_init(&obj->obj_exec_link); |
27173f1f BW |
189 | |
190 | vma->exec_entry = &exec[i]; | |
eef90ccb | 191 | if (eb->and < 0) { |
27173f1f | 192 | eb->lut[i] = vma; |
eef90ccb CW |
193 | } else { |
194 | uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle; | |
27173f1f BW |
195 | vma->exec_handle = handle; |
196 | hlist_add_head(&vma->exec_node, | |
eef90ccb CW |
197 | &eb->buckets[handle & eb->and]); |
198 | } | |
27173f1f | 199 | ++i; |
3b96eff4 | 200 | } |
3b96eff4 | 201 | |
9ae9ab52 | 202 | return 0; |
27173f1f | 203 | |
27173f1f | 204 | |
9ae9ab52 | 205 | err: |
27173f1f BW |
206 | while (!list_empty(&objects)) { |
207 | obj = list_first_entry(&objects, | |
208 | struct drm_i915_gem_object, | |
209 | obj_exec_link); | |
210 | list_del_init(&obj->obj_exec_link); | |
f8c417cd | 211 | i915_gem_object_put(obj); |
27173f1f | 212 | } |
9ae9ab52 CW |
213 | /* |
214 | * Objects already transfered to the vmas list will be unreferenced by | |
215 | * eb_destroy. | |
216 | */ | |
217 | ||
27173f1f | 218 | return ret; |
3b96eff4 CW |
219 | } |
220 | ||
27173f1f | 221 | static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle) |
67731b87 | 222 | { |
eef90ccb CW |
223 | if (eb->and < 0) { |
224 | if (handle >= -eb->and) | |
225 | return NULL; | |
226 | return eb->lut[handle]; | |
227 | } else { | |
228 | struct hlist_head *head; | |
aa45950b | 229 | struct i915_vma *vma; |
67731b87 | 230 | |
eef90ccb | 231 | head = &eb->buckets[handle & eb->and]; |
aa45950b | 232 | hlist_for_each_entry(vma, head, exec_node) { |
27173f1f BW |
233 | if (vma->exec_handle == handle) |
234 | return vma; | |
eef90ccb CW |
235 | } |
236 | return NULL; | |
237 | } | |
67731b87 CW |
238 | } |
239 | ||
a415d355 CW |
240 | static void |
241 | i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma) | |
242 | { | |
243 | struct drm_i915_gem_exec_object2 *entry; | |
244 | struct drm_i915_gem_object *obj = vma->obj; | |
245 | ||
246 | if (!drm_mm_node_allocated(&vma->node)) | |
247 | return; | |
248 | ||
249 | entry = vma->exec_entry; | |
250 | ||
251 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) | |
252 | i915_gem_object_unpin_fence(obj); | |
253 | ||
254 | if (entry->flags & __EXEC_OBJECT_HAS_PIN) | |
20dfbde4 | 255 | __i915_vma_unpin(vma); |
a415d355 | 256 | |
de4e783a | 257 | entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN); |
a415d355 CW |
258 | } |
259 | ||
260 | static void eb_destroy(struct eb_vmas *eb) | |
261 | { | |
27173f1f BW |
262 | while (!list_empty(&eb->vmas)) { |
263 | struct i915_vma *vma; | |
bcffc3fa | 264 | |
27173f1f BW |
265 | vma = list_first_entry(&eb->vmas, |
266 | struct i915_vma, | |
bcffc3fa | 267 | exec_list); |
27173f1f | 268 | list_del_init(&vma->exec_list); |
a415d355 | 269 | i915_gem_execbuffer_unreserve_vma(vma); |
f8c417cd | 270 | i915_gem_object_put(vma->obj); |
bcffc3fa | 271 | } |
67731b87 CW |
272 | kfree(eb); |
273 | } | |
274 | ||
dabdfe02 CW |
275 | static inline int use_cpu_reloc(struct drm_i915_gem_object *obj) |
276 | { | |
2cc86b82 CW |
277 | return (HAS_LLC(obj->base.dev) || |
278 | obj->base.write_domain == I915_GEM_DOMAIN_CPU || | |
dabdfe02 CW |
279 | obj->cache_level != I915_CACHE_NONE); |
280 | } | |
281 | ||
934acce3 MW |
282 | /* Used to convert any address to canonical form. |
283 | * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS, | |
284 | * MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the | |
285 | * addresses to be in a canonical form: | |
286 | * "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct | |
287 | * canonical form [63:48] == [47]." | |
288 | */ | |
289 | #define GEN8_HIGH_ADDRESS_BIT 47 | |
290 | static inline uint64_t gen8_canonical_addr(uint64_t address) | |
291 | { | |
292 | return sign_extend64(address, GEN8_HIGH_ADDRESS_BIT); | |
293 | } | |
294 | ||
295 | static inline uint64_t gen8_noncanonical_addr(uint64_t address) | |
296 | { | |
297 | return address & ((1ULL << (GEN8_HIGH_ADDRESS_BIT + 1)) - 1); | |
298 | } | |
299 | ||
300 | static inline uint64_t | |
301 | relocation_target(struct drm_i915_gem_relocation_entry *reloc, | |
302 | uint64_t target_offset) | |
303 | { | |
304 | return gen8_canonical_addr((int)reloc->delta + target_offset); | |
305 | } | |
306 | ||
5032d871 RB |
307 | static int |
308 | relocate_entry_cpu(struct drm_i915_gem_object *obj, | |
d9ceb957 BW |
309 | struct drm_i915_gem_relocation_entry *reloc, |
310 | uint64_t target_offset) | |
5032d871 | 311 | { |
3c94ceee | 312 | struct drm_device *dev = obj->base.dev; |
5032d871 | 313 | uint32_t page_offset = offset_in_page(reloc->offset); |
934acce3 | 314 | uint64_t delta = relocation_target(reloc, target_offset); |
5032d871 | 315 | char *vaddr; |
8b78f0e5 | 316 | int ret; |
5032d871 | 317 | |
2cc86b82 | 318 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
5032d871 RB |
319 | if (ret) |
320 | return ret; | |
321 | ||
033908ae | 322 | vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, |
5032d871 | 323 | reloc->offset >> PAGE_SHIFT)); |
d9ceb957 | 324 | *(uint32_t *)(vaddr + page_offset) = lower_32_bits(delta); |
3c94ceee BW |
325 | |
326 | if (INTEL_INFO(dev)->gen >= 8) { | |
327 | page_offset = offset_in_page(page_offset + sizeof(uint32_t)); | |
328 | ||
329 | if (page_offset == 0) { | |
330 | kunmap_atomic(vaddr); | |
033908ae | 331 | vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, |
3c94ceee BW |
332 | (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT)); |
333 | } | |
334 | ||
d9ceb957 | 335 | *(uint32_t *)(vaddr + page_offset) = upper_32_bits(delta); |
3c94ceee BW |
336 | } |
337 | ||
5032d871 RB |
338 | kunmap_atomic(vaddr); |
339 | ||
340 | return 0; | |
341 | } | |
342 | ||
343 | static int | |
344 | relocate_entry_gtt(struct drm_i915_gem_object *obj, | |
d9ceb957 BW |
345 | struct drm_i915_gem_relocation_entry *reloc, |
346 | uint64_t target_offset) | |
5032d871 RB |
347 | { |
348 | struct drm_device *dev = obj->base.dev; | |
72e96d64 JL |
349 | struct drm_i915_private *dev_priv = to_i915(dev); |
350 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
934acce3 | 351 | uint64_t delta = relocation_target(reloc, target_offset); |
906843c3 | 352 | uint64_t offset; |
5032d871 | 353 | void __iomem *reloc_page; |
8b78f0e5 | 354 | int ret; |
5032d871 RB |
355 | |
356 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
357 | if (ret) | |
358 | return ret; | |
359 | ||
360 | ret = i915_gem_object_put_fence(obj); | |
361 | if (ret) | |
362 | return ret; | |
363 | ||
364 | /* Map the page containing the relocation we're going to perform. */ | |
906843c3 CW |
365 | offset = i915_gem_obj_ggtt_offset(obj); |
366 | offset += reloc->offset; | |
72e96d64 | 367 | reloc_page = io_mapping_map_atomic_wc(ggtt->mappable, |
906843c3 CW |
368 | offset & PAGE_MASK); |
369 | iowrite32(lower_32_bits(delta), reloc_page + offset_in_page(offset)); | |
3c94ceee BW |
370 | |
371 | if (INTEL_INFO(dev)->gen >= 8) { | |
906843c3 | 372 | offset += sizeof(uint32_t); |
3c94ceee | 373 | |
906843c3 | 374 | if (offset_in_page(offset) == 0) { |
3c94ceee | 375 | io_mapping_unmap_atomic(reloc_page); |
906843c3 | 376 | reloc_page = |
72e96d64 | 377 | io_mapping_map_atomic_wc(ggtt->mappable, |
906843c3 | 378 | offset); |
3c94ceee BW |
379 | } |
380 | ||
906843c3 CW |
381 | iowrite32(upper_32_bits(delta), |
382 | reloc_page + offset_in_page(offset)); | |
3c94ceee BW |
383 | } |
384 | ||
5032d871 RB |
385 | io_mapping_unmap_atomic(reloc_page); |
386 | ||
387 | return 0; | |
388 | } | |
389 | ||
edf4427b CW |
390 | static void |
391 | clflush_write32(void *addr, uint32_t value) | |
392 | { | |
393 | /* This is not a fast path, so KISS. */ | |
394 | drm_clflush_virt_range(addr, sizeof(uint32_t)); | |
395 | *(uint32_t *)addr = value; | |
396 | drm_clflush_virt_range(addr, sizeof(uint32_t)); | |
397 | } | |
398 | ||
399 | static int | |
400 | relocate_entry_clflush(struct drm_i915_gem_object *obj, | |
401 | struct drm_i915_gem_relocation_entry *reloc, | |
402 | uint64_t target_offset) | |
403 | { | |
404 | struct drm_device *dev = obj->base.dev; | |
405 | uint32_t page_offset = offset_in_page(reloc->offset); | |
934acce3 | 406 | uint64_t delta = relocation_target(reloc, target_offset); |
edf4427b CW |
407 | char *vaddr; |
408 | int ret; | |
409 | ||
410 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
411 | if (ret) | |
412 | return ret; | |
413 | ||
033908ae | 414 | vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, |
edf4427b CW |
415 | reloc->offset >> PAGE_SHIFT)); |
416 | clflush_write32(vaddr + page_offset, lower_32_bits(delta)); | |
417 | ||
418 | if (INTEL_INFO(dev)->gen >= 8) { | |
419 | page_offset = offset_in_page(page_offset + sizeof(uint32_t)); | |
420 | ||
421 | if (page_offset == 0) { | |
422 | kunmap_atomic(vaddr); | |
033908ae | 423 | vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, |
edf4427b CW |
424 | (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT)); |
425 | } | |
426 | ||
427 | clflush_write32(vaddr + page_offset, upper_32_bits(delta)); | |
428 | } | |
429 | ||
430 | kunmap_atomic(vaddr); | |
431 | ||
432 | return 0; | |
433 | } | |
434 | ||
909d074c CW |
435 | static bool object_is_idle(struct drm_i915_gem_object *obj) |
436 | { | |
573adb39 | 437 | unsigned long active = i915_gem_object_get_active(obj); |
909d074c CW |
438 | int idx; |
439 | ||
440 | for_each_active(active, idx) { | |
441 | if (!i915_gem_active_is_idle(&obj->last_read[idx], | |
442 | &obj->base.dev->struct_mutex)) | |
443 | return false; | |
444 | } | |
445 | ||
446 | return true; | |
447 | } | |
448 | ||
54cf91dc CW |
449 | static int |
450 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, | |
27173f1f | 451 | struct eb_vmas *eb, |
3e7a0322 | 452 | struct drm_i915_gem_relocation_entry *reloc) |
54cf91dc CW |
453 | { |
454 | struct drm_device *dev = obj->base.dev; | |
455 | struct drm_gem_object *target_obj; | |
149c8407 | 456 | struct drm_i915_gem_object *target_i915_obj; |
27173f1f | 457 | struct i915_vma *target_vma; |
d9ceb957 | 458 | uint64_t target_offset; |
8b78f0e5 | 459 | int ret; |
54cf91dc | 460 | |
67731b87 | 461 | /* we've already hold a reference to all valid objects */ |
27173f1f BW |
462 | target_vma = eb_get_vma(eb, reloc->target_handle); |
463 | if (unlikely(target_vma == NULL)) | |
54cf91dc | 464 | return -ENOENT; |
27173f1f BW |
465 | target_i915_obj = target_vma->obj; |
466 | target_obj = &target_vma->obj->base; | |
54cf91dc | 467 | |
934acce3 | 468 | target_offset = gen8_canonical_addr(target_vma->node.start); |
54cf91dc | 469 | |
e844b990 EA |
470 | /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and |
471 | * pipe_control writes because the gpu doesn't properly redirect them | |
472 | * through the ppgtt for non_secure batchbuffers. */ | |
473 | if (unlikely(IS_GEN6(dev) && | |
0875546c | 474 | reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) { |
fe14d5f4 | 475 | ret = i915_vma_bind(target_vma, target_i915_obj->cache_level, |
0875546c | 476 | PIN_GLOBAL); |
fe14d5f4 TU |
477 | if (WARN_ONCE(ret, "Unexpected failure to bind target VMA!")) |
478 | return ret; | |
479 | } | |
e844b990 | 480 | |
54cf91dc | 481 | /* Validate that the target is in a valid r/w GPU domain */ |
b8f7ab17 | 482 | if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { |
ff240199 | 483 | DRM_DEBUG("reloc with multiple write domains: " |
54cf91dc CW |
484 | "obj %p target %d offset %d " |
485 | "read %08x write %08x", | |
486 | obj, reloc->target_handle, | |
487 | (int) reloc->offset, | |
488 | reloc->read_domains, | |
489 | reloc->write_domain); | |
8b78f0e5 | 490 | return -EINVAL; |
54cf91dc | 491 | } |
4ca4a250 DV |
492 | if (unlikely((reloc->write_domain | reloc->read_domains) |
493 | & ~I915_GEM_GPU_DOMAINS)) { | |
ff240199 | 494 | DRM_DEBUG("reloc with read/write non-GPU domains: " |
54cf91dc CW |
495 | "obj %p target %d offset %d " |
496 | "read %08x write %08x", | |
497 | obj, reloc->target_handle, | |
498 | (int) reloc->offset, | |
499 | reloc->read_domains, | |
500 | reloc->write_domain); | |
8b78f0e5 | 501 | return -EINVAL; |
54cf91dc | 502 | } |
54cf91dc CW |
503 | |
504 | target_obj->pending_read_domains |= reloc->read_domains; | |
505 | target_obj->pending_write_domain |= reloc->write_domain; | |
506 | ||
507 | /* If the relocation already has the right value in it, no | |
508 | * more work needs to be done. | |
509 | */ | |
510 | if (target_offset == reloc->presumed_offset) | |
67731b87 | 511 | return 0; |
54cf91dc CW |
512 | |
513 | /* Check that the relocation address is valid... */ | |
3c94ceee BW |
514 | if (unlikely(reloc->offset > |
515 | obj->base.size - (INTEL_INFO(dev)->gen >= 8 ? 8 : 4))) { | |
ff240199 | 516 | DRM_DEBUG("Relocation beyond object bounds: " |
54cf91dc CW |
517 | "obj %p target %d offset %d size %d.\n", |
518 | obj, reloc->target_handle, | |
519 | (int) reloc->offset, | |
520 | (int) obj->base.size); | |
8b78f0e5 | 521 | return -EINVAL; |
54cf91dc | 522 | } |
b8f7ab17 | 523 | if (unlikely(reloc->offset & 3)) { |
ff240199 | 524 | DRM_DEBUG("Relocation not 4-byte aligned: " |
54cf91dc CW |
525 | "obj %p target %d offset %d.\n", |
526 | obj, reloc->target_handle, | |
527 | (int) reloc->offset); | |
8b78f0e5 | 528 | return -EINVAL; |
54cf91dc CW |
529 | } |
530 | ||
dabdfe02 | 531 | /* We can't wait for rendering with pagefaults disabled */ |
909d074c | 532 | if (pagefault_disabled() && !object_is_idle(obj)) |
dabdfe02 CW |
533 | return -EFAULT; |
534 | ||
5032d871 | 535 | if (use_cpu_reloc(obj)) |
d9ceb957 | 536 | ret = relocate_entry_cpu(obj, reloc, target_offset); |
edf4427b | 537 | else if (obj->map_and_fenceable) |
d9ceb957 | 538 | ret = relocate_entry_gtt(obj, reloc, target_offset); |
906bf7fd | 539 | else if (static_cpu_has(X86_FEATURE_CLFLUSH)) |
edf4427b CW |
540 | ret = relocate_entry_clflush(obj, reloc, target_offset); |
541 | else { | |
542 | WARN_ONCE(1, "Impossible case in relocation handling\n"); | |
543 | ret = -ENODEV; | |
544 | } | |
54cf91dc | 545 | |
d4d36014 DV |
546 | if (ret) |
547 | return ret; | |
548 | ||
54cf91dc CW |
549 | /* and update the user's relocation entry */ |
550 | reloc->presumed_offset = target_offset; | |
551 | ||
67731b87 | 552 | return 0; |
54cf91dc CW |
553 | } |
554 | ||
555 | static int | |
27173f1f BW |
556 | i915_gem_execbuffer_relocate_vma(struct i915_vma *vma, |
557 | struct eb_vmas *eb) | |
54cf91dc | 558 | { |
1d83f442 CW |
559 | #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) |
560 | struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)]; | |
54cf91dc | 561 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
27173f1f | 562 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
1d83f442 | 563 | int remain, ret; |
54cf91dc | 564 | |
3ed605bc | 565 | user_relocs = u64_to_user_ptr(entry->relocs_ptr); |
54cf91dc | 566 | |
1d83f442 CW |
567 | remain = entry->relocation_count; |
568 | while (remain) { | |
569 | struct drm_i915_gem_relocation_entry *r = stack_reloc; | |
570 | int count = remain; | |
571 | if (count > ARRAY_SIZE(stack_reloc)) | |
572 | count = ARRAY_SIZE(stack_reloc); | |
573 | remain -= count; | |
574 | ||
575 | if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0]))) | |
54cf91dc CW |
576 | return -EFAULT; |
577 | ||
1d83f442 CW |
578 | do { |
579 | u64 offset = r->presumed_offset; | |
54cf91dc | 580 | |
3e7a0322 | 581 | ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r); |
1d83f442 CW |
582 | if (ret) |
583 | return ret; | |
584 | ||
585 | if (r->presumed_offset != offset && | |
5b09c3ed | 586 | __put_user(r->presumed_offset, &user_relocs->presumed_offset)) { |
1d83f442 CW |
587 | return -EFAULT; |
588 | } | |
589 | ||
590 | user_relocs++; | |
591 | r++; | |
592 | } while (--count); | |
54cf91dc CW |
593 | } |
594 | ||
595 | return 0; | |
1d83f442 | 596 | #undef N_RELOC |
54cf91dc CW |
597 | } |
598 | ||
599 | static int | |
27173f1f BW |
600 | i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma, |
601 | struct eb_vmas *eb, | |
602 | struct drm_i915_gem_relocation_entry *relocs) | |
54cf91dc | 603 | { |
27173f1f | 604 | const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
54cf91dc CW |
605 | int i, ret; |
606 | ||
607 | for (i = 0; i < entry->relocation_count; i++) { | |
3e7a0322 | 608 | ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i]); |
54cf91dc CW |
609 | if (ret) |
610 | return ret; | |
611 | } | |
612 | ||
613 | return 0; | |
614 | } | |
615 | ||
616 | static int | |
17601cbc | 617 | i915_gem_execbuffer_relocate(struct eb_vmas *eb) |
54cf91dc | 618 | { |
27173f1f | 619 | struct i915_vma *vma; |
d4aeee77 CW |
620 | int ret = 0; |
621 | ||
622 | /* This is the fast path and we cannot handle a pagefault whilst | |
623 | * holding the struct mutex lest the user pass in the relocations | |
624 | * contained within a mmaped bo. For in such a case we, the page | |
625 | * fault handler would call i915_gem_fault() and we would try to | |
626 | * acquire the struct mutex again. Obviously this is bad and so | |
627 | * lockdep complains vehemently. | |
628 | */ | |
629 | pagefault_disable(); | |
27173f1f BW |
630 | list_for_each_entry(vma, &eb->vmas, exec_list) { |
631 | ret = i915_gem_execbuffer_relocate_vma(vma, eb); | |
54cf91dc | 632 | if (ret) |
d4aeee77 | 633 | break; |
54cf91dc | 634 | } |
d4aeee77 | 635 | pagefault_enable(); |
54cf91dc | 636 | |
d4aeee77 | 637 | return ret; |
54cf91dc CW |
638 | } |
639 | ||
edf4427b CW |
640 | static bool only_mappable_for_reloc(unsigned int flags) |
641 | { | |
642 | return (flags & (EXEC_OBJECT_NEEDS_FENCE | __EXEC_OBJECT_NEEDS_MAP)) == | |
643 | __EXEC_OBJECT_NEEDS_MAP; | |
644 | } | |
645 | ||
1690e1eb | 646 | static int |
27173f1f | 647 | i915_gem_execbuffer_reserve_vma(struct i915_vma *vma, |
0bc40be8 | 648 | struct intel_engine_cs *engine, |
27173f1f | 649 | bool *need_reloc) |
1690e1eb | 650 | { |
6f65e29a | 651 | struct drm_i915_gem_object *obj = vma->obj; |
27173f1f | 652 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
d23db88c | 653 | uint64_t flags; |
1690e1eb CW |
654 | int ret; |
655 | ||
0875546c | 656 | flags = PIN_USER; |
0229da32 DV |
657 | if (entry->flags & EXEC_OBJECT_NEEDS_GTT) |
658 | flags |= PIN_GLOBAL; | |
659 | ||
edf4427b | 660 | if (!drm_mm_node_allocated(&vma->node)) { |
101b506a MT |
661 | /* Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset, |
662 | * limit address to the first 4GBs for unflagged objects. | |
663 | */ | |
664 | if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0) | |
665 | flags |= PIN_ZONE_4G; | |
edf4427b CW |
666 | if (entry->flags & __EXEC_OBJECT_NEEDS_MAP) |
667 | flags |= PIN_GLOBAL | PIN_MAPPABLE; | |
edf4427b CW |
668 | if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS) |
669 | flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS; | |
506a8e87 CW |
670 | if (entry->flags & EXEC_OBJECT_PINNED) |
671 | flags |= entry->offset | PIN_OFFSET_FIXED; | |
101b506a MT |
672 | if ((flags & PIN_MAPPABLE) == 0) |
673 | flags |= PIN_HIGH; | |
edf4427b | 674 | } |
1ec9e26d | 675 | |
59bfa124 CW |
676 | ret = i915_vma_pin(vma, |
677 | entry->pad_to_size, | |
678 | entry->alignment, | |
679 | flags); | |
680 | if ((ret == -ENOSPC || ret == -E2BIG) && | |
edf4427b | 681 | only_mappable_for_reloc(entry->flags)) |
59bfa124 CW |
682 | ret = i915_vma_pin(vma, |
683 | entry->pad_to_size, | |
684 | entry->alignment, | |
685 | flags & ~PIN_MAPPABLE); | |
1690e1eb CW |
686 | if (ret) |
687 | return ret; | |
688 | ||
7788a765 CW |
689 | entry->flags |= __EXEC_OBJECT_HAS_PIN; |
690 | ||
82b6b6d7 CW |
691 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { |
692 | ret = i915_gem_object_get_fence(obj); | |
693 | if (ret) | |
694 | return ret; | |
9a5a53b3 | 695 | |
82b6b6d7 CW |
696 | if (i915_gem_object_pin_fence(obj)) |
697 | entry->flags |= __EXEC_OBJECT_HAS_FENCE; | |
1690e1eb CW |
698 | } |
699 | ||
27173f1f BW |
700 | if (entry->offset != vma->node.start) { |
701 | entry->offset = vma->node.start; | |
ed5982e6 DV |
702 | *need_reloc = true; |
703 | } | |
704 | ||
705 | if (entry->flags & EXEC_OBJECT_WRITE) { | |
706 | obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER; | |
707 | obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER; | |
708 | } | |
709 | ||
1690e1eb | 710 | return 0; |
7788a765 | 711 | } |
1690e1eb | 712 | |
d23db88c | 713 | static bool |
e6a84468 | 714 | need_reloc_mappable(struct i915_vma *vma) |
d23db88c CW |
715 | { |
716 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; | |
d23db88c | 717 | |
e6a84468 CW |
718 | if (entry->relocation_count == 0) |
719 | return false; | |
720 | ||
3272db53 | 721 | if (!i915_vma_is_ggtt(vma)) |
e6a84468 CW |
722 | return false; |
723 | ||
724 | /* See also use_cpu_reloc() */ | |
725 | if (HAS_LLC(vma->obj->base.dev)) | |
726 | return false; | |
727 | ||
728 | if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU) | |
729 | return false; | |
730 | ||
731 | return true; | |
732 | } | |
733 | ||
734 | static bool | |
735 | eb_vma_misplaced(struct i915_vma *vma) | |
736 | { | |
737 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; | |
738 | struct drm_i915_gem_object *obj = vma->obj; | |
d23db88c | 739 | |
3272db53 CW |
740 | WARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP && |
741 | !i915_vma_is_ggtt(vma)); | |
d23db88c CW |
742 | |
743 | if (entry->alignment && | |
744 | vma->node.start & (entry->alignment - 1)) | |
745 | return true; | |
746 | ||
91b2db6f CW |
747 | if (vma->node.size < entry->pad_to_size) |
748 | return true; | |
749 | ||
506a8e87 CW |
750 | if (entry->flags & EXEC_OBJECT_PINNED && |
751 | vma->node.start != entry->offset) | |
752 | return true; | |
753 | ||
d23db88c CW |
754 | if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS && |
755 | vma->node.start < BATCH_OFFSET_BIAS) | |
756 | return true; | |
757 | ||
edf4427b CW |
758 | /* avoid costly ping-pong once a batch bo ended up non-mappable */ |
759 | if (entry->flags & __EXEC_OBJECT_NEEDS_MAP && !obj->map_and_fenceable) | |
760 | return !only_mappable_for_reloc(entry->flags); | |
761 | ||
101b506a MT |
762 | if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0 && |
763 | (vma->node.start + vma->node.size - 1) >> 32) | |
764 | return true; | |
765 | ||
d23db88c CW |
766 | return false; |
767 | } | |
768 | ||
54cf91dc | 769 | static int |
0bc40be8 | 770 | i915_gem_execbuffer_reserve(struct intel_engine_cs *engine, |
27173f1f | 771 | struct list_head *vmas, |
e2efd130 | 772 | struct i915_gem_context *ctx, |
ed5982e6 | 773 | bool *need_relocs) |
54cf91dc | 774 | { |
432e58ed | 775 | struct drm_i915_gem_object *obj; |
27173f1f | 776 | struct i915_vma *vma; |
68c8c17f | 777 | struct i915_address_space *vm; |
27173f1f | 778 | struct list_head ordered_vmas; |
506a8e87 | 779 | struct list_head pinned_vmas; |
c033666a | 780 | bool has_fenced_gpu_access = INTEL_GEN(engine->i915) < 4; |
7788a765 | 781 | int retry; |
6fe4f140 | 782 | |
68c8c17f BW |
783 | vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm; |
784 | ||
27173f1f | 785 | INIT_LIST_HEAD(&ordered_vmas); |
506a8e87 | 786 | INIT_LIST_HEAD(&pinned_vmas); |
27173f1f | 787 | while (!list_empty(vmas)) { |
6fe4f140 CW |
788 | struct drm_i915_gem_exec_object2 *entry; |
789 | bool need_fence, need_mappable; | |
790 | ||
27173f1f BW |
791 | vma = list_first_entry(vmas, struct i915_vma, exec_list); |
792 | obj = vma->obj; | |
793 | entry = vma->exec_entry; | |
6fe4f140 | 794 | |
b1b38278 DW |
795 | if (ctx->flags & CONTEXT_NO_ZEROMAP) |
796 | entry->flags |= __EXEC_OBJECT_NEEDS_BIAS; | |
797 | ||
82b6b6d7 CW |
798 | if (!has_fenced_gpu_access) |
799 | entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE; | |
6fe4f140 | 800 | need_fence = |
6fe4f140 CW |
801 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
802 | obj->tiling_mode != I915_TILING_NONE; | |
27173f1f | 803 | need_mappable = need_fence || need_reloc_mappable(vma); |
6fe4f140 | 804 | |
506a8e87 CW |
805 | if (entry->flags & EXEC_OBJECT_PINNED) |
806 | list_move_tail(&vma->exec_list, &pinned_vmas); | |
807 | else if (need_mappable) { | |
e6a84468 | 808 | entry->flags |= __EXEC_OBJECT_NEEDS_MAP; |
27173f1f | 809 | list_move(&vma->exec_list, &ordered_vmas); |
e6a84468 | 810 | } else |
27173f1f | 811 | list_move_tail(&vma->exec_list, &ordered_vmas); |
595dad76 | 812 | |
ed5982e6 | 813 | obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND; |
595dad76 | 814 | obj->base.pending_write_domain = 0; |
6fe4f140 | 815 | } |
27173f1f | 816 | list_splice(&ordered_vmas, vmas); |
506a8e87 | 817 | list_splice(&pinned_vmas, vmas); |
54cf91dc CW |
818 | |
819 | /* Attempt to pin all of the buffers into the GTT. | |
820 | * This is done in 3 phases: | |
821 | * | |
822 | * 1a. Unbind all objects that do not match the GTT constraints for | |
823 | * the execbuffer (fenceable, mappable, alignment etc). | |
824 | * 1b. Increment pin count for already bound objects. | |
825 | * 2. Bind new objects. | |
826 | * 3. Decrement pin count. | |
827 | * | |
7788a765 | 828 | * This avoid unnecessary unbinding of later objects in order to make |
54cf91dc CW |
829 | * room for the earlier objects *unless* we need to defragment. |
830 | */ | |
831 | retry = 0; | |
832 | do { | |
7788a765 | 833 | int ret = 0; |
54cf91dc CW |
834 | |
835 | /* Unbind any ill-fitting objects or pin. */ | |
27173f1f | 836 | list_for_each_entry(vma, vmas, exec_list) { |
27173f1f | 837 | if (!drm_mm_node_allocated(&vma->node)) |
54cf91dc CW |
838 | continue; |
839 | ||
e6a84468 | 840 | if (eb_vma_misplaced(vma)) |
27173f1f | 841 | ret = i915_vma_unbind(vma); |
54cf91dc | 842 | else |
0bc40be8 TU |
843 | ret = i915_gem_execbuffer_reserve_vma(vma, |
844 | engine, | |
845 | need_relocs); | |
432e58ed | 846 | if (ret) |
54cf91dc | 847 | goto err; |
54cf91dc CW |
848 | } |
849 | ||
850 | /* Bind fresh objects */ | |
27173f1f BW |
851 | list_for_each_entry(vma, vmas, exec_list) { |
852 | if (drm_mm_node_allocated(&vma->node)) | |
1690e1eb | 853 | continue; |
54cf91dc | 854 | |
0bc40be8 TU |
855 | ret = i915_gem_execbuffer_reserve_vma(vma, engine, |
856 | need_relocs); | |
7788a765 CW |
857 | if (ret) |
858 | goto err; | |
54cf91dc CW |
859 | } |
860 | ||
a415d355 | 861 | err: |
6c085a72 | 862 | if (ret != -ENOSPC || retry++) |
54cf91dc CW |
863 | return ret; |
864 | ||
a415d355 CW |
865 | /* Decrement pin count for bound objects */ |
866 | list_for_each_entry(vma, vmas, exec_list) | |
867 | i915_gem_execbuffer_unreserve_vma(vma); | |
868 | ||
68c8c17f | 869 | ret = i915_gem_evict_vm(vm, true); |
54cf91dc CW |
870 | if (ret) |
871 | return ret; | |
54cf91dc CW |
872 | } while (1); |
873 | } | |
874 | ||
875 | static int | |
876 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, | |
ed5982e6 | 877 | struct drm_i915_gem_execbuffer2 *args, |
54cf91dc | 878 | struct drm_file *file, |
0bc40be8 | 879 | struct intel_engine_cs *engine, |
27173f1f | 880 | struct eb_vmas *eb, |
b1b38278 | 881 | struct drm_i915_gem_exec_object2 *exec, |
e2efd130 | 882 | struct i915_gem_context *ctx) |
54cf91dc CW |
883 | { |
884 | struct drm_i915_gem_relocation_entry *reloc; | |
27173f1f BW |
885 | struct i915_address_space *vm; |
886 | struct i915_vma *vma; | |
ed5982e6 | 887 | bool need_relocs; |
dd6864a4 | 888 | int *reloc_offset; |
54cf91dc | 889 | int i, total, ret; |
b205ca57 | 890 | unsigned count = args->buffer_count; |
54cf91dc | 891 | |
27173f1f BW |
892 | vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm; |
893 | ||
67731b87 | 894 | /* We may process another execbuffer during the unlock... */ |
27173f1f BW |
895 | while (!list_empty(&eb->vmas)) { |
896 | vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list); | |
897 | list_del_init(&vma->exec_list); | |
a415d355 | 898 | i915_gem_execbuffer_unreserve_vma(vma); |
f8c417cd | 899 | i915_gem_object_put(vma->obj); |
67731b87 CW |
900 | } |
901 | ||
54cf91dc CW |
902 | mutex_unlock(&dev->struct_mutex); |
903 | ||
904 | total = 0; | |
905 | for (i = 0; i < count; i++) | |
432e58ed | 906 | total += exec[i].relocation_count; |
54cf91dc | 907 | |
dd6864a4 | 908 | reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset)); |
54cf91dc | 909 | reloc = drm_malloc_ab(total, sizeof(*reloc)); |
dd6864a4 CW |
910 | if (reloc == NULL || reloc_offset == NULL) { |
911 | drm_free_large(reloc); | |
912 | drm_free_large(reloc_offset); | |
54cf91dc CW |
913 | mutex_lock(&dev->struct_mutex); |
914 | return -ENOMEM; | |
915 | } | |
916 | ||
917 | total = 0; | |
918 | for (i = 0; i < count; i++) { | |
919 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
262b6d36 CW |
920 | u64 invalid_offset = (u64)-1; |
921 | int j; | |
54cf91dc | 922 | |
3ed605bc | 923 | user_relocs = u64_to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
924 | |
925 | if (copy_from_user(reloc+total, user_relocs, | |
432e58ed | 926 | exec[i].relocation_count * sizeof(*reloc))) { |
54cf91dc CW |
927 | ret = -EFAULT; |
928 | mutex_lock(&dev->struct_mutex); | |
929 | goto err; | |
930 | } | |
931 | ||
262b6d36 CW |
932 | /* As we do not update the known relocation offsets after |
933 | * relocating (due to the complexities in lock handling), | |
934 | * we need to mark them as invalid now so that we force the | |
935 | * relocation processing next time. Just in case the target | |
936 | * object is evicted and then rebound into its old | |
937 | * presumed_offset before the next execbuffer - if that | |
938 | * happened we would make the mistake of assuming that the | |
939 | * relocations were valid. | |
940 | */ | |
941 | for (j = 0; j < exec[i].relocation_count; j++) { | |
9aab8bff CW |
942 | if (__copy_to_user(&user_relocs[j].presumed_offset, |
943 | &invalid_offset, | |
944 | sizeof(invalid_offset))) { | |
262b6d36 CW |
945 | ret = -EFAULT; |
946 | mutex_lock(&dev->struct_mutex); | |
947 | goto err; | |
948 | } | |
949 | } | |
950 | ||
dd6864a4 | 951 | reloc_offset[i] = total; |
432e58ed | 952 | total += exec[i].relocation_count; |
54cf91dc CW |
953 | } |
954 | ||
955 | ret = i915_mutex_lock_interruptible(dev); | |
956 | if (ret) { | |
957 | mutex_lock(&dev->struct_mutex); | |
958 | goto err; | |
959 | } | |
960 | ||
67731b87 | 961 | /* reacquire the objects */ |
67731b87 | 962 | eb_reset(eb); |
27173f1f | 963 | ret = eb_lookup_vmas(eb, exec, args, vm, file); |
3b96eff4 CW |
964 | if (ret) |
965 | goto err; | |
67731b87 | 966 | |
ed5982e6 | 967 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
0bc40be8 TU |
968 | ret = i915_gem_execbuffer_reserve(engine, &eb->vmas, ctx, |
969 | &need_relocs); | |
54cf91dc CW |
970 | if (ret) |
971 | goto err; | |
972 | ||
27173f1f BW |
973 | list_for_each_entry(vma, &eb->vmas, exec_list) { |
974 | int offset = vma->exec_entry - exec; | |
975 | ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb, | |
976 | reloc + reloc_offset[offset]); | |
54cf91dc CW |
977 | if (ret) |
978 | goto err; | |
54cf91dc CW |
979 | } |
980 | ||
981 | /* Leave the user relocations as are, this is the painfully slow path, | |
982 | * and we want to avoid the complication of dropping the lock whilst | |
983 | * having buffers reserved in the aperture and so causing spurious | |
984 | * ENOSPC for random operations. | |
985 | */ | |
986 | ||
987 | err: | |
988 | drm_free_large(reloc); | |
dd6864a4 | 989 | drm_free_large(reloc_offset); |
54cf91dc CW |
990 | return ret; |
991 | } | |
992 | ||
573adb39 CW |
993 | static unsigned int eb_other_engines(struct drm_i915_gem_request *req) |
994 | { | |
995 | unsigned int mask; | |
996 | ||
997 | mask = ~intel_engine_flag(req->engine) & I915_BO_ACTIVE_MASK; | |
998 | mask <<= I915_BO_ACTIVE_SHIFT; | |
999 | ||
1000 | return mask; | |
1001 | } | |
1002 | ||
54cf91dc | 1003 | static int |
535fbe82 | 1004 | i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req, |
27173f1f | 1005 | struct list_head *vmas) |
54cf91dc | 1006 | { |
573adb39 | 1007 | const unsigned int other_rings = eb_other_engines(req); |
27173f1f | 1008 | struct i915_vma *vma; |
6ac42f41 | 1009 | uint32_t flush_domains = 0; |
000433b6 | 1010 | bool flush_chipset = false; |
432e58ed | 1011 | int ret; |
54cf91dc | 1012 | |
27173f1f BW |
1013 | list_for_each_entry(vma, vmas, exec_list) { |
1014 | struct drm_i915_gem_object *obj = vma->obj; | |
03ade511 | 1015 | |
573adb39 | 1016 | if (obj->flags & other_rings) { |
8e637178 | 1017 | ret = i915_gem_object_sync(obj, req); |
03ade511 CW |
1018 | if (ret) |
1019 | return ret; | |
1020 | } | |
6ac42f41 DV |
1021 | |
1022 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) | |
000433b6 | 1023 | flush_chipset |= i915_gem_clflush_object(obj, false); |
6ac42f41 | 1024 | |
6ac42f41 | 1025 | flush_domains |= obj->base.write_domain; |
c59a333f CW |
1026 | } |
1027 | ||
000433b6 | 1028 | if (flush_chipset) |
c033666a | 1029 | i915_gem_chipset_flush(req->engine->i915); |
6ac42f41 DV |
1030 | |
1031 | if (flush_domains & I915_GEM_DOMAIN_GTT) | |
1032 | wmb(); | |
1033 | ||
c7fe7d25 | 1034 | /* Unconditionally invalidate GPU caches and TLBs. */ |
7c9cf4e3 | 1035 | return req->engine->emit_flush(req, EMIT_INVALIDATE); |
54cf91dc CW |
1036 | } |
1037 | ||
432e58ed CW |
1038 | static bool |
1039 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) | |
54cf91dc | 1040 | { |
ed5982e6 DV |
1041 | if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS) |
1042 | return false; | |
1043 | ||
2f5945bc CW |
1044 | /* Kernel clipping was a DRI1 misfeature */ |
1045 | if (exec->num_cliprects || exec->cliprects_ptr) | |
1046 | return false; | |
1047 | ||
1048 | if (exec->DR4 == 0xffffffff) { | |
1049 | DRM_DEBUG("UXA submitting garbage DR4, fixing up\n"); | |
1050 | exec->DR4 = 0; | |
1051 | } | |
1052 | if (exec->DR1 || exec->DR4) | |
1053 | return false; | |
1054 | ||
1055 | if ((exec->batch_start_offset | exec->batch_len) & 0x7) | |
1056 | return false; | |
1057 | ||
1058 | return true; | |
54cf91dc CW |
1059 | } |
1060 | ||
1061 | static int | |
ad19f10b CW |
1062 | validate_exec_list(struct drm_device *dev, |
1063 | struct drm_i915_gem_exec_object2 *exec, | |
54cf91dc CW |
1064 | int count) |
1065 | { | |
b205ca57 DV |
1066 | unsigned relocs_total = 0; |
1067 | unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry); | |
ad19f10b CW |
1068 | unsigned invalid_flags; |
1069 | int i; | |
1070 | ||
9e2793f6 DG |
1071 | /* INTERNAL flags must not overlap with external ones */ |
1072 | BUILD_BUG_ON(__EXEC_OBJECT_INTERNAL_FLAGS & ~__EXEC_OBJECT_UNKNOWN_FLAGS); | |
1073 | ||
ad19f10b CW |
1074 | invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS; |
1075 | if (USES_FULL_PPGTT(dev)) | |
1076 | invalid_flags |= EXEC_OBJECT_NEEDS_GTT; | |
54cf91dc CW |
1077 | |
1078 | for (i = 0; i < count; i++) { | |
3ed605bc | 1079 | char __user *ptr = u64_to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
1080 | int length; /* limited by fault_in_pages_readable() */ |
1081 | ||
ad19f10b | 1082 | if (exec[i].flags & invalid_flags) |
ed5982e6 DV |
1083 | return -EINVAL; |
1084 | ||
934acce3 MW |
1085 | /* Offset can be used as input (EXEC_OBJECT_PINNED), reject |
1086 | * any non-page-aligned or non-canonical addresses. | |
1087 | */ | |
1088 | if (exec[i].flags & EXEC_OBJECT_PINNED) { | |
1089 | if (exec[i].offset != | |
1090 | gen8_canonical_addr(exec[i].offset & PAGE_MASK)) | |
1091 | return -EINVAL; | |
1092 | ||
1093 | /* From drm_mm perspective address space is continuous, | |
1094 | * so from this point we're always using non-canonical | |
1095 | * form internally. | |
1096 | */ | |
1097 | exec[i].offset = gen8_noncanonical_addr(exec[i].offset); | |
1098 | } | |
1099 | ||
55a9785d CW |
1100 | if (exec[i].alignment && !is_power_of_2(exec[i].alignment)) |
1101 | return -EINVAL; | |
1102 | ||
91b2db6f CW |
1103 | /* pad_to_size was once a reserved field, so sanitize it */ |
1104 | if (exec[i].flags & EXEC_OBJECT_PAD_TO_SIZE) { | |
1105 | if (offset_in_page(exec[i].pad_to_size)) | |
1106 | return -EINVAL; | |
1107 | } else { | |
1108 | exec[i].pad_to_size = 0; | |
1109 | } | |
1110 | ||
3118a4f6 KC |
1111 | /* First check for malicious input causing overflow in |
1112 | * the worst case where we need to allocate the entire | |
1113 | * relocation tree as a single array. | |
1114 | */ | |
1115 | if (exec[i].relocation_count > relocs_max - relocs_total) | |
54cf91dc | 1116 | return -EINVAL; |
3118a4f6 | 1117 | relocs_total += exec[i].relocation_count; |
54cf91dc CW |
1118 | |
1119 | length = exec[i].relocation_count * | |
1120 | sizeof(struct drm_i915_gem_relocation_entry); | |
30587535 KC |
1121 | /* |
1122 | * We must check that the entire relocation array is safe | |
1123 | * to read, but since we may need to update the presumed | |
1124 | * offsets during execution, check for full write access. | |
1125 | */ | |
54cf91dc CW |
1126 | if (!access_ok(VERIFY_WRITE, ptr, length)) |
1127 | return -EFAULT; | |
1128 | ||
d330a953 | 1129 | if (likely(!i915.prefault_disable)) { |
0b74b508 XZ |
1130 | if (fault_in_multipages_readable(ptr, length)) |
1131 | return -EFAULT; | |
1132 | } | |
54cf91dc CW |
1133 | } |
1134 | ||
1135 | return 0; | |
1136 | } | |
1137 | ||
e2efd130 | 1138 | static struct i915_gem_context * |
d299cce7 | 1139 | i915_gem_validate_context(struct drm_device *dev, struct drm_file *file, |
0bc40be8 | 1140 | struct intel_engine_cs *engine, const u32 ctx_id) |
d299cce7 | 1141 | { |
e2efd130 | 1142 | struct i915_gem_context *ctx = NULL; |
d299cce7 MK |
1143 | struct i915_ctx_hang_stats *hs; |
1144 | ||
0bc40be8 | 1145 | if (engine->id != RCS && ctx_id != DEFAULT_CONTEXT_HANDLE) |
7c9c4b8f DV |
1146 | return ERR_PTR(-EINVAL); |
1147 | ||
ca585b5d | 1148 | ctx = i915_gem_context_lookup(file->driver_priv, ctx_id); |
72ad5c45 | 1149 | if (IS_ERR(ctx)) |
41bde553 | 1150 | return ctx; |
d299cce7 | 1151 | |
41bde553 | 1152 | hs = &ctx->hang_stats; |
d299cce7 MK |
1153 | if (hs->banned) { |
1154 | DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id); | |
41bde553 | 1155 | return ERR_PTR(-EIO); |
d299cce7 MK |
1156 | } |
1157 | ||
41bde553 | 1158 | return ctx; |
d299cce7 MK |
1159 | } |
1160 | ||
5cf3d280 CW |
1161 | void i915_vma_move_to_active(struct i915_vma *vma, |
1162 | struct drm_i915_gem_request *req, | |
1163 | unsigned int flags) | |
1164 | { | |
1165 | struct drm_i915_gem_object *obj = vma->obj; | |
1166 | const unsigned int idx = req->engine->id; | |
1167 | ||
1168 | GEM_BUG_ON(!drm_mm_node_allocated(&vma->node)); | |
1169 | ||
1170 | obj->dirty = 1; /* be paranoid */ | |
1171 | ||
b0decaf7 CW |
1172 | /* Add a reference if we're newly entering the active list. |
1173 | * The order in which we add operations to the retirement queue is | |
1174 | * vital here: mark_active adds to the start of the callback list, | |
1175 | * such that subsequent callbacks are called first. Therefore we | |
1176 | * add the active reference first and queue for it to be dropped | |
1177 | * *last*. | |
1178 | */ | |
573adb39 | 1179 | if (!i915_gem_object_is_active(obj)) |
5cf3d280 | 1180 | i915_gem_object_get(obj); |
573adb39 | 1181 | i915_gem_object_set_active(obj, idx); |
5cf3d280 CW |
1182 | i915_gem_active_set(&obj->last_read[idx], req); |
1183 | ||
1184 | if (flags & EXEC_OBJECT_WRITE) { | |
1185 | i915_gem_active_set(&obj->last_write, req); | |
1186 | ||
1187 | intel_fb_obj_invalidate(obj, ORIGIN_CS); | |
1188 | ||
1189 | /* update for the implicit flush after a batch */ | |
1190 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
1191 | } | |
1192 | ||
1193 | if (flags & EXEC_OBJECT_NEEDS_FENCE) { | |
1194 | i915_gem_active_set(&obj->last_fence, req); | |
1195 | if (flags & __EXEC_OBJECT_HAS_FENCE) { | |
1196 | struct drm_i915_private *dev_priv = req->i915; | |
1197 | ||
1198 | list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list, | |
1199 | &dev_priv->mm.fence_list); | |
1200 | } | |
1201 | } | |
1202 | ||
b0decaf7 CW |
1203 | i915_vma_set_active(vma, idx); |
1204 | i915_gem_active_set(&vma->last_read[idx], req); | |
5cf3d280 CW |
1205 | list_move_tail(&vma->vm_link, &vma->vm->active_list); |
1206 | } | |
1207 | ||
5b043f4e | 1208 | static void |
27173f1f | 1209 | i915_gem_execbuffer_move_to_active(struct list_head *vmas, |
8a8edb59 | 1210 | struct drm_i915_gem_request *req) |
432e58ed | 1211 | { |
27173f1f | 1212 | struct i915_vma *vma; |
432e58ed | 1213 | |
27173f1f BW |
1214 | list_for_each_entry(vma, vmas, exec_list) { |
1215 | struct drm_i915_gem_object *obj = vma->obj; | |
69c2fc89 CW |
1216 | u32 old_read = obj->base.read_domains; |
1217 | u32 old_write = obj->base.write_domain; | |
db53a302 | 1218 | |
432e58ed | 1219 | obj->base.write_domain = obj->base.pending_write_domain; |
5cf3d280 CW |
1220 | if (obj->base.write_domain) |
1221 | vma->exec_entry->flags |= EXEC_OBJECT_WRITE; | |
1222 | else | |
ed5982e6 DV |
1223 | obj->base.pending_read_domains |= obj->base.read_domains; |
1224 | obj->base.read_domains = obj->base.pending_read_domains; | |
432e58ed | 1225 | |
5cf3d280 | 1226 | i915_vma_move_to_active(vma, req, vma->exec_entry->flags); |
db53a302 | 1227 | trace_i915_gem_object_change_domain(obj, old_read, old_write); |
432e58ed CW |
1228 | } |
1229 | } | |
1230 | ||
ae662d31 | 1231 | static int |
b5321f30 | 1232 | i915_reset_gen7_sol_offsets(struct drm_i915_gem_request *req) |
ae662d31 | 1233 | { |
7e37f889 | 1234 | struct intel_ring *ring = req->ring; |
ae662d31 EA |
1235 | int ret, i; |
1236 | ||
b5321f30 | 1237 | if (!IS_GEN7(req->i915) || req->engine->id != RCS) { |
9d662da8 DV |
1238 | DRM_DEBUG("sol reset is gen7/rcs only\n"); |
1239 | return -EINVAL; | |
1240 | } | |
ae662d31 | 1241 | |
5fb9de1a | 1242 | ret = intel_ring_begin(req, 4 * 3); |
ae662d31 EA |
1243 | if (ret) |
1244 | return ret; | |
1245 | ||
1246 | for (i = 0; i < 4; i++) { | |
b5321f30 CW |
1247 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
1248 | intel_ring_emit_reg(ring, GEN7_SO_WRITE_OFFSET(i)); | |
1249 | intel_ring_emit(ring, 0); | |
ae662d31 EA |
1250 | } |
1251 | ||
b5321f30 | 1252 | intel_ring_advance(ring); |
ae662d31 EA |
1253 | |
1254 | return 0; | |
1255 | } | |
1256 | ||
59bfa124 | 1257 | static struct i915_vma* |
0bc40be8 | 1258 | i915_gem_execbuffer_parse(struct intel_engine_cs *engine, |
71745376 | 1259 | struct drm_i915_gem_exec_object2 *shadow_exec_entry, |
71745376 | 1260 | struct drm_i915_gem_object *batch_obj, |
59bfa124 | 1261 | struct eb_vmas *eb, |
71745376 BV |
1262 | u32 batch_start_offset, |
1263 | u32 batch_len, | |
17cabf57 | 1264 | bool is_master) |
71745376 | 1265 | { |
71745376 | 1266 | struct drm_i915_gem_object *shadow_batch_obj; |
17cabf57 | 1267 | struct i915_vma *vma; |
71745376 BV |
1268 | int ret; |
1269 | ||
0bc40be8 | 1270 | shadow_batch_obj = i915_gem_batch_pool_get(&engine->batch_pool, |
17cabf57 | 1271 | PAGE_ALIGN(batch_len)); |
71745376 | 1272 | if (IS_ERR(shadow_batch_obj)) |
59bfa124 | 1273 | return ERR_CAST(shadow_batch_obj); |
71745376 | 1274 | |
33a051a5 CW |
1275 | ret = intel_engine_cmd_parser(engine, |
1276 | batch_obj, | |
1277 | shadow_batch_obj, | |
1278 | batch_start_offset, | |
1279 | batch_len, | |
1280 | is_master); | |
17cabf57 CW |
1281 | if (ret) |
1282 | goto err; | |
71745376 | 1283 | |
de895082 | 1284 | ret = i915_gem_object_ggtt_pin(shadow_batch_obj, NULL, 0, 0, 0); |
17cabf57 CW |
1285 | if (ret) |
1286 | goto err; | |
71745376 | 1287 | |
de4e783a CW |
1288 | i915_gem_object_unpin_pages(shadow_batch_obj); |
1289 | ||
17cabf57 | 1290 | memset(shadow_exec_entry, 0, sizeof(*shadow_exec_entry)); |
71745376 | 1291 | |
17cabf57 CW |
1292 | vma = i915_gem_obj_to_ggtt(shadow_batch_obj); |
1293 | vma->exec_entry = shadow_exec_entry; | |
de4e783a | 1294 | vma->exec_entry->flags = __EXEC_OBJECT_HAS_PIN; |
25dc556a | 1295 | i915_gem_object_get(shadow_batch_obj); |
17cabf57 | 1296 | list_add_tail(&vma->exec_list, &eb->vmas); |
71745376 | 1297 | |
59bfa124 | 1298 | return vma; |
71745376 | 1299 | |
17cabf57 | 1300 | err: |
de4e783a | 1301 | i915_gem_object_unpin_pages(shadow_batch_obj); |
17cabf57 | 1302 | if (ret == -EACCES) /* unhandled chained batch */ |
59bfa124 | 1303 | return NULL; |
17cabf57 CW |
1304 | else |
1305 | return ERR_PTR(ret); | |
71745376 | 1306 | } |
5c6c6003 | 1307 | |
5b043f4e CW |
1308 | static int |
1309 | execbuf_submit(struct i915_execbuffer_params *params, | |
1310 | struct drm_i915_gem_execbuffer2 *args, | |
1311 | struct list_head *vmas) | |
78382593 | 1312 | { |
b5321f30 | 1313 | struct drm_i915_private *dev_priv = params->request->i915; |
5f19e2bf | 1314 | u64 exec_start, exec_len; |
78382593 OM |
1315 | int instp_mode; |
1316 | u32 instp_mask; | |
2f5945bc | 1317 | int ret; |
78382593 | 1318 | |
535fbe82 | 1319 | ret = i915_gem_execbuffer_move_to_gpu(params->request, vmas); |
78382593 | 1320 | if (ret) |
2f5945bc | 1321 | return ret; |
78382593 | 1322 | |
ba01cc93 | 1323 | ret = i915_switch_context(params->request); |
78382593 | 1324 | if (ret) |
2f5945bc | 1325 | return ret; |
78382593 OM |
1326 | |
1327 | instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK; | |
1328 | instp_mask = I915_EXEC_CONSTANTS_MASK; | |
1329 | switch (instp_mode) { | |
1330 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
1331 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
1332 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
b5321f30 | 1333 | if (instp_mode != 0 && params->engine->id != RCS) { |
78382593 | 1334 | DRM_DEBUG("non-0 rel constants mode on non-RCS\n"); |
2f5945bc | 1335 | return -EINVAL; |
78382593 OM |
1336 | } |
1337 | ||
1338 | if (instp_mode != dev_priv->relative_constants_mode) { | |
b5321f30 | 1339 | if (INTEL_INFO(dev_priv)->gen < 4) { |
78382593 | 1340 | DRM_DEBUG("no rel constants on pre-gen4\n"); |
2f5945bc | 1341 | return -EINVAL; |
78382593 OM |
1342 | } |
1343 | ||
b5321f30 | 1344 | if (INTEL_INFO(dev_priv)->gen > 5 && |
78382593 OM |
1345 | instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) { |
1346 | DRM_DEBUG("rel surface constants mode invalid on gen5+\n"); | |
2f5945bc | 1347 | return -EINVAL; |
78382593 OM |
1348 | } |
1349 | ||
1350 | /* The HW changed the meaning on this bit on gen6 */ | |
b5321f30 | 1351 | if (INTEL_INFO(dev_priv)->gen >= 6) |
78382593 OM |
1352 | instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; |
1353 | } | |
1354 | break; | |
1355 | default: | |
1356 | DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode); | |
2f5945bc | 1357 | return -EINVAL; |
78382593 OM |
1358 | } |
1359 | ||
b5321f30 | 1360 | if (params->engine->id == RCS && |
2f5945bc | 1361 | instp_mode != dev_priv->relative_constants_mode) { |
7e37f889 | 1362 | struct intel_ring *ring = params->request->ring; |
b5321f30 | 1363 | |
5fb9de1a | 1364 | ret = intel_ring_begin(params->request, 4); |
78382593 | 1365 | if (ret) |
2f5945bc | 1366 | return ret; |
78382593 | 1367 | |
b5321f30 CW |
1368 | intel_ring_emit(ring, MI_NOOP); |
1369 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
1370 | intel_ring_emit_reg(ring, INSTPM); | |
1371 | intel_ring_emit(ring, instp_mask << 16 | instp_mode); | |
1372 | intel_ring_advance(ring); | |
78382593 OM |
1373 | |
1374 | dev_priv->relative_constants_mode = instp_mode; | |
1375 | } | |
1376 | ||
1377 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { | |
b5321f30 | 1378 | ret = i915_reset_gen7_sol_offsets(params->request); |
78382593 | 1379 | if (ret) |
2f5945bc | 1380 | return ret; |
78382593 OM |
1381 | } |
1382 | ||
5f19e2bf | 1383 | exec_len = args->batch_len; |
59bfa124 | 1384 | exec_start = params->batch->node.start + |
5f19e2bf JH |
1385 | params->args_batch_start_offset; |
1386 | ||
9d611c03 | 1387 | if (exec_len == 0) |
59bfa124 | 1388 | exec_len = params->batch->size; |
9d611c03 | 1389 | |
803688ba CW |
1390 | ret = params->engine->emit_bb_start(params->request, |
1391 | exec_start, exec_len, | |
1392 | params->dispatch_flags); | |
2f5945bc CW |
1393 | if (ret) |
1394 | return ret; | |
78382593 | 1395 | |
95c24161 | 1396 | trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags); |
78382593 | 1397 | |
8a8edb59 | 1398 | i915_gem_execbuffer_move_to_active(vmas, params->request); |
78382593 | 1399 | |
2f5945bc | 1400 | return 0; |
78382593 OM |
1401 | } |
1402 | ||
a8ebba75 ZY |
1403 | /** |
1404 | * Find one BSD ring to dispatch the corresponding BSD command. | |
c80ff16e | 1405 | * The engine index is returned. |
a8ebba75 | 1406 | */ |
de1add36 | 1407 | static unsigned int |
c80ff16e CW |
1408 | gen8_dispatch_bsd_engine(struct drm_i915_private *dev_priv, |
1409 | struct drm_file *file) | |
a8ebba75 | 1410 | { |
a8ebba75 ZY |
1411 | struct drm_i915_file_private *file_priv = file->driver_priv; |
1412 | ||
de1add36 | 1413 | /* Check whether the file_priv has already selected one ring. */ |
c80ff16e | 1414 | if ((int)file_priv->bsd_engine < 0) { |
de1add36 | 1415 | /* If not, use the ping-pong mechanism to select one. */ |
91c8a326 | 1416 | mutex_lock(&dev_priv->drm.struct_mutex); |
c80ff16e CW |
1417 | file_priv->bsd_engine = dev_priv->mm.bsd_engine_dispatch_index; |
1418 | dev_priv->mm.bsd_engine_dispatch_index ^= 1; | |
91c8a326 | 1419 | mutex_unlock(&dev_priv->drm.struct_mutex); |
a8ebba75 | 1420 | } |
de1add36 | 1421 | |
c80ff16e | 1422 | return file_priv->bsd_engine; |
a8ebba75 ZY |
1423 | } |
1424 | ||
de1add36 TU |
1425 | #define I915_USER_RINGS (4) |
1426 | ||
117897f4 | 1427 | static const enum intel_engine_id user_ring_map[I915_USER_RINGS + 1] = { |
de1add36 TU |
1428 | [I915_EXEC_DEFAULT] = RCS, |
1429 | [I915_EXEC_RENDER] = RCS, | |
1430 | [I915_EXEC_BLT] = BCS, | |
1431 | [I915_EXEC_BSD] = VCS, | |
1432 | [I915_EXEC_VEBOX] = VECS | |
1433 | }; | |
1434 | ||
f8ca0c07 DG |
1435 | static struct intel_engine_cs * |
1436 | eb_select_engine(struct drm_i915_private *dev_priv, | |
1437 | struct drm_file *file, | |
1438 | struct drm_i915_gem_execbuffer2 *args) | |
de1add36 TU |
1439 | { |
1440 | unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK; | |
f8ca0c07 | 1441 | struct intel_engine_cs *engine; |
de1add36 TU |
1442 | |
1443 | if (user_ring_id > I915_USER_RINGS) { | |
1444 | DRM_DEBUG("execbuf with unknown ring: %u\n", user_ring_id); | |
f8ca0c07 | 1445 | return NULL; |
de1add36 TU |
1446 | } |
1447 | ||
1448 | if ((user_ring_id != I915_EXEC_BSD) && | |
1449 | ((args->flags & I915_EXEC_BSD_MASK) != 0)) { | |
1450 | DRM_DEBUG("execbuf with non bsd ring but with invalid " | |
1451 | "bsd dispatch flags: %d\n", (int)(args->flags)); | |
f8ca0c07 | 1452 | return NULL; |
de1add36 TU |
1453 | } |
1454 | ||
1455 | if (user_ring_id == I915_EXEC_BSD && HAS_BSD2(dev_priv)) { | |
1456 | unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK; | |
1457 | ||
1458 | if (bsd_idx == I915_EXEC_BSD_DEFAULT) { | |
c80ff16e | 1459 | bsd_idx = gen8_dispatch_bsd_engine(dev_priv, file); |
de1add36 TU |
1460 | } else if (bsd_idx >= I915_EXEC_BSD_RING1 && |
1461 | bsd_idx <= I915_EXEC_BSD_RING2) { | |
d9da6aa0 | 1462 | bsd_idx >>= I915_EXEC_BSD_SHIFT; |
de1add36 TU |
1463 | bsd_idx--; |
1464 | } else { | |
1465 | DRM_DEBUG("execbuf with unknown bsd ring: %u\n", | |
1466 | bsd_idx); | |
f8ca0c07 | 1467 | return NULL; |
de1add36 TU |
1468 | } |
1469 | ||
f8ca0c07 | 1470 | engine = &dev_priv->engine[_VCS(bsd_idx)]; |
de1add36 | 1471 | } else { |
f8ca0c07 | 1472 | engine = &dev_priv->engine[user_ring_map[user_ring_id]]; |
de1add36 TU |
1473 | } |
1474 | ||
f8ca0c07 | 1475 | if (!intel_engine_initialized(engine)) { |
de1add36 | 1476 | DRM_DEBUG("execbuf with invalid ring: %u\n", user_ring_id); |
f8ca0c07 | 1477 | return NULL; |
de1add36 TU |
1478 | } |
1479 | ||
f8ca0c07 | 1480 | return engine; |
de1add36 TU |
1481 | } |
1482 | ||
54cf91dc CW |
1483 | static int |
1484 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, | |
1485 | struct drm_file *file, | |
1486 | struct drm_i915_gem_execbuffer2 *args, | |
41bde553 | 1487 | struct drm_i915_gem_exec_object2 *exec) |
54cf91dc | 1488 | { |
72e96d64 JL |
1489 | struct drm_i915_private *dev_priv = to_i915(dev); |
1490 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
27173f1f | 1491 | struct eb_vmas *eb; |
78a42377 | 1492 | struct drm_i915_gem_exec_object2 shadow_exec_entry; |
e2f80391 | 1493 | struct intel_engine_cs *engine; |
e2efd130 | 1494 | struct i915_gem_context *ctx; |
41bde553 | 1495 | struct i915_address_space *vm; |
5f19e2bf JH |
1496 | struct i915_execbuffer_params params_master; /* XXX: will be removed later */ |
1497 | struct i915_execbuffer_params *params = ¶ms_master; | |
d299cce7 | 1498 | const u32 ctx_id = i915_execbuffer2_get_context_id(*args); |
8e004efc | 1499 | u32 dispatch_flags; |
78382593 | 1500 | int ret; |
ed5982e6 | 1501 | bool need_relocs; |
54cf91dc | 1502 | |
ed5982e6 | 1503 | if (!i915_gem_check_execbuffer(args)) |
432e58ed | 1504 | return -EINVAL; |
432e58ed | 1505 | |
ad19f10b | 1506 | ret = validate_exec_list(dev, exec, args->buffer_count); |
54cf91dc CW |
1507 | if (ret) |
1508 | return ret; | |
1509 | ||
8e004efc | 1510 | dispatch_flags = 0; |
d7d4eedd | 1511 | if (args->flags & I915_EXEC_SECURE) { |
b3ac9f25 | 1512 | if (!drm_is_current_master(file) || !capable(CAP_SYS_ADMIN)) |
d7d4eedd CW |
1513 | return -EPERM; |
1514 | ||
8e004efc | 1515 | dispatch_flags |= I915_DISPATCH_SECURE; |
d7d4eedd | 1516 | } |
b45305fc | 1517 | if (args->flags & I915_EXEC_IS_PINNED) |
8e004efc | 1518 | dispatch_flags |= I915_DISPATCH_PINNED; |
d7d4eedd | 1519 | |
f8ca0c07 DG |
1520 | engine = eb_select_engine(dev_priv, file, args); |
1521 | if (!engine) | |
1522 | return -EINVAL; | |
54cf91dc CW |
1523 | |
1524 | if (args->buffer_count < 1) { | |
ff240199 | 1525 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1526 | return -EINVAL; |
1527 | } | |
54cf91dc | 1528 | |
a9ed33ca AJ |
1529 | if (args->flags & I915_EXEC_RESOURCE_STREAMER) { |
1530 | if (!HAS_RESOURCE_STREAMER(dev)) { | |
1531 | DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n"); | |
1532 | return -EINVAL; | |
1533 | } | |
e2f80391 | 1534 | if (engine->id != RCS) { |
a9ed33ca | 1535 | DRM_DEBUG("RS is not available on %s\n", |
e2f80391 | 1536 | engine->name); |
a9ed33ca AJ |
1537 | return -EINVAL; |
1538 | } | |
1539 | ||
1540 | dispatch_flags |= I915_DISPATCH_RS; | |
1541 | } | |
1542 | ||
67d97da3 CW |
1543 | /* Take a local wakeref for preparing to dispatch the execbuf as |
1544 | * we expect to access the hardware fairly frequently in the | |
1545 | * process. Upon first dispatch, we acquire another prolonged | |
1546 | * wakeref that we hold until the GPU has been idle for at least | |
1547 | * 100ms. | |
1548 | */ | |
f65c9168 PZ |
1549 | intel_runtime_pm_get(dev_priv); |
1550 | ||
54cf91dc CW |
1551 | ret = i915_mutex_lock_interruptible(dev); |
1552 | if (ret) | |
1553 | goto pre_mutex_err; | |
1554 | ||
e2f80391 | 1555 | ctx = i915_gem_validate_context(dev, file, engine, ctx_id); |
72ad5c45 | 1556 | if (IS_ERR(ctx)) { |
d299cce7 | 1557 | mutex_unlock(&dev->struct_mutex); |
41bde553 | 1558 | ret = PTR_ERR(ctx); |
d299cce7 | 1559 | goto pre_mutex_err; |
935f38d6 | 1560 | } |
41bde553 | 1561 | |
9a6feaf0 | 1562 | i915_gem_context_get(ctx); |
41bde553 | 1563 | |
ae6c4806 DV |
1564 | if (ctx->ppgtt) |
1565 | vm = &ctx->ppgtt->base; | |
1566 | else | |
72e96d64 | 1567 | vm = &ggtt->base; |
d299cce7 | 1568 | |
5f19e2bf JH |
1569 | memset(¶ms_master, 0x00, sizeof(params_master)); |
1570 | ||
17601cbc | 1571 | eb = eb_create(args); |
67731b87 | 1572 | if (eb == NULL) { |
9a6feaf0 | 1573 | i915_gem_context_put(ctx); |
67731b87 CW |
1574 | mutex_unlock(&dev->struct_mutex); |
1575 | ret = -ENOMEM; | |
1576 | goto pre_mutex_err; | |
1577 | } | |
1578 | ||
54cf91dc | 1579 | /* Look up object handles */ |
27173f1f | 1580 | ret = eb_lookup_vmas(eb, exec, args, vm, file); |
3b96eff4 CW |
1581 | if (ret) |
1582 | goto err; | |
54cf91dc | 1583 | |
6fe4f140 | 1584 | /* take note of the batch buffer before we might reorder the lists */ |
59bfa124 | 1585 | params->batch = eb_get_batch(eb); |
6fe4f140 | 1586 | |
54cf91dc | 1587 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
ed5982e6 | 1588 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
e2f80391 TU |
1589 | ret = i915_gem_execbuffer_reserve(engine, &eb->vmas, ctx, |
1590 | &need_relocs); | |
54cf91dc CW |
1591 | if (ret) |
1592 | goto err; | |
1593 | ||
1594 | /* The objects are in their final locations, apply the relocations. */ | |
ed5982e6 | 1595 | if (need_relocs) |
17601cbc | 1596 | ret = i915_gem_execbuffer_relocate(eb); |
54cf91dc CW |
1597 | if (ret) { |
1598 | if (ret == -EFAULT) { | |
e2f80391 TU |
1599 | ret = i915_gem_execbuffer_relocate_slow(dev, args, file, |
1600 | engine, | |
b1b38278 | 1601 | eb, exec, ctx); |
54cf91dc CW |
1602 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
1603 | } | |
1604 | if (ret) | |
1605 | goto err; | |
1606 | } | |
1607 | ||
1608 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
59bfa124 | 1609 | if (params->batch->obj->base.pending_write_domain) { |
ff240199 | 1610 | DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); |
54cf91dc CW |
1611 | ret = -EINVAL; |
1612 | goto err; | |
1613 | } | |
54cf91dc | 1614 | |
5f19e2bf | 1615 | params->args_batch_start_offset = args->batch_start_offset; |
33a051a5 | 1616 | if (intel_engine_needs_cmd_parser(engine) && args->batch_len) { |
59bfa124 CW |
1617 | struct i915_vma *vma; |
1618 | ||
1619 | vma = i915_gem_execbuffer_parse(engine, &shadow_exec_entry, | |
1620 | params->batch->obj, | |
1621 | eb, | |
1622 | args->batch_start_offset, | |
1623 | args->batch_len, | |
1624 | drm_is_current_master(file)); | |
1625 | if (IS_ERR(vma)) { | |
1626 | ret = PTR_ERR(vma); | |
78a42377 BV |
1627 | goto err; |
1628 | } | |
17cabf57 | 1629 | |
59bfa124 | 1630 | if (vma) { |
c7c7372e RP |
1631 | /* |
1632 | * Batch parsed and accepted: | |
1633 | * | |
1634 | * Set the DISPATCH_SECURE bit to remove the NON_SECURE | |
1635 | * bit from MI_BATCH_BUFFER_START commands issued in | |
1636 | * the dispatch_execbuffer implementations. We | |
1637 | * specifically don't want that set on batches the | |
1638 | * command parser has accepted. | |
1639 | */ | |
1640 | dispatch_flags |= I915_DISPATCH_SECURE; | |
5f19e2bf | 1641 | params->args_batch_start_offset = 0; |
59bfa124 | 1642 | params->batch = vma; |
c7c7372e | 1643 | } |
351e3db2 BV |
1644 | } |
1645 | ||
59bfa124 | 1646 | params->batch->obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; |
78a42377 | 1647 | |
d7d4eedd CW |
1648 | /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure |
1649 | * batch" bit. Hence we need to pin secure batches into the global gtt. | |
28cf5415 | 1650 | * hsw should have this fixed, but bdw mucks it up again. */ |
8e004efc | 1651 | if (dispatch_flags & I915_DISPATCH_SECURE) { |
59bfa124 CW |
1652 | struct drm_i915_gem_object *obj = params->batch->obj; |
1653 | ||
da51a1e7 DV |
1654 | /* |
1655 | * So on first glance it looks freaky that we pin the batch here | |
1656 | * outside of the reservation loop. But: | |
1657 | * - The batch is already pinned into the relevant ppgtt, so we | |
1658 | * already have the backing storage fully allocated. | |
1659 | * - No other BO uses the global gtt (well contexts, but meh), | |
fd0753cf | 1660 | * so we don't really have issues with multiple objects not |
da51a1e7 DV |
1661 | * fitting due to fragmentation. |
1662 | * So this is actually safe. | |
1663 | */ | |
de895082 | 1664 | ret = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0); |
da51a1e7 DV |
1665 | if (ret) |
1666 | goto err; | |
d7d4eedd | 1667 | |
59bfa124 CW |
1668 | params->batch = i915_gem_obj_to_ggtt(obj); |
1669 | } | |
d7d4eedd | 1670 | |
0c8dac88 | 1671 | /* Allocate a request for this batch buffer nice and early. */ |
8e637178 CW |
1672 | params->request = i915_gem_request_alloc(engine, ctx); |
1673 | if (IS_ERR(params->request)) { | |
1674 | ret = PTR_ERR(params->request); | |
0c8dac88 | 1675 | goto err_batch_unpin; |
26827088 | 1676 | } |
0c8dac88 | 1677 | |
8e637178 | 1678 | ret = i915_gem_request_add_to_client(params->request, file); |
fcfa423c | 1679 | if (ret) |
aa9b7810 | 1680 | goto err_request; |
fcfa423c | 1681 | |
5f19e2bf JH |
1682 | /* |
1683 | * Save assorted stuff away to pass through to *_submission(). | |
1684 | * NB: This data should be 'persistent' and not local as it will | |
1685 | * kept around beyond the duration of the IOCTL once the GPU | |
1686 | * scheduler arrives. | |
1687 | */ | |
1688 | params->dev = dev; | |
1689 | params->file = file; | |
4a570db5 | 1690 | params->engine = engine; |
5f19e2bf | 1691 | params->dispatch_flags = dispatch_flags; |
5f19e2bf JH |
1692 | params->ctx = ctx; |
1693 | ||
5b043f4e | 1694 | ret = execbuf_submit(params, args, &eb->vmas); |
aa9b7810 | 1695 | err_request: |
59bfa124 | 1696 | __i915_add_request(params->request, params->batch->obj, ret == 0); |
54cf91dc | 1697 | |
0c8dac88 | 1698 | err_batch_unpin: |
da51a1e7 DV |
1699 | /* |
1700 | * FIXME: We crucially rely upon the active tracking for the (ppgtt) | |
1701 | * batch vma for correctness. For less ugly and less fragility this | |
1702 | * needs to be adjusted to also track the ggtt batch vma properly as | |
1703 | * active. | |
1704 | */ | |
8e004efc | 1705 | if (dispatch_flags & I915_DISPATCH_SECURE) |
59bfa124 | 1706 | i915_vma_unpin(params->batch); |
54cf91dc | 1707 | err: |
41bde553 | 1708 | /* the request owns the ref now */ |
9a6feaf0 | 1709 | i915_gem_context_put(ctx); |
67731b87 | 1710 | eb_destroy(eb); |
54cf91dc CW |
1711 | |
1712 | mutex_unlock(&dev->struct_mutex); | |
1713 | ||
1714 | pre_mutex_err: | |
f65c9168 PZ |
1715 | /* intel_gpu_busy should also get a ref, so it will free when the device |
1716 | * is really idle. */ | |
1717 | intel_runtime_pm_put(dev_priv); | |
54cf91dc CW |
1718 | return ret; |
1719 | } | |
1720 | ||
1721 | /* | |
1722 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
1723 | * list array and passes it to the real function. | |
1724 | */ | |
1725 | int | |
1726 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1727 | struct drm_file *file) | |
1728 | { | |
1729 | struct drm_i915_gem_execbuffer *args = data; | |
1730 | struct drm_i915_gem_execbuffer2 exec2; | |
1731 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
1732 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1733 | int ret, i; | |
1734 | ||
54cf91dc | 1735 | if (args->buffer_count < 1) { |
ff240199 | 1736 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1737 | return -EINVAL; |
1738 | } | |
1739 | ||
1740 | /* Copy in the exec list from userland */ | |
1741 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
1742 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
1743 | if (exec_list == NULL || exec2_list == NULL) { | |
ff240199 | 1744 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1745 | args->buffer_count); |
1746 | drm_free_large(exec_list); | |
1747 | drm_free_large(exec2_list); | |
1748 | return -ENOMEM; | |
1749 | } | |
1750 | ret = copy_from_user(exec_list, | |
3ed605bc | 1751 | u64_to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1752 | sizeof(*exec_list) * args->buffer_count); |
1753 | if (ret != 0) { | |
ff240199 | 1754 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1755 | args->buffer_count, ret); |
1756 | drm_free_large(exec_list); | |
1757 | drm_free_large(exec2_list); | |
1758 | return -EFAULT; | |
1759 | } | |
1760 | ||
1761 | for (i = 0; i < args->buffer_count; i++) { | |
1762 | exec2_list[i].handle = exec_list[i].handle; | |
1763 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
1764 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
1765 | exec2_list[i].alignment = exec_list[i].alignment; | |
1766 | exec2_list[i].offset = exec_list[i].offset; | |
1767 | if (INTEL_INFO(dev)->gen < 4) | |
1768 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; | |
1769 | else | |
1770 | exec2_list[i].flags = 0; | |
1771 | } | |
1772 | ||
1773 | exec2.buffers_ptr = args->buffers_ptr; | |
1774 | exec2.buffer_count = args->buffer_count; | |
1775 | exec2.batch_start_offset = args->batch_start_offset; | |
1776 | exec2.batch_len = args->batch_len; | |
1777 | exec2.DR1 = args->DR1; | |
1778 | exec2.DR4 = args->DR4; | |
1779 | exec2.num_cliprects = args->num_cliprects; | |
1780 | exec2.cliprects_ptr = args->cliprects_ptr; | |
1781 | exec2.flags = I915_EXEC_RENDER; | |
6e0a69db | 1782 | i915_execbuffer2_set_context_id(exec2, 0); |
54cf91dc | 1783 | |
41bde553 | 1784 | ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list); |
54cf91dc | 1785 | if (!ret) { |
9aab8bff | 1786 | struct drm_i915_gem_exec_object __user *user_exec_list = |
3ed605bc | 1787 | u64_to_user_ptr(args->buffers_ptr); |
9aab8bff | 1788 | |
54cf91dc | 1789 | /* Copy the new buffer offsets back to the user's exec list. */ |
9aab8bff | 1790 | for (i = 0; i < args->buffer_count; i++) { |
934acce3 MW |
1791 | exec2_list[i].offset = |
1792 | gen8_canonical_addr(exec2_list[i].offset); | |
9aab8bff CW |
1793 | ret = __copy_to_user(&user_exec_list[i].offset, |
1794 | &exec2_list[i].offset, | |
1795 | sizeof(user_exec_list[i].offset)); | |
1796 | if (ret) { | |
1797 | ret = -EFAULT; | |
1798 | DRM_DEBUG("failed to copy %d exec entries " | |
1799 | "back to user (%d)\n", | |
1800 | args->buffer_count, ret); | |
1801 | break; | |
1802 | } | |
54cf91dc CW |
1803 | } |
1804 | } | |
1805 | ||
1806 | drm_free_large(exec_list); | |
1807 | drm_free_large(exec2_list); | |
1808 | return ret; | |
1809 | } | |
1810 | ||
1811 | int | |
1812 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
1813 | struct drm_file *file) | |
1814 | { | |
1815 | struct drm_i915_gem_execbuffer2 *args = data; | |
1816 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1817 | int ret; | |
1818 | ||
ed8cd3b2 XW |
1819 | if (args->buffer_count < 1 || |
1820 | args->buffer_count > UINT_MAX / sizeof(*exec2_list)) { | |
ff240199 | 1821 | DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1822 | return -EINVAL; |
1823 | } | |
1824 | ||
9cb34664 DV |
1825 | if (args->rsvd2 != 0) { |
1826 | DRM_DEBUG("dirty rvsd2 field\n"); | |
1827 | return -EINVAL; | |
1828 | } | |
1829 | ||
f2a85e19 CW |
1830 | exec2_list = drm_malloc_gfp(args->buffer_count, |
1831 | sizeof(*exec2_list), | |
1832 | GFP_TEMPORARY); | |
54cf91dc | 1833 | if (exec2_list == NULL) { |
ff240199 | 1834 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1835 | args->buffer_count); |
1836 | return -ENOMEM; | |
1837 | } | |
1838 | ret = copy_from_user(exec2_list, | |
3ed605bc | 1839 | u64_to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1840 | sizeof(*exec2_list) * args->buffer_count); |
1841 | if (ret != 0) { | |
ff240199 | 1842 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1843 | args->buffer_count, ret); |
1844 | drm_free_large(exec2_list); | |
1845 | return -EFAULT; | |
1846 | } | |
1847 | ||
41bde553 | 1848 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list); |
54cf91dc CW |
1849 | if (!ret) { |
1850 | /* Copy the new buffer offsets back to the user's exec list. */ | |
d593d992 | 1851 | struct drm_i915_gem_exec_object2 __user *user_exec_list = |
3ed605bc | 1852 | u64_to_user_ptr(args->buffers_ptr); |
9aab8bff CW |
1853 | int i; |
1854 | ||
1855 | for (i = 0; i < args->buffer_count; i++) { | |
934acce3 MW |
1856 | exec2_list[i].offset = |
1857 | gen8_canonical_addr(exec2_list[i].offset); | |
9aab8bff CW |
1858 | ret = __copy_to_user(&user_exec_list[i].offset, |
1859 | &exec2_list[i].offset, | |
1860 | sizeof(user_exec_list[i].offset)); | |
1861 | if (ret) { | |
1862 | ret = -EFAULT; | |
1863 | DRM_DEBUG("failed to copy %d exec entries " | |
1864 | "back to user\n", | |
1865 | args->buffer_count); | |
1866 | break; | |
1867 | } | |
54cf91dc CW |
1868 | } |
1869 | } | |
1870 | ||
1871 | drm_free_large(exec2_list); | |
1872 | return ret; | |
1873 | } |