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254f965c BW |
1 | /* |
2 | * Copyright © 2011-2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | /* | |
29 | * This file implements HW context support. On gen5+ a HW context consists of an | |
30 | * opaque GPU object which is referenced at times of context saves and restores. | |
31 | * With RC6 enabled, the context is also referenced as the GPU enters and exists | |
32 | * from RC6 (GPU has it's own internal power context, except on gen5). Though | |
33 | * something like a context does exist for the media ring, the code only | |
34 | * supports contexts for the render ring. | |
35 | * | |
36 | * In software, there is a distinction between contexts created by the user, | |
37 | * and the default HW context. The default HW context is used by GPU clients | |
38 | * that do not request setup of their own hardware context. The default | |
39 | * context's state is never restored to help prevent programming errors. This | |
40 | * would happen if a client ran and piggy-backed off another clients GPU state. | |
41 | * The default context only exists to give the GPU some offset to load as the | |
42 | * current to invoke a save of the context we actually care about. In fact, the | |
43 | * code could likely be constructed, albeit in a more complicated fashion, to | |
44 | * never use the default context, though that limits the driver's ability to | |
45 | * swap out, and/or destroy other contexts. | |
46 | * | |
47 | * All other contexts are created as a request by the GPU client. These contexts | |
48 | * store GPU state, and thus allow GPU clients to not re-emit state (and | |
49 | * potentially query certain state) at any time. The kernel driver makes | |
50 | * certain that the appropriate commands are inserted. | |
51 | * | |
52 | * The context life cycle is semi-complicated in that context BOs may live | |
53 | * longer than the context itself because of the way the hardware, and object | |
54 | * tracking works. Below is a very crude representation of the state machine | |
55 | * describing the context life. | |
56 | * refcount pincount active | |
57 | * S0: initial state 0 0 0 | |
58 | * S1: context created 1 0 0 | |
59 | * S2: context is currently running 2 1 X | |
60 | * S3: GPU referenced, but not current 2 0 1 | |
61 | * S4: context is current, but destroyed 1 1 0 | |
62 | * S5: like S3, but destroyed 1 0 1 | |
63 | * | |
64 | * The most common (but not all) transitions: | |
65 | * S0->S1: client creates a context | |
66 | * S1->S2: client submits execbuf with context | |
67 | * S2->S3: other clients submits execbuf with context | |
68 | * S3->S1: context object was retired | |
69 | * S3->S2: clients submits another execbuf | |
70 | * S2->S4: context destroy called with current context | |
71 | * S3->S5->S0: destroy path | |
72 | * S4->S5->S0: destroy path on current context | |
73 | * | |
74 | * There are two confusing terms used above: | |
75 | * The "current context" means the context which is currently running on the | |
508842a0 | 76 | * GPU. The GPU has loaded its state already and has stored away the gtt |
254f965c BW |
77 | * offset of the BO. The GPU is not actively referencing the data at this |
78 | * offset, but it will on the next context switch. The only way to avoid this | |
79 | * is to do a GPU reset. | |
80 | * | |
81 | * An "active context' is one which was previously the "current context" and is | |
82 | * on the active list waiting for the next context switch to occur. Until this | |
83 | * happens, the object must remain at the same gtt offset. It is therefore | |
84 | * possible to destroy a context, but it is still active. | |
85 | * | |
86 | */ | |
87 | ||
760285e7 DH |
88 | #include <drm/drmP.h> |
89 | #include <drm/i915_drm.h> | |
254f965c | 90 | #include "i915_drv.h" |
198c974d | 91 | #include "i915_trace.h" |
254f965c | 92 | |
b2e862d0 CW |
93 | #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1 |
94 | ||
dce3271b | 95 | void i915_gem_context_free(struct kref *ctx_ref) |
40521054 | 96 | { |
e2efd130 | 97 | struct i915_gem_context *ctx = container_of(ctx_ref, typeof(*ctx), ref); |
bca44d80 | 98 | int i; |
40521054 | 99 | |
91c8a326 | 100 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
198c974d | 101 | trace_i915_context_free(ctx); |
6095868a | 102 | GEM_BUG_ON(!i915_gem_context_is_closed(ctx)); |
198c974d | 103 | |
ae6c4806 DV |
104 | i915_ppgtt_put(ctx->ppgtt); |
105 | ||
bca44d80 CW |
106 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
107 | struct intel_context *ce = &ctx->engine[i]; | |
108 | ||
109 | if (!ce->state) | |
110 | continue; | |
111 | ||
112 | WARN_ON(ce->pin_count); | |
dca33ecc | 113 | if (ce->ring) |
7e37f889 | 114 | intel_ring_free(ce->ring); |
bca44d80 | 115 | |
f8a7fde4 | 116 | __i915_gem_object_release_unless_active(ce->state->obj); |
bca44d80 CW |
117 | } |
118 | ||
562f5d45 | 119 | kfree(ctx->name); |
c84455b4 | 120 | put_pid(ctx->pid); |
c7c48dfd | 121 | list_del(&ctx->link); |
5d1808ec CW |
122 | |
123 | ida_simple_remove(&ctx->i915->context_hw_ida, ctx->hw_id); | |
40521054 BW |
124 | kfree(ctx); |
125 | } | |
126 | ||
50e046b6 CW |
127 | static void context_close(struct i915_gem_context *ctx) |
128 | { | |
6095868a | 129 | i915_gem_context_set_closed(ctx); |
50e046b6 CW |
130 | if (ctx->ppgtt) |
131 | i915_ppgtt_close(&ctx->ppgtt->base); | |
132 | ctx->file_priv = ERR_PTR(-EBADF); | |
133 | i915_gem_context_put(ctx); | |
134 | } | |
135 | ||
5d1808ec CW |
136 | static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out) |
137 | { | |
138 | int ret; | |
139 | ||
140 | ret = ida_simple_get(&dev_priv->context_hw_ida, | |
141 | 0, MAX_CONTEXT_HW_ID, GFP_KERNEL); | |
142 | if (ret < 0) { | |
143 | /* Contexts are only released when no longer active. | |
144 | * Flush any pending retires to hopefully release some | |
145 | * stale contexts and try again. | |
146 | */ | |
c033666a | 147 | i915_gem_retire_requests(dev_priv); |
5d1808ec CW |
148 | ret = ida_simple_get(&dev_priv->context_hw_ida, |
149 | 0, MAX_CONTEXT_HW_ID, GFP_KERNEL); | |
150 | if (ret < 0) | |
151 | return ret; | |
152 | } | |
153 | ||
154 | *out = ret; | |
155 | return 0; | |
156 | } | |
157 | ||
949e8ab3 CW |
158 | static u32 default_desc_template(const struct drm_i915_private *i915, |
159 | const struct i915_hw_ppgtt *ppgtt) | |
2355cf08 | 160 | { |
949e8ab3 | 161 | u32 address_mode; |
2355cf08 MK |
162 | u32 desc; |
163 | ||
949e8ab3 | 164 | desc = GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE; |
2355cf08 | 165 | |
949e8ab3 CW |
166 | address_mode = INTEL_LEGACY_32B_CONTEXT; |
167 | if (ppgtt && i915_vm_is_48bit(&ppgtt->base)) | |
168 | address_mode = INTEL_LEGACY_64B_CONTEXT; | |
169 | desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT; | |
170 | ||
171 | if (IS_GEN8(i915)) | |
2355cf08 MK |
172 | desc |= GEN8_CTX_L3LLC_COHERENT; |
173 | ||
174 | /* TODO: WaDisableLiteRestore when we start using semaphore | |
175 | * signalling between Command Streamers | |
176 | * ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; | |
177 | */ | |
178 | ||
179 | return desc; | |
180 | } | |
181 | ||
e2efd130 | 182 | static struct i915_gem_context * |
bf9e8429 | 183 | __create_hw_context(struct drm_i915_private *dev_priv, |
ee960be7 | 184 | struct drm_i915_file_private *file_priv) |
40521054 | 185 | { |
e2efd130 | 186 | struct i915_gem_context *ctx; |
c8c470af | 187 | int ret; |
40521054 | 188 | |
f94982b0 | 189 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
146937e5 BW |
190 | if (ctx == NULL) |
191 | return ERR_PTR(-ENOMEM); | |
40521054 | 192 | |
5d1808ec CW |
193 | ret = assign_hw_id(dev_priv, &ctx->hw_id); |
194 | if (ret) { | |
195 | kfree(ctx); | |
196 | return ERR_PTR(ret); | |
197 | } | |
198 | ||
dce3271b | 199 | kref_init(&ctx->ref); |
691e6415 | 200 | list_add_tail(&ctx->link, &dev_priv->context_list); |
9ea4feec | 201 | ctx->i915 = dev_priv; |
40521054 | 202 | |
40521054 | 203 | /* Default context will never have a file_priv */ |
562f5d45 CW |
204 | ret = DEFAULT_CONTEXT_HANDLE; |
205 | if (file_priv) { | |
691e6415 | 206 | ret = idr_alloc(&file_priv->context_idr, ctx, |
821d66dd | 207 | DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL); |
691e6415 CW |
208 | if (ret < 0) |
209 | goto err_out; | |
562f5d45 CW |
210 | } |
211 | ctx->user_handle = ret; | |
dce3271b MK |
212 | |
213 | ctx->file_priv = file_priv; | |
562f5d45 | 214 | if (file_priv) { |
c84455b4 | 215 | ctx->pid = get_task_pid(current, PIDTYPE_PID); |
562f5d45 CW |
216 | ctx->name = kasprintf(GFP_KERNEL, "%s[%d]/%x", |
217 | current->comm, | |
218 | pid_nr(ctx->pid), | |
219 | ctx->user_handle); | |
220 | if (!ctx->name) { | |
221 | ret = -ENOMEM; | |
222 | goto err_pid; | |
223 | } | |
224 | } | |
c84455b4 | 225 | |
3ccfd19d BW |
226 | /* NB: Mark all slices as needing a remap so that when the context first |
227 | * loads it will restore whatever remap state already exists. If there | |
228 | * is no remap info, it will be a NOP. */ | |
b2e862d0 | 229 | ctx->remap_slice = ALL_L3_SLICES(dev_priv); |
40521054 | 230 | |
6095868a | 231 | i915_gem_context_set_bannable(ctx); |
bcd794c2 | 232 | ctx->ring_size = 4 * PAGE_SIZE; |
949e8ab3 CW |
233 | ctx->desc_template = |
234 | default_desc_template(dev_priv, dev_priv->mm.aliasing_ppgtt); | |
676fa572 | 235 | |
d3ef1af6 DCS |
236 | /* GuC requires the ring to be placed above GUC_WOPCM_TOP. If GuC is not |
237 | * present or not in use we still need a small bias as ring wraparound | |
238 | * at offset 0 sometimes hangs. No idea why. | |
239 | */ | |
240 | if (HAS_GUC(dev_priv) && i915.enable_guc_loading) | |
241 | ctx->ggtt_offset_bias = GUC_WOPCM_TOP; | |
242 | else | |
f51455d4 | 243 | ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE; |
d3ef1af6 | 244 | |
146937e5 | 245 | return ctx; |
40521054 | 246 | |
562f5d45 CW |
247 | err_pid: |
248 | put_pid(ctx->pid); | |
249 | idr_remove(&file_priv->context_idr, ctx->user_handle); | |
40521054 | 250 | err_out: |
50e046b6 | 251 | context_close(ctx); |
146937e5 | 252 | return ERR_PTR(ret); |
40521054 BW |
253 | } |
254 | ||
6d1f9fb3 JL |
255 | static void __destroy_hw_context(struct i915_gem_context *ctx, |
256 | struct drm_i915_file_private *file_priv) | |
257 | { | |
258 | idr_remove(&file_priv->context_idr, ctx->user_handle); | |
259 | context_close(ctx); | |
260 | } | |
261 | ||
254f965c BW |
262 | /** |
263 | * The default context needs to exist per ring that uses contexts. It stores the | |
264 | * context state of the GPU for applications that don't utilize HW contexts, as | |
265 | * well as an idle case. | |
266 | */ | |
e2efd130 | 267 | static struct i915_gem_context * |
bf9e8429 | 268 | i915_gem_create_context(struct drm_i915_private *dev_priv, |
d624d86e | 269 | struct drm_i915_file_private *file_priv) |
254f965c | 270 | { |
e2efd130 | 271 | struct i915_gem_context *ctx; |
40521054 | 272 | |
bf9e8429 | 273 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
40521054 | 274 | |
bf9e8429 | 275 | ctx = __create_hw_context(dev_priv, file_priv); |
146937e5 | 276 | if (IS_ERR(ctx)) |
a45d0f6a | 277 | return ctx; |
40521054 | 278 | |
bf9e8429 | 279 | if (USES_FULL_PPGTT(dev_priv)) { |
80b204bc | 280 | struct i915_hw_ppgtt *ppgtt; |
bdf4fd7e | 281 | |
bf9e8429 | 282 | ppgtt = i915_ppgtt_create(dev_priv, file_priv, ctx->name); |
c6aab916 | 283 | if (IS_ERR(ppgtt)) { |
0eea67eb BW |
284 | DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n", |
285 | PTR_ERR(ppgtt)); | |
6d1f9fb3 | 286 | __destroy_hw_context(ctx, file_priv); |
c6aab916 | 287 | return ERR_CAST(ppgtt); |
ae6c4806 DV |
288 | } |
289 | ||
290 | ctx->ppgtt = ppgtt; | |
949e8ab3 | 291 | ctx->desc_template = default_desc_template(dev_priv, ppgtt); |
ae6c4806 | 292 | } |
bdf4fd7e | 293 | |
198c974d DCS |
294 | trace_i915_context_create(ctx); |
295 | ||
a45d0f6a | 296 | return ctx; |
254f965c BW |
297 | } |
298 | ||
c8c35799 ZW |
299 | /** |
300 | * i915_gem_context_create_gvt - create a GVT GEM context | |
301 | * @dev: drm device * | |
302 | * | |
303 | * This function is used to create a GVT specific GEM context. | |
304 | * | |
305 | * Returns: | |
306 | * pointer to i915_gem_context on success, error pointer if failed | |
307 | * | |
308 | */ | |
309 | struct i915_gem_context * | |
310 | i915_gem_context_create_gvt(struct drm_device *dev) | |
311 | { | |
312 | struct i915_gem_context *ctx; | |
313 | int ret; | |
314 | ||
315 | if (!IS_ENABLED(CONFIG_DRM_I915_GVT)) | |
316 | return ERR_PTR(-ENODEV); | |
317 | ||
318 | ret = i915_mutex_lock_interruptible(dev); | |
319 | if (ret) | |
320 | return ERR_PTR(ret); | |
321 | ||
984ff29f | 322 | ctx = __create_hw_context(to_i915(dev), NULL); |
c8c35799 ZW |
323 | if (IS_ERR(ctx)) |
324 | goto out; | |
325 | ||
984ff29f | 326 | ctx->file_priv = ERR_PTR(-EBADF); |
6095868a CW |
327 | i915_gem_context_set_closed(ctx); /* not user accessible */ |
328 | i915_gem_context_clear_bannable(ctx); | |
329 | i915_gem_context_set_force_single_submission(ctx); | |
718e884a CD |
330 | if (!i915.enable_guc_submission) |
331 | ctx->ring_size = 512 * PAGE_SIZE; /* Max ring buffer size */ | |
984ff29f CW |
332 | |
333 | GEM_BUG_ON(i915_gem_context_is_kernel(ctx)); | |
c8c35799 ZW |
334 | out: |
335 | mutex_unlock(&dev->struct_mutex); | |
336 | return ctx; | |
337 | } | |
338 | ||
bf9e8429 | 339 | int i915_gem_context_init(struct drm_i915_private *dev_priv) |
254f965c | 340 | { |
e2efd130 | 341 | struct i915_gem_context *ctx; |
254f965c | 342 | |
2fa48d8d BW |
343 | /* Init should only be called once per module load. Eventually the |
344 | * restriction on the context_disabled check can be loosened. */ | |
ed54c1a1 | 345 | if (WARN_ON(dev_priv->kernel_context)) |
8245be31 | 346 | return 0; |
254f965c | 347 | |
c033666a CW |
348 | if (intel_vgpu_active(dev_priv) && |
349 | HAS_LOGICAL_RING_CONTEXTS(dev_priv)) { | |
a0bd6c31 ZL |
350 | if (!i915.enable_execlists) { |
351 | DRM_INFO("Only EXECLIST mode is supported in vgpu.\n"); | |
352 | return -EINVAL; | |
353 | } | |
354 | } | |
355 | ||
5d1808ec CW |
356 | /* Using the simple ida interface, the max is limited by sizeof(int) */ |
357 | BUILD_BUG_ON(MAX_CONTEXT_HW_ID > INT_MAX); | |
358 | ida_init(&dev_priv->context_hw_ida); | |
359 | ||
bf9e8429 | 360 | ctx = i915_gem_create_context(dev_priv, NULL); |
691e6415 CW |
361 | if (IS_ERR(ctx)) { |
362 | DRM_ERROR("Failed to create default global context (error %ld)\n", | |
363 | PTR_ERR(ctx)); | |
364 | return PTR_ERR(ctx); | |
254f965c BW |
365 | } |
366 | ||
5d12fcef CW |
367 | /* For easy recognisablity, we want the kernel context to be 0 and then |
368 | * all user contexts will have non-zero hw_id. | |
369 | */ | |
370 | GEM_BUG_ON(ctx->hw_id); | |
371 | ||
6095868a | 372 | i915_gem_context_clear_bannable(ctx); |
9f792eba | 373 | ctx->priority = I915_PRIORITY_MIN; /* lowest priority; idle task */ |
ed54c1a1 | 374 | dev_priv->kernel_context = ctx; |
67e3d297 | 375 | |
984ff29f CW |
376 | GEM_BUG_ON(!i915_gem_context_is_kernel(ctx)); |
377 | ||
ede7d42b | 378 | DRM_DEBUG_DRIVER("%s context support initialized\n", |
63ffbcda JL |
379 | dev_priv->engine[RCS]->context_size ? "logical" : |
380 | "fake"); | |
8245be31 | 381 | return 0; |
254f965c BW |
382 | } |
383 | ||
b2e862d0 CW |
384 | void i915_gem_context_lost(struct drm_i915_private *dev_priv) |
385 | { | |
386 | struct intel_engine_cs *engine; | |
3b3f1650 | 387 | enum intel_engine_id id; |
b2e862d0 | 388 | |
91c8a326 | 389 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
499f2697 | 390 | |
3b3f1650 | 391 | for_each_engine(engine, dev_priv, id) { |
e8a9c58f CW |
392 | engine->legacy_active_context = NULL; |
393 | ||
394 | if (!engine->last_retired_context) | |
395 | continue; | |
396 | ||
397 | engine->context_unpin(engine, engine->last_retired_context); | |
398 | engine->last_retired_context = NULL; | |
b2e862d0 CW |
399 | } |
400 | ||
c7c3c07d CW |
401 | /* Force the GPU state to be restored on enabling */ |
402 | if (!i915.enable_execlists) { | |
a168b2d8 CW |
403 | struct i915_gem_context *ctx; |
404 | ||
405 | list_for_each_entry(ctx, &dev_priv->context_list, link) { | |
406 | if (!i915_gem_context_is_default(ctx)) | |
407 | continue; | |
408 | ||
3b3f1650 | 409 | for_each_engine(engine, dev_priv, id) |
a168b2d8 CW |
410 | ctx->engine[engine->id].initialised = false; |
411 | ||
412 | ctx->remap_slice = ALL_L3_SLICES(dev_priv); | |
413 | } | |
414 | ||
3b3f1650 | 415 | for_each_engine(engine, dev_priv, id) { |
c7c3c07d CW |
416 | struct intel_context *kce = |
417 | &dev_priv->kernel_context->engine[engine->id]; | |
418 | ||
419 | kce->initialised = true; | |
420 | } | |
421 | } | |
b2e862d0 CW |
422 | } |
423 | ||
cb15d9f8 | 424 | void i915_gem_context_fini(struct drm_i915_private *dev_priv) |
254f965c | 425 | { |
e2efd130 | 426 | struct i915_gem_context *dctx = dev_priv->kernel_context; |
b2e862d0 | 427 | |
cb15d9f8 | 428 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
499f2697 | 429 | |
984ff29f CW |
430 | GEM_BUG_ON(!i915_gem_context_is_kernel(dctx)); |
431 | ||
50e046b6 | 432 | context_close(dctx); |
ed54c1a1 | 433 | dev_priv->kernel_context = NULL; |
5d1808ec CW |
434 | |
435 | ida_destroy(&dev_priv->context_hw_ida); | |
254f965c BW |
436 | } |
437 | ||
40521054 BW |
438 | static int context_idr_cleanup(int id, void *p, void *data) |
439 | { | |
e2efd130 | 440 | struct i915_gem_context *ctx = p; |
40521054 | 441 | |
50e046b6 | 442 | context_close(ctx); |
40521054 | 443 | return 0; |
254f965c BW |
444 | } |
445 | ||
e422b888 BW |
446 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file) |
447 | { | |
448 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
e2efd130 | 449 | struct i915_gem_context *ctx; |
e422b888 BW |
450 | |
451 | idr_init(&file_priv->context_idr); | |
452 | ||
0eea67eb | 453 | mutex_lock(&dev->struct_mutex); |
bf9e8429 | 454 | ctx = i915_gem_create_context(to_i915(dev), file_priv); |
0eea67eb BW |
455 | mutex_unlock(&dev->struct_mutex); |
456 | ||
984ff29f CW |
457 | GEM_BUG_ON(i915_gem_context_is_kernel(ctx)); |
458 | ||
f83d6518 | 459 | if (IS_ERR(ctx)) { |
0eea67eb | 460 | idr_destroy(&file_priv->context_idr); |
f83d6518 | 461 | return PTR_ERR(ctx); |
0eea67eb BW |
462 | } |
463 | ||
e422b888 BW |
464 | return 0; |
465 | } | |
466 | ||
254f965c BW |
467 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file) |
468 | { | |
40521054 | 469 | struct drm_i915_file_private *file_priv = file->driver_priv; |
254f965c | 470 | |
499f2697 CW |
471 | lockdep_assert_held(&dev->struct_mutex); |
472 | ||
73c273eb | 473 | idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL); |
40521054 | 474 | idr_destroy(&file_priv->context_idr); |
40521054 BW |
475 | } |
476 | ||
e0556841 | 477 | static inline int |
e555e326 | 478 | mi_set_context(struct drm_i915_gem_request *req, u32 flags) |
e0556841 | 479 | { |
c033666a | 480 | struct drm_i915_private *dev_priv = req->i915; |
4a570db5 | 481 | struct intel_engine_cs *engine = req->engine; |
3b3f1650 | 482 | enum intel_engine_id id; |
2c550183 | 483 | const int num_rings = |
e02d9d76 CW |
484 | /* Use an extended w/a on gen7 if signalling from other rings */ |
485 | (i915.semaphores && INTEL_GEN(dev_priv) == 7) ? | |
c1bb1145 | 486 | INTEL_INFO(dev_priv)->num_rings - 1 : |
2c550183 | 487 | 0; |
a937eaf8 | 488 | int len; |
e555e326 | 489 | u32 *cs; |
e0556841 | 490 | |
e555e326 | 491 | flags |= MI_MM_SPACE_GTT; |
c033666a | 492 | if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) |
e555e326 CW |
493 | /* These flags are for resource streamer on HSW+ */ |
494 | flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN; | |
495 | else | |
496 | flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN; | |
2c550183 CW |
497 | |
498 | len = 4; | |
c033666a | 499 | if (INTEL_GEN(dev_priv) >= 7) |
e9135c4f | 500 | len += 2 + (num_rings ? 4*num_rings + 6 : 0); |
2c550183 | 501 | |
73dec95e TU |
502 | cs = intel_ring_begin(req, len); |
503 | if (IS_ERR(cs)) | |
504 | return PTR_ERR(cs); | |
e0556841 | 505 | |
b3f797ac | 506 | /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ |
c033666a | 507 | if (INTEL_GEN(dev_priv) >= 7) { |
73dec95e | 508 | *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; |
2c550183 CW |
509 | if (num_rings) { |
510 | struct intel_engine_cs *signaller; | |
511 | ||
73dec95e | 512 | *cs++ = MI_LOAD_REGISTER_IMM(num_rings); |
3b3f1650 | 513 | for_each_engine(signaller, dev_priv, id) { |
e2f80391 | 514 | if (signaller == engine) |
2c550183 CW |
515 | continue; |
516 | ||
73dec95e TU |
517 | *cs++ = i915_mmio_reg_offset( |
518 | RING_PSMI_CTL(signaller->mmio_base)); | |
519 | *cs++ = _MASKED_BIT_ENABLE( | |
520 | GEN6_PSMI_SLEEP_MSG_DISABLE); | |
2c550183 CW |
521 | } |
522 | } | |
523 | } | |
e37ec39b | 524 | |
73dec95e TU |
525 | *cs++ = MI_NOOP; |
526 | *cs++ = MI_SET_CONTEXT; | |
527 | *cs++ = i915_ggtt_offset(req->ctx->engine[RCS].state) | flags; | |
2b7e8082 VS |
528 | /* |
529 | * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP | |
530 | * WaMiSetContext_Hang:snb,ivb,vlv | |
531 | */ | |
73dec95e | 532 | *cs++ = MI_NOOP; |
e0556841 | 533 | |
c033666a | 534 | if (INTEL_GEN(dev_priv) >= 7) { |
2c550183 CW |
535 | if (num_rings) { |
536 | struct intel_engine_cs *signaller; | |
e9135c4f | 537 | i915_reg_t last_reg = {}; /* keep gcc quiet */ |
2c550183 | 538 | |
73dec95e | 539 | *cs++ = MI_LOAD_REGISTER_IMM(num_rings); |
3b3f1650 | 540 | for_each_engine(signaller, dev_priv, id) { |
e2f80391 | 541 | if (signaller == engine) |
2c550183 CW |
542 | continue; |
543 | ||
e9135c4f | 544 | last_reg = RING_PSMI_CTL(signaller->mmio_base); |
73dec95e TU |
545 | *cs++ = i915_mmio_reg_offset(last_reg); |
546 | *cs++ = _MASKED_BIT_DISABLE( | |
547 | GEN6_PSMI_SLEEP_MSG_DISABLE); | |
2c550183 | 548 | } |
e9135c4f CW |
549 | |
550 | /* Insert a delay before the next switch! */ | |
73dec95e TU |
551 | *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; |
552 | *cs++ = i915_mmio_reg_offset(last_reg); | |
553 | *cs++ = i915_ggtt_offset(engine->scratch); | |
554 | *cs++ = MI_NOOP; | |
2c550183 | 555 | } |
73dec95e | 556 | *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; |
2c550183 | 557 | } |
e37ec39b | 558 | |
73dec95e | 559 | intel_ring_advance(req, cs); |
e0556841 | 560 | |
a937eaf8 | 561 | return 0; |
e0556841 BW |
562 | } |
563 | ||
d200cda6 | 564 | static int remap_l3(struct drm_i915_gem_request *req, int slice) |
b0ebde39 | 565 | { |
73dec95e TU |
566 | u32 *cs, *remap_info = req->i915->l3_parity.remap_info[slice]; |
567 | int i; | |
b0ebde39 | 568 | |
ff55b5e8 | 569 | if (!remap_info) |
b0ebde39 CW |
570 | return 0; |
571 | ||
73dec95e TU |
572 | cs = intel_ring_begin(req, GEN7_L3LOG_SIZE/4 * 2 + 2); |
573 | if (IS_ERR(cs)) | |
574 | return PTR_ERR(cs); | |
b0ebde39 CW |
575 | |
576 | /* | |
577 | * Note: We do not worry about the concurrent register cacheline hang | |
578 | * here because no other code should access these registers other than | |
579 | * at initialization time. | |
580 | */ | |
73dec95e | 581 | *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4); |
ff55b5e8 | 582 | for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) { |
73dec95e TU |
583 | *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i)); |
584 | *cs++ = remap_info[i]; | |
b0ebde39 | 585 | } |
73dec95e TU |
586 | *cs++ = MI_NOOP; |
587 | intel_ring_advance(req, cs); | |
b0ebde39 | 588 | |
ff55b5e8 | 589 | return 0; |
b0ebde39 CW |
590 | } |
591 | ||
f9326be5 CW |
592 | static inline bool skip_rcs_switch(struct i915_hw_ppgtt *ppgtt, |
593 | struct intel_engine_cs *engine, | |
e2efd130 | 594 | struct i915_gem_context *to) |
317b4e90 | 595 | { |
563222a7 BW |
596 | if (to->remap_slice) |
597 | return false; | |
598 | ||
bca44d80 | 599 | if (!to->engine[RCS].initialised) |
fcb5106d CW |
600 | return false; |
601 | ||
f9326be5 | 602 | if (ppgtt && (intel_engine_flag(engine) & ppgtt->pd_dirty_rings)) |
fcb5106d | 603 | return false; |
317b4e90 | 604 | |
e8a9c58f | 605 | return to == engine->legacy_active_context; |
317b4e90 BW |
606 | } |
607 | ||
608 | static bool | |
f9326be5 CW |
609 | needs_pd_load_pre(struct i915_hw_ppgtt *ppgtt, |
610 | struct intel_engine_cs *engine, | |
e2efd130 | 611 | struct i915_gem_context *to) |
317b4e90 | 612 | { |
f9326be5 | 613 | if (!ppgtt) |
317b4e90 BW |
614 | return false; |
615 | ||
f9326be5 | 616 | /* Always load the ppgtt on first use */ |
e8a9c58f | 617 | if (!engine->legacy_active_context) |
f9326be5 CW |
618 | return true; |
619 | ||
620 | /* Same context without new entries, skip */ | |
e8a9c58f | 621 | if (engine->legacy_active_context == to && |
f9326be5 | 622 | !(intel_engine_flag(engine) & ppgtt->pd_dirty_rings)) |
e1a8daa2 CW |
623 | return false; |
624 | ||
625 | if (engine->id != RCS) | |
317b4e90 BW |
626 | return true; |
627 | ||
c033666a | 628 | if (INTEL_GEN(engine->i915) < 8) |
317b4e90 BW |
629 | return true; |
630 | ||
631 | return false; | |
632 | } | |
633 | ||
634 | static bool | |
f9326be5 | 635 | needs_pd_load_post(struct i915_hw_ppgtt *ppgtt, |
e2efd130 | 636 | struct i915_gem_context *to, |
f9326be5 | 637 | u32 hw_flags) |
317b4e90 | 638 | { |
f9326be5 | 639 | if (!ppgtt) |
317b4e90 BW |
640 | return false; |
641 | ||
fcb5106d | 642 | if (!IS_GEN8(to->i915)) |
317b4e90 BW |
643 | return false; |
644 | ||
6702cf16 | 645 | if (hw_flags & MI_RESTORE_INHIBIT) |
317b4e90 BW |
646 | return true; |
647 | ||
648 | return false; | |
649 | } | |
650 | ||
e1a8daa2 | 651 | static int do_rcs_switch(struct drm_i915_gem_request *req) |
e0556841 | 652 | { |
e2efd130 | 653 | struct i915_gem_context *to = req->ctx; |
4a570db5 | 654 | struct intel_engine_cs *engine = req->engine; |
f9326be5 | 655 | struct i915_hw_ppgtt *ppgtt = to->ppgtt ?: req->i915->mm.aliasing_ppgtt; |
e8a9c58f | 656 | struct i915_gem_context *from = engine->legacy_active_context; |
fcb5106d | 657 | u32 hw_flags; |
3ccfd19d | 658 | int ret, i; |
e0556841 | 659 | |
e8a9c58f CW |
660 | GEM_BUG_ON(engine->id != RCS); |
661 | ||
f9326be5 | 662 | if (skip_rcs_switch(ppgtt, engine, to)) |
9a3b5304 CW |
663 | return 0; |
664 | ||
f9326be5 | 665 | if (needs_pd_load_pre(ppgtt, engine, to)) { |
fcb5106d CW |
666 | /* Older GENs and non render rings still want the load first, |
667 | * "PP_DCLV followed by PP_DIR_BASE register through Load | |
668 | * Register Immediate commands in Ring Buffer before submitting | |
669 | * a context."*/ | |
670 | trace_switch_mm(engine, to); | |
f9326be5 | 671 | ret = ppgtt->switch_mm(ppgtt, req); |
fcb5106d | 672 | if (ret) |
e8a9c58f | 673 | return ret; |
fcb5106d CW |
674 | } |
675 | ||
bca44d80 | 676 | if (!to->engine[RCS].initialised || i915_gem_context_is_default(to)) |
6702cf16 BW |
677 | /* NB: If we inhibit the restore, the context is not allowed to |
678 | * die because future work may end up depending on valid address | |
679 | * space. This means we must enforce that a page table load | |
680 | * occur when this occurs. */ | |
fcb5106d | 681 | hw_flags = MI_RESTORE_INHIBIT; |
f9326be5 | 682 | else if (ppgtt && intel_engine_flag(engine) & ppgtt->pd_dirty_rings) |
fcb5106d CW |
683 | hw_flags = MI_FORCE_RESTORE; |
684 | else | |
685 | hw_flags = 0; | |
e0556841 | 686 | |
fcb5106d CW |
687 | if (to != from || (hw_flags & MI_FORCE_RESTORE)) { |
688 | ret = mi_set_context(req, hw_flags); | |
3ccfd19d | 689 | if (ret) |
e8a9c58f | 690 | return ret; |
3ccfd19d | 691 | |
e8a9c58f | 692 | engine->legacy_active_context = to; |
e0556841 | 693 | } |
e0556841 | 694 | |
fcb5106d CW |
695 | /* GEN8 does *not* require an explicit reload if the PDPs have been |
696 | * setup, and we do not wish to move them. | |
697 | */ | |
f9326be5 | 698 | if (needs_pd_load_post(ppgtt, to, hw_flags)) { |
fcb5106d | 699 | trace_switch_mm(engine, to); |
f9326be5 | 700 | ret = ppgtt->switch_mm(ppgtt, req); |
fcb5106d CW |
701 | /* The hardware context switch is emitted, but we haven't |
702 | * actually changed the state - so it's probably safe to bail | |
703 | * here. Still, let the user know something dangerous has | |
704 | * happened. | |
705 | */ | |
706 | if (ret) | |
707 | return ret; | |
708 | } | |
709 | ||
f9326be5 CW |
710 | if (ppgtt) |
711 | ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); | |
fcb5106d CW |
712 | |
713 | for (i = 0; i < MAX_L3_SLICES; i++) { | |
714 | if (!(to->remap_slice & (1<<i))) | |
715 | continue; | |
716 | ||
d200cda6 | 717 | ret = remap_l3(req, i); |
fcb5106d CW |
718 | if (ret) |
719 | return ret; | |
720 | ||
721 | to->remap_slice &= ~(1<<i); | |
722 | } | |
723 | ||
bca44d80 | 724 | if (!to->engine[RCS].initialised) { |
e2f80391 TU |
725 | if (engine->init_context) { |
726 | ret = engine->init_context(req); | |
86d7f238 | 727 | if (ret) |
fcb5106d | 728 | return ret; |
86d7f238 | 729 | } |
bca44d80 | 730 | to->engine[RCS].initialised = true; |
46470fc9 MK |
731 | } |
732 | ||
e0556841 BW |
733 | return 0; |
734 | } | |
735 | ||
736 | /** | |
737 | * i915_switch_context() - perform a GPU context switch. | |
ba01cc93 | 738 | * @req: request for which we'll execute the context switch |
e0556841 BW |
739 | * |
740 | * The context life cycle is simple. The context refcount is incremented and | |
741 | * decremented by 1 and create and destroy. If the context is in use by the GPU, | |
ecdb5fd8 | 742 | * it will have a refcount > 1. This allows us to destroy the context abstract |
e0556841 | 743 | * object while letting the normal object tracking destroy the backing BO. |
ecdb5fd8 TD |
744 | * |
745 | * This function should not be used in execlists mode. Instead the context is | |
746 | * switched by writing to the ELSP and requests keep a reference to their | |
747 | * context. | |
e0556841 | 748 | */ |
ba01cc93 | 749 | int i915_switch_context(struct drm_i915_gem_request *req) |
e0556841 | 750 | { |
4a570db5 | 751 | struct intel_engine_cs *engine = req->engine; |
e0556841 | 752 | |
91c8a326 | 753 | lockdep_assert_held(&req->i915->drm.struct_mutex); |
5b043f4e CW |
754 | if (i915.enable_execlists) |
755 | return 0; | |
0eea67eb | 756 | |
bca44d80 | 757 | if (!req->ctx->engine[engine->id].state) { |
e2efd130 | 758 | struct i915_gem_context *to = req->ctx; |
f9326be5 CW |
759 | struct i915_hw_ppgtt *ppgtt = |
760 | to->ppgtt ?: req->i915->mm.aliasing_ppgtt; | |
e1a8daa2 | 761 | |
f9326be5 | 762 | if (needs_pd_load_pre(ppgtt, engine, to)) { |
e1a8daa2 CW |
763 | int ret; |
764 | ||
765 | trace_switch_mm(engine, to); | |
f9326be5 | 766 | ret = ppgtt->switch_mm(ppgtt, req); |
e1a8daa2 CW |
767 | if (ret) |
768 | return ret; | |
769 | ||
f9326be5 | 770 | ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); |
e1a8daa2 CW |
771 | } |
772 | ||
c482972a | 773 | return 0; |
a95f6a00 | 774 | } |
c482972a | 775 | |
e1a8daa2 | 776 | return do_rcs_switch(req); |
e0556841 | 777 | } |
84624813 | 778 | |
f131e356 CW |
779 | static bool engine_has_kernel_context(struct intel_engine_cs *engine) |
780 | { | |
781 | struct i915_gem_timeline *timeline; | |
782 | ||
783 | list_for_each_entry(timeline, &engine->i915->gt.timelines, link) { | |
784 | struct intel_timeline *tl; | |
785 | ||
786 | if (timeline == &engine->i915->gt.global_timeline) | |
787 | continue; | |
788 | ||
789 | tl = &timeline->engine[engine->id]; | |
790 | if (i915_gem_active_peek(&tl->last_request, | |
791 | &engine->i915->drm.struct_mutex)) | |
792 | return false; | |
793 | } | |
794 | ||
795 | return (!engine->last_retired_context || | |
796 | i915_gem_context_is_kernel(engine->last_retired_context)); | |
797 | } | |
798 | ||
945657b4 CW |
799 | int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv) |
800 | { | |
801 | struct intel_engine_cs *engine; | |
3033acab | 802 | struct i915_gem_timeline *timeline; |
3b3f1650 | 803 | enum intel_engine_id id; |
945657b4 | 804 | |
3033acab CW |
805 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
806 | ||
f131e356 CW |
807 | i915_gem_retire_requests(dev_priv); |
808 | ||
3b3f1650 | 809 | for_each_engine(engine, dev_priv, id) { |
945657b4 CW |
810 | struct drm_i915_gem_request *req; |
811 | int ret; | |
812 | ||
f131e356 CW |
813 | if (engine_has_kernel_context(engine)) |
814 | continue; | |
815 | ||
945657b4 CW |
816 | req = i915_gem_request_alloc(engine, dev_priv->kernel_context); |
817 | if (IS_ERR(req)) | |
818 | return PTR_ERR(req); | |
819 | ||
3033acab CW |
820 | /* Queue this switch after all other activity */ |
821 | list_for_each_entry(timeline, &dev_priv->gt.timelines, link) { | |
822 | struct drm_i915_gem_request *prev; | |
823 | struct intel_timeline *tl; | |
824 | ||
825 | tl = &timeline->engine[engine->id]; | |
826 | prev = i915_gem_active_raw(&tl->last_request, | |
827 | &dev_priv->drm.struct_mutex); | |
828 | if (prev) | |
829 | i915_sw_fence_await_sw_fence_gfp(&req->submit, | |
830 | &prev->submit, | |
831 | GFP_KERNEL); | |
832 | } | |
833 | ||
5b043f4e | 834 | ret = i915_switch_context(req); |
e642c85b | 835 | i915_add_request(req); |
945657b4 CW |
836 | if (ret) |
837 | return ret; | |
838 | } | |
839 | ||
840 | return 0; | |
841 | } | |
842 | ||
b083a087 MK |
843 | static bool client_is_banned(struct drm_i915_file_private *file_priv) |
844 | { | |
845 | return file_priv->context_bans > I915_MAX_CLIENT_CONTEXT_BANS; | |
846 | } | |
847 | ||
84624813 BW |
848 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
849 | struct drm_file *file) | |
850 | { | |
63ffbcda | 851 | struct drm_i915_private *dev_priv = to_i915(dev); |
84624813 BW |
852 | struct drm_i915_gem_context_create *args = data; |
853 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
e2efd130 | 854 | struct i915_gem_context *ctx; |
84624813 BW |
855 | int ret; |
856 | ||
63ffbcda | 857 | if (!dev_priv->engine[RCS]->context_size) |
5fa8be65 DV |
858 | return -ENODEV; |
859 | ||
b31e5136 CW |
860 | if (args->pad != 0) |
861 | return -EINVAL; | |
862 | ||
b083a087 MK |
863 | if (client_is_banned(file_priv)) { |
864 | DRM_DEBUG("client %s[%d] banned from creating ctx\n", | |
865 | current->comm, | |
866 | pid_nr(get_task_pid(current, PIDTYPE_PID))); | |
867 | ||
868 | return -EIO; | |
869 | } | |
870 | ||
84624813 BW |
871 | ret = i915_mutex_lock_interruptible(dev); |
872 | if (ret) | |
873 | return ret; | |
874 | ||
63ffbcda | 875 | ctx = i915_gem_create_context(dev_priv, file_priv); |
84624813 | 876 | mutex_unlock(&dev->struct_mutex); |
be636387 DC |
877 | if (IS_ERR(ctx)) |
878 | return PTR_ERR(ctx); | |
84624813 | 879 | |
984ff29f CW |
880 | GEM_BUG_ON(i915_gem_context_is_kernel(ctx)); |
881 | ||
821d66dd | 882 | args->ctx_id = ctx->user_handle; |
b84cf536 | 883 | DRM_DEBUG("HW context %d created\n", args->ctx_id); |
84624813 | 884 | |
be636387 | 885 | return 0; |
84624813 BW |
886 | } |
887 | ||
888 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
889 | struct drm_file *file) | |
890 | { | |
891 | struct drm_i915_gem_context_destroy *args = data; | |
892 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
e2efd130 | 893 | struct i915_gem_context *ctx; |
84624813 BW |
894 | int ret; |
895 | ||
b31e5136 CW |
896 | if (args->pad != 0) |
897 | return -EINVAL; | |
898 | ||
821d66dd | 899 | if (args->ctx_id == DEFAULT_CONTEXT_HANDLE) |
c2cf2416 | 900 | return -ENOENT; |
0eea67eb | 901 | |
84624813 BW |
902 | ret = i915_mutex_lock_interruptible(dev); |
903 | if (ret) | |
904 | return ret; | |
905 | ||
ca585b5d | 906 | ctx = i915_gem_context_lookup(file_priv, args->ctx_id); |
72ad5c45 | 907 | if (IS_ERR(ctx)) { |
84624813 | 908 | mutex_unlock(&dev->struct_mutex); |
72ad5c45 | 909 | return PTR_ERR(ctx); |
84624813 BW |
910 | } |
911 | ||
6d1f9fb3 | 912 | __destroy_hw_context(ctx, file_priv); |
84624813 BW |
913 | mutex_unlock(&dev->struct_mutex); |
914 | ||
b84cf536 | 915 | DRM_DEBUG("HW context %d destroyed\n", args->ctx_id); |
84624813 BW |
916 | return 0; |
917 | } | |
c9dc0f35 CW |
918 | |
919 | int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, | |
920 | struct drm_file *file) | |
921 | { | |
922 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
923 | struct drm_i915_gem_context_param *args = data; | |
e2efd130 | 924 | struct i915_gem_context *ctx; |
c9dc0f35 CW |
925 | int ret; |
926 | ||
927 | ret = i915_mutex_lock_interruptible(dev); | |
928 | if (ret) | |
929 | return ret; | |
930 | ||
ca585b5d | 931 | ctx = i915_gem_context_lookup(file_priv, args->ctx_id); |
c9dc0f35 CW |
932 | if (IS_ERR(ctx)) { |
933 | mutex_unlock(&dev->struct_mutex); | |
934 | return PTR_ERR(ctx); | |
935 | } | |
936 | ||
937 | args->size = 0; | |
938 | switch (args->param) { | |
939 | case I915_CONTEXT_PARAM_BAN_PERIOD: | |
84102171 | 940 | ret = -EINVAL; |
c9dc0f35 | 941 | break; |
b1b38278 DW |
942 | case I915_CONTEXT_PARAM_NO_ZEROMAP: |
943 | args->value = ctx->flags & CONTEXT_NO_ZEROMAP; | |
944 | break; | |
fa8848f2 CW |
945 | case I915_CONTEXT_PARAM_GTT_SIZE: |
946 | if (ctx->ppgtt) | |
947 | args->value = ctx->ppgtt->base.total; | |
948 | else if (to_i915(dev)->mm.aliasing_ppgtt) | |
949 | args->value = to_i915(dev)->mm.aliasing_ppgtt->base.total; | |
950 | else | |
62106b4f | 951 | args->value = to_i915(dev)->ggtt.base.total; |
fa8848f2 | 952 | break; |
bc3d6744 | 953 | case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE: |
6095868a | 954 | args->value = i915_gem_context_no_error_capture(ctx); |
bc3d6744 | 955 | break; |
84102171 | 956 | case I915_CONTEXT_PARAM_BANNABLE: |
6095868a | 957 | args->value = i915_gem_context_is_bannable(ctx); |
84102171 | 958 | break; |
c9dc0f35 CW |
959 | default: |
960 | ret = -EINVAL; | |
961 | break; | |
962 | } | |
963 | mutex_unlock(&dev->struct_mutex); | |
964 | ||
965 | return ret; | |
966 | } | |
967 | ||
968 | int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, | |
969 | struct drm_file *file) | |
970 | { | |
971 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
972 | struct drm_i915_gem_context_param *args = data; | |
e2efd130 | 973 | struct i915_gem_context *ctx; |
c9dc0f35 CW |
974 | int ret; |
975 | ||
976 | ret = i915_mutex_lock_interruptible(dev); | |
977 | if (ret) | |
978 | return ret; | |
979 | ||
ca585b5d | 980 | ctx = i915_gem_context_lookup(file_priv, args->ctx_id); |
c9dc0f35 CW |
981 | if (IS_ERR(ctx)) { |
982 | mutex_unlock(&dev->struct_mutex); | |
983 | return PTR_ERR(ctx); | |
984 | } | |
985 | ||
986 | switch (args->param) { | |
987 | case I915_CONTEXT_PARAM_BAN_PERIOD: | |
84102171 | 988 | ret = -EINVAL; |
c9dc0f35 | 989 | break; |
b1b38278 DW |
990 | case I915_CONTEXT_PARAM_NO_ZEROMAP: |
991 | if (args->size) { | |
992 | ret = -EINVAL; | |
993 | } else { | |
994 | ctx->flags &= ~CONTEXT_NO_ZEROMAP; | |
995 | ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0; | |
bc3d6744 CW |
996 | } |
997 | break; | |
998 | case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE: | |
6095868a | 999 | if (args->size) |
bc3d6744 | 1000 | ret = -EINVAL; |
6095868a CW |
1001 | else if (args->value) |
1002 | i915_gem_context_set_no_error_capture(ctx); | |
1003 | else | |
1004 | i915_gem_context_clear_no_error_capture(ctx); | |
b1b38278 | 1005 | break; |
84102171 MK |
1006 | case I915_CONTEXT_PARAM_BANNABLE: |
1007 | if (args->size) | |
1008 | ret = -EINVAL; | |
1009 | else if (!capable(CAP_SYS_ADMIN) && !args->value) | |
1010 | ret = -EPERM; | |
6095868a CW |
1011 | else if (args->value) |
1012 | i915_gem_context_set_bannable(ctx); | |
84102171 | 1013 | else |
6095868a | 1014 | i915_gem_context_clear_bannable(ctx); |
84102171 | 1015 | break; |
c9dc0f35 CW |
1016 | default: |
1017 | ret = -EINVAL; | |
1018 | break; | |
1019 | } | |
1020 | mutex_unlock(&dev->struct_mutex); | |
1021 | ||
1022 | return ret; | |
1023 | } | |
d538704b CW |
1024 | |
1025 | int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, | |
1026 | void *data, struct drm_file *file) | |
1027 | { | |
fac5e23e | 1028 | struct drm_i915_private *dev_priv = to_i915(dev); |
d538704b | 1029 | struct drm_i915_reset_stats *args = data; |
e2efd130 | 1030 | struct i915_gem_context *ctx; |
d538704b CW |
1031 | int ret; |
1032 | ||
1033 | if (args->flags || args->pad) | |
1034 | return -EINVAL; | |
1035 | ||
1036 | if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN)) | |
1037 | return -EPERM; | |
1038 | ||
bdb04614 | 1039 | ret = i915_mutex_lock_interruptible(dev); |
d538704b CW |
1040 | if (ret) |
1041 | return ret; | |
1042 | ||
ca585b5d | 1043 | ctx = i915_gem_context_lookup(file->driver_priv, args->ctx_id); |
d538704b CW |
1044 | if (IS_ERR(ctx)) { |
1045 | mutex_unlock(&dev->struct_mutex); | |
1046 | return PTR_ERR(ctx); | |
1047 | } | |
d538704b CW |
1048 | |
1049 | if (capable(CAP_SYS_ADMIN)) | |
1050 | args->reset_count = i915_reset_count(&dev_priv->gpu_error); | |
1051 | else | |
1052 | args->reset_count = 0; | |
1053 | ||
bc1d53c6 MK |
1054 | args->batch_active = ctx->guilty_count; |
1055 | args->batch_pending = ctx->active_count; | |
d538704b CW |
1056 | |
1057 | mutex_unlock(&dev->struct_mutex); | |
1058 | ||
1059 | return 0; | |
1060 | } | |
0daf0113 CW |
1061 | |
1062 | #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) | |
1063 | #include "selftests/mock_context.c" | |
791ff39a | 1064 | #include "selftests/i915_gem_context.c" |
0daf0113 | 1065 | #endif |