Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5a0e3ad6 | 34 | #include <linux/slab.h> |
673a394b | 35 | #include <linux/swap.h> |
79e53945 | 36 | #include <linux/pci.h> |
f8f235e5 | 37 | #include <linux/intel-gtt.h> |
673a394b | 38 | |
0108a3ed | 39 | static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj); |
ba3d8d74 DV |
40 | |
41 | static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, | |
42 | bool pipelined); | |
e47c68e9 EA |
43 | static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); |
44 | static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); | |
e47c68e9 EA |
45 | static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, |
46 | int write); | |
47 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
48 | uint64_t offset, | |
49 | uint64_t size); | |
50 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj); | |
2cf34d7b CW |
51 | static int i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
52 | bool interruptible); | |
de151cf6 JB |
53 | static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
54 | unsigned alignment); | |
de151cf6 | 55 | static void i915_gem_clear_fence_reg(struct drm_gem_object *obj); |
71acb5eb DA |
56 | static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
57 | struct drm_i915_gem_pwrite *args, | |
58 | struct drm_file *file_priv); | |
be72615b | 59 | static void i915_gem_free_object_tail(struct drm_gem_object *obj); |
673a394b | 60 | |
5cdf5881 CW |
61 | static int |
62 | i915_gem_object_get_pages(struct drm_gem_object *obj, | |
63 | gfp_t gfpmask); | |
64 | ||
65 | static void | |
66 | i915_gem_object_put_pages(struct drm_gem_object *obj); | |
67 | ||
31169714 CW |
68 | static LIST_HEAD(shrink_list); |
69 | static DEFINE_SPINLOCK(shrink_list_lock); | |
70 | ||
73aa808f CW |
71 | /* some bookkeeping */ |
72 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
73 | size_t size) | |
74 | { | |
75 | dev_priv->mm.object_count++; | |
76 | dev_priv->mm.object_memory += size; | |
77 | } | |
78 | ||
79 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
80 | size_t size) | |
81 | { | |
82 | dev_priv->mm.object_count--; | |
83 | dev_priv->mm.object_memory -= size; | |
84 | } | |
85 | ||
86 | static void i915_gem_info_add_gtt(struct drm_i915_private *dev_priv, | |
87 | size_t size) | |
88 | { | |
89 | dev_priv->mm.gtt_count++; | |
90 | dev_priv->mm.gtt_memory += size; | |
91 | } | |
92 | ||
93 | static void i915_gem_info_remove_gtt(struct drm_i915_private *dev_priv, | |
94 | size_t size) | |
95 | { | |
96 | dev_priv->mm.gtt_count--; | |
97 | dev_priv->mm.gtt_memory -= size; | |
98 | } | |
99 | ||
100 | static void i915_gem_info_add_pin(struct drm_i915_private *dev_priv, | |
101 | size_t size) | |
102 | { | |
103 | dev_priv->mm.pin_count++; | |
104 | dev_priv->mm.pin_memory += size; | |
105 | } | |
106 | ||
107 | static void i915_gem_info_remove_pin(struct drm_i915_private *dev_priv, | |
108 | size_t size) | |
109 | { | |
110 | dev_priv->mm.pin_count--; | |
111 | dev_priv->mm.pin_memory -= size; | |
112 | } | |
113 | ||
30dbf0c0 CW |
114 | int |
115 | i915_gem_check_is_wedged(struct drm_device *dev) | |
116 | { | |
117 | struct drm_i915_private *dev_priv = dev->dev_private; | |
118 | struct completion *x = &dev_priv->error_completion; | |
119 | unsigned long flags; | |
120 | int ret; | |
121 | ||
122 | if (!atomic_read(&dev_priv->mm.wedged)) | |
123 | return 0; | |
124 | ||
125 | ret = wait_for_completion_interruptible(x); | |
126 | if (ret) | |
127 | return ret; | |
128 | ||
129 | /* Success, we reset the GPU! */ | |
130 | if (!atomic_read(&dev_priv->mm.wedged)) | |
131 | return 0; | |
132 | ||
133 | /* GPU is hung, bump the completion count to account for | |
134 | * the token we just consumed so that we never hit zero and | |
135 | * end up waiting upon a subsequent completion event that | |
136 | * will never happen. | |
137 | */ | |
138 | spin_lock_irqsave(&x->wait.lock, flags); | |
139 | x->done++; | |
140 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
141 | return -EIO; | |
142 | } | |
143 | ||
76c1dec1 CW |
144 | static int i915_mutex_lock_interruptible(struct drm_device *dev) |
145 | { | |
146 | struct drm_i915_private *dev_priv = dev->dev_private; | |
147 | int ret; | |
148 | ||
149 | ret = i915_gem_check_is_wedged(dev); | |
150 | if (ret) | |
151 | return ret; | |
152 | ||
153 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
154 | if (ret) | |
155 | return ret; | |
156 | ||
157 | if (atomic_read(&dev_priv->mm.wedged)) { | |
158 | mutex_unlock(&dev->struct_mutex); | |
159 | return -EAGAIN; | |
160 | } | |
161 | ||
23bc5982 | 162 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
163 | return 0; |
164 | } | |
30dbf0c0 | 165 | |
7d1c4804 CW |
166 | static inline bool |
167 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv) | |
168 | { | |
169 | return obj_priv->gtt_space && | |
170 | !obj_priv->active && | |
171 | obj_priv->pin_count == 0; | |
172 | } | |
173 | ||
73aa808f CW |
174 | int i915_gem_do_init(struct drm_device *dev, |
175 | unsigned long start, | |
79e53945 | 176 | unsigned long end) |
673a394b EA |
177 | { |
178 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b | 179 | |
79e53945 JB |
180 | if (start >= end || |
181 | (start & (PAGE_SIZE - 1)) != 0 || | |
182 | (end & (PAGE_SIZE - 1)) != 0) { | |
673a394b EA |
183 | return -EINVAL; |
184 | } | |
185 | ||
79e53945 JB |
186 | drm_mm_init(&dev_priv->mm.gtt_space, start, |
187 | end - start); | |
673a394b | 188 | |
73aa808f | 189 | dev_priv->mm.gtt_total = end - start; |
79e53945 JB |
190 | |
191 | return 0; | |
192 | } | |
673a394b | 193 | |
79e53945 JB |
194 | int |
195 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
196 | struct drm_file *file_priv) | |
197 | { | |
198 | struct drm_i915_gem_init *args = data; | |
199 | int ret; | |
200 | ||
201 | mutex_lock(&dev->struct_mutex); | |
202 | ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end); | |
673a394b EA |
203 | mutex_unlock(&dev->struct_mutex); |
204 | ||
79e53945 | 205 | return ret; |
673a394b EA |
206 | } |
207 | ||
5a125c3c EA |
208 | int |
209 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
210 | struct drm_file *file_priv) | |
211 | { | |
73aa808f | 212 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 213 | struct drm_i915_gem_get_aperture *args = data; |
5a125c3c EA |
214 | |
215 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
216 | return -ENODEV; | |
217 | ||
73aa808f CW |
218 | mutex_lock(&dev->struct_mutex); |
219 | args->aper_size = dev_priv->mm.gtt_total; | |
220 | args->aper_available_size = args->aper_size - dev_priv->mm.pin_memory; | |
221 | mutex_unlock(&dev->struct_mutex); | |
5a125c3c EA |
222 | |
223 | return 0; | |
224 | } | |
225 | ||
673a394b EA |
226 | |
227 | /** | |
228 | * Creates a new mm object and returns a handle to it. | |
229 | */ | |
230 | int | |
231 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
232 | struct drm_file *file_priv) | |
233 | { | |
234 | struct drm_i915_gem_create *args = data; | |
235 | struct drm_gem_object *obj; | |
a1a2d1d3 PP |
236 | int ret; |
237 | u32 handle; | |
673a394b EA |
238 | |
239 | args->size = roundup(args->size, PAGE_SIZE); | |
240 | ||
241 | /* Allocate the new object */ | |
ac52bc56 | 242 | obj = i915_gem_alloc_object(dev, args->size); |
673a394b EA |
243 | if (obj == NULL) |
244 | return -ENOMEM; | |
245 | ||
246 | ret = drm_gem_handle_create(file_priv, obj, &handle); | |
1dfd9754 | 247 | if (ret) { |
202f2fef CW |
248 | drm_gem_object_release(obj); |
249 | i915_gem_info_remove_obj(dev->dev_private, obj->size); | |
250 | kfree(obj); | |
673a394b | 251 | return ret; |
1dfd9754 | 252 | } |
673a394b | 253 | |
202f2fef CW |
254 | /* drop reference from allocate - handle holds it now */ |
255 | drm_gem_object_unreference(obj); | |
256 | trace_i915_gem_object_create(obj); | |
257 | ||
1dfd9754 | 258 | args->handle = handle; |
673a394b EA |
259 | return 0; |
260 | } | |
261 | ||
eb01459f EA |
262 | static inline int |
263 | fast_shmem_read(struct page **pages, | |
264 | loff_t page_base, int page_offset, | |
265 | char __user *data, | |
266 | int length) | |
267 | { | |
2bc43b5c | 268 | int unwritten; |
b5e4feb6 | 269 | char *vaddr; |
eb01459f EA |
270 | |
271 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0); | |
2bc43b5c | 272 | unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length); |
eb01459f EA |
273 | kunmap_atomic(vaddr, KM_USER0); |
274 | ||
b5e4feb6 | 275 | return unwritten ? -EFAULT : 0; |
eb01459f EA |
276 | } |
277 | ||
280b713b EA |
278 | static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj) |
279 | { | |
280 | drm_i915_private_t *dev_priv = obj->dev->dev_private; | |
23010e43 | 281 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
280b713b EA |
282 | |
283 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
284 | obj_priv->tiling_mode != I915_TILING_NONE; | |
285 | } | |
286 | ||
99a03df5 | 287 | static inline void |
40123c1f EA |
288 | slow_shmem_copy(struct page *dst_page, |
289 | int dst_offset, | |
290 | struct page *src_page, | |
291 | int src_offset, | |
292 | int length) | |
293 | { | |
294 | char *dst_vaddr, *src_vaddr; | |
295 | ||
99a03df5 CW |
296 | dst_vaddr = kmap(dst_page); |
297 | src_vaddr = kmap(src_page); | |
40123c1f EA |
298 | |
299 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); | |
300 | ||
99a03df5 CW |
301 | kunmap(src_page); |
302 | kunmap(dst_page); | |
40123c1f EA |
303 | } |
304 | ||
99a03df5 | 305 | static inline void |
280b713b EA |
306 | slow_shmem_bit17_copy(struct page *gpu_page, |
307 | int gpu_offset, | |
308 | struct page *cpu_page, | |
309 | int cpu_offset, | |
310 | int length, | |
311 | int is_read) | |
312 | { | |
313 | char *gpu_vaddr, *cpu_vaddr; | |
314 | ||
315 | /* Use the unswizzled path if this page isn't affected. */ | |
316 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { | |
317 | if (is_read) | |
318 | return slow_shmem_copy(cpu_page, cpu_offset, | |
319 | gpu_page, gpu_offset, length); | |
320 | else | |
321 | return slow_shmem_copy(gpu_page, gpu_offset, | |
322 | cpu_page, cpu_offset, length); | |
323 | } | |
324 | ||
99a03df5 CW |
325 | gpu_vaddr = kmap(gpu_page); |
326 | cpu_vaddr = kmap(cpu_page); | |
280b713b EA |
327 | |
328 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's | |
329 | * XORing with the other bits (A9 for Y, A9 and A10 for X) | |
330 | */ | |
331 | while (length > 0) { | |
332 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
333 | int this_length = min(cacheline_end - gpu_offset, length); | |
334 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
335 | ||
336 | if (is_read) { | |
337 | memcpy(cpu_vaddr + cpu_offset, | |
338 | gpu_vaddr + swizzled_gpu_offset, | |
339 | this_length); | |
340 | } else { | |
341 | memcpy(gpu_vaddr + swizzled_gpu_offset, | |
342 | cpu_vaddr + cpu_offset, | |
343 | this_length); | |
344 | } | |
345 | cpu_offset += this_length; | |
346 | gpu_offset += this_length; | |
347 | length -= this_length; | |
348 | } | |
349 | ||
99a03df5 CW |
350 | kunmap(cpu_page); |
351 | kunmap(gpu_page); | |
280b713b EA |
352 | } |
353 | ||
eb01459f EA |
354 | /** |
355 | * This is the fast shmem pread path, which attempts to copy_from_user directly | |
356 | * from the backing pages of the object to the user's address space. On a | |
357 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). | |
358 | */ | |
359 | static int | |
360 | i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj, | |
361 | struct drm_i915_gem_pread *args, | |
362 | struct drm_file *file_priv) | |
363 | { | |
23010e43 | 364 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
eb01459f EA |
365 | ssize_t remain; |
366 | loff_t offset, page_base; | |
367 | char __user *user_data; | |
368 | int page_offset, page_length; | |
369 | int ret; | |
370 | ||
371 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
372 | remain = args->size; | |
373 | ||
76c1dec1 CW |
374 | ret = i915_mutex_lock_interruptible(dev); |
375 | if (ret) | |
376 | return ret; | |
eb01459f | 377 | |
4bdadb97 | 378 | ret = i915_gem_object_get_pages(obj, 0); |
eb01459f EA |
379 | if (ret != 0) |
380 | goto fail_unlock; | |
381 | ||
382 | ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, | |
383 | args->size); | |
384 | if (ret != 0) | |
385 | goto fail_put_pages; | |
386 | ||
23010e43 | 387 | obj_priv = to_intel_bo(obj); |
eb01459f EA |
388 | offset = args->offset; |
389 | ||
390 | while (remain > 0) { | |
391 | /* Operation in this page | |
392 | * | |
393 | * page_base = page offset within aperture | |
394 | * page_offset = offset within page | |
395 | * page_length = bytes to copy for this page | |
396 | */ | |
397 | page_base = (offset & ~(PAGE_SIZE-1)); | |
398 | page_offset = offset & (PAGE_SIZE-1); | |
399 | page_length = remain; | |
400 | if ((page_offset + remain) > PAGE_SIZE) | |
401 | page_length = PAGE_SIZE - page_offset; | |
402 | ||
403 | ret = fast_shmem_read(obj_priv->pages, | |
404 | page_base, page_offset, | |
405 | user_data, page_length); | |
406 | if (ret) | |
407 | goto fail_put_pages; | |
408 | ||
409 | remain -= page_length; | |
410 | user_data += page_length; | |
411 | offset += page_length; | |
412 | } | |
413 | ||
414 | fail_put_pages: | |
415 | i915_gem_object_put_pages(obj); | |
416 | fail_unlock: | |
417 | mutex_unlock(&dev->struct_mutex); | |
418 | ||
419 | return ret; | |
420 | } | |
421 | ||
07f73f69 CW |
422 | static int |
423 | i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj) | |
424 | { | |
425 | int ret; | |
426 | ||
4bdadb97 | 427 | ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN); |
07f73f69 CW |
428 | |
429 | /* If we've insufficient memory to map in the pages, attempt | |
430 | * to make some space by throwing out some old buffers. | |
431 | */ | |
432 | if (ret == -ENOMEM) { | |
433 | struct drm_device *dev = obj->dev; | |
07f73f69 | 434 | |
0108a3ed DV |
435 | ret = i915_gem_evict_something(dev, obj->size, |
436 | i915_gem_get_gtt_alignment(obj)); | |
07f73f69 CW |
437 | if (ret) |
438 | return ret; | |
439 | ||
4bdadb97 | 440 | ret = i915_gem_object_get_pages(obj, 0); |
07f73f69 CW |
441 | } |
442 | ||
443 | return ret; | |
444 | } | |
445 | ||
eb01459f EA |
446 | /** |
447 | * This is the fallback shmem pread path, which allocates temporary storage | |
448 | * in kernel space to copy_to_user into outside of the struct_mutex, so we | |
449 | * can copy out of the object's backing pages while holding the struct mutex | |
450 | * and not take page faults. | |
451 | */ | |
452 | static int | |
453 | i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
454 | struct drm_i915_gem_pread *args, | |
455 | struct drm_file *file_priv) | |
456 | { | |
23010e43 | 457 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
eb01459f EA |
458 | struct mm_struct *mm = current->mm; |
459 | struct page **user_pages; | |
460 | ssize_t remain; | |
461 | loff_t offset, pinned_pages, i; | |
462 | loff_t first_data_page, last_data_page, num_pages; | |
463 | int shmem_page_index, shmem_page_offset; | |
464 | int data_page_index, data_page_offset; | |
465 | int page_length; | |
466 | int ret; | |
467 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 468 | int do_bit17_swizzling; |
eb01459f EA |
469 | |
470 | remain = args->size; | |
471 | ||
472 | /* Pin the user pages containing the data. We can't fault while | |
473 | * holding the struct mutex, yet we want to hold it while | |
474 | * dereferencing the user data. | |
475 | */ | |
476 | first_data_page = data_ptr / PAGE_SIZE; | |
477 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
478 | num_pages = last_data_page - first_data_page + 1; | |
479 | ||
8e7d2b2c | 480 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
eb01459f EA |
481 | if (user_pages == NULL) |
482 | return -ENOMEM; | |
483 | ||
484 | down_read(&mm->mmap_sem); | |
485 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
e5e9ecde | 486 | num_pages, 1, 0, user_pages, NULL); |
eb01459f EA |
487 | up_read(&mm->mmap_sem); |
488 | if (pinned_pages < num_pages) { | |
489 | ret = -EFAULT; | |
490 | goto fail_put_user_pages; | |
491 | } | |
492 | ||
280b713b EA |
493 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
494 | ||
76c1dec1 CW |
495 | ret = i915_mutex_lock_interruptible(dev); |
496 | if (ret) | |
497 | goto fail_put_user_pages; | |
eb01459f | 498 | |
07f73f69 CW |
499 | ret = i915_gem_object_get_pages_or_evict(obj); |
500 | if (ret) | |
eb01459f EA |
501 | goto fail_unlock; |
502 | ||
503 | ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, | |
504 | args->size); | |
505 | if (ret != 0) | |
506 | goto fail_put_pages; | |
507 | ||
23010e43 | 508 | obj_priv = to_intel_bo(obj); |
eb01459f EA |
509 | offset = args->offset; |
510 | ||
511 | while (remain > 0) { | |
512 | /* Operation in this page | |
513 | * | |
514 | * shmem_page_index = page number within shmem file | |
515 | * shmem_page_offset = offset within page in shmem file | |
516 | * data_page_index = page number in get_user_pages return | |
517 | * data_page_offset = offset with data_page_index page. | |
518 | * page_length = bytes to copy for this page | |
519 | */ | |
520 | shmem_page_index = offset / PAGE_SIZE; | |
521 | shmem_page_offset = offset & ~PAGE_MASK; | |
522 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
523 | data_page_offset = data_ptr & ~PAGE_MASK; | |
524 | ||
525 | page_length = remain; | |
526 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
527 | page_length = PAGE_SIZE - shmem_page_offset; | |
528 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
529 | page_length = PAGE_SIZE - data_page_offset; | |
530 | ||
280b713b | 531 | if (do_bit17_swizzling) { |
99a03df5 | 532 | slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
280b713b | 533 | shmem_page_offset, |
99a03df5 CW |
534 | user_pages[data_page_index], |
535 | data_page_offset, | |
536 | page_length, | |
537 | 1); | |
538 | } else { | |
539 | slow_shmem_copy(user_pages[data_page_index], | |
540 | data_page_offset, | |
541 | obj_priv->pages[shmem_page_index], | |
542 | shmem_page_offset, | |
543 | page_length); | |
280b713b | 544 | } |
eb01459f EA |
545 | |
546 | remain -= page_length; | |
547 | data_ptr += page_length; | |
548 | offset += page_length; | |
549 | } | |
550 | ||
551 | fail_put_pages: | |
552 | i915_gem_object_put_pages(obj); | |
553 | fail_unlock: | |
554 | mutex_unlock(&dev->struct_mutex); | |
555 | fail_put_user_pages: | |
556 | for (i = 0; i < pinned_pages; i++) { | |
557 | SetPageDirty(user_pages[i]); | |
558 | page_cache_release(user_pages[i]); | |
559 | } | |
8e7d2b2c | 560 | drm_free_large(user_pages); |
eb01459f EA |
561 | |
562 | return ret; | |
563 | } | |
564 | ||
673a394b EA |
565 | /** |
566 | * Reads data from the object referenced by handle. | |
567 | * | |
568 | * On error, the contents of *data are undefined. | |
569 | */ | |
570 | int | |
571 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
572 | struct drm_file *file_priv) | |
573 | { | |
574 | struct drm_i915_gem_pread *args = data; | |
575 | struct drm_gem_object *obj; | |
576 | struct drm_i915_gem_object *obj_priv; | |
35b62a89 | 577 | int ret = 0; |
673a394b EA |
578 | |
579 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
580 | if (obj == NULL) | |
bf79cb91 | 581 | return -ENOENT; |
23010e43 | 582 | obj_priv = to_intel_bo(obj); |
673a394b | 583 | |
7dcd2499 CW |
584 | /* Bounds check source. */ |
585 | if (args->offset > obj->size || args->size > obj->size - args->offset) { | |
ce9d419d | 586 | ret = -EINVAL; |
35b62a89 | 587 | goto out; |
ce9d419d CW |
588 | } |
589 | ||
35b62a89 CW |
590 | if (args->size == 0) |
591 | goto out; | |
592 | ||
ce9d419d CW |
593 | if (!access_ok(VERIFY_WRITE, |
594 | (char __user *)(uintptr_t)args->data_ptr, | |
595 | args->size)) { | |
596 | ret = -EFAULT; | |
35b62a89 | 597 | goto out; |
673a394b EA |
598 | } |
599 | ||
b5e4feb6 CW |
600 | ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr, |
601 | args->size); | |
602 | if (ret) { | |
603 | ret = -EFAULT; | |
604 | goto out; | |
605 | } | |
606 | ||
280b713b | 607 | if (i915_gem_object_needs_bit17_swizzle(obj)) { |
eb01459f | 608 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv); |
280b713b EA |
609 | } else { |
610 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv); | |
611 | if (ret != 0) | |
612 | ret = i915_gem_shmem_pread_slow(dev, obj, args, | |
613 | file_priv); | |
614 | } | |
673a394b | 615 | |
35b62a89 | 616 | out: |
bc9025bd | 617 | drm_gem_object_unreference_unlocked(obj); |
eb01459f | 618 | return ret; |
673a394b EA |
619 | } |
620 | ||
0839ccb8 KP |
621 | /* This is the fast write path which cannot handle |
622 | * page faults in the source data | |
9b7530cc | 623 | */ |
0839ccb8 KP |
624 | |
625 | static inline int | |
626 | fast_user_write(struct io_mapping *mapping, | |
627 | loff_t page_base, int page_offset, | |
628 | char __user *user_data, | |
629 | int length) | |
9b7530cc | 630 | { |
9b7530cc | 631 | char *vaddr_atomic; |
0839ccb8 | 632 | unsigned long unwritten; |
9b7530cc | 633 | |
fca3ec01 | 634 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base, KM_USER0); |
0839ccb8 KP |
635 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
636 | user_data, length); | |
fca3ec01 | 637 | io_mapping_unmap_atomic(vaddr_atomic, KM_USER0); |
fbd5a26d | 638 | return unwritten; |
0839ccb8 KP |
639 | } |
640 | ||
641 | /* Here's the write path which can sleep for | |
642 | * page faults | |
643 | */ | |
644 | ||
ab34c226 | 645 | static inline void |
3de09aa3 EA |
646 | slow_kernel_write(struct io_mapping *mapping, |
647 | loff_t gtt_base, int gtt_offset, | |
648 | struct page *user_page, int user_offset, | |
649 | int length) | |
0839ccb8 | 650 | { |
ab34c226 CW |
651 | char __iomem *dst_vaddr; |
652 | char *src_vaddr; | |
0839ccb8 | 653 | |
ab34c226 CW |
654 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
655 | src_vaddr = kmap(user_page); | |
656 | ||
657 | memcpy_toio(dst_vaddr + gtt_offset, | |
658 | src_vaddr + user_offset, | |
659 | length); | |
660 | ||
661 | kunmap(user_page); | |
662 | io_mapping_unmap(dst_vaddr); | |
9b7530cc LT |
663 | } |
664 | ||
40123c1f EA |
665 | static inline int |
666 | fast_shmem_write(struct page **pages, | |
667 | loff_t page_base, int page_offset, | |
668 | char __user *data, | |
669 | int length) | |
670 | { | |
b5e4feb6 | 671 | char *vaddr; |
fbd5a26d | 672 | int ret; |
40123c1f EA |
673 | |
674 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0); | |
fbd5a26d | 675 | ret = __copy_from_user_inatomic(vaddr + page_offset, data, length); |
40123c1f EA |
676 | kunmap_atomic(vaddr, KM_USER0); |
677 | ||
fbd5a26d | 678 | return ret; |
40123c1f EA |
679 | } |
680 | ||
3de09aa3 EA |
681 | /** |
682 | * This is the fast pwrite path, where we copy the data directly from the | |
683 | * user into the GTT, uncached. | |
684 | */ | |
673a394b | 685 | static int |
3de09aa3 EA |
686 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
687 | struct drm_i915_gem_pwrite *args, | |
688 | struct drm_file *file_priv) | |
673a394b | 689 | { |
23010e43 | 690 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
0839ccb8 | 691 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 692 | ssize_t remain; |
0839ccb8 | 693 | loff_t offset, page_base; |
673a394b | 694 | char __user *user_data; |
0839ccb8 | 695 | int page_offset, page_length; |
673a394b EA |
696 | |
697 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
698 | remain = args->size; | |
673a394b | 699 | |
23010e43 | 700 | obj_priv = to_intel_bo(obj); |
673a394b | 701 | offset = obj_priv->gtt_offset + args->offset; |
673a394b EA |
702 | |
703 | while (remain > 0) { | |
704 | /* Operation in this page | |
705 | * | |
0839ccb8 KP |
706 | * page_base = page offset within aperture |
707 | * page_offset = offset within page | |
708 | * page_length = bytes to copy for this page | |
673a394b | 709 | */ |
0839ccb8 KP |
710 | page_base = (offset & ~(PAGE_SIZE-1)); |
711 | page_offset = offset & (PAGE_SIZE-1); | |
712 | page_length = remain; | |
713 | if ((page_offset + remain) > PAGE_SIZE) | |
714 | page_length = PAGE_SIZE - page_offset; | |
715 | ||
0839ccb8 | 716 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
717 | * source page isn't available. Return the error and we'll |
718 | * retry in the slow path. | |
0839ccb8 | 719 | */ |
fbd5a26d CW |
720 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
721 | page_offset, user_data, page_length)) | |
722 | ||
723 | return -EFAULT; | |
673a394b | 724 | |
0839ccb8 KP |
725 | remain -= page_length; |
726 | user_data += page_length; | |
727 | offset += page_length; | |
673a394b | 728 | } |
673a394b | 729 | |
fbd5a26d | 730 | return 0; |
673a394b EA |
731 | } |
732 | ||
3de09aa3 EA |
733 | /** |
734 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin | |
735 | * the memory and maps it using kmap_atomic for copying. | |
736 | * | |
737 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU | |
738 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). | |
739 | */ | |
3043c60c | 740 | static int |
3de09aa3 EA |
741 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
742 | struct drm_i915_gem_pwrite *args, | |
743 | struct drm_file *file_priv) | |
673a394b | 744 | { |
23010e43 | 745 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
3de09aa3 EA |
746 | drm_i915_private_t *dev_priv = dev->dev_private; |
747 | ssize_t remain; | |
748 | loff_t gtt_page_base, offset; | |
749 | loff_t first_data_page, last_data_page, num_pages; | |
750 | loff_t pinned_pages, i; | |
751 | struct page **user_pages; | |
752 | struct mm_struct *mm = current->mm; | |
753 | int gtt_page_offset, data_page_offset, data_page_index, page_length; | |
673a394b | 754 | int ret; |
3de09aa3 EA |
755 | uint64_t data_ptr = args->data_ptr; |
756 | ||
757 | remain = args->size; | |
758 | ||
759 | /* Pin the user pages containing the data. We can't fault while | |
760 | * holding the struct mutex, and all of the pwrite implementations | |
761 | * want to hold it while dereferencing the user data. | |
762 | */ | |
763 | first_data_page = data_ptr / PAGE_SIZE; | |
764 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
765 | num_pages = last_data_page - first_data_page + 1; | |
766 | ||
fbd5a26d | 767 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
3de09aa3 EA |
768 | if (user_pages == NULL) |
769 | return -ENOMEM; | |
770 | ||
fbd5a26d | 771 | mutex_unlock(&dev->struct_mutex); |
3de09aa3 EA |
772 | down_read(&mm->mmap_sem); |
773 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
774 | num_pages, 0, 0, user_pages, NULL); | |
775 | up_read(&mm->mmap_sem); | |
fbd5a26d | 776 | mutex_lock(&dev->struct_mutex); |
3de09aa3 EA |
777 | if (pinned_pages < num_pages) { |
778 | ret = -EFAULT; | |
779 | goto out_unpin_pages; | |
780 | } | |
673a394b | 781 | |
3de09aa3 EA |
782 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
783 | if (ret) | |
fbd5a26d | 784 | goto out_unpin_pages; |
3de09aa3 | 785 | |
23010e43 | 786 | obj_priv = to_intel_bo(obj); |
3de09aa3 EA |
787 | offset = obj_priv->gtt_offset + args->offset; |
788 | ||
789 | while (remain > 0) { | |
790 | /* Operation in this page | |
791 | * | |
792 | * gtt_page_base = page offset within aperture | |
793 | * gtt_page_offset = offset within page in aperture | |
794 | * data_page_index = page number in get_user_pages return | |
795 | * data_page_offset = offset with data_page_index page. | |
796 | * page_length = bytes to copy for this page | |
797 | */ | |
798 | gtt_page_base = offset & PAGE_MASK; | |
799 | gtt_page_offset = offset & ~PAGE_MASK; | |
800 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
801 | data_page_offset = data_ptr & ~PAGE_MASK; | |
802 | ||
803 | page_length = remain; | |
804 | if ((gtt_page_offset + page_length) > PAGE_SIZE) | |
805 | page_length = PAGE_SIZE - gtt_page_offset; | |
806 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
807 | page_length = PAGE_SIZE - data_page_offset; | |
808 | ||
ab34c226 CW |
809 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
810 | gtt_page_base, gtt_page_offset, | |
811 | user_pages[data_page_index], | |
812 | data_page_offset, | |
813 | page_length); | |
3de09aa3 EA |
814 | |
815 | remain -= page_length; | |
816 | offset += page_length; | |
817 | data_ptr += page_length; | |
818 | } | |
819 | ||
3de09aa3 EA |
820 | out_unpin_pages: |
821 | for (i = 0; i < pinned_pages; i++) | |
822 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 823 | drm_free_large(user_pages); |
3de09aa3 EA |
824 | |
825 | return ret; | |
826 | } | |
827 | ||
40123c1f EA |
828 | /** |
829 | * This is the fast shmem pwrite path, which attempts to directly | |
830 | * copy_from_user into the kmapped pages backing the object. | |
831 | */ | |
3043c60c | 832 | static int |
40123c1f EA |
833 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
834 | struct drm_i915_gem_pwrite *args, | |
835 | struct drm_file *file_priv) | |
673a394b | 836 | { |
23010e43 | 837 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
40123c1f EA |
838 | ssize_t remain; |
839 | loff_t offset, page_base; | |
840 | char __user *user_data; | |
841 | int page_offset, page_length; | |
40123c1f EA |
842 | |
843 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
844 | remain = args->size; | |
673a394b | 845 | |
23010e43 | 846 | obj_priv = to_intel_bo(obj); |
40123c1f EA |
847 | offset = args->offset; |
848 | obj_priv->dirty = 1; | |
849 | ||
850 | while (remain > 0) { | |
851 | /* Operation in this page | |
852 | * | |
853 | * page_base = page offset within aperture | |
854 | * page_offset = offset within page | |
855 | * page_length = bytes to copy for this page | |
856 | */ | |
857 | page_base = (offset & ~(PAGE_SIZE-1)); | |
858 | page_offset = offset & (PAGE_SIZE-1); | |
859 | page_length = remain; | |
860 | if ((page_offset + remain) > PAGE_SIZE) | |
861 | page_length = PAGE_SIZE - page_offset; | |
862 | ||
fbd5a26d | 863 | if (fast_shmem_write(obj_priv->pages, |
40123c1f | 864 | page_base, page_offset, |
fbd5a26d CW |
865 | user_data, page_length)) |
866 | return -EFAULT; | |
40123c1f EA |
867 | |
868 | remain -= page_length; | |
869 | user_data += page_length; | |
870 | offset += page_length; | |
871 | } | |
872 | ||
fbd5a26d | 873 | return 0; |
40123c1f EA |
874 | } |
875 | ||
876 | /** | |
877 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin | |
878 | * the memory and maps it using kmap_atomic for copying. | |
879 | * | |
880 | * This avoids taking mmap_sem for faulting on the user's address while the | |
881 | * struct_mutex is held. | |
882 | */ | |
883 | static int | |
884 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
885 | struct drm_i915_gem_pwrite *args, | |
886 | struct drm_file *file_priv) | |
887 | { | |
23010e43 | 888 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
40123c1f EA |
889 | struct mm_struct *mm = current->mm; |
890 | struct page **user_pages; | |
891 | ssize_t remain; | |
892 | loff_t offset, pinned_pages, i; | |
893 | loff_t first_data_page, last_data_page, num_pages; | |
894 | int shmem_page_index, shmem_page_offset; | |
895 | int data_page_index, data_page_offset; | |
896 | int page_length; | |
897 | int ret; | |
898 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 899 | int do_bit17_swizzling; |
40123c1f EA |
900 | |
901 | remain = args->size; | |
902 | ||
903 | /* Pin the user pages containing the data. We can't fault while | |
904 | * holding the struct mutex, and all of the pwrite implementations | |
905 | * want to hold it while dereferencing the user data. | |
906 | */ | |
907 | first_data_page = data_ptr / PAGE_SIZE; | |
908 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
909 | num_pages = last_data_page - first_data_page + 1; | |
910 | ||
8e7d2b2c | 911 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
40123c1f EA |
912 | if (user_pages == NULL) |
913 | return -ENOMEM; | |
914 | ||
fbd5a26d | 915 | mutex_unlock(&dev->struct_mutex); |
40123c1f EA |
916 | down_read(&mm->mmap_sem); |
917 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
918 | num_pages, 0, 0, user_pages, NULL); | |
919 | up_read(&mm->mmap_sem); | |
fbd5a26d | 920 | mutex_lock(&dev->struct_mutex); |
40123c1f EA |
921 | if (pinned_pages < num_pages) { |
922 | ret = -EFAULT; | |
fbd5a26d | 923 | goto out; |
673a394b EA |
924 | } |
925 | ||
fbd5a26d | 926 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
07f73f69 | 927 | if (ret) |
fbd5a26d | 928 | goto out; |
40123c1f | 929 | |
fbd5a26d | 930 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 931 | |
23010e43 | 932 | obj_priv = to_intel_bo(obj); |
673a394b | 933 | offset = args->offset; |
40123c1f | 934 | obj_priv->dirty = 1; |
673a394b | 935 | |
40123c1f EA |
936 | while (remain > 0) { |
937 | /* Operation in this page | |
938 | * | |
939 | * shmem_page_index = page number within shmem file | |
940 | * shmem_page_offset = offset within page in shmem file | |
941 | * data_page_index = page number in get_user_pages return | |
942 | * data_page_offset = offset with data_page_index page. | |
943 | * page_length = bytes to copy for this page | |
944 | */ | |
945 | shmem_page_index = offset / PAGE_SIZE; | |
946 | shmem_page_offset = offset & ~PAGE_MASK; | |
947 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
948 | data_page_offset = data_ptr & ~PAGE_MASK; | |
949 | ||
950 | page_length = remain; | |
951 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
952 | page_length = PAGE_SIZE - shmem_page_offset; | |
953 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
954 | page_length = PAGE_SIZE - data_page_offset; | |
955 | ||
280b713b | 956 | if (do_bit17_swizzling) { |
99a03df5 | 957 | slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
280b713b EA |
958 | shmem_page_offset, |
959 | user_pages[data_page_index], | |
960 | data_page_offset, | |
99a03df5 CW |
961 | page_length, |
962 | 0); | |
963 | } else { | |
964 | slow_shmem_copy(obj_priv->pages[shmem_page_index], | |
965 | shmem_page_offset, | |
966 | user_pages[data_page_index], | |
967 | data_page_offset, | |
968 | page_length); | |
280b713b | 969 | } |
40123c1f EA |
970 | |
971 | remain -= page_length; | |
972 | data_ptr += page_length; | |
973 | offset += page_length; | |
673a394b EA |
974 | } |
975 | ||
fbd5a26d | 976 | out: |
40123c1f EA |
977 | for (i = 0; i < pinned_pages; i++) |
978 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 979 | drm_free_large(user_pages); |
673a394b | 980 | |
40123c1f | 981 | return ret; |
673a394b EA |
982 | } |
983 | ||
984 | /** | |
985 | * Writes data to the object referenced by handle. | |
986 | * | |
987 | * On error, the contents of the buffer that were to be modified are undefined. | |
988 | */ | |
989 | int | |
990 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 991 | struct drm_file *file) |
673a394b EA |
992 | { |
993 | struct drm_i915_gem_pwrite *args = data; | |
994 | struct drm_gem_object *obj; | |
995 | struct drm_i915_gem_object *obj_priv; | |
996 | int ret = 0; | |
997 | ||
fbd5a26d | 998 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 999 | if (obj == NULL) |
bf79cb91 | 1000 | return -ENOENT; |
23010e43 | 1001 | obj_priv = to_intel_bo(obj); |
673a394b | 1002 | |
fbd5a26d CW |
1003 | ret = i915_mutex_lock_interruptible(dev); |
1004 | if (ret) { | |
1005 | drm_gem_object_unreference_unlocked(obj); | |
1006 | return ret; | |
1007 | } | |
1008 | ||
7dcd2499 CW |
1009 | /* Bounds check destination. */ |
1010 | if (args->offset > obj->size || args->size > obj->size - args->offset) { | |
ce9d419d | 1011 | ret = -EINVAL; |
35b62a89 | 1012 | goto out; |
ce9d419d CW |
1013 | } |
1014 | ||
35b62a89 CW |
1015 | if (args->size == 0) |
1016 | goto out; | |
1017 | ||
ce9d419d CW |
1018 | if (!access_ok(VERIFY_READ, |
1019 | (char __user *)(uintptr_t)args->data_ptr, | |
1020 | args->size)) { | |
1021 | ret = -EFAULT; | |
35b62a89 | 1022 | goto out; |
673a394b EA |
1023 | } |
1024 | ||
b5e4feb6 CW |
1025 | ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr, |
1026 | args->size); | |
1027 | if (ret) { | |
1028 | ret = -EFAULT; | |
1029 | goto out; | |
1030 | } | |
1031 | ||
673a394b EA |
1032 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1033 | * it would end up going through the fenced access, and we'll get | |
1034 | * different detiling behavior between reading and writing. | |
1035 | * pread/pwrite currently are reading and writing from the CPU | |
1036 | * perspective, requiring manual detiling by the client. | |
1037 | */ | |
71acb5eb | 1038 | if (obj_priv->phys_obj) |
fbd5a26d | 1039 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
71acb5eb | 1040 | else if (obj_priv->tiling_mode == I915_TILING_NONE && |
5cdf5881 | 1041 | obj_priv->gtt_space && |
9b8c4a0b | 1042 | obj->write_domain != I915_GEM_DOMAIN_CPU) { |
fbd5a26d CW |
1043 | ret = i915_gem_object_pin(obj, 0); |
1044 | if (ret) | |
1045 | goto out; | |
1046 | ||
1047 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); | |
1048 | if (ret) | |
1049 | goto out_unpin; | |
1050 | ||
1051 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); | |
1052 | if (ret == -EFAULT) | |
1053 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file); | |
1054 | ||
1055 | out_unpin: | |
1056 | i915_gem_object_unpin(obj); | |
40123c1f | 1057 | } else { |
fbd5a26d CW |
1058 | ret = i915_gem_object_get_pages_or_evict(obj); |
1059 | if (ret) | |
1060 | goto out; | |
673a394b | 1061 | |
fbd5a26d CW |
1062 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
1063 | if (ret) | |
1064 | goto out_put; | |
1065 | ||
1066 | ret = -EFAULT; | |
1067 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
1068 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file); | |
1069 | if (ret == -EFAULT) | |
1070 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file); | |
1071 | ||
1072 | out_put: | |
1073 | i915_gem_object_put_pages(obj); | |
1074 | } | |
673a394b | 1075 | |
35b62a89 | 1076 | out: |
fbd5a26d CW |
1077 | drm_gem_object_unreference(obj); |
1078 | mutex_unlock(&dev->struct_mutex); | |
673a394b EA |
1079 | return ret; |
1080 | } | |
1081 | ||
1082 | /** | |
2ef7eeaa EA |
1083 | * Called when user space prepares to use an object with the CPU, either |
1084 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1085 | */ |
1086 | int | |
1087 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
1088 | struct drm_file *file_priv) | |
1089 | { | |
a09ba7fa | 1090 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
1091 | struct drm_i915_gem_set_domain *args = data; |
1092 | struct drm_gem_object *obj; | |
652c393a | 1093 | struct drm_i915_gem_object *obj_priv; |
2ef7eeaa EA |
1094 | uint32_t read_domains = args->read_domains; |
1095 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1096 | int ret; |
1097 | ||
1098 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1099 | return -ENODEV; | |
1100 | ||
2ef7eeaa | 1101 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1102 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1103 | return -EINVAL; |
1104 | ||
21d509e3 | 1105 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1106 | return -EINVAL; |
1107 | ||
1108 | /* Having something in the write domain implies it's in the read | |
1109 | * domain, and only that read domain. Enforce that in the request. | |
1110 | */ | |
1111 | if (write_domain != 0 && read_domains != write_domain) | |
1112 | return -EINVAL; | |
1113 | ||
673a394b EA |
1114 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1115 | if (obj == NULL) | |
bf79cb91 | 1116 | return -ENOENT; |
23010e43 | 1117 | obj_priv = to_intel_bo(obj); |
673a394b | 1118 | |
76c1dec1 CW |
1119 | ret = i915_mutex_lock_interruptible(dev); |
1120 | if (ret) { | |
1121 | drm_gem_object_unreference_unlocked(obj); | |
1122 | return ret; | |
1123 | } | |
652c393a JB |
1124 | |
1125 | intel_mark_busy(dev, obj); | |
1126 | ||
2ef7eeaa EA |
1127 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1128 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 | 1129 | |
a09ba7fa EA |
1130 | /* Update the LRU on the fence for the CPU access that's |
1131 | * about to occur. | |
1132 | */ | |
1133 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
007cc8ac DV |
1134 | struct drm_i915_fence_reg *reg = |
1135 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
1136 | list_move_tail(®->lru_list, | |
a09ba7fa EA |
1137 | &dev_priv->mm.fence_list); |
1138 | } | |
1139 | ||
02354392 EA |
1140 | /* Silently promote "you're not bound, there was nothing to do" |
1141 | * to success, since the client was just asking us to | |
1142 | * make sure everything was done. | |
1143 | */ | |
1144 | if (ret == -EINVAL) | |
1145 | ret = 0; | |
2ef7eeaa | 1146 | } else { |
e47c68e9 | 1147 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1148 | } |
1149 | ||
7d1c4804 CW |
1150 | /* Maintain LRU order of "inactive" objects */ |
1151 | if (ret == 0 && i915_gem_object_is_inactive(obj_priv)) | |
1152 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); | |
1153 | ||
673a394b EA |
1154 | drm_gem_object_unreference(obj); |
1155 | mutex_unlock(&dev->struct_mutex); | |
1156 | return ret; | |
1157 | } | |
1158 | ||
1159 | /** | |
1160 | * Called when user space has done writes to this buffer | |
1161 | */ | |
1162 | int | |
1163 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1164 | struct drm_file *file_priv) | |
1165 | { | |
1166 | struct drm_i915_gem_sw_finish *args = data; | |
1167 | struct drm_gem_object *obj; | |
673a394b EA |
1168 | int ret = 0; |
1169 | ||
1170 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1171 | return -ENODEV; | |
1172 | ||
673a394b | 1173 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
76c1dec1 | 1174 | if (obj == NULL) |
bf79cb91 | 1175 | return -ENOENT; |
76c1dec1 CW |
1176 | |
1177 | ret = i915_mutex_lock_interruptible(dev); | |
1178 | if (ret) { | |
1179 | drm_gem_object_unreference_unlocked(obj); | |
1180 | return ret; | |
673a394b EA |
1181 | } |
1182 | ||
673a394b | 1183 | /* Pinned buffers may be scanout, so flush the cache */ |
3d2a812a | 1184 | if (to_intel_bo(obj)->pin_count) |
e47c68e9 EA |
1185 | i915_gem_object_flush_cpu_write_domain(obj); |
1186 | ||
673a394b EA |
1187 | drm_gem_object_unreference(obj); |
1188 | mutex_unlock(&dev->struct_mutex); | |
1189 | return ret; | |
1190 | } | |
1191 | ||
1192 | /** | |
1193 | * Maps the contents of an object, returning the address it is mapped | |
1194 | * into. | |
1195 | * | |
1196 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1197 | * imply a ref on the object itself. | |
1198 | */ | |
1199 | int | |
1200 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1201 | struct drm_file *file_priv) | |
1202 | { | |
1203 | struct drm_i915_gem_mmap *args = data; | |
1204 | struct drm_gem_object *obj; | |
1205 | loff_t offset; | |
1206 | unsigned long addr; | |
1207 | ||
1208 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1209 | return -ENODEV; | |
1210 | ||
1211 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1212 | if (obj == NULL) | |
bf79cb91 | 1213 | return -ENOENT; |
673a394b EA |
1214 | |
1215 | offset = args->offset; | |
1216 | ||
1217 | down_write(¤t->mm->mmap_sem); | |
1218 | addr = do_mmap(obj->filp, 0, args->size, | |
1219 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
1220 | args->offset); | |
1221 | up_write(¤t->mm->mmap_sem); | |
bc9025bd | 1222 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1223 | if (IS_ERR((void *)addr)) |
1224 | return addr; | |
1225 | ||
1226 | args->addr_ptr = (uint64_t) addr; | |
1227 | ||
1228 | return 0; | |
1229 | } | |
1230 | ||
de151cf6 JB |
1231 | /** |
1232 | * i915_gem_fault - fault a page into the GTT | |
1233 | * vma: VMA in question | |
1234 | * vmf: fault info | |
1235 | * | |
1236 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1237 | * from userspace. The fault handler takes care of binding the object to | |
1238 | * the GTT (if needed), allocating and programming a fence register (again, | |
1239 | * only if needed based on whether the old reg is still valid or the object | |
1240 | * is tiled) and inserting a new PTE into the faulting process. | |
1241 | * | |
1242 | * Note that the faulting process may involve evicting existing objects | |
1243 | * from the GTT and/or fence registers to make room. So performance may | |
1244 | * suffer if the GTT working set is large or there are few fence registers | |
1245 | * left. | |
1246 | */ | |
1247 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1248 | { | |
1249 | struct drm_gem_object *obj = vma->vm_private_data; | |
1250 | struct drm_device *dev = obj->dev; | |
7d1c4804 | 1251 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 1252 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
1253 | pgoff_t page_offset; |
1254 | unsigned long pfn; | |
1255 | int ret = 0; | |
0f973f27 | 1256 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1257 | |
1258 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1259 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1260 | PAGE_SHIFT; | |
1261 | ||
1262 | /* Now bind it into the GTT if needed */ | |
1263 | mutex_lock(&dev->struct_mutex); | |
1264 | if (!obj_priv->gtt_space) { | |
e67b8ce1 | 1265 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
c715089f CW |
1266 | if (ret) |
1267 | goto unlock; | |
07f4f3e8 | 1268 | |
07f4f3e8 | 1269 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
c715089f CW |
1270 | if (ret) |
1271 | goto unlock; | |
de151cf6 JB |
1272 | } |
1273 | ||
1274 | /* Need a new fence register? */ | |
a09ba7fa | 1275 | if (obj_priv->tiling_mode != I915_TILING_NONE) { |
2cf34d7b | 1276 | ret = i915_gem_object_get_fence_reg(obj, true); |
c715089f CW |
1277 | if (ret) |
1278 | goto unlock; | |
d9ddcb96 | 1279 | } |
de151cf6 | 1280 | |
7d1c4804 CW |
1281 | if (i915_gem_object_is_inactive(obj_priv)) |
1282 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); | |
1283 | ||
de151cf6 JB |
1284 | pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) + |
1285 | page_offset; | |
1286 | ||
1287 | /* Finally, remap it using the new GTT offset */ | |
1288 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1289 | unlock: |
de151cf6 JB |
1290 | mutex_unlock(&dev->struct_mutex); |
1291 | ||
1292 | switch (ret) { | |
c715089f CW |
1293 | case 0: |
1294 | case -ERESTARTSYS: | |
1295 | return VM_FAULT_NOPAGE; | |
de151cf6 JB |
1296 | case -ENOMEM: |
1297 | case -EAGAIN: | |
1298 | return VM_FAULT_OOM; | |
de151cf6 | 1299 | default: |
c715089f | 1300 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1301 | } |
1302 | } | |
1303 | ||
1304 | /** | |
1305 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object | |
1306 | * @obj: obj in question | |
1307 | * | |
1308 | * GEM memory mapping works by handing back to userspace a fake mmap offset | |
1309 | * it can use in a subsequent mmap(2) call. The DRM core code then looks | |
1310 | * up the object based on the offset and sets up the various memory mapping | |
1311 | * structures. | |
1312 | * | |
1313 | * This routine allocates and attaches a fake offset for @obj. | |
1314 | */ | |
1315 | static int | |
1316 | i915_gem_create_mmap_offset(struct drm_gem_object *obj) | |
1317 | { | |
1318 | struct drm_device *dev = obj->dev; | |
1319 | struct drm_gem_mm *mm = dev->mm_private; | |
23010e43 | 1320 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 1321 | struct drm_map_list *list; |
f77d390c | 1322 | struct drm_local_map *map; |
de151cf6 JB |
1323 | int ret = 0; |
1324 | ||
1325 | /* Set the object up for mmap'ing */ | |
1326 | list = &obj->map_list; | |
9a298b2a | 1327 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
de151cf6 JB |
1328 | if (!list->map) |
1329 | return -ENOMEM; | |
1330 | ||
1331 | map = list->map; | |
1332 | map->type = _DRM_GEM; | |
1333 | map->size = obj->size; | |
1334 | map->handle = obj; | |
1335 | ||
1336 | /* Get a DRM GEM mmap offset allocated... */ | |
1337 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, | |
1338 | obj->size / PAGE_SIZE, 0, 0); | |
1339 | if (!list->file_offset_node) { | |
1340 | DRM_ERROR("failed to allocate offset for bo %d\n", obj->name); | |
9e0ae534 | 1341 | ret = -ENOSPC; |
de151cf6 JB |
1342 | goto out_free_list; |
1343 | } | |
1344 | ||
1345 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, | |
1346 | obj->size / PAGE_SIZE, 0); | |
1347 | if (!list->file_offset_node) { | |
1348 | ret = -ENOMEM; | |
1349 | goto out_free_list; | |
1350 | } | |
1351 | ||
1352 | list->hash.key = list->file_offset_node->start; | |
9e0ae534 CW |
1353 | ret = drm_ht_insert_item(&mm->offset_hash, &list->hash); |
1354 | if (ret) { | |
de151cf6 JB |
1355 | DRM_ERROR("failed to add to map hash\n"); |
1356 | goto out_free_mm; | |
1357 | } | |
1358 | ||
1359 | /* By now we should be all set, any drm_mmap request on the offset | |
1360 | * below will get to our mmap & fault handler */ | |
1361 | obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT; | |
1362 | ||
1363 | return 0; | |
1364 | ||
1365 | out_free_mm: | |
1366 | drm_mm_put_block(list->file_offset_node); | |
1367 | out_free_list: | |
9a298b2a | 1368 | kfree(list->map); |
de151cf6 JB |
1369 | |
1370 | return ret; | |
1371 | } | |
1372 | ||
901782b2 CW |
1373 | /** |
1374 | * i915_gem_release_mmap - remove physical page mappings | |
1375 | * @obj: obj in question | |
1376 | * | |
af901ca1 | 1377 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1378 | * relinquish ownership of the pages back to the system. |
1379 | * | |
1380 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1381 | * object through the GTT and then lose the fence register due to | |
1382 | * resource pressure. Similarly if the object has been moved out of the | |
1383 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1384 | * mapping will then trigger a page fault on the next user access, allowing | |
1385 | * fixup by i915_gem_fault(). | |
1386 | */ | |
d05ca301 | 1387 | void |
901782b2 CW |
1388 | i915_gem_release_mmap(struct drm_gem_object *obj) |
1389 | { | |
1390 | struct drm_device *dev = obj->dev; | |
23010e43 | 1391 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
901782b2 CW |
1392 | |
1393 | if (dev->dev_mapping) | |
1394 | unmap_mapping_range(dev->dev_mapping, | |
1395 | obj_priv->mmap_offset, obj->size, 1); | |
1396 | } | |
1397 | ||
ab00b3e5 JB |
1398 | static void |
1399 | i915_gem_free_mmap_offset(struct drm_gem_object *obj) | |
1400 | { | |
1401 | struct drm_device *dev = obj->dev; | |
23010e43 | 1402 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ab00b3e5 JB |
1403 | struct drm_gem_mm *mm = dev->mm_private; |
1404 | struct drm_map_list *list; | |
1405 | ||
1406 | list = &obj->map_list; | |
1407 | drm_ht_remove_item(&mm->offset_hash, &list->hash); | |
1408 | ||
1409 | if (list->file_offset_node) { | |
1410 | drm_mm_put_block(list->file_offset_node); | |
1411 | list->file_offset_node = NULL; | |
1412 | } | |
1413 | ||
1414 | if (list->map) { | |
9a298b2a | 1415 | kfree(list->map); |
ab00b3e5 JB |
1416 | list->map = NULL; |
1417 | } | |
1418 | ||
1419 | obj_priv->mmap_offset = 0; | |
1420 | } | |
1421 | ||
de151cf6 JB |
1422 | /** |
1423 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1424 | * @obj: object to check | |
1425 | * | |
1426 | * Return the required GTT alignment for an object, taking into account | |
1427 | * potential fence register mapping if needed. | |
1428 | */ | |
1429 | static uint32_t | |
1430 | i915_gem_get_gtt_alignment(struct drm_gem_object *obj) | |
1431 | { | |
1432 | struct drm_device *dev = obj->dev; | |
23010e43 | 1433 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
1434 | int start, i; |
1435 | ||
1436 | /* | |
1437 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1438 | * if a fence register is needed for the object. | |
1439 | */ | |
a6c45cf0 | 1440 | if (INTEL_INFO(dev)->gen >= 4 || obj_priv->tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1441 | return 4096; |
1442 | ||
1443 | /* | |
1444 | * Previous chips need to be aligned to the size of the smallest | |
1445 | * fence register that can contain the object. | |
1446 | */ | |
a6c45cf0 | 1447 | if (INTEL_INFO(dev)->gen == 3) |
de151cf6 JB |
1448 | start = 1024*1024; |
1449 | else | |
1450 | start = 512*1024; | |
1451 | ||
1452 | for (i = start; i < obj->size; i <<= 1) | |
1453 | ; | |
1454 | ||
1455 | return i; | |
1456 | } | |
1457 | ||
1458 | /** | |
1459 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1460 | * @dev: DRM device | |
1461 | * @data: GTT mapping ioctl data | |
1462 | * @file_priv: GEM object info | |
1463 | * | |
1464 | * Simply returns the fake offset to userspace so it can mmap it. | |
1465 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1466 | * up so we can get faults in the handler above. | |
1467 | * | |
1468 | * The fault handler will take care of binding the object into the GTT | |
1469 | * (since it may have been evicted to make room for something), allocating | |
1470 | * a fence register, and mapping the appropriate aperture address into | |
1471 | * userspace. | |
1472 | */ | |
1473 | int | |
1474 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1475 | struct drm_file *file_priv) | |
1476 | { | |
1477 | struct drm_i915_gem_mmap_gtt *args = data; | |
de151cf6 JB |
1478 | struct drm_gem_object *obj; |
1479 | struct drm_i915_gem_object *obj_priv; | |
1480 | int ret; | |
1481 | ||
1482 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1483 | return -ENODEV; | |
1484 | ||
1485 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1486 | if (obj == NULL) | |
bf79cb91 | 1487 | return -ENOENT; |
de151cf6 | 1488 | |
76c1dec1 CW |
1489 | ret = i915_mutex_lock_interruptible(dev); |
1490 | if (ret) { | |
1491 | drm_gem_object_unreference_unlocked(obj); | |
1492 | return ret; | |
1493 | } | |
de151cf6 | 1494 | |
23010e43 | 1495 | obj_priv = to_intel_bo(obj); |
de151cf6 | 1496 | |
ab18282d CW |
1497 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
1498 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); | |
1499 | drm_gem_object_unreference(obj); | |
1500 | mutex_unlock(&dev->struct_mutex); | |
1501 | return -EINVAL; | |
1502 | } | |
1503 | ||
1504 | ||
de151cf6 JB |
1505 | if (!obj_priv->mmap_offset) { |
1506 | ret = i915_gem_create_mmap_offset(obj); | |
13af1062 CW |
1507 | if (ret) { |
1508 | drm_gem_object_unreference(obj); | |
1509 | mutex_unlock(&dev->struct_mutex); | |
de151cf6 | 1510 | return ret; |
13af1062 | 1511 | } |
de151cf6 JB |
1512 | } |
1513 | ||
1514 | args->offset = obj_priv->mmap_offset; | |
1515 | ||
de151cf6 JB |
1516 | /* |
1517 | * Pull it into the GTT so that we have a page list (makes the | |
1518 | * initial fault faster and any subsequent flushing possible). | |
1519 | */ | |
1520 | if (!obj_priv->agp_mem) { | |
e67b8ce1 | 1521 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
de151cf6 JB |
1522 | if (ret) { |
1523 | drm_gem_object_unreference(obj); | |
1524 | mutex_unlock(&dev->struct_mutex); | |
1525 | return ret; | |
1526 | } | |
de151cf6 JB |
1527 | } |
1528 | ||
1529 | drm_gem_object_unreference(obj); | |
1530 | mutex_unlock(&dev->struct_mutex); | |
1531 | ||
1532 | return 0; | |
1533 | } | |
1534 | ||
5cdf5881 | 1535 | static void |
856fa198 | 1536 | i915_gem_object_put_pages(struct drm_gem_object *obj) |
673a394b | 1537 | { |
23010e43 | 1538 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
1539 | int page_count = obj->size / PAGE_SIZE; |
1540 | int i; | |
1541 | ||
856fa198 | 1542 | BUG_ON(obj_priv->pages_refcount == 0); |
bb6baf76 | 1543 | BUG_ON(obj_priv->madv == __I915_MADV_PURGED); |
673a394b | 1544 | |
856fa198 EA |
1545 | if (--obj_priv->pages_refcount != 0) |
1546 | return; | |
673a394b | 1547 | |
280b713b EA |
1548 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
1549 | i915_gem_object_save_bit_17_swizzle(obj); | |
1550 | ||
3ef94daa | 1551 | if (obj_priv->madv == I915_MADV_DONTNEED) |
13a05fd9 | 1552 | obj_priv->dirty = 0; |
3ef94daa CW |
1553 | |
1554 | for (i = 0; i < page_count; i++) { | |
3ef94daa CW |
1555 | if (obj_priv->dirty) |
1556 | set_page_dirty(obj_priv->pages[i]); | |
1557 | ||
1558 | if (obj_priv->madv == I915_MADV_WILLNEED) | |
856fa198 | 1559 | mark_page_accessed(obj_priv->pages[i]); |
3ef94daa CW |
1560 | |
1561 | page_cache_release(obj_priv->pages[i]); | |
1562 | } | |
673a394b EA |
1563 | obj_priv->dirty = 0; |
1564 | ||
8e7d2b2c | 1565 | drm_free_large(obj_priv->pages); |
856fa198 | 1566 | obj_priv->pages = NULL; |
673a394b EA |
1567 | } |
1568 | ||
a56ba56c CW |
1569 | static uint32_t |
1570 | i915_gem_next_request_seqno(struct drm_device *dev, | |
1571 | struct intel_ring_buffer *ring) | |
1572 | { | |
1573 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1574 | ||
1575 | ring->outstanding_lazy_request = true; | |
1576 | return dev_priv->next_seqno; | |
1577 | } | |
1578 | ||
673a394b | 1579 | static void |
617dbe27 | 1580 | i915_gem_object_move_to_active(struct drm_gem_object *obj, |
852835f3 | 1581 | struct intel_ring_buffer *ring) |
673a394b | 1582 | { |
a56ba56c | 1583 | struct drm_device *dev = obj->dev; |
23010e43 | 1584 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
a56ba56c | 1585 | uint32_t seqno = i915_gem_next_request_seqno(dev, ring); |
617dbe27 | 1586 | |
852835f3 ZN |
1587 | BUG_ON(ring == NULL); |
1588 | obj_priv->ring = ring; | |
673a394b EA |
1589 | |
1590 | /* Add a reference if we're newly entering the active list. */ | |
1591 | if (!obj_priv->active) { | |
1592 | drm_gem_object_reference(obj); | |
1593 | obj_priv->active = 1; | |
1594 | } | |
e35a41de | 1595 | |
673a394b | 1596 | /* Move from whatever list we were on to the tail of execution. */ |
852835f3 | 1597 | list_move_tail(&obj_priv->list, &ring->active_list); |
a56ba56c | 1598 | obj_priv->last_rendering_seqno = seqno; |
673a394b EA |
1599 | } |
1600 | ||
ce44b0ea EA |
1601 | static void |
1602 | i915_gem_object_move_to_flushing(struct drm_gem_object *obj) | |
1603 | { | |
1604 | struct drm_device *dev = obj->dev; | |
1605 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1606 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ce44b0ea EA |
1607 | |
1608 | BUG_ON(!obj_priv->active); | |
1609 | list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list); | |
1610 | obj_priv->last_rendering_seqno = 0; | |
1611 | } | |
673a394b | 1612 | |
963b4836 CW |
1613 | /* Immediately discard the backing storage */ |
1614 | static void | |
1615 | i915_gem_object_truncate(struct drm_gem_object *obj) | |
1616 | { | |
23010e43 | 1617 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
bb6baf76 | 1618 | struct inode *inode; |
963b4836 | 1619 | |
ae9fed6b CW |
1620 | /* Our goal here is to return as much of the memory as |
1621 | * is possible back to the system as we are called from OOM. | |
1622 | * To do this we must instruct the shmfs to drop all of its | |
1623 | * backing pages, *now*. Here we mirror the actions taken | |
1624 | * when by shmem_delete_inode() to release the backing store. | |
1625 | */ | |
bb6baf76 | 1626 | inode = obj->filp->f_path.dentry->d_inode; |
ae9fed6b CW |
1627 | truncate_inode_pages(inode->i_mapping, 0); |
1628 | if (inode->i_op->truncate_range) | |
1629 | inode->i_op->truncate_range(inode, 0, (loff_t)-1); | |
bb6baf76 CW |
1630 | |
1631 | obj_priv->madv = __I915_MADV_PURGED; | |
963b4836 CW |
1632 | } |
1633 | ||
1634 | static inline int | |
1635 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv) | |
1636 | { | |
1637 | return obj_priv->madv == I915_MADV_DONTNEED; | |
1638 | } | |
1639 | ||
673a394b EA |
1640 | static void |
1641 | i915_gem_object_move_to_inactive(struct drm_gem_object *obj) | |
1642 | { | |
1643 | struct drm_device *dev = obj->dev; | |
1644 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1645 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 1646 | |
673a394b | 1647 | if (obj_priv->pin_count != 0) |
f13d3f73 | 1648 | list_move_tail(&obj_priv->list, &dev_priv->mm.pinned_list); |
673a394b EA |
1649 | else |
1650 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); | |
1651 | ||
99fcb766 DV |
1652 | BUG_ON(!list_empty(&obj_priv->gpu_write_list)); |
1653 | ||
ce44b0ea | 1654 | obj_priv->last_rendering_seqno = 0; |
852835f3 | 1655 | obj_priv->ring = NULL; |
673a394b EA |
1656 | if (obj_priv->active) { |
1657 | obj_priv->active = 0; | |
1658 | drm_gem_object_unreference(obj); | |
1659 | } | |
23bc5982 | 1660 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
1661 | } |
1662 | ||
9220434a | 1663 | static void |
63560396 | 1664 | i915_gem_process_flushing_list(struct drm_device *dev, |
8a1a49f9 | 1665 | uint32_t flush_domains, |
852835f3 | 1666 | struct intel_ring_buffer *ring) |
63560396 DV |
1667 | { |
1668 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1669 | struct drm_i915_gem_object *obj_priv, *next; | |
1670 | ||
1671 | list_for_each_entry_safe(obj_priv, next, | |
1672 | &dev_priv->mm.gpu_write_list, | |
1673 | gpu_write_list) { | |
a8089e84 | 1674 | struct drm_gem_object *obj = &obj_priv->base; |
63560396 | 1675 | |
2b6efaa4 CW |
1676 | if (obj->write_domain & flush_domains && |
1677 | obj_priv->ring == ring) { | |
63560396 DV |
1678 | uint32_t old_write_domain = obj->write_domain; |
1679 | ||
1680 | obj->write_domain = 0; | |
1681 | list_del_init(&obj_priv->gpu_write_list); | |
617dbe27 | 1682 | i915_gem_object_move_to_active(obj, ring); |
63560396 DV |
1683 | |
1684 | /* update the fence lru list */ | |
007cc8ac DV |
1685 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
1686 | struct drm_i915_fence_reg *reg = | |
1687 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
1688 | list_move_tail(®->lru_list, | |
63560396 | 1689 | &dev_priv->mm.fence_list); |
007cc8ac | 1690 | } |
63560396 DV |
1691 | |
1692 | trace_i915_gem_object_change_domain(obj, | |
1693 | obj->read_domains, | |
1694 | old_write_domain); | |
1695 | } | |
1696 | } | |
1697 | } | |
8187a2b7 | 1698 | |
5a5a0c64 | 1699 | uint32_t |
8a1a49f9 | 1700 | i915_add_request(struct drm_device *dev, |
f787a5f5 | 1701 | struct drm_file *file, |
8dc5d147 | 1702 | struct drm_i915_gem_request *request, |
8a1a49f9 | 1703 | struct intel_ring_buffer *ring) |
673a394b EA |
1704 | { |
1705 | drm_i915_private_t *dev_priv = dev->dev_private; | |
f787a5f5 | 1706 | struct drm_i915_file_private *file_priv = NULL; |
673a394b EA |
1707 | uint32_t seqno; |
1708 | int was_empty; | |
673a394b | 1709 | |
f787a5f5 CW |
1710 | if (file != NULL) |
1711 | file_priv = file->driver_priv; | |
b962442e | 1712 | |
8dc5d147 CW |
1713 | if (request == NULL) { |
1714 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
1715 | if (request == NULL) | |
1716 | return 0; | |
1717 | } | |
673a394b | 1718 | |
f787a5f5 | 1719 | seqno = ring->add_request(dev, ring, 0); |
a56ba56c | 1720 | ring->outstanding_lazy_request = false; |
673a394b EA |
1721 | |
1722 | request->seqno = seqno; | |
852835f3 | 1723 | request->ring = ring; |
673a394b | 1724 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1725 | was_empty = list_empty(&ring->request_list); |
1726 | list_add_tail(&request->list, &ring->request_list); | |
1727 | ||
f787a5f5 | 1728 | if (file_priv) { |
1c25595f | 1729 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 1730 | request->file_priv = file_priv; |
b962442e | 1731 | list_add_tail(&request->client_list, |
f787a5f5 | 1732 | &file_priv->mm.request_list); |
1c25595f | 1733 | spin_unlock(&file_priv->mm.lock); |
b962442e | 1734 | } |
673a394b | 1735 | |
f65d9421 | 1736 | if (!dev_priv->mm.suspended) { |
b3b079db CW |
1737 | mod_timer(&dev_priv->hangcheck_timer, |
1738 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
f65d9421 | 1739 | if (was_empty) |
b3b079db CW |
1740 | queue_delayed_work(dev_priv->wq, |
1741 | &dev_priv->mm.retire_work, HZ); | |
f65d9421 | 1742 | } |
673a394b EA |
1743 | return seqno; |
1744 | } | |
1745 | ||
1746 | /** | |
1747 | * Command execution barrier | |
1748 | * | |
1749 | * Ensures that all commands in the ring are finished | |
1750 | * before signalling the CPU | |
1751 | */ | |
8a1a49f9 | 1752 | static void |
852835f3 | 1753 | i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring) |
673a394b | 1754 | { |
673a394b | 1755 | uint32_t flush_domains = 0; |
673a394b EA |
1756 | |
1757 | /* The sampler always gets flushed on i965 (sigh) */ | |
a6c45cf0 | 1758 | if (INTEL_INFO(dev)->gen >= 4) |
673a394b | 1759 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; |
852835f3 ZN |
1760 | |
1761 | ring->flush(dev, ring, | |
1762 | I915_GEM_DOMAIN_COMMAND, flush_domains); | |
673a394b EA |
1763 | } |
1764 | ||
f787a5f5 CW |
1765 | static inline void |
1766 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 1767 | { |
1c25595f CW |
1768 | struct drm_i915_file_private *file_priv = request->file_priv; |
1769 | ||
1770 | if (!file_priv) | |
1771 | return; | |
1772 | ||
1773 | spin_lock(&file_priv->mm.lock); | |
1774 | list_del(&request->client_list); | |
1775 | request->file_priv = NULL; | |
1776 | spin_unlock(&file_priv->mm.lock); | |
673a394b EA |
1777 | } |
1778 | ||
dfaae392 CW |
1779 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
1780 | struct intel_ring_buffer *ring) | |
9375e446 | 1781 | { |
dfaae392 CW |
1782 | while (!list_empty(&ring->request_list)) { |
1783 | struct drm_i915_gem_request *request; | |
9375e446 | 1784 | |
dfaae392 CW |
1785 | request = list_first_entry(&ring->request_list, |
1786 | struct drm_i915_gem_request, | |
1787 | list); | |
1788 | ||
1789 | list_del(&request->list); | |
f787a5f5 | 1790 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
1791 | kfree(request); |
1792 | } | |
1793 | ||
1794 | while (!list_empty(&ring->active_list)) { | |
9375e446 CW |
1795 | struct drm_i915_gem_object *obj_priv; |
1796 | ||
dfaae392 | 1797 | obj_priv = list_first_entry(&ring->active_list, |
9375e446 CW |
1798 | struct drm_i915_gem_object, |
1799 | list); | |
1800 | ||
1801 | obj_priv->base.write_domain = 0; | |
dfaae392 | 1802 | list_del_init(&obj_priv->gpu_write_list); |
9375e446 CW |
1803 | i915_gem_object_move_to_inactive(&obj_priv->base); |
1804 | } | |
1805 | } | |
1806 | ||
069efc1d | 1807 | void i915_gem_reset(struct drm_device *dev) |
77f01230 CW |
1808 | { |
1809 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1810 | struct drm_i915_gem_object *obj_priv; | |
069efc1d | 1811 | int i; |
77f01230 | 1812 | |
dfaae392 CW |
1813 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->render_ring); |
1814 | if (HAS_BSD(dev)) | |
1815 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->bsd_ring); | |
1816 | ||
1817 | /* Remove anything from the flushing lists. The GPU cache is likely | |
1818 | * to be lost on reset along with the data, so simply move the | |
1819 | * lost bo to the inactive list. | |
1820 | */ | |
1821 | while (!list_empty(&dev_priv->mm.flushing_list)) { | |
1822 | obj_priv = list_first_entry(&dev_priv->mm.flushing_list, | |
1823 | struct drm_i915_gem_object, | |
1824 | list); | |
1825 | ||
1826 | obj_priv->base.write_domain = 0; | |
1827 | list_del_init(&obj_priv->gpu_write_list); | |
1828 | i915_gem_object_move_to_inactive(&obj_priv->base); | |
1829 | } | |
1830 | ||
1831 | /* Move everything out of the GPU domains to ensure we do any | |
1832 | * necessary invalidation upon reuse. | |
1833 | */ | |
77f01230 CW |
1834 | list_for_each_entry(obj_priv, |
1835 | &dev_priv->mm.inactive_list, | |
1836 | list) | |
1837 | { | |
1838 | obj_priv->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
1839 | } | |
069efc1d CW |
1840 | |
1841 | /* The fence registers are invalidated so clear them out */ | |
1842 | for (i = 0; i < 16; i++) { | |
1843 | struct drm_i915_fence_reg *reg; | |
1844 | ||
1845 | reg = &dev_priv->fence_regs[i]; | |
1846 | if (!reg->obj) | |
1847 | continue; | |
1848 | ||
1849 | i915_gem_clear_fence_reg(reg->obj); | |
1850 | } | |
77f01230 CW |
1851 | } |
1852 | ||
673a394b EA |
1853 | /** |
1854 | * This function clears the request list as sequence numbers are passed. | |
1855 | */ | |
b09a1fec CW |
1856 | static void |
1857 | i915_gem_retire_requests_ring(struct drm_device *dev, | |
1858 | struct intel_ring_buffer *ring) | |
673a394b EA |
1859 | { |
1860 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1861 | uint32_t seqno; | |
1862 | ||
b84d5f0c CW |
1863 | if (!ring->status_page.page_addr || |
1864 | list_empty(&ring->request_list)) | |
6c0594a3 KW |
1865 | return; |
1866 | ||
23bc5982 CW |
1867 | WARN_ON(i915_verify_lists(dev)); |
1868 | ||
f787a5f5 | 1869 | seqno = ring->get_seqno(dev, ring); |
852835f3 | 1870 | while (!list_empty(&ring->request_list)) { |
673a394b | 1871 | struct drm_i915_gem_request *request; |
673a394b | 1872 | |
852835f3 | 1873 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1874 | struct drm_i915_gem_request, |
1875 | list); | |
673a394b | 1876 | |
dfaae392 | 1877 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
1878 | break; |
1879 | ||
1880 | trace_i915_gem_request_retire(dev, request->seqno); | |
1881 | ||
1882 | list_del(&request->list); | |
f787a5f5 | 1883 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
1884 | kfree(request); |
1885 | } | |
1886 | ||
1887 | /* Move any buffers on the active list that are no longer referenced | |
1888 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1889 | */ | |
1890 | while (!list_empty(&ring->active_list)) { | |
1891 | struct drm_gem_object *obj; | |
1892 | struct drm_i915_gem_object *obj_priv; | |
1893 | ||
1894 | obj_priv = list_first_entry(&ring->active_list, | |
1895 | struct drm_i915_gem_object, | |
1896 | list); | |
673a394b | 1897 | |
dfaae392 | 1898 | if (!i915_seqno_passed(seqno, obj_priv->last_rendering_seqno)) |
673a394b | 1899 | break; |
b84d5f0c CW |
1900 | |
1901 | obj = &obj_priv->base; | |
b84d5f0c CW |
1902 | if (obj->write_domain != 0) |
1903 | i915_gem_object_move_to_flushing(obj); | |
1904 | else | |
1905 | i915_gem_object_move_to_inactive(obj); | |
673a394b | 1906 | } |
9d34e5db CW |
1907 | |
1908 | if (unlikely (dev_priv->trace_irq_seqno && | |
1909 | i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) { | |
8187a2b7 | 1910 | ring->user_irq_put(dev, ring); |
9d34e5db CW |
1911 | dev_priv->trace_irq_seqno = 0; |
1912 | } | |
23bc5982 CW |
1913 | |
1914 | WARN_ON(i915_verify_lists(dev)); | |
673a394b EA |
1915 | } |
1916 | ||
b09a1fec CW |
1917 | void |
1918 | i915_gem_retire_requests(struct drm_device *dev) | |
1919 | { | |
1920 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1921 | ||
be72615b CW |
1922 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
1923 | struct drm_i915_gem_object *obj_priv, *tmp; | |
1924 | ||
1925 | /* We must be careful that during unbind() we do not | |
1926 | * accidentally infinitely recurse into retire requests. | |
1927 | * Currently: | |
1928 | * retire -> free -> unbind -> wait -> retire_ring | |
1929 | */ | |
1930 | list_for_each_entry_safe(obj_priv, tmp, | |
1931 | &dev_priv->mm.deferred_free_list, | |
1932 | list) | |
1933 | i915_gem_free_object_tail(&obj_priv->base); | |
1934 | } | |
1935 | ||
b09a1fec CW |
1936 | i915_gem_retire_requests_ring(dev, &dev_priv->render_ring); |
1937 | if (HAS_BSD(dev)) | |
1938 | i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring); | |
1939 | } | |
1940 | ||
75ef9da2 | 1941 | static void |
673a394b EA |
1942 | i915_gem_retire_work_handler(struct work_struct *work) |
1943 | { | |
1944 | drm_i915_private_t *dev_priv; | |
1945 | struct drm_device *dev; | |
1946 | ||
1947 | dev_priv = container_of(work, drm_i915_private_t, | |
1948 | mm.retire_work.work); | |
1949 | dev = dev_priv->dev; | |
1950 | ||
891b48cf CW |
1951 | /* Come back later if the device is busy... */ |
1952 | if (!mutex_trylock(&dev->struct_mutex)) { | |
1953 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
1954 | return; | |
1955 | } | |
1956 | ||
b09a1fec | 1957 | i915_gem_retire_requests(dev); |
d1b851fc | 1958 | |
6dbe2772 | 1959 | if (!dev_priv->mm.suspended && |
d1b851fc ZN |
1960 | (!list_empty(&dev_priv->render_ring.request_list) || |
1961 | (HAS_BSD(dev) && | |
1962 | !list_empty(&dev_priv->bsd_ring.request_list)))) | |
9c9fe1f8 | 1963 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
673a394b EA |
1964 | mutex_unlock(&dev->struct_mutex); |
1965 | } | |
1966 | ||
5a5a0c64 | 1967 | int |
852835f3 | 1968 | i915_do_wait_request(struct drm_device *dev, uint32_t seqno, |
8a1a49f9 | 1969 | bool interruptible, struct intel_ring_buffer *ring) |
673a394b EA |
1970 | { |
1971 | drm_i915_private_t *dev_priv = dev->dev_private; | |
802c7eb6 | 1972 | u32 ier; |
673a394b EA |
1973 | int ret = 0; |
1974 | ||
1975 | BUG_ON(seqno == 0); | |
1976 | ||
30dbf0c0 CW |
1977 | if (atomic_read(&dev_priv->mm.wedged)) |
1978 | return -EAGAIN; | |
1979 | ||
a56ba56c | 1980 | if (ring->outstanding_lazy_request) { |
8dc5d147 | 1981 | seqno = i915_add_request(dev, NULL, NULL, ring); |
e35a41de DV |
1982 | if (seqno == 0) |
1983 | return -ENOMEM; | |
1984 | } | |
a56ba56c | 1985 | BUG_ON(seqno == dev_priv->next_seqno); |
e35a41de | 1986 | |
f787a5f5 | 1987 | if (!i915_seqno_passed(ring->get_seqno(dev, ring), seqno)) { |
bad720ff | 1988 | if (HAS_PCH_SPLIT(dev)) |
036a4a7d ZW |
1989 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
1990 | else | |
1991 | ier = I915_READ(IER); | |
802c7eb6 JB |
1992 | if (!ier) { |
1993 | DRM_ERROR("something (likely vbetool) disabled " | |
1994 | "interrupts, re-enabling\n"); | |
1995 | i915_driver_irq_preinstall(dev); | |
1996 | i915_driver_irq_postinstall(dev); | |
1997 | } | |
1998 | ||
1c5d22f7 CW |
1999 | trace_i915_gem_request_wait_begin(dev, seqno); |
2000 | ||
852835f3 | 2001 | ring->waiting_gem_seqno = seqno; |
8187a2b7 | 2002 | ring->user_irq_get(dev, ring); |
48764bf4 | 2003 | if (interruptible) |
852835f3 ZN |
2004 | ret = wait_event_interruptible(ring->irq_queue, |
2005 | i915_seqno_passed( | |
f787a5f5 | 2006 | ring->get_seqno(dev, ring), seqno) |
852835f3 | 2007 | || atomic_read(&dev_priv->mm.wedged)); |
48764bf4 | 2008 | else |
852835f3 ZN |
2009 | wait_event(ring->irq_queue, |
2010 | i915_seqno_passed( | |
f787a5f5 | 2011 | ring->get_seqno(dev, ring), seqno) |
852835f3 | 2012 | || atomic_read(&dev_priv->mm.wedged)); |
48764bf4 | 2013 | |
8187a2b7 | 2014 | ring->user_irq_put(dev, ring); |
852835f3 | 2015 | ring->waiting_gem_seqno = 0; |
1c5d22f7 CW |
2016 | |
2017 | trace_i915_gem_request_wait_end(dev, seqno); | |
673a394b | 2018 | } |
ba1234d1 | 2019 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 | 2020 | ret = -EAGAIN; |
673a394b EA |
2021 | |
2022 | if (ret && ret != -ERESTARTSYS) | |
8bff917c | 2023 | DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n", |
f787a5f5 | 2024 | __func__, ret, seqno, ring->get_seqno(dev, ring), |
8bff917c | 2025 | dev_priv->next_seqno); |
673a394b EA |
2026 | |
2027 | /* Directly dispatch request retiring. While we have the work queue | |
2028 | * to handle this, the waiter on a request often wants an associated | |
2029 | * buffer to have made it to the inactive list, and we would need | |
2030 | * a separate wait queue to handle that. | |
2031 | */ | |
2032 | if (ret == 0) | |
b09a1fec | 2033 | i915_gem_retire_requests_ring(dev, ring); |
673a394b EA |
2034 | |
2035 | return ret; | |
2036 | } | |
2037 | ||
48764bf4 DV |
2038 | /** |
2039 | * Waits for a sequence number to be signaled, and cleans up the | |
2040 | * request and object lists appropriately for that event. | |
2041 | */ | |
2042 | static int | |
852835f3 | 2043 | i915_wait_request(struct drm_device *dev, uint32_t seqno, |
a56ba56c | 2044 | struct intel_ring_buffer *ring) |
48764bf4 | 2045 | { |
852835f3 | 2046 | return i915_do_wait_request(dev, seqno, 1, ring); |
48764bf4 DV |
2047 | } |
2048 | ||
20f0cd55 | 2049 | static void |
9220434a | 2050 | i915_gem_flush_ring(struct drm_device *dev, |
c78ec30b | 2051 | struct drm_file *file_priv, |
9220434a CW |
2052 | struct intel_ring_buffer *ring, |
2053 | uint32_t invalidate_domains, | |
2054 | uint32_t flush_domains) | |
2055 | { | |
2056 | ring->flush(dev, ring, invalidate_domains, flush_domains); | |
2057 | i915_gem_process_flushing_list(dev, flush_domains, ring); | |
2058 | } | |
2059 | ||
8187a2b7 ZN |
2060 | static void |
2061 | i915_gem_flush(struct drm_device *dev, | |
c78ec30b | 2062 | struct drm_file *file_priv, |
8187a2b7 | 2063 | uint32_t invalidate_domains, |
9220434a CW |
2064 | uint32_t flush_domains, |
2065 | uint32_t flush_rings) | |
8187a2b7 ZN |
2066 | { |
2067 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8bff917c | 2068 | |
8187a2b7 ZN |
2069 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
2070 | drm_agp_chipset_flush(dev); | |
8bff917c | 2071 | |
9220434a CW |
2072 | if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) { |
2073 | if (flush_rings & RING_RENDER) | |
c78ec30b | 2074 | i915_gem_flush_ring(dev, file_priv, |
9220434a CW |
2075 | &dev_priv->render_ring, |
2076 | invalidate_domains, flush_domains); | |
2077 | if (flush_rings & RING_BSD) | |
c78ec30b | 2078 | i915_gem_flush_ring(dev, file_priv, |
9220434a CW |
2079 | &dev_priv->bsd_ring, |
2080 | invalidate_domains, flush_domains); | |
2081 | } | |
8187a2b7 ZN |
2082 | } |
2083 | ||
673a394b EA |
2084 | /** |
2085 | * Ensures that all rendering to the object has completed and the object is | |
2086 | * safe to unbind from the GTT or access from the CPU. | |
2087 | */ | |
2088 | static int | |
2cf34d7b CW |
2089 | i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
2090 | bool interruptible) | |
673a394b EA |
2091 | { |
2092 | struct drm_device *dev = obj->dev; | |
23010e43 | 2093 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2094 | int ret; |
2095 | ||
e47c68e9 EA |
2096 | /* This function only exists to support waiting for existing rendering, |
2097 | * not for emitting required flushes. | |
673a394b | 2098 | */ |
e47c68e9 | 2099 | BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
2100 | |
2101 | /* If there is rendering queued on the buffer being evicted, wait for | |
2102 | * it. | |
2103 | */ | |
2104 | if (obj_priv->active) { | |
2cf34d7b CW |
2105 | ret = i915_do_wait_request(dev, |
2106 | obj_priv->last_rendering_seqno, | |
2107 | interruptible, | |
2108 | obj_priv->ring); | |
2109 | if (ret) | |
673a394b EA |
2110 | return ret; |
2111 | } | |
2112 | ||
2113 | return 0; | |
2114 | } | |
2115 | ||
2116 | /** | |
2117 | * Unbinds an object from the GTT aperture. | |
2118 | */ | |
0f973f27 | 2119 | int |
673a394b EA |
2120 | i915_gem_object_unbind(struct drm_gem_object *obj) |
2121 | { | |
2122 | struct drm_device *dev = obj->dev; | |
73aa808f | 2123 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2124 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2125 | int ret = 0; |
2126 | ||
673a394b EA |
2127 | if (obj_priv->gtt_space == NULL) |
2128 | return 0; | |
2129 | ||
2130 | if (obj_priv->pin_count != 0) { | |
2131 | DRM_ERROR("Attempting to unbind pinned buffer\n"); | |
2132 | return -EINVAL; | |
2133 | } | |
2134 | ||
5323fd04 EA |
2135 | /* blow away mappings if mapped through GTT */ |
2136 | i915_gem_release_mmap(obj); | |
2137 | ||
673a394b EA |
2138 | /* Move the object to the CPU domain to ensure that |
2139 | * any possible CPU writes while it's not in the GTT | |
2140 | * are flushed when we go to remap it. This will | |
2141 | * also ensure that all pending GPU writes are finished | |
2142 | * before we unbind. | |
2143 | */ | |
e47c68e9 | 2144 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
8dc1775d | 2145 | if (ret == -ERESTARTSYS) |
673a394b | 2146 | return ret; |
8dc1775d CW |
2147 | /* Continue on if we fail due to EIO, the GPU is hung so we |
2148 | * should be safe and we need to cleanup or else we might | |
2149 | * cause memory corruption through use-after-free. | |
2150 | */ | |
812ed492 CW |
2151 | if (ret) { |
2152 | i915_gem_clflush_object(obj); | |
2153 | obj->read_domains = obj->write_domain = I915_GEM_DOMAIN_CPU; | |
2154 | } | |
673a394b | 2155 | |
96b47b65 DV |
2156 | /* release the fence reg _after_ flushing */ |
2157 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) | |
2158 | i915_gem_clear_fence_reg(obj); | |
2159 | ||
73aa808f CW |
2160 | drm_unbind_agp(obj_priv->agp_mem); |
2161 | drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE); | |
673a394b | 2162 | |
856fa198 | 2163 | i915_gem_object_put_pages(obj); |
a32808c0 | 2164 | BUG_ON(obj_priv->pages_refcount); |
673a394b | 2165 | |
73aa808f | 2166 | i915_gem_info_remove_gtt(dev_priv, obj->size); |
f13d3f73 | 2167 | list_del_init(&obj_priv->list); |
673a394b | 2168 | |
73aa808f CW |
2169 | drm_mm_put_block(obj_priv->gtt_space); |
2170 | obj_priv->gtt_space = NULL; | |
2171 | ||
963b4836 CW |
2172 | if (i915_gem_object_is_purgeable(obj_priv)) |
2173 | i915_gem_object_truncate(obj); | |
2174 | ||
1c5d22f7 CW |
2175 | trace_i915_gem_object_unbind(obj); |
2176 | ||
8dc1775d | 2177 | return ret; |
673a394b EA |
2178 | } |
2179 | ||
a56ba56c CW |
2180 | static int i915_ring_idle(struct drm_device *dev, |
2181 | struct intel_ring_buffer *ring) | |
2182 | { | |
2183 | i915_gem_flush_ring(dev, NULL, ring, | |
2184 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
2185 | return i915_wait_request(dev, | |
2186 | i915_gem_next_request_seqno(dev, ring), | |
2187 | ring); | |
2188 | } | |
2189 | ||
b47eb4a2 | 2190 | int |
4df2faf4 DV |
2191 | i915_gpu_idle(struct drm_device *dev) |
2192 | { | |
2193 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2194 | bool lists_empty; | |
852835f3 | 2195 | int ret; |
4df2faf4 | 2196 | |
d1b851fc ZN |
2197 | lists_empty = (list_empty(&dev_priv->mm.flushing_list) && |
2198 | list_empty(&dev_priv->render_ring.active_list) && | |
2199 | (!HAS_BSD(dev) || | |
2200 | list_empty(&dev_priv->bsd_ring.active_list))); | |
4df2faf4 DV |
2201 | if (lists_empty) |
2202 | return 0; | |
2203 | ||
2204 | /* Flush everything onto the inactive list. */ | |
a56ba56c | 2205 | ret = i915_ring_idle(dev, &dev_priv->render_ring); |
8a1a49f9 DV |
2206 | if (ret) |
2207 | return ret; | |
d1b851fc ZN |
2208 | |
2209 | if (HAS_BSD(dev)) { | |
a56ba56c | 2210 | ret = i915_ring_idle(dev, &dev_priv->bsd_ring); |
d1b851fc ZN |
2211 | if (ret) |
2212 | return ret; | |
2213 | } | |
2214 | ||
8a1a49f9 | 2215 | return 0; |
4df2faf4 DV |
2216 | } |
2217 | ||
5cdf5881 | 2218 | static int |
4bdadb97 CW |
2219 | i915_gem_object_get_pages(struct drm_gem_object *obj, |
2220 | gfp_t gfpmask) | |
673a394b | 2221 | { |
23010e43 | 2222 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2223 | int page_count, i; |
2224 | struct address_space *mapping; | |
2225 | struct inode *inode; | |
2226 | struct page *page; | |
673a394b | 2227 | |
778c3544 DV |
2228 | BUG_ON(obj_priv->pages_refcount |
2229 | == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT); | |
2230 | ||
856fa198 | 2231 | if (obj_priv->pages_refcount++ != 0) |
673a394b EA |
2232 | return 0; |
2233 | ||
2234 | /* Get the list of pages out of our struct file. They'll be pinned | |
2235 | * at this point until we release them. | |
2236 | */ | |
2237 | page_count = obj->size / PAGE_SIZE; | |
856fa198 | 2238 | BUG_ON(obj_priv->pages != NULL); |
8e7d2b2c | 2239 | obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *)); |
856fa198 | 2240 | if (obj_priv->pages == NULL) { |
856fa198 | 2241 | obj_priv->pages_refcount--; |
673a394b EA |
2242 | return -ENOMEM; |
2243 | } | |
2244 | ||
2245 | inode = obj->filp->f_path.dentry->d_inode; | |
2246 | mapping = inode->i_mapping; | |
2247 | for (i = 0; i < page_count; i++) { | |
4bdadb97 | 2248 | page = read_cache_page_gfp(mapping, i, |
985b823b | 2249 | GFP_HIGHUSER | |
4bdadb97 | 2250 | __GFP_COLD | |
cd9f040d | 2251 | __GFP_RECLAIMABLE | |
4bdadb97 | 2252 | gfpmask); |
1f2b1013 CW |
2253 | if (IS_ERR(page)) |
2254 | goto err_pages; | |
2255 | ||
856fa198 | 2256 | obj_priv->pages[i] = page; |
673a394b | 2257 | } |
280b713b EA |
2258 | |
2259 | if (obj_priv->tiling_mode != I915_TILING_NONE) | |
2260 | i915_gem_object_do_bit_17_swizzle(obj); | |
2261 | ||
673a394b | 2262 | return 0; |
1f2b1013 CW |
2263 | |
2264 | err_pages: | |
2265 | while (i--) | |
2266 | page_cache_release(obj_priv->pages[i]); | |
2267 | ||
2268 | drm_free_large(obj_priv->pages); | |
2269 | obj_priv->pages = NULL; | |
2270 | obj_priv->pages_refcount--; | |
2271 | return PTR_ERR(page); | |
673a394b EA |
2272 | } |
2273 | ||
4e901fdc EA |
2274 | static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg) |
2275 | { | |
2276 | struct drm_gem_object *obj = reg->obj; | |
2277 | struct drm_device *dev = obj->dev; | |
2278 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2279 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
4e901fdc EA |
2280 | int regnum = obj_priv->fence_reg; |
2281 | uint64_t val; | |
2282 | ||
2283 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & | |
2284 | 0xfffff000) << 32; | |
2285 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2286 | val |= (uint64_t)((obj_priv->stride / 128) - 1) << | |
2287 | SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2288 | ||
2289 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2290 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2291 | val |= I965_FENCE_REG_VALID; | |
2292 | ||
2293 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val); | |
2294 | } | |
2295 | ||
de151cf6 JB |
2296 | static void i965_write_fence_reg(struct drm_i915_fence_reg *reg) |
2297 | { | |
2298 | struct drm_gem_object *obj = reg->obj; | |
2299 | struct drm_device *dev = obj->dev; | |
2300 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2301 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
2302 | int regnum = obj_priv->fence_reg; |
2303 | uint64_t val; | |
2304 | ||
2305 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & | |
2306 | 0xfffff000) << 32; | |
2307 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2308 | val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2309 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2310 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2311 | val |= I965_FENCE_REG_VALID; | |
2312 | ||
2313 | I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val); | |
2314 | } | |
2315 | ||
2316 | static void i915_write_fence_reg(struct drm_i915_fence_reg *reg) | |
2317 | { | |
2318 | struct drm_gem_object *obj = reg->obj; | |
2319 | struct drm_device *dev = obj->dev; | |
2320 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2321 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 2322 | int regnum = obj_priv->fence_reg; |
0f973f27 | 2323 | int tile_width; |
dc529a4f | 2324 | uint32_t fence_reg, val; |
de151cf6 JB |
2325 | uint32_t pitch_val; |
2326 | ||
2327 | if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) || | |
2328 | (obj_priv->gtt_offset & (obj->size - 1))) { | |
f06da264 | 2329 | WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n", |
0f973f27 | 2330 | __func__, obj_priv->gtt_offset, obj->size); |
de151cf6 JB |
2331 | return; |
2332 | } | |
2333 | ||
0f973f27 JB |
2334 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2335 | HAS_128_BYTE_Y_TILING(dev)) | |
2336 | tile_width = 128; | |
de151cf6 | 2337 | else |
0f973f27 JB |
2338 | tile_width = 512; |
2339 | ||
2340 | /* Note: pitch better be a power of two tile widths */ | |
2341 | pitch_val = obj_priv->stride / tile_width; | |
2342 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2343 | |
c36a2a6d DV |
2344 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2345 | HAS_128_BYTE_Y_TILING(dev)) | |
2346 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2347 | else | |
2348 | WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL); | |
2349 | ||
de151cf6 JB |
2350 | val = obj_priv->gtt_offset; |
2351 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2352 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2353 | val |= I915_FENCE_SIZE_BITS(obj->size); | |
2354 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2355 | val |= I830_FENCE_REG_VALID; | |
2356 | ||
dc529a4f EA |
2357 | if (regnum < 8) |
2358 | fence_reg = FENCE_REG_830_0 + (regnum * 4); | |
2359 | else | |
2360 | fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4); | |
2361 | I915_WRITE(fence_reg, val); | |
de151cf6 JB |
2362 | } |
2363 | ||
2364 | static void i830_write_fence_reg(struct drm_i915_fence_reg *reg) | |
2365 | { | |
2366 | struct drm_gem_object *obj = reg->obj; | |
2367 | struct drm_device *dev = obj->dev; | |
2368 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2369 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
2370 | int regnum = obj_priv->fence_reg; |
2371 | uint32_t val; | |
2372 | uint32_t pitch_val; | |
8d7773a3 | 2373 | uint32_t fence_size_bits; |
de151cf6 | 2374 | |
8d7773a3 | 2375 | if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) || |
de151cf6 | 2376 | (obj_priv->gtt_offset & (obj->size - 1))) { |
8d7773a3 | 2377 | WARN(1, "%s: object 0x%08x not 512K or size aligned\n", |
0f973f27 | 2378 | __func__, obj_priv->gtt_offset); |
de151cf6 JB |
2379 | return; |
2380 | } | |
2381 | ||
e76a16de EA |
2382 | pitch_val = obj_priv->stride / 128; |
2383 | pitch_val = ffs(pitch_val) - 1; | |
2384 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2385 | ||
de151cf6 JB |
2386 | val = obj_priv->gtt_offset; |
2387 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2388 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
8d7773a3 DV |
2389 | fence_size_bits = I830_FENCE_SIZE_BITS(obj->size); |
2390 | WARN_ON(fence_size_bits & ~0x00000f00); | |
2391 | val |= fence_size_bits; | |
de151cf6 JB |
2392 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2393 | val |= I830_FENCE_REG_VALID; | |
2394 | ||
2395 | I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); | |
de151cf6 JB |
2396 | } |
2397 | ||
2cf34d7b CW |
2398 | static int i915_find_fence_reg(struct drm_device *dev, |
2399 | bool interruptible) | |
ae3db24a DV |
2400 | { |
2401 | struct drm_i915_fence_reg *reg = NULL; | |
2402 | struct drm_i915_gem_object *obj_priv = NULL; | |
2403 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2404 | struct drm_gem_object *obj = NULL; | |
2405 | int i, avail, ret; | |
2406 | ||
2407 | /* First try to find a free reg */ | |
2408 | avail = 0; | |
2409 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { | |
2410 | reg = &dev_priv->fence_regs[i]; | |
2411 | if (!reg->obj) | |
2412 | return i; | |
2413 | ||
23010e43 | 2414 | obj_priv = to_intel_bo(reg->obj); |
ae3db24a DV |
2415 | if (!obj_priv->pin_count) |
2416 | avail++; | |
2417 | } | |
2418 | ||
2419 | if (avail == 0) | |
2420 | return -ENOSPC; | |
2421 | ||
2422 | /* None available, try to steal one or wait for a user to finish */ | |
2423 | i = I915_FENCE_REG_NONE; | |
007cc8ac DV |
2424 | list_for_each_entry(reg, &dev_priv->mm.fence_list, |
2425 | lru_list) { | |
2426 | obj = reg->obj; | |
2427 | obj_priv = to_intel_bo(obj); | |
ae3db24a DV |
2428 | |
2429 | if (obj_priv->pin_count) | |
2430 | continue; | |
2431 | ||
2432 | /* found one! */ | |
2433 | i = obj_priv->fence_reg; | |
2434 | break; | |
2435 | } | |
2436 | ||
2437 | BUG_ON(i == I915_FENCE_REG_NONE); | |
2438 | ||
2439 | /* We only have a reference on obj from the active list. put_fence_reg | |
2440 | * might drop that one, causing a use-after-free in it. So hold a | |
2441 | * private reference to obj like the other callers of put_fence_reg | |
2442 | * (set_tiling ioctl) do. */ | |
2443 | drm_gem_object_reference(obj); | |
2cf34d7b | 2444 | ret = i915_gem_object_put_fence_reg(obj, interruptible); |
ae3db24a DV |
2445 | drm_gem_object_unreference(obj); |
2446 | if (ret != 0) | |
2447 | return ret; | |
2448 | ||
2449 | return i; | |
2450 | } | |
2451 | ||
de151cf6 JB |
2452 | /** |
2453 | * i915_gem_object_get_fence_reg - set up a fence reg for an object | |
2454 | * @obj: object to map through a fence reg | |
2455 | * | |
2456 | * When mapping objects through the GTT, userspace wants to be able to write | |
2457 | * to them without having to worry about swizzling if the object is tiled. | |
2458 | * | |
2459 | * This function walks the fence regs looking for a free one for @obj, | |
2460 | * stealing one if it can't find any. | |
2461 | * | |
2462 | * It then sets up the reg based on the object's properties: address, pitch | |
2463 | * and tiling format. | |
2464 | */ | |
8c4b8c3f | 2465 | int |
2cf34d7b CW |
2466 | i915_gem_object_get_fence_reg(struct drm_gem_object *obj, |
2467 | bool interruptible) | |
de151cf6 JB |
2468 | { |
2469 | struct drm_device *dev = obj->dev; | |
79e53945 | 2470 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2471 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 2472 | struct drm_i915_fence_reg *reg = NULL; |
ae3db24a | 2473 | int ret; |
de151cf6 | 2474 | |
a09ba7fa EA |
2475 | /* Just update our place in the LRU if our fence is getting used. */ |
2476 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
007cc8ac DV |
2477 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
2478 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); | |
a09ba7fa EA |
2479 | return 0; |
2480 | } | |
2481 | ||
de151cf6 JB |
2482 | switch (obj_priv->tiling_mode) { |
2483 | case I915_TILING_NONE: | |
2484 | WARN(1, "allocating a fence for non-tiled object?\n"); | |
2485 | break; | |
2486 | case I915_TILING_X: | |
0f973f27 JB |
2487 | if (!obj_priv->stride) |
2488 | return -EINVAL; | |
2489 | WARN((obj_priv->stride & (512 - 1)), | |
2490 | "object 0x%08x is X tiled but has non-512B pitch\n", | |
2491 | obj_priv->gtt_offset); | |
de151cf6 JB |
2492 | break; |
2493 | case I915_TILING_Y: | |
0f973f27 JB |
2494 | if (!obj_priv->stride) |
2495 | return -EINVAL; | |
2496 | WARN((obj_priv->stride & (128 - 1)), | |
2497 | "object 0x%08x is Y tiled but has non-128B pitch\n", | |
2498 | obj_priv->gtt_offset); | |
de151cf6 JB |
2499 | break; |
2500 | } | |
2501 | ||
2cf34d7b | 2502 | ret = i915_find_fence_reg(dev, interruptible); |
ae3db24a DV |
2503 | if (ret < 0) |
2504 | return ret; | |
de151cf6 | 2505 | |
ae3db24a DV |
2506 | obj_priv->fence_reg = ret; |
2507 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; | |
007cc8ac | 2508 | list_add_tail(®->lru_list, &dev_priv->mm.fence_list); |
a09ba7fa | 2509 | |
de151cf6 JB |
2510 | reg->obj = obj; |
2511 | ||
e259befd CW |
2512 | switch (INTEL_INFO(dev)->gen) { |
2513 | case 6: | |
4e901fdc | 2514 | sandybridge_write_fence_reg(reg); |
e259befd CW |
2515 | break; |
2516 | case 5: | |
2517 | case 4: | |
de151cf6 | 2518 | i965_write_fence_reg(reg); |
e259befd CW |
2519 | break; |
2520 | case 3: | |
de151cf6 | 2521 | i915_write_fence_reg(reg); |
e259befd CW |
2522 | break; |
2523 | case 2: | |
de151cf6 | 2524 | i830_write_fence_reg(reg); |
e259befd CW |
2525 | break; |
2526 | } | |
d9ddcb96 | 2527 | |
ae3db24a DV |
2528 | trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg, |
2529 | obj_priv->tiling_mode); | |
1c5d22f7 | 2530 | |
d9ddcb96 | 2531 | return 0; |
de151cf6 JB |
2532 | } |
2533 | ||
2534 | /** | |
2535 | * i915_gem_clear_fence_reg - clear out fence register info | |
2536 | * @obj: object to clear | |
2537 | * | |
2538 | * Zeroes out the fence register itself and clears out the associated | |
2539 | * data structures in dev_priv and obj_priv. | |
2540 | */ | |
2541 | static void | |
2542 | i915_gem_clear_fence_reg(struct drm_gem_object *obj) | |
2543 | { | |
2544 | struct drm_device *dev = obj->dev; | |
79e53945 | 2545 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 2546 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
007cc8ac DV |
2547 | struct drm_i915_fence_reg *reg = |
2548 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
e259befd | 2549 | uint32_t fence_reg; |
de151cf6 | 2550 | |
e259befd CW |
2551 | switch (INTEL_INFO(dev)->gen) { |
2552 | case 6: | |
4e901fdc EA |
2553 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + |
2554 | (obj_priv->fence_reg * 8), 0); | |
e259befd CW |
2555 | break; |
2556 | case 5: | |
2557 | case 4: | |
de151cf6 | 2558 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); |
e259befd CW |
2559 | break; |
2560 | case 3: | |
9b74f734 | 2561 | if (obj_priv->fence_reg >= 8) |
e259befd | 2562 | fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4; |
dc529a4f | 2563 | else |
e259befd CW |
2564 | case 2: |
2565 | fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4; | |
dc529a4f EA |
2566 | |
2567 | I915_WRITE(fence_reg, 0); | |
e259befd | 2568 | break; |
dc529a4f | 2569 | } |
de151cf6 | 2570 | |
007cc8ac | 2571 | reg->obj = NULL; |
de151cf6 | 2572 | obj_priv->fence_reg = I915_FENCE_REG_NONE; |
007cc8ac | 2573 | list_del_init(®->lru_list); |
de151cf6 JB |
2574 | } |
2575 | ||
52dc7d32 CW |
2576 | /** |
2577 | * i915_gem_object_put_fence_reg - waits on outstanding fenced access | |
2578 | * to the buffer to finish, and then resets the fence register. | |
2579 | * @obj: tiled object holding a fence register. | |
2cf34d7b | 2580 | * @bool: whether the wait upon the fence is interruptible |
52dc7d32 CW |
2581 | * |
2582 | * Zeroes out the fence register itself and clears out the associated | |
2583 | * data structures in dev_priv and obj_priv. | |
2584 | */ | |
2585 | int | |
2cf34d7b CW |
2586 | i915_gem_object_put_fence_reg(struct drm_gem_object *obj, |
2587 | bool interruptible) | |
52dc7d32 CW |
2588 | { |
2589 | struct drm_device *dev = obj->dev; | |
53640e1d | 2590 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2591 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
53640e1d | 2592 | struct drm_i915_fence_reg *reg; |
52dc7d32 CW |
2593 | |
2594 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE) | |
2595 | return 0; | |
2596 | ||
10ae9bd2 DV |
2597 | /* If we've changed tiling, GTT-mappings of the object |
2598 | * need to re-fault to ensure that the correct fence register | |
2599 | * setup is in place. | |
2600 | */ | |
2601 | i915_gem_release_mmap(obj); | |
2602 | ||
52dc7d32 CW |
2603 | /* On the i915, GPU access to tiled buffers is via a fence, |
2604 | * therefore we must wait for any outstanding access to complete | |
2605 | * before clearing the fence. | |
2606 | */ | |
53640e1d CW |
2607 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
2608 | if (reg->gpu) { | |
52dc7d32 CW |
2609 | int ret; |
2610 | ||
2cf34d7b | 2611 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
0bc23aad CW |
2612 | if (ret) |
2613 | return ret; | |
2614 | ||
2cf34d7b | 2615 | ret = i915_gem_object_wait_rendering(obj, interruptible); |
0bc23aad | 2616 | if (ret) |
52dc7d32 | 2617 | return ret; |
53640e1d CW |
2618 | |
2619 | reg->gpu = false; | |
52dc7d32 CW |
2620 | } |
2621 | ||
4a726612 | 2622 | i915_gem_object_flush_gtt_write_domain(obj); |
0bc23aad | 2623 | i915_gem_clear_fence_reg(obj); |
52dc7d32 CW |
2624 | |
2625 | return 0; | |
2626 | } | |
2627 | ||
673a394b EA |
2628 | /** |
2629 | * Finds free space in the GTT aperture and binds the object there. | |
2630 | */ | |
2631 | static int | |
2632 | i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment) | |
2633 | { | |
2634 | struct drm_device *dev = obj->dev; | |
2635 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2636 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 2637 | struct drm_mm_node *free_space; |
4bdadb97 | 2638 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
07f73f69 | 2639 | int ret; |
673a394b | 2640 | |
bb6baf76 | 2641 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2642 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2643 | return -EINVAL; | |
2644 | } | |
2645 | ||
673a394b | 2646 | if (alignment == 0) |
0f973f27 | 2647 | alignment = i915_gem_get_gtt_alignment(obj); |
8d7773a3 | 2648 | if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) { |
673a394b EA |
2649 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2650 | return -EINVAL; | |
2651 | } | |
2652 | ||
654fc607 CW |
2653 | /* If the object is bigger than the entire aperture, reject it early |
2654 | * before evicting everything in a vain attempt to find space. | |
2655 | */ | |
73aa808f | 2656 | if (obj->size > dev_priv->mm.gtt_total) { |
654fc607 CW |
2657 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2658 | return -E2BIG; | |
2659 | } | |
2660 | ||
673a394b EA |
2661 | search_free: |
2662 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
2663 | obj->size, alignment, 0); | |
2664 | if (free_space != NULL) { | |
2665 | obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size, | |
2666 | alignment); | |
db3307a9 | 2667 | if (obj_priv->gtt_space != NULL) |
673a394b | 2668 | obj_priv->gtt_offset = obj_priv->gtt_space->start; |
673a394b EA |
2669 | } |
2670 | if (obj_priv->gtt_space == NULL) { | |
2671 | /* If the gtt is empty and we're still having trouble | |
2672 | * fitting our object in, we're out of memory. | |
2673 | */ | |
0108a3ed | 2674 | ret = i915_gem_evict_something(dev, obj->size, alignment); |
9731129c | 2675 | if (ret) |
673a394b | 2676 | return ret; |
9731129c | 2677 | |
673a394b EA |
2678 | goto search_free; |
2679 | } | |
2680 | ||
4bdadb97 | 2681 | ret = i915_gem_object_get_pages(obj, gfpmask); |
673a394b EA |
2682 | if (ret) { |
2683 | drm_mm_put_block(obj_priv->gtt_space); | |
2684 | obj_priv->gtt_space = NULL; | |
07f73f69 CW |
2685 | |
2686 | if (ret == -ENOMEM) { | |
2687 | /* first try to clear up some space from the GTT */ | |
0108a3ed DV |
2688 | ret = i915_gem_evict_something(dev, obj->size, |
2689 | alignment); | |
07f73f69 | 2690 | if (ret) { |
07f73f69 | 2691 | /* now try to shrink everyone else */ |
4bdadb97 CW |
2692 | if (gfpmask) { |
2693 | gfpmask = 0; | |
2694 | goto search_free; | |
07f73f69 CW |
2695 | } |
2696 | ||
2697 | return ret; | |
2698 | } | |
2699 | ||
2700 | goto search_free; | |
2701 | } | |
2702 | ||
673a394b EA |
2703 | return ret; |
2704 | } | |
2705 | ||
673a394b EA |
2706 | /* Create an AGP memory structure pointing at our pages, and bind it |
2707 | * into the GTT. | |
2708 | */ | |
2709 | obj_priv->agp_mem = drm_agp_bind_pages(dev, | |
856fa198 | 2710 | obj_priv->pages, |
07f73f69 | 2711 | obj->size >> PAGE_SHIFT, |
ba1eb1d8 KP |
2712 | obj_priv->gtt_offset, |
2713 | obj_priv->agp_type); | |
673a394b | 2714 | if (obj_priv->agp_mem == NULL) { |
856fa198 | 2715 | i915_gem_object_put_pages(obj); |
673a394b EA |
2716 | drm_mm_put_block(obj_priv->gtt_space); |
2717 | obj_priv->gtt_space = NULL; | |
07f73f69 | 2718 | |
0108a3ed | 2719 | ret = i915_gem_evict_something(dev, obj->size, alignment); |
9731129c | 2720 | if (ret) |
07f73f69 | 2721 | return ret; |
07f73f69 CW |
2722 | |
2723 | goto search_free; | |
673a394b | 2724 | } |
673a394b | 2725 | |
bf1a1092 CW |
2726 | /* keep track of bounds object by adding it to the inactive list */ |
2727 | list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list); | |
73aa808f | 2728 | i915_gem_info_add_gtt(dev_priv, obj->size); |
bf1a1092 | 2729 | |
673a394b EA |
2730 | /* Assert that the object is not currently in any GPU domain. As it |
2731 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2732 | * a GPU cache | |
2733 | */ | |
21d509e3 CW |
2734 | BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS); |
2735 | BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2736 | |
1c5d22f7 CW |
2737 | trace_i915_gem_object_bind(obj, obj_priv->gtt_offset); |
2738 | ||
673a394b EA |
2739 | return 0; |
2740 | } | |
2741 | ||
2742 | void | |
2743 | i915_gem_clflush_object(struct drm_gem_object *obj) | |
2744 | { | |
23010e43 | 2745 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2746 | |
2747 | /* If we don't have a page list set up, then we're not pinned | |
2748 | * to GPU, and we can ignore the cache flush because it'll happen | |
2749 | * again at bind time. | |
2750 | */ | |
856fa198 | 2751 | if (obj_priv->pages == NULL) |
673a394b EA |
2752 | return; |
2753 | ||
1c5d22f7 | 2754 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2755 | |
856fa198 | 2756 | drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE); |
673a394b EA |
2757 | } |
2758 | ||
e47c68e9 | 2759 | /** Flushes any GPU write domain for the object if it's dirty. */ |
2dafb1e0 | 2760 | static int |
ba3d8d74 DV |
2761 | i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, |
2762 | bool pipelined) | |
e47c68e9 EA |
2763 | { |
2764 | struct drm_device *dev = obj->dev; | |
1c5d22f7 | 2765 | uint32_t old_write_domain; |
e47c68e9 EA |
2766 | |
2767 | if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) | |
2dafb1e0 | 2768 | return 0; |
e47c68e9 EA |
2769 | |
2770 | /* Queue the GPU write cache flushing we need. */ | |
1c5d22f7 | 2771 | old_write_domain = obj->write_domain; |
c78ec30b | 2772 | i915_gem_flush_ring(dev, NULL, |
9220434a CW |
2773 | to_intel_bo(obj)->ring, |
2774 | 0, obj->write_domain); | |
48b956c5 | 2775 | BUG_ON(obj->write_domain); |
1c5d22f7 CW |
2776 | |
2777 | trace_i915_gem_object_change_domain(obj, | |
2778 | obj->read_domains, | |
2779 | old_write_domain); | |
ba3d8d74 DV |
2780 | |
2781 | if (pipelined) | |
2782 | return 0; | |
2783 | ||
2cf34d7b | 2784 | return i915_gem_object_wait_rendering(obj, true); |
e47c68e9 EA |
2785 | } |
2786 | ||
2787 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2788 | static void | |
2789 | i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj) | |
2790 | { | |
1c5d22f7 CW |
2791 | uint32_t old_write_domain; |
2792 | ||
e47c68e9 EA |
2793 | if (obj->write_domain != I915_GEM_DOMAIN_GTT) |
2794 | return; | |
2795 | ||
2796 | /* No actual flushing is required for the GTT write domain. Writes | |
2797 | * to it immediately go to main memory as far as we know, so there's | |
2798 | * no chipset flush. It also doesn't land in render cache. | |
2799 | */ | |
1c5d22f7 | 2800 | old_write_domain = obj->write_domain; |
e47c68e9 | 2801 | obj->write_domain = 0; |
1c5d22f7 CW |
2802 | |
2803 | trace_i915_gem_object_change_domain(obj, | |
2804 | obj->read_domains, | |
2805 | old_write_domain); | |
e47c68e9 EA |
2806 | } |
2807 | ||
2808 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2809 | static void | |
2810 | i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj) | |
2811 | { | |
2812 | struct drm_device *dev = obj->dev; | |
1c5d22f7 | 2813 | uint32_t old_write_domain; |
e47c68e9 EA |
2814 | |
2815 | if (obj->write_domain != I915_GEM_DOMAIN_CPU) | |
2816 | return; | |
2817 | ||
2818 | i915_gem_clflush_object(obj); | |
2819 | drm_agp_chipset_flush(dev); | |
1c5d22f7 | 2820 | old_write_domain = obj->write_domain; |
e47c68e9 | 2821 | obj->write_domain = 0; |
1c5d22f7 CW |
2822 | |
2823 | trace_i915_gem_object_change_domain(obj, | |
2824 | obj->read_domains, | |
2825 | old_write_domain); | |
e47c68e9 EA |
2826 | } |
2827 | ||
2ef7eeaa EA |
2828 | /** |
2829 | * Moves a single object to the GTT read, and possibly write domain. | |
2830 | * | |
2831 | * This function returns when the move is complete, including waiting on | |
2832 | * flushes to occur. | |
2833 | */ | |
79e53945 | 2834 | int |
2ef7eeaa EA |
2835 | i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) |
2836 | { | |
23010e43 | 2837 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 2838 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2839 | int ret; |
2ef7eeaa | 2840 | |
02354392 EA |
2841 | /* Not valid to be called on unbound objects. */ |
2842 | if (obj_priv->gtt_space == NULL) | |
2843 | return -EINVAL; | |
2844 | ||
ba3d8d74 | 2845 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 EA |
2846 | if (ret != 0) |
2847 | return ret; | |
2848 | ||
7213342d | 2849 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 2850 | |
ba3d8d74 | 2851 | if (write) { |
2cf34d7b | 2852 | ret = i915_gem_object_wait_rendering(obj, true); |
ba3d8d74 DV |
2853 | if (ret) |
2854 | return ret; | |
ba3d8d74 | 2855 | } |
2ef7eeaa | 2856 | |
7213342d CW |
2857 | old_write_domain = obj->write_domain; |
2858 | old_read_domains = obj->read_domains; | |
2ef7eeaa | 2859 | |
e47c68e9 EA |
2860 | /* It should now be out of any other write domains, and we can update |
2861 | * the domain values for our changes. | |
2862 | */ | |
2863 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); | |
2864 | obj->read_domains |= I915_GEM_DOMAIN_GTT; | |
2865 | if (write) { | |
7213342d | 2866 | obj->read_domains = I915_GEM_DOMAIN_GTT; |
e47c68e9 EA |
2867 | obj->write_domain = I915_GEM_DOMAIN_GTT; |
2868 | obj_priv->dirty = 1; | |
2ef7eeaa EA |
2869 | } |
2870 | ||
1c5d22f7 CW |
2871 | trace_i915_gem_object_change_domain(obj, |
2872 | old_read_domains, | |
2873 | old_write_domain); | |
2874 | ||
e47c68e9 EA |
2875 | return 0; |
2876 | } | |
2877 | ||
b9241ea3 ZW |
2878 | /* |
2879 | * Prepare buffer for display plane. Use uninterruptible for possible flush | |
2880 | * wait, as in modesetting process we're not supposed to be interrupted. | |
2881 | */ | |
2882 | int | |
48b956c5 CW |
2883 | i915_gem_object_set_to_display_plane(struct drm_gem_object *obj, |
2884 | bool pipelined) | |
b9241ea3 | 2885 | { |
23010e43 | 2886 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ba3d8d74 | 2887 | uint32_t old_read_domains; |
b9241ea3 ZW |
2888 | int ret; |
2889 | ||
2890 | /* Not valid to be called on unbound objects. */ | |
2891 | if (obj_priv->gtt_space == NULL) | |
2892 | return -EINVAL; | |
2893 | ||
ced270fa | 2894 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
48b956c5 | 2895 | if (ret) |
e35a41de | 2896 | return ret; |
b9241ea3 | 2897 | |
ced270fa CW |
2898 | /* Currently, we are always called from an non-interruptible context. */ |
2899 | if (!pipelined) { | |
2900 | ret = i915_gem_object_wait_rendering(obj, false); | |
2901 | if (ret) | |
2902 | return ret; | |
2903 | } | |
2904 | ||
b118c1e3 CW |
2905 | i915_gem_object_flush_cpu_write_domain(obj); |
2906 | ||
b9241ea3 | 2907 | old_read_domains = obj->read_domains; |
c78ec30b | 2908 | obj->read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
2909 | |
2910 | trace_i915_gem_object_change_domain(obj, | |
2911 | old_read_domains, | |
ba3d8d74 | 2912 | obj->write_domain); |
b9241ea3 ZW |
2913 | |
2914 | return 0; | |
2915 | } | |
2916 | ||
e47c68e9 EA |
2917 | /** |
2918 | * Moves a single object to the CPU read, and possibly write domain. | |
2919 | * | |
2920 | * This function returns when the move is complete, including waiting on | |
2921 | * flushes to occur. | |
2922 | */ | |
2923 | static int | |
2924 | i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) | |
2925 | { | |
1c5d22f7 | 2926 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
2927 | int ret; |
2928 | ||
ba3d8d74 | 2929 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 EA |
2930 | if (ret != 0) |
2931 | return ret; | |
2ef7eeaa | 2932 | |
e47c68e9 | 2933 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 2934 | |
e47c68e9 EA |
2935 | /* If we have a partially-valid cache of the object in the CPU, |
2936 | * finish invalidating it and free the per-page flags. | |
2ef7eeaa | 2937 | */ |
e47c68e9 | 2938 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
2ef7eeaa | 2939 | |
7213342d | 2940 | if (write) { |
2cf34d7b | 2941 | ret = i915_gem_object_wait_rendering(obj, true); |
7213342d CW |
2942 | if (ret) |
2943 | return ret; | |
2944 | } | |
2945 | ||
1c5d22f7 CW |
2946 | old_write_domain = obj->write_domain; |
2947 | old_read_domains = obj->read_domains; | |
2948 | ||
e47c68e9 EA |
2949 | /* Flush the CPU cache if it's still invalid. */ |
2950 | if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) { | |
2ef7eeaa | 2951 | i915_gem_clflush_object(obj); |
2ef7eeaa | 2952 | |
e47c68e9 | 2953 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
2954 | } |
2955 | ||
2956 | /* It should now be out of any other write domains, and we can update | |
2957 | * the domain values for our changes. | |
2958 | */ | |
e47c68e9 EA |
2959 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
2960 | ||
2961 | /* If we're writing through the CPU, then the GPU read domains will | |
2962 | * need to be invalidated at next use. | |
2963 | */ | |
2964 | if (write) { | |
c78ec30b | 2965 | obj->read_domains = I915_GEM_DOMAIN_CPU; |
e47c68e9 EA |
2966 | obj->write_domain = I915_GEM_DOMAIN_CPU; |
2967 | } | |
2ef7eeaa | 2968 | |
1c5d22f7 CW |
2969 | trace_i915_gem_object_change_domain(obj, |
2970 | old_read_domains, | |
2971 | old_write_domain); | |
2972 | ||
2ef7eeaa EA |
2973 | return 0; |
2974 | } | |
2975 | ||
673a394b EA |
2976 | /* |
2977 | * Set the next domain for the specified object. This | |
2978 | * may not actually perform the necessary flushing/invaliding though, | |
2979 | * as that may want to be batched with other set_domain operations | |
2980 | * | |
2981 | * This is (we hope) the only really tricky part of gem. The goal | |
2982 | * is fairly simple -- track which caches hold bits of the object | |
2983 | * and make sure they remain coherent. A few concrete examples may | |
2984 | * help to explain how it works. For shorthand, we use the notation | |
2985 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the | |
2986 | * a pair of read and write domain masks. | |
2987 | * | |
2988 | * Case 1: the batch buffer | |
2989 | * | |
2990 | * 1. Allocated | |
2991 | * 2. Written by CPU | |
2992 | * 3. Mapped to GTT | |
2993 | * 4. Read by GPU | |
2994 | * 5. Unmapped from GTT | |
2995 | * 6. Freed | |
2996 | * | |
2997 | * Let's take these a step at a time | |
2998 | * | |
2999 | * 1. Allocated | |
3000 | * Pages allocated from the kernel may still have | |
3001 | * cache contents, so we set them to (CPU, CPU) always. | |
3002 | * 2. Written by CPU (using pwrite) | |
3003 | * The pwrite function calls set_domain (CPU, CPU) and | |
3004 | * this function does nothing (as nothing changes) | |
3005 | * 3. Mapped by GTT | |
3006 | * This function asserts that the object is not | |
3007 | * currently in any GPU-based read or write domains | |
3008 | * 4. Read by GPU | |
3009 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). | |
3010 | * As write_domain is zero, this function adds in the | |
3011 | * current read domains (CPU+COMMAND, 0). | |
3012 | * flush_domains is set to CPU. | |
3013 | * invalidate_domains is set to COMMAND | |
3014 | * clflush is run to get data out of the CPU caches | |
3015 | * then i915_dev_set_domain calls i915_gem_flush to | |
3016 | * emit an MI_FLUSH and drm_agp_chipset_flush | |
3017 | * 5. Unmapped from GTT | |
3018 | * i915_gem_object_unbind calls set_domain (CPU, CPU) | |
3019 | * flush_domains and invalidate_domains end up both zero | |
3020 | * so no flushing/invalidating happens | |
3021 | * 6. Freed | |
3022 | * yay, done | |
3023 | * | |
3024 | * Case 2: The shared render buffer | |
3025 | * | |
3026 | * 1. Allocated | |
3027 | * 2. Mapped to GTT | |
3028 | * 3. Read/written by GPU | |
3029 | * 4. set_domain to (CPU,CPU) | |
3030 | * 5. Read/written by CPU | |
3031 | * 6. Read/written by GPU | |
3032 | * | |
3033 | * 1. Allocated | |
3034 | * Same as last example, (CPU, CPU) | |
3035 | * 2. Mapped to GTT | |
3036 | * Nothing changes (assertions find that it is not in the GPU) | |
3037 | * 3. Read/written by GPU | |
3038 | * execbuffer calls set_domain (RENDER, RENDER) | |
3039 | * flush_domains gets CPU | |
3040 | * invalidate_domains gets GPU | |
3041 | * clflush (obj) | |
3042 | * MI_FLUSH and drm_agp_chipset_flush | |
3043 | * 4. set_domain (CPU, CPU) | |
3044 | * flush_domains gets GPU | |
3045 | * invalidate_domains gets CPU | |
3046 | * wait_rendering (obj) to make sure all drawing is complete. | |
3047 | * This will include an MI_FLUSH to get the data from GPU | |
3048 | * to memory | |
3049 | * clflush (obj) to invalidate the CPU cache | |
3050 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) | |
3051 | * 5. Read/written by CPU | |
3052 | * cache lines are loaded and dirtied | |
3053 | * 6. Read written by GPU | |
3054 | * Same as last GPU access | |
3055 | * | |
3056 | * Case 3: The constant buffer | |
3057 | * | |
3058 | * 1. Allocated | |
3059 | * 2. Written by CPU | |
3060 | * 3. Read by GPU | |
3061 | * 4. Updated (written) by CPU again | |
3062 | * 5. Read by GPU | |
3063 | * | |
3064 | * 1. Allocated | |
3065 | * (CPU, CPU) | |
3066 | * 2. Written by CPU | |
3067 | * (CPU, CPU) | |
3068 | * 3. Read by GPU | |
3069 | * (CPU+RENDER, 0) | |
3070 | * flush_domains = CPU | |
3071 | * invalidate_domains = RENDER | |
3072 | * clflush (obj) | |
3073 | * MI_FLUSH | |
3074 | * drm_agp_chipset_flush | |
3075 | * 4. Updated (written) by CPU again | |
3076 | * (CPU, CPU) | |
3077 | * flush_domains = 0 (no previous write domain) | |
3078 | * invalidate_domains = 0 (no new read domains) | |
3079 | * 5. Read by GPU | |
3080 | * (CPU+RENDER, 0) | |
3081 | * flush_domains = CPU | |
3082 | * invalidate_domains = RENDER | |
3083 | * clflush (obj) | |
3084 | * MI_FLUSH | |
3085 | * drm_agp_chipset_flush | |
3086 | */ | |
c0d90829 | 3087 | static void |
8b0e378a | 3088 | i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj) |
673a394b EA |
3089 | { |
3090 | struct drm_device *dev = obj->dev; | |
9220434a | 3091 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 3092 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
3093 | uint32_t invalidate_domains = 0; |
3094 | uint32_t flush_domains = 0; | |
1c5d22f7 | 3095 | uint32_t old_read_domains; |
e47c68e9 | 3096 | |
652c393a JB |
3097 | intel_mark_busy(dev, obj); |
3098 | ||
673a394b EA |
3099 | /* |
3100 | * If the object isn't moving to a new write domain, | |
3101 | * let the object stay in multiple read domains | |
3102 | */ | |
8b0e378a EA |
3103 | if (obj->pending_write_domain == 0) |
3104 | obj->pending_read_domains |= obj->read_domains; | |
673a394b EA |
3105 | else |
3106 | obj_priv->dirty = 1; | |
3107 | ||
3108 | /* | |
3109 | * Flush the current write domain if | |
3110 | * the new read domains don't match. Invalidate | |
3111 | * any read domains which differ from the old | |
3112 | * write domain | |
3113 | */ | |
8b0e378a EA |
3114 | if (obj->write_domain && |
3115 | obj->write_domain != obj->pending_read_domains) { | |
673a394b | 3116 | flush_domains |= obj->write_domain; |
8b0e378a EA |
3117 | invalidate_domains |= |
3118 | obj->pending_read_domains & ~obj->write_domain; | |
673a394b EA |
3119 | } |
3120 | /* | |
3121 | * Invalidate any read caches which may have | |
3122 | * stale data. That is, any new read domains. | |
3123 | */ | |
8b0e378a | 3124 | invalidate_domains |= obj->pending_read_domains & ~obj->read_domains; |
3d2a812a | 3125 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) |
673a394b | 3126 | i915_gem_clflush_object(obj); |
673a394b | 3127 | |
1c5d22f7 CW |
3128 | old_read_domains = obj->read_domains; |
3129 | ||
efbeed96 EA |
3130 | /* The actual obj->write_domain will be updated with |
3131 | * pending_write_domain after we emit the accumulated flush for all | |
3132 | * of our domain changes in execbuffers (which clears objects' | |
3133 | * write_domains). So if we have a current write domain that we | |
3134 | * aren't changing, set pending_write_domain to that. | |
3135 | */ | |
3136 | if (flush_domains == 0 && obj->pending_write_domain == 0) | |
3137 | obj->pending_write_domain = obj->write_domain; | |
8b0e378a | 3138 | obj->read_domains = obj->pending_read_domains; |
673a394b EA |
3139 | |
3140 | dev->invalidate_domains |= invalidate_domains; | |
3141 | dev->flush_domains |= flush_domains; | |
9220434a CW |
3142 | if (obj_priv->ring) |
3143 | dev_priv->mm.flush_rings |= obj_priv->ring->id; | |
1c5d22f7 CW |
3144 | |
3145 | trace_i915_gem_object_change_domain(obj, | |
3146 | old_read_domains, | |
3147 | obj->write_domain); | |
673a394b EA |
3148 | } |
3149 | ||
3150 | /** | |
e47c68e9 | 3151 | * Moves the object from a partially CPU read to a full one. |
673a394b | 3152 | * |
e47c68e9 EA |
3153 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
3154 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). | |
673a394b | 3155 | */ |
e47c68e9 EA |
3156 | static void |
3157 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj) | |
673a394b | 3158 | { |
23010e43 | 3159 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 3160 | |
e47c68e9 EA |
3161 | if (!obj_priv->page_cpu_valid) |
3162 | return; | |
3163 | ||
3164 | /* If we're partially in the CPU read domain, finish moving it in. | |
3165 | */ | |
3166 | if (obj->read_domains & I915_GEM_DOMAIN_CPU) { | |
3167 | int i; | |
3168 | ||
3169 | for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) { | |
3170 | if (obj_priv->page_cpu_valid[i]) | |
3171 | continue; | |
856fa198 | 3172 | drm_clflush_pages(obj_priv->pages + i, 1); |
e47c68e9 | 3173 | } |
e47c68e9 EA |
3174 | } |
3175 | ||
3176 | /* Free the page_cpu_valid mappings which are now stale, whether | |
3177 | * or not we've got I915_GEM_DOMAIN_CPU. | |
3178 | */ | |
9a298b2a | 3179 | kfree(obj_priv->page_cpu_valid); |
e47c68e9 EA |
3180 | obj_priv->page_cpu_valid = NULL; |
3181 | } | |
3182 | ||
3183 | /** | |
3184 | * Set the CPU read domain on a range of the object. | |
3185 | * | |
3186 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's | |
3187 | * not entirely valid. The page_cpu_valid member of the object flags which | |
3188 | * pages have been flushed, and will be respected by | |
3189 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping | |
3190 | * of the whole object. | |
3191 | * | |
3192 | * This function returns when the move is complete, including waiting on | |
3193 | * flushes to occur. | |
3194 | */ | |
3195 | static int | |
3196 | i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
3197 | uint64_t offset, uint64_t size) | |
3198 | { | |
23010e43 | 3199 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 3200 | uint32_t old_read_domains; |
e47c68e9 | 3201 | int i, ret; |
673a394b | 3202 | |
e47c68e9 EA |
3203 | if (offset == 0 && size == obj->size) |
3204 | return i915_gem_object_set_to_cpu_domain(obj, 0); | |
673a394b | 3205 | |
ba3d8d74 | 3206 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 | 3207 | if (ret != 0) |
6a47baa6 | 3208 | return ret; |
e47c68e9 EA |
3209 | i915_gem_object_flush_gtt_write_domain(obj); |
3210 | ||
3211 | /* If we're already fully in the CPU read domain, we're done. */ | |
3212 | if (obj_priv->page_cpu_valid == NULL && | |
3213 | (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0) | |
3214 | return 0; | |
673a394b | 3215 | |
e47c68e9 EA |
3216 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
3217 | * newly adding I915_GEM_DOMAIN_CPU | |
3218 | */ | |
673a394b | 3219 | if (obj_priv->page_cpu_valid == NULL) { |
9a298b2a EA |
3220 | obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE, |
3221 | GFP_KERNEL); | |
e47c68e9 EA |
3222 | if (obj_priv->page_cpu_valid == NULL) |
3223 | return -ENOMEM; | |
3224 | } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
3225 | memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE); | |
673a394b EA |
3226 | |
3227 | /* Flush the cache on any pages that are still invalid from the CPU's | |
3228 | * perspective. | |
3229 | */ | |
e47c68e9 EA |
3230 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
3231 | i++) { | |
673a394b EA |
3232 | if (obj_priv->page_cpu_valid[i]) |
3233 | continue; | |
3234 | ||
856fa198 | 3235 | drm_clflush_pages(obj_priv->pages + i, 1); |
673a394b EA |
3236 | |
3237 | obj_priv->page_cpu_valid[i] = 1; | |
3238 | } | |
3239 | ||
e47c68e9 EA |
3240 | /* It should now be out of any other write domains, and we can update |
3241 | * the domain values for our changes. | |
3242 | */ | |
3243 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); | |
3244 | ||
1c5d22f7 | 3245 | old_read_domains = obj->read_domains; |
e47c68e9 EA |
3246 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
3247 | ||
1c5d22f7 CW |
3248 | trace_i915_gem_object_change_domain(obj, |
3249 | old_read_domains, | |
3250 | obj->write_domain); | |
3251 | ||
673a394b EA |
3252 | return 0; |
3253 | } | |
3254 | ||
673a394b EA |
3255 | /** |
3256 | * Pin an object to the GTT and evaluate the relocations landing in it. | |
3257 | */ | |
3258 | static int | |
3259 | i915_gem_object_pin_and_relocate(struct drm_gem_object *obj, | |
3260 | struct drm_file *file_priv, | |
2549d6c2 | 3261 | struct drm_i915_gem_exec_object2 *entry) |
673a394b EA |
3262 | { |
3263 | struct drm_device *dev = obj->dev; | |
0839ccb8 | 3264 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 3265 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
2549d6c2 | 3266 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
673a394b | 3267 | int i, ret; |
76446cac JB |
3268 | bool need_fence; |
3269 | ||
3270 | need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
3271 | obj_priv->tiling_mode != I915_TILING_NONE; | |
3272 | ||
3273 | /* Check fence reg constraints and rebind if necessary */ | |
808b24d6 CW |
3274 | if (need_fence && |
3275 | !i915_gem_object_fence_offset_ok(obj, | |
3276 | obj_priv->tiling_mode)) { | |
3277 | ret = i915_gem_object_unbind(obj); | |
3278 | if (ret) | |
3279 | return ret; | |
3280 | } | |
673a394b EA |
3281 | |
3282 | /* Choose the GTT offset for our buffer and put it there. */ | |
3283 | ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment); | |
3284 | if (ret) | |
3285 | return ret; | |
3286 | ||
76446cac JB |
3287 | /* |
3288 | * Pre-965 chips need a fence register set up in order to | |
3289 | * properly handle blits to/from tiled surfaces. | |
3290 | */ | |
3291 | if (need_fence) { | |
53640e1d | 3292 | ret = i915_gem_object_get_fence_reg(obj, true); |
76446cac | 3293 | if (ret != 0) { |
76446cac JB |
3294 | i915_gem_object_unpin(obj); |
3295 | return ret; | |
3296 | } | |
53640e1d CW |
3297 | |
3298 | dev_priv->fence_regs[obj_priv->fence_reg].gpu = true; | |
76446cac JB |
3299 | } |
3300 | ||
673a394b EA |
3301 | entry->offset = obj_priv->gtt_offset; |
3302 | ||
673a394b EA |
3303 | /* Apply the relocations, using the GTT aperture to avoid cache |
3304 | * flushing requirements. | |
3305 | */ | |
2549d6c2 | 3306 | user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr; |
673a394b | 3307 | for (i = 0; i < entry->relocation_count; i++) { |
2549d6c2 | 3308 | struct drm_i915_gem_relocation_entry reloc; |
673a394b EA |
3309 | struct drm_gem_object *target_obj; |
3310 | struct drm_i915_gem_object *target_obj_priv; | |
673a394b | 3311 | |
2549d6c2 CW |
3312 | ret = __copy_from_user_inatomic(&reloc, |
3313 | user_relocs+i, | |
3314 | sizeof(reloc)); | |
3315 | if (ret) { | |
3316 | i915_gem_object_unpin(obj); | |
3317 | return -EFAULT; | |
3318 | } | |
3319 | ||
673a394b | 3320 | target_obj = drm_gem_object_lookup(obj->dev, file_priv, |
2549d6c2 | 3321 | reloc.target_handle); |
673a394b EA |
3322 | if (target_obj == NULL) { |
3323 | i915_gem_object_unpin(obj); | |
bf79cb91 | 3324 | return -ENOENT; |
673a394b | 3325 | } |
23010e43 | 3326 | target_obj_priv = to_intel_bo(target_obj); |
673a394b | 3327 | |
8542a0bb CW |
3328 | #if WATCH_RELOC |
3329 | DRM_INFO("%s: obj %p offset %08x target %d " | |
3330 | "read %08x write %08x gtt %08x " | |
3331 | "presumed %08x delta %08x\n", | |
3332 | __func__, | |
3333 | obj, | |
2549d6c2 CW |
3334 | (int) reloc.offset, |
3335 | (int) reloc.target_handle, | |
3336 | (int) reloc.read_domains, | |
3337 | (int) reloc.write_domain, | |
8542a0bb | 3338 | (int) target_obj_priv->gtt_offset, |
2549d6c2 CW |
3339 | (int) reloc.presumed_offset, |
3340 | reloc.delta); | |
8542a0bb CW |
3341 | #endif |
3342 | ||
673a394b EA |
3343 | /* The target buffer should have appeared before us in the |
3344 | * exec_object list, so it should have a GTT space bound by now. | |
3345 | */ | |
3346 | if (target_obj_priv->gtt_space == NULL) { | |
3347 | DRM_ERROR("No GTT space found for object %d\n", | |
2549d6c2 | 3348 | reloc.target_handle); |
673a394b EA |
3349 | drm_gem_object_unreference(target_obj); |
3350 | i915_gem_object_unpin(obj); | |
3351 | return -EINVAL; | |
3352 | } | |
3353 | ||
8542a0bb | 3354 | /* Validate that the target is in a valid r/w GPU domain */ |
2549d6c2 | 3355 | if (reloc.write_domain & (reloc.write_domain - 1)) { |
16edd550 DV |
3356 | DRM_ERROR("reloc with multiple write domains: " |
3357 | "obj %p target %d offset %d " | |
3358 | "read %08x write %08x", | |
2549d6c2 CW |
3359 | obj, reloc.target_handle, |
3360 | (int) reloc.offset, | |
3361 | reloc.read_domains, | |
3362 | reloc.write_domain); | |
929f49bf JL |
3363 | drm_gem_object_unreference(target_obj); |
3364 | i915_gem_object_unpin(obj); | |
16edd550 DV |
3365 | return -EINVAL; |
3366 | } | |
2549d6c2 CW |
3367 | if (reloc.write_domain & I915_GEM_DOMAIN_CPU || |
3368 | reloc.read_domains & I915_GEM_DOMAIN_CPU) { | |
e47c68e9 EA |
3369 | DRM_ERROR("reloc with read/write CPU domains: " |
3370 | "obj %p target %d offset %d " | |
3371 | "read %08x write %08x", | |
2549d6c2 CW |
3372 | obj, reloc.target_handle, |
3373 | (int) reloc.offset, | |
3374 | reloc.read_domains, | |
3375 | reloc.write_domain); | |
491152b8 CW |
3376 | drm_gem_object_unreference(target_obj); |
3377 | i915_gem_object_unpin(obj); | |
e47c68e9 EA |
3378 | return -EINVAL; |
3379 | } | |
2549d6c2 CW |
3380 | if (reloc.write_domain && target_obj->pending_write_domain && |
3381 | reloc.write_domain != target_obj->pending_write_domain) { | |
673a394b EA |
3382 | DRM_ERROR("Write domain conflict: " |
3383 | "obj %p target %d offset %d " | |
3384 | "new %08x old %08x\n", | |
2549d6c2 CW |
3385 | obj, reloc.target_handle, |
3386 | (int) reloc.offset, | |
3387 | reloc.write_domain, | |
673a394b EA |
3388 | target_obj->pending_write_domain); |
3389 | drm_gem_object_unreference(target_obj); | |
3390 | i915_gem_object_unpin(obj); | |
3391 | return -EINVAL; | |
3392 | } | |
3393 | ||
2549d6c2 CW |
3394 | target_obj->pending_read_domains |= reloc.read_domains; |
3395 | target_obj->pending_write_domain |= reloc.write_domain; | |
673a394b EA |
3396 | |
3397 | /* If the relocation already has the right value in it, no | |
3398 | * more work needs to be done. | |
3399 | */ | |
2549d6c2 | 3400 | if (target_obj_priv->gtt_offset == reloc.presumed_offset) { |
673a394b EA |
3401 | drm_gem_object_unreference(target_obj); |
3402 | continue; | |
3403 | } | |
3404 | ||
8542a0bb | 3405 | /* Check that the relocation address is valid... */ |
2549d6c2 | 3406 | if (reloc.offset > obj->size - 4) { |
8542a0bb CW |
3407 | DRM_ERROR("Relocation beyond object bounds: " |
3408 | "obj %p target %d offset %d size %d.\n", | |
2549d6c2 CW |
3409 | obj, reloc.target_handle, |
3410 | (int) reloc.offset, (int) obj->size); | |
8542a0bb CW |
3411 | drm_gem_object_unreference(target_obj); |
3412 | i915_gem_object_unpin(obj); | |
3413 | return -EINVAL; | |
3414 | } | |
2549d6c2 | 3415 | if (reloc.offset & 3) { |
8542a0bb CW |
3416 | DRM_ERROR("Relocation not 4-byte aligned: " |
3417 | "obj %p target %d offset %d.\n", | |
2549d6c2 CW |
3418 | obj, reloc.target_handle, |
3419 | (int) reloc.offset); | |
8542a0bb CW |
3420 | drm_gem_object_unreference(target_obj); |
3421 | i915_gem_object_unpin(obj); | |
3422 | return -EINVAL; | |
3423 | } | |
3424 | ||
3425 | /* and points to somewhere within the target object. */ | |
2549d6c2 | 3426 | if (reloc.delta >= target_obj->size) { |
8542a0bb CW |
3427 | DRM_ERROR("Relocation beyond target object bounds: " |
3428 | "obj %p target %d delta %d size %d.\n", | |
2549d6c2 CW |
3429 | obj, reloc.target_handle, |
3430 | (int) reloc.delta, (int) target_obj->size); | |
8542a0bb CW |
3431 | drm_gem_object_unreference(target_obj); |
3432 | i915_gem_object_unpin(obj); | |
3433 | return -EINVAL; | |
3434 | } | |
3435 | ||
f0c43d9b CW |
3436 | reloc.delta += target_obj_priv->gtt_offset; |
3437 | if (obj->write_domain == I915_GEM_DOMAIN_CPU) { | |
3438 | uint32_t page_offset = reloc.offset & ~PAGE_MASK; | |
3439 | char *vaddr; | |
673a394b | 3440 | |
f0c43d9b CW |
3441 | vaddr = kmap_atomic(obj_priv->pages[reloc.offset >> PAGE_SHIFT], KM_USER0); |
3442 | *(uint32_t *)(vaddr + page_offset) = reloc.delta; | |
3443 | kunmap_atomic(vaddr, KM_USER0); | |
3444 | } else { | |
3445 | uint32_t __iomem *reloc_entry; | |
3446 | void __iomem *reloc_page; | |
3447 | int ret; | |
3448 | ||
3449 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); | |
3450 | if (ret) { | |
3451 | drm_gem_object_unreference(target_obj); | |
3452 | i915_gem_object_unpin(obj); | |
3453 | return ret; | |
3454 | } | |
3455 | ||
3456 | /* Map the page containing the relocation we're going to perform. */ | |
3457 | reloc.offset += obj_priv->gtt_offset; | |
3458 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, | |
3459 | reloc.offset & PAGE_MASK, | |
3460 | KM_USER0); | |
3461 | reloc_entry = (uint32_t __iomem *) | |
3462 | (reloc_page + (reloc.offset & ~PAGE_MASK)); | |
3463 | iowrite32(reloc.delta, reloc_entry); | |
3464 | io_mapping_unmap_atomic(reloc_page, KM_USER0); | |
3465 | } | |
673a394b | 3466 | |
673a394b EA |
3467 | drm_gem_object_unreference(target_obj); |
3468 | } | |
3469 | ||
673a394b EA |
3470 | return 0; |
3471 | } | |
3472 | ||
673a394b EA |
3473 | /* Throttle our rendering by waiting until the ring has completed our requests |
3474 | * emitted over 20 msec ago. | |
3475 | * | |
b962442e EA |
3476 | * Note that if we were to use the current jiffies each time around the loop, |
3477 | * we wouldn't escape the function with any frames outstanding if the time to | |
3478 | * render a frame was over 20ms. | |
3479 | * | |
673a394b EA |
3480 | * This should get us reasonable parallelism between CPU and GPU but also |
3481 | * relatively low latency when blocking on a particular request to finish. | |
3482 | */ | |
3483 | static int | |
f787a5f5 | 3484 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
673a394b | 3485 | { |
f787a5f5 CW |
3486 | struct drm_i915_private *dev_priv = dev->dev_private; |
3487 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3488 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3489 | struct drm_i915_gem_request *request; |
3490 | struct intel_ring_buffer *ring = NULL; | |
3491 | u32 seqno = 0; | |
3492 | int ret; | |
673a394b | 3493 | |
1c25595f | 3494 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3495 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3496 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3497 | break; | |
3498 | ||
f787a5f5 CW |
3499 | ring = request->ring; |
3500 | seqno = request->seqno; | |
b962442e | 3501 | } |
1c25595f | 3502 | spin_unlock(&file_priv->mm.lock); |
f787a5f5 CW |
3503 | |
3504 | if (seqno == 0) | |
3505 | return 0; | |
3506 | ||
3507 | ret = 0; | |
3508 | if (!i915_seqno_passed(ring->get_seqno(dev, ring), seqno)) { | |
3509 | /* And wait for the seqno passing without holding any locks and | |
3510 | * causing extra latency for others. This is safe as the irq | |
3511 | * generation is designed to be run atomically and so is | |
3512 | * lockless. | |
3513 | */ | |
3514 | ring->user_irq_get(dev, ring); | |
3515 | ret = wait_event_interruptible(ring->irq_queue, | |
3516 | i915_seqno_passed(ring->get_seqno(dev, ring), seqno) | |
3517 | || atomic_read(&dev_priv->mm.wedged)); | |
3518 | ring->user_irq_put(dev, ring); | |
3519 | ||
3520 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) | |
3521 | ret = -EIO; | |
3522 | } | |
3523 | ||
3524 | if (ret == 0) | |
3525 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
b962442e | 3526 | |
673a394b EA |
3527 | return ret; |
3528 | } | |
3529 | ||
40a5f0de | 3530 | static int |
2549d6c2 CW |
3531 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec, |
3532 | uint64_t exec_offset) | |
40a5f0de | 3533 | { |
2549d6c2 | 3534 | uint32_t exec_start, exec_len; |
40a5f0de | 3535 | |
2549d6c2 CW |
3536 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; |
3537 | exec_len = (uint32_t) exec->batch_len; | |
40a5f0de | 3538 | |
2549d6c2 CW |
3539 | if ((exec_start | exec_len) & 0x7) |
3540 | return -EINVAL; | |
40a5f0de | 3541 | |
2549d6c2 CW |
3542 | if (!exec_start) |
3543 | return -EINVAL; | |
40a5f0de | 3544 | |
2bc43b5c | 3545 | return 0; |
40a5f0de EA |
3546 | } |
3547 | ||
3548 | static int | |
2549d6c2 CW |
3549 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, |
3550 | int count) | |
40a5f0de | 3551 | { |
2549d6c2 | 3552 | int i; |
40a5f0de | 3553 | |
2549d6c2 CW |
3554 | for (i = 0; i < count; i++) { |
3555 | char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr; | |
3556 | size_t length = exec[i].relocation_count * sizeof(struct drm_i915_gem_relocation_entry); | |
2bc43b5c | 3557 | |
2549d6c2 CW |
3558 | if (!access_ok(VERIFY_READ, ptr, length)) |
3559 | return -EFAULT; | |
40a5f0de | 3560 | |
2549d6c2 CW |
3561 | if (fault_in_pages_readable(ptr, length)) |
3562 | return -EFAULT; | |
40a5f0de EA |
3563 | } |
3564 | ||
83d60795 CW |
3565 | return 0; |
3566 | } | |
3567 | ||
8dc5d147 | 3568 | static int |
76446cac JB |
3569 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, |
3570 | struct drm_file *file_priv, | |
3571 | struct drm_i915_gem_execbuffer2 *args, | |
3572 | struct drm_i915_gem_exec_object2 *exec_list) | |
673a394b EA |
3573 | { |
3574 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b EA |
3575 | struct drm_gem_object **object_list = NULL; |
3576 | struct drm_gem_object *batch_obj; | |
b70d11da | 3577 | struct drm_i915_gem_object *obj_priv; |
201361a5 | 3578 | struct drm_clip_rect *cliprects = NULL; |
8dc5d147 | 3579 | struct drm_i915_gem_request *request = NULL; |
2549d6c2 | 3580 | int ret, i, pinned = 0; |
673a394b | 3581 | uint64_t exec_offset; |
6b95a207 | 3582 | int pin_tries, flips; |
673a394b | 3583 | |
852835f3 ZN |
3584 | struct intel_ring_buffer *ring = NULL; |
3585 | ||
30dbf0c0 CW |
3586 | ret = i915_gem_check_is_wedged(dev); |
3587 | if (ret) | |
3588 | return ret; | |
3589 | ||
2549d6c2 CW |
3590 | ret = validate_exec_list(exec_list, args->buffer_count); |
3591 | if (ret) | |
3592 | return ret; | |
3593 | ||
673a394b EA |
3594 | #if WATCH_EXEC |
3595 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
3596 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
3597 | #endif | |
d1b851fc ZN |
3598 | if (args->flags & I915_EXEC_BSD) { |
3599 | if (!HAS_BSD(dev)) { | |
3600 | DRM_ERROR("execbuf with wrong flag\n"); | |
3601 | return -EINVAL; | |
3602 | } | |
3603 | ring = &dev_priv->bsd_ring; | |
3604 | } else { | |
3605 | ring = &dev_priv->render_ring; | |
3606 | } | |
3607 | ||
4f481ed2 EA |
3608 | if (args->buffer_count < 1) { |
3609 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
3610 | return -EINVAL; | |
3611 | } | |
c8e0f93a | 3612 | object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count); |
76446cac JB |
3613 | if (object_list == NULL) { |
3614 | DRM_ERROR("Failed to allocate object list for %d buffers\n", | |
673a394b EA |
3615 | args->buffer_count); |
3616 | ret = -ENOMEM; | |
3617 | goto pre_mutex_err; | |
3618 | } | |
673a394b | 3619 | |
201361a5 | 3620 | if (args->num_cliprects != 0) { |
9a298b2a EA |
3621 | cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects), |
3622 | GFP_KERNEL); | |
a40e8d31 OA |
3623 | if (cliprects == NULL) { |
3624 | ret = -ENOMEM; | |
201361a5 | 3625 | goto pre_mutex_err; |
a40e8d31 | 3626 | } |
201361a5 EA |
3627 | |
3628 | ret = copy_from_user(cliprects, | |
3629 | (struct drm_clip_rect __user *) | |
3630 | (uintptr_t) args->cliprects_ptr, | |
3631 | sizeof(*cliprects) * args->num_cliprects); | |
3632 | if (ret != 0) { | |
3633 | DRM_ERROR("copy %d cliprects failed: %d\n", | |
3634 | args->num_cliprects, ret); | |
c877cdce | 3635 | ret = -EFAULT; |
201361a5 EA |
3636 | goto pre_mutex_err; |
3637 | } | |
3638 | } | |
3639 | ||
8dc5d147 CW |
3640 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
3641 | if (request == NULL) { | |
3642 | ret = -ENOMEM; | |
3643 | goto pre_mutex_err; | |
3644 | } | |
3645 | ||
76c1dec1 CW |
3646 | ret = i915_mutex_lock_interruptible(dev); |
3647 | if (ret) | |
3648 | goto pre_mutex_err; | |
673a394b | 3649 | |
673a394b | 3650 | if (dev_priv->mm.suspended) { |
673a394b | 3651 | mutex_unlock(&dev->struct_mutex); |
a198bc80 CW |
3652 | ret = -EBUSY; |
3653 | goto pre_mutex_err; | |
673a394b EA |
3654 | } |
3655 | ||
ac94a962 | 3656 | /* Look up object handles */ |
673a394b EA |
3657 | for (i = 0; i < args->buffer_count; i++) { |
3658 | object_list[i] = drm_gem_object_lookup(dev, file_priv, | |
3659 | exec_list[i].handle); | |
3660 | if (object_list[i] == NULL) { | |
3661 | DRM_ERROR("Invalid object handle %d at index %d\n", | |
3662 | exec_list[i].handle, i); | |
0ce907f8 CW |
3663 | /* prevent error path from reading uninitialized data */ |
3664 | args->buffer_count = i + 1; | |
bf79cb91 | 3665 | ret = -ENOENT; |
673a394b EA |
3666 | goto err; |
3667 | } | |
b70d11da | 3668 | |
23010e43 | 3669 | obj_priv = to_intel_bo(object_list[i]); |
b70d11da KH |
3670 | if (obj_priv->in_execbuffer) { |
3671 | DRM_ERROR("Object %p appears more than once in object list\n", | |
3672 | object_list[i]); | |
0ce907f8 CW |
3673 | /* prevent error path from reading uninitialized data */ |
3674 | args->buffer_count = i + 1; | |
bf79cb91 | 3675 | ret = -EINVAL; |
b70d11da KH |
3676 | goto err; |
3677 | } | |
3678 | obj_priv->in_execbuffer = true; | |
ac94a962 | 3679 | } |
673a394b | 3680 | |
ac94a962 KP |
3681 | /* Pin and relocate */ |
3682 | for (pin_tries = 0; ; pin_tries++) { | |
3683 | ret = 0; | |
40a5f0de | 3684 | |
ac94a962 KP |
3685 | for (i = 0; i < args->buffer_count; i++) { |
3686 | object_list[i]->pending_read_domains = 0; | |
3687 | object_list[i]->pending_write_domain = 0; | |
3688 | ret = i915_gem_object_pin_and_relocate(object_list[i], | |
3689 | file_priv, | |
2549d6c2 | 3690 | &exec_list[i]); |
ac94a962 KP |
3691 | if (ret) |
3692 | break; | |
3693 | pinned = i + 1; | |
3694 | } | |
3695 | /* success */ | |
3696 | if (ret == 0) | |
3697 | break; | |
3698 | ||
3699 | /* error other than GTT full, or we've already tried again */ | |
2939e1f5 | 3700 | if (ret != -ENOSPC || pin_tries >= 1) { |
07f73f69 CW |
3701 | if (ret != -ERESTARTSYS) { |
3702 | unsigned long long total_size = 0; | |
3d1cc470 CW |
3703 | int num_fences = 0; |
3704 | for (i = 0; i < args->buffer_count; i++) { | |
43b27f40 | 3705 | obj_priv = to_intel_bo(object_list[i]); |
3d1cc470 | 3706 | |
07f73f69 | 3707 | total_size += object_list[i]->size; |
3d1cc470 CW |
3708 | num_fences += |
3709 | exec_list[i].flags & EXEC_OBJECT_NEEDS_FENCE && | |
3710 | obj_priv->tiling_mode != I915_TILING_NONE; | |
3711 | } | |
3712 | DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n", | |
07f73f69 | 3713 | pinned+1, args->buffer_count, |
3d1cc470 CW |
3714 | total_size, num_fences, |
3715 | ret); | |
73aa808f CW |
3716 | DRM_ERROR("%u objects [%u pinned, %u GTT], " |
3717 | "%zu object bytes [%zu pinned], " | |
3718 | "%zu /%zu gtt bytes\n", | |
3719 | dev_priv->mm.object_count, | |
3720 | dev_priv->mm.pin_count, | |
3721 | dev_priv->mm.gtt_count, | |
3722 | dev_priv->mm.object_memory, | |
3723 | dev_priv->mm.pin_memory, | |
3724 | dev_priv->mm.gtt_memory, | |
3725 | dev_priv->mm.gtt_total); | |
07f73f69 | 3726 | } |
673a394b EA |
3727 | goto err; |
3728 | } | |
ac94a962 KP |
3729 | |
3730 | /* unpin all of our buffers */ | |
3731 | for (i = 0; i < pinned; i++) | |
3732 | i915_gem_object_unpin(object_list[i]); | |
b1177636 | 3733 | pinned = 0; |
ac94a962 KP |
3734 | |
3735 | /* evict everyone we can from the aperture */ | |
3736 | ret = i915_gem_evict_everything(dev); | |
07f73f69 | 3737 | if (ret && ret != -ENOSPC) |
ac94a962 | 3738 | goto err; |
673a394b EA |
3739 | } |
3740 | ||
3741 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
3742 | batch_obj = object_list[args->buffer_count-1]; | |
5f26a2c7 CW |
3743 | if (batch_obj->pending_write_domain) { |
3744 | DRM_ERROR("Attempting to use self-modifying batch buffer\n"); | |
3745 | ret = -EINVAL; | |
3746 | goto err; | |
3747 | } | |
3748 | batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
673a394b | 3749 | |
83d60795 CW |
3750 | /* Sanity check the batch buffer, prior to moving objects */ |
3751 | exec_offset = exec_list[args->buffer_count - 1].offset; | |
3752 | ret = i915_gem_check_execbuffer (args, exec_offset); | |
3753 | if (ret != 0) { | |
3754 | DRM_ERROR("execbuf with invalid offset/length\n"); | |
3755 | goto err; | |
3756 | } | |
3757 | ||
646f0f6e KP |
3758 | /* Zero the global flush/invalidate flags. These |
3759 | * will be modified as new domains are computed | |
3760 | * for each object | |
3761 | */ | |
3762 | dev->invalidate_domains = 0; | |
3763 | dev->flush_domains = 0; | |
9220434a | 3764 | dev_priv->mm.flush_rings = 0; |
646f0f6e | 3765 | |
673a394b EA |
3766 | for (i = 0; i < args->buffer_count; i++) { |
3767 | struct drm_gem_object *obj = object_list[i]; | |
673a394b | 3768 | |
646f0f6e | 3769 | /* Compute new gpu domains and update invalidate/flush */ |
8b0e378a | 3770 | i915_gem_object_set_to_gpu_domain(obj); |
673a394b EA |
3771 | } |
3772 | ||
646f0f6e KP |
3773 | if (dev->invalidate_domains | dev->flush_domains) { |
3774 | #if WATCH_EXEC | |
3775 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", | |
3776 | __func__, | |
3777 | dev->invalidate_domains, | |
3778 | dev->flush_domains); | |
3779 | #endif | |
c78ec30b | 3780 | i915_gem_flush(dev, file_priv, |
646f0f6e | 3781 | dev->invalidate_domains, |
9220434a CW |
3782 | dev->flush_domains, |
3783 | dev_priv->mm.flush_rings); | |
a6910434 DV |
3784 | } |
3785 | ||
efbeed96 EA |
3786 | for (i = 0; i < args->buffer_count; i++) { |
3787 | struct drm_gem_object *obj = object_list[i]; | |
23010e43 | 3788 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 3789 | uint32_t old_write_domain = obj->write_domain; |
efbeed96 EA |
3790 | |
3791 | obj->write_domain = obj->pending_write_domain; | |
99fcb766 DV |
3792 | if (obj->write_domain) |
3793 | list_move_tail(&obj_priv->gpu_write_list, | |
3794 | &dev_priv->mm.gpu_write_list); | |
99fcb766 | 3795 | |
1c5d22f7 CW |
3796 | trace_i915_gem_object_change_domain(obj, |
3797 | obj->read_domains, | |
3798 | old_write_domain); | |
efbeed96 EA |
3799 | } |
3800 | ||
673a394b EA |
3801 | #if WATCH_COHERENCY |
3802 | for (i = 0; i < args->buffer_count; i++) { | |
3803 | i915_gem_object_check_coherency(object_list[i], | |
3804 | exec_list[i].handle); | |
3805 | } | |
3806 | #endif | |
3807 | ||
673a394b | 3808 | #if WATCH_EXEC |
6911a9b8 | 3809 | i915_gem_dump_object(batch_obj, |
673a394b EA |
3810 | args->batch_len, |
3811 | __func__, | |
3812 | ~0); | |
3813 | #endif | |
3814 | ||
e59f2bac CW |
3815 | /* Check for any pending flips. As we only maintain a flip queue depth |
3816 | * of 1, we can simply insert a WAIT for the next display flip prior | |
3817 | * to executing the batch and avoid stalling the CPU. | |
3818 | */ | |
3819 | flips = 0; | |
3820 | for (i = 0; i < args->buffer_count; i++) { | |
3821 | if (object_list[i]->write_domain) | |
3822 | flips |= atomic_read(&to_intel_bo(object_list[i])->pending_flip); | |
3823 | } | |
3824 | if (flips) { | |
3825 | int plane, flip_mask; | |
3826 | ||
3827 | for (plane = 0; flips >> plane; plane++) { | |
3828 | if (((flips >> plane) & 1) == 0) | |
3829 | continue; | |
3830 | ||
3831 | if (plane) | |
3832 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
3833 | else | |
3834 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
3835 | ||
3836 | intel_ring_begin(dev, ring, 2); | |
3837 | intel_ring_emit(dev, ring, | |
3838 | MI_WAIT_FOR_EVENT | flip_mask); | |
3839 | intel_ring_emit(dev, ring, MI_NOOP); | |
3840 | intel_ring_advance(dev, ring); | |
3841 | } | |
3842 | } | |
3843 | ||
673a394b | 3844 | /* Exec the batchbuffer */ |
852835f3 | 3845 | ret = ring->dispatch_gem_execbuffer(dev, ring, args, |
e59f2bac | 3846 | cliprects, exec_offset); |
673a394b EA |
3847 | if (ret) { |
3848 | DRM_ERROR("dispatch failed %d\n", ret); | |
3849 | goto err; | |
3850 | } | |
3851 | ||
3852 | /* | |
3853 | * Ensure that the commands in the batch buffer are | |
3854 | * finished before the interrupt fires | |
3855 | */ | |
8a1a49f9 | 3856 | i915_retire_commands(dev, ring); |
673a394b | 3857 | |
617dbe27 DV |
3858 | for (i = 0; i < args->buffer_count; i++) { |
3859 | struct drm_gem_object *obj = object_list[i]; | |
3860 | obj_priv = to_intel_bo(obj); | |
3861 | ||
3862 | i915_gem_object_move_to_active(obj, ring); | |
617dbe27 | 3863 | } |
a56ba56c | 3864 | |
5c12a07e | 3865 | i915_add_request(dev, file_priv, request, ring); |
8dc5d147 | 3866 | request = NULL; |
673a394b | 3867 | |
673a394b | 3868 | err: |
aad87dff JL |
3869 | for (i = 0; i < pinned; i++) |
3870 | i915_gem_object_unpin(object_list[i]); | |
3871 | ||
b70d11da KH |
3872 | for (i = 0; i < args->buffer_count; i++) { |
3873 | if (object_list[i]) { | |
23010e43 | 3874 | obj_priv = to_intel_bo(object_list[i]); |
b70d11da KH |
3875 | obj_priv->in_execbuffer = false; |
3876 | } | |
aad87dff | 3877 | drm_gem_object_unreference(object_list[i]); |
b70d11da | 3878 | } |
673a394b | 3879 | |
673a394b EA |
3880 | mutex_unlock(&dev->struct_mutex); |
3881 | ||
93533c29 | 3882 | pre_mutex_err: |
8e7d2b2c | 3883 | drm_free_large(object_list); |
9a298b2a | 3884 | kfree(cliprects); |
8dc5d147 | 3885 | kfree(request); |
673a394b EA |
3886 | |
3887 | return ret; | |
3888 | } | |
3889 | ||
76446cac JB |
3890 | /* |
3891 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
3892 | * list array and passes it to the real function. | |
3893 | */ | |
3894 | int | |
3895 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
3896 | struct drm_file *file_priv) | |
3897 | { | |
3898 | struct drm_i915_gem_execbuffer *args = data; | |
3899 | struct drm_i915_gem_execbuffer2 exec2; | |
3900 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
3901 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
3902 | int ret, i; | |
3903 | ||
3904 | #if WATCH_EXEC | |
3905 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
3906 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
3907 | #endif | |
3908 | ||
3909 | if (args->buffer_count < 1) { | |
3910 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
3911 | return -EINVAL; | |
3912 | } | |
3913 | ||
3914 | /* Copy in the exec list from userland */ | |
3915 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
3916 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
3917 | if (exec_list == NULL || exec2_list == NULL) { | |
3918 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
3919 | args->buffer_count); | |
3920 | drm_free_large(exec_list); | |
3921 | drm_free_large(exec2_list); | |
3922 | return -ENOMEM; | |
3923 | } | |
3924 | ret = copy_from_user(exec_list, | |
3925 | (struct drm_i915_relocation_entry __user *) | |
3926 | (uintptr_t) args->buffers_ptr, | |
3927 | sizeof(*exec_list) * args->buffer_count); | |
3928 | if (ret != 0) { | |
3929 | DRM_ERROR("copy %d exec entries failed %d\n", | |
3930 | args->buffer_count, ret); | |
3931 | drm_free_large(exec_list); | |
3932 | drm_free_large(exec2_list); | |
3933 | return -EFAULT; | |
3934 | } | |
3935 | ||
3936 | for (i = 0; i < args->buffer_count; i++) { | |
3937 | exec2_list[i].handle = exec_list[i].handle; | |
3938 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
3939 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
3940 | exec2_list[i].alignment = exec_list[i].alignment; | |
3941 | exec2_list[i].offset = exec_list[i].offset; | |
a6c45cf0 | 3942 | if (INTEL_INFO(dev)->gen < 4) |
76446cac JB |
3943 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; |
3944 | else | |
3945 | exec2_list[i].flags = 0; | |
3946 | } | |
3947 | ||
3948 | exec2.buffers_ptr = args->buffers_ptr; | |
3949 | exec2.buffer_count = args->buffer_count; | |
3950 | exec2.batch_start_offset = args->batch_start_offset; | |
3951 | exec2.batch_len = args->batch_len; | |
3952 | exec2.DR1 = args->DR1; | |
3953 | exec2.DR4 = args->DR4; | |
3954 | exec2.num_cliprects = args->num_cliprects; | |
3955 | exec2.cliprects_ptr = args->cliprects_ptr; | |
852835f3 | 3956 | exec2.flags = I915_EXEC_RENDER; |
76446cac JB |
3957 | |
3958 | ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list); | |
3959 | if (!ret) { | |
3960 | /* Copy the new buffer offsets back to the user's exec list. */ | |
3961 | for (i = 0; i < args->buffer_count; i++) | |
3962 | exec_list[i].offset = exec2_list[i].offset; | |
3963 | /* ... and back out to userspace */ | |
3964 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
3965 | (uintptr_t) args->buffers_ptr, | |
3966 | exec_list, | |
3967 | sizeof(*exec_list) * args->buffer_count); | |
3968 | if (ret) { | |
3969 | ret = -EFAULT; | |
3970 | DRM_ERROR("failed to copy %d exec entries " | |
3971 | "back to user (%d)\n", | |
3972 | args->buffer_count, ret); | |
3973 | } | |
76446cac JB |
3974 | } |
3975 | ||
3976 | drm_free_large(exec_list); | |
3977 | drm_free_large(exec2_list); | |
3978 | return ret; | |
3979 | } | |
3980 | ||
3981 | int | |
3982 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
3983 | struct drm_file *file_priv) | |
3984 | { | |
3985 | struct drm_i915_gem_execbuffer2 *args = data; | |
3986 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
3987 | int ret; | |
3988 | ||
3989 | #if WATCH_EXEC | |
3990 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
3991 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
3992 | #endif | |
3993 | ||
3994 | if (args->buffer_count < 1) { | |
3995 | DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count); | |
3996 | return -EINVAL; | |
3997 | } | |
3998 | ||
3999 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
4000 | if (exec2_list == NULL) { | |
4001 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
4002 | args->buffer_count); | |
4003 | return -ENOMEM; | |
4004 | } | |
4005 | ret = copy_from_user(exec2_list, | |
4006 | (struct drm_i915_relocation_entry __user *) | |
4007 | (uintptr_t) args->buffers_ptr, | |
4008 | sizeof(*exec2_list) * args->buffer_count); | |
4009 | if (ret != 0) { | |
4010 | DRM_ERROR("copy %d exec entries failed %d\n", | |
4011 | args->buffer_count, ret); | |
4012 | drm_free_large(exec2_list); | |
4013 | return -EFAULT; | |
4014 | } | |
4015 | ||
4016 | ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list); | |
4017 | if (!ret) { | |
4018 | /* Copy the new buffer offsets back to the user's exec list. */ | |
4019 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
4020 | (uintptr_t) args->buffers_ptr, | |
4021 | exec2_list, | |
4022 | sizeof(*exec2_list) * args->buffer_count); | |
4023 | if (ret) { | |
4024 | ret = -EFAULT; | |
4025 | DRM_ERROR("failed to copy %d exec entries " | |
4026 | "back to user (%d)\n", | |
4027 | args->buffer_count, ret); | |
4028 | } | |
4029 | } | |
4030 | ||
4031 | drm_free_large(exec2_list); | |
4032 | return ret; | |
4033 | } | |
4034 | ||
673a394b EA |
4035 | int |
4036 | i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment) | |
4037 | { | |
4038 | struct drm_device *dev = obj->dev; | |
f13d3f73 | 4039 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 4040 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
4041 | int ret; |
4042 | ||
778c3544 | 4043 | BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
23bc5982 | 4044 | WARN_ON(i915_verify_lists(dev)); |
ac0c6b5a CW |
4045 | |
4046 | if (obj_priv->gtt_space != NULL) { | |
4047 | if (alignment == 0) | |
4048 | alignment = i915_gem_get_gtt_alignment(obj); | |
4049 | if (obj_priv->gtt_offset & (alignment - 1)) { | |
ae7d49d8 CW |
4050 | WARN(obj_priv->pin_count, |
4051 | "bo is already pinned with incorrect alignment:" | |
4052 | " offset=%x, req.alignment=%x\n", | |
4053 | obj_priv->gtt_offset, alignment); | |
ac0c6b5a CW |
4054 | ret = i915_gem_object_unbind(obj); |
4055 | if (ret) | |
4056 | return ret; | |
4057 | } | |
4058 | } | |
4059 | ||
673a394b EA |
4060 | if (obj_priv->gtt_space == NULL) { |
4061 | ret = i915_gem_object_bind_to_gtt(obj, alignment); | |
9731129c | 4062 | if (ret) |
673a394b | 4063 | return ret; |
22c344e9 | 4064 | } |
76446cac | 4065 | |
673a394b EA |
4066 | obj_priv->pin_count++; |
4067 | ||
4068 | /* If the object is not active and not pending a flush, | |
4069 | * remove it from the inactive list | |
4070 | */ | |
4071 | if (obj_priv->pin_count == 1) { | |
73aa808f | 4072 | i915_gem_info_add_pin(dev_priv, obj->size); |
f13d3f73 CW |
4073 | if (!obj_priv->active) |
4074 | list_move_tail(&obj_priv->list, | |
4075 | &dev_priv->mm.pinned_list); | |
673a394b | 4076 | } |
673a394b | 4077 | |
23bc5982 | 4078 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4079 | return 0; |
4080 | } | |
4081 | ||
4082 | void | |
4083 | i915_gem_object_unpin(struct drm_gem_object *obj) | |
4084 | { | |
4085 | struct drm_device *dev = obj->dev; | |
4086 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 4087 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 4088 | |
23bc5982 | 4089 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4090 | obj_priv->pin_count--; |
4091 | BUG_ON(obj_priv->pin_count < 0); | |
4092 | BUG_ON(obj_priv->gtt_space == NULL); | |
4093 | ||
4094 | /* If the object is no longer pinned, and is | |
4095 | * neither active nor being flushed, then stick it on | |
4096 | * the inactive list | |
4097 | */ | |
4098 | if (obj_priv->pin_count == 0) { | |
f13d3f73 | 4099 | if (!obj_priv->active) |
673a394b EA |
4100 | list_move_tail(&obj_priv->list, |
4101 | &dev_priv->mm.inactive_list); | |
73aa808f | 4102 | i915_gem_info_remove_pin(dev_priv, obj->size); |
673a394b | 4103 | } |
23bc5982 | 4104 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4105 | } |
4106 | ||
4107 | int | |
4108 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
4109 | struct drm_file *file_priv) | |
4110 | { | |
4111 | struct drm_i915_gem_pin *args = data; | |
4112 | struct drm_gem_object *obj; | |
4113 | struct drm_i915_gem_object *obj_priv; | |
4114 | int ret; | |
4115 | ||
673a394b EA |
4116 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
4117 | if (obj == NULL) { | |
4118 | DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n", | |
4119 | args->handle); | |
bf79cb91 | 4120 | return -ENOENT; |
673a394b | 4121 | } |
23010e43 | 4122 | obj_priv = to_intel_bo(obj); |
673a394b | 4123 | |
76c1dec1 CW |
4124 | ret = i915_mutex_lock_interruptible(dev); |
4125 | if (ret) { | |
4126 | drm_gem_object_unreference_unlocked(obj); | |
4127 | return ret; | |
4128 | } | |
4129 | ||
bb6baf76 CW |
4130 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
4131 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); | |
3ef94daa CW |
4132 | drm_gem_object_unreference(obj); |
4133 | mutex_unlock(&dev->struct_mutex); | |
4134 | return -EINVAL; | |
4135 | } | |
4136 | ||
79e53945 JB |
4137 | if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) { |
4138 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", | |
4139 | args->handle); | |
96dec61d | 4140 | drm_gem_object_unreference(obj); |
673a394b | 4141 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
4142 | return -EINVAL; |
4143 | } | |
4144 | ||
4145 | obj_priv->user_pin_count++; | |
4146 | obj_priv->pin_filp = file_priv; | |
4147 | if (obj_priv->user_pin_count == 1) { | |
4148 | ret = i915_gem_object_pin(obj, args->alignment); | |
4149 | if (ret != 0) { | |
4150 | drm_gem_object_unreference(obj); | |
4151 | mutex_unlock(&dev->struct_mutex); | |
4152 | return ret; | |
4153 | } | |
673a394b EA |
4154 | } |
4155 | ||
4156 | /* XXX - flush the CPU caches for pinned objects | |
4157 | * as the X server doesn't manage domains yet | |
4158 | */ | |
e47c68e9 | 4159 | i915_gem_object_flush_cpu_write_domain(obj); |
673a394b EA |
4160 | args->offset = obj_priv->gtt_offset; |
4161 | drm_gem_object_unreference(obj); | |
4162 | mutex_unlock(&dev->struct_mutex); | |
4163 | ||
4164 | return 0; | |
4165 | } | |
4166 | ||
4167 | int | |
4168 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
4169 | struct drm_file *file_priv) | |
4170 | { | |
4171 | struct drm_i915_gem_pin *args = data; | |
4172 | struct drm_gem_object *obj; | |
79e53945 | 4173 | struct drm_i915_gem_object *obj_priv; |
76c1dec1 | 4174 | int ret; |
673a394b EA |
4175 | |
4176 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4177 | if (obj == NULL) { | |
4178 | DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n", | |
4179 | args->handle); | |
bf79cb91 | 4180 | return -ENOENT; |
673a394b EA |
4181 | } |
4182 | ||
23010e43 | 4183 | obj_priv = to_intel_bo(obj); |
76c1dec1 CW |
4184 | |
4185 | ret = i915_mutex_lock_interruptible(dev); | |
4186 | if (ret) { | |
4187 | drm_gem_object_unreference_unlocked(obj); | |
4188 | return ret; | |
4189 | } | |
4190 | ||
79e53945 JB |
4191 | if (obj_priv->pin_filp != file_priv) { |
4192 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", | |
4193 | args->handle); | |
4194 | drm_gem_object_unreference(obj); | |
4195 | mutex_unlock(&dev->struct_mutex); | |
4196 | return -EINVAL; | |
4197 | } | |
4198 | obj_priv->user_pin_count--; | |
4199 | if (obj_priv->user_pin_count == 0) { | |
4200 | obj_priv->pin_filp = NULL; | |
4201 | i915_gem_object_unpin(obj); | |
4202 | } | |
673a394b EA |
4203 | |
4204 | drm_gem_object_unreference(obj); | |
4205 | mutex_unlock(&dev->struct_mutex); | |
4206 | return 0; | |
4207 | } | |
4208 | ||
4209 | int | |
4210 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
4211 | struct drm_file *file_priv) | |
4212 | { | |
4213 | struct drm_i915_gem_busy *args = data; | |
4214 | struct drm_gem_object *obj; | |
4215 | struct drm_i915_gem_object *obj_priv; | |
30dbf0c0 CW |
4216 | int ret; |
4217 | ||
673a394b EA |
4218 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
4219 | if (obj == NULL) { | |
4220 | DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n", | |
4221 | args->handle); | |
bf79cb91 | 4222 | return -ENOENT; |
673a394b EA |
4223 | } |
4224 | ||
76c1dec1 CW |
4225 | ret = i915_mutex_lock_interruptible(dev); |
4226 | if (ret) { | |
4227 | drm_gem_object_unreference_unlocked(obj); | |
4228 | return ret; | |
30dbf0c0 CW |
4229 | } |
4230 | ||
0be555b6 CW |
4231 | /* Count all active objects as busy, even if they are currently not used |
4232 | * by the gpu. Users of this interface expect objects to eventually | |
4233 | * become non-busy without any further actions, therefore emit any | |
4234 | * necessary flushes here. | |
c4de0a5d | 4235 | */ |
0be555b6 CW |
4236 | obj_priv = to_intel_bo(obj); |
4237 | args->busy = obj_priv->active; | |
4238 | if (args->busy) { | |
4239 | /* Unconditionally flush objects, even when the gpu still uses this | |
4240 | * object. Userspace calling this function indicates that it wants to | |
4241 | * use this buffer rather sooner than later, so issuing the required | |
4242 | * flush earlier is beneficial. | |
4243 | */ | |
c78ec30b CW |
4244 | if (obj->write_domain & I915_GEM_GPU_DOMAINS) |
4245 | i915_gem_flush_ring(dev, file_priv, | |
9220434a CW |
4246 | obj_priv->ring, |
4247 | 0, obj->write_domain); | |
0be555b6 CW |
4248 | |
4249 | /* Update the active list for the hardware's current position. | |
4250 | * Otherwise this only updates on a delayed timer or when irqs | |
4251 | * are actually unmasked, and our working set ends up being | |
4252 | * larger than required. | |
4253 | */ | |
4254 | i915_gem_retire_requests_ring(dev, obj_priv->ring); | |
4255 | ||
4256 | args->busy = obj_priv->active; | |
4257 | } | |
673a394b EA |
4258 | |
4259 | drm_gem_object_unreference(obj); | |
4260 | mutex_unlock(&dev->struct_mutex); | |
76c1dec1 | 4261 | return 0; |
673a394b EA |
4262 | } |
4263 | ||
4264 | int | |
4265 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4266 | struct drm_file *file_priv) | |
4267 | { | |
4268 | return i915_gem_ring_throttle(dev, file_priv); | |
4269 | } | |
4270 | ||
3ef94daa CW |
4271 | int |
4272 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4273 | struct drm_file *file_priv) | |
4274 | { | |
4275 | struct drm_i915_gem_madvise *args = data; | |
4276 | struct drm_gem_object *obj; | |
4277 | struct drm_i915_gem_object *obj_priv; | |
76c1dec1 | 4278 | int ret; |
3ef94daa CW |
4279 | |
4280 | switch (args->madv) { | |
4281 | case I915_MADV_DONTNEED: | |
4282 | case I915_MADV_WILLNEED: | |
4283 | break; | |
4284 | default: | |
4285 | return -EINVAL; | |
4286 | } | |
4287 | ||
4288 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4289 | if (obj == NULL) { | |
4290 | DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n", | |
4291 | args->handle); | |
bf79cb91 | 4292 | return -ENOENT; |
3ef94daa | 4293 | } |
23010e43 | 4294 | obj_priv = to_intel_bo(obj); |
3ef94daa | 4295 | |
76c1dec1 CW |
4296 | ret = i915_mutex_lock_interruptible(dev); |
4297 | if (ret) { | |
4298 | drm_gem_object_unreference_unlocked(obj); | |
4299 | return ret; | |
4300 | } | |
4301 | ||
3ef94daa CW |
4302 | if (obj_priv->pin_count) { |
4303 | drm_gem_object_unreference(obj); | |
4304 | mutex_unlock(&dev->struct_mutex); | |
4305 | ||
4306 | DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n"); | |
4307 | return -EINVAL; | |
4308 | } | |
4309 | ||
bb6baf76 CW |
4310 | if (obj_priv->madv != __I915_MADV_PURGED) |
4311 | obj_priv->madv = args->madv; | |
3ef94daa | 4312 | |
2d7ef395 CW |
4313 | /* if the object is no longer bound, discard its backing storage */ |
4314 | if (i915_gem_object_is_purgeable(obj_priv) && | |
4315 | obj_priv->gtt_space == NULL) | |
4316 | i915_gem_object_truncate(obj); | |
4317 | ||
bb6baf76 CW |
4318 | args->retained = obj_priv->madv != __I915_MADV_PURGED; |
4319 | ||
3ef94daa CW |
4320 | drm_gem_object_unreference(obj); |
4321 | mutex_unlock(&dev->struct_mutex); | |
4322 | ||
4323 | return 0; | |
4324 | } | |
4325 | ||
ac52bc56 DV |
4326 | struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev, |
4327 | size_t size) | |
4328 | { | |
73aa808f | 4329 | struct drm_i915_private *dev_priv = dev->dev_private; |
c397b908 | 4330 | struct drm_i915_gem_object *obj; |
ac52bc56 | 4331 | |
c397b908 DV |
4332 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
4333 | if (obj == NULL) | |
4334 | return NULL; | |
673a394b | 4335 | |
c397b908 DV |
4336 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
4337 | kfree(obj); | |
4338 | return NULL; | |
4339 | } | |
673a394b | 4340 | |
73aa808f CW |
4341 | i915_gem_info_add_obj(dev_priv, size); |
4342 | ||
c397b908 DV |
4343 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4344 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4345 | |
c397b908 | 4346 | obj->agp_type = AGP_USER_MEMORY; |
62b8b215 | 4347 | obj->base.driver_private = NULL; |
c397b908 DV |
4348 | obj->fence_reg = I915_FENCE_REG_NONE; |
4349 | INIT_LIST_HEAD(&obj->list); | |
4350 | INIT_LIST_HEAD(&obj->gpu_write_list); | |
c397b908 | 4351 | obj->madv = I915_MADV_WILLNEED; |
de151cf6 | 4352 | |
c397b908 DV |
4353 | return &obj->base; |
4354 | } | |
4355 | ||
4356 | int i915_gem_init_object(struct drm_gem_object *obj) | |
4357 | { | |
4358 | BUG(); | |
de151cf6 | 4359 | |
673a394b EA |
4360 | return 0; |
4361 | } | |
4362 | ||
be72615b | 4363 | static void i915_gem_free_object_tail(struct drm_gem_object *obj) |
673a394b | 4364 | { |
de151cf6 | 4365 | struct drm_device *dev = obj->dev; |
be72615b | 4366 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 4367 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
be72615b | 4368 | int ret; |
673a394b | 4369 | |
be72615b CW |
4370 | ret = i915_gem_object_unbind(obj); |
4371 | if (ret == -ERESTARTSYS) { | |
4372 | list_move(&obj_priv->list, | |
4373 | &dev_priv->mm.deferred_free_list); | |
4374 | return; | |
4375 | } | |
673a394b | 4376 | |
7e616158 CW |
4377 | if (obj_priv->mmap_offset) |
4378 | i915_gem_free_mmap_offset(obj); | |
de151cf6 | 4379 | |
c397b908 | 4380 | drm_gem_object_release(obj); |
73aa808f | 4381 | i915_gem_info_remove_obj(dev_priv, obj->size); |
c397b908 | 4382 | |
9a298b2a | 4383 | kfree(obj_priv->page_cpu_valid); |
280b713b | 4384 | kfree(obj_priv->bit_17); |
c397b908 | 4385 | kfree(obj_priv); |
673a394b EA |
4386 | } |
4387 | ||
be72615b CW |
4388 | void i915_gem_free_object(struct drm_gem_object *obj) |
4389 | { | |
4390 | struct drm_device *dev = obj->dev; | |
4391 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
4392 | ||
4393 | trace_i915_gem_object_destroy(obj); | |
4394 | ||
4395 | while (obj_priv->pin_count > 0) | |
4396 | i915_gem_object_unpin(obj); | |
4397 | ||
4398 | if (obj_priv->phys_obj) | |
4399 | i915_gem_detach_phys_object(dev, obj); | |
4400 | ||
4401 | i915_gem_free_object_tail(obj); | |
4402 | } | |
4403 | ||
29105ccc CW |
4404 | int |
4405 | i915_gem_idle(struct drm_device *dev) | |
4406 | { | |
4407 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4408 | int ret; | |
28dfe52a | 4409 | |
29105ccc | 4410 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 4411 | |
8187a2b7 | 4412 | if (dev_priv->mm.suspended || |
d1b851fc ZN |
4413 | (dev_priv->render_ring.gem_object == NULL) || |
4414 | (HAS_BSD(dev) && | |
4415 | dev_priv->bsd_ring.gem_object == NULL)) { | |
29105ccc CW |
4416 | mutex_unlock(&dev->struct_mutex); |
4417 | return 0; | |
28dfe52a EA |
4418 | } |
4419 | ||
29105ccc | 4420 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
4421 | if (ret) { |
4422 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 4423 | return ret; |
6dbe2772 | 4424 | } |
673a394b | 4425 | |
29105ccc CW |
4426 | /* Under UMS, be paranoid and evict. */ |
4427 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { | |
b47eb4a2 | 4428 | ret = i915_gem_evict_inactive(dev); |
29105ccc CW |
4429 | if (ret) { |
4430 | mutex_unlock(&dev->struct_mutex); | |
4431 | return ret; | |
4432 | } | |
4433 | } | |
4434 | ||
4435 | /* Hack! Don't let anybody do execbuf while we don't control the chip. | |
4436 | * We need to replace this with a semaphore, or something. | |
4437 | * And not confound mm.suspended! | |
4438 | */ | |
4439 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 4440 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
4441 | |
4442 | i915_kernel_lost_context(dev); | |
6dbe2772 | 4443 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 4444 | |
6dbe2772 KP |
4445 | mutex_unlock(&dev->struct_mutex); |
4446 | ||
29105ccc CW |
4447 | /* Cancel the retire work handler, which should be idle now. */ |
4448 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
4449 | ||
673a394b EA |
4450 | return 0; |
4451 | } | |
4452 | ||
e552eb70 JB |
4453 | /* |
4454 | * 965+ support PIPE_CONTROL commands, which provide finer grained control | |
4455 | * over cache flushing. | |
4456 | */ | |
8187a2b7 | 4457 | static int |
e552eb70 JB |
4458 | i915_gem_init_pipe_control(struct drm_device *dev) |
4459 | { | |
4460 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4461 | struct drm_gem_object *obj; | |
4462 | struct drm_i915_gem_object *obj_priv; | |
4463 | int ret; | |
4464 | ||
34dc4d44 | 4465 | obj = i915_gem_alloc_object(dev, 4096); |
e552eb70 JB |
4466 | if (obj == NULL) { |
4467 | DRM_ERROR("Failed to allocate seqno page\n"); | |
4468 | ret = -ENOMEM; | |
4469 | goto err; | |
4470 | } | |
4471 | obj_priv = to_intel_bo(obj); | |
4472 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; | |
4473 | ||
4474 | ret = i915_gem_object_pin(obj, 4096); | |
4475 | if (ret) | |
4476 | goto err_unref; | |
4477 | ||
4478 | dev_priv->seqno_gfx_addr = obj_priv->gtt_offset; | |
4479 | dev_priv->seqno_page = kmap(obj_priv->pages[0]); | |
4480 | if (dev_priv->seqno_page == NULL) | |
4481 | goto err_unpin; | |
4482 | ||
4483 | dev_priv->seqno_obj = obj; | |
4484 | memset(dev_priv->seqno_page, 0, PAGE_SIZE); | |
4485 | ||
4486 | return 0; | |
4487 | ||
4488 | err_unpin: | |
4489 | i915_gem_object_unpin(obj); | |
4490 | err_unref: | |
4491 | drm_gem_object_unreference(obj); | |
4492 | err: | |
4493 | return ret; | |
4494 | } | |
4495 | ||
8187a2b7 ZN |
4496 | |
4497 | static void | |
e552eb70 JB |
4498 | i915_gem_cleanup_pipe_control(struct drm_device *dev) |
4499 | { | |
4500 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4501 | struct drm_gem_object *obj; | |
4502 | struct drm_i915_gem_object *obj_priv; | |
4503 | ||
4504 | obj = dev_priv->seqno_obj; | |
4505 | obj_priv = to_intel_bo(obj); | |
4506 | kunmap(obj_priv->pages[0]); | |
4507 | i915_gem_object_unpin(obj); | |
4508 | drm_gem_object_unreference(obj); | |
4509 | dev_priv->seqno_obj = NULL; | |
4510 | ||
4511 | dev_priv->seqno_page = NULL; | |
673a394b EA |
4512 | } |
4513 | ||
8187a2b7 ZN |
4514 | int |
4515 | i915_gem_init_ringbuffer(struct drm_device *dev) | |
4516 | { | |
4517 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4518 | int ret; | |
68f95ba9 | 4519 | |
8187a2b7 ZN |
4520 | if (HAS_PIPE_CONTROL(dev)) { |
4521 | ret = i915_gem_init_pipe_control(dev); | |
4522 | if (ret) | |
4523 | return ret; | |
4524 | } | |
68f95ba9 | 4525 | |
5c1143bb | 4526 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 CW |
4527 | if (ret) |
4528 | goto cleanup_pipe_control; | |
4529 | ||
4530 | if (HAS_BSD(dev)) { | |
5c1143bb | 4531 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4532 | if (ret) |
4533 | goto cleanup_render_ring; | |
d1b851fc | 4534 | } |
68f95ba9 | 4535 | |
6f392d54 CW |
4536 | dev_priv->next_seqno = 1; |
4537 | ||
68f95ba9 CW |
4538 | return 0; |
4539 | ||
4540 | cleanup_render_ring: | |
4541 | intel_cleanup_ring_buffer(dev, &dev_priv->render_ring); | |
4542 | cleanup_pipe_control: | |
4543 | if (HAS_PIPE_CONTROL(dev)) | |
4544 | i915_gem_cleanup_pipe_control(dev); | |
8187a2b7 ZN |
4545 | return ret; |
4546 | } | |
4547 | ||
4548 | void | |
4549 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4550 | { | |
4551 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4552 | ||
4553 | intel_cleanup_ring_buffer(dev, &dev_priv->render_ring); | |
d1b851fc ZN |
4554 | if (HAS_BSD(dev)) |
4555 | intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring); | |
8187a2b7 ZN |
4556 | if (HAS_PIPE_CONTROL(dev)) |
4557 | i915_gem_cleanup_pipe_control(dev); | |
4558 | } | |
4559 | ||
673a394b EA |
4560 | int |
4561 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4562 | struct drm_file *file_priv) | |
4563 | { | |
4564 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4565 | int ret; | |
4566 | ||
79e53945 JB |
4567 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4568 | return 0; | |
4569 | ||
ba1234d1 | 4570 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 4571 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 4572 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
4573 | } |
4574 | ||
673a394b | 4575 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
4576 | dev_priv->mm.suspended = 0; |
4577 | ||
4578 | ret = i915_gem_init_ringbuffer(dev); | |
d816f6ac WF |
4579 | if (ret != 0) { |
4580 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4581 | return ret; |
d816f6ac | 4582 | } |
9bb2d6f9 | 4583 | |
852835f3 | 4584 | BUG_ON(!list_empty(&dev_priv->render_ring.active_list)); |
d1b851fc | 4585 | BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list)); |
673a394b EA |
4586 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
4587 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
852835f3 | 4588 | BUG_ON(!list_empty(&dev_priv->render_ring.request_list)); |
d1b851fc | 4589 | BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list)); |
673a394b | 4590 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4591 | |
5f35308b CW |
4592 | ret = drm_irq_install(dev); |
4593 | if (ret) | |
4594 | goto cleanup_ringbuffer; | |
dbb19d30 | 4595 | |
673a394b | 4596 | return 0; |
5f35308b CW |
4597 | |
4598 | cleanup_ringbuffer: | |
4599 | mutex_lock(&dev->struct_mutex); | |
4600 | i915_gem_cleanup_ringbuffer(dev); | |
4601 | dev_priv->mm.suspended = 1; | |
4602 | mutex_unlock(&dev->struct_mutex); | |
4603 | ||
4604 | return ret; | |
673a394b EA |
4605 | } |
4606 | ||
4607 | int | |
4608 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4609 | struct drm_file *file_priv) | |
4610 | { | |
79e53945 JB |
4611 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4612 | return 0; | |
4613 | ||
dbb19d30 | 4614 | drm_irq_uninstall(dev); |
e6890f6f | 4615 | return i915_gem_idle(dev); |
673a394b EA |
4616 | } |
4617 | ||
4618 | void | |
4619 | i915_gem_lastclose(struct drm_device *dev) | |
4620 | { | |
4621 | int ret; | |
673a394b | 4622 | |
e806b495 EA |
4623 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4624 | return; | |
4625 | ||
6dbe2772 KP |
4626 | ret = i915_gem_idle(dev); |
4627 | if (ret) | |
4628 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4629 | } |
4630 | ||
4631 | void | |
4632 | i915_gem_load(struct drm_device *dev) | |
4633 | { | |
b5aa8a0f | 4634 | int i; |
673a394b EA |
4635 | drm_i915_private_t *dev_priv = dev->dev_private; |
4636 | ||
673a394b | 4637 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
99fcb766 | 4638 | INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list); |
673a394b | 4639 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
f13d3f73 | 4640 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
a09ba7fa | 4641 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
be72615b | 4642 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
852835f3 ZN |
4643 | INIT_LIST_HEAD(&dev_priv->render_ring.active_list); |
4644 | INIT_LIST_HEAD(&dev_priv->render_ring.request_list); | |
d1b851fc ZN |
4645 | if (HAS_BSD(dev)) { |
4646 | INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list); | |
4647 | INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list); | |
4648 | } | |
007cc8ac DV |
4649 | for (i = 0; i < 16; i++) |
4650 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); | |
673a394b EA |
4651 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4652 | i915_gem_retire_work_handler); | |
30dbf0c0 | 4653 | init_completion(&dev_priv->error_completion); |
31169714 CW |
4654 | spin_lock(&shrink_list_lock); |
4655 | list_add(&dev_priv->mm.shrink_list, &shrink_list); | |
4656 | spin_unlock(&shrink_list_lock); | |
4657 | ||
94400120 DA |
4658 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4659 | if (IS_GEN3(dev)) { | |
4660 | u32 tmp = I915_READ(MI_ARB_STATE); | |
4661 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { | |
4662 | /* arb state is a masked write, so set bit + bit in mask */ | |
4663 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); | |
4664 | I915_WRITE(MI_ARB_STATE, tmp); | |
4665 | } | |
4666 | } | |
4667 | ||
de151cf6 | 4668 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4669 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4670 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4671 | |
a6c45cf0 | 4672 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
4673 | dev_priv->num_fence_regs = 16; |
4674 | else | |
4675 | dev_priv->num_fence_regs = 8; | |
4676 | ||
b5aa8a0f | 4677 | /* Initialize fence registers to zero */ |
a6c45cf0 CW |
4678 | switch (INTEL_INFO(dev)->gen) { |
4679 | case 6: | |
4680 | for (i = 0; i < 16; i++) | |
4681 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0); | |
4682 | break; | |
4683 | case 5: | |
4684 | case 4: | |
b5aa8a0f GH |
4685 | for (i = 0; i < 16; i++) |
4686 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); | |
a6c45cf0 CW |
4687 | break; |
4688 | case 3: | |
b5aa8a0f GH |
4689 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
4690 | for (i = 0; i < 8; i++) | |
4691 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); | |
a6c45cf0 CW |
4692 | case 2: |
4693 | for (i = 0; i < 8; i++) | |
4694 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); | |
4695 | break; | |
b5aa8a0f | 4696 | } |
673a394b | 4697 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4698 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
673a394b | 4699 | } |
71acb5eb DA |
4700 | |
4701 | /* | |
4702 | * Create a physically contiguous memory object for this object | |
4703 | * e.g. for cursor + overlay regs | |
4704 | */ | |
995b6762 CW |
4705 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4706 | int id, int size, int align) | |
71acb5eb DA |
4707 | { |
4708 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4709 | struct drm_i915_gem_phys_object *phys_obj; | |
4710 | int ret; | |
4711 | ||
4712 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4713 | return 0; | |
4714 | ||
9a298b2a | 4715 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4716 | if (!phys_obj) |
4717 | return -ENOMEM; | |
4718 | ||
4719 | phys_obj->id = id; | |
4720 | ||
6eeefaf3 | 4721 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4722 | if (!phys_obj->handle) { |
4723 | ret = -ENOMEM; | |
4724 | goto kfree_obj; | |
4725 | } | |
4726 | #ifdef CONFIG_X86 | |
4727 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4728 | #endif | |
4729 | ||
4730 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4731 | ||
4732 | return 0; | |
4733 | kfree_obj: | |
9a298b2a | 4734 | kfree(phys_obj); |
71acb5eb DA |
4735 | return ret; |
4736 | } | |
4737 | ||
995b6762 | 4738 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4739 | { |
4740 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4741 | struct drm_i915_gem_phys_object *phys_obj; | |
4742 | ||
4743 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4744 | return; | |
4745 | ||
4746 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4747 | if (phys_obj->cur_obj) { | |
4748 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4749 | } | |
4750 | ||
4751 | #ifdef CONFIG_X86 | |
4752 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4753 | #endif | |
4754 | drm_pci_free(dev, phys_obj->handle); | |
4755 | kfree(phys_obj); | |
4756 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4757 | } | |
4758 | ||
4759 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4760 | { | |
4761 | int i; | |
4762 | ||
260883c8 | 4763 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4764 | i915_gem_free_phys_object(dev, i); |
4765 | } | |
4766 | ||
4767 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
4768 | struct drm_gem_object *obj) | |
4769 | { | |
4770 | struct drm_i915_gem_object *obj_priv; | |
4771 | int i; | |
4772 | int ret; | |
4773 | int page_count; | |
4774 | ||
23010e43 | 4775 | obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4776 | if (!obj_priv->phys_obj) |
4777 | return; | |
4778 | ||
4bdadb97 | 4779 | ret = i915_gem_object_get_pages(obj, 0); |
71acb5eb DA |
4780 | if (ret) |
4781 | goto out; | |
4782 | ||
4783 | page_count = obj->size / PAGE_SIZE; | |
4784 | ||
4785 | for (i = 0; i < page_count; i++) { | |
856fa198 | 4786 | char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0); |
71acb5eb DA |
4787 | char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
4788 | ||
4789 | memcpy(dst, src, PAGE_SIZE); | |
4790 | kunmap_atomic(dst, KM_USER0); | |
4791 | } | |
856fa198 | 4792 | drm_clflush_pages(obj_priv->pages, page_count); |
71acb5eb | 4793 | drm_agp_chipset_flush(dev); |
d78b47b9 CW |
4794 | |
4795 | i915_gem_object_put_pages(obj); | |
71acb5eb DA |
4796 | out: |
4797 | obj_priv->phys_obj->cur_obj = NULL; | |
4798 | obj_priv->phys_obj = NULL; | |
4799 | } | |
4800 | ||
4801 | int | |
4802 | i915_gem_attach_phys_object(struct drm_device *dev, | |
6eeefaf3 CW |
4803 | struct drm_gem_object *obj, |
4804 | int id, | |
4805 | int align) | |
71acb5eb DA |
4806 | { |
4807 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4808 | struct drm_i915_gem_object *obj_priv; | |
4809 | int ret = 0; | |
4810 | int page_count; | |
4811 | int i; | |
4812 | ||
4813 | if (id > I915_MAX_PHYS_OBJECT) | |
4814 | return -EINVAL; | |
4815 | ||
23010e43 | 4816 | obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4817 | |
4818 | if (obj_priv->phys_obj) { | |
4819 | if (obj_priv->phys_obj->id == id) | |
4820 | return 0; | |
4821 | i915_gem_detach_phys_object(dev, obj); | |
4822 | } | |
4823 | ||
71acb5eb DA |
4824 | /* create a new object */ |
4825 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4826 | ret = i915_gem_init_phys_object(dev, id, | |
6eeefaf3 | 4827 | obj->size, align); |
71acb5eb | 4828 | if (ret) { |
aeb565df | 4829 | DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size); |
71acb5eb DA |
4830 | goto out; |
4831 | } | |
4832 | } | |
4833 | ||
4834 | /* bind to the object */ | |
4835 | obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4836 | obj_priv->phys_obj->cur_obj = obj; | |
4837 | ||
4bdadb97 | 4838 | ret = i915_gem_object_get_pages(obj, 0); |
71acb5eb DA |
4839 | if (ret) { |
4840 | DRM_ERROR("failed to get page list\n"); | |
4841 | goto out; | |
4842 | } | |
4843 | ||
4844 | page_count = obj->size / PAGE_SIZE; | |
4845 | ||
4846 | for (i = 0; i < page_count; i++) { | |
856fa198 | 4847 | char *src = kmap_atomic(obj_priv->pages[i], KM_USER0); |
71acb5eb DA |
4848 | char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
4849 | ||
4850 | memcpy(dst, src, PAGE_SIZE); | |
4851 | kunmap_atomic(src, KM_USER0); | |
4852 | } | |
4853 | ||
d78b47b9 CW |
4854 | i915_gem_object_put_pages(obj); |
4855 | ||
71acb5eb DA |
4856 | return 0; |
4857 | out: | |
4858 | return ret; | |
4859 | } | |
4860 | ||
4861 | static int | |
4862 | i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, | |
4863 | struct drm_i915_gem_pwrite *args, | |
4864 | struct drm_file *file_priv) | |
4865 | { | |
23010e43 | 4866 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4867 | void *obj_addr; |
4868 | int ret; | |
4869 | char __user *user_data; | |
4870 | ||
4871 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
4872 | obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset; | |
4873 | ||
44d98a61 | 4874 | DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size); |
71acb5eb DA |
4875 | ret = copy_from_user(obj_addr, user_data, args->size); |
4876 | if (ret) | |
4877 | return -EFAULT; | |
4878 | ||
4879 | drm_agp_chipset_flush(dev); | |
4880 | return 0; | |
4881 | } | |
b962442e | 4882 | |
f787a5f5 | 4883 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4884 | { |
f787a5f5 | 4885 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4886 | |
4887 | /* Clean up our request list when the client is going away, so that | |
4888 | * later retire_requests won't dereference our soon-to-be-gone | |
4889 | * file_priv. | |
4890 | */ | |
1c25595f | 4891 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4892 | while (!list_empty(&file_priv->mm.request_list)) { |
4893 | struct drm_i915_gem_request *request; | |
4894 | ||
4895 | request = list_first_entry(&file_priv->mm.request_list, | |
4896 | struct drm_i915_gem_request, | |
4897 | client_list); | |
4898 | list_del(&request->client_list); | |
4899 | request->file_priv = NULL; | |
4900 | } | |
1c25595f | 4901 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4902 | } |
31169714 | 4903 | |
1637ef41 CW |
4904 | static int |
4905 | i915_gpu_is_active(struct drm_device *dev) | |
4906 | { | |
4907 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4908 | int lists_empty; | |
4909 | ||
1637ef41 | 4910 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
852835f3 | 4911 | list_empty(&dev_priv->render_ring.active_list); |
d1b851fc ZN |
4912 | if (HAS_BSD(dev)) |
4913 | lists_empty &= list_empty(&dev_priv->bsd_ring.active_list); | |
1637ef41 CW |
4914 | |
4915 | return !lists_empty; | |
4916 | } | |
4917 | ||
31169714 | 4918 | static int |
7f8275d0 | 4919 | i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask) |
31169714 CW |
4920 | { |
4921 | drm_i915_private_t *dev_priv, *next_dev; | |
4922 | struct drm_i915_gem_object *obj_priv, *next_obj; | |
4923 | int cnt = 0; | |
4924 | int would_deadlock = 1; | |
4925 | ||
4926 | /* "fast-path" to count number of available objects */ | |
4927 | if (nr_to_scan == 0) { | |
4928 | spin_lock(&shrink_list_lock); | |
4929 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { | |
4930 | struct drm_device *dev = dev_priv->dev; | |
4931 | ||
4932 | if (mutex_trylock(&dev->struct_mutex)) { | |
4933 | list_for_each_entry(obj_priv, | |
4934 | &dev_priv->mm.inactive_list, | |
4935 | list) | |
4936 | cnt++; | |
4937 | mutex_unlock(&dev->struct_mutex); | |
4938 | } | |
4939 | } | |
4940 | spin_unlock(&shrink_list_lock); | |
4941 | ||
4942 | return (cnt / 100) * sysctl_vfs_cache_pressure; | |
4943 | } | |
4944 | ||
4945 | spin_lock(&shrink_list_lock); | |
4946 | ||
1637ef41 | 4947 | rescan: |
31169714 CW |
4948 | /* first scan for clean buffers */ |
4949 | list_for_each_entry_safe(dev_priv, next_dev, | |
4950 | &shrink_list, mm.shrink_list) { | |
4951 | struct drm_device *dev = dev_priv->dev; | |
4952 | ||
4953 | if (! mutex_trylock(&dev->struct_mutex)) | |
4954 | continue; | |
4955 | ||
4956 | spin_unlock(&shrink_list_lock); | |
b09a1fec | 4957 | i915_gem_retire_requests(dev); |
31169714 CW |
4958 | |
4959 | list_for_each_entry_safe(obj_priv, next_obj, | |
4960 | &dev_priv->mm.inactive_list, | |
4961 | list) { | |
4962 | if (i915_gem_object_is_purgeable(obj_priv)) { | |
a8089e84 | 4963 | i915_gem_object_unbind(&obj_priv->base); |
31169714 CW |
4964 | if (--nr_to_scan <= 0) |
4965 | break; | |
4966 | } | |
4967 | } | |
4968 | ||
4969 | spin_lock(&shrink_list_lock); | |
4970 | mutex_unlock(&dev->struct_mutex); | |
4971 | ||
963b4836 CW |
4972 | would_deadlock = 0; |
4973 | ||
31169714 CW |
4974 | if (nr_to_scan <= 0) |
4975 | break; | |
4976 | } | |
4977 | ||
4978 | /* second pass, evict/count anything still on the inactive list */ | |
4979 | list_for_each_entry_safe(dev_priv, next_dev, | |
4980 | &shrink_list, mm.shrink_list) { | |
4981 | struct drm_device *dev = dev_priv->dev; | |
4982 | ||
4983 | if (! mutex_trylock(&dev->struct_mutex)) | |
4984 | continue; | |
4985 | ||
4986 | spin_unlock(&shrink_list_lock); | |
4987 | ||
4988 | list_for_each_entry_safe(obj_priv, next_obj, | |
4989 | &dev_priv->mm.inactive_list, | |
4990 | list) { | |
4991 | if (nr_to_scan > 0) { | |
a8089e84 | 4992 | i915_gem_object_unbind(&obj_priv->base); |
31169714 CW |
4993 | nr_to_scan--; |
4994 | } else | |
4995 | cnt++; | |
4996 | } | |
4997 | ||
4998 | spin_lock(&shrink_list_lock); | |
4999 | mutex_unlock(&dev->struct_mutex); | |
5000 | ||
5001 | would_deadlock = 0; | |
5002 | } | |
5003 | ||
1637ef41 CW |
5004 | if (nr_to_scan) { |
5005 | int active = 0; | |
5006 | ||
5007 | /* | |
5008 | * We are desperate for pages, so as a last resort, wait | |
5009 | * for the GPU to finish and discard whatever we can. | |
5010 | * This has a dramatic impact to reduce the number of | |
5011 | * OOM-killer events whilst running the GPU aggressively. | |
5012 | */ | |
5013 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { | |
5014 | struct drm_device *dev = dev_priv->dev; | |
5015 | ||
5016 | if (!mutex_trylock(&dev->struct_mutex)) | |
5017 | continue; | |
5018 | ||
5019 | spin_unlock(&shrink_list_lock); | |
5020 | ||
5021 | if (i915_gpu_is_active(dev)) { | |
5022 | i915_gpu_idle(dev); | |
5023 | active++; | |
5024 | } | |
5025 | ||
5026 | spin_lock(&shrink_list_lock); | |
5027 | mutex_unlock(&dev->struct_mutex); | |
5028 | } | |
5029 | ||
5030 | if (active) | |
5031 | goto rescan; | |
5032 | } | |
5033 | ||
31169714 CW |
5034 | spin_unlock(&shrink_list_lock); |
5035 | ||
5036 | if (would_deadlock) | |
5037 | return -1; | |
5038 | else if (cnt > 0) | |
5039 | return (cnt / 100) * sysctl_vfs_cache_pressure; | |
5040 | else | |
5041 | return 0; | |
5042 | } | |
5043 | ||
5044 | static struct shrinker shrinker = { | |
5045 | .shrink = i915_gem_shrink, | |
5046 | .seeks = DEFAULT_SEEKS, | |
5047 | }; | |
5048 | ||
5049 | __init void | |
5050 | i915_gem_shrinker_init(void) | |
5051 | { | |
5052 | register_shrinker(&shrinker); | |
5053 | } | |
5054 | ||
5055 | __exit void | |
5056 | i915_gem_shrinker_exit(void) | |
5057 | { | |
5058 | unregister_shrinker(&shrinker); | |
5059 | } |