Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5a0e3ad6 | 34 | #include <linux/slab.h> |
673a394b | 35 | #include <linux/swap.h> |
79e53945 | 36 | #include <linux/pci.h> |
f8f235e5 | 37 | #include <linux/intel-gtt.h> |
673a394b | 38 | |
0108a3ed | 39 | static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj); |
ba3d8d74 DV |
40 | |
41 | static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, | |
42 | bool pipelined); | |
e47c68e9 EA |
43 | static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); |
44 | static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); | |
e47c68e9 EA |
45 | static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, |
46 | int write); | |
47 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
48 | uint64_t offset, | |
49 | uint64_t size); | |
50 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj); | |
2cf34d7b CW |
51 | static int i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
52 | bool interruptible); | |
de151cf6 | 53 | static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
920afa77 | 54 | unsigned alignment, bool mappable); |
de151cf6 | 55 | static void i915_gem_clear_fence_reg(struct drm_gem_object *obj); |
71acb5eb DA |
56 | static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
57 | struct drm_i915_gem_pwrite *args, | |
58 | struct drm_file *file_priv); | |
be72615b | 59 | static void i915_gem_free_object_tail(struct drm_gem_object *obj); |
673a394b | 60 | |
17250b71 CW |
61 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
62 | int nr_to_scan, | |
63 | gfp_t gfp_mask); | |
64 | ||
31169714 | 65 | |
73aa808f CW |
66 | /* some bookkeeping */ |
67 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
68 | size_t size) | |
69 | { | |
70 | dev_priv->mm.object_count++; | |
71 | dev_priv->mm.object_memory += size; | |
72 | } | |
73 | ||
74 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
75 | size_t size) | |
76 | { | |
77 | dev_priv->mm.object_count--; | |
78 | dev_priv->mm.object_memory -= size; | |
79 | } | |
80 | ||
81 | static void i915_gem_info_add_gtt(struct drm_i915_private *dev_priv, | |
fb7d516a | 82 | struct drm_gem_object *obj) |
73aa808f | 83 | { |
fb7d516a | 84 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
73aa808f | 85 | dev_priv->mm.gtt_count++; |
fb7d516a DV |
86 | dev_priv->mm.gtt_memory += obj->size; |
87 | if (obj_priv->gtt_offset < dev_priv->mm.gtt_mappable_end) { | |
88 | dev_priv->mm.mappable_gtt_used += | |
89 | min_t(size_t, obj->size, | |
90 | dev_priv->mm.gtt_mappable_end | |
91 | - obj_priv->gtt_offset); | |
92 | } | |
73aa808f CW |
93 | } |
94 | ||
95 | static void i915_gem_info_remove_gtt(struct drm_i915_private *dev_priv, | |
fb7d516a | 96 | struct drm_gem_object *obj) |
73aa808f | 97 | { |
fb7d516a | 98 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
73aa808f | 99 | dev_priv->mm.gtt_count--; |
fb7d516a DV |
100 | dev_priv->mm.gtt_memory -= obj->size; |
101 | if (obj_priv->gtt_offset < dev_priv->mm.gtt_mappable_end) { | |
102 | dev_priv->mm.mappable_gtt_used -= | |
103 | min_t(size_t, obj->size, | |
104 | dev_priv->mm.gtt_mappable_end | |
105 | - obj_priv->gtt_offset); | |
106 | } | |
107 | } | |
108 | ||
109 | /** | |
110 | * Update the mappable working set counters. Call _only_ when there is a change | |
111 | * in one of (pin|fault)_mappable and update *_mappable _before_ calling. | |
112 | * @mappable: new state the changed mappable flag (either pin_ or fault_). | |
113 | */ | |
114 | static void | |
115 | i915_gem_info_update_mappable(struct drm_i915_private *dev_priv, | |
116 | struct drm_gem_object *obj, | |
117 | bool mappable) | |
118 | { | |
119 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
120 | ||
121 | if (mappable) { | |
122 | if (obj_priv->pin_mappable && obj_priv->fault_mappable) | |
123 | /* Combined state was already mappable. */ | |
124 | return; | |
125 | dev_priv->mm.gtt_mappable_count++; | |
126 | dev_priv->mm.gtt_mappable_memory += obj->size; | |
127 | } else { | |
128 | if (obj_priv->pin_mappable || obj_priv->fault_mappable) | |
129 | /* Combined state still mappable. */ | |
130 | return; | |
131 | dev_priv->mm.gtt_mappable_count--; | |
132 | dev_priv->mm.gtt_mappable_memory -= obj->size; | |
133 | } | |
73aa808f CW |
134 | } |
135 | ||
136 | static void i915_gem_info_add_pin(struct drm_i915_private *dev_priv, | |
fb7d516a DV |
137 | struct drm_gem_object *obj, |
138 | bool mappable) | |
73aa808f | 139 | { |
fb7d516a | 140 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
73aa808f | 141 | dev_priv->mm.pin_count++; |
fb7d516a DV |
142 | dev_priv->mm.pin_memory += obj->size; |
143 | if (mappable) { | |
144 | obj_priv->pin_mappable = true; | |
145 | i915_gem_info_update_mappable(dev_priv, obj, true); | |
146 | } | |
73aa808f CW |
147 | } |
148 | ||
149 | static void i915_gem_info_remove_pin(struct drm_i915_private *dev_priv, | |
fb7d516a | 150 | struct drm_gem_object *obj) |
73aa808f | 151 | { |
fb7d516a | 152 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
73aa808f | 153 | dev_priv->mm.pin_count--; |
fb7d516a DV |
154 | dev_priv->mm.pin_memory -= obj->size; |
155 | if (obj_priv->pin_mappable) { | |
156 | obj_priv->pin_mappable = false; | |
157 | i915_gem_info_update_mappable(dev_priv, obj, false); | |
158 | } | |
73aa808f CW |
159 | } |
160 | ||
30dbf0c0 CW |
161 | int |
162 | i915_gem_check_is_wedged(struct drm_device *dev) | |
163 | { | |
164 | struct drm_i915_private *dev_priv = dev->dev_private; | |
165 | struct completion *x = &dev_priv->error_completion; | |
166 | unsigned long flags; | |
167 | int ret; | |
168 | ||
169 | if (!atomic_read(&dev_priv->mm.wedged)) | |
170 | return 0; | |
171 | ||
172 | ret = wait_for_completion_interruptible(x); | |
173 | if (ret) | |
174 | return ret; | |
175 | ||
176 | /* Success, we reset the GPU! */ | |
177 | if (!atomic_read(&dev_priv->mm.wedged)) | |
178 | return 0; | |
179 | ||
180 | /* GPU is hung, bump the completion count to account for | |
181 | * the token we just consumed so that we never hit zero and | |
182 | * end up waiting upon a subsequent completion event that | |
183 | * will never happen. | |
184 | */ | |
185 | spin_lock_irqsave(&x->wait.lock, flags); | |
186 | x->done++; | |
187 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
188 | return -EIO; | |
189 | } | |
190 | ||
76c1dec1 CW |
191 | static int i915_mutex_lock_interruptible(struct drm_device *dev) |
192 | { | |
193 | struct drm_i915_private *dev_priv = dev->dev_private; | |
194 | int ret; | |
195 | ||
196 | ret = i915_gem_check_is_wedged(dev); | |
197 | if (ret) | |
198 | return ret; | |
199 | ||
200 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
201 | if (ret) | |
202 | return ret; | |
203 | ||
204 | if (atomic_read(&dev_priv->mm.wedged)) { | |
205 | mutex_unlock(&dev->struct_mutex); | |
206 | return -EAGAIN; | |
207 | } | |
208 | ||
23bc5982 | 209 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
210 | return 0; |
211 | } | |
30dbf0c0 | 212 | |
7d1c4804 CW |
213 | static inline bool |
214 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv) | |
215 | { | |
216 | return obj_priv->gtt_space && | |
217 | !obj_priv->active && | |
218 | obj_priv->pin_count == 0; | |
219 | } | |
220 | ||
73aa808f CW |
221 | int i915_gem_do_init(struct drm_device *dev, |
222 | unsigned long start, | |
53984635 | 223 | unsigned long mappable_end, |
79e53945 | 224 | unsigned long end) |
673a394b EA |
225 | { |
226 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b | 227 | |
79e53945 JB |
228 | if (start >= end || |
229 | (start & (PAGE_SIZE - 1)) != 0 || | |
230 | (end & (PAGE_SIZE - 1)) != 0) { | |
673a394b EA |
231 | return -EINVAL; |
232 | } | |
233 | ||
79e53945 JB |
234 | drm_mm_init(&dev_priv->mm.gtt_space, start, |
235 | end - start); | |
673a394b | 236 | |
73aa808f | 237 | dev_priv->mm.gtt_total = end - start; |
fb7d516a | 238 | dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start; |
53984635 | 239 | dev_priv->mm.gtt_mappable_end = mappable_end; |
79e53945 JB |
240 | |
241 | return 0; | |
242 | } | |
673a394b | 243 | |
79e53945 JB |
244 | int |
245 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
246 | struct drm_file *file_priv) | |
247 | { | |
248 | struct drm_i915_gem_init *args = data; | |
249 | int ret; | |
250 | ||
251 | mutex_lock(&dev->struct_mutex); | |
53984635 | 252 | ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end); |
673a394b EA |
253 | mutex_unlock(&dev->struct_mutex); |
254 | ||
79e53945 | 255 | return ret; |
673a394b EA |
256 | } |
257 | ||
5a125c3c EA |
258 | int |
259 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
260 | struct drm_file *file_priv) | |
261 | { | |
73aa808f | 262 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 263 | struct drm_i915_gem_get_aperture *args = data; |
5a125c3c EA |
264 | |
265 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
266 | return -ENODEV; | |
267 | ||
73aa808f CW |
268 | mutex_lock(&dev->struct_mutex); |
269 | args->aper_size = dev_priv->mm.gtt_total; | |
270 | args->aper_available_size = args->aper_size - dev_priv->mm.pin_memory; | |
271 | mutex_unlock(&dev->struct_mutex); | |
5a125c3c EA |
272 | |
273 | return 0; | |
274 | } | |
275 | ||
673a394b EA |
276 | |
277 | /** | |
278 | * Creates a new mm object and returns a handle to it. | |
279 | */ | |
280 | int | |
281 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
282 | struct drm_file *file_priv) | |
283 | { | |
284 | struct drm_i915_gem_create *args = data; | |
285 | struct drm_gem_object *obj; | |
a1a2d1d3 PP |
286 | int ret; |
287 | u32 handle; | |
673a394b EA |
288 | |
289 | args->size = roundup(args->size, PAGE_SIZE); | |
290 | ||
291 | /* Allocate the new object */ | |
ac52bc56 | 292 | obj = i915_gem_alloc_object(dev, args->size); |
673a394b EA |
293 | if (obj == NULL) |
294 | return -ENOMEM; | |
295 | ||
296 | ret = drm_gem_handle_create(file_priv, obj, &handle); | |
1dfd9754 | 297 | if (ret) { |
202f2fef CW |
298 | drm_gem_object_release(obj); |
299 | i915_gem_info_remove_obj(dev->dev_private, obj->size); | |
300 | kfree(obj); | |
673a394b | 301 | return ret; |
1dfd9754 | 302 | } |
673a394b | 303 | |
202f2fef CW |
304 | /* drop reference from allocate - handle holds it now */ |
305 | drm_gem_object_unreference(obj); | |
306 | trace_i915_gem_object_create(obj); | |
307 | ||
1dfd9754 | 308 | args->handle = handle; |
673a394b EA |
309 | return 0; |
310 | } | |
311 | ||
16e809ac DV |
312 | static bool |
313 | i915_gem_object_cpu_accessible(struct drm_i915_gem_object *obj) | |
314 | { | |
315 | struct drm_device *dev = obj->base.dev; | |
316 | drm_i915_private_t *dev_priv = dev->dev_private; | |
317 | ||
318 | return obj->gtt_space == NULL || | |
319 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; | |
320 | } | |
321 | ||
280b713b EA |
322 | static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj) |
323 | { | |
324 | drm_i915_private_t *dev_priv = obj->dev->dev_private; | |
23010e43 | 325 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
280b713b EA |
326 | |
327 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
328 | obj_priv->tiling_mode != I915_TILING_NONE; | |
329 | } | |
330 | ||
99a03df5 | 331 | static inline void |
40123c1f EA |
332 | slow_shmem_copy(struct page *dst_page, |
333 | int dst_offset, | |
334 | struct page *src_page, | |
335 | int src_offset, | |
336 | int length) | |
337 | { | |
338 | char *dst_vaddr, *src_vaddr; | |
339 | ||
99a03df5 CW |
340 | dst_vaddr = kmap(dst_page); |
341 | src_vaddr = kmap(src_page); | |
40123c1f EA |
342 | |
343 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); | |
344 | ||
99a03df5 CW |
345 | kunmap(src_page); |
346 | kunmap(dst_page); | |
40123c1f EA |
347 | } |
348 | ||
99a03df5 | 349 | static inline void |
280b713b EA |
350 | slow_shmem_bit17_copy(struct page *gpu_page, |
351 | int gpu_offset, | |
352 | struct page *cpu_page, | |
353 | int cpu_offset, | |
354 | int length, | |
355 | int is_read) | |
356 | { | |
357 | char *gpu_vaddr, *cpu_vaddr; | |
358 | ||
359 | /* Use the unswizzled path if this page isn't affected. */ | |
360 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { | |
361 | if (is_read) | |
362 | return slow_shmem_copy(cpu_page, cpu_offset, | |
363 | gpu_page, gpu_offset, length); | |
364 | else | |
365 | return slow_shmem_copy(gpu_page, gpu_offset, | |
366 | cpu_page, cpu_offset, length); | |
367 | } | |
368 | ||
99a03df5 CW |
369 | gpu_vaddr = kmap(gpu_page); |
370 | cpu_vaddr = kmap(cpu_page); | |
280b713b EA |
371 | |
372 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's | |
373 | * XORing with the other bits (A9 for Y, A9 and A10 for X) | |
374 | */ | |
375 | while (length > 0) { | |
376 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
377 | int this_length = min(cacheline_end - gpu_offset, length); | |
378 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
379 | ||
380 | if (is_read) { | |
381 | memcpy(cpu_vaddr + cpu_offset, | |
382 | gpu_vaddr + swizzled_gpu_offset, | |
383 | this_length); | |
384 | } else { | |
385 | memcpy(gpu_vaddr + swizzled_gpu_offset, | |
386 | cpu_vaddr + cpu_offset, | |
387 | this_length); | |
388 | } | |
389 | cpu_offset += this_length; | |
390 | gpu_offset += this_length; | |
391 | length -= this_length; | |
392 | } | |
393 | ||
99a03df5 CW |
394 | kunmap(cpu_page); |
395 | kunmap(gpu_page); | |
280b713b EA |
396 | } |
397 | ||
eb01459f EA |
398 | /** |
399 | * This is the fast shmem pread path, which attempts to copy_from_user directly | |
400 | * from the backing pages of the object to the user's address space. On a | |
401 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). | |
402 | */ | |
403 | static int | |
404 | i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj, | |
405 | struct drm_i915_gem_pread *args, | |
406 | struct drm_file *file_priv) | |
407 | { | |
23010e43 | 408 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
e5281ccd | 409 | struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping; |
eb01459f | 410 | ssize_t remain; |
e5281ccd | 411 | loff_t offset; |
eb01459f EA |
412 | char __user *user_data; |
413 | int page_offset, page_length; | |
eb01459f EA |
414 | |
415 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
416 | remain = args->size; | |
417 | ||
23010e43 | 418 | obj_priv = to_intel_bo(obj); |
eb01459f EA |
419 | offset = args->offset; |
420 | ||
421 | while (remain > 0) { | |
e5281ccd CW |
422 | struct page *page; |
423 | char *vaddr; | |
424 | int ret; | |
425 | ||
eb01459f EA |
426 | /* Operation in this page |
427 | * | |
eb01459f EA |
428 | * page_offset = offset within page |
429 | * page_length = bytes to copy for this page | |
430 | */ | |
eb01459f EA |
431 | page_offset = offset & (PAGE_SIZE-1); |
432 | page_length = remain; | |
433 | if ((page_offset + remain) > PAGE_SIZE) | |
434 | page_length = PAGE_SIZE - page_offset; | |
435 | ||
e5281ccd CW |
436 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
437 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
438 | if (IS_ERR(page)) | |
439 | return PTR_ERR(page); | |
440 | ||
441 | vaddr = kmap_atomic(page); | |
442 | ret = __copy_to_user_inatomic(user_data, | |
443 | vaddr + page_offset, | |
444 | page_length); | |
445 | kunmap_atomic(vaddr); | |
446 | ||
447 | mark_page_accessed(page); | |
448 | page_cache_release(page); | |
449 | if (ret) | |
4f27b75d | 450 | return -EFAULT; |
eb01459f EA |
451 | |
452 | remain -= page_length; | |
453 | user_data += page_length; | |
454 | offset += page_length; | |
455 | } | |
456 | ||
4f27b75d | 457 | return 0; |
eb01459f EA |
458 | } |
459 | ||
460 | /** | |
461 | * This is the fallback shmem pread path, which allocates temporary storage | |
462 | * in kernel space to copy_to_user into outside of the struct_mutex, so we | |
463 | * can copy out of the object's backing pages while holding the struct mutex | |
464 | * and not take page faults. | |
465 | */ | |
466 | static int | |
467 | i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
468 | struct drm_i915_gem_pread *args, | |
469 | struct drm_file *file_priv) | |
470 | { | |
e5281ccd | 471 | struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping; |
23010e43 | 472 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
eb01459f EA |
473 | struct mm_struct *mm = current->mm; |
474 | struct page **user_pages; | |
475 | ssize_t remain; | |
476 | loff_t offset, pinned_pages, i; | |
477 | loff_t first_data_page, last_data_page, num_pages; | |
e5281ccd CW |
478 | int shmem_page_offset; |
479 | int data_page_index, data_page_offset; | |
eb01459f EA |
480 | int page_length; |
481 | int ret; | |
482 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 483 | int do_bit17_swizzling; |
eb01459f EA |
484 | |
485 | remain = args->size; | |
486 | ||
487 | /* Pin the user pages containing the data. We can't fault while | |
488 | * holding the struct mutex, yet we want to hold it while | |
489 | * dereferencing the user data. | |
490 | */ | |
491 | first_data_page = data_ptr / PAGE_SIZE; | |
492 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
493 | num_pages = last_data_page - first_data_page + 1; | |
494 | ||
4f27b75d | 495 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
eb01459f EA |
496 | if (user_pages == NULL) |
497 | return -ENOMEM; | |
498 | ||
4f27b75d | 499 | mutex_unlock(&dev->struct_mutex); |
eb01459f EA |
500 | down_read(&mm->mmap_sem); |
501 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
e5e9ecde | 502 | num_pages, 1, 0, user_pages, NULL); |
eb01459f | 503 | up_read(&mm->mmap_sem); |
4f27b75d | 504 | mutex_lock(&dev->struct_mutex); |
eb01459f EA |
505 | if (pinned_pages < num_pages) { |
506 | ret = -EFAULT; | |
4f27b75d | 507 | goto out; |
eb01459f EA |
508 | } |
509 | ||
4f27b75d CW |
510 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
511 | args->offset, | |
512 | args->size); | |
07f73f69 | 513 | if (ret) |
4f27b75d | 514 | goto out; |
eb01459f | 515 | |
4f27b75d | 516 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 517 | |
23010e43 | 518 | obj_priv = to_intel_bo(obj); |
eb01459f EA |
519 | offset = args->offset; |
520 | ||
521 | while (remain > 0) { | |
e5281ccd CW |
522 | struct page *page; |
523 | ||
eb01459f EA |
524 | /* Operation in this page |
525 | * | |
eb01459f EA |
526 | * shmem_page_offset = offset within page in shmem file |
527 | * data_page_index = page number in get_user_pages return | |
528 | * data_page_offset = offset with data_page_index page. | |
529 | * page_length = bytes to copy for this page | |
530 | */ | |
eb01459f EA |
531 | shmem_page_offset = offset & ~PAGE_MASK; |
532 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
533 | data_page_offset = data_ptr & ~PAGE_MASK; | |
534 | ||
535 | page_length = remain; | |
536 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
537 | page_length = PAGE_SIZE - shmem_page_offset; | |
538 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
539 | page_length = PAGE_SIZE - data_page_offset; | |
540 | ||
e5281ccd CW |
541 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
542 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
543 | if (IS_ERR(page)) | |
544 | return PTR_ERR(page); | |
545 | ||
280b713b | 546 | if (do_bit17_swizzling) { |
e5281ccd | 547 | slow_shmem_bit17_copy(page, |
280b713b | 548 | shmem_page_offset, |
99a03df5 CW |
549 | user_pages[data_page_index], |
550 | data_page_offset, | |
551 | page_length, | |
552 | 1); | |
553 | } else { | |
554 | slow_shmem_copy(user_pages[data_page_index], | |
555 | data_page_offset, | |
e5281ccd | 556 | page, |
99a03df5 CW |
557 | shmem_page_offset, |
558 | page_length); | |
280b713b | 559 | } |
eb01459f | 560 | |
e5281ccd CW |
561 | mark_page_accessed(page); |
562 | page_cache_release(page); | |
563 | ||
eb01459f EA |
564 | remain -= page_length; |
565 | data_ptr += page_length; | |
566 | offset += page_length; | |
567 | } | |
568 | ||
4f27b75d | 569 | out: |
eb01459f EA |
570 | for (i = 0; i < pinned_pages; i++) { |
571 | SetPageDirty(user_pages[i]); | |
e5281ccd | 572 | mark_page_accessed(user_pages[i]); |
eb01459f EA |
573 | page_cache_release(user_pages[i]); |
574 | } | |
8e7d2b2c | 575 | drm_free_large(user_pages); |
eb01459f EA |
576 | |
577 | return ret; | |
578 | } | |
579 | ||
673a394b EA |
580 | /** |
581 | * Reads data from the object referenced by handle. | |
582 | * | |
583 | * On error, the contents of *data are undefined. | |
584 | */ | |
585 | int | |
586 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
587 | struct drm_file *file_priv) | |
588 | { | |
589 | struct drm_i915_gem_pread *args = data; | |
590 | struct drm_gem_object *obj; | |
591 | struct drm_i915_gem_object *obj_priv; | |
35b62a89 | 592 | int ret = 0; |
673a394b | 593 | |
4f27b75d | 594 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 595 | if (ret) |
4f27b75d | 596 | return ret; |
673a394b EA |
597 | |
598 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1d7cfea1 CW |
599 | if (obj == NULL) { |
600 | ret = -ENOENT; | |
601 | goto unlock; | |
4f27b75d | 602 | } |
23010e43 | 603 | obj_priv = to_intel_bo(obj); |
673a394b | 604 | |
7dcd2499 CW |
605 | /* Bounds check source. */ |
606 | if (args->offset > obj->size || args->size > obj->size - args->offset) { | |
ce9d419d | 607 | ret = -EINVAL; |
35b62a89 | 608 | goto out; |
ce9d419d CW |
609 | } |
610 | ||
35b62a89 CW |
611 | if (args->size == 0) |
612 | goto out; | |
613 | ||
ce9d419d CW |
614 | if (!access_ok(VERIFY_WRITE, |
615 | (char __user *)(uintptr_t)args->data_ptr, | |
616 | args->size)) { | |
617 | ret = -EFAULT; | |
35b62a89 | 618 | goto out; |
673a394b EA |
619 | } |
620 | ||
b5e4feb6 CW |
621 | ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr, |
622 | args->size); | |
623 | if (ret) { | |
624 | ret = -EFAULT; | |
625 | goto out; | |
280b713b | 626 | } |
673a394b | 627 | |
4f27b75d CW |
628 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
629 | args->offset, | |
630 | args->size); | |
631 | if (ret) | |
e5281ccd | 632 | goto out; |
4f27b75d CW |
633 | |
634 | ret = -EFAULT; | |
635 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
280b713b | 636 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv); |
4f27b75d CW |
637 | if (ret == -EFAULT) |
638 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv); | |
673a394b | 639 | |
35b62a89 | 640 | out: |
4f27b75d | 641 | drm_gem_object_unreference(obj); |
1d7cfea1 | 642 | unlock: |
4f27b75d | 643 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 644 | return ret; |
673a394b EA |
645 | } |
646 | ||
0839ccb8 KP |
647 | /* This is the fast write path which cannot handle |
648 | * page faults in the source data | |
9b7530cc | 649 | */ |
0839ccb8 KP |
650 | |
651 | static inline int | |
652 | fast_user_write(struct io_mapping *mapping, | |
653 | loff_t page_base, int page_offset, | |
654 | char __user *user_data, | |
655 | int length) | |
9b7530cc | 656 | { |
9b7530cc | 657 | char *vaddr_atomic; |
0839ccb8 | 658 | unsigned long unwritten; |
9b7530cc | 659 | |
3e4d3af5 | 660 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
0839ccb8 KP |
661 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
662 | user_data, length); | |
3e4d3af5 | 663 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 664 | return unwritten; |
0839ccb8 KP |
665 | } |
666 | ||
667 | /* Here's the write path which can sleep for | |
668 | * page faults | |
669 | */ | |
670 | ||
ab34c226 | 671 | static inline void |
3de09aa3 EA |
672 | slow_kernel_write(struct io_mapping *mapping, |
673 | loff_t gtt_base, int gtt_offset, | |
674 | struct page *user_page, int user_offset, | |
675 | int length) | |
0839ccb8 | 676 | { |
ab34c226 CW |
677 | char __iomem *dst_vaddr; |
678 | char *src_vaddr; | |
0839ccb8 | 679 | |
ab34c226 CW |
680 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
681 | src_vaddr = kmap(user_page); | |
682 | ||
683 | memcpy_toio(dst_vaddr + gtt_offset, | |
684 | src_vaddr + user_offset, | |
685 | length); | |
686 | ||
687 | kunmap(user_page); | |
688 | io_mapping_unmap(dst_vaddr); | |
9b7530cc LT |
689 | } |
690 | ||
3de09aa3 EA |
691 | /** |
692 | * This is the fast pwrite path, where we copy the data directly from the | |
693 | * user into the GTT, uncached. | |
694 | */ | |
673a394b | 695 | static int |
3de09aa3 EA |
696 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
697 | struct drm_i915_gem_pwrite *args, | |
698 | struct drm_file *file_priv) | |
673a394b | 699 | { |
23010e43 | 700 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
0839ccb8 | 701 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 702 | ssize_t remain; |
0839ccb8 | 703 | loff_t offset, page_base; |
673a394b | 704 | char __user *user_data; |
0839ccb8 | 705 | int page_offset, page_length; |
673a394b EA |
706 | |
707 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
708 | remain = args->size; | |
673a394b | 709 | |
23010e43 | 710 | obj_priv = to_intel_bo(obj); |
673a394b | 711 | offset = obj_priv->gtt_offset + args->offset; |
673a394b EA |
712 | |
713 | while (remain > 0) { | |
714 | /* Operation in this page | |
715 | * | |
0839ccb8 KP |
716 | * page_base = page offset within aperture |
717 | * page_offset = offset within page | |
718 | * page_length = bytes to copy for this page | |
673a394b | 719 | */ |
0839ccb8 KP |
720 | page_base = (offset & ~(PAGE_SIZE-1)); |
721 | page_offset = offset & (PAGE_SIZE-1); | |
722 | page_length = remain; | |
723 | if ((page_offset + remain) > PAGE_SIZE) | |
724 | page_length = PAGE_SIZE - page_offset; | |
725 | ||
0839ccb8 | 726 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
727 | * source page isn't available. Return the error and we'll |
728 | * retry in the slow path. | |
0839ccb8 | 729 | */ |
fbd5a26d CW |
730 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
731 | page_offset, user_data, page_length)) | |
732 | ||
733 | return -EFAULT; | |
673a394b | 734 | |
0839ccb8 KP |
735 | remain -= page_length; |
736 | user_data += page_length; | |
737 | offset += page_length; | |
673a394b | 738 | } |
673a394b | 739 | |
fbd5a26d | 740 | return 0; |
673a394b EA |
741 | } |
742 | ||
3de09aa3 EA |
743 | /** |
744 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin | |
745 | * the memory and maps it using kmap_atomic for copying. | |
746 | * | |
747 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU | |
748 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). | |
749 | */ | |
3043c60c | 750 | static int |
3de09aa3 EA |
751 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
752 | struct drm_i915_gem_pwrite *args, | |
753 | struct drm_file *file_priv) | |
673a394b | 754 | { |
23010e43 | 755 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
3de09aa3 EA |
756 | drm_i915_private_t *dev_priv = dev->dev_private; |
757 | ssize_t remain; | |
758 | loff_t gtt_page_base, offset; | |
759 | loff_t first_data_page, last_data_page, num_pages; | |
760 | loff_t pinned_pages, i; | |
761 | struct page **user_pages; | |
762 | struct mm_struct *mm = current->mm; | |
763 | int gtt_page_offset, data_page_offset, data_page_index, page_length; | |
673a394b | 764 | int ret; |
3de09aa3 EA |
765 | uint64_t data_ptr = args->data_ptr; |
766 | ||
767 | remain = args->size; | |
768 | ||
769 | /* Pin the user pages containing the data. We can't fault while | |
770 | * holding the struct mutex, and all of the pwrite implementations | |
771 | * want to hold it while dereferencing the user data. | |
772 | */ | |
773 | first_data_page = data_ptr / PAGE_SIZE; | |
774 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
775 | num_pages = last_data_page - first_data_page + 1; | |
776 | ||
fbd5a26d | 777 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
3de09aa3 EA |
778 | if (user_pages == NULL) |
779 | return -ENOMEM; | |
780 | ||
fbd5a26d | 781 | mutex_unlock(&dev->struct_mutex); |
3de09aa3 EA |
782 | down_read(&mm->mmap_sem); |
783 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
784 | num_pages, 0, 0, user_pages, NULL); | |
785 | up_read(&mm->mmap_sem); | |
fbd5a26d | 786 | mutex_lock(&dev->struct_mutex); |
3de09aa3 EA |
787 | if (pinned_pages < num_pages) { |
788 | ret = -EFAULT; | |
789 | goto out_unpin_pages; | |
790 | } | |
673a394b | 791 | |
3de09aa3 EA |
792 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
793 | if (ret) | |
fbd5a26d | 794 | goto out_unpin_pages; |
3de09aa3 | 795 | |
23010e43 | 796 | obj_priv = to_intel_bo(obj); |
3de09aa3 EA |
797 | offset = obj_priv->gtt_offset + args->offset; |
798 | ||
799 | while (remain > 0) { | |
800 | /* Operation in this page | |
801 | * | |
802 | * gtt_page_base = page offset within aperture | |
803 | * gtt_page_offset = offset within page in aperture | |
804 | * data_page_index = page number in get_user_pages return | |
805 | * data_page_offset = offset with data_page_index page. | |
806 | * page_length = bytes to copy for this page | |
807 | */ | |
808 | gtt_page_base = offset & PAGE_MASK; | |
809 | gtt_page_offset = offset & ~PAGE_MASK; | |
810 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
811 | data_page_offset = data_ptr & ~PAGE_MASK; | |
812 | ||
813 | page_length = remain; | |
814 | if ((gtt_page_offset + page_length) > PAGE_SIZE) | |
815 | page_length = PAGE_SIZE - gtt_page_offset; | |
816 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
817 | page_length = PAGE_SIZE - data_page_offset; | |
818 | ||
ab34c226 CW |
819 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
820 | gtt_page_base, gtt_page_offset, | |
821 | user_pages[data_page_index], | |
822 | data_page_offset, | |
823 | page_length); | |
3de09aa3 EA |
824 | |
825 | remain -= page_length; | |
826 | offset += page_length; | |
827 | data_ptr += page_length; | |
828 | } | |
829 | ||
3de09aa3 EA |
830 | out_unpin_pages: |
831 | for (i = 0; i < pinned_pages; i++) | |
832 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 833 | drm_free_large(user_pages); |
3de09aa3 EA |
834 | |
835 | return ret; | |
836 | } | |
837 | ||
40123c1f EA |
838 | /** |
839 | * This is the fast shmem pwrite path, which attempts to directly | |
840 | * copy_from_user into the kmapped pages backing the object. | |
841 | */ | |
3043c60c | 842 | static int |
40123c1f EA |
843 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
844 | struct drm_i915_gem_pwrite *args, | |
845 | struct drm_file *file_priv) | |
673a394b | 846 | { |
e5281ccd | 847 | struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping; |
23010e43 | 848 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
40123c1f | 849 | ssize_t remain; |
e5281ccd | 850 | loff_t offset; |
40123c1f EA |
851 | char __user *user_data; |
852 | int page_offset, page_length; | |
40123c1f EA |
853 | |
854 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
855 | remain = args->size; | |
673a394b | 856 | |
23010e43 | 857 | obj_priv = to_intel_bo(obj); |
40123c1f EA |
858 | offset = args->offset; |
859 | obj_priv->dirty = 1; | |
860 | ||
861 | while (remain > 0) { | |
e5281ccd CW |
862 | struct page *page; |
863 | char *vaddr; | |
864 | int ret; | |
865 | ||
40123c1f EA |
866 | /* Operation in this page |
867 | * | |
40123c1f EA |
868 | * page_offset = offset within page |
869 | * page_length = bytes to copy for this page | |
870 | */ | |
40123c1f EA |
871 | page_offset = offset & (PAGE_SIZE-1); |
872 | page_length = remain; | |
873 | if ((page_offset + remain) > PAGE_SIZE) | |
874 | page_length = PAGE_SIZE - page_offset; | |
875 | ||
e5281ccd CW |
876 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
877 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
878 | if (IS_ERR(page)) | |
879 | return PTR_ERR(page); | |
880 | ||
881 | vaddr = kmap_atomic(page, KM_USER0); | |
882 | ret = __copy_from_user_inatomic(vaddr + page_offset, | |
883 | user_data, | |
884 | page_length); | |
885 | kunmap_atomic(vaddr, KM_USER0); | |
886 | ||
887 | set_page_dirty(page); | |
888 | mark_page_accessed(page); | |
889 | page_cache_release(page); | |
890 | ||
891 | /* If we get a fault while copying data, then (presumably) our | |
892 | * source page isn't available. Return the error and we'll | |
893 | * retry in the slow path. | |
894 | */ | |
895 | if (ret) | |
fbd5a26d | 896 | return -EFAULT; |
40123c1f EA |
897 | |
898 | remain -= page_length; | |
899 | user_data += page_length; | |
900 | offset += page_length; | |
901 | } | |
902 | ||
fbd5a26d | 903 | return 0; |
40123c1f EA |
904 | } |
905 | ||
906 | /** | |
907 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin | |
908 | * the memory and maps it using kmap_atomic for copying. | |
909 | * | |
910 | * This avoids taking mmap_sem for faulting on the user's address while the | |
911 | * struct_mutex is held. | |
912 | */ | |
913 | static int | |
914 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
915 | struct drm_i915_gem_pwrite *args, | |
916 | struct drm_file *file_priv) | |
917 | { | |
e5281ccd | 918 | struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping; |
23010e43 | 919 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
40123c1f EA |
920 | struct mm_struct *mm = current->mm; |
921 | struct page **user_pages; | |
922 | ssize_t remain; | |
923 | loff_t offset, pinned_pages, i; | |
924 | loff_t first_data_page, last_data_page, num_pages; | |
e5281ccd | 925 | int shmem_page_offset; |
40123c1f EA |
926 | int data_page_index, data_page_offset; |
927 | int page_length; | |
928 | int ret; | |
929 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 930 | int do_bit17_swizzling; |
40123c1f EA |
931 | |
932 | remain = args->size; | |
933 | ||
934 | /* Pin the user pages containing the data. We can't fault while | |
935 | * holding the struct mutex, and all of the pwrite implementations | |
936 | * want to hold it while dereferencing the user data. | |
937 | */ | |
938 | first_data_page = data_ptr / PAGE_SIZE; | |
939 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
940 | num_pages = last_data_page - first_data_page + 1; | |
941 | ||
4f27b75d | 942 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
40123c1f EA |
943 | if (user_pages == NULL) |
944 | return -ENOMEM; | |
945 | ||
fbd5a26d | 946 | mutex_unlock(&dev->struct_mutex); |
40123c1f EA |
947 | down_read(&mm->mmap_sem); |
948 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
949 | num_pages, 0, 0, user_pages, NULL); | |
950 | up_read(&mm->mmap_sem); | |
fbd5a26d | 951 | mutex_lock(&dev->struct_mutex); |
40123c1f EA |
952 | if (pinned_pages < num_pages) { |
953 | ret = -EFAULT; | |
fbd5a26d | 954 | goto out; |
673a394b EA |
955 | } |
956 | ||
fbd5a26d | 957 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
07f73f69 | 958 | if (ret) |
fbd5a26d | 959 | goto out; |
40123c1f | 960 | |
fbd5a26d | 961 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 962 | |
23010e43 | 963 | obj_priv = to_intel_bo(obj); |
673a394b | 964 | offset = args->offset; |
40123c1f | 965 | obj_priv->dirty = 1; |
673a394b | 966 | |
40123c1f | 967 | while (remain > 0) { |
e5281ccd CW |
968 | struct page *page; |
969 | ||
40123c1f EA |
970 | /* Operation in this page |
971 | * | |
40123c1f EA |
972 | * shmem_page_offset = offset within page in shmem file |
973 | * data_page_index = page number in get_user_pages return | |
974 | * data_page_offset = offset with data_page_index page. | |
975 | * page_length = bytes to copy for this page | |
976 | */ | |
40123c1f EA |
977 | shmem_page_offset = offset & ~PAGE_MASK; |
978 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
979 | data_page_offset = data_ptr & ~PAGE_MASK; | |
980 | ||
981 | page_length = remain; | |
982 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
983 | page_length = PAGE_SIZE - shmem_page_offset; | |
984 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
985 | page_length = PAGE_SIZE - data_page_offset; | |
986 | ||
e5281ccd CW |
987 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
988 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
989 | if (IS_ERR(page)) { | |
990 | ret = PTR_ERR(page); | |
991 | goto out; | |
992 | } | |
993 | ||
280b713b | 994 | if (do_bit17_swizzling) { |
e5281ccd | 995 | slow_shmem_bit17_copy(page, |
280b713b EA |
996 | shmem_page_offset, |
997 | user_pages[data_page_index], | |
998 | data_page_offset, | |
99a03df5 CW |
999 | page_length, |
1000 | 0); | |
1001 | } else { | |
e5281ccd | 1002 | slow_shmem_copy(page, |
99a03df5 CW |
1003 | shmem_page_offset, |
1004 | user_pages[data_page_index], | |
1005 | data_page_offset, | |
1006 | page_length); | |
280b713b | 1007 | } |
40123c1f | 1008 | |
e5281ccd CW |
1009 | set_page_dirty(page); |
1010 | mark_page_accessed(page); | |
1011 | page_cache_release(page); | |
1012 | ||
40123c1f EA |
1013 | remain -= page_length; |
1014 | data_ptr += page_length; | |
1015 | offset += page_length; | |
673a394b EA |
1016 | } |
1017 | ||
fbd5a26d | 1018 | out: |
40123c1f EA |
1019 | for (i = 0; i < pinned_pages; i++) |
1020 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 1021 | drm_free_large(user_pages); |
673a394b | 1022 | |
40123c1f | 1023 | return ret; |
673a394b EA |
1024 | } |
1025 | ||
1026 | /** | |
1027 | * Writes data to the object referenced by handle. | |
1028 | * | |
1029 | * On error, the contents of the buffer that were to be modified are undefined. | |
1030 | */ | |
1031 | int | |
1032 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1033 | struct drm_file *file) |
673a394b EA |
1034 | { |
1035 | struct drm_i915_gem_pwrite *args = data; | |
1036 | struct drm_gem_object *obj; | |
1037 | struct drm_i915_gem_object *obj_priv; | |
1038 | int ret = 0; | |
1039 | ||
fbd5a26d | 1040 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1041 | if (ret) |
fbd5a26d | 1042 | return ret; |
1d7cfea1 CW |
1043 | |
1044 | obj = drm_gem_object_lookup(dev, file, args->handle); | |
1045 | if (obj == NULL) { | |
1046 | ret = -ENOENT; | |
1047 | goto unlock; | |
fbd5a26d | 1048 | } |
23010e43 | 1049 | obj_priv = to_intel_bo(obj); |
673a394b | 1050 | |
fbd5a26d | 1051 | |
7dcd2499 CW |
1052 | /* Bounds check destination. */ |
1053 | if (args->offset > obj->size || args->size > obj->size - args->offset) { | |
ce9d419d | 1054 | ret = -EINVAL; |
35b62a89 | 1055 | goto out; |
ce9d419d CW |
1056 | } |
1057 | ||
35b62a89 CW |
1058 | if (args->size == 0) |
1059 | goto out; | |
1060 | ||
ce9d419d CW |
1061 | if (!access_ok(VERIFY_READ, |
1062 | (char __user *)(uintptr_t)args->data_ptr, | |
1063 | args->size)) { | |
1064 | ret = -EFAULT; | |
35b62a89 | 1065 | goto out; |
673a394b EA |
1066 | } |
1067 | ||
b5e4feb6 CW |
1068 | ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr, |
1069 | args->size); | |
1070 | if (ret) { | |
1071 | ret = -EFAULT; | |
1072 | goto out; | |
673a394b EA |
1073 | } |
1074 | ||
1075 | /* We can only do the GTT pwrite on untiled buffers, as otherwise | |
1076 | * it would end up going through the fenced access, and we'll get | |
1077 | * different detiling behavior between reading and writing. | |
1078 | * pread/pwrite currently are reading and writing from the CPU | |
1079 | * perspective, requiring manual detiling by the client. | |
1080 | */ | |
71acb5eb | 1081 | if (obj_priv->phys_obj) |
fbd5a26d | 1082 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
71acb5eb | 1083 | else if (obj_priv->tiling_mode == I915_TILING_NONE && |
5cdf5881 | 1084 | obj_priv->gtt_space && |
9b8c4a0b | 1085 | obj->write_domain != I915_GEM_DOMAIN_CPU) { |
920afa77 | 1086 | ret = i915_gem_object_pin(obj, 0, true); |
fbd5a26d CW |
1087 | if (ret) |
1088 | goto out; | |
1089 | ||
1090 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); | |
1091 | if (ret) | |
1092 | goto out_unpin; | |
1093 | ||
1094 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); | |
1095 | if (ret == -EFAULT) | |
1096 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file); | |
1097 | ||
1098 | out_unpin: | |
1099 | i915_gem_object_unpin(obj); | |
40123c1f | 1100 | } else { |
fbd5a26d CW |
1101 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
1102 | if (ret) | |
e5281ccd | 1103 | goto out; |
673a394b | 1104 | |
fbd5a26d CW |
1105 | ret = -EFAULT; |
1106 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
1107 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file); | |
1108 | if (ret == -EFAULT) | |
1109 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file); | |
fbd5a26d | 1110 | } |
673a394b | 1111 | |
35b62a89 | 1112 | out: |
fbd5a26d | 1113 | drm_gem_object_unreference(obj); |
1d7cfea1 | 1114 | unlock: |
fbd5a26d | 1115 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
1116 | return ret; |
1117 | } | |
1118 | ||
1119 | /** | |
2ef7eeaa EA |
1120 | * Called when user space prepares to use an object with the CPU, either |
1121 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1122 | */ |
1123 | int | |
1124 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
1125 | struct drm_file *file_priv) | |
1126 | { | |
a09ba7fa | 1127 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
1128 | struct drm_i915_gem_set_domain *args = data; |
1129 | struct drm_gem_object *obj; | |
652c393a | 1130 | struct drm_i915_gem_object *obj_priv; |
2ef7eeaa EA |
1131 | uint32_t read_domains = args->read_domains; |
1132 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1133 | int ret; |
1134 | ||
1135 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1136 | return -ENODEV; | |
1137 | ||
2ef7eeaa | 1138 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1139 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1140 | return -EINVAL; |
1141 | ||
21d509e3 | 1142 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1143 | return -EINVAL; |
1144 | ||
1145 | /* Having something in the write domain implies it's in the read | |
1146 | * domain, and only that read domain. Enforce that in the request. | |
1147 | */ | |
1148 | if (write_domain != 0 && read_domains != write_domain) | |
1149 | return -EINVAL; | |
1150 | ||
76c1dec1 | 1151 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1152 | if (ret) |
76c1dec1 | 1153 | return ret; |
1d7cfea1 | 1154 | |
673a394b | 1155 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1d7cfea1 CW |
1156 | if (obj == NULL) { |
1157 | ret = -ENOENT; | |
1158 | goto unlock; | |
76c1dec1 | 1159 | } |
23010e43 | 1160 | obj_priv = to_intel_bo(obj); |
673a394b | 1161 | |
652c393a JB |
1162 | intel_mark_busy(dev, obj); |
1163 | ||
2ef7eeaa EA |
1164 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1165 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 | 1166 | |
a09ba7fa EA |
1167 | /* Update the LRU on the fence for the CPU access that's |
1168 | * about to occur. | |
1169 | */ | |
1170 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
007cc8ac DV |
1171 | struct drm_i915_fence_reg *reg = |
1172 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
1173 | list_move_tail(®->lru_list, | |
a09ba7fa EA |
1174 | &dev_priv->mm.fence_list); |
1175 | } | |
1176 | ||
02354392 EA |
1177 | /* Silently promote "you're not bound, there was nothing to do" |
1178 | * to success, since the client was just asking us to | |
1179 | * make sure everything was done. | |
1180 | */ | |
1181 | if (ret == -EINVAL) | |
1182 | ret = 0; | |
2ef7eeaa | 1183 | } else { |
e47c68e9 | 1184 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1185 | } |
1186 | ||
7d1c4804 CW |
1187 | /* Maintain LRU order of "inactive" objects */ |
1188 | if (ret == 0 && i915_gem_object_is_inactive(obj_priv)) | |
69dc4987 | 1189 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
7d1c4804 | 1190 | |
673a394b | 1191 | drm_gem_object_unreference(obj); |
1d7cfea1 | 1192 | unlock: |
673a394b EA |
1193 | mutex_unlock(&dev->struct_mutex); |
1194 | return ret; | |
1195 | } | |
1196 | ||
1197 | /** | |
1198 | * Called when user space has done writes to this buffer | |
1199 | */ | |
1200 | int | |
1201 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1202 | struct drm_file *file_priv) | |
1203 | { | |
1204 | struct drm_i915_gem_sw_finish *args = data; | |
1205 | struct drm_gem_object *obj; | |
673a394b EA |
1206 | int ret = 0; |
1207 | ||
1208 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1209 | return -ENODEV; | |
1210 | ||
76c1dec1 | 1211 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1212 | if (ret) |
76c1dec1 | 1213 | return ret; |
1d7cfea1 | 1214 | |
673a394b EA |
1215 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1216 | if (obj == NULL) { | |
1d7cfea1 CW |
1217 | ret = -ENOENT; |
1218 | goto unlock; | |
673a394b EA |
1219 | } |
1220 | ||
673a394b | 1221 | /* Pinned buffers may be scanout, so flush the cache */ |
3d2a812a | 1222 | if (to_intel_bo(obj)->pin_count) |
e47c68e9 EA |
1223 | i915_gem_object_flush_cpu_write_domain(obj); |
1224 | ||
673a394b | 1225 | drm_gem_object_unreference(obj); |
1d7cfea1 | 1226 | unlock: |
673a394b EA |
1227 | mutex_unlock(&dev->struct_mutex); |
1228 | return ret; | |
1229 | } | |
1230 | ||
1231 | /** | |
1232 | * Maps the contents of an object, returning the address it is mapped | |
1233 | * into. | |
1234 | * | |
1235 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1236 | * imply a ref on the object itself. | |
1237 | */ | |
1238 | int | |
1239 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1240 | struct drm_file *file_priv) | |
1241 | { | |
da761a6e | 1242 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
1243 | struct drm_i915_gem_mmap *args = data; |
1244 | struct drm_gem_object *obj; | |
1245 | loff_t offset; | |
1246 | unsigned long addr; | |
1247 | ||
1248 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1249 | return -ENODEV; | |
1250 | ||
1251 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1252 | if (obj == NULL) | |
bf79cb91 | 1253 | return -ENOENT; |
673a394b | 1254 | |
da761a6e CW |
1255 | if (obj->size > dev_priv->mm.gtt_mappable_end) { |
1256 | drm_gem_object_unreference_unlocked(obj); | |
1257 | return -E2BIG; | |
1258 | } | |
1259 | ||
673a394b EA |
1260 | offset = args->offset; |
1261 | ||
1262 | down_write(¤t->mm->mmap_sem); | |
1263 | addr = do_mmap(obj->filp, 0, args->size, | |
1264 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
1265 | args->offset); | |
1266 | up_write(¤t->mm->mmap_sem); | |
bc9025bd | 1267 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1268 | if (IS_ERR((void *)addr)) |
1269 | return addr; | |
1270 | ||
1271 | args->addr_ptr = (uint64_t) addr; | |
1272 | ||
1273 | return 0; | |
1274 | } | |
1275 | ||
de151cf6 JB |
1276 | /** |
1277 | * i915_gem_fault - fault a page into the GTT | |
1278 | * vma: VMA in question | |
1279 | * vmf: fault info | |
1280 | * | |
1281 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1282 | * from userspace. The fault handler takes care of binding the object to | |
1283 | * the GTT (if needed), allocating and programming a fence register (again, | |
1284 | * only if needed based on whether the old reg is still valid or the object | |
1285 | * is tiled) and inserting a new PTE into the faulting process. | |
1286 | * | |
1287 | * Note that the faulting process may involve evicting existing objects | |
1288 | * from the GTT and/or fence registers to make room. So performance may | |
1289 | * suffer if the GTT working set is large or there are few fence registers | |
1290 | * left. | |
1291 | */ | |
1292 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1293 | { | |
1294 | struct drm_gem_object *obj = vma->vm_private_data; | |
1295 | struct drm_device *dev = obj->dev; | |
7d1c4804 | 1296 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 1297 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
1298 | pgoff_t page_offset; |
1299 | unsigned long pfn; | |
1300 | int ret = 0; | |
0f973f27 | 1301 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1302 | |
1303 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1304 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1305 | PAGE_SHIFT; | |
1306 | ||
1307 | /* Now bind it into the GTT if needed */ | |
1308 | mutex_lock(&dev->struct_mutex); | |
fb7d516a | 1309 | BUG_ON(obj_priv->pin_count && !obj_priv->pin_mappable); |
16e809ac DV |
1310 | if (!i915_gem_object_cpu_accessible(obj_priv)) |
1311 | i915_gem_object_unbind(obj); | |
1312 | ||
de151cf6 | 1313 | if (!obj_priv->gtt_space) { |
920afa77 | 1314 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
c715089f CW |
1315 | if (ret) |
1316 | goto unlock; | |
07f4f3e8 | 1317 | |
07f4f3e8 | 1318 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
c715089f CW |
1319 | if (ret) |
1320 | goto unlock; | |
de151cf6 JB |
1321 | } |
1322 | ||
fb7d516a DV |
1323 | if (!obj_priv->fault_mappable) { |
1324 | obj_priv->fault_mappable = true; | |
1325 | i915_gem_info_update_mappable(dev_priv, obj, true); | |
1326 | } | |
1327 | ||
de151cf6 | 1328 | /* Need a new fence register? */ |
a09ba7fa | 1329 | if (obj_priv->tiling_mode != I915_TILING_NONE) { |
2cf34d7b | 1330 | ret = i915_gem_object_get_fence_reg(obj, true); |
c715089f CW |
1331 | if (ret) |
1332 | goto unlock; | |
d9ddcb96 | 1333 | } |
de151cf6 | 1334 | |
7d1c4804 | 1335 | if (i915_gem_object_is_inactive(obj_priv)) |
69dc4987 | 1336 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
7d1c4804 | 1337 | |
de151cf6 JB |
1338 | pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) + |
1339 | page_offset; | |
1340 | ||
1341 | /* Finally, remap it using the new GTT offset */ | |
1342 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1343 | unlock: |
de151cf6 JB |
1344 | mutex_unlock(&dev->struct_mutex); |
1345 | ||
1346 | switch (ret) { | |
c715089f CW |
1347 | case 0: |
1348 | case -ERESTARTSYS: | |
1349 | return VM_FAULT_NOPAGE; | |
de151cf6 JB |
1350 | case -ENOMEM: |
1351 | case -EAGAIN: | |
1352 | return VM_FAULT_OOM; | |
de151cf6 | 1353 | default: |
c715089f | 1354 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1355 | } |
1356 | } | |
1357 | ||
1358 | /** | |
1359 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object | |
1360 | * @obj: obj in question | |
1361 | * | |
1362 | * GEM memory mapping works by handing back to userspace a fake mmap offset | |
1363 | * it can use in a subsequent mmap(2) call. The DRM core code then looks | |
1364 | * up the object based on the offset and sets up the various memory mapping | |
1365 | * structures. | |
1366 | * | |
1367 | * This routine allocates and attaches a fake offset for @obj. | |
1368 | */ | |
1369 | static int | |
1370 | i915_gem_create_mmap_offset(struct drm_gem_object *obj) | |
1371 | { | |
1372 | struct drm_device *dev = obj->dev; | |
1373 | struct drm_gem_mm *mm = dev->mm_private; | |
de151cf6 | 1374 | struct drm_map_list *list; |
f77d390c | 1375 | struct drm_local_map *map; |
de151cf6 JB |
1376 | int ret = 0; |
1377 | ||
1378 | /* Set the object up for mmap'ing */ | |
1379 | list = &obj->map_list; | |
9a298b2a | 1380 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
de151cf6 JB |
1381 | if (!list->map) |
1382 | return -ENOMEM; | |
1383 | ||
1384 | map = list->map; | |
1385 | map->type = _DRM_GEM; | |
1386 | map->size = obj->size; | |
1387 | map->handle = obj; | |
1388 | ||
1389 | /* Get a DRM GEM mmap offset allocated... */ | |
1390 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, | |
1391 | obj->size / PAGE_SIZE, 0, 0); | |
1392 | if (!list->file_offset_node) { | |
1393 | DRM_ERROR("failed to allocate offset for bo %d\n", obj->name); | |
9e0ae534 | 1394 | ret = -ENOSPC; |
de151cf6 JB |
1395 | goto out_free_list; |
1396 | } | |
1397 | ||
1398 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, | |
1399 | obj->size / PAGE_SIZE, 0); | |
1400 | if (!list->file_offset_node) { | |
1401 | ret = -ENOMEM; | |
1402 | goto out_free_list; | |
1403 | } | |
1404 | ||
1405 | list->hash.key = list->file_offset_node->start; | |
9e0ae534 CW |
1406 | ret = drm_ht_insert_item(&mm->offset_hash, &list->hash); |
1407 | if (ret) { | |
de151cf6 JB |
1408 | DRM_ERROR("failed to add to map hash\n"); |
1409 | goto out_free_mm; | |
1410 | } | |
1411 | ||
de151cf6 JB |
1412 | return 0; |
1413 | ||
1414 | out_free_mm: | |
1415 | drm_mm_put_block(list->file_offset_node); | |
1416 | out_free_list: | |
9a298b2a | 1417 | kfree(list->map); |
39a01d1f | 1418 | list->map = NULL; |
de151cf6 JB |
1419 | |
1420 | return ret; | |
1421 | } | |
1422 | ||
901782b2 CW |
1423 | /** |
1424 | * i915_gem_release_mmap - remove physical page mappings | |
1425 | * @obj: obj in question | |
1426 | * | |
af901ca1 | 1427 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1428 | * relinquish ownership of the pages back to the system. |
1429 | * | |
1430 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1431 | * object through the GTT and then lose the fence register due to | |
1432 | * resource pressure. Similarly if the object has been moved out of the | |
1433 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1434 | * mapping will then trigger a page fault on the next user access, allowing | |
1435 | * fixup by i915_gem_fault(). | |
1436 | */ | |
d05ca301 | 1437 | void |
901782b2 CW |
1438 | i915_gem_release_mmap(struct drm_gem_object *obj) |
1439 | { | |
1440 | struct drm_device *dev = obj->dev; | |
fb7d516a | 1441 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 1442 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
901782b2 | 1443 | |
39a01d1f | 1444 | if (unlikely(obj->map_list.map && dev->dev_mapping)) |
901782b2 | 1445 | unmap_mapping_range(dev->dev_mapping, |
39a01d1f CW |
1446 | (loff_t)obj->map_list.hash.key<<PAGE_SHIFT, |
1447 | obj->size, 1); | |
fb7d516a DV |
1448 | |
1449 | if (obj_priv->fault_mappable) { | |
1450 | obj_priv->fault_mappable = false; | |
1451 | i915_gem_info_update_mappable(dev_priv, obj, false); | |
1452 | } | |
901782b2 CW |
1453 | } |
1454 | ||
ab00b3e5 JB |
1455 | static void |
1456 | i915_gem_free_mmap_offset(struct drm_gem_object *obj) | |
1457 | { | |
1458 | struct drm_device *dev = obj->dev; | |
ab00b3e5 | 1459 | struct drm_gem_mm *mm = dev->mm_private; |
39a01d1f | 1460 | struct drm_map_list *list = &obj->map_list; |
ab00b3e5 | 1461 | |
ab00b3e5 | 1462 | drm_ht_remove_item(&mm->offset_hash, &list->hash); |
39a01d1f CW |
1463 | drm_mm_put_block(list->file_offset_node); |
1464 | kfree(list->map); | |
1465 | list->map = NULL; | |
ab00b3e5 JB |
1466 | } |
1467 | ||
de151cf6 JB |
1468 | /** |
1469 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1470 | * @obj: object to check | |
1471 | * | |
1472 | * Return the required GTT alignment for an object, taking into account | |
1473 | * potential fence register mapping if needed. | |
1474 | */ | |
1475 | static uint32_t | |
1476 | i915_gem_get_gtt_alignment(struct drm_gem_object *obj) | |
1477 | { | |
1478 | struct drm_device *dev = obj->dev; | |
23010e43 | 1479 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
1480 | int start, i; |
1481 | ||
1482 | /* | |
1483 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1484 | * if a fence register is needed for the object. | |
1485 | */ | |
a6c45cf0 | 1486 | if (INTEL_INFO(dev)->gen >= 4 || obj_priv->tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1487 | return 4096; |
1488 | ||
1489 | /* | |
1490 | * Previous chips need to be aligned to the size of the smallest | |
1491 | * fence register that can contain the object. | |
1492 | */ | |
a6c45cf0 | 1493 | if (INTEL_INFO(dev)->gen == 3) |
de151cf6 JB |
1494 | start = 1024*1024; |
1495 | else | |
1496 | start = 512*1024; | |
1497 | ||
1498 | for (i = start; i < obj->size; i <<= 1) | |
1499 | ; | |
1500 | ||
1501 | return i; | |
1502 | } | |
1503 | ||
1504 | /** | |
1505 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1506 | * @dev: DRM device | |
1507 | * @data: GTT mapping ioctl data | |
1508 | * @file_priv: GEM object info | |
1509 | * | |
1510 | * Simply returns the fake offset to userspace so it can mmap it. | |
1511 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1512 | * up so we can get faults in the handler above. | |
1513 | * | |
1514 | * The fault handler will take care of binding the object into the GTT | |
1515 | * (since it may have been evicted to make room for something), allocating | |
1516 | * a fence register, and mapping the appropriate aperture address into | |
1517 | * userspace. | |
1518 | */ | |
1519 | int | |
1520 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1521 | struct drm_file *file_priv) | |
1522 | { | |
da761a6e | 1523 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 | 1524 | struct drm_i915_gem_mmap_gtt *args = data; |
de151cf6 JB |
1525 | struct drm_gem_object *obj; |
1526 | struct drm_i915_gem_object *obj_priv; | |
1527 | int ret; | |
1528 | ||
1529 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1530 | return -ENODEV; | |
1531 | ||
76c1dec1 | 1532 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1533 | if (ret) |
76c1dec1 | 1534 | return ret; |
de151cf6 | 1535 | |
1d7cfea1 CW |
1536 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1537 | if (obj == NULL) { | |
1538 | ret = -ENOENT; | |
1539 | goto unlock; | |
1540 | } | |
23010e43 | 1541 | obj_priv = to_intel_bo(obj); |
de151cf6 | 1542 | |
da761a6e CW |
1543 | if (obj->size > dev_priv->mm.gtt_mappable_end) { |
1544 | ret = -E2BIG; | |
1545 | goto unlock; | |
1546 | } | |
1547 | ||
ab18282d CW |
1548 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
1549 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); | |
1d7cfea1 CW |
1550 | ret = -EINVAL; |
1551 | goto out; | |
ab18282d CW |
1552 | } |
1553 | ||
39a01d1f | 1554 | if (!obj->map_list.map) { |
de151cf6 | 1555 | ret = i915_gem_create_mmap_offset(obj); |
1d7cfea1 CW |
1556 | if (ret) |
1557 | goto out; | |
de151cf6 JB |
1558 | } |
1559 | ||
39a01d1f | 1560 | args->offset = (u64)obj->map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1561 | |
1d7cfea1 | 1562 | out: |
de151cf6 | 1563 | drm_gem_object_unreference(obj); |
1d7cfea1 | 1564 | unlock: |
de151cf6 | 1565 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1566 | return ret; |
de151cf6 JB |
1567 | } |
1568 | ||
e5281ccd CW |
1569 | static int |
1570 | i915_gem_object_get_pages_gtt(struct drm_gem_object *obj, | |
1571 | gfp_t gfpmask) | |
1572 | { | |
1573 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
1574 | int page_count, i; | |
1575 | struct address_space *mapping; | |
1576 | struct inode *inode; | |
1577 | struct page *page; | |
1578 | ||
1579 | /* Get the list of pages out of our struct file. They'll be pinned | |
1580 | * at this point until we release them. | |
1581 | */ | |
1582 | page_count = obj->size / PAGE_SIZE; | |
1583 | BUG_ON(obj_priv->pages != NULL); | |
1584 | obj_priv->pages = drm_malloc_ab(page_count, sizeof(struct page *)); | |
1585 | if (obj_priv->pages == NULL) | |
1586 | return -ENOMEM; | |
1587 | ||
1588 | inode = obj->filp->f_path.dentry->d_inode; | |
1589 | mapping = inode->i_mapping; | |
1590 | for (i = 0; i < page_count; i++) { | |
1591 | page = read_cache_page_gfp(mapping, i, | |
1592 | GFP_HIGHUSER | | |
1593 | __GFP_COLD | | |
1594 | __GFP_RECLAIMABLE | | |
1595 | gfpmask); | |
1596 | if (IS_ERR(page)) | |
1597 | goto err_pages; | |
1598 | ||
1599 | obj_priv->pages[i] = page; | |
1600 | } | |
1601 | ||
1602 | if (obj_priv->tiling_mode != I915_TILING_NONE) | |
1603 | i915_gem_object_do_bit_17_swizzle(obj); | |
1604 | ||
1605 | return 0; | |
1606 | ||
1607 | err_pages: | |
1608 | while (i--) | |
1609 | page_cache_release(obj_priv->pages[i]); | |
1610 | ||
1611 | drm_free_large(obj_priv->pages); | |
1612 | obj_priv->pages = NULL; | |
1613 | return PTR_ERR(page); | |
1614 | } | |
1615 | ||
5cdf5881 | 1616 | static void |
e5281ccd | 1617 | i915_gem_object_put_pages_gtt(struct drm_gem_object *obj) |
673a394b | 1618 | { |
23010e43 | 1619 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
1620 | int page_count = obj->size / PAGE_SIZE; |
1621 | int i; | |
1622 | ||
bb6baf76 | 1623 | BUG_ON(obj_priv->madv == __I915_MADV_PURGED); |
673a394b | 1624 | |
280b713b EA |
1625 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
1626 | i915_gem_object_save_bit_17_swizzle(obj); | |
1627 | ||
3ef94daa | 1628 | if (obj_priv->madv == I915_MADV_DONTNEED) |
13a05fd9 | 1629 | obj_priv->dirty = 0; |
3ef94daa CW |
1630 | |
1631 | for (i = 0; i < page_count; i++) { | |
3ef94daa CW |
1632 | if (obj_priv->dirty) |
1633 | set_page_dirty(obj_priv->pages[i]); | |
1634 | ||
1635 | if (obj_priv->madv == I915_MADV_WILLNEED) | |
856fa198 | 1636 | mark_page_accessed(obj_priv->pages[i]); |
3ef94daa CW |
1637 | |
1638 | page_cache_release(obj_priv->pages[i]); | |
1639 | } | |
673a394b EA |
1640 | obj_priv->dirty = 0; |
1641 | ||
8e7d2b2c | 1642 | drm_free_large(obj_priv->pages); |
856fa198 | 1643 | obj_priv->pages = NULL; |
673a394b EA |
1644 | } |
1645 | ||
a56ba56c CW |
1646 | static uint32_t |
1647 | i915_gem_next_request_seqno(struct drm_device *dev, | |
1648 | struct intel_ring_buffer *ring) | |
1649 | { | |
1650 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1651 | ||
1652 | ring->outstanding_lazy_request = true; | |
1653 | return dev_priv->next_seqno; | |
1654 | } | |
1655 | ||
673a394b | 1656 | static void |
617dbe27 | 1657 | i915_gem_object_move_to_active(struct drm_gem_object *obj, |
852835f3 | 1658 | struct intel_ring_buffer *ring) |
673a394b EA |
1659 | { |
1660 | struct drm_device *dev = obj->dev; | |
69dc4987 | 1661 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 1662 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
a56ba56c | 1663 | uint32_t seqno = i915_gem_next_request_seqno(dev, ring); |
617dbe27 | 1664 | |
852835f3 ZN |
1665 | BUG_ON(ring == NULL); |
1666 | obj_priv->ring = ring; | |
673a394b EA |
1667 | |
1668 | /* Add a reference if we're newly entering the active list. */ | |
1669 | if (!obj_priv->active) { | |
1670 | drm_gem_object_reference(obj); | |
1671 | obj_priv->active = 1; | |
1672 | } | |
e35a41de | 1673 | |
673a394b | 1674 | /* Move from whatever list we were on to the tail of execution. */ |
69dc4987 CW |
1675 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.active_list); |
1676 | list_move_tail(&obj_priv->ring_list, &ring->active_list); | |
ce44b0ea | 1677 | obj_priv->last_rendering_seqno = seqno; |
673a394b EA |
1678 | } |
1679 | ||
ce44b0ea EA |
1680 | static void |
1681 | i915_gem_object_move_to_flushing(struct drm_gem_object *obj) | |
1682 | { | |
1683 | struct drm_device *dev = obj->dev; | |
1684 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1685 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ce44b0ea EA |
1686 | |
1687 | BUG_ON(!obj_priv->active); | |
69dc4987 CW |
1688 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.flushing_list); |
1689 | list_del_init(&obj_priv->ring_list); | |
ce44b0ea EA |
1690 | obj_priv->last_rendering_seqno = 0; |
1691 | } | |
673a394b | 1692 | |
963b4836 CW |
1693 | /* Immediately discard the backing storage */ |
1694 | static void | |
1695 | i915_gem_object_truncate(struct drm_gem_object *obj) | |
1696 | { | |
23010e43 | 1697 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
bb6baf76 | 1698 | struct inode *inode; |
963b4836 | 1699 | |
ae9fed6b CW |
1700 | /* Our goal here is to return as much of the memory as |
1701 | * is possible back to the system as we are called from OOM. | |
1702 | * To do this we must instruct the shmfs to drop all of its | |
1703 | * backing pages, *now*. Here we mirror the actions taken | |
1704 | * when by shmem_delete_inode() to release the backing store. | |
1705 | */ | |
bb6baf76 | 1706 | inode = obj->filp->f_path.dentry->d_inode; |
ae9fed6b CW |
1707 | truncate_inode_pages(inode->i_mapping, 0); |
1708 | if (inode->i_op->truncate_range) | |
1709 | inode->i_op->truncate_range(inode, 0, (loff_t)-1); | |
bb6baf76 CW |
1710 | |
1711 | obj_priv->madv = __I915_MADV_PURGED; | |
963b4836 CW |
1712 | } |
1713 | ||
1714 | static inline int | |
1715 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv) | |
1716 | { | |
1717 | return obj_priv->madv == I915_MADV_DONTNEED; | |
1718 | } | |
1719 | ||
673a394b EA |
1720 | static void |
1721 | i915_gem_object_move_to_inactive(struct drm_gem_object *obj) | |
1722 | { | |
1723 | struct drm_device *dev = obj->dev; | |
1724 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1725 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 1726 | |
673a394b | 1727 | if (obj_priv->pin_count != 0) |
69dc4987 | 1728 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.pinned_list); |
673a394b | 1729 | else |
69dc4987 CW |
1730 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
1731 | list_del_init(&obj_priv->ring_list); | |
673a394b | 1732 | |
99fcb766 DV |
1733 | BUG_ON(!list_empty(&obj_priv->gpu_write_list)); |
1734 | ||
ce44b0ea | 1735 | obj_priv->last_rendering_seqno = 0; |
852835f3 | 1736 | obj_priv->ring = NULL; |
673a394b EA |
1737 | if (obj_priv->active) { |
1738 | obj_priv->active = 0; | |
1739 | drm_gem_object_unreference(obj); | |
1740 | } | |
23bc5982 | 1741 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
1742 | } |
1743 | ||
63560396 DV |
1744 | static void |
1745 | i915_gem_process_flushing_list(struct drm_device *dev, | |
8a1a49f9 | 1746 | uint32_t flush_domains, |
852835f3 | 1747 | struct intel_ring_buffer *ring) |
63560396 DV |
1748 | { |
1749 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1750 | struct drm_i915_gem_object *obj_priv, *next; | |
1751 | ||
1752 | list_for_each_entry_safe(obj_priv, next, | |
64193406 | 1753 | &ring->gpu_write_list, |
63560396 | 1754 | gpu_write_list) { |
a8089e84 | 1755 | struct drm_gem_object *obj = &obj_priv->base; |
63560396 | 1756 | |
64193406 | 1757 | if (obj->write_domain & flush_domains) { |
63560396 DV |
1758 | uint32_t old_write_domain = obj->write_domain; |
1759 | ||
1760 | obj->write_domain = 0; | |
1761 | list_del_init(&obj_priv->gpu_write_list); | |
617dbe27 | 1762 | i915_gem_object_move_to_active(obj, ring); |
63560396 DV |
1763 | |
1764 | /* update the fence lru list */ | |
007cc8ac DV |
1765 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
1766 | struct drm_i915_fence_reg *reg = | |
1767 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
1768 | list_move_tail(®->lru_list, | |
63560396 | 1769 | &dev_priv->mm.fence_list); |
007cc8ac | 1770 | } |
63560396 DV |
1771 | |
1772 | trace_i915_gem_object_change_domain(obj, | |
1773 | obj->read_domains, | |
1774 | old_write_domain); | |
1775 | } | |
1776 | } | |
1777 | } | |
8187a2b7 | 1778 | |
3cce469c | 1779 | int |
8a1a49f9 | 1780 | i915_add_request(struct drm_device *dev, |
f787a5f5 | 1781 | struct drm_file *file, |
8dc5d147 | 1782 | struct drm_i915_gem_request *request, |
8a1a49f9 | 1783 | struct intel_ring_buffer *ring) |
673a394b EA |
1784 | { |
1785 | drm_i915_private_t *dev_priv = dev->dev_private; | |
f787a5f5 | 1786 | struct drm_i915_file_private *file_priv = NULL; |
673a394b EA |
1787 | uint32_t seqno; |
1788 | int was_empty; | |
3cce469c CW |
1789 | int ret; |
1790 | ||
1791 | BUG_ON(request == NULL); | |
673a394b | 1792 | |
f787a5f5 CW |
1793 | if (file != NULL) |
1794 | file_priv = file->driver_priv; | |
b962442e | 1795 | |
3cce469c CW |
1796 | ret = ring->add_request(ring, &seqno); |
1797 | if (ret) | |
1798 | return ret; | |
673a394b | 1799 | |
a56ba56c | 1800 | ring->outstanding_lazy_request = false; |
673a394b EA |
1801 | |
1802 | request->seqno = seqno; | |
852835f3 | 1803 | request->ring = ring; |
673a394b | 1804 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1805 | was_empty = list_empty(&ring->request_list); |
1806 | list_add_tail(&request->list, &ring->request_list); | |
1807 | ||
f787a5f5 | 1808 | if (file_priv) { |
1c25595f | 1809 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 1810 | request->file_priv = file_priv; |
b962442e | 1811 | list_add_tail(&request->client_list, |
f787a5f5 | 1812 | &file_priv->mm.request_list); |
1c25595f | 1813 | spin_unlock(&file_priv->mm.lock); |
b962442e | 1814 | } |
673a394b | 1815 | |
f65d9421 | 1816 | if (!dev_priv->mm.suspended) { |
b3b079db CW |
1817 | mod_timer(&dev_priv->hangcheck_timer, |
1818 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
f65d9421 | 1819 | if (was_empty) |
b3b079db CW |
1820 | queue_delayed_work(dev_priv->wq, |
1821 | &dev_priv->mm.retire_work, HZ); | |
f65d9421 | 1822 | } |
3cce469c | 1823 | return 0; |
673a394b EA |
1824 | } |
1825 | ||
1826 | /** | |
1827 | * Command execution barrier | |
1828 | * | |
1829 | * Ensures that all commands in the ring are finished | |
1830 | * before signalling the CPU | |
1831 | */ | |
8a1a49f9 | 1832 | static void |
852835f3 | 1833 | i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring) |
673a394b | 1834 | { |
673a394b | 1835 | uint32_t flush_domains = 0; |
673a394b EA |
1836 | |
1837 | /* The sampler always gets flushed on i965 (sigh) */ | |
a6c45cf0 | 1838 | if (INTEL_INFO(dev)->gen >= 4) |
673a394b | 1839 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; |
852835f3 | 1840 | |
78501eac | 1841 | ring->flush(ring, I915_GEM_DOMAIN_COMMAND, flush_domains); |
673a394b EA |
1842 | } |
1843 | ||
f787a5f5 CW |
1844 | static inline void |
1845 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 1846 | { |
1c25595f | 1847 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 1848 | |
1c25595f CW |
1849 | if (!file_priv) |
1850 | return; | |
1c5d22f7 | 1851 | |
1c25595f CW |
1852 | spin_lock(&file_priv->mm.lock); |
1853 | list_del(&request->client_list); | |
1854 | request->file_priv = NULL; | |
1855 | spin_unlock(&file_priv->mm.lock); | |
673a394b | 1856 | } |
673a394b | 1857 | |
dfaae392 CW |
1858 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
1859 | struct intel_ring_buffer *ring) | |
9375e446 | 1860 | { |
dfaae392 CW |
1861 | while (!list_empty(&ring->request_list)) { |
1862 | struct drm_i915_gem_request *request; | |
673a394b | 1863 | |
dfaae392 CW |
1864 | request = list_first_entry(&ring->request_list, |
1865 | struct drm_i915_gem_request, | |
1866 | list); | |
de151cf6 | 1867 | |
dfaae392 | 1868 | list_del(&request->list); |
f787a5f5 | 1869 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
1870 | kfree(request); |
1871 | } | |
673a394b | 1872 | |
dfaae392 | 1873 | while (!list_empty(&ring->active_list)) { |
9375e446 CW |
1874 | struct drm_i915_gem_object *obj_priv; |
1875 | ||
dfaae392 | 1876 | obj_priv = list_first_entry(&ring->active_list, |
9375e446 | 1877 | struct drm_i915_gem_object, |
69dc4987 | 1878 | ring_list); |
9375e446 CW |
1879 | |
1880 | obj_priv->base.write_domain = 0; | |
dfaae392 | 1881 | list_del_init(&obj_priv->gpu_write_list); |
9375e446 | 1882 | i915_gem_object_move_to_inactive(&obj_priv->base); |
673a394b EA |
1883 | } |
1884 | } | |
1885 | ||
069efc1d | 1886 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 1887 | { |
77f01230 CW |
1888 | struct drm_i915_private *dev_priv = dev->dev_private; |
1889 | struct drm_i915_gem_object *obj_priv; | |
069efc1d | 1890 | int i; |
673a394b | 1891 | |
dfaae392 | 1892 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->render_ring); |
87acb0a5 | 1893 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->bsd_ring); |
549f7365 | 1894 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->blt_ring); |
dfaae392 CW |
1895 | |
1896 | /* Remove anything from the flushing lists. The GPU cache is likely | |
1897 | * to be lost on reset along with the data, so simply move the | |
1898 | * lost bo to the inactive list. | |
1899 | */ | |
1900 | while (!list_empty(&dev_priv->mm.flushing_list)) { | |
1901 | obj_priv = list_first_entry(&dev_priv->mm.flushing_list, | |
1902 | struct drm_i915_gem_object, | |
69dc4987 | 1903 | mm_list); |
dfaae392 CW |
1904 | |
1905 | obj_priv->base.write_domain = 0; | |
1906 | list_del_init(&obj_priv->gpu_write_list); | |
1907 | i915_gem_object_move_to_inactive(&obj_priv->base); | |
1908 | } | |
1909 | ||
1910 | /* Move everything out of the GPU domains to ensure we do any | |
1911 | * necessary invalidation upon reuse. | |
1912 | */ | |
77f01230 CW |
1913 | list_for_each_entry(obj_priv, |
1914 | &dev_priv->mm.inactive_list, | |
69dc4987 | 1915 | mm_list) |
77f01230 CW |
1916 | { |
1917 | obj_priv->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
1918 | } | |
069efc1d CW |
1919 | |
1920 | /* The fence registers are invalidated so clear them out */ | |
1921 | for (i = 0; i < 16; i++) { | |
1922 | struct drm_i915_fence_reg *reg; | |
1923 | ||
1924 | reg = &dev_priv->fence_regs[i]; | |
1925 | if (!reg->obj) | |
1926 | continue; | |
1927 | ||
1928 | i915_gem_clear_fence_reg(reg->obj); | |
1929 | } | |
673a394b EA |
1930 | } |
1931 | ||
1932 | /** | |
1933 | * This function clears the request list as sequence numbers are passed. | |
1934 | */ | |
b09a1fec CW |
1935 | static void |
1936 | i915_gem_retire_requests_ring(struct drm_device *dev, | |
1937 | struct intel_ring_buffer *ring) | |
673a394b EA |
1938 | { |
1939 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1940 | uint32_t seqno; | |
1941 | ||
b84d5f0c CW |
1942 | if (!ring->status_page.page_addr || |
1943 | list_empty(&ring->request_list)) | |
6c0594a3 KW |
1944 | return; |
1945 | ||
23bc5982 | 1946 | WARN_ON(i915_verify_lists(dev)); |
673a394b | 1947 | |
78501eac | 1948 | seqno = ring->get_seqno(ring); |
852835f3 | 1949 | while (!list_empty(&ring->request_list)) { |
673a394b | 1950 | struct drm_i915_gem_request *request; |
673a394b | 1951 | |
852835f3 | 1952 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1953 | struct drm_i915_gem_request, |
1954 | list); | |
673a394b | 1955 | |
dfaae392 | 1956 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
1957 | break; |
1958 | ||
1959 | trace_i915_gem_request_retire(dev, request->seqno); | |
1960 | ||
1961 | list_del(&request->list); | |
f787a5f5 | 1962 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
1963 | kfree(request); |
1964 | } | |
673a394b | 1965 | |
b84d5f0c CW |
1966 | /* Move any buffers on the active list that are no longer referenced |
1967 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1968 | */ | |
1969 | while (!list_empty(&ring->active_list)) { | |
1970 | struct drm_gem_object *obj; | |
1971 | struct drm_i915_gem_object *obj_priv; | |
1972 | ||
1973 | obj_priv = list_first_entry(&ring->active_list, | |
1974 | struct drm_i915_gem_object, | |
69dc4987 | 1975 | ring_list); |
673a394b | 1976 | |
dfaae392 | 1977 | if (!i915_seqno_passed(seqno, obj_priv->last_rendering_seqno)) |
673a394b | 1978 | break; |
b84d5f0c CW |
1979 | |
1980 | obj = &obj_priv->base; | |
b84d5f0c CW |
1981 | if (obj->write_domain != 0) |
1982 | i915_gem_object_move_to_flushing(obj); | |
1983 | else | |
1984 | i915_gem_object_move_to_inactive(obj); | |
673a394b | 1985 | } |
9d34e5db CW |
1986 | |
1987 | if (unlikely (dev_priv->trace_irq_seqno && | |
1988 | i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) { | |
78501eac | 1989 | ring->user_irq_put(ring); |
9d34e5db CW |
1990 | dev_priv->trace_irq_seqno = 0; |
1991 | } | |
23bc5982 CW |
1992 | |
1993 | WARN_ON(i915_verify_lists(dev)); | |
673a394b EA |
1994 | } |
1995 | ||
b09a1fec CW |
1996 | void |
1997 | i915_gem_retire_requests(struct drm_device *dev) | |
1998 | { | |
1999 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2000 | ||
be72615b CW |
2001 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
2002 | struct drm_i915_gem_object *obj_priv, *tmp; | |
2003 | ||
2004 | /* We must be careful that during unbind() we do not | |
2005 | * accidentally infinitely recurse into retire requests. | |
2006 | * Currently: | |
2007 | * retire -> free -> unbind -> wait -> retire_ring | |
2008 | */ | |
2009 | list_for_each_entry_safe(obj_priv, tmp, | |
2010 | &dev_priv->mm.deferred_free_list, | |
69dc4987 | 2011 | mm_list) |
be72615b CW |
2012 | i915_gem_free_object_tail(&obj_priv->base); |
2013 | } | |
2014 | ||
b09a1fec | 2015 | i915_gem_retire_requests_ring(dev, &dev_priv->render_ring); |
87acb0a5 | 2016 | i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring); |
549f7365 | 2017 | i915_gem_retire_requests_ring(dev, &dev_priv->blt_ring); |
b09a1fec CW |
2018 | } |
2019 | ||
75ef9da2 | 2020 | static void |
673a394b EA |
2021 | i915_gem_retire_work_handler(struct work_struct *work) |
2022 | { | |
2023 | drm_i915_private_t *dev_priv; | |
2024 | struct drm_device *dev; | |
2025 | ||
2026 | dev_priv = container_of(work, drm_i915_private_t, | |
2027 | mm.retire_work.work); | |
2028 | dev = dev_priv->dev; | |
2029 | ||
891b48cf CW |
2030 | /* Come back later if the device is busy... */ |
2031 | if (!mutex_trylock(&dev->struct_mutex)) { | |
2032 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
2033 | return; | |
2034 | } | |
2035 | ||
b09a1fec | 2036 | i915_gem_retire_requests(dev); |
d1b851fc | 2037 | |
6dbe2772 | 2038 | if (!dev_priv->mm.suspended && |
d1b851fc | 2039 | (!list_empty(&dev_priv->render_ring.request_list) || |
549f7365 CW |
2040 | !list_empty(&dev_priv->bsd_ring.request_list) || |
2041 | !list_empty(&dev_priv->blt_ring.request_list))) | |
9c9fe1f8 | 2042 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
673a394b EA |
2043 | mutex_unlock(&dev->struct_mutex); |
2044 | } | |
2045 | ||
5a5a0c64 | 2046 | int |
852835f3 | 2047 | i915_do_wait_request(struct drm_device *dev, uint32_t seqno, |
8a1a49f9 | 2048 | bool interruptible, struct intel_ring_buffer *ring) |
673a394b EA |
2049 | { |
2050 | drm_i915_private_t *dev_priv = dev->dev_private; | |
802c7eb6 | 2051 | u32 ier; |
673a394b EA |
2052 | int ret = 0; |
2053 | ||
2054 | BUG_ON(seqno == 0); | |
2055 | ||
ba1234d1 | 2056 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 CW |
2057 | return -EAGAIN; |
2058 | ||
a56ba56c | 2059 | if (ring->outstanding_lazy_request) { |
3cce469c CW |
2060 | struct drm_i915_gem_request *request; |
2061 | ||
2062 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
2063 | if (request == NULL) | |
e35a41de | 2064 | return -ENOMEM; |
3cce469c CW |
2065 | |
2066 | ret = i915_add_request(dev, NULL, request, ring); | |
2067 | if (ret) { | |
2068 | kfree(request); | |
2069 | return ret; | |
2070 | } | |
2071 | ||
2072 | seqno = request->seqno; | |
e35a41de | 2073 | } |
a56ba56c | 2074 | BUG_ON(seqno == dev_priv->next_seqno); |
ffed1d09 | 2075 | |
78501eac | 2076 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
bad720ff | 2077 | if (HAS_PCH_SPLIT(dev)) |
036a4a7d ZW |
2078 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
2079 | else | |
2080 | ier = I915_READ(IER); | |
802c7eb6 JB |
2081 | if (!ier) { |
2082 | DRM_ERROR("something (likely vbetool) disabled " | |
2083 | "interrupts, re-enabling\n"); | |
2084 | i915_driver_irq_preinstall(dev); | |
2085 | i915_driver_irq_postinstall(dev); | |
2086 | } | |
2087 | ||
1c5d22f7 CW |
2088 | trace_i915_gem_request_wait_begin(dev, seqno); |
2089 | ||
b2223497 | 2090 | ring->waiting_seqno = seqno; |
78501eac | 2091 | ring->user_irq_get(ring); |
48764bf4 | 2092 | if (interruptible) |
852835f3 | 2093 | ret = wait_event_interruptible(ring->irq_queue, |
78501eac | 2094 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
852835f3 | 2095 | || atomic_read(&dev_priv->mm.wedged)); |
48764bf4 | 2096 | else |
852835f3 | 2097 | wait_event(ring->irq_queue, |
78501eac | 2098 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
852835f3 | 2099 | || atomic_read(&dev_priv->mm.wedged)); |
48764bf4 | 2100 | |
78501eac | 2101 | ring->user_irq_put(ring); |
b2223497 | 2102 | ring->waiting_seqno = 0; |
1c5d22f7 CW |
2103 | |
2104 | trace_i915_gem_request_wait_end(dev, seqno); | |
673a394b | 2105 | } |
ba1234d1 | 2106 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 | 2107 | ret = -EAGAIN; |
673a394b EA |
2108 | |
2109 | if (ret && ret != -ERESTARTSYS) | |
8bff917c | 2110 | DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n", |
78501eac | 2111 | __func__, ret, seqno, ring->get_seqno(ring), |
8bff917c | 2112 | dev_priv->next_seqno); |
673a394b EA |
2113 | |
2114 | /* Directly dispatch request retiring. While we have the work queue | |
2115 | * to handle this, the waiter on a request often wants an associated | |
2116 | * buffer to have made it to the inactive list, and we would need | |
2117 | * a separate wait queue to handle that. | |
2118 | */ | |
2119 | if (ret == 0) | |
b09a1fec | 2120 | i915_gem_retire_requests_ring(dev, ring); |
673a394b EA |
2121 | |
2122 | return ret; | |
2123 | } | |
2124 | ||
48764bf4 DV |
2125 | /** |
2126 | * Waits for a sequence number to be signaled, and cleans up the | |
2127 | * request and object lists appropriately for that event. | |
2128 | */ | |
2129 | static int | |
852835f3 | 2130 | i915_wait_request(struct drm_device *dev, uint32_t seqno, |
a56ba56c | 2131 | struct intel_ring_buffer *ring) |
48764bf4 | 2132 | { |
852835f3 | 2133 | return i915_do_wait_request(dev, seqno, 1, ring); |
48764bf4 DV |
2134 | } |
2135 | ||
20f0cd55 | 2136 | static void |
9220434a | 2137 | i915_gem_flush_ring(struct drm_device *dev, |
c78ec30b | 2138 | struct drm_file *file_priv, |
9220434a CW |
2139 | struct intel_ring_buffer *ring, |
2140 | uint32_t invalidate_domains, | |
2141 | uint32_t flush_domains) | |
2142 | { | |
78501eac | 2143 | ring->flush(ring, invalidate_domains, flush_domains); |
9220434a CW |
2144 | i915_gem_process_flushing_list(dev, flush_domains, ring); |
2145 | } | |
2146 | ||
8187a2b7 ZN |
2147 | static void |
2148 | i915_gem_flush(struct drm_device *dev, | |
c78ec30b | 2149 | struct drm_file *file_priv, |
8187a2b7 | 2150 | uint32_t invalidate_domains, |
9220434a CW |
2151 | uint32_t flush_domains, |
2152 | uint32_t flush_rings) | |
8187a2b7 ZN |
2153 | { |
2154 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8bff917c | 2155 | |
8187a2b7 ZN |
2156 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
2157 | drm_agp_chipset_flush(dev); | |
8bff917c | 2158 | |
9220434a CW |
2159 | if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) { |
2160 | if (flush_rings & RING_RENDER) | |
c78ec30b | 2161 | i915_gem_flush_ring(dev, file_priv, |
9220434a CW |
2162 | &dev_priv->render_ring, |
2163 | invalidate_domains, flush_domains); | |
2164 | if (flush_rings & RING_BSD) | |
c78ec30b | 2165 | i915_gem_flush_ring(dev, file_priv, |
9220434a CW |
2166 | &dev_priv->bsd_ring, |
2167 | invalidate_domains, flush_domains); | |
549f7365 CW |
2168 | if (flush_rings & RING_BLT) |
2169 | i915_gem_flush_ring(dev, file_priv, | |
2170 | &dev_priv->blt_ring, | |
2171 | invalidate_domains, flush_domains); | |
9220434a | 2172 | } |
8187a2b7 ZN |
2173 | } |
2174 | ||
673a394b EA |
2175 | /** |
2176 | * Ensures that all rendering to the object has completed and the object is | |
2177 | * safe to unbind from the GTT or access from the CPU. | |
2178 | */ | |
2179 | static int | |
2cf34d7b CW |
2180 | i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
2181 | bool interruptible) | |
673a394b EA |
2182 | { |
2183 | struct drm_device *dev = obj->dev; | |
23010e43 | 2184 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2185 | int ret; |
2186 | ||
e47c68e9 EA |
2187 | /* This function only exists to support waiting for existing rendering, |
2188 | * not for emitting required flushes. | |
673a394b | 2189 | */ |
e47c68e9 | 2190 | BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
2191 | |
2192 | /* If there is rendering queued on the buffer being evicted, wait for | |
2193 | * it. | |
2194 | */ | |
2195 | if (obj_priv->active) { | |
2cf34d7b CW |
2196 | ret = i915_do_wait_request(dev, |
2197 | obj_priv->last_rendering_seqno, | |
2198 | interruptible, | |
2199 | obj_priv->ring); | |
2200 | if (ret) | |
673a394b EA |
2201 | return ret; |
2202 | } | |
2203 | ||
2204 | return 0; | |
2205 | } | |
2206 | ||
2207 | /** | |
2208 | * Unbinds an object from the GTT aperture. | |
2209 | */ | |
0f973f27 | 2210 | int |
673a394b EA |
2211 | i915_gem_object_unbind(struct drm_gem_object *obj) |
2212 | { | |
2213 | struct drm_device *dev = obj->dev; | |
73aa808f | 2214 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2215 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2216 | int ret = 0; |
2217 | ||
673a394b EA |
2218 | if (obj_priv->gtt_space == NULL) |
2219 | return 0; | |
2220 | ||
2221 | if (obj_priv->pin_count != 0) { | |
2222 | DRM_ERROR("Attempting to unbind pinned buffer\n"); | |
2223 | return -EINVAL; | |
2224 | } | |
2225 | ||
5323fd04 EA |
2226 | /* blow away mappings if mapped through GTT */ |
2227 | i915_gem_release_mmap(obj); | |
2228 | ||
673a394b EA |
2229 | /* Move the object to the CPU domain to ensure that |
2230 | * any possible CPU writes while it's not in the GTT | |
2231 | * are flushed when we go to remap it. This will | |
2232 | * also ensure that all pending GPU writes are finished | |
2233 | * before we unbind. | |
2234 | */ | |
e47c68e9 | 2235 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
8dc1775d | 2236 | if (ret == -ERESTARTSYS) |
673a394b | 2237 | return ret; |
8dc1775d CW |
2238 | /* Continue on if we fail due to EIO, the GPU is hung so we |
2239 | * should be safe and we need to cleanup or else we might | |
2240 | * cause memory corruption through use-after-free. | |
2241 | */ | |
812ed492 CW |
2242 | if (ret) { |
2243 | i915_gem_clflush_object(obj); | |
2244 | obj->read_domains = obj->write_domain = I915_GEM_DOMAIN_CPU; | |
2245 | } | |
673a394b | 2246 | |
96b47b65 DV |
2247 | /* release the fence reg _after_ flushing */ |
2248 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) | |
2249 | i915_gem_clear_fence_reg(obj); | |
2250 | ||
73aa808f CW |
2251 | drm_unbind_agp(obj_priv->agp_mem); |
2252 | drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE); | |
673a394b | 2253 | |
e5281ccd | 2254 | i915_gem_object_put_pages_gtt(obj); |
673a394b | 2255 | |
fb7d516a | 2256 | i915_gem_info_remove_gtt(dev_priv, obj); |
69dc4987 | 2257 | list_del_init(&obj_priv->mm_list); |
673a394b | 2258 | |
73aa808f CW |
2259 | drm_mm_put_block(obj_priv->gtt_space); |
2260 | obj_priv->gtt_space = NULL; | |
9af90d19 | 2261 | obj_priv->gtt_offset = 0; |
673a394b | 2262 | |
963b4836 CW |
2263 | if (i915_gem_object_is_purgeable(obj_priv)) |
2264 | i915_gem_object_truncate(obj); | |
2265 | ||
1c5d22f7 CW |
2266 | trace_i915_gem_object_unbind(obj); |
2267 | ||
8dc1775d | 2268 | return ret; |
673a394b EA |
2269 | } |
2270 | ||
a56ba56c CW |
2271 | static int i915_ring_idle(struct drm_device *dev, |
2272 | struct intel_ring_buffer *ring) | |
2273 | { | |
64193406 CW |
2274 | if (list_empty(&ring->gpu_write_list)) |
2275 | return 0; | |
2276 | ||
a56ba56c CW |
2277 | i915_gem_flush_ring(dev, NULL, ring, |
2278 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
2279 | return i915_wait_request(dev, | |
2280 | i915_gem_next_request_seqno(dev, ring), | |
2281 | ring); | |
2282 | } | |
2283 | ||
b47eb4a2 | 2284 | int |
4df2faf4 DV |
2285 | i915_gpu_idle(struct drm_device *dev) |
2286 | { | |
2287 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2288 | bool lists_empty; | |
852835f3 | 2289 | int ret; |
4df2faf4 | 2290 | |
d1b851fc ZN |
2291 | lists_empty = (list_empty(&dev_priv->mm.flushing_list) && |
2292 | list_empty(&dev_priv->render_ring.active_list) && | |
549f7365 CW |
2293 | list_empty(&dev_priv->bsd_ring.active_list) && |
2294 | list_empty(&dev_priv->blt_ring.active_list)); | |
4df2faf4 DV |
2295 | if (lists_empty) |
2296 | return 0; | |
2297 | ||
2298 | /* Flush everything onto the inactive list. */ | |
a56ba56c | 2299 | ret = i915_ring_idle(dev, &dev_priv->render_ring); |
8a1a49f9 DV |
2300 | if (ret) |
2301 | return ret; | |
d1b851fc | 2302 | |
87acb0a5 CW |
2303 | ret = i915_ring_idle(dev, &dev_priv->bsd_ring); |
2304 | if (ret) | |
2305 | return ret; | |
d1b851fc | 2306 | |
549f7365 CW |
2307 | ret = i915_ring_idle(dev, &dev_priv->blt_ring); |
2308 | if (ret) | |
2309 | return ret; | |
4df2faf4 | 2310 | |
8a1a49f9 | 2311 | return 0; |
4df2faf4 DV |
2312 | } |
2313 | ||
4e901fdc EA |
2314 | static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg) |
2315 | { | |
2316 | struct drm_gem_object *obj = reg->obj; | |
2317 | struct drm_device *dev = obj->dev; | |
2318 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2319 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
4e901fdc EA |
2320 | int regnum = obj_priv->fence_reg; |
2321 | uint64_t val; | |
2322 | ||
2323 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & | |
2324 | 0xfffff000) << 32; | |
2325 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2326 | val |= (uint64_t)((obj_priv->stride / 128) - 1) << | |
2327 | SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2328 | ||
2329 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2330 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2331 | val |= I965_FENCE_REG_VALID; | |
2332 | ||
2333 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val); | |
2334 | } | |
2335 | ||
de151cf6 JB |
2336 | static void i965_write_fence_reg(struct drm_i915_fence_reg *reg) |
2337 | { | |
2338 | struct drm_gem_object *obj = reg->obj; | |
2339 | struct drm_device *dev = obj->dev; | |
2340 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2341 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
2342 | int regnum = obj_priv->fence_reg; |
2343 | uint64_t val; | |
2344 | ||
2345 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & | |
2346 | 0xfffff000) << 32; | |
2347 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2348 | val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2349 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2350 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2351 | val |= I965_FENCE_REG_VALID; | |
2352 | ||
2353 | I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val); | |
2354 | } | |
2355 | ||
2356 | static void i915_write_fence_reg(struct drm_i915_fence_reg *reg) | |
2357 | { | |
2358 | struct drm_gem_object *obj = reg->obj; | |
2359 | struct drm_device *dev = obj->dev; | |
2360 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2361 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 2362 | int regnum = obj_priv->fence_reg; |
0f973f27 | 2363 | int tile_width; |
dc529a4f | 2364 | uint32_t fence_reg, val; |
de151cf6 JB |
2365 | uint32_t pitch_val; |
2366 | ||
2367 | if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) || | |
2368 | (obj_priv->gtt_offset & (obj->size - 1))) { | |
f06da264 | 2369 | WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n", |
0f973f27 | 2370 | __func__, obj_priv->gtt_offset, obj->size); |
de151cf6 JB |
2371 | return; |
2372 | } | |
2373 | ||
0f973f27 JB |
2374 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2375 | HAS_128_BYTE_Y_TILING(dev)) | |
2376 | tile_width = 128; | |
de151cf6 | 2377 | else |
0f973f27 JB |
2378 | tile_width = 512; |
2379 | ||
2380 | /* Note: pitch better be a power of two tile widths */ | |
2381 | pitch_val = obj_priv->stride / tile_width; | |
2382 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2383 | |
c36a2a6d DV |
2384 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2385 | HAS_128_BYTE_Y_TILING(dev)) | |
2386 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2387 | else | |
2388 | WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL); | |
2389 | ||
de151cf6 JB |
2390 | val = obj_priv->gtt_offset; |
2391 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2392 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2393 | val |= I915_FENCE_SIZE_BITS(obj->size); | |
2394 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2395 | val |= I830_FENCE_REG_VALID; | |
2396 | ||
dc529a4f EA |
2397 | if (regnum < 8) |
2398 | fence_reg = FENCE_REG_830_0 + (regnum * 4); | |
2399 | else | |
2400 | fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4); | |
2401 | I915_WRITE(fence_reg, val); | |
de151cf6 JB |
2402 | } |
2403 | ||
2404 | static void i830_write_fence_reg(struct drm_i915_fence_reg *reg) | |
2405 | { | |
2406 | struct drm_gem_object *obj = reg->obj; | |
2407 | struct drm_device *dev = obj->dev; | |
2408 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2409 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
2410 | int regnum = obj_priv->fence_reg; |
2411 | uint32_t val; | |
2412 | uint32_t pitch_val; | |
8d7773a3 | 2413 | uint32_t fence_size_bits; |
de151cf6 | 2414 | |
8d7773a3 | 2415 | if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) || |
de151cf6 | 2416 | (obj_priv->gtt_offset & (obj->size - 1))) { |
8d7773a3 | 2417 | WARN(1, "%s: object 0x%08x not 512K or size aligned\n", |
0f973f27 | 2418 | __func__, obj_priv->gtt_offset); |
de151cf6 JB |
2419 | return; |
2420 | } | |
2421 | ||
e76a16de EA |
2422 | pitch_val = obj_priv->stride / 128; |
2423 | pitch_val = ffs(pitch_val) - 1; | |
2424 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2425 | ||
de151cf6 JB |
2426 | val = obj_priv->gtt_offset; |
2427 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2428 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
8d7773a3 DV |
2429 | fence_size_bits = I830_FENCE_SIZE_BITS(obj->size); |
2430 | WARN_ON(fence_size_bits & ~0x00000f00); | |
2431 | val |= fence_size_bits; | |
de151cf6 JB |
2432 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2433 | val |= I830_FENCE_REG_VALID; | |
2434 | ||
2435 | I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); | |
de151cf6 JB |
2436 | } |
2437 | ||
2cf34d7b CW |
2438 | static int i915_find_fence_reg(struct drm_device *dev, |
2439 | bool interruptible) | |
ae3db24a DV |
2440 | { |
2441 | struct drm_i915_fence_reg *reg = NULL; | |
2442 | struct drm_i915_gem_object *obj_priv = NULL; | |
2443 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2444 | struct drm_gem_object *obj = NULL; | |
2445 | int i, avail, ret; | |
2446 | ||
2447 | /* First try to find a free reg */ | |
2448 | avail = 0; | |
2449 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { | |
2450 | reg = &dev_priv->fence_regs[i]; | |
2451 | if (!reg->obj) | |
2452 | return i; | |
2453 | ||
23010e43 | 2454 | obj_priv = to_intel_bo(reg->obj); |
ae3db24a DV |
2455 | if (!obj_priv->pin_count) |
2456 | avail++; | |
2457 | } | |
2458 | ||
2459 | if (avail == 0) | |
2460 | return -ENOSPC; | |
2461 | ||
2462 | /* None available, try to steal one or wait for a user to finish */ | |
2463 | i = I915_FENCE_REG_NONE; | |
007cc8ac DV |
2464 | list_for_each_entry(reg, &dev_priv->mm.fence_list, |
2465 | lru_list) { | |
2466 | obj = reg->obj; | |
2467 | obj_priv = to_intel_bo(obj); | |
ae3db24a DV |
2468 | |
2469 | if (obj_priv->pin_count) | |
2470 | continue; | |
2471 | ||
2472 | /* found one! */ | |
2473 | i = obj_priv->fence_reg; | |
2474 | break; | |
2475 | } | |
2476 | ||
2477 | BUG_ON(i == I915_FENCE_REG_NONE); | |
2478 | ||
2479 | /* We only have a reference on obj from the active list. put_fence_reg | |
2480 | * might drop that one, causing a use-after-free in it. So hold a | |
2481 | * private reference to obj like the other callers of put_fence_reg | |
2482 | * (set_tiling ioctl) do. */ | |
2483 | drm_gem_object_reference(obj); | |
2cf34d7b | 2484 | ret = i915_gem_object_put_fence_reg(obj, interruptible); |
ae3db24a DV |
2485 | drm_gem_object_unreference(obj); |
2486 | if (ret != 0) | |
2487 | return ret; | |
2488 | ||
2489 | return i; | |
2490 | } | |
2491 | ||
de151cf6 JB |
2492 | /** |
2493 | * i915_gem_object_get_fence_reg - set up a fence reg for an object | |
2494 | * @obj: object to map through a fence reg | |
2495 | * | |
2496 | * When mapping objects through the GTT, userspace wants to be able to write | |
2497 | * to them without having to worry about swizzling if the object is tiled. | |
2498 | * | |
2499 | * This function walks the fence regs looking for a free one for @obj, | |
2500 | * stealing one if it can't find any. | |
2501 | * | |
2502 | * It then sets up the reg based on the object's properties: address, pitch | |
2503 | * and tiling format. | |
2504 | */ | |
8c4b8c3f | 2505 | int |
2cf34d7b CW |
2506 | i915_gem_object_get_fence_reg(struct drm_gem_object *obj, |
2507 | bool interruptible) | |
de151cf6 JB |
2508 | { |
2509 | struct drm_device *dev = obj->dev; | |
79e53945 | 2510 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2511 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 2512 | struct drm_i915_fence_reg *reg = NULL; |
ae3db24a | 2513 | int ret; |
de151cf6 | 2514 | |
a09ba7fa EA |
2515 | /* Just update our place in the LRU if our fence is getting used. */ |
2516 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
007cc8ac DV |
2517 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
2518 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); | |
a09ba7fa EA |
2519 | return 0; |
2520 | } | |
2521 | ||
de151cf6 JB |
2522 | switch (obj_priv->tiling_mode) { |
2523 | case I915_TILING_NONE: | |
2524 | WARN(1, "allocating a fence for non-tiled object?\n"); | |
2525 | break; | |
2526 | case I915_TILING_X: | |
0f973f27 JB |
2527 | if (!obj_priv->stride) |
2528 | return -EINVAL; | |
2529 | WARN((obj_priv->stride & (512 - 1)), | |
2530 | "object 0x%08x is X tiled but has non-512B pitch\n", | |
2531 | obj_priv->gtt_offset); | |
de151cf6 JB |
2532 | break; |
2533 | case I915_TILING_Y: | |
0f973f27 JB |
2534 | if (!obj_priv->stride) |
2535 | return -EINVAL; | |
2536 | WARN((obj_priv->stride & (128 - 1)), | |
2537 | "object 0x%08x is Y tiled but has non-128B pitch\n", | |
2538 | obj_priv->gtt_offset); | |
de151cf6 JB |
2539 | break; |
2540 | } | |
2541 | ||
2cf34d7b | 2542 | ret = i915_find_fence_reg(dev, interruptible); |
ae3db24a DV |
2543 | if (ret < 0) |
2544 | return ret; | |
de151cf6 | 2545 | |
ae3db24a DV |
2546 | obj_priv->fence_reg = ret; |
2547 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; | |
007cc8ac | 2548 | list_add_tail(®->lru_list, &dev_priv->mm.fence_list); |
a09ba7fa | 2549 | |
de151cf6 JB |
2550 | reg->obj = obj; |
2551 | ||
e259befd CW |
2552 | switch (INTEL_INFO(dev)->gen) { |
2553 | case 6: | |
4e901fdc | 2554 | sandybridge_write_fence_reg(reg); |
e259befd CW |
2555 | break; |
2556 | case 5: | |
2557 | case 4: | |
de151cf6 | 2558 | i965_write_fence_reg(reg); |
e259befd CW |
2559 | break; |
2560 | case 3: | |
de151cf6 | 2561 | i915_write_fence_reg(reg); |
e259befd CW |
2562 | break; |
2563 | case 2: | |
de151cf6 | 2564 | i830_write_fence_reg(reg); |
e259befd CW |
2565 | break; |
2566 | } | |
d9ddcb96 | 2567 | |
ae3db24a DV |
2568 | trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg, |
2569 | obj_priv->tiling_mode); | |
1c5d22f7 | 2570 | |
d9ddcb96 | 2571 | return 0; |
de151cf6 JB |
2572 | } |
2573 | ||
2574 | /** | |
2575 | * i915_gem_clear_fence_reg - clear out fence register info | |
2576 | * @obj: object to clear | |
2577 | * | |
2578 | * Zeroes out the fence register itself and clears out the associated | |
2579 | * data structures in dev_priv and obj_priv. | |
2580 | */ | |
2581 | static void | |
2582 | i915_gem_clear_fence_reg(struct drm_gem_object *obj) | |
2583 | { | |
2584 | struct drm_device *dev = obj->dev; | |
79e53945 | 2585 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 2586 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
007cc8ac DV |
2587 | struct drm_i915_fence_reg *reg = |
2588 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
e259befd | 2589 | uint32_t fence_reg; |
de151cf6 | 2590 | |
e259befd CW |
2591 | switch (INTEL_INFO(dev)->gen) { |
2592 | case 6: | |
4e901fdc EA |
2593 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + |
2594 | (obj_priv->fence_reg * 8), 0); | |
e259befd CW |
2595 | break; |
2596 | case 5: | |
2597 | case 4: | |
de151cf6 | 2598 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); |
e259befd CW |
2599 | break; |
2600 | case 3: | |
9b74f734 | 2601 | if (obj_priv->fence_reg >= 8) |
e259befd | 2602 | fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4; |
dc529a4f | 2603 | else |
e259befd CW |
2604 | case 2: |
2605 | fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4; | |
dc529a4f EA |
2606 | |
2607 | I915_WRITE(fence_reg, 0); | |
e259befd | 2608 | break; |
dc529a4f | 2609 | } |
de151cf6 | 2610 | |
007cc8ac | 2611 | reg->obj = NULL; |
de151cf6 | 2612 | obj_priv->fence_reg = I915_FENCE_REG_NONE; |
007cc8ac | 2613 | list_del_init(®->lru_list); |
de151cf6 JB |
2614 | } |
2615 | ||
52dc7d32 CW |
2616 | /** |
2617 | * i915_gem_object_put_fence_reg - waits on outstanding fenced access | |
2618 | * to the buffer to finish, and then resets the fence register. | |
2619 | * @obj: tiled object holding a fence register. | |
2cf34d7b | 2620 | * @bool: whether the wait upon the fence is interruptible |
52dc7d32 CW |
2621 | * |
2622 | * Zeroes out the fence register itself and clears out the associated | |
2623 | * data structures in dev_priv and obj_priv. | |
2624 | */ | |
2625 | int | |
2cf34d7b CW |
2626 | i915_gem_object_put_fence_reg(struct drm_gem_object *obj, |
2627 | bool interruptible) | |
52dc7d32 CW |
2628 | { |
2629 | struct drm_device *dev = obj->dev; | |
53640e1d | 2630 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2631 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
53640e1d | 2632 | struct drm_i915_fence_reg *reg; |
52dc7d32 CW |
2633 | |
2634 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE) | |
2635 | return 0; | |
2636 | ||
10ae9bd2 DV |
2637 | /* If we've changed tiling, GTT-mappings of the object |
2638 | * need to re-fault to ensure that the correct fence register | |
2639 | * setup is in place. | |
2640 | */ | |
2641 | i915_gem_release_mmap(obj); | |
2642 | ||
52dc7d32 CW |
2643 | /* On the i915, GPU access to tiled buffers is via a fence, |
2644 | * therefore we must wait for any outstanding access to complete | |
2645 | * before clearing the fence. | |
2646 | */ | |
53640e1d CW |
2647 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
2648 | if (reg->gpu) { | |
52dc7d32 CW |
2649 | int ret; |
2650 | ||
2cf34d7b | 2651 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
0bc23aad | 2652 | if (ret) |
2dafb1e0 CW |
2653 | return ret; |
2654 | ||
2cf34d7b | 2655 | ret = i915_gem_object_wait_rendering(obj, interruptible); |
0bc23aad | 2656 | if (ret) |
52dc7d32 | 2657 | return ret; |
53640e1d CW |
2658 | |
2659 | reg->gpu = false; | |
52dc7d32 CW |
2660 | } |
2661 | ||
4a726612 | 2662 | i915_gem_object_flush_gtt_write_domain(obj); |
0bc23aad | 2663 | i915_gem_clear_fence_reg(obj); |
52dc7d32 CW |
2664 | |
2665 | return 0; | |
2666 | } | |
2667 | ||
673a394b EA |
2668 | /** |
2669 | * Finds free space in the GTT aperture and binds the object there. | |
2670 | */ | |
2671 | static int | |
920afa77 DV |
2672 | i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
2673 | unsigned alignment, | |
2674 | bool mappable) | |
673a394b EA |
2675 | { |
2676 | struct drm_device *dev = obj->dev; | |
2677 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2678 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 2679 | struct drm_mm_node *free_space; |
4bdadb97 | 2680 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
07f73f69 | 2681 | int ret; |
673a394b | 2682 | |
bb6baf76 | 2683 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2684 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2685 | return -EINVAL; | |
2686 | } | |
2687 | ||
673a394b | 2688 | if (alignment == 0) |
0f973f27 | 2689 | alignment = i915_gem_get_gtt_alignment(obj); |
8d7773a3 | 2690 | if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) { |
673a394b EA |
2691 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2692 | return -EINVAL; | |
2693 | } | |
2694 | ||
654fc607 CW |
2695 | /* If the object is bigger than the entire aperture, reject it early |
2696 | * before evicting everything in a vain attempt to find space. | |
2697 | */ | |
920afa77 DV |
2698 | if (obj->size > |
2699 | (mappable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { | |
654fc607 CW |
2700 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2701 | return -E2BIG; | |
2702 | } | |
2703 | ||
673a394b | 2704 | search_free: |
920afa77 DV |
2705 | if (mappable) |
2706 | free_space = | |
2707 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, | |
2708 | obj->size, alignment, 0, | |
2709 | dev_priv->mm.gtt_mappable_end, | |
2710 | 0); | |
2711 | else | |
2712 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
2713 | obj->size, alignment, 0); | |
2714 | ||
2715 | if (free_space != NULL) { | |
2716 | if (mappable) | |
2717 | obj_priv->gtt_space = | |
2718 | drm_mm_get_block_range_generic(free_space, | |
2719 | obj->size, | |
2720 | alignment, 0, | |
2721 | dev_priv->mm.gtt_mappable_end, | |
2722 | 0); | |
2723 | else | |
2724 | obj_priv->gtt_space = | |
2725 | drm_mm_get_block(free_space, obj->size, | |
2726 | alignment); | |
2727 | } | |
673a394b EA |
2728 | if (obj_priv->gtt_space == NULL) { |
2729 | /* If the gtt is empty and we're still having trouble | |
2730 | * fitting our object in, we're out of memory. | |
2731 | */ | |
920afa77 DV |
2732 | ret = i915_gem_evict_something(dev, obj->size, alignment, |
2733 | mappable); | |
9731129c | 2734 | if (ret) |
673a394b | 2735 | return ret; |
9731129c | 2736 | |
673a394b EA |
2737 | goto search_free; |
2738 | } | |
2739 | ||
e5281ccd | 2740 | ret = i915_gem_object_get_pages_gtt(obj, gfpmask); |
673a394b EA |
2741 | if (ret) { |
2742 | drm_mm_put_block(obj_priv->gtt_space); | |
2743 | obj_priv->gtt_space = NULL; | |
07f73f69 CW |
2744 | |
2745 | if (ret == -ENOMEM) { | |
2746 | /* first try to clear up some space from the GTT */ | |
0108a3ed | 2747 | ret = i915_gem_evict_something(dev, obj->size, |
920afa77 | 2748 | alignment, mappable); |
07f73f69 | 2749 | if (ret) { |
07f73f69 | 2750 | /* now try to shrink everyone else */ |
4bdadb97 CW |
2751 | if (gfpmask) { |
2752 | gfpmask = 0; | |
2753 | goto search_free; | |
07f73f69 CW |
2754 | } |
2755 | ||
2756 | return ret; | |
2757 | } | |
2758 | ||
2759 | goto search_free; | |
2760 | } | |
2761 | ||
673a394b EA |
2762 | return ret; |
2763 | } | |
2764 | ||
673a394b EA |
2765 | /* Create an AGP memory structure pointing at our pages, and bind it |
2766 | * into the GTT. | |
2767 | */ | |
2768 | obj_priv->agp_mem = drm_agp_bind_pages(dev, | |
856fa198 | 2769 | obj_priv->pages, |
07f73f69 | 2770 | obj->size >> PAGE_SHIFT, |
9af90d19 | 2771 | obj_priv->gtt_space->start, |
ba1eb1d8 | 2772 | obj_priv->agp_type); |
673a394b | 2773 | if (obj_priv->agp_mem == NULL) { |
e5281ccd | 2774 | i915_gem_object_put_pages_gtt(obj); |
673a394b EA |
2775 | drm_mm_put_block(obj_priv->gtt_space); |
2776 | obj_priv->gtt_space = NULL; | |
07f73f69 | 2777 | |
920afa77 DV |
2778 | ret = i915_gem_evict_something(dev, obj->size, alignment, |
2779 | mappable); | |
9731129c | 2780 | if (ret) |
07f73f69 | 2781 | return ret; |
07f73f69 CW |
2782 | |
2783 | goto search_free; | |
673a394b | 2784 | } |
673a394b | 2785 | |
fb7d516a DV |
2786 | obj_priv->gtt_offset = obj_priv->gtt_space->start; |
2787 | ||
bf1a1092 | 2788 | /* keep track of bounds object by adding it to the inactive list */ |
69dc4987 | 2789 | list_add_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
fb7d516a | 2790 | i915_gem_info_add_gtt(dev_priv, obj); |
bf1a1092 | 2791 | |
673a394b EA |
2792 | /* Assert that the object is not currently in any GPU domain. As it |
2793 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2794 | * a GPU cache | |
2795 | */ | |
21d509e3 CW |
2796 | BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS); |
2797 | BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2798 | |
ec57d260 | 2799 | trace_i915_gem_object_bind(obj, obj_priv->gtt_offset, mappable); |
1c5d22f7 | 2800 | |
673a394b EA |
2801 | return 0; |
2802 | } | |
2803 | ||
2804 | void | |
2805 | i915_gem_clflush_object(struct drm_gem_object *obj) | |
2806 | { | |
23010e43 | 2807 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2808 | |
2809 | /* If we don't have a page list set up, then we're not pinned | |
2810 | * to GPU, and we can ignore the cache flush because it'll happen | |
2811 | * again at bind time. | |
2812 | */ | |
856fa198 | 2813 | if (obj_priv->pages == NULL) |
673a394b EA |
2814 | return; |
2815 | ||
1c5d22f7 | 2816 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2817 | |
856fa198 | 2818 | drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE); |
673a394b EA |
2819 | } |
2820 | ||
e47c68e9 | 2821 | /** Flushes any GPU write domain for the object if it's dirty. */ |
2dafb1e0 | 2822 | static int |
ba3d8d74 DV |
2823 | i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, |
2824 | bool pipelined) | |
e47c68e9 EA |
2825 | { |
2826 | struct drm_device *dev = obj->dev; | |
1c5d22f7 | 2827 | uint32_t old_write_domain; |
e47c68e9 EA |
2828 | |
2829 | if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) | |
2dafb1e0 | 2830 | return 0; |
e47c68e9 EA |
2831 | |
2832 | /* Queue the GPU write cache flushing we need. */ | |
1c5d22f7 | 2833 | old_write_domain = obj->write_domain; |
c78ec30b | 2834 | i915_gem_flush_ring(dev, NULL, |
9220434a CW |
2835 | to_intel_bo(obj)->ring, |
2836 | 0, obj->write_domain); | |
48b956c5 | 2837 | BUG_ON(obj->write_domain); |
1c5d22f7 CW |
2838 | |
2839 | trace_i915_gem_object_change_domain(obj, | |
2840 | obj->read_domains, | |
2841 | old_write_domain); | |
ba3d8d74 DV |
2842 | |
2843 | if (pipelined) | |
2844 | return 0; | |
2845 | ||
2cf34d7b | 2846 | return i915_gem_object_wait_rendering(obj, true); |
e47c68e9 EA |
2847 | } |
2848 | ||
2849 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2850 | static void | |
2851 | i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj) | |
2852 | { | |
1c5d22f7 CW |
2853 | uint32_t old_write_domain; |
2854 | ||
e47c68e9 EA |
2855 | if (obj->write_domain != I915_GEM_DOMAIN_GTT) |
2856 | return; | |
2857 | ||
2858 | /* No actual flushing is required for the GTT write domain. Writes | |
2859 | * to it immediately go to main memory as far as we know, so there's | |
2860 | * no chipset flush. It also doesn't land in render cache. | |
2861 | */ | |
1c5d22f7 | 2862 | old_write_domain = obj->write_domain; |
e47c68e9 | 2863 | obj->write_domain = 0; |
1c5d22f7 CW |
2864 | |
2865 | trace_i915_gem_object_change_domain(obj, | |
2866 | obj->read_domains, | |
2867 | old_write_domain); | |
e47c68e9 EA |
2868 | } |
2869 | ||
2870 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2871 | static void | |
2872 | i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj) | |
2873 | { | |
2874 | struct drm_device *dev = obj->dev; | |
1c5d22f7 | 2875 | uint32_t old_write_domain; |
e47c68e9 EA |
2876 | |
2877 | if (obj->write_domain != I915_GEM_DOMAIN_CPU) | |
2878 | return; | |
2879 | ||
2880 | i915_gem_clflush_object(obj); | |
2881 | drm_agp_chipset_flush(dev); | |
1c5d22f7 | 2882 | old_write_domain = obj->write_domain; |
e47c68e9 | 2883 | obj->write_domain = 0; |
1c5d22f7 CW |
2884 | |
2885 | trace_i915_gem_object_change_domain(obj, | |
2886 | obj->read_domains, | |
2887 | old_write_domain); | |
e47c68e9 EA |
2888 | } |
2889 | ||
2ef7eeaa EA |
2890 | /** |
2891 | * Moves a single object to the GTT read, and possibly write domain. | |
2892 | * | |
2893 | * This function returns when the move is complete, including waiting on | |
2894 | * flushes to occur. | |
2895 | */ | |
79e53945 | 2896 | int |
2ef7eeaa EA |
2897 | i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) |
2898 | { | |
23010e43 | 2899 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 2900 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2901 | int ret; |
2ef7eeaa | 2902 | |
02354392 EA |
2903 | /* Not valid to be called on unbound objects. */ |
2904 | if (obj_priv->gtt_space == NULL) | |
2905 | return -EINVAL; | |
2906 | ||
ba3d8d74 | 2907 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
2dafb1e0 CW |
2908 | if (ret != 0) |
2909 | return ret; | |
2910 | ||
7213342d | 2911 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 2912 | |
ba3d8d74 | 2913 | if (write) { |
2cf34d7b | 2914 | ret = i915_gem_object_wait_rendering(obj, true); |
ba3d8d74 DV |
2915 | if (ret) |
2916 | return ret; | |
ba3d8d74 | 2917 | } |
e47c68e9 | 2918 | |
1c5d22f7 CW |
2919 | old_write_domain = obj->write_domain; |
2920 | old_read_domains = obj->read_domains; | |
2921 | ||
e47c68e9 EA |
2922 | /* It should now be out of any other write domains, and we can update |
2923 | * the domain values for our changes. | |
2924 | */ | |
2925 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); | |
2926 | obj->read_domains |= I915_GEM_DOMAIN_GTT; | |
2927 | if (write) { | |
7213342d | 2928 | obj->read_domains = I915_GEM_DOMAIN_GTT; |
e47c68e9 EA |
2929 | obj->write_domain = I915_GEM_DOMAIN_GTT; |
2930 | obj_priv->dirty = 1; | |
2ef7eeaa EA |
2931 | } |
2932 | ||
1c5d22f7 CW |
2933 | trace_i915_gem_object_change_domain(obj, |
2934 | old_read_domains, | |
2935 | old_write_domain); | |
2936 | ||
e47c68e9 EA |
2937 | return 0; |
2938 | } | |
2939 | ||
b9241ea3 ZW |
2940 | /* |
2941 | * Prepare buffer for display plane. Use uninterruptible for possible flush | |
2942 | * wait, as in modesetting process we're not supposed to be interrupted. | |
2943 | */ | |
2944 | int | |
48b956c5 CW |
2945 | i915_gem_object_set_to_display_plane(struct drm_gem_object *obj, |
2946 | bool pipelined) | |
b9241ea3 | 2947 | { |
23010e43 | 2948 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ba3d8d74 | 2949 | uint32_t old_read_domains; |
b9241ea3 ZW |
2950 | int ret; |
2951 | ||
2952 | /* Not valid to be called on unbound objects. */ | |
2953 | if (obj_priv->gtt_space == NULL) | |
2954 | return -EINVAL; | |
2955 | ||
ced270fa | 2956 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
2dafb1e0 CW |
2957 | if (ret) |
2958 | return ret; | |
b9241ea3 | 2959 | |
ced270fa CW |
2960 | /* Currently, we are always called from an non-interruptible context. */ |
2961 | if (!pipelined) { | |
2962 | ret = i915_gem_object_wait_rendering(obj, false); | |
2963 | if (ret) | |
b9241ea3 ZW |
2964 | return ret; |
2965 | } | |
2966 | ||
b118c1e3 CW |
2967 | i915_gem_object_flush_cpu_write_domain(obj); |
2968 | ||
b9241ea3 | 2969 | old_read_domains = obj->read_domains; |
c78ec30b | 2970 | obj->read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
2971 | |
2972 | trace_i915_gem_object_change_domain(obj, | |
2973 | old_read_domains, | |
ba3d8d74 | 2974 | obj->write_domain); |
b9241ea3 ZW |
2975 | |
2976 | return 0; | |
2977 | } | |
2978 | ||
e47c68e9 EA |
2979 | /** |
2980 | * Moves a single object to the CPU read, and possibly write domain. | |
2981 | * | |
2982 | * This function returns when the move is complete, including waiting on | |
2983 | * flushes to occur. | |
2984 | */ | |
2985 | static int | |
2986 | i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) | |
2987 | { | |
1c5d22f7 | 2988 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
2989 | int ret; |
2990 | ||
ba3d8d74 | 2991 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 EA |
2992 | if (ret != 0) |
2993 | return ret; | |
2ef7eeaa | 2994 | |
e47c68e9 | 2995 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 2996 | |
e47c68e9 EA |
2997 | /* If we have a partially-valid cache of the object in the CPU, |
2998 | * finish invalidating it and free the per-page flags. | |
2ef7eeaa | 2999 | */ |
e47c68e9 | 3000 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
2ef7eeaa | 3001 | |
7213342d | 3002 | if (write) { |
2cf34d7b | 3003 | ret = i915_gem_object_wait_rendering(obj, true); |
7213342d CW |
3004 | if (ret) |
3005 | return ret; | |
3006 | } | |
3007 | ||
1c5d22f7 CW |
3008 | old_write_domain = obj->write_domain; |
3009 | old_read_domains = obj->read_domains; | |
3010 | ||
e47c68e9 EA |
3011 | /* Flush the CPU cache if it's still invalid. */ |
3012 | if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) { | |
2ef7eeaa | 3013 | i915_gem_clflush_object(obj); |
2ef7eeaa | 3014 | |
e47c68e9 | 3015 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3016 | } |
3017 | ||
3018 | /* It should now be out of any other write domains, and we can update | |
3019 | * the domain values for our changes. | |
3020 | */ | |
e47c68e9 EA |
3021 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
3022 | ||
3023 | /* If we're writing through the CPU, then the GPU read domains will | |
3024 | * need to be invalidated at next use. | |
3025 | */ | |
3026 | if (write) { | |
c78ec30b | 3027 | obj->read_domains = I915_GEM_DOMAIN_CPU; |
e47c68e9 EA |
3028 | obj->write_domain = I915_GEM_DOMAIN_CPU; |
3029 | } | |
2ef7eeaa | 3030 | |
1c5d22f7 CW |
3031 | trace_i915_gem_object_change_domain(obj, |
3032 | old_read_domains, | |
3033 | old_write_domain); | |
3034 | ||
2ef7eeaa EA |
3035 | return 0; |
3036 | } | |
3037 | ||
673a394b EA |
3038 | /* |
3039 | * Set the next domain for the specified object. This | |
3040 | * may not actually perform the necessary flushing/invaliding though, | |
3041 | * as that may want to be batched with other set_domain operations | |
3042 | * | |
3043 | * This is (we hope) the only really tricky part of gem. The goal | |
3044 | * is fairly simple -- track which caches hold bits of the object | |
3045 | * and make sure they remain coherent. A few concrete examples may | |
3046 | * help to explain how it works. For shorthand, we use the notation | |
3047 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the | |
3048 | * a pair of read and write domain masks. | |
3049 | * | |
3050 | * Case 1: the batch buffer | |
3051 | * | |
3052 | * 1. Allocated | |
3053 | * 2. Written by CPU | |
3054 | * 3. Mapped to GTT | |
3055 | * 4. Read by GPU | |
3056 | * 5. Unmapped from GTT | |
3057 | * 6. Freed | |
3058 | * | |
3059 | * Let's take these a step at a time | |
3060 | * | |
3061 | * 1. Allocated | |
3062 | * Pages allocated from the kernel may still have | |
3063 | * cache contents, so we set them to (CPU, CPU) always. | |
3064 | * 2. Written by CPU (using pwrite) | |
3065 | * The pwrite function calls set_domain (CPU, CPU) and | |
3066 | * this function does nothing (as nothing changes) | |
3067 | * 3. Mapped by GTT | |
3068 | * This function asserts that the object is not | |
3069 | * currently in any GPU-based read or write domains | |
3070 | * 4. Read by GPU | |
3071 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). | |
3072 | * As write_domain is zero, this function adds in the | |
3073 | * current read domains (CPU+COMMAND, 0). | |
3074 | * flush_domains is set to CPU. | |
3075 | * invalidate_domains is set to COMMAND | |
3076 | * clflush is run to get data out of the CPU caches | |
3077 | * then i915_dev_set_domain calls i915_gem_flush to | |
3078 | * emit an MI_FLUSH and drm_agp_chipset_flush | |
3079 | * 5. Unmapped from GTT | |
3080 | * i915_gem_object_unbind calls set_domain (CPU, CPU) | |
3081 | * flush_domains and invalidate_domains end up both zero | |
3082 | * so no flushing/invalidating happens | |
3083 | * 6. Freed | |
3084 | * yay, done | |
3085 | * | |
3086 | * Case 2: The shared render buffer | |
3087 | * | |
3088 | * 1. Allocated | |
3089 | * 2. Mapped to GTT | |
3090 | * 3. Read/written by GPU | |
3091 | * 4. set_domain to (CPU,CPU) | |
3092 | * 5. Read/written by CPU | |
3093 | * 6. Read/written by GPU | |
3094 | * | |
3095 | * 1. Allocated | |
3096 | * Same as last example, (CPU, CPU) | |
3097 | * 2. Mapped to GTT | |
3098 | * Nothing changes (assertions find that it is not in the GPU) | |
3099 | * 3. Read/written by GPU | |
3100 | * execbuffer calls set_domain (RENDER, RENDER) | |
3101 | * flush_domains gets CPU | |
3102 | * invalidate_domains gets GPU | |
3103 | * clflush (obj) | |
3104 | * MI_FLUSH and drm_agp_chipset_flush | |
3105 | * 4. set_domain (CPU, CPU) | |
3106 | * flush_domains gets GPU | |
3107 | * invalidate_domains gets CPU | |
3108 | * wait_rendering (obj) to make sure all drawing is complete. | |
3109 | * This will include an MI_FLUSH to get the data from GPU | |
3110 | * to memory | |
3111 | * clflush (obj) to invalidate the CPU cache | |
3112 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) | |
3113 | * 5. Read/written by CPU | |
3114 | * cache lines are loaded and dirtied | |
3115 | * 6. Read written by GPU | |
3116 | * Same as last GPU access | |
3117 | * | |
3118 | * Case 3: The constant buffer | |
3119 | * | |
3120 | * 1. Allocated | |
3121 | * 2. Written by CPU | |
3122 | * 3. Read by GPU | |
3123 | * 4. Updated (written) by CPU again | |
3124 | * 5. Read by GPU | |
3125 | * | |
3126 | * 1. Allocated | |
3127 | * (CPU, CPU) | |
3128 | * 2. Written by CPU | |
3129 | * (CPU, CPU) | |
3130 | * 3. Read by GPU | |
3131 | * (CPU+RENDER, 0) | |
3132 | * flush_domains = CPU | |
3133 | * invalidate_domains = RENDER | |
3134 | * clflush (obj) | |
3135 | * MI_FLUSH | |
3136 | * drm_agp_chipset_flush | |
3137 | * 4. Updated (written) by CPU again | |
3138 | * (CPU, CPU) | |
3139 | * flush_domains = 0 (no previous write domain) | |
3140 | * invalidate_domains = 0 (no new read domains) | |
3141 | * 5. Read by GPU | |
3142 | * (CPU+RENDER, 0) | |
3143 | * flush_domains = CPU | |
3144 | * invalidate_domains = RENDER | |
3145 | * clflush (obj) | |
3146 | * MI_FLUSH | |
3147 | * drm_agp_chipset_flush | |
3148 | */ | |
c0d90829 | 3149 | static void |
b6651458 CW |
3150 | i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj, |
3151 | struct intel_ring_buffer *ring) | |
673a394b EA |
3152 | { |
3153 | struct drm_device *dev = obj->dev; | |
9220434a | 3154 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 3155 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
3156 | uint32_t invalidate_domains = 0; |
3157 | uint32_t flush_domains = 0; | |
652c393a | 3158 | |
673a394b EA |
3159 | /* |
3160 | * If the object isn't moving to a new write domain, | |
3161 | * let the object stay in multiple read domains | |
3162 | */ | |
8b0e378a EA |
3163 | if (obj->pending_write_domain == 0) |
3164 | obj->pending_read_domains |= obj->read_domains; | |
673a394b EA |
3165 | |
3166 | /* | |
3167 | * Flush the current write domain if | |
3168 | * the new read domains don't match. Invalidate | |
3169 | * any read domains which differ from the old | |
3170 | * write domain | |
3171 | */ | |
8b0e378a EA |
3172 | if (obj->write_domain && |
3173 | obj->write_domain != obj->pending_read_domains) { | |
673a394b | 3174 | flush_domains |= obj->write_domain; |
8b0e378a EA |
3175 | invalidate_domains |= |
3176 | obj->pending_read_domains & ~obj->write_domain; | |
673a394b EA |
3177 | } |
3178 | /* | |
3179 | * Invalidate any read caches which may have | |
3180 | * stale data. That is, any new read domains. | |
3181 | */ | |
8b0e378a | 3182 | invalidate_domains |= obj->pending_read_domains & ~obj->read_domains; |
3d2a812a | 3183 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) |
673a394b | 3184 | i915_gem_clflush_object(obj); |
673a394b | 3185 | |
efbeed96 EA |
3186 | /* The actual obj->write_domain will be updated with |
3187 | * pending_write_domain after we emit the accumulated flush for all | |
3188 | * of our domain changes in execbuffers (which clears objects' | |
3189 | * write_domains). So if we have a current write domain that we | |
3190 | * aren't changing, set pending_write_domain to that. | |
3191 | */ | |
3192 | if (flush_domains == 0 && obj->pending_write_domain == 0) | |
3193 | obj->pending_write_domain = obj->write_domain; | |
673a394b EA |
3194 | |
3195 | dev->invalidate_domains |= invalidate_domains; | |
3196 | dev->flush_domains |= flush_domains; | |
b6651458 | 3197 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
9220434a | 3198 | dev_priv->mm.flush_rings |= obj_priv->ring->id; |
b6651458 CW |
3199 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) |
3200 | dev_priv->mm.flush_rings |= ring->id; | |
673a394b EA |
3201 | } |
3202 | ||
3203 | /** | |
e47c68e9 | 3204 | * Moves the object from a partially CPU read to a full one. |
673a394b | 3205 | * |
e47c68e9 EA |
3206 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
3207 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). | |
673a394b | 3208 | */ |
e47c68e9 EA |
3209 | static void |
3210 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj) | |
673a394b | 3211 | { |
23010e43 | 3212 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 3213 | |
e47c68e9 EA |
3214 | if (!obj_priv->page_cpu_valid) |
3215 | return; | |
3216 | ||
3217 | /* If we're partially in the CPU read domain, finish moving it in. | |
3218 | */ | |
3219 | if (obj->read_domains & I915_GEM_DOMAIN_CPU) { | |
3220 | int i; | |
3221 | ||
3222 | for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) { | |
3223 | if (obj_priv->page_cpu_valid[i]) | |
3224 | continue; | |
856fa198 | 3225 | drm_clflush_pages(obj_priv->pages + i, 1); |
e47c68e9 | 3226 | } |
e47c68e9 EA |
3227 | } |
3228 | ||
3229 | /* Free the page_cpu_valid mappings which are now stale, whether | |
3230 | * or not we've got I915_GEM_DOMAIN_CPU. | |
3231 | */ | |
9a298b2a | 3232 | kfree(obj_priv->page_cpu_valid); |
e47c68e9 EA |
3233 | obj_priv->page_cpu_valid = NULL; |
3234 | } | |
3235 | ||
3236 | /** | |
3237 | * Set the CPU read domain on a range of the object. | |
3238 | * | |
3239 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's | |
3240 | * not entirely valid. The page_cpu_valid member of the object flags which | |
3241 | * pages have been flushed, and will be respected by | |
3242 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping | |
3243 | * of the whole object. | |
3244 | * | |
3245 | * This function returns when the move is complete, including waiting on | |
3246 | * flushes to occur. | |
3247 | */ | |
3248 | static int | |
3249 | i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
3250 | uint64_t offset, uint64_t size) | |
3251 | { | |
23010e43 | 3252 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 3253 | uint32_t old_read_domains; |
e47c68e9 | 3254 | int i, ret; |
673a394b | 3255 | |
e47c68e9 EA |
3256 | if (offset == 0 && size == obj->size) |
3257 | return i915_gem_object_set_to_cpu_domain(obj, 0); | |
673a394b | 3258 | |
ba3d8d74 | 3259 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 | 3260 | if (ret != 0) |
6a47baa6 | 3261 | return ret; |
e47c68e9 EA |
3262 | i915_gem_object_flush_gtt_write_domain(obj); |
3263 | ||
3264 | /* If we're already fully in the CPU read domain, we're done. */ | |
3265 | if (obj_priv->page_cpu_valid == NULL && | |
3266 | (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0) | |
3267 | return 0; | |
673a394b | 3268 | |
e47c68e9 EA |
3269 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
3270 | * newly adding I915_GEM_DOMAIN_CPU | |
3271 | */ | |
673a394b | 3272 | if (obj_priv->page_cpu_valid == NULL) { |
9a298b2a EA |
3273 | obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE, |
3274 | GFP_KERNEL); | |
e47c68e9 EA |
3275 | if (obj_priv->page_cpu_valid == NULL) |
3276 | return -ENOMEM; | |
3277 | } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
3278 | memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE); | |
673a394b EA |
3279 | |
3280 | /* Flush the cache on any pages that are still invalid from the CPU's | |
3281 | * perspective. | |
3282 | */ | |
e47c68e9 EA |
3283 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
3284 | i++) { | |
673a394b EA |
3285 | if (obj_priv->page_cpu_valid[i]) |
3286 | continue; | |
3287 | ||
856fa198 | 3288 | drm_clflush_pages(obj_priv->pages + i, 1); |
673a394b EA |
3289 | |
3290 | obj_priv->page_cpu_valid[i] = 1; | |
3291 | } | |
3292 | ||
e47c68e9 EA |
3293 | /* It should now be out of any other write domains, and we can update |
3294 | * the domain values for our changes. | |
3295 | */ | |
3296 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); | |
3297 | ||
1c5d22f7 | 3298 | old_read_domains = obj->read_domains; |
e47c68e9 EA |
3299 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
3300 | ||
1c5d22f7 CW |
3301 | trace_i915_gem_object_change_domain(obj, |
3302 | old_read_domains, | |
3303 | obj->write_domain); | |
3304 | ||
673a394b EA |
3305 | return 0; |
3306 | } | |
3307 | ||
673a394b EA |
3308 | /** |
3309 | * Pin an object to the GTT and evaluate the relocations landing in it. | |
3310 | */ | |
3311 | static int | |
9af90d19 CW |
3312 | i915_gem_execbuffer_relocate(struct drm_i915_gem_object *obj, |
3313 | struct drm_file *file_priv, | |
3314 | struct drm_i915_gem_exec_object2 *entry) | |
673a394b | 3315 | { |
9af90d19 | 3316 | struct drm_device *dev = obj->base.dev; |
0839ccb8 | 3317 | drm_i915_private_t *dev_priv = dev->dev_private; |
2549d6c2 | 3318 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
9af90d19 CW |
3319 | struct drm_gem_object *target_obj = NULL; |
3320 | uint32_t target_handle = 0; | |
3321 | int i, ret = 0; | |
673a394b | 3322 | |
2549d6c2 | 3323 | user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr; |
673a394b | 3324 | for (i = 0; i < entry->relocation_count; i++) { |
2549d6c2 | 3325 | struct drm_i915_gem_relocation_entry reloc; |
9af90d19 | 3326 | uint32_t target_offset; |
673a394b | 3327 | |
9af90d19 CW |
3328 | if (__copy_from_user_inatomic(&reloc, |
3329 | user_relocs+i, | |
3330 | sizeof(reloc))) { | |
3331 | ret = -EFAULT; | |
3332 | break; | |
76446cac | 3333 | } |
76446cac | 3334 | |
9af90d19 CW |
3335 | if (reloc.target_handle != target_handle) { |
3336 | drm_gem_object_unreference(target_obj); | |
673a394b | 3337 | |
9af90d19 CW |
3338 | target_obj = drm_gem_object_lookup(dev, file_priv, |
3339 | reloc.target_handle); | |
3340 | if (target_obj == NULL) { | |
3341 | ret = -ENOENT; | |
3342 | break; | |
3343 | } | |
3344 | ||
3345 | target_handle = reloc.target_handle; | |
673a394b | 3346 | } |
9af90d19 | 3347 | target_offset = to_intel_bo(target_obj)->gtt_offset; |
673a394b | 3348 | |
8542a0bb CW |
3349 | #if WATCH_RELOC |
3350 | DRM_INFO("%s: obj %p offset %08x target %d " | |
3351 | "read %08x write %08x gtt %08x " | |
3352 | "presumed %08x delta %08x\n", | |
3353 | __func__, | |
3354 | obj, | |
2549d6c2 CW |
3355 | (int) reloc.offset, |
3356 | (int) reloc.target_handle, | |
3357 | (int) reloc.read_domains, | |
3358 | (int) reloc.write_domain, | |
9af90d19 | 3359 | (int) target_offset, |
2549d6c2 CW |
3360 | (int) reloc.presumed_offset, |
3361 | reloc.delta); | |
8542a0bb CW |
3362 | #endif |
3363 | ||
673a394b EA |
3364 | /* The target buffer should have appeared before us in the |
3365 | * exec_object list, so it should have a GTT space bound by now. | |
3366 | */ | |
9af90d19 | 3367 | if (target_offset == 0) { |
673a394b | 3368 | DRM_ERROR("No GTT space found for object %d\n", |
2549d6c2 | 3369 | reloc.target_handle); |
9af90d19 CW |
3370 | ret = -EINVAL; |
3371 | break; | |
673a394b EA |
3372 | } |
3373 | ||
8542a0bb | 3374 | /* Validate that the target is in a valid r/w GPU domain */ |
2549d6c2 | 3375 | if (reloc.write_domain & (reloc.write_domain - 1)) { |
16edd550 DV |
3376 | DRM_ERROR("reloc with multiple write domains: " |
3377 | "obj %p target %d offset %d " | |
3378 | "read %08x write %08x", | |
2549d6c2 CW |
3379 | obj, reloc.target_handle, |
3380 | (int) reloc.offset, | |
3381 | reloc.read_domains, | |
3382 | reloc.write_domain); | |
9af90d19 CW |
3383 | ret = -EINVAL; |
3384 | break; | |
16edd550 | 3385 | } |
2549d6c2 CW |
3386 | if (reloc.write_domain & I915_GEM_DOMAIN_CPU || |
3387 | reloc.read_domains & I915_GEM_DOMAIN_CPU) { | |
e47c68e9 EA |
3388 | DRM_ERROR("reloc with read/write CPU domains: " |
3389 | "obj %p target %d offset %d " | |
3390 | "read %08x write %08x", | |
2549d6c2 CW |
3391 | obj, reloc.target_handle, |
3392 | (int) reloc.offset, | |
3393 | reloc.read_domains, | |
3394 | reloc.write_domain); | |
9af90d19 CW |
3395 | ret = -EINVAL; |
3396 | break; | |
e47c68e9 | 3397 | } |
2549d6c2 CW |
3398 | if (reloc.write_domain && target_obj->pending_write_domain && |
3399 | reloc.write_domain != target_obj->pending_write_domain) { | |
673a394b EA |
3400 | DRM_ERROR("Write domain conflict: " |
3401 | "obj %p target %d offset %d " | |
3402 | "new %08x old %08x\n", | |
2549d6c2 CW |
3403 | obj, reloc.target_handle, |
3404 | (int) reloc.offset, | |
3405 | reloc.write_domain, | |
673a394b | 3406 | target_obj->pending_write_domain); |
9af90d19 CW |
3407 | ret = -EINVAL; |
3408 | break; | |
673a394b EA |
3409 | } |
3410 | ||
2549d6c2 | 3411 | target_obj->pending_read_domains |= reloc.read_domains; |
878a3c37 | 3412 | target_obj->pending_write_domain |= reloc.write_domain; |
673a394b EA |
3413 | |
3414 | /* If the relocation already has the right value in it, no | |
3415 | * more work needs to be done. | |
3416 | */ | |
9af90d19 | 3417 | if (target_offset == reloc.presumed_offset) |
673a394b | 3418 | continue; |
673a394b | 3419 | |
8542a0bb | 3420 | /* Check that the relocation address is valid... */ |
9af90d19 | 3421 | if (reloc.offset > obj->base.size - 4) { |
8542a0bb CW |
3422 | DRM_ERROR("Relocation beyond object bounds: " |
3423 | "obj %p target %d offset %d size %d.\n", | |
2549d6c2 | 3424 | obj, reloc.target_handle, |
9af90d19 CW |
3425 | (int) reloc.offset, (int) obj->base.size); |
3426 | ret = -EINVAL; | |
3427 | break; | |
8542a0bb | 3428 | } |
2549d6c2 | 3429 | if (reloc.offset & 3) { |
8542a0bb CW |
3430 | DRM_ERROR("Relocation not 4-byte aligned: " |
3431 | "obj %p target %d offset %d.\n", | |
2549d6c2 CW |
3432 | obj, reloc.target_handle, |
3433 | (int) reloc.offset); | |
9af90d19 CW |
3434 | ret = -EINVAL; |
3435 | break; | |
8542a0bb CW |
3436 | } |
3437 | ||
3438 | /* and points to somewhere within the target object. */ | |
2549d6c2 | 3439 | if (reloc.delta >= target_obj->size) { |
8542a0bb CW |
3440 | DRM_ERROR("Relocation beyond target object bounds: " |
3441 | "obj %p target %d delta %d size %d.\n", | |
2549d6c2 CW |
3442 | obj, reloc.target_handle, |
3443 | (int) reloc.delta, (int) target_obj->size); | |
9af90d19 CW |
3444 | ret = -EINVAL; |
3445 | break; | |
673a394b EA |
3446 | } |
3447 | ||
9af90d19 CW |
3448 | reloc.delta += target_offset; |
3449 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) { | |
f0c43d9b CW |
3450 | uint32_t page_offset = reloc.offset & ~PAGE_MASK; |
3451 | char *vaddr; | |
673a394b | 3452 | |
c48c43e4 | 3453 | vaddr = kmap_atomic(obj->pages[reloc.offset >> PAGE_SHIFT]); |
f0c43d9b | 3454 | *(uint32_t *)(vaddr + page_offset) = reloc.delta; |
c48c43e4 | 3455 | kunmap_atomic(vaddr); |
f0c43d9b CW |
3456 | } else { |
3457 | uint32_t __iomem *reloc_entry; | |
3458 | void __iomem *reloc_page; | |
b962442e | 3459 | |
9af90d19 CW |
3460 | ret = i915_gem_object_set_to_gtt_domain(&obj->base, 1); |
3461 | if (ret) | |
3462 | break; | |
b962442e | 3463 | |
f0c43d9b | 3464 | /* Map the page containing the relocation we're going to perform. */ |
9af90d19 | 3465 | reloc.offset += obj->gtt_offset; |
f0c43d9b | 3466 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
c48c43e4 | 3467 | reloc.offset & PAGE_MASK); |
f0c43d9b CW |
3468 | reloc_entry = (uint32_t __iomem *) |
3469 | (reloc_page + (reloc.offset & ~PAGE_MASK)); | |
3470 | iowrite32(reloc.delta, reloc_entry); | |
c48c43e4 | 3471 | io_mapping_unmap_atomic(reloc_page); |
f0c43d9b | 3472 | } |
b962442e | 3473 | |
b5dc608c CW |
3474 | /* and update the user's relocation entry */ |
3475 | reloc.presumed_offset = target_offset; | |
3476 | if (__copy_to_user_inatomic(&user_relocs[i].presumed_offset, | |
3477 | &reloc.presumed_offset, | |
3478 | sizeof(reloc.presumed_offset))) { | |
3479 | ret = -EFAULT; | |
3480 | break; | |
3481 | } | |
b962442e | 3482 | } |
b962442e | 3483 | |
9af90d19 | 3484 | drm_gem_object_unreference(target_obj); |
673a394b EA |
3485 | return ret; |
3486 | } | |
3487 | ||
40a5f0de | 3488 | static int |
9af90d19 CW |
3489 | i915_gem_execbuffer_pin(struct drm_device *dev, |
3490 | struct drm_file *file, | |
3491 | struct drm_gem_object **object_list, | |
3492 | struct drm_i915_gem_exec_object2 *exec_list, | |
3493 | int count) | |
40a5f0de | 3494 | { |
9af90d19 CW |
3495 | struct drm_i915_private *dev_priv = dev->dev_private; |
3496 | int ret, i, retry; | |
40a5f0de | 3497 | |
9af90d19 CW |
3498 | /* attempt to pin all of the buffers into the GTT */ |
3499 | for (retry = 0; retry < 2; retry++) { | |
3500 | ret = 0; | |
3501 | for (i = 0; i < count; i++) { | |
3502 | struct drm_i915_gem_exec_object2 *entry = &exec_list[i]; | |
16e809ac | 3503 | struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]); |
9af90d19 CW |
3504 | bool need_fence = |
3505 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
3506 | obj->tiling_mode != I915_TILING_NONE; | |
3507 | ||
16e809ac DV |
3508 | /* g33/pnv can't fence buffers in the unmappable part */ |
3509 | bool need_mappable = | |
3510 | entry->relocation_count ? true : need_fence; | |
3511 | ||
9af90d19 CW |
3512 | /* Check fence reg constraints and rebind if necessary */ |
3513 | if (need_fence && | |
3514 | !i915_gem_object_fence_offset_ok(&obj->base, | |
3515 | obj->tiling_mode)) { | |
3516 | ret = i915_gem_object_unbind(&obj->base); | |
3517 | if (ret) | |
3518 | break; | |
3519 | } | |
40a5f0de | 3520 | |
920afa77 | 3521 | ret = i915_gem_object_pin(&obj->base, |
16e809ac DV |
3522 | entry->alignment, |
3523 | need_mappable); | |
9af90d19 CW |
3524 | if (ret) |
3525 | break; | |
40a5f0de | 3526 | |
9af90d19 CW |
3527 | /* |
3528 | * Pre-965 chips need a fence register set up in order | |
3529 | * to properly handle blits to/from tiled surfaces. | |
3530 | */ | |
3531 | if (need_fence) { | |
3532 | ret = i915_gem_object_get_fence_reg(&obj->base, true); | |
3533 | if (ret) { | |
3534 | i915_gem_object_unpin(&obj->base); | |
3535 | break; | |
3536 | } | |
40a5f0de | 3537 | |
9af90d19 CW |
3538 | dev_priv->fence_regs[obj->fence_reg].gpu = true; |
3539 | } | |
40a5f0de | 3540 | |
9af90d19 | 3541 | entry->offset = obj->gtt_offset; |
40a5f0de EA |
3542 | } |
3543 | ||
9af90d19 CW |
3544 | while (i--) |
3545 | i915_gem_object_unpin(object_list[i]); | |
3546 | ||
3547 | if (ret == 0) | |
3548 | break; | |
673a394b | 3549 | |
9af90d19 CW |
3550 | if (ret != -ENOSPC || retry) |
3551 | return ret; | |
3552 | ||
3553 | ret = i915_gem_evict_everything(dev); | |
3554 | if (ret) | |
3555 | return ret; | |
40a5f0de EA |
3556 | } |
3557 | ||
2bc43b5c | 3558 | return 0; |
40a5f0de EA |
3559 | } |
3560 | ||
673a394b EA |
3561 | /* Throttle our rendering by waiting until the ring has completed our requests |
3562 | * emitted over 20 msec ago. | |
3563 | * | |
b962442e EA |
3564 | * Note that if we were to use the current jiffies each time around the loop, |
3565 | * we wouldn't escape the function with any frames outstanding if the time to | |
3566 | * render a frame was over 20ms. | |
3567 | * | |
673a394b EA |
3568 | * This should get us reasonable parallelism between CPU and GPU but also |
3569 | * relatively low latency when blocking on a particular request to finish. | |
3570 | */ | |
40a5f0de | 3571 | static int |
f787a5f5 | 3572 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3573 | { |
f787a5f5 CW |
3574 | struct drm_i915_private *dev_priv = dev->dev_private; |
3575 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3576 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3577 | struct drm_i915_gem_request *request; |
3578 | struct intel_ring_buffer *ring = NULL; | |
3579 | u32 seqno = 0; | |
3580 | int ret; | |
93533c29 | 3581 | |
1c25595f | 3582 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3583 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3584 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3585 | break; | |
40a5f0de | 3586 | |
f787a5f5 CW |
3587 | ring = request->ring; |
3588 | seqno = request->seqno; | |
b962442e | 3589 | } |
1c25595f | 3590 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3591 | |
f787a5f5 CW |
3592 | if (seqno == 0) |
3593 | return 0; | |
2bc43b5c | 3594 | |
f787a5f5 | 3595 | ret = 0; |
78501eac | 3596 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
f787a5f5 CW |
3597 | /* And wait for the seqno passing without holding any locks and |
3598 | * causing extra latency for others. This is safe as the irq | |
3599 | * generation is designed to be run atomically and so is | |
3600 | * lockless. | |
3601 | */ | |
78501eac | 3602 | ring->user_irq_get(ring); |
f787a5f5 | 3603 | ret = wait_event_interruptible(ring->irq_queue, |
78501eac | 3604 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
f787a5f5 | 3605 | || atomic_read(&dev_priv->mm.wedged)); |
78501eac | 3606 | ring->user_irq_put(ring); |
40a5f0de | 3607 | |
f787a5f5 CW |
3608 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) |
3609 | ret = -EIO; | |
40a5f0de EA |
3610 | } |
3611 | ||
f787a5f5 CW |
3612 | if (ret == 0) |
3613 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3614 | |
3615 | return ret; | |
3616 | } | |
3617 | ||
83d60795 | 3618 | static int |
2549d6c2 CW |
3619 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec, |
3620 | uint64_t exec_offset) | |
83d60795 CW |
3621 | { |
3622 | uint32_t exec_start, exec_len; | |
3623 | ||
3624 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; | |
3625 | exec_len = (uint32_t) exec->batch_len; | |
3626 | ||
3627 | if ((exec_start | exec_len) & 0x7) | |
3628 | return -EINVAL; | |
3629 | ||
3630 | if (!exec_start) | |
3631 | return -EINVAL; | |
3632 | ||
3633 | return 0; | |
3634 | } | |
3635 | ||
6b95a207 | 3636 | static int |
2549d6c2 CW |
3637 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, |
3638 | int count) | |
6b95a207 | 3639 | { |
2549d6c2 | 3640 | int i; |
6b95a207 | 3641 | |
2549d6c2 CW |
3642 | for (i = 0; i < count; i++) { |
3643 | char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr; | |
3644 | size_t length = exec[i].relocation_count * sizeof(struct drm_i915_gem_relocation_entry); | |
6b95a207 | 3645 | |
2549d6c2 CW |
3646 | if (!access_ok(VERIFY_READ, ptr, length)) |
3647 | return -EFAULT; | |
40a5f0de | 3648 | |
b5dc608c CW |
3649 | /* we may also need to update the presumed offsets */ |
3650 | if (!access_ok(VERIFY_WRITE, ptr, length)) | |
3651 | return -EFAULT; | |
3652 | ||
2549d6c2 CW |
3653 | if (fault_in_pages_readable(ptr, length)) |
3654 | return -EFAULT; | |
6b95a207 | 3655 | } |
6b95a207 | 3656 | |
83d60795 | 3657 | return 0; |
6b95a207 KH |
3658 | } |
3659 | ||
8dc5d147 | 3660 | static int |
76446cac | 3661 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, |
9af90d19 | 3662 | struct drm_file *file, |
76446cac JB |
3663 | struct drm_i915_gem_execbuffer2 *args, |
3664 | struct drm_i915_gem_exec_object2 *exec_list) | |
673a394b EA |
3665 | { |
3666 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b EA |
3667 | struct drm_gem_object **object_list = NULL; |
3668 | struct drm_gem_object *batch_obj; | |
201361a5 | 3669 | struct drm_clip_rect *cliprects = NULL; |
8dc5d147 | 3670 | struct drm_i915_gem_request *request = NULL; |
9af90d19 | 3671 | int ret, i, flips; |
673a394b | 3672 | uint64_t exec_offset; |
673a394b | 3673 | |
852835f3 ZN |
3674 | struct intel_ring_buffer *ring = NULL; |
3675 | ||
30dbf0c0 CW |
3676 | ret = i915_gem_check_is_wedged(dev); |
3677 | if (ret) | |
3678 | return ret; | |
3679 | ||
2549d6c2 CW |
3680 | ret = validate_exec_list(exec_list, args->buffer_count); |
3681 | if (ret) | |
3682 | return ret; | |
3683 | ||
673a394b EA |
3684 | #if WATCH_EXEC |
3685 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
3686 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
3687 | #endif | |
549f7365 CW |
3688 | switch (args->flags & I915_EXEC_RING_MASK) { |
3689 | case I915_EXEC_DEFAULT: | |
3690 | case I915_EXEC_RENDER: | |
3691 | ring = &dev_priv->render_ring; | |
3692 | break; | |
3693 | case I915_EXEC_BSD: | |
d1b851fc | 3694 | if (!HAS_BSD(dev)) { |
549f7365 | 3695 | DRM_ERROR("execbuf with invalid ring (BSD)\n"); |
d1b851fc ZN |
3696 | return -EINVAL; |
3697 | } | |
3698 | ring = &dev_priv->bsd_ring; | |
549f7365 CW |
3699 | break; |
3700 | case I915_EXEC_BLT: | |
3701 | if (!HAS_BLT(dev)) { | |
3702 | DRM_ERROR("execbuf with invalid ring (BLT)\n"); | |
3703 | return -EINVAL; | |
3704 | } | |
3705 | ring = &dev_priv->blt_ring; | |
3706 | break; | |
3707 | default: | |
3708 | DRM_ERROR("execbuf with unknown ring: %d\n", | |
3709 | (int)(args->flags & I915_EXEC_RING_MASK)); | |
3710 | return -EINVAL; | |
d1b851fc ZN |
3711 | } |
3712 | ||
4f481ed2 EA |
3713 | if (args->buffer_count < 1) { |
3714 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
3715 | return -EINVAL; | |
3716 | } | |
c8e0f93a | 3717 | object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count); |
76446cac JB |
3718 | if (object_list == NULL) { |
3719 | DRM_ERROR("Failed to allocate object list for %d buffers\n", | |
673a394b EA |
3720 | args->buffer_count); |
3721 | ret = -ENOMEM; | |
3722 | goto pre_mutex_err; | |
3723 | } | |
673a394b | 3724 | |
201361a5 | 3725 | if (args->num_cliprects != 0) { |
9a298b2a EA |
3726 | cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects), |
3727 | GFP_KERNEL); | |
a40e8d31 OA |
3728 | if (cliprects == NULL) { |
3729 | ret = -ENOMEM; | |
201361a5 | 3730 | goto pre_mutex_err; |
a40e8d31 | 3731 | } |
201361a5 EA |
3732 | |
3733 | ret = copy_from_user(cliprects, | |
3734 | (struct drm_clip_rect __user *) | |
3735 | (uintptr_t) args->cliprects_ptr, | |
3736 | sizeof(*cliprects) * args->num_cliprects); | |
3737 | if (ret != 0) { | |
3738 | DRM_ERROR("copy %d cliprects failed: %d\n", | |
3739 | args->num_cliprects, ret); | |
c877cdce | 3740 | ret = -EFAULT; |
201361a5 EA |
3741 | goto pre_mutex_err; |
3742 | } | |
3743 | } | |
3744 | ||
8dc5d147 CW |
3745 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
3746 | if (request == NULL) { | |
3747 | ret = -ENOMEM; | |
40a5f0de | 3748 | goto pre_mutex_err; |
8dc5d147 | 3749 | } |
40a5f0de | 3750 | |
76c1dec1 CW |
3751 | ret = i915_mutex_lock_interruptible(dev); |
3752 | if (ret) | |
a198bc80 | 3753 | goto pre_mutex_err; |
673a394b EA |
3754 | |
3755 | if (dev_priv->mm.suspended) { | |
673a394b | 3756 | mutex_unlock(&dev->struct_mutex); |
a198bc80 CW |
3757 | ret = -EBUSY; |
3758 | goto pre_mutex_err; | |
673a394b EA |
3759 | } |
3760 | ||
ac94a962 | 3761 | /* Look up object handles */ |
673a394b | 3762 | for (i = 0; i < args->buffer_count; i++) { |
7e318e18 CW |
3763 | struct drm_i915_gem_object *obj_priv; |
3764 | ||
9af90d19 | 3765 | object_list[i] = drm_gem_object_lookup(dev, file, |
673a394b EA |
3766 | exec_list[i].handle); |
3767 | if (object_list[i] == NULL) { | |
3768 | DRM_ERROR("Invalid object handle %d at index %d\n", | |
3769 | exec_list[i].handle, i); | |
0ce907f8 CW |
3770 | /* prevent error path from reading uninitialized data */ |
3771 | args->buffer_count = i + 1; | |
bf79cb91 | 3772 | ret = -ENOENT; |
673a394b EA |
3773 | goto err; |
3774 | } | |
b70d11da | 3775 | |
23010e43 | 3776 | obj_priv = to_intel_bo(object_list[i]); |
b70d11da KH |
3777 | if (obj_priv->in_execbuffer) { |
3778 | DRM_ERROR("Object %p appears more than once in object list\n", | |
3779 | object_list[i]); | |
0ce907f8 CW |
3780 | /* prevent error path from reading uninitialized data */ |
3781 | args->buffer_count = i + 1; | |
bf79cb91 | 3782 | ret = -EINVAL; |
b70d11da KH |
3783 | goto err; |
3784 | } | |
3785 | obj_priv->in_execbuffer = true; | |
ac94a962 | 3786 | } |
673a394b | 3787 | |
9af90d19 CW |
3788 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
3789 | ret = i915_gem_execbuffer_pin(dev, file, | |
3790 | object_list, exec_list, | |
3791 | args->buffer_count); | |
3792 | if (ret) | |
3793 | goto err; | |
ac94a962 | 3794 | |
9af90d19 CW |
3795 | /* The objects are in their final locations, apply the relocations. */ |
3796 | for (i = 0; i < args->buffer_count; i++) { | |
3797 | struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]); | |
3798 | obj->base.pending_read_domains = 0; | |
3799 | obj->base.pending_write_domain = 0; | |
3800 | ret = i915_gem_execbuffer_relocate(obj, file, &exec_list[i]); | |
3801 | if (ret) | |
ac94a962 | 3802 | goto err; |
673a394b EA |
3803 | } |
3804 | ||
3805 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
3806 | batch_obj = object_list[args->buffer_count-1]; | |
5f26a2c7 CW |
3807 | if (batch_obj->pending_write_domain) { |
3808 | DRM_ERROR("Attempting to use self-modifying batch buffer\n"); | |
3809 | ret = -EINVAL; | |
3810 | goto err; | |
3811 | } | |
3812 | batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
673a394b | 3813 | |
9af90d19 CW |
3814 | /* Sanity check the batch buffer */ |
3815 | exec_offset = to_intel_bo(batch_obj)->gtt_offset; | |
3816 | ret = i915_gem_check_execbuffer(args, exec_offset); | |
83d60795 CW |
3817 | if (ret != 0) { |
3818 | DRM_ERROR("execbuf with invalid offset/length\n"); | |
3819 | goto err; | |
3820 | } | |
3821 | ||
646f0f6e KP |
3822 | /* Zero the global flush/invalidate flags. These |
3823 | * will be modified as new domains are computed | |
3824 | * for each object | |
3825 | */ | |
3826 | dev->invalidate_domains = 0; | |
3827 | dev->flush_domains = 0; | |
9220434a | 3828 | dev_priv->mm.flush_rings = 0; |
7e318e18 CW |
3829 | for (i = 0; i < args->buffer_count; i++) |
3830 | i915_gem_object_set_to_gpu_domain(object_list[i], ring); | |
673a394b | 3831 | |
646f0f6e KP |
3832 | if (dev->invalidate_domains | dev->flush_domains) { |
3833 | #if WATCH_EXEC | |
3834 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", | |
3835 | __func__, | |
3836 | dev->invalidate_domains, | |
3837 | dev->flush_domains); | |
3838 | #endif | |
9af90d19 | 3839 | i915_gem_flush(dev, file, |
646f0f6e | 3840 | dev->invalidate_domains, |
9220434a CW |
3841 | dev->flush_domains, |
3842 | dev_priv->mm.flush_rings); | |
646f0f6e | 3843 | } |
673a394b | 3844 | |
673a394b EA |
3845 | #if WATCH_COHERENCY |
3846 | for (i = 0; i < args->buffer_count; i++) { | |
3847 | i915_gem_object_check_coherency(object_list[i], | |
3848 | exec_list[i].handle); | |
3849 | } | |
3850 | #endif | |
3851 | ||
673a394b | 3852 | #if WATCH_EXEC |
6911a9b8 | 3853 | i915_gem_dump_object(batch_obj, |
673a394b EA |
3854 | args->batch_len, |
3855 | __func__, | |
3856 | ~0); | |
3857 | #endif | |
3858 | ||
e59f2bac CW |
3859 | /* Check for any pending flips. As we only maintain a flip queue depth |
3860 | * of 1, we can simply insert a WAIT for the next display flip prior | |
3861 | * to executing the batch and avoid stalling the CPU. | |
3862 | */ | |
3863 | flips = 0; | |
3864 | for (i = 0; i < args->buffer_count; i++) { | |
3865 | if (object_list[i]->write_domain) | |
3866 | flips |= atomic_read(&to_intel_bo(object_list[i])->pending_flip); | |
3867 | } | |
3868 | if (flips) { | |
3869 | int plane, flip_mask; | |
3870 | ||
3871 | for (plane = 0; flips >> plane; plane++) { | |
3872 | if (((flips >> plane) & 1) == 0) | |
3873 | continue; | |
3874 | ||
3875 | if (plane) | |
3876 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
3877 | else | |
3878 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
3879 | ||
e1f99ce6 CW |
3880 | ret = intel_ring_begin(ring, 2); |
3881 | if (ret) | |
3882 | goto err; | |
3883 | ||
78501eac CW |
3884 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
3885 | intel_ring_emit(ring, MI_NOOP); | |
3886 | intel_ring_advance(ring); | |
e59f2bac CW |
3887 | } |
3888 | } | |
3889 | ||
673a394b | 3890 | /* Exec the batchbuffer */ |
78501eac | 3891 | ret = ring->dispatch_execbuffer(ring, args, cliprects, exec_offset); |
673a394b EA |
3892 | if (ret) { |
3893 | DRM_ERROR("dispatch failed %d\n", ret); | |
3894 | goto err; | |
3895 | } | |
3896 | ||
673a394b EA |
3897 | for (i = 0; i < args->buffer_count; i++) { |
3898 | struct drm_gem_object *obj = object_list[i]; | |
673a394b | 3899 | |
7e318e18 CW |
3900 | obj->read_domains = obj->pending_read_domains; |
3901 | obj->write_domain = obj->pending_write_domain; | |
3902 | ||
617dbe27 | 3903 | i915_gem_object_move_to_active(obj, ring); |
7e318e18 CW |
3904 | if (obj->write_domain) { |
3905 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
3906 | obj_priv->dirty = 1; | |
3907 | list_move_tail(&obj_priv->gpu_write_list, | |
64193406 | 3908 | &ring->gpu_write_list); |
7e318e18 CW |
3909 | intel_mark_busy(dev, obj); |
3910 | } | |
3911 | ||
3912 | trace_i915_gem_object_change_domain(obj, | |
3913 | obj->read_domains, | |
3914 | obj->write_domain); | |
673a394b | 3915 | } |
673a394b | 3916 | |
7e318e18 CW |
3917 | /* |
3918 | * Ensure that the commands in the batch buffer are | |
3919 | * finished before the interrupt fires | |
3920 | */ | |
3921 | i915_retire_commands(dev, ring); | |
3922 | ||
3cce469c CW |
3923 | if (i915_add_request(dev, file, request, ring)) |
3924 | ring->outstanding_lazy_request = true; | |
3925 | else | |
3926 | request = NULL; | |
673a394b | 3927 | |
673a394b | 3928 | err: |
b70d11da | 3929 | for (i = 0; i < args->buffer_count; i++) { |
7e318e18 CW |
3930 | if (object_list[i] == NULL) |
3931 | break; | |
3932 | ||
3933 | to_intel_bo(object_list[i])->in_execbuffer = false; | |
aad87dff | 3934 | drm_gem_object_unreference(object_list[i]); |
b70d11da | 3935 | } |
673a394b | 3936 | |
673a394b EA |
3937 | mutex_unlock(&dev->struct_mutex); |
3938 | ||
93533c29 | 3939 | pre_mutex_err: |
8e7d2b2c | 3940 | drm_free_large(object_list); |
9a298b2a | 3941 | kfree(cliprects); |
8dc5d147 | 3942 | kfree(request); |
673a394b EA |
3943 | |
3944 | return ret; | |
3945 | } | |
3946 | ||
76446cac JB |
3947 | /* |
3948 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
3949 | * list array and passes it to the real function. | |
3950 | */ | |
3951 | int | |
3952 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
3953 | struct drm_file *file_priv) | |
3954 | { | |
3955 | struct drm_i915_gem_execbuffer *args = data; | |
3956 | struct drm_i915_gem_execbuffer2 exec2; | |
3957 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
3958 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
3959 | int ret, i; | |
3960 | ||
3961 | #if WATCH_EXEC | |
3962 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
3963 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
3964 | #endif | |
3965 | ||
3966 | if (args->buffer_count < 1) { | |
3967 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
3968 | return -EINVAL; | |
3969 | } | |
3970 | ||
3971 | /* Copy in the exec list from userland */ | |
3972 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
3973 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
3974 | if (exec_list == NULL || exec2_list == NULL) { | |
3975 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
3976 | args->buffer_count); | |
3977 | drm_free_large(exec_list); | |
3978 | drm_free_large(exec2_list); | |
3979 | return -ENOMEM; | |
3980 | } | |
3981 | ret = copy_from_user(exec_list, | |
3982 | (struct drm_i915_relocation_entry __user *) | |
3983 | (uintptr_t) args->buffers_ptr, | |
3984 | sizeof(*exec_list) * args->buffer_count); | |
3985 | if (ret != 0) { | |
3986 | DRM_ERROR("copy %d exec entries failed %d\n", | |
3987 | args->buffer_count, ret); | |
3988 | drm_free_large(exec_list); | |
3989 | drm_free_large(exec2_list); | |
3990 | return -EFAULT; | |
3991 | } | |
3992 | ||
3993 | for (i = 0; i < args->buffer_count; i++) { | |
3994 | exec2_list[i].handle = exec_list[i].handle; | |
3995 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
3996 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
3997 | exec2_list[i].alignment = exec_list[i].alignment; | |
3998 | exec2_list[i].offset = exec_list[i].offset; | |
a6c45cf0 | 3999 | if (INTEL_INFO(dev)->gen < 4) |
76446cac JB |
4000 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; |
4001 | else | |
4002 | exec2_list[i].flags = 0; | |
4003 | } | |
4004 | ||
4005 | exec2.buffers_ptr = args->buffers_ptr; | |
4006 | exec2.buffer_count = args->buffer_count; | |
4007 | exec2.batch_start_offset = args->batch_start_offset; | |
4008 | exec2.batch_len = args->batch_len; | |
4009 | exec2.DR1 = args->DR1; | |
4010 | exec2.DR4 = args->DR4; | |
4011 | exec2.num_cliprects = args->num_cliprects; | |
4012 | exec2.cliprects_ptr = args->cliprects_ptr; | |
852835f3 | 4013 | exec2.flags = I915_EXEC_RENDER; |
76446cac JB |
4014 | |
4015 | ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list); | |
4016 | if (!ret) { | |
4017 | /* Copy the new buffer offsets back to the user's exec list. */ | |
4018 | for (i = 0; i < args->buffer_count; i++) | |
4019 | exec_list[i].offset = exec2_list[i].offset; | |
4020 | /* ... and back out to userspace */ | |
4021 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
4022 | (uintptr_t) args->buffers_ptr, | |
4023 | exec_list, | |
4024 | sizeof(*exec_list) * args->buffer_count); | |
4025 | if (ret) { | |
4026 | ret = -EFAULT; | |
4027 | DRM_ERROR("failed to copy %d exec entries " | |
4028 | "back to user (%d)\n", | |
4029 | args->buffer_count, ret); | |
4030 | } | |
76446cac JB |
4031 | } |
4032 | ||
4033 | drm_free_large(exec_list); | |
4034 | drm_free_large(exec2_list); | |
4035 | return ret; | |
4036 | } | |
4037 | ||
4038 | int | |
4039 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
4040 | struct drm_file *file_priv) | |
4041 | { | |
4042 | struct drm_i915_gem_execbuffer2 *args = data; | |
4043 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
4044 | int ret; | |
4045 | ||
4046 | #if WATCH_EXEC | |
4047 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
4048 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
4049 | #endif | |
4050 | ||
4051 | if (args->buffer_count < 1) { | |
4052 | DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count); | |
4053 | return -EINVAL; | |
4054 | } | |
4055 | ||
4056 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
4057 | if (exec2_list == NULL) { | |
4058 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
4059 | args->buffer_count); | |
4060 | return -ENOMEM; | |
4061 | } | |
4062 | ret = copy_from_user(exec2_list, | |
4063 | (struct drm_i915_relocation_entry __user *) | |
4064 | (uintptr_t) args->buffers_ptr, | |
4065 | sizeof(*exec2_list) * args->buffer_count); | |
4066 | if (ret != 0) { | |
4067 | DRM_ERROR("copy %d exec entries failed %d\n", | |
4068 | args->buffer_count, ret); | |
4069 | drm_free_large(exec2_list); | |
4070 | return -EFAULT; | |
4071 | } | |
4072 | ||
4073 | ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list); | |
4074 | if (!ret) { | |
4075 | /* Copy the new buffer offsets back to the user's exec list. */ | |
4076 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
4077 | (uintptr_t) args->buffers_ptr, | |
4078 | exec2_list, | |
4079 | sizeof(*exec2_list) * args->buffer_count); | |
4080 | if (ret) { | |
4081 | ret = -EFAULT; | |
4082 | DRM_ERROR("failed to copy %d exec entries " | |
4083 | "back to user (%d)\n", | |
4084 | args->buffer_count, ret); | |
4085 | } | |
4086 | } | |
4087 | ||
4088 | drm_free_large(exec2_list); | |
4089 | return ret; | |
4090 | } | |
4091 | ||
673a394b | 4092 | int |
920afa77 DV |
4093 | i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment, |
4094 | bool mappable) | |
673a394b EA |
4095 | { |
4096 | struct drm_device *dev = obj->dev; | |
f13d3f73 | 4097 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 4098 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
4099 | int ret; |
4100 | ||
778c3544 | 4101 | BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
23bc5982 | 4102 | WARN_ON(i915_verify_lists(dev)); |
ac0c6b5a CW |
4103 | |
4104 | if (obj_priv->gtt_space != NULL) { | |
4105 | if (alignment == 0) | |
4106 | alignment = i915_gem_get_gtt_alignment(obj); | |
16e809ac DV |
4107 | if (obj_priv->gtt_offset & (alignment - 1) || |
4108 | (mappable && !i915_gem_object_cpu_accessible(obj_priv))) { | |
ae7d49d8 CW |
4109 | WARN(obj_priv->pin_count, |
4110 | "bo is already pinned with incorrect alignment:" | |
4111 | " offset=%x, req.alignment=%x\n", | |
4112 | obj_priv->gtt_offset, alignment); | |
ac0c6b5a CW |
4113 | ret = i915_gem_object_unbind(obj); |
4114 | if (ret) | |
4115 | return ret; | |
4116 | } | |
4117 | } | |
4118 | ||
673a394b | 4119 | if (obj_priv->gtt_space == NULL) { |
920afa77 | 4120 | ret = i915_gem_object_bind_to_gtt(obj, alignment, mappable); |
9731129c | 4121 | if (ret) |
673a394b | 4122 | return ret; |
22c344e9 | 4123 | } |
76446cac | 4124 | |
673a394b EA |
4125 | obj_priv->pin_count++; |
4126 | ||
4127 | /* If the object is not active and not pending a flush, | |
4128 | * remove it from the inactive list | |
4129 | */ | |
4130 | if (obj_priv->pin_count == 1) { | |
fb7d516a | 4131 | i915_gem_info_add_pin(dev_priv, obj, mappable); |
f13d3f73 | 4132 | if (!obj_priv->active) |
69dc4987 | 4133 | list_move_tail(&obj_priv->mm_list, |
f13d3f73 | 4134 | &dev_priv->mm.pinned_list); |
673a394b | 4135 | } |
fb7d516a | 4136 | BUG_ON(!obj_priv->pin_mappable && mappable); |
673a394b | 4137 | |
23bc5982 | 4138 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4139 | return 0; |
4140 | } | |
4141 | ||
4142 | void | |
4143 | i915_gem_object_unpin(struct drm_gem_object *obj) | |
4144 | { | |
4145 | struct drm_device *dev = obj->dev; | |
4146 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 4147 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 4148 | |
23bc5982 | 4149 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4150 | obj_priv->pin_count--; |
4151 | BUG_ON(obj_priv->pin_count < 0); | |
4152 | BUG_ON(obj_priv->gtt_space == NULL); | |
4153 | ||
4154 | /* If the object is no longer pinned, and is | |
4155 | * neither active nor being flushed, then stick it on | |
4156 | * the inactive list | |
4157 | */ | |
4158 | if (obj_priv->pin_count == 0) { | |
f13d3f73 | 4159 | if (!obj_priv->active) |
69dc4987 | 4160 | list_move_tail(&obj_priv->mm_list, |
673a394b | 4161 | &dev_priv->mm.inactive_list); |
fb7d516a | 4162 | i915_gem_info_remove_pin(dev_priv, obj); |
673a394b | 4163 | } |
23bc5982 | 4164 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4165 | } |
4166 | ||
4167 | int | |
4168 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
4169 | struct drm_file *file_priv) | |
4170 | { | |
4171 | struct drm_i915_gem_pin *args = data; | |
4172 | struct drm_gem_object *obj; | |
4173 | struct drm_i915_gem_object *obj_priv; | |
4174 | int ret; | |
4175 | ||
1d7cfea1 CW |
4176 | ret = i915_mutex_lock_interruptible(dev); |
4177 | if (ret) | |
4178 | return ret; | |
673a394b EA |
4179 | |
4180 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4181 | if (obj == NULL) { | |
1d7cfea1 CW |
4182 | ret = -ENOENT; |
4183 | goto unlock; | |
673a394b | 4184 | } |
23010e43 | 4185 | obj_priv = to_intel_bo(obj); |
673a394b | 4186 | |
bb6baf76 CW |
4187 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
4188 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); | |
1d7cfea1 CW |
4189 | ret = -EINVAL; |
4190 | goto out; | |
3ef94daa CW |
4191 | } |
4192 | ||
79e53945 JB |
4193 | if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) { |
4194 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", | |
4195 | args->handle); | |
1d7cfea1 CW |
4196 | ret = -EINVAL; |
4197 | goto out; | |
79e53945 JB |
4198 | } |
4199 | ||
4200 | obj_priv->user_pin_count++; | |
4201 | obj_priv->pin_filp = file_priv; | |
4202 | if (obj_priv->user_pin_count == 1) { | |
920afa77 | 4203 | ret = i915_gem_object_pin(obj, args->alignment, true); |
1d7cfea1 CW |
4204 | if (ret) |
4205 | goto out; | |
673a394b EA |
4206 | } |
4207 | ||
4208 | /* XXX - flush the CPU caches for pinned objects | |
4209 | * as the X server doesn't manage domains yet | |
4210 | */ | |
e47c68e9 | 4211 | i915_gem_object_flush_cpu_write_domain(obj); |
673a394b | 4212 | args->offset = obj_priv->gtt_offset; |
1d7cfea1 | 4213 | out: |
673a394b | 4214 | drm_gem_object_unreference(obj); |
1d7cfea1 | 4215 | unlock: |
673a394b | 4216 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4217 | return ret; |
673a394b EA |
4218 | } |
4219 | ||
4220 | int | |
4221 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
4222 | struct drm_file *file_priv) | |
4223 | { | |
4224 | struct drm_i915_gem_pin *args = data; | |
4225 | struct drm_gem_object *obj; | |
79e53945 | 4226 | struct drm_i915_gem_object *obj_priv; |
76c1dec1 | 4227 | int ret; |
673a394b | 4228 | |
1d7cfea1 CW |
4229 | ret = i915_mutex_lock_interruptible(dev); |
4230 | if (ret) | |
4231 | return ret; | |
673a394b EA |
4232 | |
4233 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4234 | if (obj == NULL) { | |
1d7cfea1 CW |
4235 | ret = -ENOENT; |
4236 | goto unlock; | |
673a394b | 4237 | } |
23010e43 | 4238 | obj_priv = to_intel_bo(obj); |
76c1dec1 | 4239 | |
79e53945 JB |
4240 | if (obj_priv->pin_filp != file_priv) { |
4241 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", | |
4242 | args->handle); | |
1d7cfea1 CW |
4243 | ret = -EINVAL; |
4244 | goto out; | |
79e53945 JB |
4245 | } |
4246 | obj_priv->user_pin_count--; | |
4247 | if (obj_priv->user_pin_count == 0) { | |
4248 | obj_priv->pin_filp = NULL; | |
4249 | i915_gem_object_unpin(obj); | |
4250 | } | |
673a394b | 4251 | |
1d7cfea1 | 4252 | out: |
673a394b | 4253 | drm_gem_object_unreference(obj); |
1d7cfea1 | 4254 | unlock: |
673a394b | 4255 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4256 | return ret; |
673a394b EA |
4257 | } |
4258 | ||
4259 | int | |
4260 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
4261 | struct drm_file *file_priv) | |
4262 | { | |
4263 | struct drm_i915_gem_busy *args = data; | |
4264 | struct drm_gem_object *obj; | |
4265 | struct drm_i915_gem_object *obj_priv; | |
30dbf0c0 CW |
4266 | int ret; |
4267 | ||
76c1dec1 | 4268 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 4269 | if (ret) |
76c1dec1 | 4270 | return ret; |
673a394b | 4271 | |
673a394b EA |
4272 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
4273 | if (obj == NULL) { | |
1d7cfea1 CW |
4274 | ret = -ENOENT; |
4275 | goto unlock; | |
673a394b | 4276 | } |
1d7cfea1 | 4277 | obj_priv = to_intel_bo(obj); |
d1b851fc | 4278 | |
0be555b6 CW |
4279 | /* Count all active objects as busy, even if they are currently not used |
4280 | * by the gpu. Users of this interface expect objects to eventually | |
4281 | * become non-busy without any further actions, therefore emit any | |
4282 | * necessary flushes here. | |
c4de0a5d | 4283 | */ |
0be555b6 CW |
4284 | args->busy = obj_priv->active; |
4285 | if (args->busy) { | |
4286 | /* Unconditionally flush objects, even when the gpu still uses this | |
4287 | * object. Userspace calling this function indicates that it wants to | |
4288 | * use this buffer rather sooner than later, so issuing the required | |
4289 | * flush earlier is beneficial. | |
4290 | */ | |
c78ec30b CW |
4291 | if (obj->write_domain & I915_GEM_GPU_DOMAINS) |
4292 | i915_gem_flush_ring(dev, file_priv, | |
9220434a CW |
4293 | obj_priv->ring, |
4294 | 0, obj->write_domain); | |
0be555b6 CW |
4295 | |
4296 | /* Update the active list for the hardware's current position. | |
4297 | * Otherwise this only updates on a delayed timer or when irqs | |
4298 | * are actually unmasked, and our working set ends up being | |
4299 | * larger than required. | |
4300 | */ | |
4301 | i915_gem_retire_requests_ring(dev, obj_priv->ring); | |
4302 | ||
4303 | args->busy = obj_priv->active; | |
4304 | } | |
673a394b EA |
4305 | |
4306 | drm_gem_object_unreference(obj); | |
1d7cfea1 | 4307 | unlock: |
673a394b | 4308 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4309 | return ret; |
673a394b EA |
4310 | } |
4311 | ||
4312 | int | |
4313 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4314 | struct drm_file *file_priv) | |
4315 | { | |
4316 | return i915_gem_ring_throttle(dev, file_priv); | |
4317 | } | |
4318 | ||
3ef94daa CW |
4319 | int |
4320 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4321 | struct drm_file *file_priv) | |
4322 | { | |
4323 | struct drm_i915_gem_madvise *args = data; | |
4324 | struct drm_gem_object *obj; | |
4325 | struct drm_i915_gem_object *obj_priv; | |
76c1dec1 | 4326 | int ret; |
3ef94daa CW |
4327 | |
4328 | switch (args->madv) { | |
4329 | case I915_MADV_DONTNEED: | |
4330 | case I915_MADV_WILLNEED: | |
4331 | break; | |
4332 | default: | |
4333 | return -EINVAL; | |
4334 | } | |
4335 | ||
1d7cfea1 CW |
4336 | ret = i915_mutex_lock_interruptible(dev); |
4337 | if (ret) | |
4338 | return ret; | |
4339 | ||
3ef94daa CW |
4340 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
4341 | if (obj == NULL) { | |
1d7cfea1 CW |
4342 | ret = -ENOENT; |
4343 | goto unlock; | |
3ef94daa | 4344 | } |
23010e43 | 4345 | obj_priv = to_intel_bo(obj); |
3ef94daa CW |
4346 | |
4347 | if (obj_priv->pin_count) { | |
1d7cfea1 CW |
4348 | ret = -EINVAL; |
4349 | goto out; | |
3ef94daa CW |
4350 | } |
4351 | ||
bb6baf76 CW |
4352 | if (obj_priv->madv != __I915_MADV_PURGED) |
4353 | obj_priv->madv = args->madv; | |
3ef94daa | 4354 | |
2d7ef395 CW |
4355 | /* if the object is no longer bound, discard its backing storage */ |
4356 | if (i915_gem_object_is_purgeable(obj_priv) && | |
4357 | obj_priv->gtt_space == NULL) | |
4358 | i915_gem_object_truncate(obj); | |
4359 | ||
bb6baf76 CW |
4360 | args->retained = obj_priv->madv != __I915_MADV_PURGED; |
4361 | ||
1d7cfea1 | 4362 | out: |
3ef94daa | 4363 | drm_gem_object_unreference(obj); |
1d7cfea1 | 4364 | unlock: |
3ef94daa | 4365 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4366 | return ret; |
3ef94daa CW |
4367 | } |
4368 | ||
ac52bc56 DV |
4369 | struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev, |
4370 | size_t size) | |
4371 | { | |
73aa808f | 4372 | struct drm_i915_private *dev_priv = dev->dev_private; |
c397b908 | 4373 | struct drm_i915_gem_object *obj; |
ac52bc56 | 4374 | |
c397b908 DV |
4375 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
4376 | if (obj == NULL) | |
4377 | return NULL; | |
673a394b | 4378 | |
c397b908 DV |
4379 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
4380 | kfree(obj); | |
4381 | return NULL; | |
4382 | } | |
673a394b | 4383 | |
73aa808f CW |
4384 | i915_gem_info_add_obj(dev_priv, size); |
4385 | ||
c397b908 DV |
4386 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4387 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4388 | |
c397b908 | 4389 | obj->agp_type = AGP_USER_MEMORY; |
62b8b215 | 4390 | obj->base.driver_private = NULL; |
c397b908 | 4391 | obj->fence_reg = I915_FENCE_REG_NONE; |
69dc4987 CW |
4392 | INIT_LIST_HEAD(&obj->mm_list); |
4393 | INIT_LIST_HEAD(&obj->ring_list); | |
c397b908 | 4394 | INIT_LIST_HEAD(&obj->gpu_write_list); |
c397b908 | 4395 | obj->madv = I915_MADV_WILLNEED; |
de151cf6 | 4396 | |
c397b908 DV |
4397 | return &obj->base; |
4398 | } | |
4399 | ||
4400 | int i915_gem_init_object(struct drm_gem_object *obj) | |
4401 | { | |
4402 | BUG(); | |
de151cf6 | 4403 | |
673a394b EA |
4404 | return 0; |
4405 | } | |
4406 | ||
be72615b | 4407 | static void i915_gem_free_object_tail(struct drm_gem_object *obj) |
673a394b | 4408 | { |
de151cf6 | 4409 | struct drm_device *dev = obj->dev; |
be72615b | 4410 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 4411 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
be72615b | 4412 | int ret; |
673a394b | 4413 | |
be72615b CW |
4414 | ret = i915_gem_object_unbind(obj); |
4415 | if (ret == -ERESTARTSYS) { | |
69dc4987 | 4416 | list_move(&obj_priv->mm_list, |
be72615b CW |
4417 | &dev_priv->mm.deferred_free_list); |
4418 | return; | |
4419 | } | |
673a394b | 4420 | |
39a01d1f | 4421 | if (obj->map_list.map) |
7e616158 | 4422 | i915_gem_free_mmap_offset(obj); |
de151cf6 | 4423 | |
c397b908 | 4424 | drm_gem_object_release(obj); |
73aa808f | 4425 | i915_gem_info_remove_obj(dev_priv, obj->size); |
c397b908 | 4426 | |
9a298b2a | 4427 | kfree(obj_priv->page_cpu_valid); |
280b713b | 4428 | kfree(obj_priv->bit_17); |
c397b908 | 4429 | kfree(obj_priv); |
673a394b EA |
4430 | } |
4431 | ||
be72615b CW |
4432 | void i915_gem_free_object(struct drm_gem_object *obj) |
4433 | { | |
4434 | struct drm_device *dev = obj->dev; | |
4435 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
4436 | ||
4437 | trace_i915_gem_object_destroy(obj); | |
4438 | ||
4439 | while (obj_priv->pin_count > 0) | |
4440 | i915_gem_object_unpin(obj); | |
4441 | ||
4442 | if (obj_priv->phys_obj) | |
4443 | i915_gem_detach_phys_object(dev, obj); | |
4444 | ||
4445 | i915_gem_free_object_tail(obj); | |
4446 | } | |
4447 | ||
29105ccc CW |
4448 | int |
4449 | i915_gem_idle(struct drm_device *dev) | |
4450 | { | |
4451 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4452 | int ret; | |
28dfe52a | 4453 | |
29105ccc | 4454 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 4455 | |
87acb0a5 | 4456 | if (dev_priv->mm.suspended) { |
29105ccc CW |
4457 | mutex_unlock(&dev->struct_mutex); |
4458 | return 0; | |
28dfe52a EA |
4459 | } |
4460 | ||
29105ccc | 4461 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
4462 | if (ret) { |
4463 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 4464 | return ret; |
6dbe2772 | 4465 | } |
673a394b | 4466 | |
29105ccc CW |
4467 | /* Under UMS, be paranoid and evict. */ |
4468 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { | |
b47eb4a2 | 4469 | ret = i915_gem_evict_inactive(dev); |
29105ccc CW |
4470 | if (ret) { |
4471 | mutex_unlock(&dev->struct_mutex); | |
4472 | return ret; | |
4473 | } | |
4474 | } | |
4475 | ||
4476 | /* Hack! Don't let anybody do execbuf while we don't control the chip. | |
4477 | * We need to replace this with a semaphore, or something. | |
4478 | * And not confound mm.suspended! | |
4479 | */ | |
4480 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 4481 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
4482 | |
4483 | i915_kernel_lost_context(dev); | |
6dbe2772 | 4484 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 4485 | |
6dbe2772 KP |
4486 | mutex_unlock(&dev->struct_mutex); |
4487 | ||
29105ccc CW |
4488 | /* Cancel the retire work handler, which should be idle now. */ |
4489 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
4490 | ||
673a394b EA |
4491 | return 0; |
4492 | } | |
4493 | ||
e552eb70 JB |
4494 | /* |
4495 | * 965+ support PIPE_CONTROL commands, which provide finer grained control | |
4496 | * over cache flushing. | |
4497 | */ | |
8187a2b7 | 4498 | static int |
e552eb70 JB |
4499 | i915_gem_init_pipe_control(struct drm_device *dev) |
4500 | { | |
4501 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4502 | struct drm_gem_object *obj; | |
4503 | struct drm_i915_gem_object *obj_priv; | |
4504 | int ret; | |
4505 | ||
34dc4d44 | 4506 | obj = i915_gem_alloc_object(dev, 4096); |
e552eb70 JB |
4507 | if (obj == NULL) { |
4508 | DRM_ERROR("Failed to allocate seqno page\n"); | |
4509 | ret = -ENOMEM; | |
4510 | goto err; | |
4511 | } | |
4512 | obj_priv = to_intel_bo(obj); | |
4513 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; | |
4514 | ||
920afa77 | 4515 | ret = i915_gem_object_pin(obj, 4096, true); |
e552eb70 JB |
4516 | if (ret) |
4517 | goto err_unref; | |
4518 | ||
4519 | dev_priv->seqno_gfx_addr = obj_priv->gtt_offset; | |
4520 | dev_priv->seqno_page = kmap(obj_priv->pages[0]); | |
4521 | if (dev_priv->seqno_page == NULL) | |
4522 | goto err_unpin; | |
4523 | ||
4524 | dev_priv->seqno_obj = obj; | |
4525 | memset(dev_priv->seqno_page, 0, PAGE_SIZE); | |
4526 | ||
4527 | return 0; | |
4528 | ||
4529 | err_unpin: | |
4530 | i915_gem_object_unpin(obj); | |
4531 | err_unref: | |
4532 | drm_gem_object_unreference(obj); | |
4533 | err: | |
4534 | return ret; | |
4535 | } | |
4536 | ||
8187a2b7 ZN |
4537 | |
4538 | static void | |
e552eb70 JB |
4539 | i915_gem_cleanup_pipe_control(struct drm_device *dev) |
4540 | { | |
4541 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4542 | struct drm_gem_object *obj; | |
4543 | struct drm_i915_gem_object *obj_priv; | |
4544 | ||
4545 | obj = dev_priv->seqno_obj; | |
4546 | obj_priv = to_intel_bo(obj); | |
4547 | kunmap(obj_priv->pages[0]); | |
4548 | i915_gem_object_unpin(obj); | |
4549 | drm_gem_object_unreference(obj); | |
4550 | dev_priv->seqno_obj = NULL; | |
4551 | ||
4552 | dev_priv->seqno_page = NULL; | |
673a394b EA |
4553 | } |
4554 | ||
8187a2b7 ZN |
4555 | int |
4556 | i915_gem_init_ringbuffer(struct drm_device *dev) | |
4557 | { | |
4558 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4559 | int ret; | |
68f95ba9 | 4560 | |
8187a2b7 ZN |
4561 | if (HAS_PIPE_CONTROL(dev)) { |
4562 | ret = i915_gem_init_pipe_control(dev); | |
4563 | if (ret) | |
4564 | return ret; | |
4565 | } | |
68f95ba9 | 4566 | |
5c1143bb | 4567 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 CW |
4568 | if (ret) |
4569 | goto cleanup_pipe_control; | |
4570 | ||
4571 | if (HAS_BSD(dev)) { | |
5c1143bb | 4572 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4573 | if (ret) |
4574 | goto cleanup_render_ring; | |
d1b851fc | 4575 | } |
68f95ba9 | 4576 | |
549f7365 CW |
4577 | if (HAS_BLT(dev)) { |
4578 | ret = intel_init_blt_ring_buffer(dev); | |
4579 | if (ret) | |
4580 | goto cleanup_bsd_ring; | |
4581 | } | |
4582 | ||
6f392d54 CW |
4583 | dev_priv->next_seqno = 1; |
4584 | ||
68f95ba9 CW |
4585 | return 0; |
4586 | ||
549f7365 | 4587 | cleanup_bsd_ring: |
78501eac | 4588 | intel_cleanup_ring_buffer(&dev_priv->bsd_ring); |
68f95ba9 | 4589 | cleanup_render_ring: |
78501eac | 4590 | intel_cleanup_ring_buffer(&dev_priv->render_ring); |
68f95ba9 CW |
4591 | cleanup_pipe_control: |
4592 | if (HAS_PIPE_CONTROL(dev)) | |
4593 | i915_gem_cleanup_pipe_control(dev); | |
8187a2b7 ZN |
4594 | return ret; |
4595 | } | |
4596 | ||
4597 | void | |
4598 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4599 | { | |
4600 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4601 | ||
78501eac CW |
4602 | intel_cleanup_ring_buffer(&dev_priv->render_ring); |
4603 | intel_cleanup_ring_buffer(&dev_priv->bsd_ring); | |
4604 | intel_cleanup_ring_buffer(&dev_priv->blt_ring); | |
8187a2b7 ZN |
4605 | if (HAS_PIPE_CONTROL(dev)) |
4606 | i915_gem_cleanup_pipe_control(dev); | |
4607 | } | |
4608 | ||
673a394b EA |
4609 | int |
4610 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4611 | struct drm_file *file_priv) | |
4612 | { | |
4613 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4614 | int ret; | |
4615 | ||
79e53945 JB |
4616 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4617 | return 0; | |
4618 | ||
ba1234d1 | 4619 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 4620 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 4621 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
4622 | } |
4623 | ||
673a394b | 4624 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
4625 | dev_priv->mm.suspended = 0; |
4626 | ||
4627 | ret = i915_gem_init_ringbuffer(dev); | |
d816f6ac WF |
4628 | if (ret != 0) { |
4629 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4630 | return ret; |
d816f6ac | 4631 | } |
9bb2d6f9 | 4632 | |
69dc4987 | 4633 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
852835f3 | 4634 | BUG_ON(!list_empty(&dev_priv->render_ring.active_list)); |
87acb0a5 | 4635 | BUG_ON(!list_empty(&dev_priv->bsd_ring.active_list)); |
549f7365 | 4636 | BUG_ON(!list_empty(&dev_priv->blt_ring.active_list)); |
673a394b EA |
4637 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
4638 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
852835f3 | 4639 | BUG_ON(!list_empty(&dev_priv->render_ring.request_list)); |
87acb0a5 | 4640 | BUG_ON(!list_empty(&dev_priv->bsd_ring.request_list)); |
549f7365 | 4641 | BUG_ON(!list_empty(&dev_priv->blt_ring.request_list)); |
673a394b | 4642 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4643 | |
5f35308b CW |
4644 | ret = drm_irq_install(dev); |
4645 | if (ret) | |
4646 | goto cleanup_ringbuffer; | |
dbb19d30 | 4647 | |
673a394b | 4648 | return 0; |
5f35308b CW |
4649 | |
4650 | cleanup_ringbuffer: | |
4651 | mutex_lock(&dev->struct_mutex); | |
4652 | i915_gem_cleanup_ringbuffer(dev); | |
4653 | dev_priv->mm.suspended = 1; | |
4654 | mutex_unlock(&dev->struct_mutex); | |
4655 | ||
4656 | return ret; | |
673a394b EA |
4657 | } |
4658 | ||
4659 | int | |
4660 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4661 | struct drm_file *file_priv) | |
4662 | { | |
79e53945 JB |
4663 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4664 | return 0; | |
4665 | ||
dbb19d30 | 4666 | drm_irq_uninstall(dev); |
e6890f6f | 4667 | return i915_gem_idle(dev); |
673a394b EA |
4668 | } |
4669 | ||
4670 | void | |
4671 | i915_gem_lastclose(struct drm_device *dev) | |
4672 | { | |
4673 | int ret; | |
673a394b | 4674 | |
e806b495 EA |
4675 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4676 | return; | |
4677 | ||
6dbe2772 KP |
4678 | ret = i915_gem_idle(dev); |
4679 | if (ret) | |
4680 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4681 | } |
4682 | ||
64193406 CW |
4683 | static void |
4684 | init_ring_lists(struct intel_ring_buffer *ring) | |
4685 | { | |
4686 | INIT_LIST_HEAD(&ring->active_list); | |
4687 | INIT_LIST_HEAD(&ring->request_list); | |
4688 | INIT_LIST_HEAD(&ring->gpu_write_list); | |
4689 | } | |
4690 | ||
673a394b EA |
4691 | void |
4692 | i915_gem_load(struct drm_device *dev) | |
4693 | { | |
b5aa8a0f | 4694 | int i; |
673a394b EA |
4695 | drm_i915_private_t *dev_priv = dev->dev_private; |
4696 | ||
69dc4987 | 4697 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b EA |
4698 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
4699 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); | |
f13d3f73 | 4700 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
a09ba7fa | 4701 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
be72615b | 4702 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
64193406 CW |
4703 | init_ring_lists(&dev_priv->render_ring); |
4704 | init_ring_lists(&dev_priv->bsd_ring); | |
4705 | init_ring_lists(&dev_priv->blt_ring); | |
007cc8ac DV |
4706 | for (i = 0; i < 16; i++) |
4707 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); | |
673a394b EA |
4708 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4709 | i915_gem_retire_work_handler); | |
30dbf0c0 | 4710 | init_completion(&dev_priv->error_completion); |
31169714 | 4711 | |
94400120 DA |
4712 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4713 | if (IS_GEN3(dev)) { | |
4714 | u32 tmp = I915_READ(MI_ARB_STATE); | |
4715 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { | |
4716 | /* arb state is a masked write, so set bit + bit in mask */ | |
4717 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); | |
4718 | I915_WRITE(MI_ARB_STATE, tmp); | |
4719 | } | |
4720 | } | |
4721 | ||
de151cf6 | 4722 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4723 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4724 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4725 | |
a6c45cf0 | 4726 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
4727 | dev_priv->num_fence_regs = 16; |
4728 | else | |
4729 | dev_priv->num_fence_regs = 8; | |
4730 | ||
b5aa8a0f | 4731 | /* Initialize fence registers to zero */ |
a6c45cf0 CW |
4732 | switch (INTEL_INFO(dev)->gen) { |
4733 | case 6: | |
4734 | for (i = 0; i < 16; i++) | |
4735 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0); | |
4736 | break; | |
4737 | case 5: | |
4738 | case 4: | |
b5aa8a0f GH |
4739 | for (i = 0; i < 16; i++) |
4740 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); | |
a6c45cf0 CW |
4741 | break; |
4742 | case 3: | |
b5aa8a0f GH |
4743 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
4744 | for (i = 0; i < 8; i++) | |
4745 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); | |
a6c45cf0 CW |
4746 | case 2: |
4747 | for (i = 0; i < 8; i++) | |
4748 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); | |
4749 | break; | |
b5aa8a0f | 4750 | } |
673a394b | 4751 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4752 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 CW |
4753 | |
4754 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; | |
4755 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
4756 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 4757 | } |
71acb5eb DA |
4758 | |
4759 | /* | |
4760 | * Create a physically contiguous memory object for this object | |
4761 | * e.g. for cursor + overlay regs | |
4762 | */ | |
995b6762 CW |
4763 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4764 | int id, int size, int align) | |
71acb5eb DA |
4765 | { |
4766 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4767 | struct drm_i915_gem_phys_object *phys_obj; | |
4768 | int ret; | |
4769 | ||
4770 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4771 | return 0; | |
4772 | ||
9a298b2a | 4773 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4774 | if (!phys_obj) |
4775 | return -ENOMEM; | |
4776 | ||
4777 | phys_obj->id = id; | |
4778 | ||
6eeefaf3 | 4779 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4780 | if (!phys_obj->handle) { |
4781 | ret = -ENOMEM; | |
4782 | goto kfree_obj; | |
4783 | } | |
4784 | #ifdef CONFIG_X86 | |
4785 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4786 | #endif | |
4787 | ||
4788 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4789 | ||
4790 | return 0; | |
4791 | kfree_obj: | |
9a298b2a | 4792 | kfree(phys_obj); |
71acb5eb DA |
4793 | return ret; |
4794 | } | |
4795 | ||
995b6762 | 4796 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4797 | { |
4798 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4799 | struct drm_i915_gem_phys_object *phys_obj; | |
4800 | ||
4801 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4802 | return; | |
4803 | ||
4804 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4805 | if (phys_obj->cur_obj) { | |
4806 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4807 | } | |
4808 | ||
4809 | #ifdef CONFIG_X86 | |
4810 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4811 | #endif | |
4812 | drm_pci_free(dev, phys_obj->handle); | |
4813 | kfree(phys_obj); | |
4814 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4815 | } | |
4816 | ||
4817 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4818 | { | |
4819 | int i; | |
4820 | ||
260883c8 | 4821 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4822 | i915_gem_free_phys_object(dev, i); |
4823 | } | |
4824 | ||
4825 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
4826 | struct drm_gem_object *obj) | |
4827 | { | |
e5281ccd CW |
4828 | struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping; |
4829 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
4830 | char *vaddr; | |
71acb5eb | 4831 | int i; |
71acb5eb DA |
4832 | int page_count; |
4833 | ||
71acb5eb DA |
4834 | if (!obj_priv->phys_obj) |
4835 | return; | |
e5281ccd | 4836 | vaddr = obj_priv->phys_obj->handle->vaddr; |
71acb5eb DA |
4837 | |
4838 | page_count = obj->size / PAGE_SIZE; | |
4839 | ||
4840 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4841 | struct page *page = read_cache_page_gfp(mapping, i, |
4842 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
4843 | if (!IS_ERR(page)) { | |
4844 | char *dst = kmap_atomic(page); | |
4845 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
4846 | kunmap_atomic(dst); | |
4847 | ||
4848 | drm_clflush_pages(&page, 1); | |
4849 | ||
4850 | set_page_dirty(page); | |
4851 | mark_page_accessed(page); | |
4852 | page_cache_release(page); | |
4853 | } | |
71acb5eb | 4854 | } |
71acb5eb | 4855 | drm_agp_chipset_flush(dev); |
d78b47b9 | 4856 | |
71acb5eb DA |
4857 | obj_priv->phys_obj->cur_obj = NULL; |
4858 | obj_priv->phys_obj = NULL; | |
4859 | } | |
4860 | ||
4861 | int | |
4862 | i915_gem_attach_phys_object(struct drm_device *dev, | |
6eeefaf3 CW |
4863 | struct drm_gem_object *obj, |
4864 | int id, | |
4865 | int align) | |
71acb5eb | 4866 | { |
e5281ccd | 4867 | struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping; |
71acb5eb DA |
4868 | drm_i915_private_t *dev_priv = dev->dev_private; |
4869 | struct drm_i915_gem_object *obj_priv; | |
4870 | int ret = 0; | |
4871 | int page_count; | |
4872 | int i; | |
4873 | ||
4874 | if (id > I915_MAX_PHYS_OBJECT) | |
4875 | return -EINVAL; | |
4876 | ||
23010e43 | 4877 | obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4878 | |
4879 | if (obj_priv->phys_obj) { | |
4880 | if (obj_priv->phys_obj->id == id) | |
4881 | return 0; | |
4882 | i915_gem_detach_phys_object(dev, obj); | |
4883 | } | |
4884 | ||
71acb5eb DA |
4885 | /* create a new object */ |
4886 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4887 | ret = i915_gem_init_phys_object(dev, id, | |
6eeefaf3 | 4888 | obj->size, align); |
71acb5eb | 4889 | if (ret) { |
aeb565df | 4890 | DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size); |
e5281ccd | 4891 | return ret; |
71acb5eb DA |
4892 | } |
4893 | } | |
4894 | ||
4895 | /* bind to the object */ | |
4896 | obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4897 | obj_priv->phys_obj->cur_obj = obj; | |
4898 | ||
71acb5eb DA |
4899 | page_count = obj->size / PAGE_SIZE; |
4900 | ||
4901 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4902 | struct page *page; |
4903 | char *dst, *src; | |
4904 | ||
4905 | page = read_cache_page_gfp(mapping, i, | |
4906 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
4907 | if (IS_ERR(page)) | |
4908 | return PTR_ERR(page); | |
71acb5eb | 4909 | |
e5281ccd CW |
4910 | src = kmap_atomic(obj_priv->pages[i]); |
4911 | dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); | |
71acb5eb | 4912 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 4913 | kunmap_atomic(src); |
71acb5eb | 4914 | |
e5281ccd CW |
4915 | mark_page_accessed(page); |
4916 | page_cache_release(page); | |
4917 | } | |
d78b47b9 | 4918 | |
71acb5eb | 4919 | return 0; |
71acb5eb DA |
4920 | } |
4921 | ||
4922 | static int | |
4923 | i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, | |
4924 | struct drm_i915_gem_pwrite *args, | |
4925 | struct drm_file *file_priv) | |
4926 | { | |
23010e43 | 4927 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4928 | void *obj_addr; |
4929 | int ret; | |
4930 | char __user *user_data; | |
4931 | ||
4932 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
4933 | obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset; | |
4934 | ||
44d98a61 | 4935 | DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size); |
71acb5eb DA |
4936 | ret = copy_from_user(obj_addr, user_data, args->size); |
4937 | if (ret) | |
4938 | return -EFAULT; | |
4939 | ||
4940 | drm_agp_chipset_flush(dev); | |
4941 | return 0; | |
4942 | } | |
b962442e | 4943 | |
f787a5f5 | 4944 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4945 | { |
f787a5f5 | 4946 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4947 | |
4948 | /* Clean up our request list when the client is going away, so that | |
4949 | * later retire_requests won't dereference our soon-to-be-gone | |
4950 | * file_priv. | |
4951 | */ | |
1c25595f | 4952 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4953 | while (!list_empty(&file_priv->mm.request_list)) { |
4954 | struct drm_i915_gem_request *request; | |
4955 | ||
4956 | request = list_first_entry(&file_priv->mm.request_list, | |
4957 | struct drm_i915_gem_request, | |
4958 | client_list); | |
4959 | list_del(&request->client_list); | |
4960 | request->file_priv = NULL; | |
4961 | } | |
1c25595f | 4962 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4963 | } |
31169714 | 4964 | |
1637ef41 CW |
4965 | static int |
4966 | i915_gpu_is_active(struct drm_device *dev) | |
4967 | { | |
4968 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4969 | int lists_empty; | |
4970 | ||
1637ef41 | 4971 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
17250b71 | 4972 | list_empty(&dev_priv->mm.active_list); |
1637ef41 CW |
4973 | |
4974 | return !lists_empty; | |
4975 | } | |
4976 | ||
31169714 | 4977 | static int |
17250b71 CW |
4978 | i915_gem_inactive_shrink(struct shrinker *shrinker, |
4979 | int nr_to_scan, | |
4980 | gfp_t gfp_mask) | |
31169714 | 4981 | { |
17250b71 CW |
4982 | struct drm_i915_private *dev_priv = |
4983 | container_of(shrinker, | |
4984 | struct drm_i915_private, | |
4985 | mm.inactive_shrinker); | |
4986 | struct drm_device *dev = dev_priv->dev; | |
4987 | struct drm_i915_gem_object *obj, *next; | |
4988 | int cnt; | |
4989 | ||
4990 | if (!mutex_trylock(&dev->struct_mutex)) | |
4991 | return nr_to_scan ? 0 : -1; | |
31169714 CW |
4992 | |
4993 | /* "fast-path" to count number of available objects */ | |
4994 | if (nr_to_scan == 0) { | |
17250b71 CW |
4995 | cnt = 0; |
4996 | list_for_each_entry(obj, | |
4997 | &dev_priv->mm.inactive_list, | |
4998 | mm_list) | |
4999 | cnt++; | |
5000 | mutex_unlock(&dev->struct_mutex); | |
5001 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 CW |
5002 | } |
5003 | ||
1637ef41 | 5004 | rescan: |
31169714 | 5005 | /* first scan for clean buffers */ |
17250b71 | 5006 | i915_gem_retire_requests(dev); |
31169714 | 5007 | |
17250b71 CW |
5008 | list_for_each_entry_safe(obj, next, |
5009 | &dev_priv->mm.inactive_list, | |
5010 | mm_list) { | |
5011 | if (i915_gem_object_is_purgeable(obj)) { | |
5012 | i915_gem_object_unbind(&obj->base); | |
5013 | if (--nr_to_scan == 0) | |
5014 | break; | |
31169714 | 5015 | } |
31169714 CW |
5016 | } |
5017 | ||
5018 | /* second pass, evict/count anything still on the inactive list */ | |
17250b71 CW |
5019 | cnt = 0; |
5020 | list_for_each_entry_safe(obj, next, | |
5021 | &dev_priv->mm.inactive_list, | |
5022 | mm_list) { | |
5023 | if (nr_to_scan) { | |
5024 | i915_gem_object_unbind(&obj->base); | |
5025 | nr_to_scan--; | |
5026 | } else | |
5027 | cnt++; | |
5028 | } | |
5029 | ||
5030 | if (nr_to_scan && i915_gpu_is_active(dev)) { | |
1637ef41 CW |
5031 | /* |
5032 | * We are desperate for pages, so as a last resort, wait | |
5033 | * for the GPU to finish and discard whatever we can. | |
5034 | * This has a dramatic impact to reduce the number of | |
5035 | * OOM-killer events whilst running the GPU aggressively. | |
5036 | */ | |
17250b71 | 5037 | if (i915_gpu_idle(dev) == 0) |
1637ef41 CW |
5038 | goto rescan; |
5039 | } | |
17250b71 CW |
5040 | mutex_unlock(&dev->struct_mutex); |
5041 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 | 5042 | } |