Commit | Line | Data |
---|---|---|
673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5949eac4 | 34 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
673a394b | 36 | #include <linux/swap.h> |
79e53945 | 37 | #include <linux/pci.h> |
673a394b | 38 | |
88241785 | 39 | static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj); |
05394f39 CW |
40 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
41 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); | |
88241785 CW |
42 | static __must_check int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, |
43 | bool write); | |
44 | static __must_check int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj, | |
45 | uint64_t offset, | |
46 | uint64_t size); | |
05394f39 | 47 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj); |
88241785 CW |
48 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
49 | unsigned alignment, | |
50 | bool map_and_fenceable); | |
d9e86c0e CW |
51 | static void i915_gem_clear_fence_reg(struct drm_device *dev, |
52 | struct drm_i915_fence_reg *reg); | |
05394f39 CW |
53 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
54 | struct drm_i915_gem_object *obj, | |
71acb5eb | 55 | struct drm_i915_gem_pwrite *args, |
05394f39 CW |
56 | struct drm_file *file); |
57 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj); | |
673a394b | 58 | |
17250b71 | 59 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
1495f230 | 60 | struct shrink_control *sc); |
8c59967c | 61 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
31169714 | 62 | |
73aa808f CW |
63 | /* some bookkeeping */ |
64 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
65 | size_t size) | |
66 | { | |
67 | dev_priv->mm.object_count++; | |
68 | dev_priv->mm.object_memory += size; | |
69 | } | |
70 | ||
71 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
72 | size_t size) | |
73 | { | |
74 | dev_priv->mm.object_count--; | |
75 | dev_priv->mm.object_memory -= size; | |
76 | } | |
77 | ||
21dd3734 CW |
78 | static int |
79 | i915_gem_wait_for_error(struct drm_device *dev) | |
30dbf0c0 CW |
80 | { |
81 | struct drm_i915_private *dev_priv = dev->dev_private; | |
82 | struct completion *x = &dev_priv->error_completion; | |
83 | unsigned long flags; | |
84 | int ret; | |
85 | ||
86 | if (!atomic_read(&dev_priv->mm.wedged)) | |
87 | return 0; | |
88 | ||
89 | ret = wait_for_completion_interruptible(x); | |
90 | if (ret) | |
91 | return ret; | |
92 | ||
21dd3734 CW |
93 | if (atomic_read(&dev_priv->mm.wedged)) { |
94 | /* GPU is hung, bump the completion count to account for | |
95 | * the token we just consumed so that we never hit zero and | |
96 | * end up waiting upon a subsequent completion event that | |
97 | * will never happen. | |
98 | */ | |
99 | spin_lock_irqsave(&x->wait.lock, flags); | |
100 | x->done++; | |
101 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
102 | } | |
103 | return 0; | |
30dbf0c0 CW |
104 | } |
105 | ||
54cf91dc | 106 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 107 | { |
76c1dec1 CW |
108 | int ret; |
109 | ||
21dd3734 | 110 | ret = i915_gem_wait_for_error(dev); |
76c1dec1 CW |
111 | if (ret) |
112 | return ret; | |
113 | ||
114 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
115 | if (ret) | |
116 | return ret; | |
117 | ||
23bc5982 | 118 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
119 | return 0; |
120 | } | |
30dbf0c0 | 121 | |
7d1c4804 | 122 | static inline bool |
05394f39 | 123 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 124 | { |
05394f39 | 125 | return obj->gtt_space && !obj->active && obj->pin_count == 0; |
7d1c4804 CW |
126 | } |
127 | ||
79e53945 JB |
128 | int |
129 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 130 | struct drm_file *file) |
79e53945 JB |
131 | { |
132 | struct drm_i915_gem_init *args = data; | |
2021746e CW |
133 | |
134 | if (args->gtt_start >= args->gtt_end || | |
135 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
136 | return -EINVAL; | |
79e53945 JB |
137 | |
138 | mutex_lock(&dev->struct_mutex); | |
644ec02b DV |
139 | i915_gem_init_global_gtt(dev, args->gtt_start, |
140 | args->gtt_end, args->gtt_end); | |
673a394b EA |
141 | mutex_unlock(&dev->struct_mutex); |
142 | ||
2021746e | 143 | return 0; |
673a394b EA |
144 | } |
145 | ||
5a125c3c EA |
146 | int |
147 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 148 | struct drm_file *file) |
5a125c3c | 149 | { |
73aa808f | 150 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 151 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
152 | struct drm_i915_gem_object *obj; |
153 | size_t pinned; | |
5a125c3c EA |
154 | |
155 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
156 | return -ENODEV; | |
157 | ||
6299f992 | 158 | pinned = 0; |
73aa808f | 159 | mutex_lock(&dev->struct_mutex); |
6299f992 CW |
160 | list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list) |
161 | pinned += obj->gtt_space->size; | |
73aa808f | 162 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 163 | |
6299f992 | 164 | args->aper_size = dev_priv->mm.gtt_total; |
0206e353 | 165 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 166 | |
5a125c3c EA |
167 | return 0; |
168 | } | |
169 | ||
ff72145b DA |
170 | static int |
171 | i915_gem_create(struct drm_file *file, | |
172 | struct drm_device *dev, | |
173 | uint64_t size, | |
174 | uint32_t *handle_p) | |
673a394b | 175 | { |
05394f39 | 176 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
177 | int ret; |
178 | u32 handle; | |
673a394b | 179 | |
ff72145b | 180 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
181 | if (size == 0) |
182 | return -EINVAL; | |
673a394b EA |
183 | |
184 | /* Allocate the new object */ | |
ff72145b | 185 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
186 | if (obj == NULL) |
187 | return -ENOMEM; | |
188 | ||
05394f39 | 189 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
1dfd9754 | 190 | if (ret) { |
05394f39 CW |
191 | drm_gem_object_release(&obj->base); |
192 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); | |
202f2fef | 193 | kfree(obj); |
673a394b | 194 | return ret; |
1dfd9754 | 195 | } |
673a394b | 196 | |
202f2fef | 197 | /* drop reference from allocate - handle holds it now */ |
05394f39 | 198 | drm_gem_object_unreference(&obj->base); |
202f2fef CW |
199 | trace_i915_gem_object_create(obj); |
200 | ||
ff72145b | 201 | *handle_p = handle; |
673a394b EA |
202 | return 0; |
203 | } | |
204 | ||
ff72145b DA |
205 | int |
206 | i915_gem_dumb_create(struct drm_file *file, | |
207 | struct drm_device *dev, | |
208 | struct drm_mode_create_dumb *args) | |
209 | { | |
210 | /* have to work out size/pitch and return them */ | |
ed0291fd | 211 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
ff72145b DA |
212 | args->size = args->pitch * args->height; |
213 | return i915_gem_create(file, dev, | |
214 | args->size, &args->handle); | |
215 | } | |
216 | ||
217 | int i915_gem_dumb_destroy(struct drm_file *file, | |
218 | struct drm_device *dev, | |
219 | uint32_t handle) | |
220 | { | |
221 | return drm_gem_handle_delete(file, handle); | |
222 | } | |
223 | ||
224 | /** | |
225 | * Creates a new mm object and returns a handle to it. | |
226 | */ | |
227 | int | |
228 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
229 | struct drm_file *file) | |
230 | { | |
231 | struct drm_i915_gem_create *args = data; | |
232 | return i915_gem_create(file, dev, | |
233 | args->size, &args->handle); | |
234 | } | |
235 | ||
05394f39 | 236 | static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
280b713b | 237 | { |
05394f39 | 238 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
280b713b EA |
239 | |
240 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
05394f39 | 241 | obj->tiling_mode != I915_TILING_NONE; |
280b713b EA |
242 | } |
243 | ||
eb01459f EA |
244 | /** |
245 | * This is the fast shmem pread path, which attempts to copy_from_user directly | |
246 | * from the backing pages of the object to the user's address space. On a | |
247 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). | |
248 | */ | |
249 | static int | |
05394f39 CW |
250 | i915_gem_shmem_pread_fast(struct drm_device *dev, |
251 | struct drm_i915_gem_object *obj, | |
eb01459f | 252 | struct drm_i915_gem_pread *args, |
05394f39 | 253 | struct drm_file *file) |
eb01459f | 254 | { |
05394f39 | 255 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
eb01459f | 256 | ssize_t remain; |
e5281ccd | 257 | loff_t offset; |
eb01459f EA |
258 | char __user *user_data; |
259 | int page_offset, page_length; | |
eb01459f EA |
260 | |
261 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
262 | remain = args->size; | |
263 | ||
eb01459f EA |
264 | offset = args->offset; |
265 | ||
266 | while (remain > 0) { | |
e5281ccd CW |
267 | struct page *page; |
268 | char *vaddr; | |
269 | int ret; | |
270 | ||
eb01459f EA |
271 | /* Operation in this page |
272 | * | |
eb01459f EA |
273 | * page_offset = offset within page |
274 | * page_length = bytes to copy for this page | |
275 | */ | |
c8cbbb8b | 276 | page_offset = offset_in_page(offset); |
eb01459f EA |
277 | page_length = remain; |
278 | if ((page_offset + remain) > PAGE_SIZE) | |
279 | page_length = PAGE_SIZE - page_offset; | |
280 | ||
5949eac4 | 281 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
e5281ccd CW |
282 | if (IS_ERR(page)) |
283 | return PTR_ERR(page); | |
284 | ||
285 | vaddr = kmap_atomic(page); | |
286 | ret = __copy_to_user_inatomic(user_data, | |
287 | vaddr + page_offset, | |
288 | page_length); | |
289 | kunmap_atomic(vaddr); | |
290 | ||
291 | mark_page_accessed(page); | |
292 | page_cache_release(page); | |
293 | if (ret) | |
4f27b75d | 294 | return -EFAULT; |
eb01459f EA |
295 | |
296 | remain -= page_length; | |
297 | user_data += page_length; | |
298 | offset += page_length; | |
299 | } | |
300 | ||
4f27b75d | 301 | return 0; |
eb01459f EA |
302 | } |
303 | ||
8461d226 DV |
304 | static inline int |
305 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
306 | const char *gpu_vaddr, int gpu_offset, | |
307 | int length) | |
308 | { | |
309 | int ret, cpu_offset = 0; | |
310 | ||
311 | while (length > 0) { | |
312 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
313 | int this_length = min(cacheline_end - gpu_offset, length); | |
314 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
315 | ||
316 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
317 | gpu_vaddr + swizzled_gpu_offset, | |
318 | this_length); | |
319 | if (ret) | |
320 | return ret + length; | |
321 | ||
322 | cpu_offset += this_length; | |
323 | gpu_offset += this_length; | |
324 | length -= this_length; | |
325 | } | |
326 | ||
327 | return 0; | |
328 | } | |
329 | ||
8c59967c DV |
330 | static inline int |
331 | __copy_from_user_swizzled(char __user *gpu_vaddr, int gpu_offset, | |
332 | const char *cpu_vaddr, | |
333 | int length) | |
334 | { | |
335 | int ret, cpu_offset = 0; | |
336 | ||
337 | while (length > 0) { | |
338 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
339 | int this_length = min(cacheline_end - gpu_offset, length); | |
340 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
341 | ||
342 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
343 | cpu_vaddr + cpu_offset, | |
344 | this_length); | |
345 | if (ret) | |
346 | return ret + length; | |
347 | ||
348 | cpu_offset += this_length; | |
349 | gpu_offset += this_length; | |
350 | length -= this_length; | |
351 | } | |
352 | ||
353 | return 0; | |
354 | } | |
355 | ||
eb01459f EA |
356 | /** |
357 | * This is the fallback shmem pread path, which allocates temporary storage | |
358 | * in kernel space to copy_to_user into outside of the struct_mutex, so we | |
359 | * can copy out of the object's backing pages while holding the struct mutex | |
360 | * and not take page faults. | |
361 | */ | |
362 | static int | |
05394f39 CW |
363 | i915_gem_shmem_pread_slow(struct drm_device *dev, |
364 | struct drm_i915_gem_object *obj, | |
eb01459f | 365 | struct drm_i915_gem_pread *args, |
05394f39 | 366 | struct drm_file *file) |
eb01459f | 367 | { |
05394f39 | 368 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
8461d226 | 369 | char __user *user_data; |
eb01459f | 370 | ssize_t remain; |
8461d226 | 371 | loff_t offset; |
eb2c0c81 | 372 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 373 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
eb01459f | 374 | |
8461d226 | 375 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
eb01459f EA |
376 | remain = args->size; |
377 | ||
8461d226 | 378 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 379 | |
8461d226 | 380 | offset = args->offset; |
eb01459f | 381 | |
4f27b75d | 382 | mutex_unlock(&dev->struct_mutex); |
eb01459f EA |
383 | |
384 | while (remain > 0) { | |
e5281ccd | 385 | struct page *page; |
8461d226 | 386 | char *vaddr; |
e5281ccd | 387 | |
eb01459f EA |
388 | /* Operation in this page |
389 | * | |
eb01459f | 390 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
391 | * page_length = bytes to copy for this page |
392 | */ | |
c8cbbb8b | 393 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
394 | page_length = remain; |
395 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
396 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 397 | |
5949eac4 | 398 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
b65552f0 JJ |
399 | if (IS_ERR(page)) { |
400 | ret = PTR_ERR(page); | |
401 | goto out; | |
402 | } | |
e5281ccd | 403 | |
8461d226 DV |
404 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
405 | (page_to_phys(page) & (1 << 17)) != 0; | |
406 | ||
407 | vaddr = kmap(page); | |
408 | if (page_do_bit17_swizzling) | |
409 | ret = __copy_to_user_swizzled(user_data, | |
410 | vaddr, shmem_page_offset, | |
411 | page_length); | |
412 | else | |
413 | ret = __copy_to_user(user_data, | |
414 | vaddr + shmem_page_offset, | |
415 | page_length); | |
416 | kunmap(page); | |
eb01459f | 417 | |
e5281ccd CW |
418 | mark_page_accessed(page); |
419 | page_cache_release(page); | |
420 | ||
8461d226 DV |
421 | if (ret) { |
422 | ret = -EFAULT; | |
423 | goto out; | |
424 | } | |
425 | ||
eb01459f | 426 | remain -= page_length; |
8461d226 | 427 | user_data += page_length; |
eb01459f EA |
428 | offset += page_length; |
429 | } | |
430 | ||
4f27b75d | 431 | out: |
8461d226 DV |
432 | mutex_lock(&dev->struct_mutex); |
433 | /* Fixup: Kill any reinstated backing storage pages */ | |
434 | if (obj->madv == __I915_MADV_PURGED) | |
435 | i915_gem_object_truncate(obj); | |
eb01459f EA |
436 | |
437 | return ret; | |
438 | } | |
439 | ||
673a394b EA |
440 | /** |
441 | * Reads data from the object referenced by handle. | |
442 | * | |
443 | * On error, the contents of *data are undefined. | |
444 | */ | |
445 | int | |
446 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 447 | struct drm_file *file) |
673a394b EA |
448 | { |
449 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 450 | struct drm_i915_gem_object *obj; |
35b62a89 | 451 | int ret = 0; |
673a394b | 452 | |
51311d0a CW |
453 | if (args->size == 0) |
454 | return 0; | |
455 | ||
456 | if (!access_ok(VERIFY_WRITE, | |
457 | (char __user *)(uintptr_t)args->data_ptr, | |
458 | args->size)) | |
459 | return -EFAULT; | |
460 | ||
461 | ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr, | |
462 | args->size); | |
463 | if (ret) | |
464 | return -EFAULT; | |
465 | ||
4f27b75d | 466 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 467 | if (ret) |
4f27b75d | 468 | return ret; |
673a394b | 469 | |
05394f39 | 470 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 471 | if (&obj->base == NULL) { |
1d7cfea1 CW |
472 | ret = -ENOENT; |
473 | goto unlock; | |
4f27b75d | 474 | } |
673a394b | 475 | |
7dcd2499 | 476 | /* Bounds check source. */ |
05394f39 CW |
477 | if (args->offset > obj->base.size || |
478 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 479 | ret = -EINVAL; |
35b62a89 | 480 | goto out; |
ce9d419d CW |
481 | } |
482 | ||
db53a302 CW |
483 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
484 | ||
4f27b75d CW |
485 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
486 | args->offset, | |
487 | args->size); | |
488 | if (ret) | |
e5281ccd | 489 | goto out; |
4f27b75d CW |
490 | |
491 | ret = -EFAULT; | |
492 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
05394f39 | 493 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file); |
4f27b75d | 494 | if (ret == -EFAULT) |
05394f39 | 495 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file); |
673a394b | 496 | |
35b62a89 | 497 | out: |
05394f39 | 498 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 499 | unlock: |
4f27b75d | 500 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 501 | return ret; |
673a394b EA |
502 | } |
503 | ||
0839ccb8 KP |
504 | /* This is the fast write path which cannot handle |
505 | * page faults in the source data | |
9b7530cc | 506 | */ |
0839ccb8 KP |
507 | |
508 | static inline int | |
509 | fast_user_write(struct io_mapping *mapping, | |
510 | loff_t page_base, int page_offset, | |
511 | char __user *user_data, | |
512 | int length) | |
9b7530cc | 513 | { |
9b7530cc | 514 | char *vaddr_atomic; |
0839ccb8 | 515 | unsigned long unwritten; |
9b7530cc | 516 | |
3e4d3af5 | 517 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
0839ccb8 KP |
518 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
519 | user_data, length); | |
3e4d3af5 | 520 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 521 | return unwritten; |
0839ccb8 KP |
522 | } |
523 | ||
524 | /* Here's the write path which can sleep for | |
525 | * page faults | |
526 | */ | |
527 | ||
ab34c226 | 528 | static inline void |
3de09aa3 EA |
529 | slow_kernel_write(struct io_mapping *mapping, |
530 | loff_t gtt_base, int gtt_offset, | |
531 | struct page *user_page, int user_offset, | |
532 | int length) | |
0839ccb8 | 533 | { |
ab34c226 CW |
534 | char __iomem *dst_vaddr; |
535 | char *src_vaddr; | |
0839ccb8 | 536 | |
ab34c226 CW |
537 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
538 | src_vaddr = kmap(user_page); | |
539 | ||
540 | memcpy_toio(dst_vaddr + gtt_offset, | |
541 | src_vaddr + user_offset, | |
542 | length); | |
543 | ||
544 | kunmap(user_page); | |
545 | io_mapping_unmap(dst_vaddr); | |
9b7530cc LT |
546 | } |
547 | ||
3de09aa3 EA |
548 | /** |
549 | * This is the fast pwrite path, where we copy the data directly from the | |
550 | * user into the GTT, uncached. | |
551 | */ | |
673a394b | 552 | static int |
05394f39 CW |
553 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
554 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 555 | struct drm_i915_gem_pwrite *args, |
05394f39 | 556 | struct drm_file *file) |
673a394b | 557 | { |
0839ccb8 | 558 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 559 | ssize_t remain; |
0839ccb8 | 560 | loff_t offset, page_base; |
673a394b | 561 | char __user *user_data; |
0839ccb8 | 562 | int page_offset, page_length; |
673a394b EA |
563 | |
564 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
565 | remain = args->size; | |
673a394b | 566 | |
05394f39 | 567 | offset = obj->gtt_offset + args->offset; |
673a394b EA |
568 | |
569 | while (remain > 0) { | |
570 | /* Operation in this page | |
571 | * | |
0839ccb8 KP |
572 | * page_base = page offset within aperture |
573 | * page_offset = offset within page | |
574 | * page_length = bytes to copy for this page | |
673a394b | 575 | */ |
c8cbbb8b CW |
576 | page_base = offset & PAGE_MASK; |
577 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
578 | page_length = remain; |
579 | if ((page_offset + remain) > PAGE_SIZE) | |
580 | page_length = PAGE_SIZE - page_offset; | |
581 | ||
0839ccb8 | 582 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
583 | * source page isn't available. Return the error and we'll |
584 | * retry in the slow path. | |
0839ccb8 | 585 | */ |
fbd5a26d CW |
586 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
587 | page_offset, user_data, page_length)) | |
fbd5a26d | 588 | return -EFAULT; |
673a394b | 589 | |
0839ccb8 KP |
590 | remain -= page_length; |
591 | user_data += page_length; | |
592 | offset += page_length; | |
673a394b | 593 | } |
673a394b | 594 | |
fbd5a26d | 595 | return 0; |
673a394b EA |
596 | } |
597 | ||
3de09aa3 EA |
598 | /** |
599 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin | |
600 | * the memory and maps it using kmap_atomic for copying. | |
601 | * | |
602 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU | |
603 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). | |
604 | */ | |
3043c60c | 605 | static int |
05394f39 CW |
606 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, |
607 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 608 | struct drm_i915_gem_pwrite *args, |
05394f39 | 609 | struct drm_file *file) |
673a394b | 610 | { |
3de09aa3 EA |
611 | drm_i915_private_t *dev_priv = dev->dev_private; |
612 | ssize_t remain; | |
613 | loff_t gtt_page_base, offset; | |
614 | loff_t first_data_page, last_data_page, num_pages; | |
615 | loff_t pinned_pages, i; | |
616 | struct page **user_pages; | |
617 | struct mm_struct *mm = current->mm; | |
618 | int gtt_page_offset, data_page_offset, data_page_index, page_length; | |
673a394b | 619 | int ret; |
3de09aa3 EA |
620 | uint64_t data_ptr = args->data_ptr; |
621 | ||
622 | remain = args->size; | |
623 | ||
624 | /* Pin the user pages containing the data. We can't fault while | |
625 | * holding the struct mutex, and all of the pwrite implementations | |
626 | * want to hold it while dereferencing the user data. | |
627 | */ | |
628 | first_data_page = data_ptr / PAGE_SIZE; | |
629 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
630 | num_pages = last_data_page - first_data_page + 1; | |
631 | ||
fbd5a26d | 632 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
3de09aa3 EA |
633 | if (user_pages == NULL) |
634 | return -ENOMEM; | |
635 | ||
fbd5a26d | 636 | mutex_unlock(&dev->struct_mutex); |
3de09aa3 EA |
637 | down_read(&mm->mmap_sem); |
638 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
639 | num_pages, 0, 0, user_pages, NULL); | |
640 | up_read(&mm->mmap_sem); | |
fbd5a26d | 641 | mutex_lock(&dev->struct_mutex); |
3de09aa3 EA |
642 | if (pinned_pages < num_pages) { |
643 | ret = -EFAULT; | |
644 | goto out_unpin_pages; | |
645 | } | |
673a394b | 646 | |
d9e86c0e CW |
647 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
648 | if (ret) | |
649 | goto out_unpin_pages; | |
650 | ||
651 | ret = i915_gem_object_put_fence(obj); | |
3de09aa3 | 652 | if (ret) |
fbd5a26d | 653 | goto out_unpin_pages; |
3de09aa3 | 654 | |
05394f39 | 655 | offset = obj->gtt_offset + args->offset; |
3de09aa3 EA |
656 | |
657 | while (remain > 0) { | |
658 | /* Operation in this page | |
659 | * | |
660 | * gtt_page_base = page offset within aperture | |
661 | * gtt_page_offset = offset within page in aperture | |
662 | * data_page_index = page number in get_user_pages return | |
663 | * data_page_offset = offset with data_page_index page. | |
664 | * page_length = bytes to copy for this page | |
665 | */ | |
666 | gtt_page_base = offset & PAGE_MASK; | |
c8cbbb8b | 667 | gtt_page_offset = offset_in_page(offset); |
3de09aa3 | 668 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
c8cbbb8b | 669 | data_page_offset = offset_in_page(data_ptr); |
3de09aa3 EA |
670 | |
671 | page_length = remain; | |
672 | if ((gtt_page_offset + page_length) > PAGE_SIZE) | |
673 | page_length = PAGE_SIZE - gtt_page_offset; | |
674 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
675 | page_length = PAGE_SIZE - data_page_offset; | |
676 | ||
ab34c226 CW |
677 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
678 | gtt_page_base, gtt_page_offset, | |
679 | user_pages[data_page_index], | |
680 | data_page_offset, | |
681 | page_length); | |
3de09aa3 EA |
682 | |
683 | remain -= page_length; | |
684 | offset += page_length; | |
685 | data_ptr += page_length; | |
686 | } | |
687 | ||
3de09aa3 EA |
688 | out_unpin_pages: |
689 | for (i = 0; i < pinned_pages; i++) | |
690 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 691 | drm_free_large(user_pages); |
3de09aa3 EA |
692 | |
693 | return ret; | |
694 | } | |
695 | ||
40123c1f EA |
696 | /** |
697 | * This is the fast shmem pwrite path, which attempts to directly | |
698 | * copy_from_user into the kmapped pages backing the object. | |
699 | */ | |
3043c60c | 700 | static int |
05394f39 CW |
701 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, |
702 | struct drm_i915_gem_object *obj, | |
40123c1f | 703 | struct drm_i915_gem_pwrite *args, |
05394f39 | 704 | struct drm_file *file) |
673a394b | 705 | { |
05394f39 | 706 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
40123c1f | 707 | ssize_t remain; |
e5281ccd | 708 | loff_t offset; |
40123c1f EA |
709 | char __user *user_data; |
710 | int page_offset, page_length; | |
40123c1f EA |
711 | |
712 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
713 | remain = args->size; | |
673a394b | 714 | |
40123c1f | 715 | offset = args->offset; |
05394f39 | 716 | obj->dirty = 1; |
40123c1f EA |
717 | |
718 | while (remain > 0) { | |
e5281ccd CW |
719 | struct page *page; |
720 | char *vaddr; | |
721 | int ret; | |
722 | ||
40123c1f EA |
723 | /* Operation in this page |
724 | * | |
40123c1f EA |
725 | * page_offset = offset within page |
726 | * page_length = bytes to copy for this page | |
727 | */ | |
c8cbbb8b | 728 | page_offset = offset_in_page(offset); |
40123c1f EA |
729 | page_length = remain; |
730 | if ((page_offset + remain) > PAGE_SIZE) | |
731 | page_length = PAGE_SIZE - page_offset; | |
732 | ||
5949eac4 | 733 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
e5281ccd CW |
734 | if (IS_ERR(page)) |
735 | return PTR_ERR(page); | |
736 | ||
130c2561 | 737 | vaddr = kmap_atomic(page); |
e5281ccd CW |
738 | ret = __copy_from_user_inatomic(vaddr + page_offset, |
739 | user_data, | |
740 | page_length); | |
130c2561 | 741 | kunmap_atomic(vaddr); |
e5281ccd CW |
742 | |
743 | set_page_dirty(page); | |
744 | mark_page_accessed(page); | |
745 | page_cache_release(page); | |
746 | ||
747 | /* If we get a fault while copying data, then (presumably) our | |
748 | * source page isn't available. Return the error and we'll | |
749 | * retry in the slow path. | |
750 | */ | |
751 | if (ret) | |
fbd5a26d | 752 | return -EFAULT; |
40123c1f EA |
753 | |
754 | remain -= page_length; | |
755 | user_data += page_length; | |
756 | offset += page_length; | |
757 | } | |
758 | ||
fbd5a26d | 759 | return 0; |
40123c1f EA |
760 | } |
761 | ||
762 | /** | |
763 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin | |
764 | * the memory and maps it using kmap_atomic for copying. | |
765 | * | |
766 | * This avoids taking mmap_sem for faulting on the user's address while the | |
767 | * struct_mutex is held. | |
768 | */ | |
769 | static int | |
05394f39 CW |
770 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, |
771 | struct drm_i915_gem_object *obj, | |
40123c1f | 772 | struct drm_i915_gem_pwrite *args, |
05394f39 | 773 | struct drm_file *file) |
40123c1f | 774 | { |
05394f39 | 775 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
40123c1f | 776 | ssize_t remain; |
8c59967c DV |
777 | loff_t offset; |
778 | char __user *user_data; | |
eb2c0c81 | 779 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 780 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
40123c1f | 781 | |
8c59967c | 782 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
40123c1f EA |
783 | remain = args->size; |
784 | ||
8c59967c | 785 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 786 | |
673a394b | 787 | offset = args->offset; |
05394f39 | 788 | obj->dirty = 1; |
673a394b | 789 | |
8c59967c DV |
790 | mutex_unlock(&dev->struct_mutex); |
791 | ||
40123c1f | 792 | while (remain > 0) { |
e5281ccd | 793 | struct page *page; |
8c59967c | 794 | char *vaddr; |
e5281ccd | 795 | |
40123c1f EA |
796 | /* Operation in this page |
797 | * | |
40123c1f | 798 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
799 | * page_length = bytes to copy for this page |
800 | */ | |
c8cbbb8b | 801 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
802 | |
803 | page_length = remain; | |
804 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
805 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 806 | |
5949eac4 | 807 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
e5281ccd CW |
808 | if (IS_ERR(page)) { |
809 | ret = PTR_ERR(page); | |
810 | goto out; | |
811 | } | |
812 | ||
8c59967c DV |
813 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
814 | (page_to_phys(page) & (1 << 17)) != 0; | |
815 | ||
816 | vaddr = kmap(page); | |
817 | if (page_do_bit17_swizzling) | |
818 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
819 | user_data, | |
820 | page_length); | |
821 | else | |
822 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
823 | user_data, | |
824 | page_length); | |
825 | kunmap(page); | |
40123c1f | 826 | |
e5281ccd CW |
827 | set_page_dirty(page); |
828 | mark_page_accessed(page); | |
829 | page_cache_release(page); | |
830 | ||
8c59967c DV |
831 | if (ret) { |
832 | ret = -EFAULT; | |
833 | goto out; | |
834 | } | |
835 | ||
40123c1f | 836 | remain -= page_length; |
8c59967c | 837 | user_data += page_length; |
40123c1f | 838 | offset += page_length; |
673a394b EA |
839 | } |
840 | ||
fbd5a26d | 841 | out: |
8c59967c DV |
842 | mutex_lock(&dev->struct_mutex); |
843 | /* Fixup: Kill any reinstated backing storage pages */ | |
844 | if (obj->madv == __I915_MADV_PURGED) | |
845 | i915_gem_object_truncate(obj); | |
846 | /* and flush dirty cachelines in case the object isn't in the cpu write | |
847 | * domain anymore. */ | |
848 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
849 | i915_gem_clflush_object(obj); | |
850 | intel_gtt_chipset_flush(); | |
851 | } | |
673a394b | 852 | |
40123c1f | 853 | return ret; |
673a394b EA |
854 | } |
855 | ||
856 | /** | |
857 | * Writes data to the object referenced by handle. | |
858 | * | |
859 | * On error, the contents of the buffer that were to be modified are undefined. | |
860 | */ | |
861 | int | |
862 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 863 | struct drm_file *file) |
673a394b EA |
864 | { |
865 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 866 | struct drm_i915_gem_object *obj; |
51311d0a CW |
867 | int ret; |
868 | ||
869 | if (args->size == 0) | |
870 | return 0; | |
871 | ||
872 | if (!access_ok(VERIFY_READ, | |
873 | (char __user *)(uintptr_t)args->data_ptr, | |
874 | args->size)) | |
875 | return -EFAULT; | |
876 | ||
877 | ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr, | |
878 | args->size); | |
879 | if (ret) | |
880 | return -EFAULT; | |
673a394b | 881 | |
fbd5a26d | 882 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 883 | if (ret) |
fbd5a26d | 884 | return ret; |
1d7cfea1 | 885 | |
05394f39 | 886 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 887 | if (&obj->base == NULL) { |
1d7cfea1 CW |
888 | ret = -ENOENT; |
889 | goto unlock; | |
fbd5a26d | 890 | } |
673a394b | 891 | |
7dcd2499 | 892 | /* Bounds check destination. */ |
05394f39 CW |
893 | if (args->offset > obj->base.size || |
894 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 895 | ret = -EINVAL; |
35b62a89 | 896 | goto out; |
ce9d419d CW |
897 | } |
898 | ||
db53a302 CW |
899 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
900 | ||
673a394b EA |
901 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
902 | * it would end up going through the fenced access, and we'll get | |
903 | * different detiling behavior between reading and writing. | |
904 | * pread/pwrite currently are reading and writing from the CPU | |
905 | * perspective, requiring manual detiling by the client. | |
906 | */ | |
5c0480f2 | 907 | if (obj->phys_obj) { |
fbd5a26d | 908 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
5c0480f2 DV |
909 | goto out; |
910 | } | |
911 | ||
912 | if (obj->gtt_space && | |
913 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
75e9e915 | 914 | ret = i915_gem_object_pin(obj, 0, true); |
fbd5a26d CW |
915 | if (ret) |
916 | goto out; | |
917 | ||
d9e86c0e CW |
918 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
919 | if (ret) | |
920 | goto out_unpin; | |
921 | ||
922 | ret = i915_gem_object_put_fence(obj); | |
fbd5a26d CW |
923 | if (ret) |
924 | goto out_unpin; | |
925 | ||
926 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); | |
927 | if (ret == -EFAULT) | |
928 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file); | |
929 | ||
930 | out_unpin: | |
931 | i915_gem_object_unpin(obj); | |
673a394b | 932 | |
5c0480f2 DV |
933 | if (ret != -EFAULT) |
934 | goto out; | |
935 | /* Fall through to the shmfs paths because the gtt paths might | |
936 | * fail with non-page-backed user pointers (e.g. gtt mappings | |
937 | * when moving data between textures). */ | |
fbd5a26d | 938 | } |
673a394b | 939 | |
5c0480f2 DV |
940 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
941 | if (ret) | |
942 | goto out; | |
943 | ||
944 | ret = -EFAULT; | |
945 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
946 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file); | |
947 | if (ret == -EFAULT) | |
948 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file); | |
949 | ||
35b62a89 | 950 | out: |
05394f39 | 951 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 952 | unlock: |
fbd5a26d | 953 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
954 | return ret; |
955 | } | |
956 | ||
957 | /** | |
2ef7eeaa EA |
958 | * Called when user space prepares to use an object with the CPU, either |
959 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
960 | */ |
961 | int | |
962 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 963 | struct drm_file *file) |
673a394b EA |
964 | { |
965 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 966 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
967 | uint32_t read_domains = args->read_domains; |
968 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
969 | int ret; |
970 | ||
971 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
972 | return -ENODEV; | |
973 | ||
2ef7eeaa | 974 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 975 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
976 | return -EINVAL; |
977 | ||
21d509e3 | 978 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
979 | return -EINVAL; |
980 | ||
981 | /* Having something in the write domain implies it's in the read | |
982 | * domain, and only that read domain. Enforce that in the request. | |
983 | */ | |
984 | if (write_domain != 0 && read_domains != write_domain) | |
985 | return -EINVAL; | |
986 | ||
76c1dec1 | 987 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 988 | if (ret) |
76c1dec1 | 989 | return ret; |
1d7cfea1 | 990 | |
05394f39 | 991 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 992 | if (&obj->base == NULL) { |
1d7cfea1 CW |
993 | ret = -ENOENT; |
994 | goto unlock; | |
76c1dec1 | 995 | } |
673a394b | 996 | |
2ef7eeaa EA |
997 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
998 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
999 | |
1000 | /* Silently promote "you're not bound, there was nothing to do" | |
1001 | * to success, since the client was just asking us to | |
1002 | * make sure everything was done. | |
1003 | */ | |
1004 | if (ret == -EINVAL) | |
1005 | ret = 0; | |
2ef7eeaa | 1006 | } else { |
e47c68e9 | 1007 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1008 | } |
1009 | ||
05394f39 | 1010 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1011 | unlock: |
673a394b EA |
1012 | mutex_unlock(&dev->struct_mutex); |
1013 | return ret; | |
1014 | } | |
1015 | ||
1016 | /** | |
1017 | * Called when user space has done writes to this buffer | |
1018 | */ | |
1019 | int | |
1020 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1021 | struct drm_file *file) |
673a394b EA |
1022 | { |
1023 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1024 | struct drm_i915_gem_object *obj; |
673a394b EA |
1025 | int ret = 0; |
1026 | ||
1027 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1028 | return -ENODEV; | |
1029 | ||
76c1dec1 | 1030 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1031 | if (ret) |
76c1dec1 | 1032 | return ret; |
1d7cfea1 | 1033 | |
05394f39 | 1034 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1035 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1036 | ret = -ENOENT; |
1037 | goto unlock; | |
673a394b EA |
1038 | } |
1039 | ||
673a394b | 1040 | /* Pinned buffers may be scanout, so flush the cache */ |
05394f39 | 1041 | if (obj->pin_count) |
e47c68e9 EA |
1042 | i915_gem_object_flush_cpu_write_domain(obj); |
1043 | ||
05394f39 | 1044 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1045 | unlock: |
673a394b EA |
1046 | mutex_unlock(&dev->struct_mutex); |
1047 | return ret; | |
1048 | } | |
1049 | ||
1050 | /** | |
1051 | * Maps the contents of an object, returning the address it is mapped | |
1052 | * into. | |
1053 | * | |
1054 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1055 | * imply a ref on the object itself. | |
1056 | */ | |
1057 | int | |
1058 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1059 | struct drm_file *file) |
673a394b EA |
1060 | { |
1061 | struct drm_i915_gem_mmap *args = data; | |
1062 | struct drm_gem_object *obj; | |
673a394b EA |
1063 | unsigned long addr; |
1064 | ||
1065 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1066 | return -ENODEV; | |
1067 | ||
05394f39 | 1068 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1069 | if (obj == NULL) |
bf79cb91 | 1070 | return -ENOENT; |
673a394b | 1071 | |
673a394b EA |
1072 | down_write(¤t->mm->mmap_sem); |
1073 | addr = do_mmap(obj->filp, 0, args->size, | |
1074 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
1075 | args->offset); | |
1076 | up_write(¤t->mm->mmap_sem); | |
bc9025bd | 1077 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1078 | if (IS_ERR((void *)addr)) |
1079 | return addr; | |
1080 | ||
1081 | args->addr_ptr = (uint64_t) addr; | |
1082 | ||
1083 | return 0; | |
1084 | } | |
1085 | ||
de151cf6 JB |
1086 | /** |
1087 | * i915_gem_fault - fault a page into the GTT | |
1088 | * vma: VMA in question | |
1089 | * vmf: fault info | |
1090 | * | |
1091 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1092 | * from userspace. The fault handler takes care of binding the object to | |
1093 | * the GTT (if needed), allocating and programming a fence register (again, | |
1094 | * only if needed based on whether the old reg is still valid or the object | |
1095 | * is tiled) and inserting a new PTE into the faulting process. | |
1096 | * | |
1097 | * Note that the faulting process may involve evicting existing objects | |
1098 | * from the GTT and/or fence registers to make room. So performance may | |
1099 | * suffer if the GTT working set is large or there are few fence registers | |
1100 | * left. | |
1101 | */ | |
1102 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1103 | { | |
05394f39 CW |
1104 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1105 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1106 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1107 | pgoff_t page_offset; |
1108 | unsigned long pfn; | |
1109 | int ret = 0; | |
0f973f27 | 1110 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1111 | |
1112 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1113 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1114 | PAGE_SHIFT; | |
1115 | ||
d9bc7e9f CW |
1116 | ret = i915_mutex_lock_interruptible(dev); |
1117 | if (ret) | |
1118 | goto out; | |
a00b10c3 | 1119 | |
db53a302 CW |
1120 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1121 | ||
d9bc7e9f | 1122 | /* Now bind it into the GTT if needed */ |
919926ae CW |
1123 | if (!obj->map_and_fenceable) { |
1124 | ret = i915_gem_object_unbind(obj); | |
1125 | if (ret) | |
1126 | goto unlock; | |
a00b10c3 | 1127 | } |
05394f39 | 1128 | if (!obj->gtt_space) { |
75e9e915 | 1129 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
c715089f CW |
1130 | if (ret) |
1131 | goto unlock; | |
de151cf6 | 1132 | |
e92d03bf EA |
1133 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1134 | if (ret) | |
1135 | goto unlock; | |
1136 | } | |
4a684a41 | 1137 | |
74898d7e DV |
1138 | if (!obj->has_global_gtt_mapping) |
1139 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
1140 | ||
d9e86c0e CW |
1141 | if (obj->tiling_mode == I915_TILING_NONE) |
1142 | ret = i915_gem_object_put_fence(obj); | |
1143 | else | |
ce453d81 | 1144 | ret = i915_gem_object_get_fence(obj, NULL); |
d9e86c0e CW |
1145 | if (ret) |
1146 | goto unlock; | |
de151cf6 | 1147 | |
05394f39 CW |
1148 | if (i915_gem_object_is_inactive(obj)) |
1149 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
7d1c4804 | 1150 | |
6299f992 CW |
1151 | obj->fault_mappable = true; |
1152 | ||
05394f39 | 1153 | pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) + |
de151cf6 JB |
1154 | page_offset; |
1155 | ||
1156 | /* Finally, remap it using the new GTT offset */ | |
1157 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1158 | unlock: |
de151cf6 | 1159 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1160 | out: |
de151cf6 | 1161 | switch (ret) { |
d9bc7e9f | 1162 | case -EIO: |
045e769a | 1163 | case -EAGAIN: |
d9bc7e9f CW |
1164 | /* Give the error handler a chance to run and move the |
1165 | * objects off the GPU active list. Next time we service the | |
1166 | * fault, we should be able to transition the page into the | |
1167 | * GTT without touching the GPU (and so avoid further | |
1168 | * EIO/EGAIN). If the GPU is wedged, then there is no issue | |
1169 | * with coherency, just lost writes. | |
1170 | */ | |
045e769a | 1171 | set_need_resched(); |
c715089f CW |
1172 | case 0: |
1173 | case -ERESTARTSYS: | |
bed636ab | 1174 | case -EINTR: |
c715089f | 1175 | return VM_FAULT_NOPAGE; |
de151cf6 | 1176 | case -ENOMEM: |
de151cf6 | 1177 | return VM_FAULT_OOM; |
de151cf6 | 1178 | default: |
c715089f | 1179 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1180 | } |
1181 | } | |
1182 | ||
901782b2 CW |
1183 | /** |
1184 | * i915_gem_release_mmap - remove physical page mappings | |
1185 | * @obj: obj in question | |
1186 | * | |
af901ca1 | 1187 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1188 | * relinquish ownership of the pages back to the system. |
1189 | * | |
1190 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1191 | * object through the GTT and then lose the fence register due to | |
1192 | * resource pressure. Similarly if the object has been moved out of the | |
1193 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1194 | * mapping will then trigger a page fault on the next user access, allowing | |
1195 | * fixup by i915_gem_fault(). | |
1196 | */ | |
d05ca301 | 1197 | void |
05394f39 | 1198 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1199 | { |
6299f992 CW |
1200 | if (!obj->fault_mappable) |
1201 | return; | |
901782b2 | 1202 | |
f6e47884 CW |
1203 | if (obj->base.dev->dev_mapping) |
1204 | unmap_mapping_range(obj->base.dev->dev_mapping, | |
1205 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, | |
1206 | obj->base.size, 1); | |
fb7d516a | 1207 | |
6299f992 | 1208 | obj->fault_mappable = false; |
901782b2 CW |
1209 | } |
1210 | ||
92b88aeb | 1211 | static uint32_t |
e28f8711 | 1212 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1213 | { |
e28f8711 | 1214 | uint32_t gtt_size; |
92b88aeb CW |
1215 | |
1216 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1217 | tiling_mode == I915_TILING_NONE) |
1218 | return size; | |
92b88aeb CW |
1219 | |
1220 | /* Previous chips need a power-of-two fence region when tiling */ | |
1221 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1222 | gtt_size = 1024*1024; |
92b88aeb | 1223 | else |
e28f8711 | 1224 | gtt_size = 512*1024; |
92b88aeb | 1225 | |
e28f8711 CW |
1226 | while (gtt_size < size) |
1227 | gtt_size <<= 1; | |
92b88aeb | 1228 | |
e28f8711 | 1229 | return gtt_size; |
92b88aeb CW |
1230 | } |
1231 | ||
de151cf6 JB |
1232 | /** |
1233 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1234 | * @obj: object to check | |
1235 | * | |
1236 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1237 | * potential fence register mapping. |
de151cf6 JB |
1238 | */ |
1239 | static uint32_t | |
e28f8711 CW |
1240 | i915_gem_get_gtt_alignment(struct drm_device *dev, |
1241 | uint32_t size, | |
1242 | int tiling_mode) | |
de151cf6 | 1243 | { |
de151cf6 JB |
1244 | /* |
1245 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1246 | * if a fence register is needed for the object. | |
1247 | */ | |
a00b10c3 | 1248 | if (INTEL_INFO(dev)->gen >= 4 || |
e28f8711 | 1249 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1250 | return 4096; |
1251 | ||
a00b10c3 CW |
1252 | /* |
1253 | * Previous chips need to be aligned to the size of the smallest | |
1254 | * fence register that can contain the object. | |
1255 | */ | |
e28f8711 | 1256 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1257 | } |
1258 | ||
5e783301 DV |
1259 | /** |
1260 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an | |
1261 | * unfenced object | |
e28f8711 CW |
1262 | * @dev: the device |
1263 | * @size: size of the object | |
1264 | * @tiling_mode: tiling mode of the object | |
5e783301 DV |
1265 | * |
1266 | * Return the required GTT alignment for an object, only taking into account | |
1267 | * unfenced tiled surface requirements. | |
1268 | */ | |
467cffba | 1269 | uint32_t |
e28f8711 CW |
1270 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
1271 | uint32_t size, | |
1272 | int tiling_mode) | |
5e783301 | 1273 | { |
5e783301 DV |
1274 | /* |
1275 | * Minimum alignment is 4k (GTT page size) for sane hw. | |
1276 | */ | |
1277 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || | |
e28f8711 | 1278 | tiling_mode == I915_TILING_NONE) |
5e783301 DV |
1279 | return 4096; |
1280 | ||
e28f8711 CW |
1281 | /* Previous hardware however needs to be aligned to a power-of-two |
1282 | * tile height. The simplest method for determining this is to reuse | |
1283 | * the power-of-tile object size. | |
5e783301 | 1284 | */ |
e28f8711 | 1285 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
5e783301 DV |
1286 | } |
1287 | ||
de151cf6 | 1288 | int |
ff72145b DA |
1289 | i915_gem_mmap_gtt(struct drm_file *file, |
1290 | struct drm_device *dev, | |
1291 | uint32_t handle, | |
1292 | uint64_t *offset) | |
de151cf6 | 1293 | { |
da761a6e | 1294 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1295 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1296 | int ret; |
1297 | ||
1298 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1299 | return -ENODEV; | |
1300 | ||
76c1dec1 | 1301 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1302 | if (ret) |
76c1dec1 | 1303 | return ret; |
de151cf6 | 1304 | |
ff72145b | 1305 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1306 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1307 | ret = -ENOENT; |
1308 | goto unlock; | |
1309 | } | |
de151cf6 | 1310 | |
05394f39 | 1311 | if (obj->base.size > dev_priv->mm.gtt_mappable_end) { |
da761a6e | 1312 | ret = -E2BIG; |
ff56b0bc | 1313 | goto out; |
da761a6e CW |
1314 | } |
1315 | ||
05394f39 | 1316 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1317 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1318 | ret = -EINVAL; |
1319 | goto out; | |
ab18282d CW |
1320 | } |
1321 | ||
05394f39 | 1322 | if (!obj->base.map_list.map) { |
b464e9a2 | 1323 | ret = drm_gem_create_mmap_offset(&obj->base); |
1d7cfea1 CW |
1324 | if (ret) |
1325 | goto out; | |
de151cf6 JB |
1326 | } |
1327 | ||
ff72145b | 1328 | *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1329 | |
1d7cfea1 | 1330 | out: |
05394f39 | 1331 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1332 | unlock: |
de151cf6 | 1333 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1334 | return ret; |
de151cf6 JB |
1335 | } |
1336 | ||
ff72145b DA |
1337 | /** |
1338 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1339 | * @dev: DRM device | |
1340 | * @data: GTT mapping ioctl data | |
1341 | * @file: GEM object info | |
1342 | * | |
1343 | * Simply returns the fake offset to userspace so it can mmap it. | |
1344 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1345 | * up so we can get faults in the handler above. | |
1346 | * | |
1347 | * The fault handler will take care of binding the object into the GTT | |
1348 | * (since it may have been evicted to make room for something), allocating | |
1349 | * a fence register, and mapping the appropriate aperture address into | |
1350 | * userspace. | |
1351 | */ | |
1352 | int | |
1353 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1354 | struct drm_file *file) | |
1355 | { | |
1356 | struct drm_i915_gem_mmap_gtt *args = data; | |
1357 | ||
1358 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1359 | return -ENODEV; | |
1360 | ||
1361 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); | |
1362 | } | |
1363 | ||
1364 | ||
e5281ccd | 1365 | static int |
05394f39 | 1366 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj, |
e5281ccd CW |
1367 | gfp_t gfpmask) |
1368 | { | |
e5281ccd CW |
1369 | int page_count, i; |
1370 | struct address_space *mapping; | |
1371 | struct inode *inode; | |
1372 | struct page *page; | |
1373 | ||
1374 | /* Get the list of pages out of our struct file. They'll be pinned | |
1375 | * at this point until we release them. | |
1376 | */ | |
05394f39 CW |
1377 | page_count = obj->base.size / PAGE_SIZE; |
1378 | BUG_ON(obj->pages != NULL); | |
1379 | obj->pages = drm_malloc_ab(page_count, sizeof(struct page *)); | |
1380 | if (obj->pages == NULL) | |
e5281ccd CW |
1381 | return -ENOMEM; |
1382 | ||
05394f39 | 1383 | inode = obj->base.filp->f_path.dentry->d_inode; |
e5281ccd | 1384 | mapping = inode->i_mapping; |
5949eac4 HD |
1385 | gfpmask |= mapping_gfp_mask(mapping); |
1386 | ||
e5281ccd | 1387 | for (i = 0; i < page_count; i++) { |
5949eac4 | 1388 | page = shmem_read_mapping_page_gfp(mapping, i, gfpmask); |
e5281ccd CW |
1389 | if (IS_ERR(page)) |
1390 | goto err_pages; | |
1391 | ||
05394f39 | 1392 | obj->pages[i] = page; |
e5281ccd CW |
1393 | } |
1394 | ||
6dacfd2f | 1395 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
1396 | i915_gem_object_do_bit_17_swizzle(obj); |
1397 | ||
1398 | return 0; | |
1399 | ||
1400 | err_pages: | |
1401 | while (i--) | |
05394f39 | 1402 | page_cache_release(obj->pages[i]); |
e5281ccd | 1403 | |
05394f39 CW |
1404 | drm_free_large(obj->pages); |
1405 | obj->pages = NULL; | |
e5281ccd CW |
1406 | return PTR_ERR(page); |
1407 | } | |
1408 | ||
5cdf5881 | 1409 | static void |
05394f39 | 1410 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1411 | { |
05394f39 | 1412 | int page_count = obj->base.size / PAGE_SIZE; |
673a394b EA |
1413 | int i; |
1414 | ||
05394f39 | 1415 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1416 | |
6dacfd2f | 1417 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1418 | i915_gem_object_save_bit_17_swizzle(obj); |
1419 | ||
05394f39 CW |
1420 | if (obj->madv == I915_MADV_DONTNEED) |
1421 | obj->dirty = 0; | |
3ef94daa CW |
1422 | |
1423 | for (i = 0; i < page_count; i++) { | |
05394f39 CW |
1424 | if (obj->dirty) |
1425 | set_page_dirty(obj->pages[i]); | |
3ef94daa | 1426 | |
05394f39 CW |
1427 | if (obj->madv == I915_MADV_WILLNEED) |
1428 | mark_page_accessed(obj->pages[i]); | |
3ef94daa | 1429 | |
05394f39 | 1430 | page_cache_release(obj->pages[i]); |
3ef94daa | 1431 | } |
05394f39 | 1432 | obj->dirty = 0; |
673a394b | 1433 | |
05394f39 CW |
1434 | drm_free_large(obj->pages); |
1435 | obj->pages = NULL; | |
673a394b EA |
1436 | } |
1437 | ||
54cf91dc | 1438 | void |
05394f39 | 1439 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
1ec14ad3 CW |
1440 | struct intel_ring_buffer *ring, |
1441 | u32 seqno) | |
673a394b | 1442 | { |
05394f39 | 1443 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1444 | struct drm_i915_private *dev_priv = dev->dev_private; |
617dbe27 | 1445 | |
852835f3 | 1446 | BUG_ON(ring == NULL); |
05394f39 | 1447 | obj->ring = ring; |
673a394b EA |
1448 | |
1449 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1450 | if (!obj->active) { |
1451 | drm_gem_object_reference(&obj->base); | |
1452 | obj->active = 1; | |
673a394b | 1453 | } |
e35a41de | 1454 | |
673a394b | 1455 | /* Move from whatever list we were on to the tail of execution. */ |
05394f39 CW |
1456 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
1457 | list_move_tail(&obj->ring_list, &ring->active_list); | |
caea7476 | 1458 | |
05394f39 | 1459 | obj->last_rendering_seqno = seqno; |
caea7476 CW |
1460 | if (obj->fenced_gpu_access) { |
1461 | struct drm_i915_fence_reg *reg; | |
1462 | ||
1463 | BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE); | |
1464 | ||
1465 | obj->last_fenced_seqno = seqno; | |
1466 | obj->last_fenced_ring = ring; | |
1467 | ||
1468 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1469 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); | |
1470 | } | |
1471 | } | |
1472 | ||
1473 | static void | |
1474 | i915_gem_object_move_off_active(struct drm_i915_gem_object *obj) | |
1475 | { | |
1476 | list_del_init(&obj->ring_list); | |
1477 | obj->last_rendering_seqno = 0; | |
673a394b EA |
1478 | } |
1479 | ||
ce44b0ea | 1480 | static void |
05394f39 | 1481 | i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj) |
ce44b0ea | 1482 | { |
05394f39 | 1483 | struct drm_device *dev = obj->base.dev; |
ce44b0ea | 1484 | drm_i915_private_t *dev_priv = dev->dev_private; |
ce44b0ea | 1485 | |
05394f39 CW |
1486 | BUG_ON(!obj->active); |
1487 | list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list); | |
caea7476 CW |
1488 | |
1489 | i915_gem_object_move_off_active(obj); | |
1490 | } | |
1491 | ||
1492 | static void | |
1493 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) | |
1494 | { | |
1495 | struct drm_device *dev = obj->base.dev; | |
1496 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1497 | ||
1498 | if (obj->pin_count != 0) | |
1499 | list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list); | |
1500 | else | |
1501 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
1502 | ||
1503 | BUG_ON(!list_empty(&obj->gpu_write_list)); | |
1504 | BUG_ON(!obj->active); | |
1505 | obj->ring = NULL; | |
1506 | ||
1507 | i915_gem_object_move_off_active(obj); | |
1508 | obj->fenced_gpu_access = false; | |
caea7476 CW |
1509 | |
1510 | obj->active = 0; | |
87ca9c8a | 1511 | obj->pending_gpu_write = false; |
caea7476 CW |
1512 | drm_gem_object_unreference(&obj->base); |
1513 | ||
1514 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 1515 | } |
673a394b | 1516 | |
963b4836 CW |
1517 | /* Immediately discard the backing storage */ |
1518 | static void | |
05394f39 | 1519 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
963b4836 | 1520 | { |
bb6baf76 | 1521 | struct inode *inode; |
963b4836 | 1522 | |
ae9fed6b CW |
1523 | /* Our goal here is to return as much of the memory as |
1524 | * is possible back to the system as we are called from OOM. | |
1525 | * To do this we must instruct the shmfs to drop all of its | |
e2377fe0 | 1526 | * backing pages, *now*. |
ae9fed6b | 1527 | */ |
05394f39 | 1528 | inode = obj->base.filp->f_path.dentry->d_inode; |
e2377fe0 | 1529 | shmem_truncate_range(inode, 0, (loff_t)-1); |
bb6baf76 | 1530 | |
a14917ee CW |
1531 | if (obj->base.map_list.map) |
1532 | drm_gem_free_mmap_offset(&obj->base); | |
1533 | ||
05394f39 | 1534 | obj->madv = __I915_MADV_PURGED; |
963b4836 CW |
1535 | } |
1536 | ||
1537 | static inline int | |
05394f39 | 1538 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
963b4836 | 1539 | { |
05394f39 | 1540 | return obj->madv == I915_MADV_DONTNEED; |
963b4836 CW |
1541 | } |
1542 | ||
63560396 | 1543 | static void |
db53a302 CW |
1544 | i915_gem_process_flushing_list(struct intel_ring_buffer *ring, |
1545 | uint32_t flush_domains) | |
63560396 | 1546 | { |
05394f39 | 1547 | struct drm_i915_gem_object *obj, *next; |
63560396 | 1548 | |
05394f39 | 1549 | list_for_each_entry_safe(obj, next, |
64193406 | 1550 | &ring->gpu_write_list, |
63560396 | 1551 | gpu_write_list) { |
05394f39 CW |
1552 | if (obj->base.write_domain & flush_domains) { |
1553 | uint32_t old_write_domain = obj->base.write_domain; | |
63560396 | 1554 | |
05394f39 CW |
1555 | obj->base.write_domain = 0; |
1556 | list_del_init(&obj->gpu_write_list); | |
1ec14ad3 | 1557 | i915_gem_object_move_to_active(obj, ring, |
db53a302 | 1558 | i915_gem_next_request_seqno(ring)); |
63560396 | 1559 | |
63560396 | 1560 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 1561 | obj->base.read_domains, |
63560396 DV |
1562 | old_write_domain); |
1563 | } | |
1564 | } | |
1565 | } | |
8187a2b7 | 1566 | |
53d227f2 DV |
1567 | static u32 |
1568 | i915_gem_get_seqno(struct drm_device *dev) | |
1569 | { | |
1570 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1571 | u32 seqno = dev_priv->next_seqno; | |
1572 | ||
1573 | /* reserve 0 for non-seqno */ | |
1574 | if (++dev_priv->next_seqno == 0) | |
1575 | dev_priv->next_seqno = 1; | |
1576 | ||
1577 | return seqno; | |
1578 | } | |
1579 | ||
1580 | u32 | |
1581 | i915_gem_next_request_seqno(struct intel_ring_buffer *ring) | |
1582 | { | |
1583 | if (ring->outstanding_lazy_request == 0) | |
1584 | ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev); | |
1585 | ||
1586 | return ring->outstanding_lazy_request; | |
1587 | } | |
1588 | ||
3cce469c | 1589 | int |
db53a302 | 1590 | i915_add_request(struct intel_ring_buffer *ring, |
f787a5f5 | 1591 | struct drm_file *file, |
db53a302 | 1592 | struct drm_i915_gem_request *request) |
673a394b | 1593 | { |
db53a302 | 1594 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
673a394b | 1595 | uint32_t seqno; |
a71d8d94 | 1596 | u32 request_ring_position; |
673a394b | 1597 | int was_empty; |
3cce469c CW |
1598 | int ret; |
1599 | ||
1600 | BUG_ON(request == NULL); | |
53d227f2 | 1601 | seqno = i915_gem_next_request_seqno(ring); |
673a394b | 1602 | |
a71d8d94 CW |
1603 | /* Record the position of the start of the request so that |
1604 | * should we detect the updated seqno part-way through the | |
1605 | * GPU processing the request, we never over-estimate the | |
1606 | * position of the head. | |
1607 | */ | |
1608 | request_ring_position = intel_ring_get_tail(ring); | |
1609 | ||
3cce469c CW |
1610 | ret = ring->add_request(ring, &seqno); |
1611 | if (ret) | |
1612 | return ret; | |
673a394b | 1613 | |
db53a302 | 1614 | trace_i915_gem_request_add(ring, seqno); |
673a394b EA |
1615 | |
1616 | request->seqno = seqno; | |
852835f3 | 1617 | request->ring = ring; |
a71d8d94 | 1618 | request->tail = request_ring_position; |
673a394b | 1619 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1620 | was_empty = list_empty(&ring->request_list); |
1621 | list_add_tail(&request->list, &ring->request_list); | |
1622 | ||
db53a302 CW |
1623 | if (file) { |
1624 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1625 | ||
1c25595f | 1626 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 1627 | request->file_priv = file_priv; |
b962442e | 1628 | list_add_tail(&request->client_list, |
f787a5f5 | 1629 | &file_priv->mm.request_list); |
1c25595f | 1630 | spin_unlock(&file_priv->mm.lock); |
b962442e | 1631 | } |
673a394b | 1632 | |
5391d0cf | 1633 | ring->outstanding_lazy_request = 0; |
db53a302 | 1634 | |
f65d9421 | 1635 | if (!dev_priv->mm.suspended) { |
3e0dc6b0 BW |
1636 | if (i915_enable_hangcheck) { |
1637 | mod_timer(&dev_priv->hangcheck_timer, | |
1638 | jiffies + | |
1639 | msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
1640 | } | |
f65d9421 | 1641 | if (was_empty) |
b3b079db CW |
1642 | queue_delayed_work(dev_priv->wq, |
1643 | &dev_priv->mm.retire_work, HZ); | |
f65d9421 | 1644 | } |
3cce469c | 1645 | return 0; |
673a394b EA |
1646 | } |
1647 | ||
f787a5f5 CW |
1648 | static inline void |
1649 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 1650 | { |
1c25595f | 1651 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 1652 | |
1c25595f CW |
1653 | if (!file_priv) |
1654 | return; | |
1c5d22f7 | 1655 | |
1c25595f | 1656 | spin_lock(&file_priv->mm.lock); |
09bfa517 HRK |
1657 | if (request->file_priv) { |
1658 | list_del(&request->client_list); | |
1659 | request->file_priv = NULL; | |
1660 | } | |
1c25595f | 1661 | spin_unlock(&file_priv->mm.lock); |
673a394b | 1662 | } |
673a394b | 1663 | |
dfaae392 CW |
1664 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
1665 | struct intel_ring_buffer *ring) | |
9375e446 | 1666 | { |
dfaae392 CW |
1667 | while (!list_empty(&ring->request_list)) { |
1668 | struct drm_i915_gem_request *request; | |
673a394b | 1669 | |
dfaae392 CW |
1670 | request = list_first_entry(&ring->request_list, |
1671 | struct drm_i915_gem_request, | |
1672 | list); | |
de151cf6 | 1673 | |
dfaae392 | 1674 | list_del(&request->list); |
f787a5f5 | 1675 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
1676 | kfree(request); |
1677 | } | |
673a394b | 1678 | |
dfaae392 | 1679 | while (!list_empty(&ring->active_list)) { |
05394f39 | 1680 | struct drm_i915_gem_object *obj; |
9375e446 | 1681 | |
05394f39 CW |
1682 | obj = list_first_entry(&ring->active_list, |
1683 | struct drm_i915_gem_object, | |
1684 | ring_list); | |
9375e446 | 1685 | |
05394f39 CW |
1686 | obj->base.write_domain = 0; |
1687 | list_del_init(&obj->gpu_write_list); | |
1688 | i915_gem_object_move_to_inactive(obj); | |
673a394b EA |
1689 | } |
1690 | } | |
1691 | ||
312817a3 CW |
1692 | static void i915_gem_reset_fences(struct drm_device *dev) |
1693 | { | |
1694 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1695 | int i; | |
1696 | ||
4b9de737 | 1697 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 1698 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c CW |
1699 | struct drm_i915_gem_object *obj = reg->obj; |
1700 | ||
1701 | if (!obj) | |
1702 | continue; | |
1703 | ||
1704 | if (obj->tiling_mode) | |
1705 | i915_gem_release_mmap(obj); | |
1706 | ||
d9e86c0e CW |
1707 | reg->obj->fence_reg = I915_FENCE_REG_NONE; |
1708 | reg->obj->fenced_gpu_access = false; | |
1709 | reg->obj->last_fenced_seqno = 0; | |
1710 | reg->obj->last_fenced_ring = NULL; | |
1711 | i915_gem_clear_fence_reg(dev, reg); | |
312817a3 CW |
1712 | } |
1713 | } | |
1714 | ||
069efc1d | 1715 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 1716 | { |
77f01230 | 1717 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1718 | struct drm_i915_gem_object *obj; |
1ec14ad3 | 1719 | int i; |
673a394b | 1720 | |
1ec14ad3 CW |
1721 | for (i = 0; i < I915_NUM_RINGS; i++) |
1722 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]); | |
dfaae392 CW |
1723 | |
1724 | /* Remove anything from the flushing lists. The GPU cache is likely | |
1725 | * to be lost on reset along with the data, so simply move the | |
1726 | * lost bo to the inactive list. | |
1727 | */ | |
1728 | while (!list_empty(&dev_priv->mm.flushing_list)) { | |
0206e353 | 1729 | obj = list_first_entry(&dev_priv->mm.flushing_list, |
05394f39 CW |
1730 | struct drm_i915_gem_object, |
1731 | mm_list); | |
dfaae392 | 1732 | |
05394f39 CW |
1733 | obj->base.write_domain = 0; |
1734 | list_del_init(&obj->gpu_write_list); | |
1735 | i915_gem_object_move_to_inactive(obj); | |
dfaae392 CW |
1736 | } |
1737 | ||
1738 | /* Move everything out of the GPU domains to ensure we do any | |
1739 | * necessary invalidation upon reuse. | |
1740 | */ | |
05394f39 | 1741 | list_for_each_entry(obj, |
77f01230 | 1742 | &dev_priv->mm.inactive_list, |
69dc4987 | 1743 | mm_list) |
77f01230 | 1744 | { |
05394f39 | 1745 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
77f01230 | 1746 | } |
069efc1d CW |
1747 | |
1748 | /* The fence registers are invalidated so clear them out */ | |
312817a3 | 1749 | i915_gem_reset_fences(dev); |
673a394b EA |
1750 | } |
1751 | ||
1752 | /** | |
1753 | * This function clears the request list as sequence numbers are passed. | |
1754 | */ | |
a71d8d94 | 1755 | void |
db53a302 | 1756 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 1757 | { |
673a394b | 1758 | uint32_t seqno; |
1ec14ad3 | 1759 | int i; |
673a394b | 1760 | |
db53a302 | 1761 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
1762 | return; |
1763 | ||
db53a302 | 1764 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 1765 | |
78501eac | 1766 | seqno = ring->get_seqno(ring); |
1ec14ad3 | 1767 | |
076e2c0e | 1768 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) |
1ec14ad3 CW |
1769 | if (seqno >= ring->sync_seqno[i]) |
1770 | ring->sync_seqno[i] = 0; | |
1771 | ||
852835f3 | 1772 | while (!list_empty(&ring->request_list)) { |
673a394b | 1773 | struct drm_i915_gem_request *request; |
673a394b | 1774 | |
852835f3 | 1775 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1776 | struct drm_i915_gem_request, |
1777 | list); | |
673a394b | 1778 | |
dfaae392 | 1779 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
1780 | break; |
1781 | ||
db53a302 | 1782 | trace_i915_gem_request_retire(ring, request->seqno); |
a71d8d94 CW |
1783 | /* We know the GPU must have read the request to have |
1784 | * sent us the seqno + interrupt, so use the position | |
1785 | * of tail of the request to update the last known position | |
1786 | * of the GPU head. | |
1787 | */ | |
1788 | ring->last_retired_head = request->tail; | |
b84d5f0c CW |
1789 | |
1790 | list_del(&request->list); | |
f787a5f5 | 1791 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
1792 | kfree(request); |
1793 | } | |
673a394b | 1794 | |
b84d5f0c CW |
1795 | /* Move any buffers on the active list that are no longer referenced |
1796 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1797 | */ | |
1798 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 1799 | struct drm_i915_gem_object *obj; |
b84d5f0c | 1800 | |
0206e353 | 1801 | obj = list_first_entry(&ring->active_list, |
05394f39 CW |
1802 | struct drm_i915_gem_object, |
1803 | ring_list); | |
673a394b | 1804 | |
05394f39 | 1805 | if (!i915_seqno_passed(seqno, obj->last_rendering_seqno)) |
673a394b | 1806 | break; |
b84d5f0c | 1807 | |
05394f39 | 1808 | if (obj->base.write_domain != 0) |
b84d5f0c CW |
1809 | i915_gem_object_move_to_flushing(obj); |
1810 | else | |
1811 | i915_gem_object_move_to_inactive(obj); | |
673a394b | 1812 | } |
9d34e5db | 1813 | |
db53a302 CW |
1814 | if (unlikely(ring->trace_irq_seqno && |
1815 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 1816 | ring->irq_put(ring); |
db53a302 | 1817 | ring->trace_irq_seqno = 0; |
9d34e5db | 1818 | } |
23bc5982 | 1819 | |
db53a302 | 1820 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
1821 | } |
1822 | ||
b09a1fec CW |
1823 | void |
1824 | i915_gem_retire_requests(struct drm_device *dev) | |
1825 | { | |
1826 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1827 | int i; |
b09a1fec | 1828 | |
be72615b | 1829 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
05394f39 | 1830 | struct drm_i915_gem_object *obj, *next; |
be72615b CW |
1831 | |
1832 | /* We must be careful that during unbind() we do not | |
1833 | * accidentally infinitely recurse into retire requests. | |
1834 | * Currently: | |
1835 | * retire -> free -> unbind -> wait -> retire_ring | |
1836 | */ | |
05394f39 | 1837 | list_for_each_entry_safe(obj, next, |
be72615b | 1838 | &dev_priv->mm.deferred_free_list, |
69dc4987 | 1839 | mm_list) |
05394f39 | 1840 | i915_gem_free_object_tail(obj); |
be72615b CW |
1841 | } |
1842 | ||
1ec14ad3 | 1843 | for (i = 0; i < I915_NUM_RINGS; i++) |
db53a302 | 1844 | i915_gem_retire_requests_ring(&dev_priv->ring[i]); |
b09a1fec CW |
1845 | } |
1846 | ||
75ef9da2 | 1847 | static void |
673a394b EA |
1848 | i915_gem_retire_work_handler(struct work_struct *work) |
1849 | { | |
1850 | drm_i915_private_t *dev_priv; | |
1851 | struct drm_device *dev; | |
0a58705b CW |
1852 | bool idle; |
1853 | int i; | |
673a394b EA |
1854 | |
1855 | dev_priv = container_of(work, drm_i915_private_t, | |
1856 | mm.retire_work.work); | |
1857 | dev = dev_priv->dev; | |
1858 | ||
891b48cf CW |
1859 | /* Come back later if the device is busy... */ |
1860 | if (!mutex_trylock(&dev->struct_mutex)) { | |
1861 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
1862 | return; | |
1863 | } | |
1864 | ||
b09a1fec | 1865 | i915_gem_retire_requests(dev); |
d1b851fc | 1866 | |
0a58705b CW |
1867 | /* Send a periodic flush down the ring so we don't hold onto GEM |
1868 | * objects indefinitely. | |
1869 | */ | |
1870 | idle = true; | |
1871 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
1872 | struct intel_ring_buffer *ring = &dev_priv->ring[i]; | |
1873 | ||
1874 | if (!list_empty(&ring->gpu_write_list)) { | |
1875 | struct drm_i915_gem_request *request; | |
1876 | int ret; | |
1877 | ||
db53a302 CW |
1878 | ret = i915_gem_flush_ring(ring, |
1879 | 0, I915_GEM_GPU_DOMAINS); | |
0a58705b CW |
1880 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
1881 | if (ret || request == NULL || | |
db53a302 | 1882 | i915_add_request(ring, NULL, request)) |
0a58705b CW |
1883 | kfree(request); |
1884 | } | |
1885 | ||
1886 | idle &= list_empty(&ring->request_list); | |
1887 | } | |
1888 | ||
1889 | if (!dev_priv->mm.suspended && !idle) | |
9c9fe1f8 | 1890 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
0a58705b | 1891 | |
673a394b EA |
1892 | mutex_unlock(&dev->struct_mutex); |
1893 | } | |
1894 | ||
db53a302 CW |
1895 | /** |
1896 | * Waits for a sequence number to be signaled, and cleans up the | |
1897 | * request and object lists appropriately for that event. | |
1898 | */ | |
5a5a0c64 | 1899 | int |
db53a302 | 1900 | i915_wait_request(struct intel_ring_buffer *ring, |
b93f9cf1 BW |
1901 | uint32_t seqno, |
1902 | bool do_retire) | |
673a394b | 1903 | { |
db53a302 | 1904 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
802c7eb6 | 1905 | u32 ier; |
673a394b EA |
1906 | int ret = 0; |
1907 | ||
1908 | BUG_ON(seqno == 0); | |
1909 | ||
d9bc7e9f CW |
1910 | if (atomic_read(&dev_priv->mm.wedged)) { |
1911 | struct completion *x = &dev_priv->error_completion; | |
1912 | bool recovery_complete; | |
1913 | unsigned long flags; | |
1914 | ||
1915 | /* Give the error handler a chance to run. */ | |
1916 | spin_lock_irqsave(&x->wait.lock, flags); | |
1917 | recovery_complete = x->done > 0; | |
1918 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
1919 | ||
1920 | return recovery_complete ? -EIO : -EAGAIN; | |
1921 | } | |
30dbf0c0 | 1922 | |
5d97eb69 | 1923 | if (seqno == ring->outstanding_lazy_request) { |
3cce469c CW |
1924 | struct drm_i915_gem_request *request; |
1925 | ||
1926 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
1927 | if (request == NULL) | |
e35a41de | 1928 | return -ENOMEM; |
3cce469c | 1929 | |
db53a302 | 1930 | ret = i915_add_request(ring, NULL, request); |
3cce469c CW |
1931 | if (ret) { |
1932 | kfree(request); | |
1933 | return ret; | |
1934 | } | |
1935 | ||
1936 | seqno = request->seqno; | |
e35a41de | 1937 | } |
ffed1d09 | 1938 | |
78501eac | 1939 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
db53a302 | 1940 | if (HAS_PCH_SPLIT(ring->dev)) |
036a4a7d ZW |
1941 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
1942 | else | |
1943 | ier = I915_READ(IER); | |
802c7eb6 JB |
1944 | if (!ier) { |
1945 | DRM_ERROR("something (likely vbetool) disabled " | |
1946 | "interrupts, re-enabling\n"); | |
f01c22fd CW |
1947 | ring->dev->driver->irq_preinstall(ring->dev); |
1948 | ring->dev->driver->irq_postinstall(ring->dev); | |
802c7eb6 JB |
1949 | } |
1950 | ||
db53a302 | 1951 | trace_i915_gem_request_wait_begin(ring, seqno); |
1c5d22f7 | 1952 | |
b2223497 | 1953 | ring->waiting_seqno = seqno; |
b13c2b96 | 1954 | if (ring->irq_get(ring)) { |
ce453d81 | 1955 | if (dev_priv->mm.interruptible) |
b13c2b96 CW |
1956 | ret = wait_event_interruptible(ring->irq_queue, |
1957 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
1958 | || atomic_read(&dev_priv->mm.wedged)); | |
1959 | else | |
1960 | wait_event(ring->irq_queue, | |
1961 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
1962 | || atomic_read(&dev_priv->mm.wedged)); | |
1963 | ||
1964 | ring->irq_put(ring); | |
e959b5db EA |
1965 | } else if (wait_for_atomic(i915_seqno_passed(ring->get_seqno(ring), |
1966 | seqno) || | |
1967 | atomic_read(&dev_priv->mm.wedged), 3000)) | |
b5ba177d | 1968 | ret = -EBUSY; |
b2223497 | 1969 | ring->waiting_seqno = 0; |
1c5d22f7 | 1970 | |
db53a302 | 1971 | trace_i915_gem_request_wait_end(ring, seqno); |
673a394b | 1972 | } |
ba1234d1 | 1973 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 | 1974 | ret = -EAGAIN; |
673a394b | 1975 | |
673a394b EA |
1976 | /* Directly dispatch request retiring. While we have the work queue |
1977 | * to handle this, the waiter on a request often wants an associated | |
1978 | * buffer to have made it to the inactive list, and we would need | |
1979 | * a separate wait queue to handle that. | |
1980 | */ | |
b93f9cf1 | 1981 | if (ret == 0 && do_retire) |
db53a302 | 1982 | i915_gem_retire_requests_ring(ring); |
673a394b EA |
1983 | |
1984 | return ret; | |
1985 | } | |
1986 | ||
673a394b EA |
1987 | /** |
1988 | * Ensures that all rendering to the object has completed and the object is | |
1989 | * safe to unbind from the GTT or access from the CPU. | |
1990 | */ | |
54cf91dc | 1991 | int |
ce453d81 | 1992 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj) |
673a394b | 1993 | { |
673a394b EA |
1994 | int ret; |
1995 | ||
e47c68e9 EA |
1996 | /* This function only exists to support waiting for existing rendering, |
1997 | * not for emitting required flushes. | |
673a394b | 1998 | */ |
05394f39 | 1999 | BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
2000 | |
2001 | /* If there is rendering queued on the buffer being evicted, wait for | |
2002 | * it. | |
2003 | */ | |
05394f39 | 2004 | if (obj->active) { |
b93f9cf1 BW |
2005 | ret = i915_wait_request(obj->ring, obj->last_rendering_seqno, |
2006 | true); | |
2cf34d7b | 2007 | if (ret) |
673a394b EA |
2008 | return ret; |
2009 | } | |
2010 | ||
2011 | return 0; | |
2012 | } | |
2013 | ||
b5ffc9bc CW |
2014 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2015 | { | |
2016 | u32 old_write_domain, old_read_domains; | |
2017 | ||
b5ffc9bc CW |
2018 | /* Act a barrier for all accesses through the GTT */ |
2019 | mb(); | |
2020 | ||
2021 | /* Force a pagefault for domain tracking on next user access */ | |
2022 | i915_gem_release_mmap(obj); | |
2023 | ||
b97c3d9c KP |
2024 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2025 | return; | |
2026 | ||
b5ffc9bc CW |
2027 | old_read_domains = obj->base.read_domains; |
2028 | old_write_domain = obj->base.write_domain; | |
2029 | ||
2030 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2031 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2032 | ||
2033 | trace_i915_gem_object_change_domain(obj, | |
2034 | old_read_domains, | |
2035 | old_write_domain); | |
2036 | } | |
2037 | ||
673a394b EA |
2038 | /** |
2039 | * Unbinds an object from the GTT aperture. | |
2040 | */ | |
0f973f27 | 2041 | int |
05394f39 | 2042 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
673a394b | 2043 | { |
7bddb01f | 2044 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
673a394b EA |
2045 | int ret = 0; |
2046 | ||
05394f39 | 2047 | if (obj->gtt_space == NULL) |
673a394b EA |
2048 | return 0; |
2049 | ||
05394f39 | 2050 | if (obj->pin_count != 0) { |
673a394b EA |
2051 | DRM_ERROR("Attempting to unbind pinned buffer\n"); |
2052 | return -EINVAL; | |
2053 | } | |
2054 | ||
a8198eea CW |
2055 | ret = i915_gem_object_finish_gpu(obj); |
2056 | if (ret == -ERESTARTSYS) | |
2057 | return ret; | |
2058 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2059 | * should be safe and we need to cleanup or else we might | |
2060 | * cause memory corruption through use-after-free. | |
2061 | */ | |
2062 | ||
b5ffc9bc | 2063 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2064 | |
673a394b EA |
2065 | /* Move the object to the CPU domain to ensure that |
2066 | * any possible CPU writes while it's not in the GTT | |
a8198eea | 2067 | * are flushed when we go to remap it. |
673a394b | 2068 | */ |
a8198eea CW |
2069 | if (ret == 0) |
2070 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); | |
8dc1775d | 2071 | if (ret == -ERESTARTSYS) |
673a394b | 2072 | return ret; |
812ed492 | 2073 | if (ret) { |
a8198eea CW |
2074 | /* In the event of a disaster, abandon all caches and |
2075 | * hope for the best. | |
2076 | */ | |
812ed492 | 2077 | i915_gem_clflush_object(obj); |
05394f39 | 2078 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
812ed492 | 2079 | } |
673a394b | 2080 | |
96b47b65 | 2081 | /* release the fence reg _after_ flushing */ |
d9e86c0e CW |
2082 | ret = i915_gem_object_put_fence(obj); |
2083 | if (ret == -ERESTARTSYS) | |
2084 | return ret; | |
96b47b65 | 2085 | |
db53a302 CW |
2086 | trace_i915_gem_object_unbind(obj); |
2087 | ||
74898d7e DV |
2088 | if (obj->has_global_gtt_mapping) |
2089 | i915_gem_gtt_unbind_object(obj); | |
7bddb01f DV |
2090 | if (obj->has_aliasing_ppgtt_mapping) { |
2091 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); | |
2092 | obj->has_aliasing_ppgtt_mapping = 0; | |
2093 | } | |
74163907 | 2094 | i915_gem_gtt_finish_object(obj); |
7bddb01f | 2095 | |
e5281ccd | 2096 | i915_gem_object_put_pages_gtt(obj); |
673a394b | 2097 | |
6299f992 | 2098 | list_del_init(&obj->gtt_list); |
05394f39 | 2099 | list_del_init(&obj->mm_list); |
75e9e915 | 2100 | /* Avoid an unnecessary call to unbind on rebind. */ |
05394f39 | 2101 | obj->map_and_fenceable = true; |
673a394b | 2102 | |
05394f39 CW |
2103 | drm_mm_put_block(obj->gtt_space); |
2104 | obj->gtt_space = NULL; | |
2105 | obj->gtt_offset = 0; | |
673a394b | 2106 | |
05394f39 | 2107 | if (i915_gem_object_is_purgeable(obj)) |
963b4836 CW |
2108 | i915_gem_object_truncate(obj); |
2109 | ||
8dc1775d | 2110 | return ret; |
673a394b EA |
2111 | } |
2112 | ||
88241785 | 2113 | int |
db53a302 | 2114 | i915_gem_flush_ring(struct intel_ring_buffer *ring, |
54cf91dc CW |
2115 | uint32_t invalidate_domains, |
2116 | uint32_t flush_domains) | |
2117 | { | |
88241785 CW |
2118 | int ret; |
2119 | ||
36d527de CW |
2120 | if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0) |
2121 | return 0; | |
2122 | ||
db53a302 CW |
2123 | trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains); |
2124 | ||
88241785 CW |
2125 | ret = ring->flush(ring, invalidate_domains, flush_domains); |
2126 | if (ret) | |
2127 | return ret; | |
2128 | ||
36d527de CW |
2129 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
2130 | i915_gem_process_flushing_list(ring, flush_domains); | |
2131 | ||
88241785 | 2132 | return 0; |
54cf91dc CW |
2133 | } |
2134 | ||
b93f9cf1 | 2135 | static int i915_ring_idle(struct intel_ring_buffer *ring, bool do_retire) |
a56ba56c | 2136 | { |
88241785 CW |
2137 | int ret; |
2138 | ||
395b70be | 2139 | if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list)) |
64193406 CW |
2140 | return 0; |
2141 | ||
88241785 | 2142 | if (!list_empty(&ring->gpu_write_list)) { |
db53a302 | 2143 | ret = i915_gem_flush_ring(ring, |
0ac74c6b | 2144 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
88241785 CW |
2145 | if (ret) |
2146 | return ret; | |
2147 | } | |
2148 | ||
b93f9cf1 BW |
2149 | return i915_wait_request(ring, i915_gem_next_request_seqno(ring), |
2150 | do_retire); | |
a56ba56c CW |
2151 | } |
2152 | ||
b93f9cf1 | 2153 | int i915_gpu_idle(struct drm_device *dev, bool do_retire) |
4df2faf4 DV |
2154 | { |
2155 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 2156 | int ret, i; |
4df2faf4 | 2157 | |
4df2faf4 | 2158 | /* Flush everything onto the inactive list. */ |
1ec14ad3 | 2159 | for (i = 0; i < I915_NUM_RINGS; i++) { |
b93f9cf1 | 2160 | ret = i915_ring_idle(&dev_priv->ring[i], do_retire); |
1ec14ad3 CW |
2161 | if (ret) |
2162 | return ret; | |
2163 | } | |
4df2faf4 | 2164 | |
8a1a49f9 | 2165 | return 0; |
4df2faf4 DV |
2166 | } |
2167 | ||
c6642782 DV |
2168 | static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj, |
2169 | struct intel_ring_buffer *pipelined) | |
4e901fdc | 2170 | { |
05394f39 | 2171 | struct drm_device *dev = obj->base.dev; |
4e901fdc | 2172 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2173 | u32 size = obj->gtt_space->size; |
2174 | int regnum = obj->fence_reg; | |
4e901fdc EA |
2175 | uint64_t val; |
2176 | ||
05394f39 | 2177 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
c6642782 | 2178 | 0xfffff000) << 32; |
05394f39 CW |
2179 | val |= obj->gtt_offset & 0xfffff000; |
2180 | val |= (uint64_t)((obj->stride / 128) - 1) << | |
4e901fdc EA |
2181 | SANDYBRIDGE_FENCE_PITCH_SHIFT; |
2182 | ||
05394f39 | 2183 | if (obj->tiling_mode == I915_TILING_Y) |
4e901fdc EA |
2184 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
2185 | val |= I965_FENCE_REG_VALID; | |
2186 | ||
c6642782 DV |
2187 | if (pipelined) { |
2188 | int ret = intel_ring_begin(pipelined, 6); | |
2189 | if (ret) | |
2190 | return ret; | |
2191 | ||
2192 | intel_ring_emit(pipelined, MI_NOOP); | |
2193 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); | |
2194 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8); | |
2195 | intel_ring_emit(pipelined, (u32)val); | |
2196 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4); | |
2197 | intel_ring_emit(pipelined, (u32)(val >> 32)); | |
2198 | intel_ring_advance(pipelined); | |
2199 | } else | |
2200 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val); | |
2201 | ||
2202 | return 0; | |
4e901fdc EA |
2203 | } |
2204 | ||
c6642782 DV |
2205 | static int i965_write_fence_reg(struct drm_i915_gem_object *obj, |
2206 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2207 | { |
05394f39 | 2208 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2209 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2210 | u32 size = obj->gtt_space->size; |
2211 | int regnum = obj->fence_reg; | |
de151cf6 JB |
2212 | uint64_t val; |
2213 | ||
05394f39 | 2214 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
de151cf6 | 2215 | 0xfffff000) << 32; |
05394f39 CW |
2216 | val |= obj->gtt_offset & 0xfffff000; |
2217 | val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2218 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 JB |
2219 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
2220 | val |= I965_FENCE_REG_VALID; | |
2221 | ||
c6642782 DV |
2222 | if (pipelined) { |
2223 | int ret = intel_ring_begin(pipelined, 6); | |
2224 | if (ret) | |
2225 | return ret; | |
2226 | ||
2227 | intel_ring_emit(pipelined, MI_NOOP); | |
2228 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); | |
2229 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8); | |
2230 | intel_ring_emit(pipelined, (u32)val); | |
2231 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4); | |
2232 | intel_ring_emit(pipelined, (u32)(val >> 32)); | |
2233 | intel_ring_advance(pipelined); | |
2234 | } else | |
2235 | I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val); | |
2236 | ||
2237 | return 0; | |
de151cf6 JB |
2238 | } |
2239 | ||
c6642782 DV |
2240 | static int i915_write_fence_reg(struct drm_i915_gem_object *obj, |
2241 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2242 | { |
05394f39 | 2243 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2244 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 | 2245 | u32 size = obj->gtt_space->size; |
c6642782 | 2246 | u32 fence_reg, val, pitch_val; |
0f973f27 | 2247 | int tile_width; |
de151cf6 | 2248 | |
c6642782 DV |
2249 | if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
2250 | (size & -size) != size || | |
2251 | (obj->gtt_offset & (size - 1)), | |
2252 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2253 | obj->gtt_offset, obj->map_and_fenceable, size)) | |
2254 | return -EINVAL; | |
de151cf6 | 2255 | |
c6642782 | 2256 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
0f973f27 | 2257 | tile_width = 128; |
de151cf6 | 2258 | else |
0f973f27 JB |
2259 | tile_width = 512; |
2260 | ||
2261 | /* Note: pitch better be a power of two tile widths */ | |
05394f39 | 2262 | pitch_val = obj->stride / tile_width; |
0f973f27 | 2263 | pitch_val = ffs(pitch_val) - 1; |
de151cf6 | 2264 | |
05394f39 CW |
2265 | val = obj->gtt_offset; |
2266 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 | 2267 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
a00b10c3 | 2268 | val |= I915_FENCE_SIZE_BITS(size); |
de151cf6 JB |
2269 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2270 | val |= I830_FENCE_REG_VALID; | |
2271 | ||
05394f39 | 2272 | fence_reg = obj->fence_reg; |
a00b10c3 CW |
2273 | if (fence_reg < 8) |
2274 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; | |
dc529a4f | 2275 | else |
a00b10c3 | 2276 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; |
c6642782 DV |
2277 | |
2278 | if (pipelined) { | |
2279 | int ret = intel_ring_begin(pipelined, 4); | |
2280 | if (ret) | |
2281 | return ret; | |
2282 | ||
2283 | intel_ring_emit(pipelined, MI_NOOP); | |
2284 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); | |
2285 | intel_ring_emit(pipelined, fence_reg); | |
2286 | intel_ring_emit(pipelined, val); | |
2287 | intel_ring_advance(pipelined); | |
2288 | } else | |
2289 | I915_WRITE(fence_reg, val); | |
2290 | ||
2291 | return 0; | |
de151cf6 JB |
2292 | } |
2293 | ||
c6642782 DV |
2294 | static int i830_write_fence_reg(struct drm_i915_gem_object *obj, |
2295 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2296 | { |
05394f39 | 2297 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2298 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2299 | u32 size = obj->gtt_space->size; |
2300 | int regnum = obj->fence_reg; | |
de151cf6 JB |
2301 | uint32_t val; |
2302 | uint32_t pitch_val; | |
2303 | ||
c6642782 DV |
2304 | if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
2305 | (size & -size) != size || | |
2306 | (obj->gtt_offset & (size - 1)), | |
2307 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", | |
2308 | obj->gtt_offset, size)) | |
2309 | return -EINVAL; | |
de151cf6 | 2310 | |
05394f39 | 2311 | pitch_val = obj->stride / 128; |
e76a16de | 2312 | pitch_val = ffs(pitch_val) - 1; |
e76a16de | 2313 | |
05394f39 CW |
2314 | val = obj->gtt_offset; |
2315 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 | 2316 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
c6642782 | 2317 | val |= I830_FENCE_SIZE_BITS(size); |
de151cf6 JB |
2318 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2319 | val |= I830_FENCE_REG_VALID; | |
2320 | ||
c6642782 DV |
2321 | if (pipelined) { |
2322 | int ret = intel_ring_begin(pipelined, 4); | |
2323 | if (ret) | |
2324 | return ret; | |
2325 | ||
2326 | intel_ring_emit(pipelined, MI_NOOP); | |
2327 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); | |
2328 | intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4); | |
2329 | intel_ring_emit(pipelined, val); | |
2330 | intel_ring_advance(pipelined); | |
2331 | } else | |
2332 | I915_WRITE(FENCE_REG_830_0 + regnum * 4, val); | |
2333 | ||
2334 | return 0; | |
de151cf6 JB |
2335 | } |
2336 | ||
d9e86c0e CW |
2337 | static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno) |
2338 | { | |
2339 | return i915_seqno_passed(ring->get_seqno(ring), seqno); | |
2340 | } | |
2341 | ||
2342 | static int | |
2343 | i915_gem_object_flush_fence(struct drm_i915_gem_object *obj, | |
ce453d81 | 2344 | struct intel_ring_buffer *pipelined) |
d9e86c0e CW |
2345 | { |
2346 | int ret; | |
2347 | ||
2348 | if (obj->fenced_gpu_access) { | |
88241785 | 2349 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 2350 | ret = i915_gem_flush_ring(obj->last_fenced_ring, |
88241785 CW |
2351 | 0, obj->base.write_domain); |
2352 | if (ret) | |
2353 | return ret; | |
2354 | } | |
d9e86c0e CW |
2355 | |
2356 | obj->fenced_gpu_access = false; | |
2357 | } | |
2358 | ||
2359 | if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) { | |
2360 | if (!ring_passed_seqno(obj->last_fenced_ring, | |
2361 | obj->last_fenced_seqno)) { | |
db53a302 | 2362 | ret = i915_wait_request(obj->last_fenced_ring, |
b93f9cf1 BW |
2363 | obj->last_fenced_seqno, |
2364 | true); | |
d9e86c0e CW |
2365 | if (ret) |
2366 | return ret; | |
2367 | } | |
2368 | ||
2369 | obj->last_fenced_seqno = 0; | |
2370 | obj->last_fenced_ring = NULL; | |
2371 | } | |
2372 | ||
63256ec5 CW |
2373 | /* Ensure that all CPU reads are completed before installing a fence |
2374 | * and all writes before removing the fence. | |
2375 | */ | |
2376 | if (obj->base.read_domains & I915_GEM_DOMAIN_GTT) | |
2377 | mb(); | |
2378 | ||
d9e86c0e CW |
2379 | return 0; |
2380 | } | |
2381 | ||
2382 | int | |
2383 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
2384 | { | |
2385 | int ret; | |
2386 | ||
2387 | if (obj->tiling_mode) | |
2388 | i915_gem_release_mmap(obj); | |
2389 | ||
ce453d81 | 2390 | ret = i915_gem_object_flush_fence(obj, NULL); |
d9e86c0e CW |
2391 | if (ret) |
2392 | return ret; | |
2393 | ||
2394 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
2395 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1690e1eb CW |
2396 | |
2397 | WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count); | |
d9e86c0e CW |
2398 | i915_gem_clear_fence_reg(obj->base.dev, |
2399 | &dev_priv->fence_regs[obj->fence_reg]); | |
2400 | ||
2401 | obj->fence_reg = I915_FENCE_REG_NONE; | |
2402 | } | |
2403 | ||
2404 | return 0; | |
2405 | } | |
2406 | ||
2407 | static struct drm_i915_fence_reg * | |
2408 | i915_find_fence_reg(struct drm_device *dev, | |
2409 | struct intel_ring_buffer *pipelined) | |
ae3db24a | 2410 | { |
ae3db24a | 2411 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9e86c0e CW |
2412 | struct drm_i915_fence_reg *reg, *first, *avail; |
2413 | int i; | |
ae3db24a DV |
2414 | |
2415 | /* First try to find a free reg */ | |
d9e86c0e | 2416 | avail = NULL; |
ae3db24a DV |
2417 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2418 | reg = &dev_priv->fence_regs[i]; | |
2419 | if (!reg->obj) | |
d9e86c0e | 2420 | return reg; |
ae3db24a | 2421 | |
1690e1eb | 2422 | if (!reg->pin_count) |
d9e86c0e | 2423 | avail = reg; |
ae3db24a DV |
2424 | } |
2425 | ||
d9e86c0e CW |
2426 | if (avail == NULL) |
2427 | return NULL; | |
ae3db24a DV |
2428 | |
2429 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e CW |
2430 | avail = first = NULL; |
2431 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { | |
1690e1eb | 2432 | if (reg->pin_count) |
ae3db24a DV |
2433 | continue; |
2434 | ||
d9e86c0e CW |
2435 | if (first == NULL) |
2436 | first = reg; | |
2437 | ||
2438 | if (!pipelined || | |
2439 | !reg->obj->last_fenced_ring || | |
2440 | reg->obj->last_fenced_ring == pipelined) { | |
2441 | avail = reg; | |
2442 | break; | |
2443 | } | |
ae3db24a DV |
2444 | } |
2445 | ||
d9e86c0e CW |
2446 | if (avail == NULL) |
2447 | avail = first; | |
ae3db24a | 2448 | |
a00b10c3 | 2449 | return avail; |
ae3db24a DV |
2450 | } |
2451 | ||
de151cf6 | 2452 | /** |
d9e86c0e | 2453 | * i915_gem_object_get_fence - set up a fence reg for an object |
de151cf6 | 2454 | * @obj: object to map through a fence reg |
d9e86c0e CW |
2455 | * @pipelined: ring on which to queue the change, or NULL for CPU access |
2456 | * @interruptible: must we wait uninterruptibly for the register to retire? | |
de151cf6 JB |
2457 | * |
2458 | * When mapping objects through the GTT, userspace wants to be able to write | |
2459 | * to them without having to worry about swizzling if the object is tiled. | |
2460 | * | |
2461 | * This function walks the fence regs looking for a free one for @obj, | |
2462 | * stealing one if it can't find any. | |
2463 | * | |
2464 | * It then sets up the reg based on the object's properties: address, pitch | |
2465 | * and tiling format. | |
2466 | */ | |
8c4b8c3f | 2467 | int |
d9e86c0e | 2468 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj, |
ce453d81 | 2469 | struct intel_ring_buffer *pipelined) |
de151cf6 | 2470 | { |
05394f39 | 2471 | struct drm_device *dev = obj->base.dev; |
79e53945 | 2472 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9e86c0e | 2473 | struct drm_i915_fence_reg *reg; |
ae3db24a | 2474 | int ret; |
de151cf6 | 2475 | |
6bda10d1 CW |
2476 | /* XXX disable pipelining. There are bugs. Shocking. */ |
2477 | pipelined = NULL; | |
2478 | ||
d9e86c0e | 2479 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
2480 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2481 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
007cc8ac | 2482 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
d9e86c0e | 2483 | |
29c5a587 CW |
2484 | if (obj->tiling_changed) { |
2485 | ret = i915_gem_object_flush_fence(obj, pipelined); | |
2486 | if (ret) | |
2487 | return ret; | |
2488 | ||
2489 | if (!obj->fenced_gpu_access && !obj->last_fenced_seqno) | |
2490 | pipelined = NULL; | |
2491 | ||
2492 | if (pipelined) { | |
2493 | reg->setup_seqno = | |
2494 | i915_gem_next_request_seqno(pipelined); | |
2495 | obj->last_fenced_seqno = reg->setup_seqno; | |
2496 | obj->last_fenced_ring = pipelined; | |
2497 | } | |
2498 | ||
2499 | goto update; | |
2500 | } | |
d9e86c0e CW |
2501 | |
2502 | if (!pipelined) { | |
2503 | if (reg->setup_seqno) { | |
2504 | if (!ring_passed_seqno(obj->last_fenced_ring, | |
2505 | reg->setup_seqno)) { | |
db53a302 | 2506 | ret = i915_wait_request(obj->last_fenced_ring, |
b93f9cf1 BW |
2507 | reg->setup_seqno, |
2508 | true); | |
d9e86c0e CW |
2509 | if (ret) |
2510 | return ret; | |
2511 | } | |
2512 | ||
2513 | reg->setup_seqno = 0; | |
2514 | } | |
2515 | } else if (obj->last_fenced_ring && | |
2516 | obj->last_fenced_ring != pipelined) { | |
ce453d81 | 2517 | ret = i915_gem_object_flush_fence(obj, pipelined); |
d9e86c0e CW |
2518 | if (ret) |
2519 | return ret; | |
d9e86c0e CW |
2520 | } |
2521 | ||
a09ba7fa EA |
2522 | return 0; |
2523 | } | |
2524 | ||
d9e86c0e CW |
2525 | reg = i915_find_fence_reg(dev, pipelined); |
2526 | if (reg == NULL) | |
39965b37 | 2527 | return -EDEADLK; |
de151cf6 | 2528 | |
ce453d81 | 2529 | ret = i915_gem_object_flush_fence(obj, pipelined); |
d9e86c0e | 2530 | if (ret) |
ae3db24a | 2531 | return ret; |
de151cf6 | 2532 | |
d9e86c0e CW |
2533 | if (reg->obj) { |
2534 | struct drm_i915_gem_object *old = reg->obj; | |
2535 | ||
2536 | drm_gem_object_reference(&old->base); | |
2537 | ||
2538 | if (old->tiling_mode) | |
2539 | i915_gem_release_mmap(old); | |
2540 | ||
ce453d81 | 2541 | ret = i915_gem_object_flush_fence(old, pipelined); |
d9e86c0e CW |
2542 | if (ret) { |
2543 | drm_gem_object_unreference(&old->base); | |
2544 | return ret; | |
2545 | } | |
2546 | ||
2547 | if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0) | |
2548 | pipelined = NULL; | |
2549 | ||
2550 | old->fence_reg = I915_FENCE_REG_NONE; | |
2551 | old->last_fenced_ring = pipelined; | |
2552 | old->last_fenced_seqno = | |
db53a302 | 2553 | pipelined ? i915_gem_next_request_seqno(pipelined) : 0; |
d9e86c0e CW |
2554 | |
2555 | drm_gem_object_unreference(&old->base); | |
2556 | } else if (obj->last_fenced_seqno == 0) | |
2557 | pipelined = NULL; | |
a09ba7fa | 2558 | |
de151cf6 | 2559 | reg->obj = obj; |
d9e86c0e CW |
2560 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
2561 | obj->fence_reg = reg - dev_priv->fence_regs; | |
2562 | obj->last_fenced_ring = pipelined; | |
de151cf6 | 2563 | |
d9e86c0e | 2564 | reg->setup_seqno = |
db53a302 | 2565 | pipelined ? i915_gem_next_request_seqno(pipelined) : 0; |
d9e86c0e CW |
2566 | obj->last_fenced_seqno = reg->setup_seqno; |
2567 | ||
2568 | update: | |
2569 | obj->tiling_changed = false; | |
e259befd | 2570 | switch (INTEL_INFO(dev)->gen) { |
25aebfc3 | 2571 | case 7: |
e259befd | 2572 | case 6: |
c6642782 | 2573 | ret = sandybridge_write_fence_reg(obj, pipelined); |
e259befd CW |
2574 | break; |
2575 | case 5: | |
2576 | case 4: | |
c6642782 | 2577 | ret = i965_write_fence_reg(obj, pipelined); |
e259befd CW |
2578 | break; |
2579 | case 3: | |
c6642782 | 2580 | ret = i915_write_fence_reg(obj, pipelined); |
e259befd CW |
2581 | break; |
2582 | case 2: | |
c6642782 | 2583 | ret = i830_write_fence_reg(obj, pipelined); |
e259befd CW |
2584 | break; |
2585 | } | |
d9ddcb96 | 2586 | |
c6642782 | 2587 | return ret; |
de151cf6 JB |
2588 | } |
2589 | ||
2590 | /** | |
2591 | * i915_gem_clear_fence_reg - clear out fence register info | |
2592 | * @obj: object to clear | |
2593 | * | |
2594 | * Zeroes out the fence register itself and clears out the associated | |
05394f39 | 2595 | * data structures in dev_priv and obj. |
de151cf6 JB |
2596 | */ |
2597 | static void | |
d9e86c0e CW |
2598 | i915_gem_clear_fence_reg(struct drm_device *dev, |
2599 | struct drm_i915_fence_reg *reg) | |
de151cf6 | 2600 | { |
79e53945 | 2601 | drm_i915_private_t *dev_priv = dev->dev_private; |
d9e86c0e | 2602 | uint32_t fence_reg = reg - dev_priv->fence_regs; |
de151cf6 | 2603 | |
e259befd | 2604 | switch (INTEL_INFO(dev)->gen) { |
25aebfc3 | 2605 | case 7: |
e259befd | 2606 | case 6: |
d9e86c0e | 2607 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0); |
e259befd CW |
2608 | break; |
2609 | case 5: | |
2610 | case 4: | |
d9e86c0e | 2611 | I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0); |
e259befd CW |
2612 | break; |
2613 | case 3: | |
d9e86c0e CW |
2614 | if (fence_reg >= 8) |
2615 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; | |
dc529a4f | 2616 | else |
e259befd | 2617 | case 2: |
d9e86c0e | 2618 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; |
dc529a4f EA |
2619 | |
2620 | I915_WRITE(fence_reg, 0); | |
e259befd | 2621 | break; |
dc529a4f | 2622 | } |
de151cf6 | 2623 | |
007cc8ac | 2624 | list_del_init(®->lru_list); |
d9e86c0e CW |
2625 | reg->obj = NULL; |
2626 | reg->setup_seqno = 0; | |
1690e1eb | 2627 | reg->pin_count = 0; |
52dc7d32 CW |
2628 | } |
2629 | ||
673a394b EA |
2630 | /** |
2631 | * Finds free space in the GTT aperture and binds the object there. | |
2632 | */ | |
2633 | static int | |
05394f39 | 2634 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
920afa77 | 2635 | unsigned alignment, |
75e9e915 | 2636 | bool map_and_fenceable) |
673a394b | 2637 | { |
05394f39 | 2638 | struct drm_device *dev = obj->base.dev; |
673a394b | 2639 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 2640 | struct drm_mm_node *free_space; |
a00b10c3 | 2641 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
5e783301 | 2642 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
75e9e915 | 2643 | bool mappable, fenceable; |
07f73f69 | 2644 | int ret; |
673a394b | 2645 | |
05394f39 | 2646 | if (obj->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2647 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2648 | return -EINVAL; | |
2649 | } | |
2650 | ||
e28f8711 CW |
2651 | fence_size = i915_gem_get_gtt_size(dev, |
2652 | obj->base.size, | |
2653 | obj->tiling_mode); | |
2654 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
2655 | obj->base.size, | |
2656 | obj->tiling_mode); | |
2657 | unfenced_alignment = | |
2658 | i915_gem_get_unfenced_gtt_alignment(dev, | |
2659 | obj->base.size, | |
2660 | obj->tiling_mode); | |
a00b10c3 | 2661 | |
673a394b | 2662 | if (alignment == 0) |
5e783301 DV |
2663 | alignment = map_and_fenceable ? fence_alignment : |
2664 | unfenced_alignment; | |
75e9e915 | 2665 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
2666 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2667 | return -EINVAL; | |
2668 | } | |
2669 | ||
05394f39 | 2670 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 2671 | |
654fc607 CW |
2672 | /* If the object is bigger than the entire aperture, reject it early |
2673 | * before evicting everything in a vain attempt to find space. | |
2674 | */ | |
05394f39 | 2675 | if (obj->base.size > |
75e9e915 | 2676 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
654fc607 CW |
2677 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2678 | return -E2BIG; | |
2679 | } | |
2680 | ||
673a394b | 2681 | search_free: |
75e9e915 | 2682 | if (map_and_fenceable) |
920afa77 DV |
2683 | free_space = |
2684 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2685 | size, alignment, 0, |
920afa77 DV |
2686 | dev_priv->mm.gtt_mappable_end, |
2687 | 0); | |
2688 | else | |
2689 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2690 | size, alignment, 0); |
920afa77 DV |
2691 | |
2692 | if (free_space != NULL) { | |
75e9e915 | 2693 | if (map_and_fenceable) |
05394f39 | 2694 | obj->gtt_space = |
920afa77 | 2695 | drm_mm_get_block_range_generic(free_space, |
a00b10c3 | 2696 | size, alignment, 0, |
920afa77 DV |
2697 | dev_priv->mm.gtt_mappable_end, |
2698 | 0); | |
2699 | else | |
05394f39 | 2700 | obj->gtt_space = |
a00b10c3 | 2701 | drm_mm_get_block(free_space, size, alignment); |
920afa77 | 2702 | } |
05394f39 | 2703 | if (obj->gtt_space == NULL) { |
673a394b EA |
2704 | /* If the gtt is empty and we're still having trouble |
2705 | * fitting our object in, we're out of memory. | |
2706 | */ | |
75e9e915 DV |
2707 | ret = i915_gem_evict_something(dev, size, alignment, |
2708 | map_and_fenceable); | |
9731129c | 2709 | if (ret) |
673a394b | 2710 | return ret; |
9731129c | 2711 | |
673a394b EA |
2712 | goto search_free; |
2713 | } | |
2714 | ||
e5281ccd | 2715 | ret = i915_gem_object_get_pages_gtt(obj, gfpmask); |
673a394b | 2716 | if (ret) { |
05394f39 CW |
2717 | drm_mm_put_block(obj->gtt_space); |
2718 | obj->gtt_space = NULL; | |
07f73f69 CW |
2719 | |
2720 | if (ret == -ENOMEM) { | |
809b6334 CW |
2721 | /* first try to reclaim some memory by clearing the GTT */ |
2722 | ret = i915_gem_evict_everything(dev, false); | |
07f73f69 | 2723 | if (ret) { |
07f73f69 | 2724 | /* now try to shrink everyone else */ |
4bdadb97 CW |
2725 | if (gfpmask) { |
2726 | gfpmask = 0; | |
2727 | goto search_free; | |
07f73f69 CW |
2728 | } |
2729 | ||
809b6334 | 2730 | return -ENOMEM; |
07f73f69 CW |
2731 | } |
2732 | ||
2733 | goto search_free; | |
2734 | } | |
2735 | ||
673a394b EA |
2736 | return ret; |
2737 | } | |
2738 | ||
74163907 | 2739 | ret = i915_gem_gtt_prepare_object(obj); |
7c2e6fdf | 2740 | if (ret) { |
e5281ccd | 2741 | i915_gem_object_put_pages_gtt(obj); |
05394f39 CW |
2742 | drm_mm_put_block(obj->gtt_space); |
2743 | obj->gtt_space = NULL; | |
07f73f69 | 2744 | |
809b6334 | 2745 | if (i915_gem_evict_everything(dev, false)) |
07f73f69 | 2746 | return ret; |
07f73f69 CW |
2747 | |
2748 | goto search_free; | |
673a394b | 2749 | } |
0ebb9829 DV |
2750 | |
2751 | if (!dev_priv->mm.aliasing_ppgtt) | |
2752 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
673a394b | 2753 | |
6299f992 | 2754 | list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list); |
05394f39 | 2755 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
bf1a1092 | 2756 | |
673a394b EA |
2757 | /* Assert that the object is not currently in any GPU domain. As it |
2758 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2759 | * a GPU cache | |
2760 | */ | |
05394f39 CW |
2761 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
2762 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2763 | |
6299f992 | 2764 | obj->gtt_offset = obj->gtt_space->start; |
1c5d22f7 | 2765 | |
75e9e915 | 2766 | fenceable = |
05394f39 | 2767 | obj->gtt_space->size == fence_size && |
0206e353 | 2768 | (obj->gtt_space->start & (fence_alignment - 1)) == 0; |
a00b10c3 | 2769 | |
75e9e915 | 2770 | mappable = |
05394f39 | 2771 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
a00b10c3 | 2772 | |
05394f39 | 2773 | obj->map_and_fenceable = mappable && fenceable; |
75e9e915 | 2774 | |
db53a302 | 2775 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
673a394b EA |
2776 | return 0; |
2777 | } | |
2778 | ||
2779 | void | |
05394f39 | 2780 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
673a394b | 2781 | { |
673a394b EA |
2782 | /* If we don't have a page list set up, then we're not pinned |
2783 | * to GPU, and we can ignore the cache flush because it'll happen | |
2784 | * again at bind time. | |
2785 | */ | |
05394f39 | 2786 | if (obj->pages == NULL) |
673a394b EA |
2787 | return; |
2788 | ||
9c23f7fc CW |
2789 | /* If the GPU is snooping the contents of the CPU cache, |
2790 | * we do not need to manually clear the CPU cache lines. However, | |
2791 | * the caches are only snooped when the render cache is | |
2792 | * flushed/invalidated. As we always have to emit invalidations | |
2793 | * and flushes when moving into and out of the RENDER domain, correct | |
2794 | * snooping behaviour occurs naturally as the result of our domain | |
2795 | * tracking. | |
2796 | */ | |
2797 | if (obj->cache_level != I915_CACHE_NONE) | |
2798 | return; | |
2799 | ||
1c5d22f7 | 2800 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2801 | |
05394f39 | 2802 | drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE); |
673a394b EA |
2803 | } |
2804 | ||
e47c68e9 | 2805 | /** Flushes any GPU write domain for the object if it's dirty. */ |
88241785 | 2806 | static int |
3619df03 | 2807 | i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2808 | { |
05394f39 | 2809 | if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) |
88241785 | 2810 | return 0; |
e47c68e9 EA |
2811 | |
2812 | /* Queue the GPU write cache flushing we need. */ | |
db53a302 | 2813 | return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
e47c68e9 EA |
2814 | } |
2815 | ||
2816 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2817 | static void | |
05394f39 | 2818 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2819 | { |
1c5d22f7 CW |
2820 | uint32_t old_write_domain; |
2821 | ||
05394f39 | 2822 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
2823 | return; |
2824 | ||
63256ec5 | 2825 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
2826 | * to it immediately go to main memory as far as we know, so there's |
2827 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
2828 | * |
2829 | * However, we do have to enforce the order so that all writes through | |
2830 | * the GTT land before any writes to the device, such as updates to | |
2831 | * the GATT itself. | |
e47c68e9 | 2832 | */ |
63256ec5 CW |
2833 | wmb(); |
2834 | ||
05394f39 CW |
2835 | old_write_domain = obj->base.write_domain; |
2836 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2837 | |
2838 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2839 | obj->base.read_domains, |
1c5d22f7 | 2840 | old_write_domain); |
e47c68e9 EA |
2841 | } |
2842 | ||
2843 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2844 | static void | |
05394f39 | 2845 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2846 | { |
1c5d22f7 | 2847 | uint32_t old_write_domain; |
e47c68e9 | 2848 | |
05394f39 | 2849 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
2850 | return; |
2851 | ||
2852 | i915_gem_clflush_object(obj); | |
40ce6575 | 2853 | intel_gtt_chipset_flush(); |
05394f39 CW |
2854 | old_write_domain = obj->base.write_domain; |
2855 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2856 | |
2857 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2858 | obj->base.read_domains, |
1c5d22f7 | 2859 | old_write_domain); |
e47c68e9 EA |
2860 | } |
2861 | ||
2ef7eeaa EA |
2862 | /** |
2863 | * Moves a single object to the GTT read, and possibly write domain. | |
2864 | * | |
2865 | * This function returns when the move is complete, including waiting on | |
2866 | * flushes to occur. | |
2867 | */ | |
79e53945 | 2868 | int |
2021746e | 2869 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 2870 | { |
1c5d22f7 | 2871 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2872 | int ret; |
2ef7eeaa | 2873 | |
02354392 | 2874 | /* Not valid to be called on unbound objects. */ |
05394f39 | 2875 | if (obj->gtt_space == NULL) |
02354392 EA |
2876 | return -EINVAL; |
2877 | ||
8d7e3de1 CW |
2878 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
2879 | return 0; | |
2880 | ||
88241785 CW |
2881 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
2882 | if (ret) | |
2883 | return ret; | |
2884 | ||
87ca9c8a | 2885 | if (obj->pending_gpu_write || write) { |
ce453d81 | 2886 | ret = i915_gem_object_wait_rendering(obj); |
87ca9c8a CW |
2887 | if (ret) |
2888 | return ret; | |
2889 | } | |
2dafb1e0 | 2890 | |
7213342d | 2891 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 2892 | |
05394f39 CW |
2893 | old_write_domain = obj->base.write_domain; |
2894 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 2895 | |
e47c68e9 EA |
2896 | /* It should now be out of any other write domains, and we can update |
2897 | * the domain values for our changes. | |
2898 | */ | |
05394f39 CW |
2899 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
2900 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 2901 | if (write) { |
05394f39 CW |
2902 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
2903 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
2904 | obj->dirty = 1; | |
2ef7eeaa EA |
2905 | } |
2906 | ||
1c5d22f7 CW |
2907 | trace_i915_gem_object_change_domain(obj, |
2908 | old_read_domains, | |
2909 | old_write_domain); | |
2910 | ||
e47c68e9 EA |
2911 | return 0; |
2912 | } | |
2913 | ||
e4ffd173 CW |
2914 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
2915 | enum i915_cache_level cache_level) | |
2916 | { | |
7bddb01f DV |
2917 | struct drm_device *dev = obj->base.dev; |
2918 | drm_i915_private_t *dev_priv = dev->dev_private; | |
e4ffd173 CW |
2919 | int ret; |
2920 | ||
2921 | if (obj->cache_level == cache_level) | |
2922 | return 0; | |
2923 | ||
2924 | if (obj->pin_count) { | |
2925 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
2926 | return -EBUSY; | |
2927 | } | |
2928 | ||
2929 | if (obj->gtt_space) { | |
2930 | ret = i915_gem_object_finish_gpu(obj); | |
2931 | if (ret) | |
2932 | return ret; | |
2933 | ||
2934 | i915_gem_object_finish_gtt(obj); | |
2935 | ||
2936 | /* Before SandyBridge, you could not use tiling or fence | |
2937 | * registers with snooped memory, so relinquish any fences | |
2938 | * currently pointing to our region in the aperture. | |
2939 | */ | |
2940 | if (INTEL_INFO(obj->base.dev)->gen < 6) { | |
2941 | ret = i915_gem_object_put_fence(obj); | |
2942 | if (ret) | |
2943 | return ret; | |
2944 | } | |
2945 | ||
74898d7e DV |
2946 | if (obj->has_global_gtt_mapping) |
2947 | i915_gem_gtt_bind_object(obj, cache_level); | |
7bddb01f DV |
2948 | if (obj->has_aliasing_ppgtt_mapping) |
2949 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
2950 | obj, cache_level); | |
e4ffd173 CW |
2951 | } |
2952 | ||
2953 | if (cache_level == I915_CACHE_NONE) { | |
2954 | u32 old_read_domains, old_write_domain; | |
2955 | ||
2956 | /* If we're coming from LLC cached, then we haven't | |
2957 | * actually been tracking whether the data is in the | |
2958 | * CPU cache or not, since we only allow one bit set | |
2959 | * in obj->write_domain and have been skipping the clflushes. | |
2960 | * Just set it to the CPU cache for now. | |
2961 | */ | |
2962 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); | |
2963 | WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); | |
2964 | ||
2965 | old_read_domains = obj->base.read_domains; | |
2966 | old_write_domain = obj->base.write_domain; | |
2967 | ||
2968 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
2969 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
2970 | ||
2971 | trace_i915_gem_object_change_domain(obj, | |
2972 | old_read_domains, | |
2973 | old_write_domain); | |
2974 | } | |
2975 | ||
2976 | obj->cache_level = cache_level; | |
2977 | return 0; | |
2978 | } | |
2979 | ||
b9241ea3 | 2980 | /* |
2da3b9b9 CW |
2981 | * Prepare buffer for display plane (scanout, cursors, etc). |
2982 | * Can be called from an uninterruptible phase (modesetting) and allows | |
2983 | * any flushes to be pipelined (for pageflips). | |
2984 | * | |
2985 | * For the display plane, we want to be in the GTT but out of any write | |
2986 | * domains. So in many ways this looks like set_to_gtt_domain() apart from the | |
2987 | * ability to pipeline the waits, pinning and any additional subtleties | |
2988 | * that may differentiate the display plane from ordinary buffers. | |
b9241ea3 ZW |
2989 | */ |
2990 | int | |
2da3b9b9 CW |
2991 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
2992 | u32 alignment, | |
919926ae | 2993 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 2994 | { |
2da3b9b9 | 2995 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
2996 | int ret; |
2997 | ||
88241785 CW |
2998 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
2999 | if (ret) | |
3000 | return ret; | |
3001 | ||
0be73284 | 3002 | if (pipelined != obj->ring) { |
ce453d81 | 3003 | ret = i915_gem_object_wait_rendering(obj); |
f0b69efc | 3004 | if (ret == -ERESTARTSYS) |
b9241ea3 ZW |
3005 | return ret; |
3006 | } | |
3007 | ||
a7ef0640 EA |
3008 | /* The display engine is not coherent with the LLC cache on gen6. As |
3009 | * a result, we make sure that the pinning that is about to occur is | |
3010 | * done with uncached PTEs. This is lowest common denominator for all | |
3011 | * chipsets. | |
3012 | * | |
3013 | * However for gen6+, we could do better by using the GFDT bit instead | |
3014 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3015 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3016 | */ | |
3017 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); | |
3018 | if (ret) | |
3019 | return ret; | |
3020 | ||
2da3b9b9 CW |
3021 | /* As the user may map the buffer once pinned in the display plane |
3022 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3023 | * always use map_and_fenceable for all scanout buffers. | |
3024 | */ | |
3025 | ret = i915_gem_object_pin(obj, alignment, true); | |
3026 | if (ret) | |
3027 | return ret; | |
3028 | ||
b118c1e3 CW |
3029 | i915_gem_object_flush_cpu_write_domain(obj); |
3030 | ||
2da3b9b9 | 3031 | old_write_domain = obj->base.write_domain; |
05394f39 | 3032 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3033 | |
3034 | /* It should now be out of any other write domains, and we can update | |
3035 | * the domain values for our changes. | |
3036 | */ | |
3037 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); | |
05394f39 | 3038 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3039 | |
3040 | trace_i915_gem_object_change_domain(obj, | |
3041 | old_read_domains, | |
2da3b9b9 | 3042 | old_write_domain); |
b9241ea3 ZW |
3043 | |
3044 | return 0; | |
3045 | } | |
3046 | ||
85345517 | 3047 | int |
a8198eea | 3048 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3049 | { |
88241785 CW |
3050 | int ret; |
3051 | ||
a8198eea | 3052 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
3053 | return 0; |
3054 | ||
88241785 | 3055 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 3056 | ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
88241785 CW |
3057 | if (ret) |
3058 | return ret; | |
3059 | } | |
85345517 | 3060 | |
c501ae7f CW |
3061 | ret = i915_gem_object_wait_rendering(obj); |
3062 | if (ret) | |
3063 | return ret; | |
3064 | ||
a8198eea CW |
3065 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3066 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 3067 | return 0; |
85345517 CW |
3068 | } |
3069 | ||
e47c68e9 EA |
3070 | /** |
3071 | * Moves a single object to the CPU read, and possibly write domain. | |
3072 | * | |
3073 | * This function returns when the move is complete, including waiting on | |
3074 | * flushes to occur. | |
3075 | */ | |
3076 | static int | |
919926ae | 3077 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3078 | { |
1c5d22f7 | 3079 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3080 | int ret; |
3081 | ||
8d7e3de1 CW |
3082 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3083 | return 0; | |
3084 | ||
88241785 CW |
3085 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
3086 | if (ret) | |
3087 | return ret; | |
3088 | ||
ce453d81 | 3089 | ret = i915_gem_object_wait_rendering(obj); |
de18a29e | 3090 | if (ret) |
e47c68e9 | 3091 | return ret; |
2ef7eeaa | 3092 | |
e47c68e9 | 3093 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3094 | |
e47c68e9 EA |
3095 | /* If we have a partially-valid cache of the object in the CPU, |
3096 | * finish invalidating it and free the per-page flags. | |
2ef7eeaa | 3097 | */ |
e47c68e9 | 3098 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
2ef7eeaa | 3099 | |
05394f39 CW |
3100 | old_write_domain = obj->base.write_domain; |
3101 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3102 | |
e47c68e9 | 3103 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3104 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2ef7eeaa | 3105 | i915_gem_clflush_object(obj); |
2ef7eeaa | 3106 | |
05394f39 | 3107 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3108 | } |
3109 | ||
3110 | /* It should now be out of any other write domains, and we can update | |
3111 | * the domain values for our changes. | |
3112 | */ | |
05394f39 | 3113 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3114 | |
3115 | /* If we're writing through the CPU, then the GPU read domains will | |
3116 | * need to be invalidated at next use. | |
3117 | */ | |
3118 | if (write) { | |
05394f39 CW |
3119 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3120 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3121 | } |
2ef7eeaa | 3122 | |
1c5d22f7 CW |
3123 | trace_i915_gem_object_change_domain(obj, |
3124 | old_read_domains, | |
3125 | old_write_domain); | |
3126 | ||
2ef7eeaa EA |
3127 | return 0; |
3128 | } | |
3129 | ||
673a394b | 3130 | /** |
e47c68e9 | 3131 | * Moves the object from a partially CPU read to a full one. |
673a394b | 3132 | * |
e47c68e9 EA |
3133 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
3134 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). | |
673a394b | 3135 | */ |
e47c68e9 | 3136 | static void |
05394f39 | 3137 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj) |
673a394b | 3138 | { |
05394f39 | 3139 | if (!obj->page_cpu_valid) |
e47c68e9 EA |
3140 | return; |
3141 | ||
3142 | /* If we're partially in the CPU read domain, finish moving it in. | |
3143 | */ | |
05394f39 | 3144 | if (obj->base.read_domains & I915_GEM_DOMAIN_CPU) { |
e47c68e9 EA |
3145 | int i; |
3146 | ||
05394f39 CW |
3147 | for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) { |
3148 | if (obj->page_cpu_valid[i]) | |
e47c68e9 | 3149 | continue; |
05394f39 | 3150 | drm_clflush_pages(obj->pages + i, 1); |
e47c68e9 | 3151 | } |
e47c68e9 EA |
3152 | } |
3153 | ||
3154 | /* Free the page_cpu_valid mappings which are now stale, whether | |
3155 | * or not we've got I915_GEM_DOMAIN_CPU. | |
3156 | */ | |
05394f39 CW |
3157 | kfree(obj->page_cpu_valid); |
3158 | obj->page_cpu_valid = NULL; | |
e47c68e9 EA |
3159 | } |
3160 | ||
3161 | /** | |
3162 | * Set the CPU read domain on a range of the object. | |
3163 | * | |
3164 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's | |
3165 | * not entirely valid. The page_cpu_valid member of the object flags which | |
3166 | * pages have been flushed, and will be respected by | |
3167 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping | |
3168 | * of the whole object. | |
3169 | * | |
3170 | * This function returns when the move is complete, including waiting on | |
3171 | * flushes to occur. | |
3172 | */ | |
3173 | static int | |
05394f39 | 3174 | i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj, |
e47c68e9 EA |
3175 | uint64_t offset, uint64_t size) |
3176 | { | |
1c5d22f7 | 3177 | uint32_t old_read_domains; |
e47c68e9 | 3178 | int i, ret; |
673a394b | 3179 | |
05394f39 | 3180 | if (offset == 0 && size == obj->base.size) |
e47c68e9 | 3181 | return i915_gem_object_set_to_cpu_domain(obj, 0); |
673a394b | 3182 | |
88241785 CW |
3183 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
3184 | if (ret) | |
3185 | return ret; | |
3186 | ||
ce453d81 | 3187 | ret = i915_gem_object_wait_rendering(obj); |
de18a29e | 3188 | if (ret) |
6a47baa6 | 3189 | return ret; |
de18a29e | 3190 | |
e47c68e9 EA |
3191 | i915_gem_object_flush_gtt_write_domain(obj); |
3192 | ||
3193 | /* If we're already fully in the CPU read domain, we're done. */ | |
05394f39 CW |
3194 | if (obj->page_cpu_valid == NULL && |
3195 | (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0) | |
e47c68e9 | 3196 | return 0; |
673a394b | 3197 | |
e47c68e9 EA |
3198 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
3199 | * newly adding I915_GEM_DOMAIN_CPU | |
3200 | */ | |
05394f39 CW |
3201 | if (obj->page_cpu_valid == NULL) { |
3202 | obj->page_cpu_valid = kzalloc(obj->base.size / PAGE_SIZE, | |
3203 | GFP_KERNEL); | |
3204 | if (obj->page_cpu_valid == NULL) | |
e47c68e9 | 3205 | return -ENOMEM; |
05394f39 CW |
3206 | } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) |
3207 | memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE); | |
673a394b EA |
3208 | |
3209 | /* Flush the cache on any pages that are still invalid from the CPU's | |
3210 | * perspective. | |
3211 | */ | |
e47c68e9 EA |
3212 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
3213 | i++) { | |
05394f39 | 3214 | if (obj->page_cpu_valid[i]) |
673a394b EA |
3215 | continue; |
3216 | ||
05394f39 | 3217 | drm_clflush_pages(obj->pages + i, 1); |
673a394b | 3218 | |
05394f39 | 3219 | obj->page_cpu_valid[i] = 1; |
673a394b EA |
3220 | } |
3221 | ||
e47c68e9 EA |
3222 | /* It should now be out of any other write domains, and we can update |
3223 | * the domain values for our changes. | |
3224 | */ | |
05394f39 | 3225 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 | 3226 | |
05394f39 CW |
3227 | old_read_domains = obj->base.read_domains; |
3228 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3229 | |
1c5d22f7 CW |
3230 | trace_i915_gem_object_change_domain(obj, |
3231 | old_read_domains, | |
05394f39 | 3232 | obj->base.write_domain); |
1c5d22f7 | 3233 | |
673a394b EA |
3234 | return 0; |
3235 | } | |
3236 | ||
673a394b EA |
3237 | /* Throttle our rendering by waiting until the ring has completed our requests |
3238 | * emitted over 20 msec ago. | |
3239 | * | |
b962442e EA |
3240 | * Note that if we were to use the current jiffies each time around the loop, |
3241 | * we wouldn't escape the function with any frames outstanding if the time to | |
3242 | * render a frame was over 20ms. | |
3243 | * | |
673a394b EA |
3244 | * This should get us reasonable parallelism between CPU and GPU but also |
3245 | * relatively low latency when blocking on a particular request to finish. | |
3246 | */ | |
40a5f0de | 3247 | static int |
f787a5f5 | 3248 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3249 | { |
f787a5f5 CW |
3250 | struct drm_i915_private *dev_priv = dev->dev_private; |
3251 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3252 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3253 | struct drm_i915_gem_request *request; |
3254 | struct intel_ring_buffer *ring = NULL; | |
3255 | u32 seqno = 0; | |
3256 | int ret; | |
93533c29 | 3257 | |
e110e8d6 CW |
3258 | if (atomic_read(&dev_priv->mm.wedged)) |
3259 | return -EIO; | |
3260 | ||
1c25595f | 3261 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3262 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3263 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3264 | break; | |
40a5f0de | 3265 | |
f787a5f5 CW |
3266 | ring = request->ring; |
3267 | seqno = request->seqno; | |
b962442e | 3268 | } |
1c25595f | 3269 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3270 | |
f787a5f5 CW |
3271 | if (seqno == 0) |
3272 | return 0; | |
2bc43b5c | 3273 | |
f787a5f5 | 3274 | ret = 0; |
78501eac | 3275 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
f787a5f5 CW |
3276 | /* And wait for the seqno passing without holding any locks and |
3277 | * causing extra latency for others. This is safe as the irq | |
3278 | * generation is designed to be run atomically and so is | |
3279 | * lockless. | |
3280 | */ | |
b13c2b96 CW |
3281 | if (ring->irq_get(ring)) { |
3282 | ret = wait_event_interruptible(ring->irq_queue, | |
3283 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
3284 | || atomic_read(&dev_priv->mm.wedged)); | |
3285 | ring->irq_put(ring); | |
40a5f0de | 3286 | |
b13c2b96 CW |
3287 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) |
3288 | ret = -EIO; | |
e959b5db EA |
3289 | } else if (wait_for_atomic(i915_seqno_passed(ring->get_seqno(ring), |
3290 | seqno) || | |
7ea29b13 EA |
3291 | atomic_read(&dev_priv->mm.wedged), 3000)) { |
3292 | ret = -EBUSY; | |
b13c2b96 | 3293 | } |
40a5f0de EA |
3294 | } |
3295 | ||
f787a5f5 CW |
3296 | if (ret == 0) |
3297 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3298 | |
3299 | return ret; | |
3300 | } | |
3301 | ||
673a394b | 3302 | int |
05394f39 CW |
3303 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
3304 | uint32_t alignment, | |
75e9e915 | 3305 | bool map_and_fenceable) |
673a394b | 3306 | { |
05394f39 | 3307 | struct drm_device *dev = obj->base.dev; |
f13d3f73 | 3308 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
3309 | int ret; |
3310 | ||
05394f39 | 3311 | BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
23bc5982 | 3312 | WARN_ON(i915_verify_lists(dev)); |
ac0c6b5a | 3313 | |
05394f39 CW |
3314 | if (obj->gtt_space != NULL) { |
3315 | if ((alignment && obj->gtt_offset & (alignment - 1)) || | |
3316 | (map_and_fenceable && !obj->map_and_fenceable)) { | |
3317 | WARN(obj->pin_count, | |
ae7d49d8 | 3318 | "bo is already pinned with incorrect alignment:" |
75e9e915 DV |
3319 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
3320 | " obj->map_and_fenceable=%d\n", | |
05394f39 | 3321 | obj->gtt_offset, alignment, |
75e9e915 | 3322 | map_and_fenceable, |
05394f39 | 3323 | obj->map_and_fenceable); |
ac0c6b5a CW |
3324 | ret = i915_gem_object_unbind(obj); |
3325 | if (ret) | |
3326 | return ret; | |
3327 | } | |
3328 | } | |
3329 | ||
05394f39 | 3330 | if (obj->gtt_space == NULL) { |
a00b10c3 | 3331 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
75e9e915 | 3332 | map_and_fenceable); |
9731129c | 3333 | if (ret) |
673a394b | 3334 | return ret; |
22c344e9 | 3335 | } |
76446cac | 3336 | |
74898d7e DV |
3337 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
3338 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
3339 | ||
05394f39 | 3340 | if (obj->pin_count++ == 0) { |
05394f39 CW |
3341 | if (!obj->active) |
3342 | list_move_tail(&obj->mm_list, | |
f13d3f73 | 3343 | &dev_priv->mm.pinned_list); |
673a394b | 3344 | } |
6299f992 | 3345 | obj->pin_mappable |= map_and_fenceable; |
673a394b | 3346 | |
23bc5982 | 3347 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
3348 | return 0; |
3349 | } | |
3350 | ||
3351 | void | |
05394f39 | 3352 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3353 | { |
05394f39 | 3354 | struct drm_device *dev = obj->base.dev; |
673a394b | 3355 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 3356 | |
23bc5982 | 3357 | WARN_ON(i915_verify_lists(dev)); |
05394f39 CW |
3358 | BUG_ON(obj->pin_count == 0); |
3359 | BUG_ON(obj->gtt_space == NULL); | |
673a394b | 3360 | |
05394f39 CW |
3361 | if (--obj->pin_count == 0) { |
3362 | if (!obj->active) | |
3363 | list_move_tail(&obj->mm_list, | |
673a394b | 3364 | &dev_priv->mm.inactive_list); |
6299f992 | 3365 | obj->pin_mappable = false; |
673a394b | 3366 | } |
23bc5982 | 3367 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
3368 | } |
3369 | ||
3370 | int | |
3371 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3372 | struct drm_file *file) |
673a394b EA |
3373 | { |
3374 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3375 | struct drm_i915_gem_object *obj; |
673a394b EA |
3376 | int ret; |
3377 | ||
1d7cfea1 CW |
3378 | ret = i915_mutex_lock_interruptible(dev); |
3379 | if (ret) | |
3380 | return ret; | |
673a394b | 3381 | |
05394f39 | 3382 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3383 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3384 | ret = -ENOENT; |
3385 | goto unlock; | |
673a394b | 3386 | } |
673a394b | 3387 | |
05394f39 | 3388 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 3389 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
3390 | ret = -EINVAL; |
3391 | goto out; | |
3ef94daa CW |
3392 | } |
3393 | ||
05394f39 | 3394 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
3395 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3396 | args->handle); | |
1d7cfea1 CW |
3397 | ret = -EINVAL; |
3398 | goto out; | |
79e53945 JB |
3399 | } |
3400 | ||
05394f39 CW |
3401 | obj->user_pin_count++; |
3402 | obj->pin_filp = file; | |
3403 | if (obj->user_pin_count == 1) { | |
75e9e915 | 3404 | ret = i915_gem_object_pin(obj, args->alignment, true); |
1d7cfea1 CW |
3405 | if (ret) |
3406 | goto out; | |
673a394b EA |
3407 | } |
3408 | ||
3409 | /* XXX - flush the CPU caches for pinned objects | |
3410 | * as the X server doesn't manage domains yet | |
3411 | */ | |
e47c68e9 | 3412 | i915_gem_object_flush_cpu_write_domain(obj); |
05394f39 | 3413 | args->offset = obj->gtt_offset; |
1d7cfea1 | 3414 | out: |
05394f39 | 3415 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3416 | unlock: |
673a394b | 3417 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3418 | return ret; |
673a394b EA |
3419 | } |
3420 | ||
3421 | int | |
3422 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3423 | struct drm_file *file) |
673a394b EA |
3424 | { |
3425 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3426 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3427 | int ret; |
673a394b | 3428 | |
1d7cfea1 CW |
3429 | ret = i915_mutex_lock_interruptible(dev); |
3430 | if (ret) | |
3431 | return ret; | |
673a394b | 3432 | |
05394f39 | 3433 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3434 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3435 | ret = -ENOENT; |
3436 | goto unlock; | |
673a394b | 3437 | } |
76c1dec1 | 3438 | |
05394f39 | 3439 | if (obj->pin_filp != file) { |
79e53945 JB |
3440 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3441 | args->handle); | |
1d7cfea1 CW |
3442 | ret = -EINVAL; |
3443 | goto out; | |
79e53945 | 3444 | } |
05394f39 CW |
3445 | obj->user_pin_count--; |
3446 | if (obj->user_pin_count == 0) { | |
3447 | obj->pin_filp = NULL; | |
79e53945 JB |
3448 | i915_gem_object_unpin(obj); |
3449 | } | |
673a394b | 3450 | |
1d7cfea1 | 3451 | out: |
05394f39 | 3452 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3453 | unlock: |
673a394b | 3454 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3455 | return ret; |
673a394b EA |
3456 | } |
3457 | ||
3458 | int | |
3459 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3460 | struct drm_file *file) |
673a394b EA |
3461 | { |
3462 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3463 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3464 | int ret; |
3465 | ||
76c1dec1 | 3466 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3467 | if (ret) |
76c1dec1 | 3468 | return ret; |
673a394b | 3469 | |
05394f39 | 3470 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3471 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3472 | ret = -ENOENT; |
3473 | goto unlock; | |
673a394b | 3474 | } |
d1b851fc | 3475 | |
0be555b6 CW |
3476 | /* Count all active objects as busy, even if they are currently not used |
3477 | * by the gpu. Users of this interface expect objects to eventually | |
3478 | * become non-busy without any further actions, therefore emit any | |
3479 | * necessary flushes here. | |
c4de0a5d | 3480 | */ |
05394f39 | 3481 | args->busy = obj->active; |
0be555b6 CW |
3482 | if (args->busy) { |
3483 | /* Unconditionally flush objects, even when the gpu still uses this | |
3484 | * object. Userspace calling this function indicates that it wants to | |
3485 | * use this buffer rather sooner than later, so issuing the required | |
3486 | * flush earlier is beneficial. | |
3487 | */ | |
1a1c6976 | 3488 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 3489 | ret = i915_gem_flush_ring(obj->ring, |
88241785 | 3490 | 0, obj->base.write_domain); |
1a1c6976 CW |
3491 | } else if (obj->ring->outstanding_lazy_request == |
3492 | obj->last_rendering_seqno) { | |
3493 | struct drm_i915_gem_request *request; | |
3494 | ||
7a194876 CW |
3495 | /* This ring is not being cleared by active usage, |
3496 | * so emit a request to do so. | |
3497 | */ | |
1a1c6976 | 3498 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
457eafce | 3499 | if (request) { |
0206e353 | 3500 | ret = i915_add_request(obj->ring, NULL, request); |
457eafce RM |
3501 | if (ret) |
3502 | kfree(request); | |
3503 | } else | |
7a194876 CW |
3504 | ret = -ENOMEM; |
3505 | } | |
0be555b6 CW |
3506 | |
3507 | /* Update the active list for the hardware's current position. | |
3508 | * Otherwise this only updates on a delayed timer or when irqs | |
3509 | * are actually unmasked, and our working set ends up being | |
3510 | * larger than required. | |
3511 | */ | |
db53a302 | 3512 | i915_gem_retire_requests_ring(obj->ring); |
0be555b6 | 3513 | |
05394f39 | 3514 | args->busy = obj->active; |
0be555b6 | 3515 | } |
673a394b | 3516 | |
05394f39 | 3517 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3518 | unlock: |
673a394b | 3519 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3520 | return ret; |
673a394b EA |
3521 | } |
3522 | ||
3523 | int | |
3524 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3525 | struct drm_file *file_priv) | |
3526 | { | |
0206e353 | 3527 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3528 | } |
3529 | ||
3ef94daa CW |
3530 | int |
3531 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3532 | struct drm_file *file_priv) | |
3533 | { | |
3534 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 3535 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3536 | int ret; |
3ef94daa CW |
3537 | |
3538 | switch (args->madv) { | |
3539 | case I915_MADV_DONTNEED: | |
3540 | case I915_MADV_WILLNEED: | |
3541 | break; | |
3542 | default: | |
3543 | return -EINVAL; | |
3544 | } | |
3545 | ||
1d7cfea1 CW |
3546 | ret = i915_mutex_lock_interruptible(dev); |
3547 | if (ret) | |
3548 | return ret; | |
3549 | ||
05394f39 | 3550 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 3551 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3552 | ret = -ENOENT; |
3553 | goto unlock; | |
3ef94daa | 3554 | } |
3ef94daa | 3555 | |
05394f39 | 3556 | if (obj->pin_count) { |
1d7cfea1 CW |
3557 | ret = -EINVAL; |
3558 | goto out; | |
3ef94daa CW |
3559 | } |
3560 | ||
05394f39 CW |
3561 | if (obj->madv != __I915_MADV_PURGED) |
3562 | obj->madv = args->madv; | |
3ef94daa | 3563 | |
2d7ef395 | 3564 | /* if the object is no longer bound, discard its backing storage */ |
05394f39 CW |
3565 | if (i915_gem_object_is_purgeable(obj) && |
3566 | obj->gtt_space == NULL) | |
2d7ef395 CW |
3567 | i915_gem_object_truncate(obj); |
3568 | ||
05394f39 | 3569 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 3570 | |
1d7cfea1 | 3571 | out: |
05394f39 | 3572 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3573 | unlock: |
3ef94daa | 3574 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3575 | return ret; |
3ef94daa CW |
3576 | } |
3577 | ||
05394f39 CW |
3578 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
3579 | size_t size) | |
ac52bc56 | 3580 | { |
73aa808f | 3581 | struct drm_i915_private *dev_priv = dev->dev_private; |
c397b908 | 3582 | struct drm_i915_gem_object *obj; |
5949eac4 | 3583 | struct address_space *mapping; |
ac52bc56 | 3584 | |
c397b908 DV |
3585 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
3586 | if (obj == NULL) | |
3587 | return NULL; | |
673a394b | 3588 | |
c397b908 DV |
3589 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
3590 | kfree(obj); | |
3591 | return NULL; | |
3592 | } | |
673a394b | 3593 | |
5949eac4 HD |
3594 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
3595 | mapping_set_gfp_mask(mapping, GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
3596 | ||
73aa808f CW |
3597 | i915_gem_info_add_obj(dev_priv, size); |
3598 | ||
c397b908 DV |
3599 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3600 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 3601 | |
3d29b842 ED |
3602 | if (HAS_LLC(dev)) { |
3603 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
3604 | * cache) for about a 10% performance improvement |
3605 | * compared to uncached. Graphics requests other than | |
3606 | * display scanout are coherent with the CPU in | |
3607 | * accessing this cache. This means in this mode we | |
3608 | * don't need to clflush on the CPU side, and on the | |
3609 | * GPU side we only need to flush internal caches to | |
3610 | * get data visible to the CPU. | |
3611 | * | |
3612 | * However, we maintain the display planes as UC, and so | |
3613 | * need to rebind when first used as such. | |
3614 | */ | |
3615 | obj->cache_level = I915_CACHE_LLC; | |
3616 | } else | |
3617 | obj->cache_level = I915_CACHE_NONE; | |
3618 | ||
62b8b215 | 3619 | obj->base.driver_private = NULL; |
c397b908 | 3620 | obj->fence_reg = I915_FENCE_REG_NONE; |
69dc4987 | 3621 | INIT_LIST_HEAD(&obj->mm_list); |
93a37f20 | 3622 | INIT_LIST_HEAD(&obj->gtt_list); |
69dc4987 | 3623 | INIT_LIST_HEAD(&obj->ring_list); |
432e58ed | 3624 | INIT_LIST_HEAD(&obj->exec_list); |
c397b908 | 3625 | INIT_LIST_HEAD(&obj->gpu_write_list); |
c397b908 | 3626 | obj->madv = I915_MADV_WILLNEED; |
75e9e915 DV |
3627 | /* Avoid an unnecessary call to unbind on the first bind. */ |
3628 | obj->map_and_fenceable = true; | |
de151cf6 | 3629 | |
05394f39 | 3630 | return obj; |
c397b908 DV |
3631 | } |
3632 | ||
3633 | int i915_gem_init_object(struct drm_gem_object *obj) | |
3634 | { | |
3635 | BUG(); | |
de151cf6 | 3636 | |
673a394b EA |
3637 | return 0; |
3638 | } | |
3639 | ||
05394f39 | 3640 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj) |
673a394b | 3641 | { |
05394f39 | 3642 | struct drm_device *dev = obj->base.dev; |
be72615b | 3643 | drm_i915_private_t *dev_priv = dev->dev_private; |
be72615b | 3644 | int ret; |
673a394b | 3645 | |
be72615b CW |
3646 | ret = i915_gem_object_unbind(obj); |
3647 | if (ret == -ERESTARTSYS) { | |
05394f39 | 3648 | list_move(&obj->mm_list, |
be72615b CW |
3649 | &dev_priv->mm.deferred_free_list); |
3650 | return; | |
3651 | } | |
673a394b | 3652 | |
26e12f89 CW |
3653 | trace_i915_gem_object_destroy(obj); |
3654 | ||
05394f39 | 3655 | if (obj->base.map_list.map) |
b464e9a2 | 3656 | drm_gem_free_mmap_offset(&obj->base); |
de151cf6 | 3657 | |
05394f39 CW |
3658 | drm_gem_object_release(&obj->base); |
3659 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 3660 | |
05394f39 CW |
3661 | kfree(obj->page_cpu_valid); |
3662 | kfree(obj->bit_17); | |
3663 | kfree(obj); | |
673a394b EA |
3664 | } |
3665 | ||
05394f39 | 3666 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
be72615b | 3667 | { |
05394f39 CW |
3668 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
3669 | struct drm_device *dev = obj->base.dev; | |
be72615b | 3670 | |
05394f39 | 3671 | while (obj->pin_count > 0) |
be72615b CW |
3672 | i915_gem_object_unpin(obj); |
3673 | ||
05394f39 | 3674 | if (obj->phys_obj) |
be72615b CW |
3675 | i915_gem_detach_phys_object(dev, obj); |
3676 | ||
3677 | i915_gem_free_object_tail(obj); | |
3678 | } | |
3679 | ||
29105ccc CW |
3680 | int |
3681 | i915_gem_idle(struct drm_device *dev) | |
3682 | { | |
3683 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3684 | int ret; | |
28dfe52a | 3685 | |
29105ccc | 3686 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 3687 | |
87acb0a5 | 3688 | if (dev_priv->mm.suspended) { |
29105ccc CW |
3689 | mutex_unlock(&dev->struct_mutex); |
3690 | return 0; | |
28dfe52a EA |
3691 | } |
3692 | ||
b93f9cf1 | 3693 | ret = i915_gpu_idle(dev, true); |
6dbe2772 KP |
3694 | if (ret) { |
3695 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 3696 | return ret; |
6dbe2772 | 3697 | } |
673a394b | 3698 | |
29105ccc CW |
3699 | /* Under UMS, be paranoid and evict. */ |
3700 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { | |
5eac3ab4 | 3701 | ret = i915_gem_evict_inactive(dev, false); |
29105ccc CW |
3702 | if (ret) { |
3703 | mutex_unlock(&dev->struct_mutex); | |
3704 | return ret; | |
3705 | } | |
3706 | } | |
3707 | ||
312817a3 CW |
3708 | i915_gem_reset_fences(dev); |
3709 | ||
29105ccc CW |
3710 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
3711 | * We need to replace this with a semaphore, or something. | |
3712 | * And not confound mm.suspended! | |
3713 | */ | |
3714 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 3715 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
3716 | |
3717 | i915_kernel_lost_context(dev); | |
6dbe2772 | 3718 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 3719 | |
6dbe2772 KP |
3720 | mutex_unlock(&dev->struct_mutex); |
3721 | ||
29105ccc CW |
3722 | /* Cancel the retire work handler, which should be idle now. */ |
3723 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
3724 | ||
673a394b EA |
3725 | return 0; |
3726 | } | |
3727 | ||
f691e2f4 DV |
3728 | void i915_gem_init_swizzling(struct drm_device *dev) |
3729 | { | |
3730 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3731 | ||
11782b02 | 3732 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
3733 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
3734 | return; | |
3735 | ||
3736 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
3737 | DISP_TILE_SURFACE_SWIZZLING); | |
3738 | ||
11782b02 DV |
3739 | if (IS_GEN5(dev)) |
3740 | return; | |
3741 | ||
f691e2f4 DV |
3742 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
3743 | if (IS_GEN6(dev)) | |
3744 | I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_SNB)); | |
3745 | else | |
3746 | I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_IVB)); | |
3747 | } | |
e21af88d DV |
3748 | |
3749 | void i915_gem_init_ppgtt(struct drm_device *dev) | |
3750 | { | |
3751 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3752 | uint32_t pd_offset; | |
3753 | struct intel_ring_buffer *ring; | |
3754 | int i; | |
3755 | ||
3756 | if (!dev_priv->mm.aliasing_ppgtt) | |
3757 | return; | |
3758 | ||
3759 | pd_offset = dev_priv->mm.aliasing_ppgtt->pd_offset; | |
3760 | pd_offset /= 64; /* in cachelines, */ | |
3761 | pd_offset <<= 16; | |
3762 | ||
3763 | if (INTEL_INFO(dev)->gen == 6) { | |
3764 | uint32_t ecochk = I915_READ(GAM_ECOCHK); | |
3765 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | | |
3766 | ECOCHK_PPGTT_CACHE64B); | |
3767 | I915_WRITE(GFX_MODE, GFX_MODE_ENABLE(GFX_PPGTT_ENABLE)); | |
3768 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
3769 | I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B); | |
3770 | /* GFX_MODE is per-ring on gen7+ */ | |
3771 | } | |
3772 | ||
3773 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
3774 | ring = &dev_priv->ring[i]; | |
3775 | ||
3776 | if (INTEL_INFO(dev)->gen >= 7) | |
3777 | I915_WRITE(RING_MODE_GEN7(ring), | |
3778 | GFX_MODE_ENABLE(GFX_PPGTT_ENABLE)); | |
3779 | ||
3780 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
3781 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); | |
3782 | } | |
3783 | } | |
3784 | ||
8187a2b7 | 3785 | int |
f691e2f4 | 3786 | i915_gem_init_hw(struct drm_device *dev) |
8187a2b7 ZN |
3787 | { |
3788 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3789 | int ret; | |
68f95ba9 | 3790 | |
f691e2f4 DV |
3791 | i915_gem_init_swizzling(dev); |
3792 | ||
5c1143bb | 3793 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 3794 | if (ret) |
b6913e4b | 3795 | return ret; |
68f95ba9 CW |
3796 | |
3797 | if (HAS_BSD(dev)) { | |
5c1143bb | 3798 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
3799 | if (ret) |
3800 | goto cleanup_render_ring; | |
d1b851fc | 3801 | } |
68f95ba9 | 3802 | |
549f7365 CW |
3803 | if (HAS_BLT(dev)) { |
3804 | ret = intel_init_blt_ring_buffer(dev); | |
3805 | if (ret) | |
3806 | goto cleanup_bsd_ring; | |
3807 | } | |
3808 | ||
6f392d54 CW |
3809 | dev_priv->next_seqno = 1; |
3810 | ||
e21af88d DV |
3811 | i915_gem_init_ppgtt(dev); |
3812 | ||
68f95ba9 CW |
3813 | return 0; |
3814 | ||
549f7365 | 3815 | cleanup_bsd_ring: |
1ec14ad3 | 3816 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
68f95ba9 | 3817 | cleanup_render_ring: |
1ec14ad3 | 3818 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
8187a2b7 ZN |
3819 | return ret; |
3820 | } | |
3821 | ||
3822 | void | |
3823 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
3824 | { | |
3825 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 3826 | int i; |
8187a2b7 | 3827 | |
1ec14ad3 CW |
3828 | for (i = 0; i < I915_NUM_RINGS; i++) |
3829 | intel_cleanup_ring_buffer(&dev_priv->ring[i]); | |
8187a2b7 ZN |
3830 | } |
3831 | ||
673a394b EA |
3832 | int |
3833 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
3834 | struct drm_file *file_priv) | |
3835 | { | |
3836 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 3837 | int ret, i; |
673a394b | 3838 | |
79e53945 JB |
3839 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3840 | return 0; | |
3841 | ||
ba1234d1 | 3842 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 3843 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 3844 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
3845 | } |
3846 | ||
673a394b | 3847 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
3848 | dev_priv->mm.suspended = 0; |
3849 | ||
f691e2f4 | 3850 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
3851 | if (ret != 0) { |
3852 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 3853 | return ret; |
d816f6ac | 3854 | } |
9bb2d6f9 | 3855 | |
69dc4987 | 3856 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
673a394b EA |
3857 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
3858 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
1ec14ad3 CW |
3859 | for (i = 0; i < I915_NUM_RINGS; i++) { |
3860 | BUG_ON(!list_empty(&dev_priv->ring[i].active_list)); | |
3861 | BUG_ON(!list_empty(&dev_priv->ring[i].request_list)); | |
3862 | } | |
673a394b | 3863 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 3864 | |
5f35308b CW |
3865 | ret = drm_irq_install(dev); |
3866 | if (ret) | |
3867 | goto cleanup_ringbuffer; | |
dbb19d30 | 3868 | |
673a394b | 3869 | return 0; |
5f35308b CW |
3870 | |
3871 | cleanup_ringbuffer: | |
3872 | mutex_lock(&dev->struct_mutex); | |
3873 | i915_gem_cleanup_ringbuffer(dev); | |
3874 | dev_priv->mm.suspended = 1; | |
3875 | mutex_unlock(&dev->struct_mutex); | |
3876 | ||
3877 | return ret; | |
673a394b EA |
3878 | } |
3879 | ||
3880 | int | |
3881 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
3882 | struct drm_file *file_priv) | |
3883 | { | |
79e53945 JB |
3884 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3885 | return 0; | |
3886 | ||
dbb19d30 | 3887 | drm_irq_uninstall(dev); |
e6890f6f | 3888 | return i915_gem_idle(dev); |
673a394b EA |
3889 | } |
3890 | ||
3891 | void | |
3892 | i915_gem_lastclose(struct drm_device *dev) | |
3893 | { | |
3894 | int ret; | |
673a394b | 3895 | |
e806b495 EA |
3896 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3897 | return; | |
3898 | ||
6dbe2772 KP |
3899 | ret = i915_gem_idle(dev); |
3900 | if (ret) | |
3901 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
3902 | } |
3903 | ||
64193406 CW |
3904 | static void |
3905 | init_ring_lists(struct intel_ring_buffer *ring) | |
3906 | { | |
3907 | INIT_LIST_HEAD(&ring->active_list); | |
3908 | INIT_LIST_HEAD(&ring->request_list); | |
3909 | INIT_LIST_HEAD(&ring->gpu_write_list); | |
3910 | } | |
3911 | ||
673a394b EA |
3912 | void |
3913 | i915_gem_load(struct drm_device *dev) | |
3914 | { | |
b5aa8a0f | 3915 | int i; |
673a394b EA |
3916 | drm_i915_private_t *dev_priv = dev->dev_private; |
3917 | ||
69dc4987 | 3918 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b EA |
3919 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
3920 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); | |
f13d3f73 | 3921 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
a09ba7fa | 3922 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
be72615b | 3923 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
93a37f20 | 3924 | INIT_LIST_HEAD(&dev_priv->mm.gtt_list); |
1ec14ad3 CW |
3925 | for (i = 0; i < I915_NUM_RINGS; i++) |
3926 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 3927 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 3928 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
3929 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
3930 | i915_gem_retire_work_handler); | |
30dbf0c0 | 3931 | init_completion(&dev_priv->error_completion); |
31169714 | 3932 | |
94400120 DA |
3933 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
3934 | if (IS_GEN3(dev)) { | |
3935 | u32 tmp = I915_READ(MI_ARB_STATE); | |
3936 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { | |
3937 | /* arb state is a masked write, so set bit + bit in mask */ | |
3938 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); | |
3939 | I915_WRITE(MI_ARB_STATE, tmp); | |
3940 | } | |
3941 | } | |
3942 | ||
72bfa19c CW |
3943 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
3944 | ||
de151cf6 | 3945 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
3946 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
3947 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 3948 | |
a6c45cf0 | 3949 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
3950 | dev_priv->num_fence_regs = 16; |
3951 | else | |
3952 | dev_priv->num_fence_regs = 8; | |
3953 | ||
b5aa8a0f | 3954 | /* Initialize fence registers to zero */ |
10ed13e4 EA |
3955 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
3956 | i915_gem_clear_fence_reg(dev, &dev_priv->fence_regs[i]); | |
b5aa8a0f | 3957 | } |
10ed13e4 | 3958 | |
673a394b | 3959 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 3960 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 3961 | |
ce453d81 CW |
3962 | dev_priv->mm.interruptible = true; |
3963 | ||
17250b71 CW |
3964 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
3965 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
3966 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 3967 | } |
71acb5eb DA |
3968 | |
3969 | /* | |
3970 | * Create a physically contiguous memory object for this object | |
3971 | * e.g. for cursor + overlay regs | |
3972 | */ | |
995b6762 CW |
3973 | static int i915_gem_init_phys_object(struct drm_device *dev, |
3974 | int id, int size, int align) | |
71acb5eb DA |
3975 | { |
3976 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3977 | struct drm_i915_gem_phys_object *phys_obj; | |
3978 | int ret; | |
3979 | ||
3980 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
3981 | return 0; | |
3982 | ||
9a298b2a | 3983 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
3984 | if (!phys_obj) |
3985 | return -ENOMEM; | |
3986 | ||
3987 | phys_obj->id = id; | |
3988 | ||
6eeefaf3 | 3989 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
3990 | if (!phys_obj->handle) { |
3991 | ret = -ENOMEM; | |
3992 | goto kfree_obj; | |
3993 | } | |
3994 | #ifdef CONFIG_X86 | |
3995 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
3996 | #endif | |
3997 | ||
3998 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
3999 | ||
4000 | return 0; | |
4001 | kfree_obj: | |
9a298b2a | 4002 | kfree(phys_obj); |
71acb5eb DA |
4003 | return ret; |
4004 | } | |
4005 | ||
995b6762 | 4006 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4007 | { |
4008 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4009 | struct drm_i915_gem_phys_object *phys_obj; | |
4010 | ||
4011 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4012 | return; | |
4013 | ||
4014 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4015 | if (phys_obj->cur_obj) { | |
4016 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4017 | } | |
4018 | ||
4019 | #ifdef CONFIG_X86 | |
4020 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4021 | #endif | |
4022 | drm_pci_free(dev, phys_obj->handle); | |
4023 | kfree(phys_obj); | |
4024 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4025 | } | |
4026 | ||
4027 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4028 | { | |
4029 | int i; | |
4030 | ||
260883c8 | 4031 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4032 | i915_gem_free_phys_object(dev, i); |
4033 | } | |
4034 | ||
4035 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 4036 | struct drm_i915_gem_object *obj) |
71acb5eb | 4037 | { |
05394f39 | 4038 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
e5281ccd | 4039 | char *vaddr; |
71acb5eb | 4040 | int i; |
71acb5eb DA |
4041 | int page_count; |
4042 | ||
05394f39 | 4043 | if (!obj->phys_obj) |
71acb5eb | 4044 | return; |
05394f39 | 4045 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 4046 | |
05394f39 | 4047 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 4048 | for (i = 0; i < page_count; i++) { |
5949eac4 | 4049 | struct page *page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4050 | if (!IS_ERR(page)) { |
4051 | char *dst = kmap_atomic(page); | |
4052 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
4053 | kunmap_atomic(dst); | |
4054 | ||
4055 | drm_clflush_pages(&page, 1); | |
4056 | ||
4057 | set_page_dirty(page); | |
4058 | mark_page_accessed(page); | |
4059 | page_cache_release(page); | |
4060 | } | |
71acb5eb | 4061 | } |
40ce6575 | 4062 | intel_gtt_chipset_flush(); |
d78b47b9 | 4063 | |
05394f39 CW |
4064 | obj->phys_obj->cur_obj = NULL; |
4065 | obj->phys_obj = NULL; | |
71acb5eb DA |
4066 | } |
4067 | ||
4068 | int | |
4069 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 4070 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
4071 | int id, |
4072 | int align) | |
71acb5eb | 4073 | { |
05394f39 | 4074 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
71acb5eb | 4075 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
4076 | int ret = 0; |
4077 | int page_count; | |
4078 | int i; | |
4079 | ||
4080 | if (id > I915_MAX_PHYS_OBJECT) | |
4081 | return -EINVAL; | |
4082 | ||
05394f39 CW |
4083 | if (obj->phys_obj) { |
4084 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
4085 | return 0; |
4086 | i915_gem_detach_phys_object(dev, obj); | |
4087 | } | |
4088 | ||
71acb5eb DA |
4089 | /* create a new object */ |
4090 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4091 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 4092 | obj->base.size, align); |
71acb5eb | 4093 | if (ret) { |
05394f39 CW |
4094 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
4095 | id, obj->base.size); | |
e5281ccd | 4096 | return ret; |
71acb5eb DA |
4097 | } |
4098 | } | |
4099 | ||
4100 | /* bind to the object */ | |
05394f39 CW |
4101 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
4102 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 4103 | |
05394f39 | 4104 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
4105 | |
4106 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4107 | struct page *page; |
4108 | char *dst, *src; | |
4109 | ||
5949eac4 | 4110 | page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4111 | if (IS_ERR(page)) |
4112 | return PTR_ERR(page); | |
71acb5eb | 4113 | |
ff75b9bc | 4114 | src = kmap_atomic(page); |
05394f39 | 4115 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 4116 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 4117 | kunmap_atomic(src); |
71acb5eb | 4118 | |
e5281ccd CW |
4119 | mark_page_accessed(page); |
4120 | page_cache_release(page); | |
4121 | } | |
d78b47b9 | 4122 | |
71acb5eb | 4123 | return 0; |
71acb5eb DA |
4124 | } |
4125 | ||
4126 | static int | |
05394f39 CW |
4127 | i915_gem_phys_pwrite(struct drm_device *dev, |
4128 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
4129 | struct drm_i915_gem_pwrite *args, |
4130 | struct drm_file *file_priv) | |
4131 | { | |
05394f39 | 4132 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
b47b30cc | 4133 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
71acb5eb | 4134 | |
b47b30cc CW |
4135 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
4136 | unsigned long unwritten; | |
4137 | ||
4138 | /* The physical object once assigned is fixed for the lifetime | |
4139 | * of the obj, so we can safely drop the lock and continue | |
4140 | * to access vaddr. | |
4141 | */ | |
4142 | mutex_unlock(&dev->struct_mutex); | |
4143 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
4144 | mutex_lock(&dev->struct_mutex); | |
4145 | if (unwritten) | |
4146 | return -EFAULT; | |
4147 | } | |
71acb5eb | 4148 | |
40ce6575 | 4149 | intel_gtt_chipset_flush(); |
71acb5eb DA |
4150 | return 0; |
4151 | } | |
b962442e | 4152 | |
f787a5f5 | 4153 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4154 | { |
f787a5f5 | 4155 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4156 | |
4157 | /* Clean up our request list when the client is going away, so that | |
4158 | * later retire_requests won't dereference our soon-to-be-gone | |
4159 | * file_priv. | |
4160 | */ | |
1c25595f | 4161 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4162 | while (!list_empty(&file_priv->mm.request_list)) { |
4163 | struct drm_i915_gem_request *request; | |
4164 | ||
4165 | request = list_first_entry(&file_priv->mm.request_list, | |
4166 | struct drm_i915_gem_request, | |
4167 | client_list); | |
4168 | list_del(&request->client_list); | |
4169 | request->file_priv = NULL; | |
4170 | } | |
1c25595f | 4171 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4172 | } |
31169714 | 4173 | |
1637ef41 CW |
4174 | static int |
4175 | i915_gpu_is_active(struct drm_device *dev) | |
4176 | { | |
4177 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4178 | int lists_empty; | |
4179 | ||
1637ef41 | 4180 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
17250b71 | 4181 | list_empty(&dev_priv->mm.active_list); |
1637ef41 CW |
4182 | |
4183 | return !lists_empty; | |
4184 | } | |
4185 | ||
31169714 | 4186 | static int |
1495f230 | 4187 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 4188 | { |
17250b71 CW |
4189 | struct drm_i915_private *dev_priv = |
4190 | container_of(shrinker, | |
4191 | struct drm_i915_private, | |
4192 | mm.inactive_shrinker); | |
4193 | struct drm_device *dev = dev_priv->dev; | |
4194 | struct drm_i915_gem_object *obj, *next; | |
1495f230 | 4195 | int nr_to_scan = sc->nr_to_scan; |
17250b71 CW |
4196 | int cnt; |
4197 | ||
4198 | if (!mutex_trylock(&dev->struct_mutex)) | |
bbe2e11a | 4199 | return 0; |
31169714 CW |
4200 | |
4201 | /* "fast-path" to count number of available objects */ | |
4202 | if (nr_to_scan == 0) { | |
17250b71 CW |
4203 | cnt = 0; |
4204 | list_for_each_entry(obj, | |
4205 | &dev_priv->mm.inactive_list, | |
4206 | mm_list) | |
4207 | cnt++; | |
4208 | mutex_unlock(&dev->struct_mutex); | |
4209 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 CW |
4210 | } |
4211 | ||
1637ef41 | 4212 | rescan: |
31169714 | 4213 | /* first scan for clean buffers */ |
17250b71 | 4214 | i915_gem_retire_requests(dev); |
31169714 | 4215 | |
17250b71 CW |
4216 | list_for_each_entry_safe(obj, next, |
4217 | &dev_priv->mm.inactive_list, | |
4218 | mm_list) { | |
4219 | if (i915_gem_object_is_purgeable(obj)) { | |
2021746e CW |
4220 | if (i915_gem_object_unbind(obj) == 0 && |
4221 | --nr_to_scan == 0) | |
17250b71 | 4222 | break; |
31169714 | 4223 | } |
31169714 CW |
4224 | } |
4225 | ||
4226 | /* second pass, evict/count anything still on the inactive list */ | |
17250b71 CW |
4227 | cnt = 0; |
4228 | list_for_each_entry_safe(obj, next, | |
4229 | &dev_priv->mm.inactive_list, | |
4230 | mm_list) { | |
2021746e CW |
4231 | if (nr_to_scan && |
4232 | i915_gem_object_unbind(obj) == 0) | |
17250b71 | 4233 | nr_to_scan--; |
2021746e | 4234 | else |
17250b71 CW |
4235 | cnt++; |
4236 | } | |
4237 | ||
4238 | if (nr_to_scan && i915_gpu_is_active(dev)) { | |
1637ef41 CW |
4239 | /* |
4240 | * We are desperate for pages, so as a last resort, wait | |
4241 | * for the GPU to finish and discard whatever we can. | |
4242 | * This has a dramatic impact to reduce the number of | |
4243 | * OOM-killer events whilst running the GPU aggressively. | |
4244 | */ | |
b93f9cf1 | 4245 | if (i915_gpu_idle(dev, true) == 0) |
1637ef41 CW |
4246 | goto rescan; |
4247 | } | |
17250b71 CW |
4248 | mutex_unlock(&dev->struct_mutex); |
4249 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 | 4250 | } |