Commit | Line | Data |
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673a394b | 1 | /* |
be6a0376 | 2 | * Copyright © 2008-2015 Intel Corporation |
673a394b EA |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
c13d87ea | 32 | #include "i915_gem_dmabuf.h" |
eb82289a | 33 | #include "i915_vgpu.h" |
1c5d22f7 | 34 | #include "i915_trace.h" |
652c393a | 35 | #include "intel_drv.h" |
0ccdacf6 | 36 | #include "intel_mocs.h" |
c13d87ea | 37 | #include <linux/reservation.h> |
5949eac4 | 38 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 39 | #include <linux/slab.h> |
673a394b | 40 | #include <linux/swap.h> |
79e53945 | 41 | #include <linux/pci.h> |
1286ff73 | 42 | #include <linux/dma-buf.h> |
673a394b | 43 | |
05394f39 | 44 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
e62b59e4 | 45 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
61050808 | 46 | |
c76ce038 CW |
47 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
48 | enum i915_cache_level level) | |
49 | { | |
50 | return HAS_LLC(dev) || level != I915_CACHE_NONE; | |
51 | } | |
52 | ||
2c22569b CW |
53 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
54 | { | |
b50a5371 AS |
55 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
56 | return false; | |
57 | ||
2c22569b CW |
58 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
59 | return true; | |
60 | ||
61 | return obj->pin_display; | |
62 | } | |
63 | ||
4f1959ee AS |
64 | static int |
65 | insert_mappable_node(struct drm_i915_private *i915, | |
66 | struct drm_mm_node *node, u32 size) | |
67 | { | |
68 | memset(node, 0, sizeof(*node)); | |
69 | return drm_mm_insert_node_in_range_generic(&i915->ggtt.base.mm, node, | |
70 | size, 0, 0, 0, | |
71 | i915->ggtt.mappable_end, | |
72 | DRM_MM_SEARCH_DEFAULT, | |
73 | DRM_MM_CREATE_DEFAULT); | |
74 | } | |
75 | ||
76 | static void | |
77 | remove_mappable_node(struct drm_mm_node *node) | |
78 | { | |
79 | drm_mm_remove_node(node); | |
80 | } | |
81 | ||
73aa808f CW |
82 | /* some bookkeeping */ |
83 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
84 | size_t size) | |
85 | { | |
c20e8355 | 86 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
87 | dev_priv->mm.object_count++; |
88 | dev_priv->mm.object_memory += size; | |
c20e8355 | 89 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
90 | } |
91 | ||
92 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
93 | size_t size) | |
94 | { | |
c20e8355 | 95 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
96 | dev_priv->mm.object_count--; |
97 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 98 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
99 | } |
100 | ||
21dd3734 | 101 | static int |
33196ded | 102 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 103 | { |
30dbf0c0 CW |
104 | int ret; |
105 | ||
d98c52cf | 106 | if (!i915_reset_in_progress(error)) |
30dbf0c0 CW |
107 | return 0; |
108 | ||
0a6759c6 DV |
109 | /* |
110 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
111 | * userspace. If it takes that long something really bad is going on and | |
112 | * we should simply try to bail out and fail as gracefully as possible. | |
113 | */ | |
1f83fee0 | 114 | ret = wait_event_interruptible_timeout(error->reset_queue, |
d98c52cf | 115 | !i915_reset_in_progress(error), |
1f83fee0 | 116 | 10*HZ); |
0a6759c6 DV |
117 | if (ret == 0) { |
118 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
119 | return -EIO; | |
120 | } else if (ret < 0) { | |
30dbf0c0 | 121 | return ret; |
d98c52cf CW |
122 | } else { |
123 | return 0; | |
0a6759c6 | 124 | } |
30dbf0c0 CW |
125 | } |
126 | ||
54cf91dc | 127 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 128 | { |
fac5e23e | 129 | struct drm_i915_private *dev_priv = to_i915(dev); |
76c1dec1 CW |
130 | int ret; |
131 | ||
33196ded | 132 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
133 | if (ret) |
134 | return ret; | |
135 | ||
136 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
137 | if (ret) | |
138 | return ret; | |
139 | ||
76c1dec1 CW |
140 | return 0; |
141 | } | |
30dbf0c0 | 142 | |
5a125c3c EA |
143 | int |
144 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 145 | struct drm_file *file) |
5a125c3c | 146 | { |
72e96d64 | 147 | struct drm_i915_private *dev_priv = to_i915(dev); |
62106b4f | 148 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
72e96d64 | 149 | struct drm_i915_gem_get_aperture *args = data; |
ca1543be | 150 | struct i915_vma *vma; |
6299f992 | 151 | size_t pinned; |
5a125c3c | 152 | |
6299f992 | 153 | pinned = 0; |
73aa808f | 154 | mutex_lock(&dev->struct_mutex); |
1c7f4bca | 155 | list_for_each_entry(vma, &ggtt->base.active_list, vm_link) |
20dfbde4 | 156 | if (i915_vma_is_pinned(vma)) |
ca1543be | 157 | pinned += vma->node.size; |
1c7f4bca | 158 | list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link) |
20dfbde4 | 159 | if (i915_vma_is_pinned(vma)) |
ca1543be | 160 | pinned += vma->node.size; |
73aa808f | 161 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 162 | |
72e96d64 | 163 | args->aper_size = ggtt->base.total; |
0206e353 | 164 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 165 | |
5a125c3c EA |
166 | return 0; |
167 | } | |
168 | ||
6a2c4232 CW |
169 | static int |
170 | i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) | |
00731155 | 171 | { |
6a2c4232 CW |
172 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
173 | char *vaddr = obj->phys_handle->vaddr; | |
174 | struct sg_table *st; | |
175 | struct scatterlist *sg; | |
176 | int i; | |
00731155 | 177 | |
6a2c4232 CW |
178 | if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) |
179 | return -EINVAL; | |
180 | ||
181 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
182 | struct page *page; | |
183 | char *src; | |
184 | ||
185 | page = shmem_read_mapping_page(mapping, i); | |
186 | if (IS_ERR(page)) | |
187 | return PTR_ERR(page); | |
188 | ||
189 | src = kmap_atomic(page); | |
190 | memcpy(vaddr, src, PAGE_SIZE); | |
191 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
192 | kunmap_atomic(src); | |
193 | ||
09cbfeaf | 194 | put_page(page); |
6a2c4232 CW |
195 | vaddr += PAGE_SIZE; |
196 | } | |
197 | ||
c033666a | 198 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
6a2c4232 CW |
199 | |
200 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
201 | if (st == NULL) | |
202 | return -ENOMEM; | |
203 | ||
204 | if (sg_alloc_table(st, 1, GFP_KERNEL)) { | |
205 | kfree(st); | |
206 | return -ENOMEM; | |
207 | } | |
208 | ||
209 | sg = st->sgl; | |
210 | sg->offset = 0; | |
211 | sg->length = obj->base.size; | |
00731155 | 212 | |
6a2c4232 CW |
213 | sg_dma_address(sg) = obj->phys_handle->busaddr; |
214 | sg_dma_len(sg) = obj->base.size; | |
215 | ||
216 | obj->pages = st; | |
6a2c4232 CW |
217 | return 0; |
218 | } | |
219 | ||
220 | static void | |
221 | i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj) | |
222 | { | |
223 | int ret; | |
224 | ||
225 | BUG_ON(obj->madv == __I915_MADV_PURGED); | |
00731155 | 226 | |
6a2c4232 | 227 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
f4457ae7 | 228 | if (WARN_ON(ret)) { |
6a2c4232 CW |
229 | /* In the event of a disaster, abandon all caches and |
230 | * hope for the best. | |
231 | */ | |
6a2c4232 CW |
232 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
233 | } | |
234 | ||
235 | if (obj->madv == I915_MADV_DONTNEED) | |
236 | obj->dirty = 0; | |
237 | ||
238 | if (obj->dirty) { | |
00731155 | 239 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
6a2c4232 | 240 | char *vaddr = obj->phys_handle->vaddr; |
00731155 CW |
241 | int i; |
242 | ||
243 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
6a2c4232 CW |
244 | struct page *page; |
245 | char *dst; | |
246 | ||
247 | page = shmem_read_mapping_page(mapping, i); | |
248 | if (IS_ERR(page)) | |
249 | continue; | |
250 | ||
251 | dst = kmap_atomic(page); | |
252 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
253 | memcpy(dst, vaddr, PAGE_SIZE); | |
254 | kunmap_atomic(dst); | |
255 | ||
256 | set_page_dirty(page); | |
257 | if (obj->madv == I915_MADV_WILLNEED) | |
00731155 | 258 | mark_page_accessed(page); |
09cbfeaf | 259 | put_page(page); |
00731155 CW |
260 | vaddr += PAGE_SIZE; |
261 | } | |
6a2c4232 | 262 | obj->dirty = 0; |
00731155 CW |
263 | } |
264 | ||
6a2c4232 CW |
265 | sg_free_table(obj->pages); |
266 | kfree(obj->pages); | |
6a2c4232 CW |
267 | } |
268 | ||
269 | static void | |
270 | i915_gem_object_release_phys(struct drm_i915_gem_object *obj) | |
271 | { | |
272 | drm_pci_free(obj->base.dev, obj->phys_handle); | |
273 | } | |
274 | ||
275 | static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { | |
276 | .get_pages = i915_gem_object_get_pages_phys, | |
277 | .put_pages = i915_gem_object_put_pages_phys, | |
278 | .release = i915_gem_object_release_phys, | |
279 | }; | |
280 | ||
aa653a68 CW |
281 | int |
282 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) | |
283 | { | |
284 | struct i915_vma *vma; | |
285 | LIST_HEAD(still_in_list); | |
286 | int ret; | |
287 | ||
288 | /* The vma will only be freed if it is marked as closed, and if we wait | |
289 | * upon rendering to the vma, we may unbind anything in the list. | |
290 | */ | |
291 | while ((vma = list_first_entry_or_null(&obj->vma_list, | |
292 | struct i915_vma, | |
293 | obj_link))) { | |
294 | list_move_tail(&vma->obj_link, &still_in_list); | |
295 | ret = i915_vma_unbind(vma); | |
296 | if (ret) | |
297 | break; | |
298 | } | |
299 | list_splice(&still_in_list, &obj->vma_list); | |
300 | ||
301 | return ret; | |
302 | } | |
303 | ||
00731155 CW |
304 | int |
305 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, | |
306 | int align) | |
307 | { | |
308 | drm_dma_handle_t *phys; | |
6a2c4232 | 309 | int ret; |
00731155 CW |
310 | |
311 | if (obj->phys_handle) { | |
312 | if ((unsigned long)obj->phys_handle->vaddr & (align -1)) | |
313 | return -EBUSY; | |
314 | ||
315 | return 0; | |
316 | } | |
317 | ||
318 | if (obj->madv != I915_MADV_WILLNEED) | |
319 | return -EFAULT; | |
320 | ||
321 | if (obj->base.filp == NULL) | |
322 | return -EINVAL; | |
323 | ||
4717ca9e CW |
324 | ret = i915_gem_object_unbind(obj); |
325 | if (ret) | |
326 | return ret; | |
327 | ||
328 | ret = i915_gem_object_put_pages(obj); | |
6a2c4232 CW |
329 | if (ret) |
330 | return ret; | |
331 | ||
00731155 CW |
332 | /* create a new object */ |
333 | phys = drm_pci_alloc(obj->base.dev, obj->base.size, align); | |
334 | if (!phys) | |
335 | return -ENOMEM; | |
336 | ||
00731155 | 337 | obj->phys_handle = phys; |
6a2c4232 CW |
338 | obj->ops = &i915_gem_phys_ops; |
339 | ||
340 | return i915_gem_object_get_pages(obj); | |
00731155 CW |
341 | } |
342 | ||
343 | static int | |
344 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, | |
345 | struct drm_i915_gem_pwrite *args, | |
346 | struct drm_file *file_priv) | |
347 | { | |
348 | struct drm_device *dev = obj->base.dev; | |
349 | void *vaddr = obj->phys_handle->vaddr + args->offset; | |
3ed605bc | 350 | char __user *user_data = u64_to_user_ptr(args->data_ptr); |
063e4e6b | 351 | int ret = 0; |
6a2c4232 CW |
352 | |
353 | /* We manually control the domain here and pretend that it | |
354 | * remains coherent i.e. in the GTT domain, like shmem_pwrite. | |
355 | */ | |
356 | ret = i915_gem_object_wait_rendering(obj, false); | |
357 | if (ret) | |
358 | return ret; | |
00731155 | 359 | |
77a0d1ca | 360 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
00731155 CW |
361 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
362 | unsigned long unwritten; | |
363 | ||
364 | /* The physical object once assigned is fixed for the lifetime | |
365 | * of the obj, so we can safely drop the lock and continue | |
366 | * to access vaddr. | |
367 | */ | |
368 | mutex_unlock(&dev->struct_mutex); | |
369 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
370 | mutex_lock(&dev->struct_mutex); | |
063e4e6b PZ |
371 | if (unwritten) { |
372 | ret = -EFAULT; | |
373 | goto out; | |
374 | } | |
00731155 CW |
375 | } |
376 | ||
6a2c4232 | 377 | drm_clflush_virt_range(vaddr, args->size); |
c033666a | 378 | i915_gem_chipset_flush(to_i915(dev)); |
063e4e6b PZ |
379 | |
380 | out: | |
de152b62 | 381 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
063e4e6b | 382 | return ret; |
00731155 CW |
383 | } |
384 | ||
42dcedd4 CW |
385 | void *i915_gem_object_alloc(struct drm_device *dev) |
386 | { | |
fac5e23e | 387 | struct drm_i915_private *dev_priv = to_i915(dev); |
efab6d8d | 388 | return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL); |
42dcedd4 CW |
389 | } |
390 | ||
391 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
392 | { | |
fac5e23e | 393 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
efab6d8d | 394 | kmem_cache_free(dev_priv->objects, obj); |
42dcedd4 CW |
395 | } |
396 | ||
ff72145b DA |
397 | static int |
398 | i915_gem_create(struct drm_file *file, | |
399 | struct drm_device *dev, | |
400 | uint64_t size, | |
401 | uint32_t *handle_p) | |
673a394b | 402 | { |
05394f39 | 403 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
404 | int ret; |
405 | u32 handle; | |
673a394b | 406 | |
ff72145b | 407 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
408 | if (size == 0) |
409 | return -EINVAL; | |
673a394b EA |
410 | |
411 | /* Allocate the new object */ | |
d37cd8a8 | 412 | obj = i915_gem_object_create(dev, size); |
fe3db79b CW |
413 | if (IS_ERR(obj)) |
414 | return PTR_ERR(obj); | |
673a394b | 415 | |
05394f39 | 416 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 417 | /* drop reference from allocate - handle holds it now */ |
34911fd3 | 418 | i915_gem_object_put_unlocked(obj); |
d861e338 DV |
419 | if (ret) |
420 | return ret; | |
202f2fef | 421 | |
ff72145b | 422 | *handle_p = handle; |
673a394b EA |
423 | return 0; |
424 | } | |
425 | ||
ff72145b DA |
426 | int |
427 | i915_gem_dumb_create(struct drm_file *file, | |
428 | struct drm_device *dev, | |
429 | struct drm_mode_create_dumb *args) | |
430 | { | |
431 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 432 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b DA |
433 | args->size = args->pitch * args->height; |
434 | return i915_gem_create(file, dev, | |
da6b51d0 | 435 | args->size, &args->handle); |
ff72145b DA |
436 | } |
437 | ||
ff72145b DA |
438 | /** |
439 | * Creates a new mm object and returns a handle to it. | |
14bb2c11 TU |
440 | * @dev: drm device pointer |
441 | * @data: ioctl data blob | |
442 | * @file: drm file pointer | |
ff72145b DA |
443 | */ |
444 | int | |
445 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
446 | struct drm_file *file) | |
447 | { | |
448 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 449 | |
ff72145b | 450 | return i915_gem_create(file, dev, |
da6b51d0 | 451 | args->size, &args->handle); |
ff72145b DA |
452 | } |
453 | ||
8461d226 DV |
454 | static inline int |
455 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
456 | const char *gpu_vaddr, int gpu_offset, | |
457 | int length) | |
458 | { | |
459 | int ret, cpu_offset = 0; | |
460 | ||
461 | while (length > 0) { | |
462 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
463 | int this_length = min(cacheline_end - gpu_offset, length); | |
464 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
465 | ||
466 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
467 | gpu_vaddr + swizzled_gpu_offset, | |
468 | this_length); | |
469 | if (ret) | |
470 | return ret + length; | |
471 | ||
472 | cpu_offset += this_length; | |
473 | gpu_offset += this_length; | |
474 | length -= this_length; | |
475 | } | |
476 | ||
477 | return 0; | |
478 | } | |
479 | ||
8c59967c | 480 | static inline int |
4f0c7cfb BW |
481 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
482 | const char __user *cpu_vaddr, | |
8c59967c DV |
483 | int length) |
484 | { | |
485 | int ret, cpu_offset = 0; | |
486 | ||
487 | while (length > 0) { | |
488 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
489 | int this_length = min(cacheline_end - gpu_offset, length); | |
490 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
491 | ||
492 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
493 | cpu_vaddr + cpu_offset, | |
494 | this_length); | |
495 | if (ret) | |
496 | return ret + length; | |
497 | ||
498 | cpu_offset += this_length; | |
499 | gpu_offset += this_length; | |
500 | length -= this_length; | |
501 | } | |
502 | ||
503 | return 0; | |
504 | } | |
505 | ||
4c914c0c BV |
506 | /* |
507 | * Pins the specified object's pages and synchronizes the object with | |
508 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
509 | * flush the object from the CPU cache. | |
510 | */ | |
511 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
512 | int *needs_clflush) | |
513 | { | |
514 | int ret; | |
515 | ||
516 | *needs_clflush = 0; | |
517 | ||
b9bcd14a | 518 | if (WARN_ON(!i915_gem_object_has_struct_page(obj))) |
4c914c0c BV |
519 | return -EINVAL; |
520 | ||
c13d87ea CW |
521 | ret = i915_gem_object_wait_rendering(obj, true); |
522 | if (ret) | |
523 | return ret; | |
524 | ||
4c914c0c BV |
525 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
526 | /* If we're not in the cpu read domain, set ourself into the gtt | |
527 | * read domain and manually flush cachelines (if required). This | |
528 | * optimizes for the case when the gpu will dirty the data | |
529 | * anyway again before the next pread happens. */ | |
530 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, | |
531 | obj->cache_level); | |
4c914c0c BV |
532 | } |
533 | ||
534 | ret = i915_gem_object_get_pages(obj); | |
535 | if (ret) | |
536 | return ret; | |
537 | ||
538 | i915_gem_object_pin_pages(obj); | |
539 | ||
540 | return ret; | |
541 | } | |
542 | ||
d174bd64 DV |
543 | /* Per-page copy function for the shmem pread fastpath. |
544 | * Flushes invalid cachelines before reading the target if | |
545 | * needs_clflush is set. */ | |
eb01459f | 546 | static int |
d174bd64 DV |
547 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
548 | char __user *user_data, | |
549 | bool page_do_bit17_swizzling, bool needs_clflush) | |
550 | { | |
551 | char *vaddr; | |
552 | int ret; | |
553 | ||
e7e58eb5 | 554 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
555 | return -EINVAL; |
556 | ||
557 | vaddr = kmap_atomic(page); | |
558 | if (needs_clflush) | |
559 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
560 | page_length); | |
561 | ret = __copy_to_user_inatomic(user_data, | |
562 | vaddr + shmem_page_offset, | |
563 | page_length); | |
564 | kunmap_atomic(vaddr); | |
565 | ||
f60d7f0c | 566 | return ret ? -EFAULT : 0; |
d174bd64 DV |
567 | } |
568 | ||
23c18c71 DV |
569 | static void |
570 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
571 | bool swizzled) | |
572 | { | |
e7e58eb5 | 573 | if (unlikely(swizzled)) { |
23c18c71 DV |
574 | unsigned long start = (unsigned long) addr; |
575 | unsigned long end = (unsigned long) addr + length; | |
576 | ||
577 | /* For swizzling simply ensure that we always flush both | |
578 | * channels. Lame, but simple and it works. Swizzled | |
579 | * pwrite/pread is far from a hotpath - current userspace | |
580 | * doesn't use it at all. */ | |
581 | start = round_down(start, 128); | |
582 | end = round_up(end, 128); | |
583 | ||
584 | drm_clflush_virt_range((void *)start, end - start); | |
585 | } else { | |
586 | drm_clflush_virt_range(addr, length); | |
587 | } | |
588 | ||
589 | } | |
590 | ||
d174bd64 DV |
591 | /* Only difference to the fast-path function is that this can handle bit17 |
592 | * and uses non-atomic copy and kmap functions. */ | |
593 | static int | |
594 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
595 | char __user *user_data, | |
596 | bool page_do_bit17_swizzling, bool needs_clflush) | |
597 | { | |
598 | char *vaddr; | |
599 | int ret; | |
600 | ||
601 | vaddr = kmap(page); | |
602 | if (needs_clflush) | |
23c18c71 DV |
603 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
604 | page_length, | |
605 | page_do_bit17_swizzling); | |
d174bd64 DV |
606 | |
607 | if (page_do_bit17_swizzling) | |
608 | ret = __copy_to_user_swizzled(user_data, | |
609 | vaddr, shmem_page_offset, | |
610 | page_length); | |
611 | else | |
612 | ret = __copy_to_user(user_data, | |
613 | vaddr + shmem_page_offset, | |
614 | page_length); | |
615 | kunmap(page); | |
616 | ||
f60d7f0c | 617 | return ret ? - EFAULT : 0; |
d174bd64 DV |
618 | } |
619 | ||
b50a5371 AS |
620 | static inline unsigned long |
621 | slow_user_access(struct io_mapping *mapping, | |
622 | uint64_t page_base, int page_offset, | |
623 | char __user *user_data, | |
624 | unsigned long length, bool pwrite) | |
625 | { | |
626 | void __iomem *ioaddr; | |
627 | void *vaddr; | |
628 | uint64_t unwritten; | |
629 | ||
630 | ioaddr = io_mapping_map_wc(mapping, page_base, PAGE_SIZE); | |
631 | /* We can use the cpu mem copy function because this is X86. */ | |
632 | vaddr = (void __force *)ioaddr + page_offset; | |
633 | if (pwrite) | |
634 | unwritten = __copy_from_user(vaddr, user_data, length); | |
635 | else | |
636 | unwritten = __copy_to_user(user_data, vaddr, length); | |
637 | ||
638 | io_mapping_unmap(ioaddr); | |
639 | return unwritten; | |
640 | } | |
641 | ||
642 | static int | |
643 | i915_gem_gtt_pread(struct drm_device *dev, | |
644 | struct drm_i915_gem_object *obj, uint64_t size, | |
645 | uint64_t data_offset, uint64_t data_ptr) | |
646 | { | |
fac5e23e | 647 | struct drm_i915_private *dev_priv = to_i915(dev); |
b50a5371 AS |
648 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
649 | struct drm_mm_node node; | |
650 | char __user *user_data; | |
651 | uint64_t remain; | |
652 | uint64_t offset; | |
653 | int ret; | |
654 | ||
655 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE); | |
656 | if (ret) { | |
657 | ret = insert_mappable_node(dev_priv, &node, PAGE_SIZE); | |
658 | if (ret) | |
659 | goto out; | |
660 | ||
661 | ret = i915_gem_object_get_pages(obj); | |
662 | if (ret) { | |
663 | remove_mappable_node(&node); | |
664 | goto out; | |
665 | } | |
666 | ||
667 | i915_gem_object_pin_pages(obj); | |
668 | } else { | |
669 | node.start = i915_gem_obj_ggtt_offset(obj); | |
670 | node.allocated = false; | |
671 | ret = i915_gem_object_put_fence(obj); | |
672 | if (ret) | |
673 | goto out_unpin; | |
674 | } | |
675 | ||
676 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
677 | if (ret) | |
678 | goto out_unpin; | |
679 | ||
680 | user_data = u64_to_user_ptr(data_ptr); | |
681 | remain = size; | |
682 | offset = data_offset; | |
683 | ||
684 | mutex_unlock(&dev->struct_mutex); | |
685 | if (likely(!i915.prefault_disable)) { | |
686 | ret = fault_in_multipages_writeable(user_data, remain); | |
687 | if (ret) { | |
688 | mutex_lock(&dev->struct_mutex); | |
689 | goto out_unpin; | |
690 | } | |
691 | } | |
692 | ||
693 | while (remain > 0) { | |
694 | /* Operation in this page | |
695 | * | |
696 | * page_base = page offset within aperture | |
697 | * page_offset = offset within page | |
698 | * page_length = bytes to copy for this page | |
699 | */ | |
700 | u32 page_base = node.start; | |
701 | unsigned page_offset = offset_in_page(offset); | |
702 | unsigned page_length = PAGE_SIZE - page_offset; | |
703 | page_length = remain < page_length ? remain : page_length; | |
704 | if (node.allocated) { | |
705 | wmb(); | |
706 | ggtt->base.insert_page(&ggtt->base, | |
707 | i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT), | |
708 | node.start, | |
709 | I915_CACHE_NONE, 0); | |
710 | wmb(); | |
711 | } else { | |
712 | page_base += offset & PAGE_MASK; | |
713 | } | |
714 | /* This is a slow read/write as it tries to read from | |
715 | * and write to user memory which may result into page | |
716 | * faults, and so we cannot perform this under struct_mutex. | |
717 | */ | |
718 | if (slow_user_access(ggtt->mappable, page_base, | |
719 | page_offset, user_data, | |
720 | page_length, false)) { | |
721 | ret = -EFAULT; | |
722 | break; | |
723 | } | |
724 | ||
725 | remain -= page_length; | |
726 | user_data += page_length; | |
727 | offset += page_length; | |
728 | } | |
729 | ||
730 | mutex_lock(&dev->struct_mutex); | |
731 | if (ret == 0 && (obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) { | |
732 | /* The user has modified the object whilst we tried | |
733 | * reading from it, and we now have no idea what domain | |
734 | * the pages should be in. As we have just been touching | |
735 | * them directly, flush everything back to the GTT | |
736 | * domain. | |
737 | */ | |
738 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
739 | } | |
740 | ||
741 | out_unpin: | |
742 | if (node.allocated) { | |
743 | wmb(); | |
744 | ggtt->base.clear_range(&ggtt->base, | |
745 | node.start, node.size, | |
746 | true); | |
747 | i915_gem_object_unpin_pages(obj); | |
748 | remove_mappable_node(&node); | |
749 | } else { | |
750 | i915_gem_object_ggtt_unpin(obj); | |
751 | } | |
752 | out: | |
753 | return ret; | |
754 | } | |
755 | ||
eb01459f | 756 | static int |
dbf7bff0 DV |
757 | i915_gem_shmem_pread(struct drm_device *dev, |
758 | struct drm_i915_gem_object *obj, | |
759 | struct drm_i915_gem_pread *args, | |
760 | struct drm_file *file) | |
eb01459f | 761 | { |
8461d226 | 762 | char __user *user_data; |
eb01459f | 763 | ssize_t remain; |
8461d226 | 764 | loff_t offset; |
eb2c0c81 | 765 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 766 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 767 | int prefaulted = 0; |
8489731c | 768 | int needs_clflush = 0; |
67d5a50c | 769 | struct sg_page_iter sg_iter; |
eb01459f | 770 | |
6eae0059 | 771 | if (!i915_gem_object_has_struct_page(obj)) |
b50a5371 AS |
772 | return -ENODEV; |
773 | ||
3ed605bc | 774 | user_data = u64_to_user_ptr(args->data_ptr); |
eb01459f EA |
775 | remain = args->size; |
776 | ||
8461d226 | 777 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 778 | |
4c914c0c | 779 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); |
f60d7f0c CW |
780 | if (ret) |
781 | return ret; | |
782 | ||
8461d226 | 783 | offset = args->offset; |
eb01459f | 784 | |
67d5a50c ID |
785 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
786 | offset >> PAGE_SHIFT) { | |
2db76d7c | 787 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 CW |
788 | |
789 | if (remain <= 0) | |
790 | break; | |
791 | ||
eb01459f EA |
792 | /* Operation in this page |
793 | * | |
eb01459f | 794 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
795 | * page_length = bytes to copy for this page |
796 | */ | |
c8cbbb8b | 797 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
798 | page_length = remain; |
799 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
800 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 801 | |
8461d226 DV |
802 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
803 | (page_to_phys(page) & (1 << 17)) != 0; | |
804 | ||
d174bd64 DV |
805 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
806 | user_data, page_do_bit17_swizzling, | |
807 | needs_clflush); | |
808 | if (ret == 0) | |
809 | goto next_page; | |
dbf7bff0 | 810 | |
dbf7bff0 DV |
811 | mutex_unlock(&dev->struct_mutex); |
812 | ||
d330a953 | 813 | if (likely(!i915.prefault_disable) && !prefaulted) { |
f56f821f | 814 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
815 | /* Userspace is tricking us, but we've already clobbered |
816 | * its pages with the prefault and promised to write the | |
817 | * data up to the first fault. Hence ignore any errors | |
818 | * and just continue. */ | |
819 | (void)ret; | |
820 | prefaulted = 1; | |
821 | } | |
eb01459f | 822 | |
d174bd64 DV |
823 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
824 | user_data, page_do_bit17_swizzling, | |
825 | needs_clflush); | |
eb01459f | 826 | |
dbf7bff0 | 827 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 828 | |
f60d7f0c | 829 | if (ret) |
8461d226 | 830 | goto out; |
8461d226 | 831 | |
17793c9a | 832 | next_page: |
eb01459f | 833 | remain -= page_length; |
8461d226 | 834 | user_data += page_length; |
eb01459f EA |
835 | offset += page_length; |
836 | } | |
837 | ||
4f27b75d | 838 | out: |
f60d7f0c CW |
839 | i915_gem_object_unpin_pages(obj); |
840 | ||
eb01459f EA |
841 | return ret; |
842 | } | |
843 | ||
673a394b EA |
844 | /** |
845 | * Reads data from the object referenced by handle. | |
14bb2c11 TU |
846 | * @dev: drm device pointer |
847 | * @data: ioctl data blob | |
848 | * @file: drm file pointer | |
673a394b EA |
849 | * |
850 | * On error, the contents of *data are undefined. | |
851 | */ | |
852 | int | |
853 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 854 | struct drm_file *file) |
673a394b EA |
855 | { |
856 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 857 | struct drm_i915_gem_object *obj; |
35b62a89 | 858 | int ret = 0; |
673a394b | 859 | |
51311d0a CW |
860 | if (args->size == 0) |
861 | return 0; | |
862 | ||
863 | if (!access_ok(VERIFY_WRITE, | |
3ed605bc | 864 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
865 | args->size)) |
866 | return -EFAULT; | |
867 | ||
4f27b75d | 868 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 869 | if (ret) |
4f27b75d | 870 | return ret; |
673a394b | 871 | |
03ac0642 CW |
872 | obj = i915_gem_object_lookup(file, args->handle); |
873 | if (!obj) { | |
1d7cfea1 CW |
874 | ret = -ENOENT; |
875 | goto unlock; | |
4f27b75d | 876 | } |
673a394b | 877 | |
7dcd2499 | 878 | /* Bounds check source. */ |
05394f39 CW |
879 | if (args->offset > obj->base.size || |
880 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 881 | ret = -EINVAL; |
35b62a89 | 882 | goto out; |
ce9d419d CW |
883 | } |
884 | ||
db53a302 CW |
885 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
886 | ||
dbf7bff0 | 887 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 888 | |
b50a5371 | 889 | /* pread for non shmem backed objects */ |
1dd5b6f2 CW |
890 | if (ret == -EFAULT || ret == -ENODEV) { |
891 | intel_runtime_pm_get(to_i915(dev)); | |
b50a5371 AS |
892 | ret = i915_gem_gtt_pread(dev, obj, args->size, |
893 | args->offset, args->data_ptr); | |
1dd5b6f2 CW |
894 | intel_runtime_pm_put(to_i915(dev)); |
895 | } | |
b50a5371 | 896 | |
35b62a89 | 897 | out: |
f8c417cd | 898 | i915_gem_object_put(obj); |
1d7cfea1 | 899 | unlock: |
4f27b75d | 900 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 901 | return ret; |
673a394b EA |
902 | } |
903 | ||
0839ccb8 KP |
904 | /* This is the fast write path which cannot handle |
905 | * page faults in the source data | |
9b7530cc | 906 | */ |
0839ccb8 KP |
907 | |
908 | static inline int | |
909 | fast_user_write(struct io_mapping *mapping, | |
910 | loff_t page_base, int page_offset, | |
911 | char __user *user_data, | |
912 | int length) | |
9b7530cc | 913 | { |
4f0c7cfb BW |
914 | void __iomem *vaddr_atomic; |
915 | void *vaddr; | |
0839ccb8 | 916 | unsigned long unwritten; |
9b7530cc | 917 | |
3e4d3af5 | 918 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
919 | /* We can use the cpu mem copy function because this is X86. */ |
920 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
921 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 922 | user_data, length); |
3e4d3af5 | 923 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 924 | return unwritten; |
0839ccb8 KP |
925 | } |
926 | ||
3de09aa3 EA |
927 | /** |
928 | * This is the fast pwrite path, where we copy the data directly from the | |
929 | * user into the GTT, uncached. | |
62f90b38 | 930 | * @i915: i915 device private data |
14bb2c11 TU |
931 | * @obj: i915 gem object |
932 | * @args: pwrite arguments structure | |
933 | * @file: drm file pointer | |
3de09aa3 | 934 | */ |
673a394b | 935 | static int |
4f1959ee | 936 | i915_gem_gtt_pwrite_fast(struct drm_i915_private *i915, |
05394f39 | 937 | struct drm_i915_gem_object *obj, |
3de09aa3 | 938 | struct drm_i915_gem_pwrite *args, |
05394f39 | 939 | struct drm_file *file) |
673a394b | 940 | { |
4f1959ee | 941 | struct i915_ggtt *ggtt = &i915->ggtt; |
b50a5371 | 942 | struct drm_device *dev = obj->base.dev; |
4f1959ee AS |
943 | struct drm_mm_node node; |
944 | uint64_t remain, offset; | |
673a394b | 945 | char __user *user_data; |
4f1959ee | 946 | int ret; |
b50a5371 AS |
947 | bool hit_slow_path = false; |
948 | ||
949 | if (obj->tiling_mode != I915_TILING_NONE) | |
950 | return -EFAULT; | |
935aaa69 | 951 | |
1ec9e26d | 952 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); |
4f1959ee AS |
953 | if (ret) { |
954 | ret = insert_mappable_node(i915, &node, PAGE_SIZE); | |
955 | if (ret) | |
956 | goto out; | |
957 | ||
958 | ret = i915_gem_object_get_pages(obj); | |
959 | if (ret) { | |
960 | remove_mappable_node(&node); | |
961 | goto out; | |
962 | } | |
963 | ||
964 | i915_gem_object_pin_pages(obj); | |
965 | } else { | |
966 | node.start = i915_gem_obj_ggtt_offset(obj); | |
967 | node.allocated = false; | |
b50a5371 AS |
968 | ret = i915_gem_object_put_fence(obj); |
969 | if (ret) | |
970 | goto out_unpin; | |
4f1959ee | 971 | } |
935aaa69 DV |
972 | |
973 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
974 | if (ret) | |
975 | goto out_unpin; | |
976 | ||
77a0d1ca | 977 | intel_fb_obj_invalidate(obj, ORIGIN_GTT); |
4f1959ee | 978 | obj->dirty = true; |
063e4e6b | 979 | |
4f1959ee AS |
980 | user_data = u64_to_user_ptr(args->data_ptr); |
981 | offset = args->offset; | |
982 | remain = args->size; | |
983 | while (remain) { | |
673a394b EA |
984 | /* Operation in this page |
985 | * | |
0839ccb8 KP |
986 | * page_base = page offset within aperture |
987 | * page_offset = offset within page | |
988 | * page_length = bytes to copy for this page | |
673a394b | 989 | */ |
4f1959ee AS |
990 | u32 page_base = node.start; |
991 | unsigned page_offset = offset_in_page(offset); | |
992 | unsigned page_length = PAGE_SIZE - page_offset; | |
993 | page_length = remain < page_length ? remain : page_length; | |
994 | if (node.allocated) { | |
995 | wmb(); /* flush the write before we modify the GGTT */ | |
996 | ggtt->base.insert_page(&ggtt->base, | |
997 | i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT), | |
998 | node.start, I915_CACHE_NONE, 0); | |
999 | wmb(); /* flush modifications to the GGTT (insert_page) */ | |
1000 | } else { | |
1001 | page_base += offset & PAGE_MASK; | |
1002 | } | |
0839ccb8 | 1003 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
1004 | * source page isn't available. Return the error and we'll |
1005 | * retry in the slow path. | |
b50a5371 AS |
1006 | * If the object is non-shmem backed, we retry again with the |
1007 | * path that handles page fault. | |
0839ccb8 | 1008 | */ |
72e96d64 | 1009 | if (fast_user_write(ggtt->mappable, page_base, |
935aaa69 | 1010 | page_offset, user_data, page_length)) { |
b50a5371 AS |
1011 | hit_slow_path = true; |
1012 | mutex_unlock(&dev->struct_mutex); | |
1013 | if (slow_user_access(ggtt->mappable, | |
1014 | page_base, | |
1015 | page_offset, user_data, | |
1016 | page_length, true)) { | |
1017 | ret = -EFAULT; | |
1018 | mutex_lock(&dev->struct_mutex); | |
1019 | goto out_flush; | |
1020 | } | |
1021 | ||
1022 | mutex_lock(&dev->struct_mutex); | |
935aaa69 | 1023 | } |
673a394b | 1024 | |
0839ccb8 KP |
1025 | remain -= page_length; |
1026 | user_data += page_length; | |
1027 | offset += page_length; | |
673a394b | 1028 | } |
673a394b | 1029 | |
063e4e6b | 1030 | out_flush: |
b50a5371 AS |
1031 | if (hit_slow_path) { |
1032 | if (ret == 0 && | |
1033 | (obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) { | |
1034 | /* The user has modified the object whilst we tried | |
1035 | * reading from it, and we now have no idea what domain | |
1036 | * the pages should be in. As we have just been touching | |
1037 | * them directly, flush everything back to the GTT | |
1038 | * domain. | |
1039 | */ | |
1040 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
1041 | } | |
1042 | } | |
1043 | ||
de152b62 | 1044 | intel_fb_obj_flush(obj, false, ORIGIN_GTT); |
935aaa69 | 1045 | out_unpin: |
4f1959ee AS |
1046 | if (node.allocated) { |
1047 | wmb(); | |
1048 | ggtt->base.clear_range(&ggtt->base, | |
1049 | node.start, node.size, | |
1050 | true); | |
1051 | i915_gem_object_unpin_pages(obj); | |
1052 | remove_mappable_node(&node); | |
1053 | } else { | |
1054 | i915_gem_object_ggtt_unpin(obj); | |
1055 | } | |
935aaa69 | 1056 | out: |
3de09aa3 | 1057 | return ret; |
673a394b EA |
1058 | } |
1059 | ||
d174bd64 DV |
1060 | /* Per-page copy function for the shmem pwrite fastpath. |
1061 | * Flushes invalid cachelines before writing to the target if | |
1062 | * needs_clflush_before is set and flushes out any written cachelines after | |
1063 | * writing if needs_clflush is set. */ | |
3043c60c | 1064 | static int |
d174bd64 DV |
1065 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
1066 | char __user *user_data, | |
1067 | bool page_do_bit17_swizzling, | |
1068 | bool needs_clflush_before, | |
1069 | bool needs_clflush_after) | |
673a394b | 1070 | { |
d174bd64 | 1071 | char *vaddr; |
673a394b | 1072 | int ret; |
3de09aa3 | 1073 | |
e7e58eb5 | 1074 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 1075 | return -EINVAL; |
3de09aa3 | 1076 | |
d174bd64 DV |
1077 | vaddr = kmap_atomic(page); |
1078 | if (needs_clflush_before) | |
1079 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
1080 | page_length); | |
c2831a94 CW |
1081 | ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, |
1082 | user_data, page_length); | |
d174bd64 DV |
1083 | if (needs_clflush_after) |
1084 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
1085 | page_length); | |
1086 | kunmap_atomic(vaddr); | |
3de09aa3 | 1087 | |
755d2218 | 1088 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
1089 | } |
1090 | ||
d174bd64 DV |
1091 | /* Only difference to the fast-path function is that this can handle bit17 |
1092 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 1093 | static int |
d174bd64 DV |
1094 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
1095 | char __user *user_data, | |
1096 | bool page_do_bit17_swizzling, | |
1097 | bool needs_clflush_before, | |
1098 | bool needs_clflush_after) | |
673a394b | 1099 | { |
d174bd64 DV |
1100 | char *vaddr; |
1101 | int ret; | |
e5281ccd | 1102 | |
d174bd64 | 1103 | vaddr = kmap(page); |
e7e58eb5 | 1104 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
1105 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
1106 | page_length, | |
1107 | page_do_bit17_swizzling); | |
d174bd64 DV |
1108 | if (page_do_bit17_swizzling) |
1109 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
1110 | user_data, |
1111 | page_length); | |
d174bd64 DV |
1112 | else |
1113 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
1114 | user_data, | |
1115 | page_length); | |
1116 | if (needs_clflush_after) | |
23c18c71 DV |
1117 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
1118 | page_length, | |
1119 | page_do_bit17_swizzling); | |
d174bd64 | 1120 | kunmap(page); |
40123c1f | 1121 | |
755d2218 | 1122 | return ret ? -EFAULT : 0; |
40123c1f EA |
1123 | } |
1124 | ||
40123c1f | 1125 | static int |
e244a443 DV |
1126 | i915_gem_shmem_pwrite(struct drm_device *dev, |
1127 | struct drm_i915_gem_object *obj, | |
1128 | struct drm_i915_gem_pwrite *args, | |
1129 | struct drm_file *file) | |
40123c1f | 1130 | { |
40123c1f | 1131 | ssize_t remain; |
8c59967c DV |
1132 | loff_t offset; |
1133 | char __user *user_data; | |
eb2c0c81 | 1134 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 1135 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 1136 | int hit_slowpath = 0; |
58642885 DV |
1137 | int needs_clflush_after = 0; |
1138 | int needs_clflush_before = 0; | |
67d5a50c | 1139 | struct sg_page_iter sg_iter; |
40123c1f | 1140 | |
3ed605bc | 1141 | user_data = u64_to_user_ptr(args->data_ptr); |
40123c1f EA |
1142 | remain = args->size; |
1143 | ||
8c59967c | 1144 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 1145 | |
c13d87ea CW |
1146 | ret = i915_gem_object_wait_rendering(obj, false); |
1147 | if (ret) | |
1148 | return ret; | |
1149 | ||
58642885 DV |
1150 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
1151 | /* If we're not in the cpu write domain, set ourself into the gtt | |
1152 | * write domain and manually flush cachelines (if required). This | |
1153 | * optimizes for the case when the gpu will use the data | |
1154 | * right away and we therefore have to clflush anyway. */ | |
2c22569b | 1155 | needs_clflush_after = cpu_write_needs_clflush(obj); |
58642885 | 1156 | } |
c76ce038 CW |
1157 | /* Same trick applies to invalidate partially written cachelines read |
1158 | * before writing. */ | |
1159 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
1160 | needs_clflush_before = | |
1161 | !cpu_cache_is_coherent(dev, obj->cache_level); | |
58642885 | 1162 | |
755d2218 CW |
1163 | ret = i915_gem_object_get_pages(obj); |
1164 | if (ret) | |
1165 | return ret; | |
1166 | ||
77a0d1ca | 1167 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
063e4e6b | 1168 | |
755d2218 CW |
1169 | i915_gem_object_pin_pages(obj); |
1170 | ||
673a394b | 1171 | offset = args->offset; |
05394f39 | 1172 | obj->dirty = 1; |
673a394b | 1173 | |
67d5a50c ID |
1174 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
1175 | offset >> PAGE_SHIFT) { | |
2db76d7c | 1176 | struct page *page = sg_page_iter_page(&sg_iter); |
58642885 | 1177 | int partial_cacheline_write; |
e5281ccd | 1178 | |
9da3da66 CW |
1179 | if (remain <= 0) |
1180 | break; | |
1181 | ||
40123c1f EA |
1182 | /* Operation in this page |
1183 | * | |
40123c1f | 1184 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
1185 | * page_length = bytes to copy for this page |
1186 | */ | |
c8cbbb8b | 1187 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
1188 | |
1189 | page_length = remain; | |
1190 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
1191 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 1192 | |
58642885 DV |
1193 | /* If we don't overwrite a cacheline completely we need to be |
1194 | * careful to have up-to-date data by first clflushing. Don't | |
1195 | * overcomplicate things and flush the entire patch. */ | |
1196 | partial_cacheline_write = needs_clflush_before && | |
1197 | ((shmem_page_offset | page_length) | |
1198 | & (boot_cpu_data.x86_clflush_size - 1)); | |
1199 | ||
8c59967c DV |
1200 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
1201 | (page_to_phys(page) & (1 << 17)) != 0; | |
1202 | ||
d174bd64 DV |
1203 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
1204 | user_data, page_do_bit17_swizzling, | |
1205 | partial_cacheline_write, | |
1206 | needs_clflush_after); | |
1207 | if (ret == 0) | |
1208 | goto next_page; | |
e244a443 DV |
1209 | |
1210 | hit_slowpath = 1; | |
e244a443 | 1211 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
1212 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
1213 | user_data, page_do_bit17_swizzling, | |
1214 | partial_cacheline_write, | |
1215 | needs_clflush_after); | |
40123c1f | 1216 | |
e244a443 | 1217 | mutex_lock(&dev->struct_mutex); |
755d2218 | 1218 | |
755d2218 | 1219 | if (ret) |
8c59967c | 1220 | goto out; |
8c59967c | 1221 | |
17793c9a | 1222 | next_page: |
40123c1f | 1223 | remain -= page_length; |
8c59967c | 1224 | user_data += page_length; |
40123c1f | 1225 | offset += page_length; |
673a394b EA |
1226 | } |
1227 | ||
fbd5a26d | 1228 | out: |
755d2218 CW |
1229 | i915_gem_object_unpin_pages(obj); |
1230 | ||
e244a443 | 1231 | if (hit_slowpath) { |
8dcf015e DV |
1232 | /* |
1233 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
1234 | * cachelines in-line while writing and the object moved | |
1235 | * out of the cpu write domain while we've dropped the lock. | |
1236 | */ | |
1237 | if (!needs_clflush_after && | |
1238 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
000433b6 | 1239 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
ed75a55b | 1240 | needs_clflush_after = true; |
e244a443 | 1241 | } |
8c59967c | 1242 | } |
673a394b | 1243 | |
58642885 | 1244 | if (needs_clflush_after) |
c033666a | 1245 | i915_gem_chipset_flush(to_i915(dev)); |
ed75a55b VS |
1246 | else |
1247 | obj->cache_dirty = true; | |
58642885 | 1248 | |
de152b62 | 1249 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
40123c1f | 1250 | return ret; |
673a394b EA |
1251 | } |
1252 | ||
1253 | /** | |
1254 | * Writes data to the object referenced by handle. | |
14bb2c11 TU |
1255 | * @dev: drm device |
1256 | * @data: ioctl data blob | |
1257 | * @file: drm file | |
673a394b EA |
1258 | * |
1259 | * On error, the contents of the buffer that were to be modified are undefined. | |
1260 | */ | |
1261 | int | |
1262 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1263 | struct drm_file *file) |
673a394b | 1264 | { |
fac5e23e | 1265 | struct drm_i915_private *dev_priv = to_i915(dev); |
673a394b | 1266 | struct drm_i915_gem_pwrite *args = data; |
05394f39 | 1267 | struct drm_i915_gem_object *obj; |
51311d0a CW |
1268 | int ret; |
1269 | ||
1270 | if (args->size == 0) | |
1271 | return 0; | |
1272 | ||
1273 | if (!access_ok(VERIFY_READ, | |
3ed605bc | 1274 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
1275 | args->size)) |
1276 | return -EFAULT; | |
1277 | ||
d330a953 | 1278 | if (likely(!i915.prefault_disable)) { |
3ed605bc | 1279 | ret = fault_in_multipages_readable(u64_to_user_ptr(args->data_ptr), |
0b74b508 XZ |
1280 | args->size); |
1281 | if (ret) | |
1282 | return -EFAULT; | |
1283 | } | |
673a394b | 1284 | |
5d77d9c5 ID |
1285 | intel_runtime_pm_get(dev_priv); |
1286 | ||
fbd5a26d | 1287 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1288 | if (ret) |
5d77d9c5 | 1289 | goto put_rpm; |
1d7cfea1 | 1290 | |
03ac0642 CW |
1291 | obj = i915_gem_object_lookup(file, args->handle); |
1292 | if (!obj) { | |
1d7cfea1 CW |
1293 | ret = -ENOENT; |
1294 | goto unlock; | |
fbd5a26d | 1295 | } |
673a394b | 1296 | |
7dcd2499 | 1297 | /* Bounds check destination. */ |
05394f39 CW |
1298 | if (args->offset > obj->base.size || |
1299 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 1300 | ret = -EINVAL; |
35b62a89 | 1301 | goto out; |
ce9d419d CW |
1302 | } |
1303 | ||
db53a302 CW |
1304 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
1305 | ||
935aaa69 | 1306 | ret = -EFAULT; |
673a394b EA |
1307 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1308 | * it would end up going through the fenced access, and we'll get | |
1309 | * different detiling behavior between reading and writing. | |
1310 | * pread/pwrite currently are reading and writing from the CPU | |
1311 | * perspective, requiring manual detiling by the client. | |
1312 | */ | |
6eae0059 CW |
1313 | if (!i915_gem_object_has_struct_page(obj) || |
1314 | cpu_write_needs_clflush(obj)) { | |
4f1959ee | 1315 | ret = i915_gem_gtt_pwrite_fast(dev_priv, obj, args, file); |
935aaa69 DV |
1316 | /* Note that the gtt paths might fail with non-page-backed user |
1317 | * pointers (e.g. gtt mappings when moving data between | |
1318 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 1319 | } |
673a394b | 1320 | |
d1054ee4 | 1321 | if (ret == -EFAULT || ret == -ENOSPC) { |
6a2c4232 CW |
1322 | if (obj->phys_handle) |
1323 | ret = i915_gem_phys_pwrite(obj, args, file); | |
6eae0059 | 1324 | else if (i915_gem_object_has_struct_page(obj)) |
6a2c4232 | 1325 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
b50a5371 AS |
1326 | else |
1327 | ret = -ENODEV; | |
6a2c4232 | 1328 | } |
5c0480f2 | 1329 | |
35b62a89 | 1330 | out: |
f8c417cd | 1331 | i915_gem_object_put(obj); |
1d7cfea1 | 1332 | unlock: |
fbd5a26d | 1333 | mutex_unlock(&dev->struct_mutex); |
5d77d9c5 ID |
1334 | put_rpm: |
1335 | intel_runtime_pm_put(dev_priv); | |
1336 | ||
673a394b EA |
1337 | return ret; |
1338 | } | |
1339 | ||
b361237b CW |
1340 | /** |
1341 | * Ensures that all rendering to the object has completed and the object is | |
1342 | * safe to unbind from the GTT or access from the CPU. | |
14bb2c11 TU |
1343 | * @obj: i915 gem object |
1344 | * @readonly: waiting for read access or write | |
b361237b | 1345 | */ |
2e2f351d | 1346 | int |
b361237b CW |
1347 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
1348 | bool readonly) | |
1349 | { | |
c13d87ea | 1350 | struct reservation_object *resv; |
8cac6f6c CW |
1351 | struct i915_gem_active *active; |
1352 | unsigned long active_mask; | |
1353 | int idx, ret; | |
b361237b | 1354 | |
8cac6f6c CW |
1355 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
1356 | ||
1357 | if (!readonly) { | |
1358 | active = obj->last_read; | |
1359 | active_mask = obj->active; | |
b4716185 | 1360 | } else { |
8cac6f6c CW |
1361 | active_mask = 1; |
1362 | active = &obj->last_write; | |
1363 | } | |
b4716185 | 1364 | |
8cac6f6c | 1365 | for_each_active(active_mask, idx) { |
fa545cbf CW |
1366 | ret = i915_gem_active_wait(&active[idx], |
1367 | &obj->base.dev->struct_mutex); | |
8cac6f6c CW |
1368 | if (ret) |
1369 | return ret; | |
b4716185 CW |
1370 | } |
1371 | ||
c13d87ea CW |
1372 | resv = i915_gem_object_get_dmabuf_resv(obj); |
1373 | if (resv) { | |
1374 | long err; | |
1375 | ||
1376 | err = reservation_object_wait_timeout_rcu(resv, !readonly, true, | |
1377 | MAX_SCHEDULE_TIMEOUT); | |
1378 | if (err < 0) | |
1379 | return err; | |
1380 | } | |
1381 | ||
b4716185 CW |
1382 | return 0; |
1383 | } | |
1384 | ||
3236f57a CW |
1385 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1386 | * as the object state may change during this call. | |
1387 | */ | |
1388 | static __must_check int | |
1389 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
2e1b8730 | 1390 | struct intel_rps_client *rps, |
3236f57a CW |
1391 | bool readonly) |
1392 | { | |
1393 | struct drm_device *dev = obj->base.dev; | |
fac5e23e | 1394 | struct drm_i915_private *dev_priv = to_i915(dev); |
666796da | 1395 | struct drm_i915_gem_request *requests[I915_NUM_ENGINES]; |
8cac6f6c CW |
1396 | struct i915_gem_active *active; |
1397 | unsigned long active_mask; | |
b4716185 | 1398 | int ret, i, n = 0; |
3236f57a CW |
1399 | |
1400 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1401 | BUG_ON(!dev_priv->mm.interruptible); | |
1402 | ||
8cac6f6c CW |
1403 | active_mask = obj->active; |
1404 | if (!active_mask) | |
3236f57a CW |
1405 | return 0; |
1406 | ||
8cac6f6c CW |
1407 | if (!readonly) { |
1408 | active = obj->last_read; | |
b4716185 | 1409 | } else { |
8cac6f6c CW |
1410 | active_mask = 1; |
1411 | active = &obj->last_write; | |
1412 | } | |
b4716185 | 1413 | |
8cac6f6c CW |
1414 | for_each_active(active_mask, i) { |
1415 | struct drm_i915_gem_request *req; | |
b4716185 | 1416 | |
8cac6f6c CW |
1417 | req = i915_gem_active_get(&active[i], |
1418 | &obj->base.dev->struct_mutex); | |
1419 | if (req) | |
27c01aae | 1420 | requests[n++] = req; |
b4716185 CW |
1421 | } |
1422 | ||
3236f57a | 1423 | mutex_unlock(&dev->struct_mutex); |
299259a3 | 1424 | ret = 0; |
b4716185 | 1425 | for (i = 0; ret == 0 && i < n; i++) |
776f3236 | 1426 | ret = i915_wait_request(requests[i], true, NULL, rps); |
3236f57a CW |
1427 | mutex_lock(&dev->struct_mutex); |
1428 | ||
fa545cbf | 1429 | for (i = 0; i < n; i++) |
e8a261ea | 1430 | i915_gem_request_put(requests[i]); |
b4716185 CW |
1431 | |
1432 | return ret; | |
3236f57a CW |
1433 | } |
1434 | ||
2e1b8730 CW |
1435 | static struct intel_rps_client *to_rps_client(struct drm_file *file) |
1436 | { | |
1437 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
1438 | return &fpriv->rps; | |
1439 | } | |
1440 | ||
aeecc969 CW |
1441 | static enum fb_op_origin |
1442 | write_origin(struct drm_i915_gem_object *obj, unsigned domain) | |
1443 | { | |
1444 | return domain == I915_GEM_DOMAIN_GTT && !obj->has_wc_mmap ? | |
1445 | ORIGIN_GTT : ORIGIN_CPU; | |
1446 | } | |
1447 | ||
673a394b | 1448 | /** |
2ef7eeaa EA |
1449 | * Called when user space prepares to use an object with the CPU, either |
1450 | * through the mmap ioctl's mapping or a GTT mapping. | |
14bb2c11 TU |
1451 | * @dev: drm device |
1452 | * @data: ioctl data blob | |
1453 | * @file: drm file | |
673a394b EA |
1454 | */ |
1455 | int | |
1456 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1457 | struct drm_file *file) |
673a394b EA |
1458 | { |
1459 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1460 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1461 | uint32_t read_domains = args->read_domains; |
1462 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1463 | int ret; |
1464 | ||
2ef7eeaa | 1465 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1466 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1467 | return -EINVAL; |
1468 | ||
21d509e3 | 1469 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1470 | return -EINVAL; |
1471 | ||
1472 | /* Having something in the write domain implies it's in the read | |
1473 | * domain, and only that read domain. Enforce that in the request. | |
1474 | */ | |
1475 | if (write_domain != 0 && read_domains != write_domain) | |
1476 | return -EINVAL; | |
1477 | ||
76c1dec1 | 1478 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1479 | if (ret) |
76c1dec1 | 1480 | return ret; |
1d7cfea1 | 1481 | |
03ac0642 CW |
1482 | obj = i915_gem_object_lookup(file, args->handle); |
1483 | if (!obj) { | |
1d7cfea1 CW |
1484 | ret = -ENOENT; |
1485 | goto unlock; | |
76c1dec1 | 1486 | } |
673a394b | 1487 | |
3236f57a CW |
1488 | /* Try to flush the object off the GPU without holding the lock. |
1489 | * We will repeat the flush holding the lock in the normal manner | |
1490 | * to catch cases where we are gazumped. | |
1491 | */ | |
6e4930f6 | 1492 | ret = i915_gem_object_wait_rendering__nonblocking(obj, |
2e1b8730 | 1493 | to_rps_client(file), |
6e4930f6 | 1494 | !write_domain); |
3236f57a CW |
1495 | if (ret) |
1496 | goto unref; | |
1497 | ||
43566ded | 1498 | if (read_domains & I915_GEM_DOMAIN_GTT) |
2ef7eeaa | 1499 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
43566ded | 1500 | else |
e47c68e9 | 1501 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa | 1502 | |
031b698a | 1503 | if (write_domain != 0) |
aeecc969 | 1504 | intel_fb_obj_invalidate(obj, write_origin(obj, write_domain)); |
031b698a | 1505 | |
3236f57a | 1506 | unref: |
f8c417cd | 1507 | i915_gem_object_put(obj); |
1d7cfea1 | 1508 | unlock: |
673a394b EA |
1509 | mutex_unlock(&dev->struct_mutex); |
1510 | return ret; | |
1511 | } | |
1512 | ||
1513 | /** | |
1514 | * Called when user space has done writes to this buffer | |
14bb2c11 TU |
1515 | * @dev: drm device |
1516 | * @data: ioctl data blob | |
1517 | * @file: drm file | |
673a394b EA |
1518 | */ |
1519 | int | |
1520 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1521 | struct drm_file *file) |
673a394b EA |
1522 | { |
1523 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1524 | struct drm_i915_gem_object *obj; |
673a394b EA |
1525 | int ret = 0; |
1526 | ||
76c1dec1 | 1527 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1528 | if (ret) |
76c1dec1 | 1529 | return ret; |
1d7cfea1 | 1530 | |
03ac0642 CW |
1531 | obj = i915_gem_object_lookup(file, args->handle); |
1532 | if (!obj) { | |
1d7cfea1 CW |
1533 | ret = -ENOENT; |
1534 | goto unlock; | |
673a394b EA |
1535 | } |
1536 | ||
673a394b | 1537 | /* Pinned buffers may be scanout, so flush the cache */ |
2c22569b | 1538 | if (obj->pin_display) |
e62b59e4 | 1539 | i915_gem_object_flush_cpu_write_domain(obj); |
e47c68e9 | 1540 | |
f8c417cd | 1541 | i915_gem_object_put(obj); |
1d7cfea1 | 1542 | unlock: |
673a394b EA |
1543 | mutex_unlock(&dev->struct_mutex); |
1544 | return ret; | |
1545 | } | |
1546 | ||
1547 | /** | |
14bb2c11 TU |
1548 | * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address |
1549 | * it is mapped to. | |
1550 | * @dev: drm device | |
1551 | * @data: ioctl data blob | |
1552 | * @file: drm file | |
673a394b EA |
1553 | * |
1554 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1555 | * imply a ref on the object itself. | |
34367381 DV |
1556 | * |
1557 | * IMPORTANT: | |
1558 | * | |
1559 | * DRM driver writers who look a this function as an example for how to do GEM | |
1560 | * mmap support, please don't implement mmap support like here. The modern way | |
1561 | * to implement DRM mmap support is with an mmap offset ioctl (like | |
1562 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. | |
1563 | * That way debug tooling like valgrind will understand what's going on, hiding | |
1564 | * the mmap call in a driver private ioctl will break that. The i915 driver only | |
1565 | * does cpu mmaps this way because we didn't know better. | |
673a394b EA |
1566 | */ |
1567 | int | |
1568 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1569 | struct drm_file *file) |
673a394b EA |
1570 | { |
1571 | struct drm_i915_gem_mmap *args = data; | |
03ac0642 | 1572 | struct drm_i915_gem_object *obj; |
673a394b EA |
1573 | unsigned long addr; |
1574 | ||
1816f923 AG |
1575 | if (args->flags & ~(I915_MMAP_WC)) |
1576 | return -EINVAL; | |
1577 | ||
568a58e5 | 1578 | if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT)) |
1816f923 AG |
1579 | return -ENODEV; |
1580 | ||
03ac0642 CW |
1581 | obj = i915_gem_object_lookup(file, args->handle); |
1582 | if (!obj) | |
bf79cb91 | 1583 | return -ENOENT; |
673a394b | 1584 | |
1286ff73 DV |
1585 | /* prime objects have no backing filp to GEM mmap |
1586 | * pages from. | |
1587 | */ | |
03ac0642 | 1588 | if (!obj->base.filp) { |
34911fd3 | 1589 | i915_gem_object_put_unlocked(obj); |
1286ff73 DV |
1590 | return -EINVAL; |
1591 | } | |
1592 | ||
03ac0642 | 1593 | addr = vm_mmap(obj->base.filp, 0, args->size, |
673a394b EA |
1594 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1595 | args->offset); | |
1816f923 AG |
1596 | if (args->flags & I915_MMAP_WC) { |
1597 | struct mm_struct *mm = current->mm; | |
1598 | struct vm_area_struct *vma; | |
1599 | ||
80a89a5e | 1600 | if (down_write_killable(&mm->mmap_sem)) { |
34911fd3 | 1601 | i915_gem_object_put_unlocked(obj); |
80a89a5e MH |
1602 | return -EINTR; |
1603 | } | |
1816f923 AG |
1604 | vma = find_vma(mm, addr); |
1605 | if (vma) | |
1606 | vma->vm_page_prot = | |
1607 | pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); | |
1608 | else | |
1609 | addr = -ENOMEM; | |
1610 | up_write(&mm->mmap_sem); | |
aeecc969 CW |
1611 | |
1612 | /* This may race, but that's ok, it only gets set */ | |
03ac0642 | 1613 | WRITE_ONCE(obj->has_wc_mmap, true); |
1816f923 | 1614 | } |
34911fd3 | 1615 | i915_gem_object_put_unlocked(obj); |
673a394b EA |
1616 | if (IS_ERR((void *)addr)) |
1617 | return addr; | |
1618 | ||
1619 | args->addr_ptr = (uint64_t) addr; | |
1620 | ||
1621 | return 0; | |
1622 | } | |
1623 | ||
de151cf6 JB |
1624 | /** |
1625 | * i915_gem_fault - fault a page into the GTT | |
d9072a3e GT |
1626 | * @vma: VMA in question |
1627 | * @vmf: fault info | |
de151cf6 JB |
1628 | * |
1629 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1630 | * from userspace. The fault handler takes care of binding the object to | |
1631 | * the GTT (if needed), allocating and programming a fence register (again, | |
1632 | * only if needed based on whether the old reg is still valid or the object | |
1633 | * is tiled) and inserting a new PTE into the faulting process. | |
1634 | * | |
1635 | * Note that the faulting process may involve evicting existing objects | |
1636 | * from the GTT and/or fence registers to make room. So performance may | |
1637 | * suffer if the GTT working set is large or there are few fence registers | |
1638 | * left. | |
1639 | */ | |
1640 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1641 | { | |
05394f39 CW |
1642 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1643 | struct drm_device *dev = obj->base.dev; | |
72e96d64 JL |
1644 | struct drm_i915_private *dev_priv = to_i915(dev); |
1645 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
c5ad54cf | 1646 | struct i915_ggtt_view view = i915_ggtt_view_normal; |
de151cf6 JB |
1647 | pgoff_t page_offset; |
1648 | unsigned long pfn; | |
1649 | int ret = 0; | |
0f973f27 | 1650 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 | 1651 | |
f65c9168 PZ |
1652 | intel_runtime_pm_get(dev_priv); |
1653 | ||
de151cf6 JB |
1654 | /* We don't use vmf->pgoff since that has the fake offset */ |
1655 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1656 | PAGE_SHIFT; | |
1657 | ||
d9bc7e9f CW |
1658 | ret = i915_mutex_lock_interruptible(dev); |
1659 | if (ret) | |
1660 | goto out; | |
a00b10c3 | 1661 | |
db53a302 CW |
1662 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1663 | ||
6e4930f6 CW |
1664 | /* Try to flush the object off the GPU first without holding the lock. |
1665 | * Upon reacquiring the lock, we will perform our sanity checks and then | |
1666 | * repeat the flush holding the lock in the normal manner to catch cases | |
1667 | * where we are gazumped. | |
1668 | */ | |
1669 | ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write); | |
1670 | if (ret) | |
1671 | goto unlock; | |
1672 | ||
eb119bd6 CW |
1673 | /* Access to snoopable pages through the GTT is incoherent. */ |
1674 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
ddeff6ee | 1675 | ret = -EFAULT; |
eb119bd6 CW |
1676 | goto unlock; |
1677 | } | |
1678 | ||
c5ad54cf | 1679 | /* Use a partial view if the object is bigger than the aperture. */ |
72e96d64 | 1680 | if (obj->base.size >= ggtt->mappable_end && |
e7ded2d7 | 1681 | obj->tiling_mode == I915_TILING_NONE) { |
c5ad54cf | 1682 | static const unsigned int chunk_size = 256; // 1 MiB |
e7ded2d7 | 1683 | |
c5ad54cf JL |
1684 | memset(&view, 0, sizeof(view)); |
1685 | view.type = I915_GGTT_VIEW_PARTIAL; | |
1686 | view.params.partial.offset = rounddown(page_offset, chunk_size); | |
1687 | view.params.partial.size = | |
1688 | min_t(unsigned int, | |
1689 | chunk_size, | |
1690 | (vma->vm_end - vma->vm_start)/PAGE_SIZE - | |
1691 | view.params.partial.offset); | |
1692 | } | |
1693 | ||
1694 | /* Now pin it into the GTT if needed */ | |
91b2db6f | 1695 | ret = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE); |
c9839303 CW |
1696 | if (ret) |
1697 | goto unlock; | |
4a684a41 | 1698 | |
c9839303 CW |
1699 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1700 | if (ret) | |
1701 | goto unpin; | |
74898d7e | 1702 | |
06d98131 | 1703 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1704 | if (ret) |
c9839303 | 1705 | goto unpin; |
7d1c4804 | 1706 | |
b90b91d8 | 1707 | /* Finally, remap it using the new GTT offset */ |
72e96d64 | 1708 | pfn = ggtt->mappable_base + |
c5ad54cf | 1709 | i915_gem_obj_ggtt_offset_view(obj, &view); |
f343c5f6 | 1710 | pfn >>= PAGE_SHIFT; |
de151cf6 | 1711 | |
c5ad54cf JL |
1712 | if (unlikely(view.type == I915_GGTT_VIEW_PARTIAL)) { |
1713 | /* Overriding existing pages in partial view does not cause | |
1714 | * us any trouble as TLBs are still valid because the fault | |
1715 | * is due to userspace losing part of the mapping or never | |
1716 | * having accessed it before (at this partials' range). | |
1717 | */ | |
1718 | unsigned long base = vma->vm_start + | |
1719 | (view.params.partial.offset << PAGE_SHIFT); | |
1720 | unsigned int i; | |
b90b91d8 | 1721 | |
c5ad54cf JL |
1722 | for (i = 0; i < view.params.partial.size; i++) { |
1723 | ret = vm_insert_pfn(vma, base + i * PAGE_SIZE, pfn + i); | |
b90b91d8 CW |
1724 | if (ret) |
1725 | break; | |
1726 | } | |
1727 | ||
1728 | obj->fault_mappable = true; | |
c5ad54cf JL |
1729 | } else { |
1730 | if (!obj->fault_mappable) { | |
1731 | unsigned long size = min_t(unsigned long, | |
1732 | vma->vm_end - vma->vm_start, | |
1733 | obj->base.size); | |
1734 | int i; | |
1735 | ||
1736 | for (i = 0; i < size >> PAGE_SHIFT; i++) { | |
1737 | ret = vm_insert_pfn(vma, | |
1738 | (unsigned long)vma->vm_start + i * PAGE_SIZE, | |
1739 | pfn + i); | |
1740 | if (ret) | |
1741 | break; | |
1742 | } | |
1743 | ||
1744 | obj->fault_mappable = true; | |
1745 | } else | |
1746 | ret = vm_insert_pfn(vma, | |
1747 | (unsigned long)vmf->virtual_address, | |
1748 | pfn + page_offset); | |
1749 | } | |
c9839303 | 1750 | unpin: |
c5ad54cf | 1751 | i915_gem_object_ggtt_unpin_view(obj, &view); |
c715089f | 1752 | unlock: |
de151cf6 | 1753 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1754 | out: |
de151cf6 | 1755 | switch (ret) { |
d9bc7e9f | 1756 | case -EIO: |
2232f031 DV |
1757 | /* |
1758 | * We eat errors when the gpu is terminally wedged to avoid | |
1759 | * userspace unduly crashing (gl has no provisions for mmaps to | |
1760 | * fail). But any other -EIO isn't ours (e.g. swap in failure) | |
1761 | * and so needs to be reported. | |
1762 | */ | |
1763 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { | |
f65c9168 PZ |
1764 | ret = VM_FAULT_SIGBUS; |
1765 | break; | |
1766 | } | |
045e769a | 1767 | case -EAGAIN: |
571c608d DV |
1768 | /* |
1769 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1770 | * handler to reset everything when re-faulting in | |
1771 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1772 | */ |
c715089f CW |
1773 | case 0: |
1774 | case -ERESTARTSYS: | |
bed636ab | 1775 | case -EINTR: |
e79e0fe3 DR |
1776 | case -EBUSY: |
1777 | /* | |
1778 | * EBUSY is ok: this just means that another thread | |
1779 | * already did the job. | |
1780 | */ | |
f65c9168 PZ |
1781 | ret = VM_FAULT_NOPAGE; |
1782 | break; | |
de151cf6 | 1783 | case -ENOMEM: |
f65c9168 PZ |
1784 | ret = VM_FAULT_OOM; |
1785 | break; | |
a7c2e1aa | 1786 | case -ENOSPC: |
45d67817 | 1787 | case -EFAULT: |
f65c9168 PZ |
1788 | ret = VM_FAULT_SIGBUS; |
1789 | break; | |
de151cf6 | 1790 | default: |
a7c2e1aa | 1791 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
1792 | ret = VM_FAULT_SIGBUS; |
1793 | break; | |
de151cf6 | 1794 | } |
f65c9168 PZ |
1795 | |
1796 | intel_runtime_pm_put(dev_priv); | |
1797 | return ret; | |
de151cf6 JB |
1798 | } |
1799 | ||
901782b2 CW |
1800 | /** |
1801 | * i915_gem_release_mmap - remove physical page mappings | |
1802 | * @obj: obj in question | |
1803 | * | |
af901ca1 | 1804 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1805 | * relinquish ownership of the pages back to the system. |
1806 | * | |
1807 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1808 | * object through the GTT and then lose the fence register due to | |
1809 | * resource pressure. Similarly if the object has been moved out of the | |
1810 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1811 | * mapping will then trigger a page fault on the next user access, allowing | |
1812 | * fixup by i915_gem_fault(). | |
1813 | */ | |
d05ca301 | 1814 | void |
05394f39 | 1815 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1816 | { |
349f2ccf CW |
1817 | /* Serialisation between user GTT access and our code depends upon |
1818 | * revoking the CPU's PTE whilst the mutex is held. The next user | |
1819 | * pagefault then has to wait until we release the mutex. | |
1820 | */ | |
1821 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
1822 | ||
6299f992 CW |
1823 | if (!obj->fault_mappable) |
1824 | return; | |
901782b2 | 1825 | |
6796cb16 DH |
1826 | drm_vma_node_unmap(&obj->base.vma_node, |
1827 | obj->base.dev->anon_inode->i_mapping); | |
349f2ccf CW |
1828 | |
1829 | /* Ensure that the CPU's PTE are revoked and there are not outstanding | |
1830 | * memory transactions from userspace before we return. The TLB | |
1831 | * flushing implied above by changing the PTE above *should* be | |
1832 | * sufficient, an extra barrier here just provides us with a bit | |
1833 | * of paranoid documentation about our requirement to serialise | |
1834 | * memory writes before touching registers / GSM. | |
1835 | */ | |
1836 | wmb(); | |
1837 | ||
6299f992 | 1838 | obj->fault_mappable = false; |
901782b2 CW |
1839 | } |
1840 | ||
eedd10f4 CW |
1841 | void |
1842 | i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) | |
1843 | { | |
1844 | struct drm_i915_gem_object *obj; | |
1845 | ||
1846 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) | |
1847 | i915_gem_release_mmap(obj); | |
1848 | } | |
1849 | ||
ad1a7d20 CW |
1850 | /** |
1851 | * i915_gem_get_ggtt_size - return required global GTT size for an object | |
a9f1481f | 1852 | * @dev_priv: i915 device |
ad1a7d20 CW |
1853 | * @size: object size |
1854 | * @tiling_mode: tiling mode | |
1855 | * | |
1856 | * Return the required global GTT size for an object, taking into account | |
1857 | * potential fence register mapping. | |
1858 | */ | |
a9f1481f CW |
1859 | u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, |
1860 | u64 size, int tiling_mode) | |
92b88aeb | 1861 | { |
ad1a7d20 | 1862 | u64 ggtt_size; |
92b88aeb | 1863 | |
ad1a7d20 CW |
1864 | GEM_BUG_ON(size == 0); |
1865 | ||
a9f1481f | 1866 | if (INTEL_GEN(dev_priv) >= 4 || |
e28f8711 CW |
1867 | tiling_mode == I915_TILING_NONE) |
1868 | return size; | |
92b88aeb CW |
1869 | |
1870 | /* Previous chips need a power-of-two fence region when tiling */ | |
a9f1481f | 1871 | if (IS_GEN3(dev_priv)) |
ad1a7d20 | 1872 | ggtt_size = 1024*1024; |
92b88aeb | 1873 | else |
ad1a7d20 | 1874 | ggtt_size = 512*1024; |
92b88aeb | 1875 | |
ad1a7d20 CW |
1876 | while (ggtt_size < size) |
1877 | ggtt_size <<= 1; | |
92b88aeb | 1878 | |
ad1a7d20 | 1879 | return ggtt_size; |
92b88aeb CW |
1880 | } |
1881 | ||
de151cf6 | 1882 | /** |
ad1a7d20 | 1883 | * i915_gem_get_ggtt_alignment - return required global GTT alignment |
a9f1481f | 1884 | * @dev_priv: i915 device |
14bb2c11 TU |
1885 | * @size: object size |
1886 | * @tiling_mode: tiling mode | |
ad1a7d20 | 1887 | * @fenced: is fenced alignment required or not |
de151cf6 | 1888 | * |
ad1a7d20 | 1889 | * Return the required global GTT alignment for an object, taking into account |
5e783301 | 1890 | * potential fence register mapping. |
de151cf6 | 1891 | */ |
a9f1481f | 1892 | u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size, |
ad1a7d20 | 1893 | int tiling_mode, bool fenced) |
de151cf6 | 1894 | { |
ad1a7d20 CW |
1895 | GEM_BUG_ON(size == 0); |
1896 | ||
de151cf6 JB |
1897 | /* |
1898 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1899 | * if a fence register is needed for the object. | |
1900 | */ | |
a9f1481f | 1901 | if (INTEL_GEN(dev_priv) >= 4 || (!fenced && IS_G33(dev_priv)) || |
e28f8711 | 1902 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1903 | return 4096; |
1904 | ||
a00b10c3 CW |
1905 | /* |
1906 | * Previous chips need to be aligned to the size of the smallest | |
1907 | * fence register that can contain the object. | |
1908 | */ | |
a9f1481f | 1909 | return i915_gem_get_ggtt_size(dev_priv, size, tiling_mode); |
a00b10c3 CW |
1910 | } |
1911 | ||
d8cb5086 CW |
1912 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1913 | { | |
fac5e23e | 1914 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
d8cb5086 CW |
1915 | int ret; |
1916 | ||
da494d7c DV |
1917 | dev_priv->mm.shrinker_no_lock_stealing = true; |
1918 | ||
d8cb5086 CW |
1919 | ret = drm_gem_create_mmap_offset(&obj->base); |
1920 | if (ret != -ENOSPC) | |
da494d7c | 1921 | goto out; |
d8cb5086 CW |
1922 | |
1923 | /* Badly fragmented mmap space? The only way we can recover | |
1924 | * space is by destroying unwanted objects. We can't randomly release | |
1925 | * mmap_offsets as userspace expects them to be persistent for the | |
1926 | * lifetime of the objects. The closest we can is to release the | |
1927 | * offsets on purgeable objects by truncating it and marking it purged, | |
1928 | * which prevents userspace from ever using that object again. | |
1929 | */ | |
21ab4e74 CW |
1930 | i915_gem_shrink(dev_priv, |
1931 | obj->base.size >> PAGE_SHIFT, | |
1932 | I915_SHRINK_BOUND | | |
1933 | I915_SHRINK_UNBOUND | | |
1934 | I915_SHRINK_PURGEABLE); | |
d8cb5086 CW |
1935 | ret = drm_gem_create_mmap_offset(&obj->base); |
1936 | if (ret != -ENOSPC) | |
da494d7c | 1937 | goto out; |
d8cb5086 CW |
1938 | |
1939 | i915_gem_shrink_all(dev_priv); | |
da494d7c DV |
1940 | ret = drm_gem_create_mmap_offset(&obj->base); |
1941 | out: | |
1942 | dev_priv->mm.shrinker_no_lock_stealing = false; | |
1943 | ||
1944 | return ret; | |
d8cb5086 CW |
1945 | } |
1946 | ||
1947 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1948 | { | |
d8cb5086 CW |
1949 | drm_gem_free_mmap_offset(&obj->base); |
1950 | } | |
1951 | ||
da6b51d0 | 1952 | int |
ff72145b DA |
1953 | i915_gem_mmap_gtt(struct drm_file *file, |
1954 | struct drm_device *dev, | |
da6b51d0 | 1955 | uint32_t handle, |
ff72145b | 1956 | uint64_t *offset) |
de151cf6 | 1957 | { |
05394f39 | 1958 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1959 | int ret; |
1960 | ||
76c1dec1 | 1961 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1962 | if (ret) |
76c1dec1 | 1963 | return ret; |
de151cf6 | 1964 | |
03ac0642 CW |
1965 | obj = i915_gem_object_lookup(file, handle); |
1966 | if (!obj) { | |
1d7cfea1 CW |
1967 | ret = -ENOENT; |
1968 | goto unlock; | |
1969 | } | |
de151cf6 | 1970 | |
05394f39 | 1971 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 1972 | DRM_DEBUG("Attempting to mmap a purgeable buffer\n"); |
8c99e57d | 1973 | ret = -EFAULT; |
1d7cfea1 | 1974 | goto out; |
ab18282d CW |
1975 | } |
1976 | ||
d8cb5086 CW |
1977 | ret = i915_gem_object_create_mmap_offset(obj); |
1978 | if (ret) | |
1979 | goto out; | |
de151cf6 | 1980 | |
0de23977 | 1981 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
de151cf6 | 1982 | |
1d7cfea1 | 1983 | out: |
f8c417cd | 1984 | i915_gem_object_put(obj); |
1d7cfea1 | 1985 | unlock: |
de151cf6 | 1986 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1987 | return ret; |
de151cf6 JB |
1988 | } |
1989 | ||
ff72145b DA |
1990 | /** |
1991 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1992 | * @dev: DRM device | |
1993 | * @data: GTT mapping ioctl data | |
1994 | * @file: GEM object info | |
1995 | * | |
1996 | * Simply returns the fake offset to userspace so it can mmap it. | |
1997 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1998 | * up so we can get faults in the handler above. | |
1999 | * | |
2000 | * The fault handler will take care of binding the object into the GTT | |
2001 | * (since it may have been evicted to make room for something), allocating | |
2002 | * a fence register, and mapping the appropriate aperture address into | |
2003 | * userspace. | |
2004 | */ | |
2005 | int | |
2006 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
2007 | struct drm_file *file) | |
2008 | { | |
2009 | struct drm_i915_gem_mmap_gtt *args = data; | |
2010 | ||
da6b51d0 | 2011 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
ff72145b DA |
2012 | } |
2013 | ||
225067ee DV |
2014 | /* Immediately discard the backing storage */ |
2015 | static void | |
2016 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 2017 | { |
4d6294bf | 2018 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 2019 | |
4d6294bf CW |
2020 | if (obj->base.filp == NULL) |
2021 | return; | |
e5281ccd | 2022 | |
225067ee DV |
2023 | /* Our goal here is to return as much of the memory as |
2024 | * is possible back to the system as we are called from OOM. | |
2025 | * To do this we must instruct the shmfs to drop all of its | |
2026 | * backing pages, *now*. | |
2027 | */ | |
5537252b | 2028 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
225067ee DV |
2029 | obj->madv = __I915_MADV_PURGED; |
2030 | } | |
e5281ccd | 2031 | |
5537252b CW |
2032 | /* Try to discard unwanted pages */ |
2033 | static void | |
2034 | i915_gem_object_invalidate(struct drm_i915_gem_object *obj) | |
225067ee | 2035 | { |
5537252b CW |
2036 | struct address_space *mapping; |
2037 | ||
2038 | switch (obj->madv) { | |
2039 | case I915_MADV_DONTNEED: | |
2040 | i915_gem_object_truncate(obj); | |
2041 | case __I915_MADV_PURGED: | |
2042 | return; | |
2043 | } | |
2044 | ||
2045 | if (obj->base.filp == NULL) | |
2046 | return; | |
2047 | ||
2048 | mapping = file_inode(obj->base.filp)->i_mapping, | |
2049 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); | |
e5281ccd CW |
2050 | } |
2051 | ||
5cdf5881 | 2052 | static void |
05394f39 | 2053 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 2054 | { |
85d1225e DG |
2055 | struct sgt_iter sgt_iter; |
2056 | struct page *page; | |
90797e6d | 2057 | int ret; |
1286ff73 | 2058 | |
05394f39 | 2059 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 2060 | |
6c085a72 | 2061 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
f4457ae7 | 2062 | if (WARN_ON(ret)) { |
6c085a72 CW |
2063 | /* In the event of a disaster, abandon all caches and |
2064 | * hope for the best. | |
2065 | */ | |
2c22569b | 2066 | i915_gem_clflush_object(obj, true); |
6c085a72 CW |
2067 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
2068 | } | |
2069 | ||
e2273302 ID |
2070 | i915_gem_gtt_finish_object(obj); |
2071 | ||
6dacfd2f | 2072 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
2073 | i915_gem_object_save_bit_17_swizzle(obj); |
2074 | ||
05394f39 CW |
2075 | if (obj->madv == I915_MADV_DONTNEED) |
2076 | obj->dirty = 0; | |
3ef94daa | 2077 | |
85d1225e | 2078 | for_each_sgt_page(page, sgt_iter, obj->pages) { |
05394f39 | 2079 | if (obj->dirty) |
9da3da66 | 2080 | set_page_dirty(page); |
3ef94daa | 2081 | |
05394f39 | 2082 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 2083 | mark_page_accessed(page); |
3ef94daa | 2084 | |
09cbfeaf | 2085 | put_page(page); |
3ef94daa | 2086 | } |
05394f39 | 2087 | obj->dirty = 0; |
673a394b | 2088 | |
9da3da66 CW |
2089 | sg_free_table(obj->pages); |
2090 | kfree(obj->pages); | |
37e680a1 | 2091 | } |
6c085a72 | 2092 | |
dd624afd | 2093 | int |
37e680a1 CW |
2094 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
2095 | { | |
2096 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2097 | ||
2f745ad3 | 2098 | if (obj->pages == NULL) |
37e680a1 CW |
2099 | return 0; |
2100 | ||
a5570178 CW |
2101 | if (obj->pages_pin_count) |
2102 | return -EBUSY; | |
2103 | ||
15717de2 | 2104 | GEM_BUG_ON(obj->bind_count); |
3e123027 | 2105 | |
a2165e31 CW |
2106 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
2107 | * array, hence protect them from being reaped by removing them from gtt | |
2108 | * lists early. */ | |
35c20a60 | 2109 | list_del(&obj->global_list); |
a2165e31 | 2110 | |
0a798eb9 | 2111 | if (obj->mapping) { |
fb8621d3 CW |
2112 | if (is_vmalloc_addr(obj->mapping)) |
2113 | vunmap(obj->mapping); | |
2114 | else | |
2115 | kunmap(kmap_to_page(obj->mapping)); | |
0a798eb9 CW |
2116 | obj->mapping = NULL; |
2117 | } | |
2118 | ||
37e680a1 | 2119 | ops->put_pages(obj); |
05394f39 | 2120 | obj->pages = NULL; |
37e680a1 | 2121 | |
5537252b | 2122 | i915_gem_object_invalidate(obj); |
6c085a72 CW |
2123 | |
2124 | return 0; | |
2125 | } | |
2126 | ||
37e680a1 | 2127 | static int |
6c085a72 | 2128 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 2129 | { |
fac5e23e | 2130 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e5281ccd CW |
2131 | int page_count, i; |
2132 | struct address_space *mapping; | |
9da3da66 CW |
2133 | struct sg_table *st; |
2134 | struct scatterlist *sg; | |
85d1225e | 2135 | struct sgt_iter sgt_iter; |
e5281ccd | 2136 | struct page *page; |
90797e6d | 2137 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
e2273302 | 2138 | int ret; |
6c085a72 | 2139 | gfp_t gfp; |
e5281ccd | 2140 | |
6c085a72 CW |
2141 | /* Assert that the object is not currently in any GPU domain. As it |
2142 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2143 | * a GPU cache | |
2144 | */ | |
2145 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
2146 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
2147 | ||
9da3da66 CW |
2148 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
2149 | if (st == NULL) | |
2150 | return -ENOMEM; | |
2151 | ||
05394f39 | 2152 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 2153 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 2154 | kfree(st); |
e5281ccd | 2155 | return -ENOMEM; |
9da3da66 | 2156 | } |
e5281ccd | 2157 | |
9da3da66 CW |
2158 | /* Get the list of pages out of our struct file. They'll be pinned |
2159 | * at this point until we release them. | |
2160 | * | |
2161 | * Fail silently without starting the shrinker | |
2162 | */ | |
496ad9aa | 2163 | mapping = file_inode(obj->base.filp)->i_mapping; |
c62d2555 | 2164 | gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM)); |
d0164adc | 2165 | gfp |= __GFP_NORETRY | __GFP_NOWARN; |
90797e6d ID |
2166 | sg = st->sgl; |
2167 | st->nents = 0; | |
2168 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
2169 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2170 | if (IS_ERR(page)) { | |
21ab4e74 CW |
2171 | i915_gem_shrink(dev_priv, |
2172 | page_count, | |
2173 | I915_SHRINK_BOUND | | |
2174 | I915_SHRINK_UNBOUND | | |
2175 | I915_SHRINK_PURGEABLE); | |
6c085a72 CW |
2176 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2177 | } | |
2178 | if (IS_ERR(page)) { | |
2179 | /* We've tried hard to allocate the memory by reaping | |
2180 | * our own buffer, now let the real VM do its job and | |
2181 | * go down in flames if truly OOM. | |
2182 | */ | |
6c085a72 | 2183 | i915_gem_shrink_all(dev_priv); |
f461d1be | 2184 | page = shmem_read_mapping_page(mapping, i); |
e2273302 ID |
2185 | if (IS_ERR(page)) { |
2186 | ret = PTR_ERR(page); | |
6c085a72 | 2187 | goto err_pages; |
e2273302 | 2188 | } |
6c085a72 | 2189 | } |
426729dc KRW |
2190 | #ifdef CONFIG_SWIOTLB |
2191 | if (swiotlb_nr_tbl()) { | |
2192 | st->nents++; | |
2193 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2194 | sg = sg_next(sg); | |
2195 | continue; | |
2196 | } | |
2197 | #endif | |
90797e6d ID |
2198 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
2199 | if (i) | |
2200 | sg = sg_next(sg); | |
2201 | st->nents++; | |
2202 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2203 | } else { | |
2204 | sg->length += PAGE_SIZE; | |
2205 | } | |
2206 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
2207 | |
2208 | /* Check that the i965g/gm workaround works. */ | |
2209 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 2210 | } |
426729dc KRW |
2211 | #ifdef CONFIG_SWIOTLB |
2212 | if (!swiotlb_nr_tbl()) | |
2213 | #endif | |
2214 | sg_mark_end(sg); | |
74ce6b6c CW |
2215 | obj->pages = st; |
2216 | ||
e2273302 ID |
2217 | ret = i915_gem_gtt_prepare_object(obj); |
2218 | if (ret) | |
2219 | goto err_pages; | |
2220 | ||
6dacfd2f | 2221 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
2222 | i915_gem_object_do_bit_17_swizzle(obj); |
2223 | ||
656bfa3a DV |
2224 | if (obj->tiling_mode != I915_TILING_NONE && |
2225 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2226 | i915_gem_object_pin_pages(obj); | |
2227 | ||
e5281ccd CW |
2228 | return 0; |
2229 | ||
2230 | err_pages: | |
90797e6d | 2231 | sg_mark_end(sg); |
85d1225e DG |
2232 | for_each_sgt_page(page, sgt_iter, st) |
2233 | put_page(page); | |
9da3da66 CW |
2234 | sg_free_table(st); |
2235 | kfree(st); | |
0820baf3 CW |
2236 | |
2237 | /* shmemfs first checks if there is enough memory to allocate the page | |
2238 | * and reports ENOSPC should there be insufficient, along with the usual | |
2239 | * ENOMEM for a genuine allocation failure. | |
2240 | * | |
2241 | * We use ENOSPC in our driver to mean that we have run out of aperture | |
2242 | * space and so want to translate the error from shmemfs back to our | |
2243 | * usual understanding of ENOMEM. | |
2244 | */ | |
e2273302 ID |
2245 | if (ret == -ENOSPC) |
2246 | ret = -ENOMEM; | |
2247 | ||
2248 | return ret; | |
673a394b EA |
2249 | } |
2250 | ||
37e680a1 CW |
2251 | /* Ensure that the associated pages are gathered from the backing storage |
2252 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
2253 | * multiple times before they are released by a single call to | |
2254 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
2255 | * either as a result of memory pressure (reaping pages under the shrinker) | |
2256 | * or as the object is itself released. | |
2257 | */ | |
2258 | int | |
2259 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
2260 | { | |
fac5e23e | 2261 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
37e680a1 CW |
2262 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
2263 | int ret; | |
2264 | ||
2f745ad3 | 2265 | if (obj->pages) |
37e680a1 CW |
2266 | return 0; |
2267 | ||
43e28f09 | 2268 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 2269 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
8c99e57d | 2270 | return -EFAULT; |
43e28f09 CW |
2271 | } |
2272 | ||
a5570178 CW |
2273 | BUG_ON(obj->pages_pin_count); |
2274 | ||
37e680a1 CW |
2275 | ret = ops->get_pages(obj); |
2276 | if (ret) | |
2277 | return ret; | |
2278 | ||
35c20a60 | 2279 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
ee286370 CW |
2280 | |
2281 | obj->get_page.sg = obj->pages->sgl; | |
2282 | obj->get_page.last = 0; | |
2283 | ||
37e680a1 | 2284 | return 0; |
673a394b EA |
2285 | } |
2286 | ||
dd6034c6 DG |
2287 | /* The 'mapping' part of i915_gem_object_pin_map() below */ |
2288 | static void *i915_gem_object_map(const struct drm_i915_gem_object *obj) | |
2289 | { | |
2290 | unsigned long n_pages = obj->base.size >> PAGE_SHIFT; | |
2291 | struct sg_table *sgt = obj->pages; | |
85d1225e DG |
2292 | struct sgt_iter sgt_iter; |
2293 | struct page *page; | |
b338fa47 DG |
2294 | struct page *stack_pages[32]; |
2295 | struct page **pages = stack_pages; | |
dd6034c6 DG |
2296 | unsigned long i = 0; |
2297 | void *addr; | |
2298 | ||
2299 | /* A single page can always be kmapped */ | |
2300 | if (n_pages == 1) | |
2301 | return kmap(sg_page(sgt->sgl)); | |
2302 | ||
b338fa47 DG |
2303 | if (n_pages > ARRAY_SIZE(stack_pages)) { |
2304 | /* Too big for stack -- allocate temporary array instead */ | |
2305 | pages = drm_malloc_gfp(n_pages, sizeof(*pages), GFP_TEMPORARY); | |
2306 | if (!pages) | |
2307 | return NULL; | |
2308 | } | |
dd6034c6 | 2309 | |
85d1225e DG |
2310 | for_each_sgt_page(page, sgt_iter, sgt) |
2311 | pages[i++] = page; | |
dd6034c6 DG |
2312 | |
2313 | /* Check that we have the expected number of pages */ | |
2314 | GEM_BUG_ON(i != n_pages); | |
2315 | ||
2316 | addr = vmap(pages, n_pages, 0, PAGE_KERNEL); | |
2317 | ||
b338fa47 DG |
2318 | if (pages != stack_pages) |
2319 | drm_free_large(pages); | |
dd6034c6 DG |
2320 | |
2321 | return addr; | |
2322 | } | |
2323 | ||
2324 | /* get, pin, and map the pages of the object into kernel space */ | |
0a798eb9 CW |
2325 | void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj) |
2326 | { | |
2327 | int ret; | |
2328 | ||
2329 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
2330 | ||
2331 | ret = i915_gem_object_get_pages(obj); | |
2332 | if (ret) | |
2333 | return ERR_PTR(ret); | |
2334 | ||
2335 | i915_gem_object_pin_pages(obj); | |
2336 | ||
dd6034c6 DG |
2337 | if (!obj->mapping) { |
2338 | obj->mapping = i915_gem_object_map(obj); | |
2339 | if (!obj->mapping) { | |
0a798eb9 CW |
2340 | i915_gem_object_unpin_pages(obj); |
2341 | return ERR_PTR(-ENOMEM); | |
2342 | } | |
2343 | } | |
2344 | ||
2345 | return obj->mapping; | |
2346 | } | |
2347 | ||
b4716185 | 2348 | static void |
fa545cbf CW |
2349 | i915_gem_object_retire__write(struct i915_gem_active *active, |
2350 | struct drm_i915_gem_request *request) | |
e2d05a8b | 2351 | { |
fa545cbf CW |
2352 | struct drm_i915_gem_object *obj = |
2353 | container_of(active, struct drm_i915_gem_object, last_write); | |
b4716185 | 2354 | |
de152b62 | 2355 | intel_fb_obj_flush(obj, true, ORIGIN_CS); |
e2d05a8b BW |
2356 | } |
2357 | ||
caea7476 | 2358 | static void |
fa545cbf CW |
2359 | i915_gem_object_retire__read(struct i915_gem_active *active, |
2360 | struct drm_i915_gem_request *request) | |
ce44b0ea | 2361 | { |
fa545cbf CW |
2362 | int idx = request->engine->id; |
2363 | struct drm_i915_gem_object *obj = | |
2364 | container_of(active, struct drm_i915_gem_object, last_read[idx]); | |
ce44b0ea | 2365 | |
fa545cbf | 2366 | GEM_BUG_ON((obj->active & (1 << idx)) == 0); |
b4716185 | 2367 | |
7e21d648 | 2368 | obj->active &= ~(1 << idx); |
b4716185 CW |
2369 | if (obj->active) |
2370 | return; | |
caea7476 | 2371 | |
6c246959 CW |
2372 | /* Bump our place on the bound list to keep it roughly in LRU order |
2373 | * so that we don't steal from recently used but inactive objects | |
2374 | * (unless we are forced to ofc!) | |
2375 | */ | |
b0decaf7 CW |
2376 | if (obj->bind_count) |
2377 | list_move_tail(&obj->global_list, | |
2378 | &request->i915->mm.bound_list); | |
caea7476 | 2379 | |
f8c417cd | 2380 | i915_gem_object_put(obj); |
c8725f3d CW |
2381 | } |
2382 | ||
7b4d3a16 | 2383 | static bool i915_context_is_banned(const struct i915_gem_context *ctx) |
be62acb4 | 2384 | { |
44e2c070 | 2385 | unsigned long elapsed; |
be62acb4 | 2386 | |
44e2c070 | 2387 | if (ctx->hang_stats.banned) |
be62acb4 MK |
2388 | return true; |
2389 | ||
7b4d3a16 | 2390 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
676fa572 CW |
2391 | if (ctx->hang_stats.ban_period_seconds && |
2392 | elapsed <= ctx->hang_stats.ban_period_seconds) { | |
7b4d3a16 CW |
2393 | DRM_DEBUG("context hanging too fast, banning!\n"); |
2394 | return true; | |
be62acb4 MK |
2395 | } |
2396 | ||
2397 | return false; | |
2398 | } | |
2399 | ||
7b4d3a16 | 2400 | static void i915_set_reset_status(struct i915_gem_context *ctx, |
b6b0fac0 | 2401 | const bool guilty) |
aa60c664 | 2402 | { |
7b4d3a16 | 2403 | struct i915_ctx_hang_stats *hs = &ctx->hang_stats; |
44e2c070 MK |
2404 | |
2405 | if (guilty) { | |
7b4d3a16 | 2406 | hs->banned = i915_context_is_banned(ctx); |
44e2c070 MK |
2407 | hs->batch_active++; |
2408 | hs->guilty_ts = get_seconds(); | |
2409 | } else { | |
2410 | hs->batch_pending++; | |
aa60c664 MK |
2411 | } |
2412 | } | |
2413 | ||
8d9fc7fd | 2414 | struct drm_i915_gem_request * |
0bc40be8 | 2415 | i915_gem_find_active_request(struct intel_engine_cs *engine) |
9375e446 | 2416 | { |
4db080f9 CW |
2417 | struct drm_i915_gem_request *request; |
2418 | ||
f69a02c9 CW |
2419 | /* We are called by the error capture and reset at a random |
2420 | * point in time. In particular, note that neither is crucially | |
2421 | * ordered with an interrupt. After a hang, the GPU is dead and we | |
2422 | * assume that no more writes can happen (we waited long enough for | |
2423 | * all writes that were in transaction to be flushed) - adding an | |
2424 | * extra delay for a recent interrupt is pointless. Hence, we do | |
2425 | * not need an engine->irq_seqno_barrier() before the seqno reads. | |
2426 | */ | |
efdf7c06 | 2427 | list_for_each_entry(request, &engine->request_list, link) { |
f69a02c9 | 2428 | if (i915_gem_request_completed(request)) |
4db080f9 | 2429 | continue; |
aa60c664 | 2430 | |
b6b0fac0 | 2431 | return request; |
4db080f9 | 2432 | } |
b6b0fac0 MK |
2433 | |
2434 | return NULL; | |
2435 | } | |
2436 | ||
7b4d3a16 | 2437 | static void i915_gem_reset_engine_status(struct intel_engine_cs *engine) |
b6b0fac0 MK |
2438 | { |
2439 | struct drm_i915_gem_request *request; | |
2440 | bool ring_hung; | |
2441 | ||
0bc40be8 | 2442 | request = i915_gem_find_active_request(engine); |
b6b0fac0 MK |
2443 | if (request == NULL) |
2444 | return; | |
2445 | ||
0bc40be8 | 2446 | ring_hung = engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; |
b6b0fac0 | 2447 | |
7b4d3a16 | 2448 | i915_set_reset_status(request->ctx, ring_hung); |
efdf7c06 | 2449 | list_for_each_entry_continue(request, &engine->request_list, link) |
7b4d3a16 | 2450 | i915_set_reset_status(request->ctx, false); |
4db080f9 | 2451 | } |
aa60c664 | 2452 | |
7b4d3a16 | 2453 | static void i915_gem_reset_engine_cleanup(struct intel_engine_cs *engine) |
4db080f9 | 2454 | { |
7e37f889 | 2455 | struct intel_ring *ring; |
608c1a52 | 2456 | |
c4b0930b CW |
2457 | /* Mark all pending requests as complete so that any concurrent |
2458 | * (lockless) lookup doesn't try and wait upon the request as we | |
2459 | * reset it. | |
2460 | */ | |
7e37f889 | 2461 | intel_engine_init_seqno(engine, engine->last_submitted_seqno); |
c4b0930b | 2462 | |
dcb4c12a OM |
2463 | /* |
2464 | * Clear the execlists queue up before freeing the requests, as those | |
2465 | * are the ones that keep the context and ringbuffer backing objects | |
2466 | * pinned in place. | |
2467 | */ | |
dcb4c12a | 2468 | |
7de1691a | 2469 | if (i915.enable_execlists) { |
27af5eea TU |
2470 | /* Ensure irq handler finishes or is cancelled. */ |
2471 | tasklet_kill(&engine->irq_tasklet); | |
1197b4f2 | 2472 | |
e39d42fa | 2473 | intel_execlists_cancel_requests(engine); |
dcb4c12a OM |
2474 | } |
2475 | ||
1d62beea BW |
2476 | /* |
2477 | * We must free the requests after all the corresponding objects have | |
2478 | * been moved off active lists. Which is the same order as the normal | |
2479 | * retire_requests function does. This is important if object hold | |
2480 | * implicit references on things like e.g. ppgtt address spaces through | |
2481 | * the request. | |
2482 | */ | |
05235c53 | 2483 | if (!list_empty(&engine->request_list)) { |
1d62beea BW |
2484 | struct drm_i915_gem_request *request; |
2485 | ||
05235c53 CW |
2486 | request = list_last_entry(&engine->request_list, |
2487 | struct drm_i915_gem_request, | |
efdf7c06 | 2488 | link); |
1d62beea | 2489 | |
05235c53 | 2490 | i915_gem_request_retire_upto(request); |
1d62beea | 2491 | } |
608c1a52 CW |
2492 | |
2493 | /* Having flushed all requests from all queues, we know that all | |
2494 | * ringbuffers must now be empty. However, since we do not reclaim | |
2495 | * all space when retiring the request (to prevent HEADs colliding | |
2496 | * with rapid ringbuffer wraparound) the amount of available space | |
2497 | * upon reset is less than when we start. Do one more pass over | |
2498 | * all the ringbuffers to reset last_retired_head. | |
2499 | */ | |
7e37f889 CW |
2500 | list_for_each_entry(ring, &engine->buffers, link) { |
2501 | ring->last_retired_head = ring->tail; | |
2502 | intel_ring_update_space(ring); | |
608c1a52 | 2503 | } |
2ed53a94 | 2504 | |
b913b33c | 2505 | engine->i915->gt.active_engines &= ~intel_engine_flag(engine); |
673a394b EA |
2506 | } |
2507 | ||
069efc1d | 2508 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2509 | { |
fac5e23e | 2510 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 2511 | struct intel_engine_cs *engine; |
673a394b | 2512 | |
4db080f9 CW |
2513 | /* |
2514 | * Before we free the objects from the requests, we need to inspect | |
2515 | * them for finding the guilty party. As the requests only borrow | |
2516 | * their reference to the objects, the inspection must be done first. | |
2517 | */ | |
b4ac5afc | 2518 | for_each_engine(engine, dev_priv) |
7b4d3a16 | 2519 | i915_gem_reset_engine_status(engine); |
4db080f9 | 2520 | |
b4ac5afc | 2521 | for_each_engine(engine, dev_priv) |
7b4d3a16 | 2522 | i915_gem_reset_engine_cleanup(engine); |
b913b33c | 2523 | mod_delayed_work(dev_priv->wq, &dev_priv->gt.idle_work, 0); |
dfaae392 | 2524 | |
acce9ffa BW |
2525 | i915_gem_context_reset(dev); |
2526 | ||
19b2dbde | 2527 | i915_gem_restore_fences(dev); |
673a394b EA |
2528 | } |
2529 | ||
75ef9da2 | 2530 | static void |
673a394b EA |
2531 | i915_gem_retire_work_handler(struct work_struct *work) |
2532 | { | |
b29c19b6 | 2533 | struct drm_i915_private *dev_priv = |
67d97da3 | 2534 | container_of(work, typeof(*dev_priv), gt.retire_work.work); |
91c8a326 | 2535 | struct drm_device *dev = &dev_priv->drm; |
673a394b | 2536 | |
891b48cf | 2537 | /* Come back later if the device is busy... */ |
b29c19b6 | 2538 | if (mutex_trylock(&dev->struct_mutex)) { |
67d97da3 | 2539 | i915_gem_retire_requests(dev_priv); |
b29c19b6 | 2540 | mutex_unlock(&dev->struct_mutex); |
673a394b | 2541 | } |
67d97da3 CW |
2542 | |
2543 | /* Keep the retire handler running until we are finally idle. | |
2544 | * We do not need to do this test under locking as in the worst-case | |
2545 | * we queue the retire worker once too often. | |
2546 | */ | |
c9615613 CW |
2547 | if (READ_ONCE(dev_priv->gt.awake)) { |
2548 | i915_queue_hangcheck(dev_priv); | |
67d97da3 CW |
2549 | queue_delayed_work(dev_priv->wq, |
2550 | &dev_priv->gt.retire_work, | |
bcb45086 | 2551 | round_jiffies_up_relative(HZ)); |
c9615613 | 2552 | } |
b29c19b6 | 2553 | } |
0a58705b | 2554 | |
b29c19b6 CW |
2555 | static void |
2556 | i915_gem_idle_work_handler(struct work_struct *work) | |
2557 | { | |
2558 | struct drm_i915_private *dev_priv = | |
67d97da3 | 2559 | container_of(work, typeof(*dev_priv), gt.idle_work.work); |
91c8a326 | 2560 | struct drm_device *dev = &dev_priv->drm; |
b4ac5afc | 2561 | struct intel_engine_cs *engine; |
67d97da3 CW |
2562 | unsigned int stuck_engines; |
2563 | bool rearm_hangcheck; | |
2564 | ||
2565 | if (!READ_ONCE(dev_priv->gt.awake)) | |
2566 | return; | |
2567 | ||
2568 | if (READ_ONCE(dev_priv->gt.active_engines)) | |
2569 | return; | |
2570 | ||
2571 | rearm_hangcheck = | |
2572 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); | |
2573 | ||
2574 | if (!mutex_trylock(&dev->struct_mutex)) { | |
2575 | /* Currently busy, come back later */ | |
2576 | mod_delayed_work(dev_priv->wq, | |
2577 | &dev_priv->gt.idle_work, | |
2578 | msecs_to_jiffies(50)); | |
2579 | goto out_rearm; | |
2580 | } | |
2581 | ||
2582 | if (dev_priv->gt.active_engines) | |
2583 | goto out_unlock; | |
b29c19b6 | 2584 | |
b4ac5afc | 2585 | for_each_engine(engine, dev_priv) |
67d97da3 | 2586 | i915_gem_batch_pool_fini(&engine->batch_pool); |
35c94185 | 2587 | |
67d97da3 CW |
2588 | GEM_BUG_ON(!dev_priv->gt.awake); |
2589 | dev_priv->gt.awake = false; | |
2590 | rearm_hangcheck = false; | |
30ecad77 | 2591 | |
2529d570 CW |
2592 | /* As we have disabled hangcheck, we need to unstick any waiters still |
2593 | * hanging around. However, as we may be racing against the interrupt | |
2594 | * handler or the waiters themselves, we skip enabling the fake-irq. | |
2595 | */ | |
67d97da3 | 2596 | stuck_engines = intel_kick_waiters(dev_priv); |
2529d570 CW |
2597 | if (unlikely(stuck_engines)) |
2598 | DRM_DEBUG_DRIVER("kicked stuck waiters (%x)...missed irq?\n", | |
2599 | stuck_engines); | |
35c94185 | 2600 | |
67d97da3 CW |
2601 | if (INTEL_GEN(dev_priv) >= 6) |
2602 | gen6_rps_idle(dev_priv); | |
2603 | intel_runtime_pm_put(dev_priv); | |
2604 | out_unlock: | |
2605 | mutex_unlock(&dev->struct_mutex); | |
b29c19b6 | 2606 | |
67d97da3 CW |
2607 | out_rearm: |
2608 | if (rearm_hangcheck) { | |
2609 | GEM_BUG_ON(!dev_priv->gt.awake); | |
2610 | i915_queue_hangcheck(dev_priv); | |
35c94185 | 2611 | } |
673a394b EA |
2612 | } |
2613 | ||
b1f788c6 CW |
2614 | void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file) |
2615 | { | |
2616 | struct drm_i915_gem_object *obj = to_intel_bo(gem); | |
2617 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
2618 | struct i915_vma *vma, *vn; | |
2619 | ||
2620 | mutex_lock(&obj->base.dev->struct_mutex); | |
2621 | list_for_each_entry_safe(vma, vn, &obj->vma_list, obj_link) | |
2622 | if (vma->vm->file == fpriv) | |
2623 | i915_vma_close(vma); | |
2624 | mutex_unlock(&obj->base.dev->struct_mutex); | |
2625 | } | |
2626 | ||
23ba4fd0 BW |
2627 | /** |
2628 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
14bb2c11 TU |
2629 | * @dev: drm device pointer |
2630 | * @data: ioctl data blob | |
2631 | * @file: drm file pointer | |
23ba4fd0 BW |
2632 | * |
2633 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2634 | * the timeout parameter. | |
2635 | * -ETIME: object is still busy after timeout | |
2636 | * -ERESTARTSYS: signal interrupted the wait | |
2637 | * -ENONENT: object doesn't exist | |
2638 | * Also possible, but rare: | |
2639 | * -EAGAIN: GPU wedged | |
2640 | * -ENOMEM: damn | |
2641 | * -ENODEV: Internal IRQ fail | |
2642 | * -E?: The add request failed | |
2643 | * | |
2644 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2645 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2646 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2647 | * without holding struct_mutex the object may become re-busied before this | |
2648 | * function completes. A similar but shorter * race condition exists in the busy | |
2649 | * ioctl | |
2650 | */ | |
2651 | int | |
2652 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2653 | { | |
2654 | struct drm_i915_gem_wait *args = data; | |
2655 | struct drm_i915_gem_object *obj; | |
27c01aae | 2656 | struct drm_i915_gem_request *requests[I915_NUM_ENGINES]; |
b4716185 CW |
2657 | int i, n = 0; |
2658 | int ret; | |
23ba4fd0 | 2659 | |
11b5d511 DV |
2660 | if (args->flags != 0) |
2661 | return -EINVAL; | |
2662 | ||
23ba4fd0 BW |
2663 | ret = i915_mutex_lock_interruptible(dev); |
2664 | if (ret) | |
2665 | return ret; | |
2666 | ||
03ac0642 CW |
2667 | obj = i915_gem_object_lookup(file, args->bo_handle); |
2668 | if (!obj) { | |
23ba4fd0 BW |
2669 | mutex_unlock(&dev->struct_mutex); |
2670 | return -ENOENT; | |
2671 | } | |
2672 | ||
b4716185 | 2673 | if (!obj->active) |
97b2a6a1 | 2674 | goto out; |
23ba4fd0 | 2675 | |
666796da | 2676 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
27c01aae | 2677 | struct drm_i915_gem_request *req; |
b4716185 | 2678 | |
d72d908b CW |
2679 | req = i915_gem_active_get(&obj->last_read[i], |
2680 | &obj->base.dev->struct_mutex); | |
27c01aae CW |
2681 | if (req) |
2682 | requests[n++] = req; | |
b4716185 CW |
2683 | } |
2684 | ||
21c310f2 CW |
2685 | out: |
2686 | i915_gem_object_put(obj); | |
23ba4fd0 BW |
2687 | mutex_unlock(&dev->struct_mutex); |
2688 | ||
b4716185 CW |
2689 | for (i = 0; i < n; i++) { |
2690 | if (ret == 0) | |
776f3236 CW |
2691 | ret = i915_wait_request(requests[i], true, |
2692 | args->timeout_ns > 0 ? &args->timeout_ns : NULL, | |
2693 | to_rps_client(file)); | |
27c01aae | 2694 | i915_gem_request_put(requests[i]); |
b4716185 | 2695 | } |
ff865885 | 2696 | return ret; |
23ba4fd0 BW |
2697 | } |
2698 | ||
b4716185 | 2699 | static int |
fa545cbf | 2700 | __i915_gem_object_sync(struct drm_i915_gem_request *to, |
8e637178 | 2701 | struct drm_i915_gem_request *from) |
b4716185 | 2702 | { |
b4716185 CW |
2703 | int ret; |
2704 | ||
8e637178 | 2705 | if (to->engine == from->engine) |
b4716185 CW |
2706 | return 0; |
2707 | ||
39df9190 | 2708 | if (!i915.semaphores) { |
776f3236 CW |
2709 | ret = i915_wait_request(from, |
2710 | from->i915->mm.interruptible, | |
2711 | NULL, | |
2712 | NO_WAITBOOST); | |
b4716185 CW |
2713 | if (ret) |
2714 | return ret; | |
b4716185 | 2715 | } else { |
8e637178 | 2716 | int idx = intel_engine_sync_index(from->engine, to->engine); |
ddf07be7 | 2717 | if (from->fence.seqno <= from->engine->semaphore.sync_seqno[idx]) |
b4716185 CW |
2718 | return 0; |
2719 | ||
8e637178 | 2720 | trace_i915_gem_ring_sync_to(to, from); |
ddf07be7 | 2721 | ret = to->engine->semaphore.sync_to(to, from); |
b4716185 CW |
2722 | if (ret) |
2723 | return ret; | |
2724 | ||
ddf07be7 | 2725 | from->engine->semaphore.sync_seqno[idx] = from->fence.seqno; |
b4716185 CW |
2726 | } |
2727 | ||
2728 | return 0; | |
2729 | } | |
2730 | ||
5816d648 BW |
2731 | /** |
2732 | * i915_gem_object_sync - sync an object to a ring. | |
2733 | * | |
2734 | * @obj: object which may be in use on another ring. | |
8e637178 | 2735 | * @to: request we are wishing to use |
5816d648 BW |
2736 | * |
2737 | * This code is meant to abstract object synchronization with the GPU. | |
8e637178 CW |
2738 | * Conceptually we serialise writes between engines inside the GPU. |
2739 | * We only allow one engine to write into a buffer at any time, but | |
2740 | * multiple readers. To ensure each has a coherent view of memory, we must: | |
b4716185 CW |
2741 | * |
2742 | * - If there is an outstanding write request to the object, the new | |
2743 | * request must wait for it to complete (either CPU or in hw, requests | |
2744 | * on the same ring will be naturally ordered). | |
2745 | * | |
2746 | * - If we are a write request (pending_write_domain is set), the new | |
2747 | * request must wait for outstanding read requests to complete. | |
5816d648 BW |
2748 | * |
2749 | * Returns 0 if successful, else propagates up the lower layer error. | |
2750 | */ | |
2911a35b BW |
2751 | int |
2752 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
8e637178 | 2753 | struct drm_i915_gem_request *to) |
2911a35b | 2754 | { |
8cac6f6c CW |
2755 | struct i915_gem_active *active; |
2756 | unsigned long active_mask; | |
2757 | int idx; | |
41c52415 | 2758 | |
8cac6f6c | 2759 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
2911a35b | 2760 | |
8cac6f6c CW |
2761 | active_mask = obj->active; |
2762 | if (!active_mask) | |
2763 | return 0; | |
27c01aae | 2764 | |
8cac6f6c CW |
2765 | if (obj->base.pending_write_domain) { |
2766 | active = obj->last_read; | |
b4716185 | 2767 | } else { |
8cac6f6c CW |
2768 | active_mask = 1; |
2769 | active = &obj->last_write; | |
b4716185 | 2770 | } |
8cac6f6c CW |
2771 | |
2772 | for_each_active(active_mask, idx) { | |
2773 | struct drm_i915_gem_request *request; | |
2774 | int ret; | |
2775 | ||
2776 | request = i915_gem_active_peek(&active[idx], | |
2777 | &obj->base.dev->struct_mutex); | |
2778 | if (!request) | |
2779 | continue; | |
2780 | ||
fa545cbf | 2781 | ret = __i915_gem_object_sync(to, request); |
b4716185 CW |
2782 | if (ret) |
2783 | return ret; | |
2784 | } | |
2911a35b | 2785 | |
b4716185 | 2786 | return 0; |
2911a35b BW |
2787 | } |
2788 | ||
b5ffc9bc CW |
2789 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2790 | { | |
2791 | u32 old_write_domain, old_read_domains; | |
2792 | ||
b5ffc9bc CW |
2793 | /* Force a pagefault for domain tracking on next user access */ |
2794 | i915_gem_release_mmap(obj); | |
2795 | ||
b97c3d9c KP |
2796 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2797 | return; | |
2798 | ||
b5ffc9bc CW |
2799 | old_read_domains = obj->base.read_domains; |
2800 | old_write_domain = obj->base.write_domain; | |
2801 | ||
2802 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2803 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2804 | ||
2805 | trace_i915_gem_object_change_domain(obj, | |
2806 | old_read_domains, | |
2807 | old_write_domain); | |
2808 | } | |
2809 | ||
8ef8561f CW |
2810 | static void __i915_vma_iounmap(struct i915_vma *vma) |
2811 | { | |
20dfbde4 | 2812 | GEM_BUG_ON(i915_vma_is_pinned(vma)); |
8ef8561f CW |
2813 | |
2814 | if (vma->iomap == NULL) | |
2815 | return; | |
2816 | ||
2817 | io_mapping_unmap(vma->iomap); | |
2818 | vma->iomap = NULL; | |
2819 | } | |
2820 | ||
df0e9a28 | 2821 | int i915_vma_unbind(struct i915_vma *vma) |
673a394b | 2822 | { |
07fe0b12 | 2823 | struct drm_i915_gem_object *obj = vma->obj; |
b0decaf7 | 2824 | unsigned long active; |
43e28f09 | 2825 | int ret; |
673a394b | 2826 | |
b0decaf7 CW |
2827 | /* First wait upon any activity as retiring the request may |
2828 | * have side-effects such as unpinning or even unbinding this vma. | |
2829 | */ | |
2830 | active = i915_vma_get_active(vma); | |
df0e9a28 | 2831 | if (active) { |
b0decaf7 CW |
2832 | int idx; |
2833 | ||
b1f788c6 CW |
2834 | /* When a closed VMA is retired, it is unbound - eek. |
2835 | * In order to prevent it from being recursively closed, | |
2836 | * take a pin on the vma so that the second unbind is | |
2837 | * aborted. | |
2838 | */ | |
20dfbde4 | 2839 | __i915_vma_pin(vma); |
b1f788c6 | 2840 | |
b0decaf7 CW |
2841 | for_each_active(active, idx) { |
2842 | ret = i915_gem_active_retire(&vma->last_read[idx], | |
2843 | &vma->vm->dev->struct_mutex); | |
2844 | if (ret) | |
b1f788c6 | 2845 | break; |
b0decaf7 CW |
2846 | } |
2847 | ||
20dfbde4 | 2848 | __i915_vma_unpin(vma); |
b1f788c6 CW |
2849 | if (ret) |
2850 | return ret; | |
2851 | ||
b0decaf7 CW |
2852 | GEM_BUG_ON(i915_vma_is_active(vma)); |
2853 | } | |
2854 | ||
20dfbde4 | 2855 | if (i915_vma_is_pinned(vma)) |
b0decaf7 CW |
2856 | return -EBUSY; |
2857 | ||
b1f788c6 CW |
2858 | if (!drm_mm_node_allocated(&vma->node)) |
2859 | goto destroy; | |
433544bd | 2860 | |
15717de2 CW |
2861 | GEM_BUG_ON(obj->bind_count == 0); |
2862 | GEM_BUG_ON(!obj->pages); | |
c4670ad0 | 2863 | |
596c5923 | 2864 | if (vma->is_ggtt && vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { |
8b1bc9b4 | 2865 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2866 | |
8b1bc9b4 DV |
2867 | /* release the fence reg _after_ flushing */ |
2868 | ret = i915_gem_object_put_fence(obj); | |
2869 | if (ret) | |
2870 | return ret; | |
8ef8561f CW |
2871 | |
2872 | __i915_vma_iounmap(vma); | |
8b1bc9b4 | 2873 | } |
96b47b65 | 2874 | |
50e046b6 CW |
2875 | if (likely(!vma->vm->closed)) { |
2876 | trace_i915_vma_unbind(vma); | |
2877 | vma->vm->unbind_vma(vma); | |
2878 | } | |
5e562f1d | 2879 | vma->bound = 0; |
6f65e29a | 2880 | |
50e046b6 CW |
2881 | drm_mm_remove_node(&vma->node); |
2882 | list_move_tail(&vma->vm_link, &vma->vm->unbound_list); | |
2883 | ||
596c5923 | 2884 | if (vma->is_ggtt) { |
fe14d5f4 TU |
2885 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { |
2886 | obj->map_and_fenceable = false; | |
2887 | } else if (vma->ggtt_view.pages) { | |
2888 | sg_free_table(vma->ggtt_view.pages); | |
2889 | kfree(vma->ggtt_view.pages); | |
fe14d5f4 | 2890 | } |
016a65a3 | 2891 | vma->ggtt_view.pages = NULL; |
fe14d5f4 | 2892 | } |
673a394b | 2893 | |
2f633156 | 2894 | /* Since the unbound list is global, only move to that list if |
b93dab6e | 2895 | * no more VMAs exist. */ |
15717de2 CW |
2896 | if (--obj->bind_count == 0) |
2897 | list_move_tail(&obj->global_list, | |
2898 | &to_i915(obj->base.dev)->mm.unbound_list); | |
673a394b | 2899 | |
70903c3b CW |
2900 | /* And finally now the object is completely decoupled from this vma, |
2901 | * we can drop its hold on the backing storage and allow it to be | |
2902 | * reaped by the shrinker. | |
2903 | */ | |
2904 | i915_gem_object_unpin_pages(obj); | |
2905 | ||
b1f788c6 CW |
2906 | destroy: |
2907 | if (unlikely(vma->closed)) | |
2908 | i915_vma_destroy(vma); | |
2909 | ||
88241785 | 2910 | return 0; |
54cf91dc CW |
2911 | } |
2912 | ||
6e5a5beb | 2913 | int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv) |
4df2faf4 | 2914 | { |
e2f80391 | 2915 | struct intel_engine_cs *engine; |
b4ac5afc | 2916 | int ret; |
4df2faf4 | 2917 | |
91c8a326 | 2918 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
6e5a5beb | 2919 | |
b4ac5afc | 2920 | for_each_engine(engine, dev_priv) { |
62e63007 CW |
2921 | if (engine->last_context == NULL) |
2922 | continue; | |
2923 | ||
666796da | 2924 | ret = intel_engine_idle(engine); |
1ec14ad3 CW |
2925 | if (ret) |
2926 | return ret; | |
2927 | } | |
4df2faf4 | 2928 | |
8a1a49f9 | 2929 | return 0; |
4df2faf4 DV |
2930 | } |
2931 | ||
4144f9b5 | 2932 | static bool i915_gem_valid_gtt_space(struct i915_vma *vma, |
42d6ab48 CW |
2933 | unsigned long cache_level) |
2934 | { | |
4144f9b5 | 2935 | struct drm_mm_node *gtt_space = &vma->node; |
42d6ab48 CW |
2936 | struct drm_mm_node *other; |
2937 | ||
4144f9b5 CW |
2938 | /* |
2939 | * On some machines we have to be careful when putting differing types | |
2940 | * of snoopable memory together to avoid the prefetcher crossing memory | |
2941 | * domains and dying. During vm initialisation, we decide whether or not | |
2942 | * these constraints apply and set the drm_mm.color_adjust | |
2943 | * appropriately. | |
42d6ab48 | 2944 | */ |
4144f9b5 | 2945 | if (vma->vm->mm.color_adjust == NULL) |
42d6ab48 CW |
2946 | return true; |
2947 | ||
c6cfb325 | 2948 | if (!drm_mm_node_allocated(gtt_space)) |
42d6ab48 CW |
2949 | return true; |
2950 | ||
2951 | if (list_empty(>t_space->node_list)) | |
2952 | return true; | |
2953 | ||
2954 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
2955 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
2956 | return false; | |
2957 | ||
2958 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
2959 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
2960 | return false; | |
2961 | ||
2962 | return true; | |
2963 | } | |
2964 | ||
673a394b | 2965 | /** |
59bfa124 CW |
2966 | * i915_vma_insert - finds a slot for the vma in its address space |
2967 | * @vma: the vma | |
91b2db6f | 2968 | * @size: requested size in bytes (can be larger than the VMA) |
59bfa124 | 2969 | * @alignment: required alignment |
14bb2c11 | 2970 | * @flags: mask of PIN_* flags to use |
59bfa124 CW |
2971 | * |
2972 | * First we try to allocate some free space that meets the requirements for | |
2973 | * the VMA. Failiing that, if the flags permit, it will evict an old VMA, | |
2974 | * preferrably the oldest idle entry to make room for the new VMA. | |
2975 | * | |
2976 | * Returns: | |
2977 | * 0 on success, negative error code otherwise. | |
673a394b | 2978 | */ |
59bfa124 CW |
2979 | static int |
2980 | i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) | |
673a394b | 2981 | { |
59bfa124 CW |
2982 | struct drm_i915_private *dev_priv = to_i915(vma->vm->dev); |
2983 | struct drm_i915_gem_object *obj = vma->obj; | |
de180033 CW |
2984 | u64 start, end; |
2985 | u64 min_alignment; | |
07f73f69 | 2986 | int ret; |
673a394b | 2987 | |
59bfa124 CW |
2988 | GEM_BUG_ON(vma->bound); |
2989 | GEM_BUG_ON(drm_mm_node_allocated(&vma->node)); | |
de180033 CW |
2990 | |
2991 | size = max(size, vma->size); | |
2992 | if (flags & PIN_MAPPABLE) | |
2993 | size = i915_gem_get_ggtt_size(dev_priv, size, obj->tiling_mode); | |
2994 | ||
2995 | min_alignment = | |
2996 | i915_gem_get_ggtt_alignment(dev_priv, size, obj->tiling_mode, | |
2997 | flags & PIN_MAPPABLE); | |
2998 | if (alignment == 0) | |
2999 | alignment = min_alignment; | |
3000 | if (alignment & (min_alignment - 1)) { | |
3001 | DRM_DEBUG("Invalid object alignment requested %llu, minimum %llu\n", | |
3002 | alignment, min_alignment); | |
59bfa124 | 3003 | return -EINVAL; |
91e6711e | 3004 | } |
a00b10c3 | 3005 | |
101b506a | 3006 | start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; |
de180033 CW |
3007 | |
3008 | end = vma->vm->total; | |
101b506a | 3009 | if (flags & PIN_MAPPABLE) |
91b2db6f | 3010 | end = min_t(u64, end, dev_priv->ggtt.mappable_end); |
101b506a | 3011 | if (flags & PIN_ZONE_4G) |
48ea1e32 | 3012 | end = min_t(u64, end, (1ULL << 32) - PAGE_SIZE); |
101b506a | 3013 | |
91e6711e JL |
3014 | /* If binding the object/GGTT view requires more space than the entire |
3015 | * aperture has, reject it early before evicting everything in a vain | |
3016 | * attempt to find space. | |
654fc607 | 3017 | */ |
91e6711e | 3018 | if (size > end) { |
de180033 | 3019 | DRM_DEBUG("Attempting to bind an object larger than the aperture: request=%llu [object=%zd] > %s aperture=%llu\n", |
91b2db6f | 3020 | size, obj->base.size, |
1ec9e26d | 3021 | flags & PIN_MAPPABLE ? "mappable" : "total", |
d23db88c | 3022 | end); |
59bfa124 | 3023 | return -E2BIG; |
654fc607 CW |
3024 | } |
3025 | ||
37e680a1 | 3026 | ret = i915_gem_object_get_pages(obj); |
6c085a72 | 3027 | if (ret) |
59bfa124 | 3028 | return ret; |
6c085a72 | 3029 | |
fbdda6fb CW |
3030 | i915_gem_object_pin_pages(obj); |
3031 | ||
506a8e87 | 3032 | if (flags & PIN_OFFSET_FIXED) { |
59bfa124 | 3033 | u64 offset = flags & PIN_OFFSET_MASK; |
de180033 | 3034 | if (offset & (alignment - 1) || offset > end - size) { |
506a8e87 | 3035 | ret = -EINVAL; |
de180033 | 3036 | goto err_unpin; |
506a8e87 | 3037 | } |
de180033 | 3038 | |
506a8e87 CW |
3039 | vma->node.start = offset; |
3040 | vma->node.size = size; | |
3041 | vma->node.color = obj->cache_level; | |
de180033 | 3042 | ret = drm_mm_reserve_node(&vma->vm->mm, &vma->node); |
506a8e87 CW |
3043 | if (ret) { |
3044 | ret = i915_gem_evict_for_vma(vma); | |
3045 | if (ret == 0) | |
de180033 CW |
3046 | ret = drm_mm_reserve_node(&vma->vm->mm, &vma->node); |
3047 | if (ret) | |
3048 | goto err_unpin; | |
506a8e87 | 3049 | } |
101b506a | 3050 | } else { |
de180033 CW |
3051 | u32 search_flag, alloc_flag; |
3052 | ||
506a8e87 CW |
3053 | if (flags & PIN_HIGH) { |
3054 | search_flag = DRM_MM_SEARCH_BELOW; | |
3055 | alloc_flag = DRM_MM_CREATE_TOP; | |
3056 | } else { | |
3057 | search_flag = DRM_MM_SEARCH_DEFAULT; | |
3058 | alloc_flag = DRM_MM_CREATE_DEFAULT; | |
3059 | } | |
101b506a | 3060 | |
954c4691 CW |
3061 | /* We only allocate in PAGE_SIZE/GTT_PAGE_SIZE (4096) chunks, |
3062 | * so we know that we always have a minimum alignment of 4096. | |
3063 | * The drm_mm range manager is optimised to return results | |
3064 | * with zero alignment, so where possible use the optimal | |
3065 | * path. | |
3066 | */ | |
3067 | if (alignment <= 4096) | |
3068 | alignment = 0; | |
3069 | ||
0a9ae0d7 | 3070 | search_free: |
de180033 CW |
3071 | ret = drm_mm_insert_node_in_range_generic(&vma->vm->mm, |
3072 | &vma->node, | |
506a8e87 CW |
3073 | size, alignment, |
3074 | obj->cache_level, | |
3075 | start, end, | |
3076 | search_flag, | |
3077 | alloc_flag); | |
3078 | if (ret) { | |
de180033 | 3079 | ret = i915_gem_evict_something(vma->vm, size, alignment, |
506a8e87 CW |
3080 | obj->cache_level, |
3081 | start, end, | |
3082 | flags); | |
3083 | if (ret == 0) | |
3084 | goto search_free; | |
9731129c | 3085 | |
de180033 | 3086 | goto err_unpin; |
506a8e87 | 3087 | } |
673a394b | 3088 | } |
37508589 | 3089 | GEM_BUG_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level)); |
673a394b | 3090 | |
35c20a60 | 3091 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
de180033 | 3092 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); |
15717de2 | 3093 | obj->bind_count++; |
bf1a1092 | 3094 | |
59bfa124 | 3095 | return 0; |
2f633156 | 3096 | |
bc6bc15b | 3097 | err_unpin: |
2f633156 | 3098 | i915_gem_object_unpin_pages(obj); |
59bfa124 | 3099 | return ret; |
673a394b EA |
3100 | } |
3101 | ||
000433b6 | 3102 | bool |
2c22569b CW |
3103 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3104 | bool force) | |
673a394b | 3105 | { |
673a394b EA |
3106 | /* If we don't have a page list set up, then we're not pinned |
3107 | * to GPU, and we can ignore the cache flush because it'll happen | |
3108 | * again at bind time. | |
3109 | */ | |
05394f39 | 3110 | if (obj->pages == NULL) |
000433b6 | 3111 | return false; |
673a394b | 3112 | |
769ce464 ID |
3113 | /* |
3114 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3115 | * marked as wc by the system, or the system is cache-coherent. | |
3116 | */ | |
6a2c4232 | 3117 | if (obj->stolen || obj->phys_handle) |
000433b6 | 3118 | return false; |
769ce464 | 3119 | |
9c23f7fc CW |
3120 | /* If the GPU is snooping the contents of the CPU cache, |
3121 | * we do not need to manually clear the CPU cache lines. However, | |
3122 | * the caches are only snooped when the render cache is | |
3123 | * flushed/invalidated. As we always have to emit invalidations | |
3124 | * and flushes when moving into and out of the RENDER domain, correct | |
3125 | * snooping behaviour occurs naturally as the result of our domain | |
3126 | * tracking. | |
3127 | */ | |
0f71979a CW |
3128 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) { |
3129 | obj->cache_dirty = true; | |
000433b6 | 3130 | return false; |
0f71979a | 3131 | } |
9c23f7fc | 3132 | |
1c5d22f7 | 3133 | trace_i915_gem_object_clflush(obj); |
9da3da66 | 3134 | drm_clflush_sg(obj->pages); |
0f71979a | 3135 | obj->cache_dirty = false; |
000433b6 CW |
3136 | |
3137 | return true; | |
e47c68e9 EA |
3138 | } |
3139 | ||
3140 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3141 | static void | |
05394f39 | 3142 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3143 | { |
1c5d22f7 CW |
3144 | uint32_t old_write_domain; |
3145 | ||
05394f39 | 3146 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3147 | return; |
3148 | ||
63256ec5 | 3149 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3150 | * to it immediately go to main memory as far as we know, so there's |
3151 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3152 | * |
3153 | * However, we do have to enforce the order so that all writes through | |
3154 | * the GTT land before any writes to the device, such as updates to | |
3155 | * the GATT itself. | |
e47c68e9 | 3156 | */ |
63256ec5 CW |
3157 | wmb(); |
3158 | ||
05394f39 CW |
3159 | old_write_domain = obj->base.write_domain; |
3160 | obj->base.write_domain = 0; | |
1c5d22f7 | 3161 | |
de152b62 | 3162 | intel_fb_obj_flush(obj, false, ORIGIN_GTT); |
f99d7069 | 3163 | |
1c5d22f7 | 3164 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3165 | obj->base.read_domains, |
1c5d22f7 | 3166 | old_write_domain); |
e47c68e9 EA |
3167 | } |
3168 | ||
3169 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3170 | static void | |
e62b59e4 | 3171 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3172 | { |
1c5d22f7 | 3173 | uint32_t old_write_domain; |
e47c68e9 | 3174 | |
05394f39 | 3175 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3176 | return; |
3177 | ||
e62b59e4 | 3178 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
c033666a | 3179 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
000433b6 | 3180 | |
05394f39 CW |
3181 | old_write_domain = obj->base.write_domain; |
3182 | obj->base.write_domain = 0; | |
1c5d22f7 | 3183 | |
de152b62 | 3184 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
f99d7069 | 3185 | |
1c5d22f7 | 3186 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3187 | obj->base.read_domains, |
1c5d22f7 | 3188 | old_write_domain); |
e47c68e9 EA |
3189 | } |
3190 | ||
2ef7eeaa EA |
3191 | /** |
3192 | * Moves a single object to the GTT read, and possibly write domain. | |
14bb2c11 TU |
3193 | * @obj: object to act on |
3194 | * @write: ask for write access or read only | |
2ef7eeaa EA |
3195 | * |
3196 | * This function returns when the move is complete, including waiting on | |
3197 | * flushes to occur. | |
3198 | */ | |
79e53945 | 3199 | int |
2021746e | 3200 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3201 | { |
1c5d22f7 | 3202 | uint32_t old_write_domain, old_read_domains; |
43566ded | 3203 | struct i915_vma *vma; |
e47c68e9 | 3204 | int ret; |
2ef7eeaa | 3205 | |
0201f1ec | 3206 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3207 | if (ret) |
3208 | return ret; | |
3209 | ||
c13d87ea CW |
3210 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3211 | return 0; | |
3212 | ||
43566ded CW |
3213 | /* Flush and acquire obj->pages so that we are coherent through |
3214 | * direct access in memory with previous cached writes through | |
3215 | * shmemfs and that our cache domain tracking remains valid. | |
3216 | * For example, if the obj->filp was moved to swap without us | |
3217 | * being notified and releasing the pages, we would mistakenly | |
3218 | * continue to assume that the obj remained out of the CPU cached | |
3219 | * domain. | |
3220 | */ | |
3221 | ret = i915_gem_object_get_pages(obj); | |
3222 | if (ret) | |
3223 | return ret; | |
3224 | ||
e62b59e4 | 3225 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 3226 | |
d0a57789 CW |
3227 | /* Serialise direct access to this object with the barriers for |
3228 | * coherent writes from the GPU, by effectively invalidating the | |
3229 | * GTT domain upon first access. | |
3230 | */ | |
3231 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3232 | mb(); | |
3233 | ||
05394f39 CW |
3234 | old_write_domain = obj->base.write_domain; |
3235 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3236 | |
e47c68e9 EA |
3237 | /* It should now be out of any other write domains, and we can update |
3238 | * the domain values for our changes. | |
3239 | */ | |
05394f39 CW |
3240 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3241 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3242 | if (write) { |
05394f39 CW |
3243 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3244 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3245 | obj->dirty = 1; | |
2ef7eeaa EA |
3246 | } |
3247 | ||
1c5d22f7 CW |
3248 | trace_i915_gem_object_change_domain(obj, |
3249 | old_read_domains, | |
3250 | old_write_domain); | |
3251 | ||
8325a09d | 3252 | /* And bump the LRU for this access */ |
43566ded | 3253 | vma = i915_gem_obj_to_ggtt(obj); |
b0decaf7 CW |
3254 | if (vma && |
3255 | drm_mm_node_allocated(&vma->node) && | |
3256 | !i915_vma_is_active(vma)) | |
3257 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); | |
8325a09d | 3258 | |
e47c68e9 EA |
3259 | return 0; |
3260 | } | |
3261 | ||
ef55f92a CW |
3262 | /** |
3263 | * Changes the cache-level of an object across all VMA. | |
14bb2c11 TU |
3264 | * @obj: object to act on |
3265 | * @cache_level: new cache level to set for the object | |
ef55f92a CW |
3266 | * |
3267 | * After this function returns, the object will be in the new cache-level | |
3268 | * across all GTT and the contents of the backing storage will be coherent, | |
3269 | * with respect to the new cache-level. In order to keep the backing storage | |
3270 | * coherent for all users, we only allow a single cache level to be set | |
3271 | * globally on the object and prevent it from being changed whilst the | |
3272 | * hardware is reading from the object. That is if the object is currently | |
3273 | * on the scanout it will be set to uncached (or equivalent display | |
3274 | * cache coherency) and all non-MOCS GPU access will also be uncached so | |
3275 | * that all direct access to the scanout remains coherent. | |
3276 | */ | |
e4ffd173 CW |
3277 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3278 | enum i915_cache_level cache_level) | |
3279 | { | |
aa653a68 | 3280 | struct i915_vma *vma; |
ed75a55b | 3281 | int ret = 0; |
e4ffd173 CW |
3282 | |
3283 | if (obj->cache_level == cache_level) | |
ed75a55b | 3284 | goto out; |
e4ffd173 | 3285 | |
ef55f92a CW |
3286 | /* Inspect the list of currently bound VMA and unbind any that would |
3287 | * be invalid given the new cache-level. This is principally to | |
3288 | * catch the issue of the CS prefetch crossing page boundaries and | |
3289 | * reading an invalid PTE on older architectures. | |
3290 | */ | |
aa653a68 CW |
3291 | restart: |
3292 | list_for_each_entry(vma, &obj->vma_list, obj_link) { | |
ef55f92a CW |
3293 | if (!drm_mm_node_allocated(&vma->node)) |
3294 | continue; | |
3295 | ||
20dfbde4 | 3296 | if (i915_vma_is_pinned(vma)) { |
ef55f92a CW |
3297 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
3298 | return -EBUSY; | |
3299 | } | |
3300 | ||
aa653a68 CW |
3301 | if (i915_gem_valid_gtt_space(vma, cache_level)) |
3302 | continue; | |
3303 | ||
3304 | ret = i915_vma_unbind(vma); | |
3305 | if (ret) | |
3306 | return ret; | |
3307 | ||
3308 | /* As unbinding may affect other elements in the | |
3309 | * obj->vma_list (due to side-effects from retiring | |
3310 | * an active vma), play safe and restart the iterator. | |
3311 | */ | |
3312 | goto restart; | |
42d6ab48 CW |
3313 | } |
3314 | ||
ef55f92a CW |
3315 | /* We can reuse the existing drm_mm nodes but need to change the |
3316 | * cache-level on the PTE. We could simply unbind them all and | |
3317 | * rebind with the correct cache-level on next use. However since | |
3318 | * we already have a valid slot, dma mapping, pages etc, we may as | |
3319 | * rewrite the PTE in the belief that doing so tramples upon less | |
3320 | * state and so involves less work. | |
3321 | */ | |
15717de2 | 3322 | if (obj->bind_count) { |
ef55f92a CW |
3323 | /* Before we change the PTE, the GPU must not be accessing it. |
3324 | * If we wait upon the object, we know that all the bound | |
3325 | * VMA are no longer active. | |
3326 | */ | |
2e2f351d | 3327 | ret = i915_gem_object_wait_rendering(obj, false); |
e4ffd173 CW |
3328 | if (ret) |
3329 | return ret; | |
3330 | ||
aa653a68 | 3331 | if (!HAS_LLC(obj->base.dev) && cache_level != I915_CACHE_NONE) { |
ef55f92a CW |
3332 | /* Access to snoopable pages through the GTT is |
3333 | * incoherent and on some machines causes a hard | |
3334 | * lockup. Relinquish the CPU mmaping to force | |
3335 | * userspace to refault in the pages and we can | |
3336 | * then double check if the GTT mapping is still | |
3337 | * valid for that pointer access. | |
3338 | */ | |
3339 | i915_gem_release_mmap(obj); | |
3340 | ||
3341 | /* As we no longer need a fence for GTT access, | |
3342 | * we can relinquish it now (and so prevent having | |
3343 | * to steal a fence from someone else on the next | |
3344 | * fence request). Note GPU activity would have | |
3345 | * dropped the fence as all snoopable access is | |
3346 | * supposed to be linear. | |
3347 | */ | |
e4ffd173 CW |
3348 | ret = i915_gem_object_put_fence(obj); |
3349 | if (ret) | |
3350 | return ret; | |
ef55f92a CW |
3351 | } else { |
3352 | /* We either have incoherent backing store and | |
3353 | * so no GTT access or the architecture is fully | |
3354 | * coherent. In such cases, existing GTT mmaps | |
3355 | * ignore the cache bit in the PTE and we can | |
3356 | * rewrite it without confusing the GPU or having | |
3357 | * to force userspace to fault back in its mmaps. | |
3358 | */ | |
e4ffd173 CW |
3359 | } |
3360 | ||
1c7f4bca | 3361 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
ef55f92a CW |
3362 | if (!drm_mm_node_allocated(&vma->node)) |
3363 | continue; | |
3364 | ||
3365 | ret = i915_vma_bind(vma, cache_level, PIN_UPDATE); | |
3366 | if (ret) | |
3367 | return ret; | |
3368 | } | |
e4ffd173 CW |
3369 | } |
3370 | ||
1c7f4bca | 3371 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
2c22569b CW |
3372 | vma->node.color = cache_level; |
3373 | obj->cache_level = cache_level; | |
3374 | ||
ed75a55b | 3375 | out: |
ef55f92a CW |
3376 | /* Flush the dirty CPU caches to the backing storage so that the |
3377 | * object is now coherent at its new cache level (with respect | |
3378 | * to the access domain). | |
3379 | */ | |
b50a5371 | 3380 | if (obj->cache_dirty && cpu_write_needs_clflush(obj)) { |
0f71979a | 3381 | if (i915_gem_clflush_object(obj, true)) |
c033666a | 3382 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
e4ffd173 CW |
3383 | } |
3384 | ||
e4ffd173 CW |
3385 | return 0; |
3386 | } | |
3387 | ||
199adf40 BW |
3388 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3389 | struct drm_file *file) | |
e6994aee | 3390 | { |
199adf40 | 3391 | struct drm_i915_gem_caching *args = data; |
e6994aee | 3392 | struct drm_i915_gem_object *obj; |
e6994aee | 3393 | |
03ac0642 CW |
3394 | obj = i915_gem_object_lookup(file, args->handle); |
3395 | if (!obj) | |
432be69d | 3396 | return -ENOENT; |
e6994aee | 3397 | |
651d794f CW |
3398 | switch (obj->cache_level) { |
3399 | case I915_CACHE_LLC: | |
3400 | case I915_CACHE_L3_LLC: | |
3401 | args->caching = I915_CACHING_CACHED; | |
3402 | break; | |
3403 | ||
4257d3ba CW |
3404 | case I915_CACHE_WT: |
3405 | args->caching = I915_CACHING_DISPLAY; | |
3406 | break; | |
3407 | ||
651d794f CW |
3408 | default: |
3409 | args->caching = I915_CACHING_NONE; | |
3410 | break; | |
3411 | } | |
e6994aee | 3412 | |
34911fd3 | 3413 | i915_gem_object_put_unlocked(obj); |
432be69d | 3414 | return 0; |
e6994aee CW |
3415 | } |
3416 | ||
199adf40 BW |
3417 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3418 | struct drm_file *file) | |
e6994aee | 3419 | { |
fac5e23e | 3420 | struct drm_i915_private *dev_priv = to_i915(dev); |
199adf40 | 3421 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3422 | struct drm_i915_gem_object *obj; |
3423 | enum i915_cache_level level; | |
3424 | int ret; | |
3425 | ||
199adf40 BW |
3426 | switch (args->caching) { |
3427 | case I915_CACHING_NONE: | |
e6994aee CW |
3428 | level = I915_CACHE_NONE; |
3429 | break; | |
199adf40 | 3430 | case I915_CACHING_CACHED: |
e5756c10 ID |
3431 | /* |
3432 | * Due to a HW issue on BXT A stepping, GPU stores via a | |
3433 | * snooped mapping may leave stale data in a corresponding CPU | |
3434 | * cacheline, whereas normally such cachelines would get | |
3435 | * invalidated. | |
3436 | */ | |
ca377809 | 3437 | if (!HAS_LLC(dev) && !HAS_SNOOP(dev)) |
e5756c10 ID |
3438 | return -ENODEV; |
3439 | ||
e6994aee CW |
3440 | level = I915_CACHE_LLC; |
3441 | break; | |
4257d3ba CW |
3442 | case I915_CACHING_DISPLAY: |
3443 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; | |
3444 | break; | |
e6994aee CW |
3445 | default: |
3446 | return -EINVAL; | |
3447 | } | |
3448 | ||
fd0fe6ac ID |
3449 | intel_runtime_pm_get(dev_priv); |
3450 | ||
3bc2913e BW |
3451 | ret = i915_mutex_lock_interruptible(dev); |
3452 | if (ret) | |
fd0fe6ac | 3453 | goto rpm_put; |
3bc2913e | 3454 | |
03ac0642 CW |
3455 | obj = i915_gem_object_lookup(file, args->handle); |
3456 | if (!obj) { | |
e6994aee CW |
3457 | ret = -ENOENT; |
3458 | goto unlock; | |
3459 | } | |
3460 | ||
3461 | ret = i915_gem_object_set_cache_level(obj, level); | |
3462 | ||
f8c417cd | 3463 | i915_gem_object_put(obj); |
e6994aee CW |
3464 | unlock: |
3465 | mutex_unlock(&dev->struct_mutex); | |
fd0fe6ac ID |
3466 | rpm_put: |
3467 | intel_runtime_pm_put(dev_priv); | |
3468 | ||
e6994aee CW |
3469 | return ret; |
3470 | } | |
3471 | ||
b9241ea3 | 3472 | /* |
2da3b9b9 CW |
3473 | * Prepare buffer for display plane (scanout, cursors, etc). |
3474 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3475 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3476 | */ |
3477 | int | |
2da3b9b9 CW |
3478 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3479 | u32 alignment, | |
e6617330 | 3480 | const struct i915_ggtt_view *view) |
b9241ea3 | 3481 | { |
2da3b9b9 | 3482 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3483 | int ret; |
3484 | ||
cc98b413 CW |
3485 | /* Mark the pin_display early so that we account for the |
3486 | * display coherency whilst setting up the cache domains. | |
3487 | */ | |
8a0c39b1 | 3488 | obj->pin_display++; |
cc98b413 | 3489 | |
a7ef0640 EA |
3490 | /* The display engine is not coherent with the LLC cache on gen6. As |
3491 | * a result, we make sure that the pinning that is about to occur is | |
3492 | * done with uncached PTEs. This is lowest common denominator for all | |
3493 | * chipsets. | |
3494 | * | |
3495 | * However for gen6+, we could do better by using the GFDT bit instead | |
3496 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3497 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3498 | */ | |
651d794f CW |
3499 | ret = i915_gem_object_set_cache_level(obj, |
3500 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); | |
a7ef0640 | 3501 | if (ret) |
cc98b413 | 3502 | goto err_unpin_display; |
a7ef0640 | 3503 | |
2da3b9b9 CW |
3504 | /* As the user may map the buffer once pinned in the display plane |
3505 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3506 | * always use map_and_fenceable for all scanout buffers. | |
3507 | */ | |
91b2db6f | 3508 | ret = i915_gem_object_ggtt_pin(obj, view, 0, alignment, |
50470bb0 TU |
3509 | view->type == I915_GGTT_VIEW_NORMAL ? |
3510 | PIN_MAPPABLE : 0); | |
2da3b9b9 | 3511 | if (ret) |
cc98b413 | 3512 | goto err_unpin_display; |
2da3b9b9 | 3513 | |
e62b59e4 | 3514 | i915_gem_object_flush_cpu_write_domain(obj); |
b118c1e3 | 3515 | |
2da3b9b9 | 3516 | old_write_domain = obj->base.write_domain; |
05394f39 | 3517 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3518 | |
3519 | /* It should now be out of any other write domains, and we can update | |
3520 | * the domain values for our changes. | |
3521 | */ | |
e5f1d962 | 3522 | obj->base.write_domain = 0; |
05394f39 | 3523 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3524 | |
3525 | trace_i915_gem_object_change_domain(obj, | |
3526 | old_read_domains, | |
2da3b9b9 | 3527 | old_write_domain); |
b9241ea3 ZW |
3528 | |
3529 | return 0; | |
cc98b413 CW |
3530 | |
3531 | err_unpin_display: | |
8a0c39b1 | 3532 | obj->pin_display--; |
cc98b413 CW |
3533 | return ret; |
3534 | } | |
3535 | ||
3536 | void | |
e6617330 TU |
3537 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, |
3538 | const struct i915_ggtt_view *view) | |
cc98b413 | 3539 | { |
8a0c39b1 TU |
3540 | if (WARN_ON(obj->pin_display == 0)) |
3541 | return; | |
3542 | ||
e6617330 TU |
3543 | i915_gem_object_ggtt_unpin_view(obj, view); |
3544 | ||
8a0c39b1 | 3545 | obj->pin_display--; |
b9241ea3 ZW |
3546 | } |
3547 | ||
e47c68e9 EA |
3548 | /** |
3549 | * Moves a single object to the CPU read, and possibly write domain. | |
14bb2c11 TU |
3550 | * @obj: object to act on |
3551 | * @write: requesting write or read-only access | |
e47c68e9 EA |
3552 | * |
3553 | * This function returns when the move is complete, including waiting on | |
3554 | * flushes to occur. | |
3555 | */ | |
dabdfe02 | 3556 | int |
919926ae | 3557 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3558 | { |
1c5d22f7 | 3559 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3560 | int ret; |
3561 | ||
0201f1ec | 3562 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3563 | if (ret) |
3564 | return ret; | |
3565 | ||
c13d87ea CW |
3566 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3567 | return 0; | |
3568 | ||
e47c68e9 | 3569 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3570 | |
05394f39 CW |
3571 | old_write_domain = obj->base.write_domain; |
3572 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3573 | |
e47c68e9 | 3574 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3575 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 3576 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 3577 | |
05394f39 | 3578 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3579 | } |
3580 | ||
3581 | /* It should now be out of any other write domains, and we can update | |
3582 | * the domain values for our changes. | |
3583 | */ | |
05394f39 | 3584 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3585 | |
3586 | /* If we're writing through the CPU, then the GPU read domains will | |
3587 | * need to be invalidated at next use. | |
3588 | */ | |
3589 | if (write) { | |
05394f39 CW |
3590 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3591 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3592 | } |
2ef7eeaa | 3593 | |
1c5d22f7 CW |
3594 | trace_i915_gem_object_change_domain(obj, |
3595 | old_read_domains, | |
3596 | old_write_domain); | |
3597 | ||
2ef7eeaa EA |
3598 | return 0; |
3599 | } | |
3600 | ||
673a394b EA |
3601 | /* Throttle our rendering by waiting until the ring has completed our requests |
3602 | * emitted over 20 msec ago. | |
3603 | * | |
b962442e EA |
3604 | * Note that if we were to use the current jiffies each time around the loop, |
3605 | * we wouldn't escape the function with any frames outstanding if the time to | |
3606 | * render a frame was over 20ms. | |
3607 | * | |
673a394b EA |
3608 | * This should get us reasonable parallelism between CPU and GPU but also |
3609 | * relatively low latency when blocking on a particular request to finish. | |
3610 | */ | |
40a5f0de | 3611 | static int |
f787a5f5 | 3612 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3613 | { |
fac5e23e | 3614 | struct drm_i915_private *dev_priv = to_i915(dev); |
f787a5f5 | 3615 | struct drm_i915_file_private *file_priv = file->driver_priv; |
d0bc54f2 | 3616 | unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES; |
54fb2411 | 3617 | struct drm_i915_gem_request *request, *target = NULL; |
f787a5f5 | 3618 | int ret; |
93533c29 | 3619 | |
308887aa DV |
3620 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
3621 | if (ret) | |
3622 | return ret; | |
3623 | ||
f4457ae7 CW |
3624 | /* ABI: return -EIO if already wedged */ |
3625 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
3626 | return -EIO; | |
e110e8d6 | 3627 | |
1c25595f | 3628 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3629 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3630 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3631 | break; | |
40a5f0de | 3632 | |
fcfa423c JH |
3633 | /* |
3634 | * Note that the request might not have been submitted yet. | |
3635 | * In which case emitted_jiffies will be zero. | |
3636 | */ | |
3637 | if (!request->emitted_jiffies) | |
3638 | continue; | |
3639 | ||
54fb2411 | 3640 | target = request; |
b962442e | 3641 | } |
ff865885 | 3642 | if (target) |
e8a261ea | 3643 | i915_gem_request_get(target); |
1c25595f | 3644 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3645 | |
54fb2411 | 3646 | if (target == NULL) |
f787a5f5 | 3647 | return 0; |
2bc43b5c | 3648 | |
776f3236 | 3649 | ret = i915_wait_request(target, true, NULL, NULL); |
e8a261ea | 3650 | i915_gem_request_put(target); |
ff865885 | 3651 | |
40a5f0de EA |
3652 | return ret; |
3653 | } | |
3654 | ||
d23db88c | 3655 | static bool |
91b2db6f | 3656 | i915_vma_misplaced(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) |
d23db88c CW |
3657 | { |
3658 | struct drm_i915_gem_object *obj = vma->obj; | |
3659 | ||
59bfa124 CW |
3660 | if (!drm_mm_node_allocated(&vma->node)) |
3661 | return false; | |
3662 | ||
91b2db6f CW |
3663 | if (vma->node.size < size) |
3664 | return true; | |
3665 | ||
3666 | if (alignment && vma->node.start & (alignment - 1)) | |
d23db88c CW |
3667 | return true; |
3668 | ||
3669 | if (flags & PIN_MAPPABLE && !obj->map_and_fenceable) | |
3670 | return true; | |
3671 | ||
3672 | if (flags & PIN_OFFSET_BIAS && | |
3673 | vma->node.start < (flags & PIN_OFFSET_MASK)) | |
3674 | return true; | |
3675 | ||
506a8e87 CW |
3676 | if (flags & PIN_OFFSET_FIXED && |
3677 | vma->node.start != (flags & PIN_OFFSET_MASK)) | |
3678 | return true; | |
3679 | ||
d23db88c CW |
3680 | return false; |
3681 | } | |
3682 | ||
d0710abb CW |
3683 | void __i915_vma_set_map_and_fenceable(struct i915_vma *vma) |
3684 | { | |
3685 | struct drm_i915_gem_object *obj = vma->obj; | |
a9f1481f | 3686 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
d0710abb CW |
3687 | bool mappable, fenceable; |
3688 | u32 fence_size, fence_alignment; | |
3689 | ||
a9f1481f | 3690 | fence_size = i915_gem_get_ggtt_size(dev_priv, |
ad1a7d20 CW |
3691 | obj->base.size, |
3692 | obj->tiling_mode); | |
a9f1481f | 3693 | fence_alignment = i915_gem_get_ggtt_alignment(dev_priv, |
ad1a7d20 CW |
3694 | obj->base.size, |
3695 | obj->tiling_mode, | |
3696 | true); | |
d0710abb CW |
3697 | |
3698 | fenceable = (vma->node.size == fence_size && | |
3699 | (vma->node.start & (fence_alignment - 1)) == 0); | |
3700 | ||
3701 | mappable = (vma->node.start + fence_size <= | |
a9f1481f | 3702 | dev_priv->ggtt.mappable_end); |
d0710abb CW |
3703 | |
3704 | obj->map_and_fenceable = mappable && fenceable; | |
3705 | } | |
3706 | ||
59bfa124 CW |
3707 | int |
3708 | i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) | |
673a394b | 3709 | { |
59bfa124 | 3710 | unsigned int bound = vma->bound; |
673a394b EA |
3711 | int ret; |
3712 | ||
59bfa124 CW |
3713 | GEM_BUG_ON((flags & (PIN_GLOBAL | PIN_USER)) == 0); |
3714 | GEM_BUG_ON((flags & PIN_GLOBAL) && !vma->is_ggtt); | |
d7f46fc4 | 3715 | |
59bfa124 CW |
3716 | if (WARN_ON(i915_vma_pin_count(vma) == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
3717 | return -EBUSY; | |
8ea99c92 | 3718 | |
59bfa124 CW |
3719 | /* Pin early to prevent the shrinker/eviction logic from destroying |
3720 | * our vma as we insert and bind. | |
3721 | */ | |
3722 | __i915_vma_pin(vma); | |
ac0c6b5a | 3723 | |
59bfa124 CW |
3724 | if (!bound) { |
3725 | ret = i915_vma_insert(vma, size, alignment, flags); | |
3726 | if (ret) | |
3727 | goto err; | |
fe14d5f4 | 3728 | } |
74898d7e | 3729 | |
59bfa124 | 3730 | ret = i915_vma_bind(vma, vma->obj->cache_level, flags); |
3b16525c | 3731 | if (ret) |
59bfa124 | 3732 | goto err; |
3b16525c | 3733 | |
59bfa124 | 3734 | if ((bound ^ vma->bound) & GLOBAL_BIND) |
d0710abb | 3735 | __i915_vma_set_map_and_fenceable(vma); |
ef79e17c | 3736 | |
3b16525c | 3737 | GEM_BUG_ON(i915_vma_misplaced(vma, size, alignment, flags)); |
673a394b | 3738 | return 0; |
673a394b | 3739 | |
59bfa124 CW |
3740 | err: |
3741 | __i915_vma_unpin(vma); | |
3742 | return ret; | |
ec7adb6e JL |
3743 | } |
3744 | ||
3745 | int | |
3746 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, | |
3747 | const struct i915_ggtt_view *view, | |
91b2db6f | 3748 | u64 size, |
2ffffd0f CW |
3749 | u64 alignment, |
3750 | u64 flags) | |
ec7adb6e | 3751 | { |
59bfa124 CW |
3752 | struct i915_vma *vma; |
3753 | int ret; | |
72e96d64 | 3754 | |
ade7daa1 | 3755 | BUG_ON(!view); |
ec7adb6e | 3756 | |
59bfa124 CW |
3757 | vma = i915_gem_obj_lookup_or_create_ggtt_vma(obj, view); |
3758 | if (IS_ERR(vma)) | |
3759 | return PTR_ERR(vma); | |
3760 | ||
3761 | if (i915_vma_misplaced(vma, size, alignment, flags)) { | |
3762 | if (flags & PIN_NONBLOCK && | |
3763 | (i915_vma_is_pinned(vma) || i915_vma_is_active(vma))) | |
3764 | return -ENOSPC; | |
3765 | ||
3766 | WARN(i915_vma_is_pinned(vma), | |
3767 | "bo is already pinned in ggtt with incorrect alignment:" | |
3768 | " offset=%08x %08x, req.alignment=%llx, req.map_and_fenceable=%d," | |
3769 | " obj->map_and_fenceable=%d\n", | |
3770 | upper_32_bits(vma->node.start), | |
3771 | lower_32_bits(vma->node.start), | |
3772 | alignment, | |
3773 | !!(flags & PIN_MAPPABLE), | |
3774 | obj->map_and_fenceable); | |
3775 | ret = i915_vma_unbind(vma); | |
3776 | if (ret) | |
3777 | return ret; | |
3778 | } | |
3779 | ||
3780 | return i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL); | |
ec7adb6e JL |
3781 | } |
3782 | ||
673a394b | 3783 | void |
e6617330 TU |
3784 | i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj, |
3785 | const struct i915_ggtt_view *view) | |
673a394b | 3786 | { |
e6617330 | 3787 | struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view); |
673a394b | 3788 | |
20dfbde4 | 3789 | WARN_ON(!i915_vma_is_pinned(vma)); |
9abc4648 | 3790 | WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view)); |
d7f46fc4 | 3791 | |
20dfbde4 | 3792 | __i915_vma_unpin(vma); |
673a394b EA |
3793 | } |
3794 | ||
673a394b EA |
3795 | int |
3796 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3797 | struct drm_file *file) |
673a394b EA |
3798 | { |
3799 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3800 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3801 | int ret; |
3802 | ||
76c1dec1 | 3803 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3804 | if (ret) |
76c1dec1 | 3805 | return ret; |
673a394b | 3806 | |
03ac0642 CW |
3807 | obj = i915_gem_object_lookup(file, args->handle); |
3808 | if (!obj) { | |
1d7cfea1 CW |
3809 | ret = -ENOENT; |
3810 | goto unlock; | |
673a394b | 3811 | } |
d1b851fc | 3812 | |
0be555b6 CW |
3813 | /* Count all active objects as busy, even if they are currently not used |
3814 | * by the gpu. Users of this interface expect objects to eventually | |
21c310f2 | 3815 | * become non-busy without any further actions. |
c4de0a5d | 3816 | */ |
426960be CW |
3817 | args->busy = 0; |
3818 | if (obj->active) { | |
27c01aae | 3819 | struct drm_i915_gem_request *req; |
426960be CW |
3820 | int i; |
3821 | ||
666796da | 3822 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
d72d908b CW |
3823 | req = i915_gem_active_peek(&obj->last_read[i], |
3824 | &obj->base.dev->struct_mutex); | |
426960be | 3825 | if (req) |
4a570db5 | 3826 | args->busy |= 1 << (16 + req->engine->exec_id); |
426960be | 3827 | } |
d72d908b CW |
3828 | req = i915_gem_active_peek(&obj->last_write, |
3829 | &obj->base.dev->struct_mutex); | |
27c01aae CW |
3830 | if (req) |
3831 | args->busy |= req->engine->exec_id; | |
426960be | 3832 | } |
673a394b | 3833 | |
f8c417cd | 3834 | i915_gem_object_put(obj); |
1d7cfea1 | 3835 | unlock: |
673a394b | 3836 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3837 | return ret; |
673a394b EA |
3838 | } |
3839 | ||
3840 | int | |
3841 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3842 | struct drm_file *file_priv) | |
3843 | { | |
0206e353 | 3844 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3845 | } |
3846 | ||
3ef94daa CW |
3847 | int |
3848 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3849 | struct drm_file *file_priv) | |
3850 | { | |
fac5e23e | 3851 | struct drm_i915_private *dev_priv = to_i915(dev); |
3ef94daa | 3852 | struct drm_i915_gem_madvise *args = data; |
05394f39 | 3853 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3854 | int ret; |
3ef94daa CW |
3855 | |
3856 | switch (args->madv) { | |
3857 | case I915_MADV_DONTNEED: | |
3858 | case I915_MADV_WILLNEED: | |
3859 | break; | |
3860 | default: | |
3861 | return -EINVAL; | |
3862 | } | |
3863 | ||
1d7cfea1 CW |
3864 | ret = i915_mutex_lock_interruptible(dev); |
3865 | if (ret) | |
3866 | return ret; | |
3867 | ||
03ac0642 CW |
3868 | obj = i915_gem_object_lookup(file_priv, args->handle); |
3869 | if (!obj) { | |
1d7cfea1 CW |
3870 | ret = -ENOENT; |
3871 | goto unlock; | |
3ef94daa | 3872 | } |
3ef94daa | 3873 | |
d7f46fc4 | 3874 | if (i915_gem_obj_is_pinned(obj)) { |
1d7cfea1 CW |
3875 | ret = -EINVAL; |
3876 | goto out; | |
3ef94daa CW |
3877 | } |
3878 | ||
656bfa3a DV |
3879 | if (obj->pages && |
3880 | obj->tiling_mode != I915_TILING_NONE && | |
3881 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { | |
3882 | if (obj->madv == I915_MADV_WILLNEED) | |
3883 | i915_gem_object_unpin_pages(obj); | |
3884 | if (args->madv == I915_MADV_WILLNEED) | |
3885 | i915_gem_object_pin_pages(obj); | |
3886 | } | |
3887 | ||
05394f39 CW |
3888 | if (obj->madv != __I915_MADV_PURGED) |
3889 | obj->madv = args->madv; | |
3ef94daa | 3890 | |
6c085a72 | 3891 | /* if the object is no longer attached, discard its backing storage */ |
be6a0376 | 3892 | if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL) |
2d7ef395 CW |
3893 | i915_gem_object_truncate(obj); |
3894 | ||
05394f39 | 3895 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 3896 | |
1d7cfea1 | 3897 | out: |
f8c417cd | 3898 | i915_gem_object_put(obj); |
1d7cfea1 | 3899 | unlock: |
3ef94daa | 3900 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3901 | return ret; |
3ef94daa CW |
3902 | } |
3903 | ||
37e680a1 CW |
3904 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
3905 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 3906 | { |
b4716185 CW |
3907 | int i; |
3908 | ||
35c20a60 | 3909 | INIT_LIST_HEAD(&obj->global_list); |
666796da | 3910 | for (i = 0; i < I915_NUM_ENGINES; i++) |
fa545cbf CW |
3911 | init_request_active(&obj->last_read[i], |
3912 | i915_gem_object_retire__read); | |
3913 | init_request_active(&obj->last_write, | |
3914 | i915_gem_object_retire__write); | |
3915 | init_request_active(&obj->last_fence, NULL); | |
b25cb2f8 | 3916 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 3917 | INIT_LIST_HEAD(&obj->vma_list); |
8d9d5744 | 3918 | INIT_LIST_HEAD(&obj->batch_pool_link); |
0327d6ba | 3919 | |
37e680a1 CW |
3920 | obj->ops = ops; |
3921 | ||
0327d6ba CW |
3922 | obj->fence_reg = I915_FENCE_REG_NONE; |
3923 | obj->madv = I915_MADV_WILLNEED; | |
0327d6ba | 3924 | |
f19ec8cb | 3925 | i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size); |
0327d6ba CW |
3926 | } |
3927 | ||
37e680a1 | 3928 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
de472664 | 3929 | .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE, |
37e680a1 CW |
3930 | .get_pages = i915_gem_object_get_pages_gtt, |
3931 | .put_pages = i915_gem_object_put_pages_gtt, | |
3932 | }; | |
3933 | ||
d37cd8a8 | 3934 | struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev, |
05394f39 | 3935 | size_t size) |
ac52bc56 | 3936 | { |
c397b908 | 3937 | struct drm_i915_gem_object *obj; |
5949eac4 | 3938 | struct address_space *mapping; |
1a240d4d | 3939 | gfp_t mask; |
fe3db79b | 3940 | int ret; |
ac52bc56 | 3941 | |
42dcedd4 | 3942 | obj = i915_gem_object_alloc(dev); |
c397b908 | 3943 | if (obj == NULL) |
fe3db79b | 3944 | return ERR_PTR(-ENOMEM); |
673a394b | 3945 | |
fe3db79b CW |
3946 | ret = drm_gem_object_init(dev, &obj->base, size); |
3947 | if (ret) | |
3948 | goto fail; | |
673a394b | 3949 | |
bed1ea95 CW |
3950 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
3951 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
3952 | /* 965gm cannot relocate objects above 4GiB. */ | |
3953 | mask &= ~__GFP_HIGHMEM; | |
3954 | mask |= __GFP_DMA32; | |
3955 | } | |
3956 | ||
496ad9aa | 3957 | mapping = file_inode(obj->base.filp)->i_mapping; |
bed1ea95 | 3958 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 3959 | |
37e680a1 | 3960 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 3961 | |
c397b908 DV |
3962 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3963 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 3964 | |
3d29b842 ED |
3965 | if (HAS_LLC(dev)) { |
3966 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
3967 | * cache) for about a 10% performance improvement |
3968 | * compared to uncached. Graphics requests other than | |
3969 | * display scanout are coherent with the CPU in | |
3970 | * accessing this cache. This means in this mode we | |
3971 | * don't need to clflush on the CPU side, and on the | |
3972 | * GPU side we only need to flush internal caches to | |
3973 | * get data visible to the CPU. | |
3974 | * | |
3975 | * However, we maintain the display planes as UC, and so | |
3976 | * need to rebind when first used as such. | |
3977 | */ | |
3978 | obj->cache_level = I915_CACHE_LLC; | |
3979 | } else | |
3980 | obj->cache_level = I915_CACHE_NONE; | |
3981 | ||
d861e338 DV |
3982 | trace_i915_gem_object_create(obj); |
3983 | ||
05394f39 | 3984 | return obj; |
fe3db79b CW |
3985 | |
3986 | fail: | |
3987 | i915_gem_object_free(obj); | |
3988 | ||
3989 | return ERR_PTR(ret); | |
c397b908 DV |
3990 | } |
3991 | ||
340fbd8c CW |
3992 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
3993 | { | |
3994 | /* If we are the last user of the backing storage (be it shmemfs | |
3995 | * pages or stolen etc), we know that the pages are going to be | |
3996 | * immediately released. In this case, we can then skip copying | |
3997 | * back the contents from the GPU. | |
3998 | */ | |
3999 | ||
4000 | if (obj->madv != I915_MADV_WILLNEED) | |
4001 | return false; | |
4002 | ||
4003 | if (obj->base.filp == NULL) | |
4004 | return true; | |
4005 | ||
4006 | /* At first glance, this looks racy, but then again so would be | |
4007 | * userspace racing mmap against close. However, the first external | |
4008 | * reference to the filp can only be obtained through the | |
4009 | * i915_gem_mmap_ioctl() which safeguards us against the user | |
4010 | * acquiring such a reference whilst we are in the middle of | |
4011 | * freeing the object. | |
4012 | */ | |
4013 | return atomic_long_read(&obj->base.filp->f_count) == 1; | |
4014 | } | |
4015 | ||
1488fc08 | 4016 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 4017 | { |
1488fc08 | 4018 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 4019 | struct drm_device *dev = obj->base.dev; |
fac5e23e | 4020 | struct drm_i915_private *dev_priv = to_i915(dev); |
07fe0b12 | 4021 | struct i915_vma *vma, *next; |
673a394b | 4022 | |
f65c9168 PZ |
4023 | intel_runtime_pm_get(dev_priv); |
4024 | ||
26e12f89 CW |
4025 | trace_i915_gem_object_destroy(obj); |
4026 | ||
b1f788c6 CW |
4027 | /* All file-owned VMA should have been released by this point through |
4028 | * i915_gem_close_object(), or earlier by i915_gem_context_close(). | |
4029 | * However, the object may also be bound into the global GTT (e.g. | |
4030 | * older GPUs without per-process support, or for direct access through | |
4031 | * the GTT either for the user or for scanout). Those VMA still need to | |
4032 | * unbound now. | |
4033 | */ | |
1c7f4bca | 4034 | list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) { |
b1f788c6 CW |
4035 | GEM_BUG_ON(!vma->is_ggtt); |
4036 | GEM_BUG_ON(i915_vma_is_active(vma)); | |
d7f46fc4 | 4037 | vma->pin_count = 0; |
b1f788c6 | 4038 | i915_vma_close(vma); |
1488fc08 | 4039 | } |
15717de2 | 4040 | GEM_BUG_ON(obj->bind_count); |
1488fc08 | 4041 | |
1d64ae71 BW |
4042 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
4043 | * before progressing. */ | |
4044 | if (obj->stolen) | |
4045 | i915_gem_object_unpin_pages(obj); | |
4046 | ||
a071fa00 DV |
4047 | WARN_ON(obj->frontbuffer_bits); |
4048 | ||
656bfa3a DV |
4049 | if (obj->pages && obj->madv == I915_MADV_WILLNEED && |
4050 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES && | |
4051 | obj->tiling_mode != I915_TILING_NONE) | |
4052 | i915_gem_object_unpin_pages(obj); | |
4053 | ||
401c29f6 BW |
4054 | if (WARN_ON(obj->pages_pin_count)) |
4055 | obj->pages_pin_count = 0; | |
340fbd8c | 4056 | if (discard_backing_storage(obj)) |
5537252b | 4057 | obj->madv = I915_MADV_DONTNEED; |
37e680a1 | 4058 | i915_gem_object_put_pages(obj); |
de151cf6 | 4059 | |
9da3da66 CW |
4060 | BUG_ON(obj->pages); |
4061 | ||
2f745ad3 CW |
4062 | if (obj->base.import_attach) |
4063 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 4064 | |
5cc9ed4b CW |
4065 | if (obj->ops->release) |
4066 | obj->ops->release(obj); | |
4067 | ||
05394f39 CW |
4068 | drm_gem_object_release(&obj->base); |
4069 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 4070 | |
05394f39 | 4071 | kfree(obj->bit_17); |
42dcedd4 | 4072 | i915_gem_object_free(obj); |
f65c9168 PZ |
4073 | |
4074 | intel_runtime_pm_put(dev_priv); | |
673a394b EA |
4075 | } |
4076 | ||
ec7adb6e JL |
4077 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
4078 | struct i915_address_space *vm) | |
e656a6cb DV |
4079 | { |
4080 | struct i915_vma *vma; | |
1c7f4bca | 4081 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
1b683729 TU |
4082 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL && |
4083 | vma->vm == vm) | |
e656a6cb | 4084 | return vma; |
ec7adb6e JL |
4085 | } |
4086 | return NULL; | |
4087 | } | |
4088 | ||
4089 | struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj, | |
4090 | const struct i915_ggtt_view *view) | |
4091 | { | |
ec7adb6e | 4092 | struct i915_vma *vma; |
e656a6cb | 4093 | |
598b9ec8 | 4094 | GEM_BUG_ON(!view); |
ec7adb6e | 4095 | |
1c7f4bca | 4096 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
598b9ec8 | 4097 | if (vma->is_ggtt && i915_ggtt_view_equal(&vma->ggtt_view, view)) |
ec7adb6e | 4098 | return vma; |
e656a6cb DV |
4099 | return NULL; |
4100 | } | |
4101 | ||
e3efda49 | 4102 | static void |
117897f4 | 4103 | i915_gem_stop_engines(struct drm_device *dev) |
e3efda49 | 4104 | { |
fac5e23e | 4105 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 4106 | struct intel_engine_cs *engine; |
e3efda49 | 4107 | |
b4ac5afc | 4108 | for_each_engine(engine, dev_priv) |
117897f4 | 4109 | dev_priv->gt.stop_engine(engine); |
e3efda49 CW |
4110 | } |
4111 | ||
29105ccc | 4112 | int |
45c5f202 | 4113 | i915_gem_suspend(struct drm_device *dev) |
29105ccc | 4114 | { |
fac5e23e | 4115 | struct drm_i915_private *dev_priv = to_i915(dev); |
45c5f202 | 4116 | int ret = 0; |
28dfe52a | 4117 | |
54b4f68f CW |
4118 | intel_suspend_gt_powersave(dev_priv); |
4119 | ||
45c5f202 | 4120 | mutex_lock(&dev->struct_mutex); |
5ab57c70 CW |
4121 | |
4122 | /* We have to flush all the executing contexts to main memory so | |
4123 | * that they can saved in the hibernation image. To ensure the last | |
4124 | * context image is coherent, we have to switch away from it. That | |
4125 | * leaves the dev_priv->kernel_context still active when | |
4126 | * we actually suspend, and its image in memory may not match the GPU | |
4127 | * state. Fortunately, the kernel_context is disposable and we do | |
4128 | * not rely on its state. | |
4129 | */ | |
4130 | ret = i915_gem_switch_to_kernel_context(dev_priv); | |
4131 | if (ret) | |
4132 | goto err; | |
4133 | ||
6e5a5beb | 4134 | ret = i915_gem_wait_for_idle(dev_priv); |
f7403347 | 4135 | if (ret) |
45c5f202 | 4136 | goto err; |
f7403347 | 4137 | |
c033666a | 4138 | i915_gem_retire_requests(dev_priv); |
673a394b | 4139 | |
5ab57c70 CW |
4140 | /* Note that rather than stopping the engines, all we have to do |
4141 | * is assert that every RING_HEAD == RING_TAIL (all execution complete) | |
4142 | * and similar for all logical context images (to ensure they are | |
4143 | * all ready for hibernation). | |
4144 | */ | |
117897f4 | 4145 | i915_gem_stop_engines(dev); |
b2e862d0 | 4146 | i915_gem_context_lost(dev_priv); |
45c5f202 CW |
4147 | mutex_unlock(&dev->struct_mutex); |
4148 | ||
737b1506 | 4149 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
67d97da3 CW |
4150 | cancel_delayed_work_sync(&dev_priv->gt.retire_work); |
4151 | flush_delayed_work(&dev_priv->gt.idle_work); | |
29105ccc | 4152 | |
bdcf120b CW |
4153 | /* Assert that we sucessfully flushed all the work and |
4154 | * reset the GPU back to its idle, low power state. | |
4155 | */ | |
67d97da3 | 4156 | WARN_ON(dev_priv->gt.awake); |
bdcf120b | 4157 | |
673a394b | 4158 | return 0; |
45c5f202 CW |
4159 | |
4160 | err: | |
4161 | mutex_unlock(&dev->struct_mutex); | |
4162 | return ret; | |
673a394b EA |
4163 | } |
4164 | ||
5ab57c70 CW |
4165 | void i915_gem_resume(struct drm_device *dev) |
4166 | { | |
4167 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4168 | ||
4169 | mutex_lock(&dev->struct_mutex); | |
4170 | i915_gem_restore_gtt_mappings(dev); | |
4171 | ||
4172 | /* As we didn't flush the kernel context before suspend, we cannot | |
4173 | * guarantee that the context image is complete. So let's just reset | |
4174 | * it and start again. | |
4175 | */ | |
4176 | if (i915.enable_execlists) | |
4177 | intel_lr_context_reset(dev_priv, dev_priv->kernel_context); | |
4178 | ||
4179 | mutex_unlock(&dev->struct_mutex); | |
4180 | } | |
4181 | ||
f691e2f4 DV |
4182 | void i915_gem_init_swizzling(struct drm_device *dev) |
4183 | { | |
fac5e23e | 4184 | struct drm_i915_private *dev_priv = to_i915(dev); |
f691e2f4 | 4185 | |
11782b02 | 4186 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
4187 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4188 | return; | |
4189 | ||
4190 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4191 | DISP_TILE_SURFACE_SWIZZLING); | |
4192 | ||
11782b02 DV |
4193 | if (IS_GEN5(dev)) |
4194 | return; | |
4195 | ||
f691e2f4 DV |
4196 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4197 | if (IS_GEN6(dev)) | |
6b26c86d | 4198 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 4199 | else if (IS_GEN7(dev)) |
6b26c86d | 4200 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
31a5336e BW |
4201 | else if (IS_GEN8(dev)) |
4202 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); | |
8782e26c BW |
4203 | else |
4204 | BUG(); | |
f691e2f4 | 4205 | } |
e21af88d | 4206 | |
81e7f200 VS |
4207 | static void init_unused_ring(struct drm_device *dev, u32 base) |
4208 | { | |
fac5e23e | 4209 | struct drm_i915_private *dev_priv = to_i915(dev); |
81e7f200 VS |
4210 | |
4211 | I915_WRITE(RING_CTL(base), 0); | |
4212 | I915_WRITE(RING_HEAD(base), 0); | |
4213 | I915_WRITE(RING_TAIL(base), 0); | |
4214 | I915_WRITE(RING_START(base), 0); | |
4215 | } | |
4216 | ||
4217 | static void init_unused_rings(struct drm_device *dev) | |
4218 | { | |
4219 | if (IS_I830(dev)) { | |
4220 | init_unused_ring(dev, PRB1_BASE); | |
4221 | init_unused_ring(dev, SRB0_BASE); | |
4222 | init_unused_ring(dev, SRB1_BASE); | |
4223 | init_unused_ring(dev, SRB2_BASE); | |
4224 | init_unused_ring(dev, SRB3_BASE); | |
4225 | } else if (IS_GEN2(dev)) { | |
4226 | init_unused_ring(dev, SRB0_BASE); | |
4227 | init_unused_ring(dev, SRB1_BASE); | |
4228 | } else if (IS_GEN3(dev)) { | |
4229 | init_unused_ring(dev, PRB1_BASE); | |
4230 | init_unused_ring(dev, PRB2_BASE); | |
4231 | } | |
4232 | } | |
4233 | ||
4fc7c971 BW |
4234 | int |
4235 | i915_gem_init_hw(struct drm_device *dev) | |
4236 | { | |
fac5e23e | 4237 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 4238 | struct intel_engine_cs *engine; |
d200cda6 | 4239 | int ret; |
4fc7c971 | 4240 | |
5e4f5189 CW |
4241 | /* Double layer security blanket, see i915_gem_init() */ |
4242 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4243 | ||
3accaf7e | 4244 | if (HAS_EDRAM(dev) && INTEL_GEN(dev_priv) < 9) |
05e21cc4 | 4245 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4246 | |
0bf21347 VS |
4247 | if (IS_HASWELL(dev)) |
4248 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? | |
4249 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); | |
9435373e | 4250 | |
88a2b2a3 | 4251 | if (HAS_PCH_NOP(dev)) { |
6ba844b0 DV |
4252 | if (IS_IVYBRIDGE(dev)) { |
4253 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
4254 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4255 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4256 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
4257 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); | |
4258 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
4259 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
4260 | } | |
88a2b2a3 BW |
4261 | } |
4262 | ||
4fc7c971 BW |
4263 | i915_gem_init_swizzling(dev); |
4264 | ||
d5abdfda DV |
4265 | /* |
4266 | * At least 830 can leave some of the unused rings | |
4267 | * "active" (ie. head != tail) after resume which | |
4268 | * will prevent c3 entry. Makes sure all unused rings | |
4269 | * are totally idle. | |
4270 | */ | |
4271 | init_unused_rings(dev); | |
4272 | ||
ed54c1a1 | 4273 | BUG_ON(!dev_priv->kernel_context); |
90638cc1 | 4274 | |
4ad2fd88 JH |
4275 | ret = i915_ppgtt_init_hw(dev); |
4276 | if (ret) { | |
4277 | DRM_ERROR("PPGTT enable HW failed %d\n", ret); | |
4278 | goto out; | |
4279 | } | |
4280 | ||
4281 | /* Need to do basic initialisation of all rings first: */ | |
b4ac5afc | 4282 | for_each_engine(engine, dev_priv) { |
e2f80391 | 4283 | ret = engine->init_hw(engine); |
35a57ffb | 4284 | if (ret) |
5e4f5189 | 4285 | goto out; |
35a57ffb | 4286 | } |
99433931 | 4287 | |
0ccdacf6 PA |
4288 | intel_mocs_init_l3cc_table(dev); |
4289 | ||
33a732f4 | 4290 | /* We can't enable contexts until all firmware is loaded */ |
e556f7c1 DG |
4291 | ret = intel_guc_setup(dev); |
4292 | if (ret) | |
4293 | goto out; | |
33a732f4 | 4294 | |
5e4f5189 CW |
4295 | out: |
4296 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2fa48d8d | 4297 | return ret; |
8187a2b7 ZN |
4298 | } |
4299 | ||
39df9190 CW |
4300 | bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value) |
4301 | { | |
4302 | if (INTEL_INFO(dev_priv)->gen < 6) | |
4303 | return false; | |
4304 | ||
4305 | /* TODO: make semaphores and Execlists play nicely together */ | |
4306 | if (i915.enable_execlists) | |
4307 | return false; | |
4308 | ||
4309 | if (value >= 0) | |
4310 | return value; | |
4311 | ||
4312 | #ifdef CONFIG_INTEL_IOMMU | |
4313 | /* Enable semaphores on SNB when IO remapping is off */ | |
4314 | if (INTEL_INFO(dev_priv)->gen == 6 && intel_iommu_gfx_mapped) | |
4315 | return false; | |
4316 | #endif | |
4317 | ||
4318 | return true; | |
4319 | } | |
4320 | ||
1070a42b CW |
4321 | int i915_gem_init(struct drm_device *dev) |
4322 | { | |
fac5e23e | 4323 | struct drm_i915_private *dev_priv = to_i915(dev); |
1070a42b CW |
4324 | int ret; |
4325 | ||
1070a42b | 4326 | mutex_lock(&dev->struct_mutex); |
d62b4892 | 4327 | |
a83014d3 | 4328 | if (!i915.enable_execlists) { |
7e37f889 CW |
4329 | dev_priv->gt.cleanup_engine = intel_engine_cleanup; |
4330 | dev_priv->gt.stop_engine = intel_engine_stop; | |
454afebd | 4331 | } else { |
117897f4 TU |
4332 | dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup; |
4333 | dev_priv->gt.stop_engine = intel_logical_ring_stop; | |
a83014d3 OM |
4334 | } |
4335 | ||
5e4f5189 CW |
4336 | /* This is just a security blanket to placate dragons. |
4337 | * On some systems, we very sporadically observe that the first TLBs | |
4338 | * used by the CS may be stale, despite us poking the TLB reset. If | |
4339 | * we hold the forcewake during initialisation these problems | |
4340 | * just magically go away. | |
4341 | */ | |
4342 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4343 | ||
72778cb2 | 4344 | i915_gem_init_userptr(dev_priv); |
f6b9d5ca CW |
4345 | |
4346 | ret = i915_gem_init_ggtt(dev_priv); | |
4347 | if (ret) | |
4348 | goto out_unlock; | |
d62b4892 | 4349 | |
2fa48d8d | 4350 | ret = i915_gem_context_init(dev); |
7bcc3777 JN |
4351 | if (ret) |
4352 | goto out_unlock; | |
2fa48d8d | 4353 | |
8b3e2d36 | 4354 | ret = intel_engines_init(dev); |
35a57ffb | 4355 | if (ret) |
7bcc3777 | 4356 | goto out_unlock; |
2fa48d8d | 4357 | |
1070a42b | 4358 | ret = i915_gem_init_hw(dev); |
60990320 | 4359 | if (ret == -EIO) { |
7e21d648 | 4360 | /* Allow engine initialisation to fail by marking the GPU as |
60990320 CW |
4361 | * wedged. But we only want to do this where the GPU is angry, |
4362 | * for all other failure, such as an allocation failure, bail. | |
4363 | */ | |
4364 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); | |
805de8f4 | 4365 | atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter); |
60990320 | 4366 | ret = 0; |
1070a42b | 4367 | } |
7bcc3777 JN |
4368 | |
4369 | out_unlock: | |
5e4f5189 | 4370 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
60990320 | 4371 | mutex_unlock(&dev->struct_mutex); |
1070a42b | 4372 | |
60990320 | 4373 | return ret; |
1070a42b CW |
4374 | } |
4375 | ||
8187a2b7 | 4376 | void |
117897f4 | 4377 | i915_gem_cleanup_engines(struct drm_device *dev) |
8187a2b7 | 4378 | { |
fac5e23e | 4379 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 4380 | struct intel_engine_cs *engine; |
8187a2b7 | 4381 | |
b4ac5afc | 4382 | for_each_engine(engine, dev_priv) |
117897f4 | 4383 | dev_priv->gt.cleanup_engine(engine); |
8187a2b7 ZN |
4384 | } |
4385 | ||
64193406 | 4386 | static void |
666796da | 4387 | init_engine_lists(struct intel_engine_cs *engine) |
64193406 | 4388 | { |
0bc40be8 | 4389 | INIT_LIST_HEAD(&engine->request_list); |
64193406 CW |
4390 | } |
4391 | ||
40ae4e16 ID |
4392 | void |
4393 | i915_gem_load_init_fences(struct drm_i915_private *dev_priv) | |
4394 | { | |
91c8a326 | 4395 | struct drm_device *dev = &dev_priv->drm; |
40ae4e16 ID |
4396 | |
4397 | if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) && | |
4398 | !IS_CHERRYVIEW(dev_priv)) | |
4399 | dev_priv->num_fence_regs = 32; | |
4400 | else if (INTEL_INFO(dev_priv)->gen >= 4 || IS_I945G(dev_priv) || | |
4401 | IS_I945GM(dev_priv) || IS_G33(dev_priv)) | |
4402 | dev_priv->num_fence_regs = 16; | |
4403 | else | |
4404 | dev_priv->num_fence_regs = 8; | |
4405 | ||
c033666a | 4406 | if (intel_vgpu_active(dev_priv)) |
40ae4e16 ID |
4407 | dev_priv->num_fence_regs = |
4408 | I915_READ(vgtif_reg(avail_rs.fence_num)); | |
4409 | ||
4410 | /* Initialize fence registers to zero */ | |
4411 | i915_gem_restore_fences(dev); | |
4412 | ||
4413 | i915_gem_detect_bit_6_swizzle(dev); | |
4414 | } | |
4415 | ||
673a394b | 4416 | void |
d64aa096 | 4417 | i915_gem_load_init(struct drm_device *dev) |
673a394b | 4418 | { |
fac5e23e | 4419 | struct drm_i915_private *dev_priv = to_i915(dev); |
42dcedd4 CW |
4420 | int i; |
4421 | ||
efab6d8d | 4422 | dev_priv->objects = |
42dcedd4 CW |
4423 | kmem_cache_create("i915_gem_object", |
4424 | sizeof(struct drm_i915_gem_object), 0, | |
4425 | SLAB_HWCACHE_ALIGN, | |
4426 | NULL); | |
e20d2ab7 CW |
4427 | dev_priv->vmas = |
4428 | kmem_cache_create("i915_gem_vma", | |
4429 | sizeof(struct i915_vma), 0, | |
4430 | SLAB_HWCACHE_ALIGN, | |
4431 | NULL); | |
efab6d8d CW |
4432 | dev_priv->requests = |
4433 | kmem_cache_create("i915_gem_request", | |
4434 | sizeof(struct drm_i915_gem_request), 0, | |
4435 | SLAB_HWCACHE_ALIGN, | |
4436 | NULL); | |
673a394b | 4437 | |
a33afea5 | 4438 | INIT_LIST_HEAD(&dev_priv->context_list); |
6c085a72 CW |
4439 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4440 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4441 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
666796da TU |
4442 | for (i = 0; i < I915_NUM_ENGINES; i++) |
4443 | init_engine_lists(&dev_priv->engine[i]); | |
4b9de737 | 4444 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4445 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
67d97da3 | 4446 | INIT_DELAYED_WORK(&dev_priv->gt.retire_work, |
673a394b | 4447 | i915_gem_retire_work_handler); |
67d97da3 | 4448 | INIT_DELAYED_WORK(&dev_priv->gt.idle_work, |
b29c19b6 | 4449 | i915_gem_idle_work_handler); |
1f15b76f | 4450 | init_waitqueue_head(&dev_priv->gpu_error.wait_queue); |
1f83fee0 | 4451 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4452 | |
72bfa19c CW |
4453 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4454 | ||
19b2dbde | 4455 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
10ed13e4 | 4456 | |
6b95a207 | 4457 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4458 | |
ce453d81 CW |
4459 | dev_priv->mm.interruptible = true; |
4460 | ||
f99d7069 | 4461 | mutex_init(&dev_priv->fb_tracking.lock); |
673a394b | 4462 | } |
71acb5eb | 4463 | |
d64aa096 ID |
4464 | void i915_gem_load_cleanup(struct drm_device *dev) |
4465 | { | |
4466 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4467 | ||
4468 | kmem_cache_destroy(dev_priv->requests); | |
4469 | kmem_cache_destroy(dev_priv->vmas); | |
4470 | kmem_cache_destroy(dev_priv->objects); | |
4471 | } | |
4472 | ||
461fb99c CW |
4473 | int i915_gem_freeze_late(struct drm_i915_private *dev_priv) |
4474 | { | |
4475 | struct drm_i915_gem_object *obj; | |
4476 | ||
4477 | /* Called just before we write the hibernation image. | |
4478 | * | |
4479 | * We need to update the domain tracking to reflect that the CPU | |
4480 | * will be accessing all the pages to create and restore from the | |
4481 | * hibernation, and so upon restoration those pages will be in the | |
4482 | * CPU domain. | |
4483 | * | |
4484 | * To make sure the hibernation image contains the latest state, | |
4485 | * we update that state just before writing out the image. | |
4486 | */ | |
4487 | ||
4488 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
4489 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
4490 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
4491 | } | |
4492 | ||
4493 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
4494 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
4495 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
4496 | } | |
4497 | ||
4498 | return 0; | |
4499 | } | |
4500 | ||
f787a5f5 | 4501 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4502 | { |
f787a5f5 | 4503 | struct drm_i915_file_private *file_priv = file->driver_priv; |
15f7bbc7 | 4504 | struct drm_i915_gem_request *request; |
b962442e EA |
4505 | |
4506 | /* Clean up our request list when the client is going away, so that | |
4507 | * later retire_requests won't dereference our soon-to-be-gone | |
4508 | * file_priv. | |
4509 | */ | |
1c25595f | 4510 | spin_lock(&file_priv->mm.lock); |
15f7bbc7 | 4511 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) |
f787a5f5 | 4512 | request->file_priv = NULL; |
1c25595f | 4513 | spin_unlock(&file_priv->mm.lock); |
b29c19b6 | 4514 | |
2e1b8730 | 4515 | if (!list_empty(&file_priv->rps.link)) { |
8d3afd7d | 4516 | spin_lock(&to_i915(dev)->rps.client_lock); |
2e1b8730 | 4517 | list_del(&file_priv->rps.link); |
8d3afd7d | 4518 | spin_unlock(&to_i915(dev)->rps.client_lock); |
1854d5ca | 4519 | } |
b29c19b6 CW |
4520 | } |
4521 | ||
4522 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
4523 | { | |
4524 | struct drm_i915_file_private *file_priv; | |
e422b888 | 4525 | int ret; |
b29c19b6 CW |
4526 | |
4527 | DRM_DEBUG_DRIVER("\n"); | |
4528 | ||
4529 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
4530 | if (!file_priv) | |
4531 | return -ENOMEM; | |
4532 | ||
4533 | file->driver_priv = file_priv; | |
f19ec8cb | 4534 | file_priv->dev_priv = to_i915(dev); |
ab0e7ff9 | 4535 | file_priv->file = file; |
2e1b8730 | 4536 | INIT_LIST_HEAD(&file_priv->rps.link); |
b29c19b6 CW |
4537 | |
4538 | spin_lock_init(&file_priv->mm.lock); | |
4539 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
b29c19b6 | 4540 | |
c80ff16e | 4541 | file_priv->bsd_engine = -1; |
de1add36 | 4542 | |
e422b888 BW |
4543 | ret = i915_gem_context_open(dev, file); |
4544 | if (ret) | |
4545 | kfree(file_priv); | |
b29c19b6 | 4546 | |
e422b888 | 4547 | return ret; |
b29c19b6 CW |
4548 | } |
4549 | ||
b680c37a DV |
4550 | /** |
4551 | * i915_gem_track_fb - update frontbuffer tracking | |
d9072a3e GT |
4552 | * @old: current GEM buffer for the frontbuffer slots |
4553 | * @new: new GEM buffer for the frontbuffer slots | |
4554 | * @frontbuffer_bits: bitmask of frontbuffer slots | |
b680c37a DV |
4555 | * |
4556 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them | |
4557 | * from @old and setting them in @new. Both @old and @new can be NULL. | |
4558 | */ | |
a071fa00 DV |
4559 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
4560 | struct drm_i915_gem_object *new, | |
4561 | unsigned frontbuffer_bits) | |
4562 | { | |
4563 | if (old) { | |
4564 | WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex)); | |
4565 | WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits)); | |
4566 | old->frontbuffer_bits &= ~frontbuffer_bits; | |
4567 | } | |
4568 | ||
4569 | if (new) { | |
4570 | WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex)); | |
4571 | WARN_ON(new->frontbuffer_bits & frontbuffer_bits); | |
4572 | new->frontbuffer_bits |= frontbuffer_bits; | |
4573 | } | |
4574 | } | |
4575 | ||
a70a3148 | 4576 | /* All the new VM stuff */ |
088e0df4 MT |
4577 | u64 i915_gem_obj_offset(struct drm_i915_gem_object *o, |
4578 | struct i915_address_space *vm) | |
a70a3148 | 4579 | { |
fac5e23e | 4580 | struct drm_i915_private *dev_priv = to_i915(o->base.dev); |
a70a3148 BW |
4581 | struct i915_vma *vma; |
4582 | ||
896ab1a5 | 4583 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
a70a3148 | 4584 | |
1c7f4bca | 4585 | list_for_each_entry(vma, &o->vma_list, obj_link) { |
596c5923 | 4586 | if (vma->is_ggtt && |
ec7adb6e JL |
4587 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) |
4588 | continue; | |
4589 | if (vma->vm == vm) | |
a70a3148 | 4590 | return vma->node.start; |
a70a3148 | 4591 | } |
ec7adb6e | 4592 | |
f25748ea DV |
4593 | WARN(1, "%s vma for this object not found.\n", |
4594 | i915_is_ggtt(vm) ? "global" : "ppgtt"); | |
a70a3148 BW |
4595 | return -1; |
4596 | } | |
4597 | ||
088e0df4 MT |
4598 | u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, |
4599 | const struct i915_ggtt_view *view) | |
a70a3148 BW |
4600 | { |
4601 | struct i915_vma *vma; | |
4602 | ||
1c7f4bca | 4603 | list_for_each_entry(vma, &o->vma_list, obj_link) |
8aac2220 | 4604 | if (vma->is_ggtt && i915_ggtt_view_equal(&vma->ggtt_view, view)) |
ec7adb6e JL |
4605 | return vma->node.start; |
4606 | ||
5678ad73 | 4607 | WARN(1, "global vma for this object not found. (view=%u)\n", view->type); |
ec7adb6e JL |
4608 | return -1; |
4609 | } | |
4610 | ||
4611 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
4612 | struct i915_address_space *vm) | |
4613 | { | |
4614 | struct i915_vma *vma; | |
4615 | ||
1c7f4bca | 4616 | list_for_each_entry(vma, &o->vma_list, obj_link) { |
596c5923 | 4617 | if (vma->is_ggtt && |
ec7adb6e JL |
4618 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) |
4619 | continue; | |
4620 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) | |
4621 | return true; | |
4622 | } | |
4623 | ||
4624 | return false; | |
4625 | } | |
4626 | ||
4627 | bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o, | |
9abc4648 | 4628 | const struct i915_ggtt_view *view) |
ec7adb6e | 4629 | { |
ec7adb6e JL |
4630 | struct i915_vma *vma; |
4631 | ||
1c7f4bca | 4632 | list_for_each_entry(vma, &o->vma_list, obj_link) |
ff5ec22d | 4633 | if (vma->is_ggtt && |
9abc4648 | 4634 | i915_ggtt_view_equal(&vma->ggtt_view, view) && |
fe14d5f4 | 4635 | drm_mm_node_allocated(&vma->node)) |
a70a3148 BW |
4636 | return true; |
4637 | ||
4638 | return false; | |
4639 | } | |
4640 | ||
8da32727 | 4641 | unsigned long i915_gem_obj_ggtt_size(struct drm_i915_gem_object *o) |
a70a3148 | 4642 | { |
a70a3148 BW |
4643 | struct i915_vma *vma; |
4644 | ||
8da32727 | 4645 | GEM_BUG_ON(list_empty(&o->vma_list)); |
a70a3148 | 4646 | |
1c7f4bca | 4647 | list_for_each_entry(vma, &o->vma_list, obj_link) { |
596c5923 | 4648 | if (vma->is_ggtt && |
8da32727 | 4649 | vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) |
a70a3148 | 4650 | return vma->node.size; |
ec7adb6e | 4651 | } |
8da32727 | 4652 | |
a70a3148 BW |
4653 | return 0; |
4654 | } | |
4655 | ||
ec7adb6e | 4656 | bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) |
5c2abbea BW |
4657 | { |
4658 | struct i915_vma *vma; | |
1c7f4bca | 4659 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
20dfbde4 | 4660 | if (i915_vma_is_pinned(vma)) |
ec7adb6e | 4661 | return true; |
a6631ae1 | 4662 | |
ec7adb6e | 4663 | return false; |
5c2abbea | 4664 | } |
ea70299d | 4665 | |
033908ae DG |
4666 | /* Like i915_gem_object_get_page(), but mark the returned page dirty */ |
4667 | struct page * | |
4668 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n) | |
4669 | { | |
4670 | struct page *page; | |
4671 | ||
4672 | /* Only default objects have per-page dirty tracking */ | |
b9bcd14a | 4673 | if (WARN_ON(!i915_gem_object_has_struct_page(obj))) |
033908ae DG |
4674 | return NULL; |
4675 | ||
4676 | page = i915_gem_object_get_page(obj, n); | |
4677 | set_page_dirty(page); | |
4678 | return page; | |
4679 | } | |
4680 | ||
ea70299d DG |
4681 | /* Allocate a new GEM object and fill it with the supplied data */ |
4682 | struct drm_i915_gem_object * | |
4683 | i915_gem_object_create_from_data(struct drm_device *dev, | |
4684 | const void *data, size_t size) | |
4685 | { | |
4686 | struct drm_i915_gem_object *obj; | |
4687 | struct sg_table *sg; | |
4688 | size_t bytes; | |
4689 | int ret; | |
4690 | ||
d37cd8a8 | 4691 | obj = i915_gem_object_create(dev, round_up(size, PAGE_SIZE)); |
fe3db79b | 4692 | if (IS_ERR(obj)) |
ea70299d DG |
4693 | return obj; |
4694 | ||
4695 | ret = i915_gem_object_set_to_cpu_domain(obj, true); | |
4696 | if (ret) | |
4697 | goto fail; | |
4698 | ||
4699 | ret = i915_gem_object_get_pages(obj); | |
4700 | if (ret) | |
4701 | goto fail; | |
4702 | ||
4703 | i915_gem_object_pin_pages(obj); | |
4704 | sg = obj->pages; | |
4705 | bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size); | |
9e7d18c0 | 4706 | obj->dirty = 1; /* Backing store is now out of date */ |
ea70299d DG |
4707 | i915_gem_object_unpin_pages(obj); |
4708 | ||
4709 | if (WARN_ON(bytes != size)) { | |
4710 | DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size); | |
4711 | ret = -EFAULT; | |
4712 | goto fail; | |
4713 | } | |
4714 | ||
4715 | return obj; | |
4716 | ||
4717 | fail: | |
f8c417cd | 4718 | i915_gem_object_put(obj); |
ea70299d DG |
4719 | return ERR_PTR(ret); |
4720 | } |