Commit | Line | Data |
---|---|---|
673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5949eac4 | 34 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
673a394b | 36 | #include <linux/swap.h> |
79e53945 | 37 | #include <linux/pci.h> |
1286ff73 | 38 | #include <linux/dma-buf.h> |
673a394b | 39 | |
88241785 | 40 | static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj); |
05394f39 CW |
41 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
42 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); | |
88241785 CW |
43 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
44 | unsigned alignment, | |
45 | bool map_and_fenceable); | |
05394f39 CW |
46 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
47 | struct drm_i915_gem_object *obj, | |
71acb5eb | 48 | struct drm_i915_gem_pwrite *args, |
05394f39 | 49 | struct drm_file *file); |
673a394b | 50 | |
61050808 CW |
51 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
52 | struct drm_i915_gem_object *obj); | |
53 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
54 | struct drm_i915_fence_reg *fence, | |
55 | bool enable); | |
56 | ||
17250b71 | 57 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
1495f230 | 58 | struct shrink_control *sc); |
8c59967c | 59 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
31169714 | 60 | |
61050808 CW |
61 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
62 | { | |
63 | if (obj->tiling_mode) | |
64 | i915_gem_release_mmap(obj); | |
65 | ||
66 | /* As we do not have an associated fence register, we will force | |
67 | * a tiling change if we ever need to acquire one. | |
68 | */ | |
5d82e3e6 | 69 | obj->fence_dirty = false; |
61050808 CW |
70 | obj->fence_reg = I915_FENCE_REG_NONE; |
71 | } | |
72 | ||
73aa808f CW |
73 | /* some bookkeeping */ |
74 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
75 | size_t size) | |
76 | { | |
77 | dev_priv->mm.object_count++; | |
78 | dev_priv->mm.object_memory += size; | |
79 | } | |
80 | ||
81 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
82 | size_t size) | |
83 | { | |
84 | dev_priv->mm.object_count--; | |
85 | dev_priv->mm.object_memory -= size; | |
86 | } | |
87 | ||
21dd3734 CW |
88 | static int |
89 | i915_gem_wait_for_error(struct drm_device *dev) | |
30dbf0c0 CW |
90 | { |
91 | struct drm_i915_private *dev_priv = dev->dev_private; | |
92 | struct completion *x = &dev_priv->error_completion; | |
93 | unsigned long flags; | |
94 | int ret; | |
95 | ||
96 | if (!atomic_read(&dev_priv->mm.wedged)) | |
97 | return 0; | |
98 | ||
0a6759c6 DV |
99 | /* |
100 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
101 | * userspace. If it takes that long something really bad is going on and | |
102 | * we should simply try to bail out and fail as gracefully as possible. | |
103 | */ | |
104 | ret = wait_for_completion_interruptible_timeout(x, 10*HZ); | |
105 | if (ret == 0) { | |
106 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
107 | return -EIO; | |
108 | } else if (ret < 0) { | |
30dbf0c0 | 109 | return ret; |
0a6759c6 | 110 | } |
30dbf0c0 | 111 | |
21dd3734 CW |
112 | if (atomic_read(&dev_priv->mm.wedged)) { |
113 | /* GPU is hung, bump the completion count to account for | |
114 | * the token we just consumed so that we never hit zero and | |
115 | * end up waiting upon a subsequent completion event that | |
116 | * will never happen. | |
117 | */ | |
118 | spin_lock_irqsave(&x->wait.lock, flags); | |
119 | x->done++; | |
120 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
121 | } | |
122 | return 0; | |
30dbf0c0 CW |
123 | } |
124 | ||
54cf91dc | 125 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 126 | { |
76c1dec1 CW |
127 | int ret; |
128 | ||
21dd3734 | 129 | ret = i915_gem_wait_for_error(dev); |
76c1dec1 CW |
130 | if (ret) |
131 | return ret; | |
132 | ||
133 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
134 | if (ret) | |
135 | return ret; | |
136 | ||
23bc5982 | 137 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
138 | return 0; |
139 | } | |
30dbf0c0 | 140 | |
7d1c4804 | 141 | static inline bool |
05394f39 | 142 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 143 | { |
1b50247a | 144 | return !obj->active; |
7d1c4804 CW |
145 | } |
146 | ||
79e53945 JB |
147 | int |
148 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 149 | struct drm_file *file) |
79e53945 JB |
150 | { |
151 | struct drm_i915_gem_init *args = data; | |
2021746e | 152 | |
7bb6fb8d DV |
153 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
154 | return -ENODEV; | |
155 | ||
2021746e CW |
156 | if (args->gtt_start >= args->gtt_end || |
157 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
158 | return -EINVAL; | |
79e53945 | 159 | |
f534bc0b DV |
160 | /* GEM with user mode setting was never supported on ilk and later. */ |
161 | if (INTEL_INFO(dev)->gen >= 5) | |
162 | return -ENODEV; | |
163 | ||
79e53945 | 164 | mutex_lock(&dev->struct_mutex); |
644ec02b DV |
165 | i915_gem_init_global_gtt(dev, args->gtt_start, |
166 | args->gtt_end, args->gtt_end); | |
673a394b EA |
167 | mutex_unlock(&dev->struct_mutex); |
168 | ||
2021746e | 169 | return 0; |
673a394b EA |
170 | } |
171 | ||
5a125c3c EA |
172 | int |
173 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 174 | struct drm_file *file) |
5a125c3c | 175 | { |
73aa808f | 176 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 177 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
178 | struct drm_i915_gem_object *obj; |
179 | size_t pinned; | |
5a125c3c | 180 | |
6299f992 | 181 | pinned = 0; |
73aa808f | 182 | mutex_lock(&dev->struct_mutex); |
1b50247a CW |
183 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) |
184 | if (obj->pin_count) | |
185 | pinned += obj->gtt_space->size; | |
73aa808f | 186 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 187 | |
6299f992 | 188 | args->aper_size = dev_priv->mm.gtt_total; |
0206e353 | 189 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 190 | |
5a125c3c EA |
191 | return 0; |
192 | } | |
193 | ||
ff72145b DA |
194 | static int |
195 | i915_gem_create(struct drm_file *file, | |
196 | struct drm_device *dev, | |
197 | uint64_t size, | |
198 | uint32_t *handle_p) | |
673a394b | 199 | { |
05394f39 | 200 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
201 | int ret; |
202 | u32 handle; | |
673a394b | 203 | |
ff72145b | 204 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
205 | if (size == 0) |
206 | return -EINVAL; | |
673a394b EA |
207 | |
208 | /* Allocate the new object */ | |
ff72145b | 209 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
210 | if (obj == NULL) |
211 | return -ENOMEM; | |
212 | ||
05394f39 | 213 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
1dfd9754 | 214 | if (ret) { |
05394f39 CW |
215 | drm_gem_object_release(&obj->base); |
216 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); | |
202f2fef | 217 | kfree(obj); |
673a394b | 218 | return ret; |
1dfd9754 | 219 | } |
673a394b | 220 | |
202f2fef | 221 | /* drop reference from allocate - handle holds it now */ |
05394f39 | 222 | drm_gem_object_unreference(&obj->base); |
202f2fef CW |
223 | trace_i915_gem_object_create(obj); |
224 | ||
ff72145b | 225 | *handle_p = handle; |
673a394b EA |
226 | return 0; |
227 | } | |
228 | ||
ff72145b DA |
229 | int |
230 | i915_gem_dumb_create(struct drm_file *file, | |
231 | struct drm_device *dev, | |
232 | struct drm_mode_create_dumb *args) | |
233 | { | |
234 | /* have to work out size/pitch and return them */ | |
ed0291fd | 235 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
ff72145b DA |
236 | args->size = args->pitch * args->height; |
237 | return i915_gem_create(file, dev, | |
238 | args->size, &args->handle); | |
239 | } | |
240 | ||
241 | int i915_gem_dumb_destroy(struct drm_file *file, | |
242 | struct drm_device *dev, | |
243 | uint32_t handle) | |
244 | { | |
245 | return drm_gem_handle_delete(file, handle); | |
246 | } | |
247 | ||
248 | /** | |
249 | * Creates a new mm object and returns a handle to it. | |
250 | */ | |
251 | int | |
252 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
253 | struct drm_file *file) | |
254 | { | |
255 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 256 | |
ff72145b DA |
257 | return i915_gem_create(file, dev, |
258 | args->size, &args->handle); | |
259 | } | |
260 | ||
05394f39 | 261 | static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
280b713b | 262 | { |
05394f39 | 263 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
280b713b EA |
264 | |
265 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
05394f39 | 266 | obj->tiling_mode != I915_TILING_NONE; |
280b713b EA |
267 | } |
268 | ||
8461d226 DV |
269 | static inline int |
270 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
271 | const char *gpu_vaddr, int gpu_offset, | |
272 | int length) | |
273 | { | |
274 | int ret, cpu_offset = 0; | |
275 | ||
276 | while (length > 0) { | |
277 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
278 | int this_length = min(cacheline_end - gpu_offset, length); | |
279 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
280 | ||
281 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
282 | gpu_vaddr + swizzled_gpu_offset, | |
283 | this_length); | |
284 | if (ret) | |
285 | return ret + length; | |
286 | ||
287 | cpu_offset += this_length; | |
288 | gpu_offset += this_length; | |
289 | length -= this_length; | |
290 | } | |
291 | ||
292 | return 0; | |
293 | } | |
294 | ||
8c59967c | 295 | static inline int |
4f0c7cfb BW |
296 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
297 | const char __user *cpu_vaddr, | |
8c59967c DV |
298 | int length) |
299 | { | |
300 | int ret, cpu_offset = 0; | |
301 | ||
302 | while (length > 0) { | |
303 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
304 | int this_length = min(cacheline_end - gpu_offset, length); | |
305 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
306 | ||
307 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
308 | cpu_vaddr + cpu_offset, | |
309 | this_length); | |
310 | if (ret) | |
311 | return ret + length; | |
312 | ||
313 | cpu_offset += this_length; | |
314 | gpu_offset += this_length; | |
315 | length -= this_length; | |
316 | } | |
317 | ||
318 | return 0; | |
319 | } | |
320 | ||
d174bd64 DV |
321 | /* Per-page copy function for the shmem pread fastpath. |
322 | * Flushes invalid cachelines before reading the target if | |
323 | * needs_clflush is set. */ | |
eb01459f | 324 | static int |
d174bd64 DV |
325 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
326 | char __user *user_data, | |
327 | bool page_do_bit17_swizzling, bool needs_clflush) | |
328 | { | |
329 | char *vaddr; | |
330 | int ret; | |
331 | ||
e7e58eb5 | 332 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
333 | return -EINVAL; |
334 | ||
335 | vaddr = kmap_atomic(page); | |
336 | if (needs_clflush) | |
337 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
338 | page_length); | |
339 | ret = __copy_to_user_inatomic(user_data, | |
340 | vaddr + shmem_page_offset, | |
341 | page_length); | |
342 | kunmap_atomic(vaddr); | |
343 | ||
344 | return ret; | |
345 | } | |
346 | ||
23c18c71 DV |
347 | static void |
348 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
349 | bool swizzled) | |
350 | { | |
e7e58eb5 | 351 | if (unlikely(swizzled)) { |
23c18c71 DV |
352 | unsigned long start = (unsigned long) addr; |
353 | unsigned long end = (unsigned long) addr + length; | |
354 | ||
355 | /* For swizzling simply ensure that we always flush both | |
356 | * channels. Lame, but simple and it works. Swizzled | |
357 | * pwrite/pread is far from a hotpath - current userspace | |
358 | * doesn't use it at all. */ | |
359 | start = round_down(start, 128); | |
360 | end = round_up(end, 128); | |
361 | ||
362 | drm_clflush_virt_range((void *)start, end - start); | |
363 | } else { | |
364 | drm_clflush_virt_range(addr, length); | |
365 | } | |
366 | ||
367 | } | |
368 | ||
d174bd64 DV |
369 | /* Only difference to the fast-path function is that this can handle bit17 |
370 | * and uses non-atomic copy and kmap functions. */ | |
371 | static int | |
372 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
373 | char __user *user_data, | |
374 | bool page_do_bit17_swizzling, bool needs_clflush) | |
375 | { | |
376 | char *vaddr; | |
377 | int ret; | |
378 | ||
379 | vaddr = kmap(page); | |
380 | if (needs_clflush) | |
23c18c71 DV |
381 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
382 | page_length, | |
383 | page_do_bit17_swizzling); | |
d174bd64 DV |
384 | |
385 | if (page_do_bit17_swizzling) | |
386 | ret = __copy_to_user_swizzled(user_data, | |
387 | vaddr, shmem_page_offset, | |
388 | page_length); | |
389 | else | |
390 | ret = __copy_to_user(user_data, | |
391 | vaddr + shmem_page_offset, | |
392 | page_length); | |
393 | kunmap(page); | |
394 | ||
395 | return ret; | |
396 | } | |
397 | ||
eb01459f | 398 | static int |
dbf7bff0 DV |
399 | i915_gem_shmem_pread(struct drm_device *dev, |
400 | struct drm_i915_gem_object *obj, | |
401 | struct drm_i915_gem_pread *args, | |
402 | struct drm_file *file) | |
eb01459f | 403 | { |
05394f39 | 404 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
8461d226 | 405 | char __user *user_data; |
eb01459f | 406 | ssize_t remain; |
8461d226 | 407 | loff_t offset; |
eb2c0c81 | 408 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 409 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
dbf7bff0 | 410 | int hit_slowpath = 0; |
96d79b52 | 411 | int prefaulted = 0; |
8489731c | 412 | int needs_clflush = 0; |
692a576b | 413 | int release_page; |
eb01459f | 414 | |
8461d226 | 415 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
eb01459f EA |
416 | remain = args->size; |
417 | ||
8461d226 | 418 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 419 | |
8489731c DV |
420 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
421 | /* If we're not in the cpu read domain, set ourself into the gtt | |
422 | * read domain and manually flush cachelines (if required). This | |
423 | * optimizes for the case when the gpu will dirty the data | |
424 | * anyway again before the next pread happens. */ | |
425 | if (obj->cache_level == I915_CACHE_NONE) | |
426 | needs_clflush = 1; | |
427 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
428 | if (ret) | |
429 | return ret; | |
430 | } | |
eb01459f | 431 | |
8461d226 | 432 | offset = args->offset; |
eb01459f EA |
433 | |
434 | while (remain > 0) { | |
e5281ccd CW |
435 | struct page *page; |
436 | ||
eb01459f EA |
437 | /* Operation in this page |
438 | * | |
eb01459f | 439 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
440 | * page_length = bytes to copy for this page |
441 | */ | |
c8cbbb8b | 442 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
443 | page_length = remain; |
444 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
445 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 446 | |
692a576b DV |
447 | if (obj->pages) { |
448 | page = obj->pages[offset >> PAGE_SHIFT]; | |
449 | release_page = 0; | |
450 | } else { | |
451 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); | |
452 | if (IS_ERR(page)) { | |
453 | ret = PTR_ERR(page); | |
454 | goto out; | |
455 | } | |
456 | release_page = 1; | |
b65552f0 | 457 | } |
e5281ccd | 458 | |
8461d226 DV |
459 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
460 | (page_to_phys(page) & (1 << 17)) != 0; | |
461 | ||
d174bd64 DV |
462 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
463 | user_data, page_do_bit17_swizzling, | |
464 | needs_clflush); | |
465 | if (ret == 0) | |
466 | goto next_page; | |
dbf7bff0 DV |
467 | |
468 | hit_slowpath = 1; | |
692a576b | 469 | page_cache_get(page); |
dbf7bff0 DV |
470 | mutex_unlock(&dev->struct_mutex); |
471 | ||
96d79b52 | 472 | if (!prefaulted) { |
f56f821f | 473 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
474 | /* Userspace is tricking us, but we've already clobbered |
475 | * its pages with the prefault and promised to write the | |
476 | * data up to the first fault. Hence ignore any errors | |
477 | * and just continue. */ | |
478 | (void)ret; | |
479 | prefaulted = 1; | |
480 | } | |
eb01459f | 481 | |
d174bd64 DV |
482 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
483 | user_data, page_do_bit17_swizzling, | |
484 | needs_clflush); | |
eb01459f | 485 | |
dbf7bff0 | 486 | mutex_lock(&dev->struct_mutex); |
e5281ccd | 487 | page_cache_release(page); |
dbf7bff0 | 488 | next_page: |
e5281ccd | 489 | mark_page_accessed(page); |
692a576b DV |
490 | if (release_page) |
491 | page_cache_release(page); | |
e5281ccd | 492 | |
8461d226 DV |
493 | if (ret) { |
494 | ret = -EFAULT; | |
495 | goto out; | |
496 | } | |
497 | ||
eb01459f | 498 | remain -= page_length; |
8461d226 | 499 | user_data += page_length; |
eb01459f EA |
500 | offset += page_length; |
501 | } | |
502 | ||
4f27b75d | 503 | out: |
dbf7bff0 DV |
504 | if (hit_slowpath) { |
505 | /* Fixup: Kill any reinstated backing storage pages */ | |
506 | if (obj->madv == __I915_MADV_PURGED) | |
507 | i915_gem_object_truncate(obj); | |
508 | } | |
eb01459f EA |
509 | |
510 | return ret; | |
511 | } | |
512 | ||
673a394b EA |
513 | /** |
514 | * Reads data from the object referenced by handle. | |
515 | * | |
516 | * On error, the contents of *data are undefined. | |
517 | */ | |
518 | int | |
519 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 520 | struct drm_file *file) |
673a394b EA |
521 | { |
522 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 523 | struct drm_i915_gem_object *obj; |
35b62a89 | 524 | int ret = 0; |
673a394b | 525 | |
51311d0a CW |
526 | if (args->size == 0) |
527 | return 0; | |
528 | ||
529 | if (!access_ok(VERIFY_WRITE, | |
530 | (char __user *)(uintptr_t)args->data_ptr, | |
531 | args->size)) | |
532 | return -EFAULT; | |
533 | ||
4f27b75d | 534 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 535 | if (ret) |
4f27b75d | 536 | return ret; |
673a394b | 537 | |
05394f39 | 538 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 539 | if (&obj->base == NULL) { |
1d7cfea1 CW |
540 | ret = -ENOENT; |
541 | goto unlock; | |
4f27b75d | 542 | } |
673a394b | 543 | |
7dcd2499 | 544 | /* Bounds check source. */ |
05394f39 CW |
545 | if (args->offset > obj->base.size || |
546 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 547 | ret = -EINVAL; |
35b62a89 | 548 | goto out; |
ce9d419d CW |
549 | } |
550 | ||
1286ff73 DV |
551 | /* prime objects have no backing filp to GEM pread/pwrite |
552 | * pages from. | |
553 | */ | |
554 | if (!obj->base.filp) { | |
555 | ret = -EINVAL; | |
556 | goto out; | |
557 | } | |
558 | ||
db53a302 CW |
559 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
560 | ||
dbf7bff0 | 561 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 562 | |
35b62a89 | 563 | out: |
05394f39 | 564 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 565 | unlock: |
4f27b75d | 566 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 567 | return ret; |
673a394b EA |
568 | } |
569 | ||
0839ccb8 KP |
570 | /* This is the fast write path which cannot handle |
571 | * page faults in the source data | |
9b7530cc | 572 | */ |
0839ccb8 KP |
573 | |
574 | static inline int | |
575 | fast_user_write(struct io_mapping *mapping, | |
576 | loff_t page_base, int page_offset, | |
577 | char __user *user_data, | |
578 | int length) | |
9b7530cc | 579 | { |
4f0c7cfb BW |
580 | void __iomem *vaddr_atomic; |
581 | void *vaddr; | |
0839ccb8 | 582 | unsigned long unwritten; |
9b7530cc | 583 | |
3e4d3af5 | 584 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
585 | /* We can use the cpu mem copy function because this is X86. */ |
586 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
587 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 588 | user_data, length); |
3e4d3af5 | 589 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 590 | return unwritten; |
0839ccb8 KP |
591 | } |
592 | ||
3de09aa3 EA |
593 | /** |
594 | * This is the fast pwrite path, where we copy the data directly from the | |
595 | * user into the GTT, uncached. | |
596 | */ | |
673a394b | 597 | static int |
05394f39 CW |
598 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
599 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 600 | struct drm_i915_gem_pwrite *args, |
05394f39 | 601 | struct drm_file *file) |
673a394b | 602 | { |
0839ccb8 | 603 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 604 | ssize_t remain; |
0839ccb8 | 605 | loff_t offset, page_base; |
673a394b | 606 | char __user *user_data; |
935aaa69 DV |
607 | int page_offset, page_length, ret; |
608 | ||
609 | ret = i915_gem_object_pin(obj, 0, true); | |
610 | if (ret) | |
611 | goto out; | |
612 | ||
613 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
614 | if (ret) | |
615 | goto out_unpin; | |
616 | ||
617 | ret = i915_gem_object_put_fence(obj); | |
618 | if (ret) | |
619 | goto out_unpin; | |
673a394b EA |
620 | |
621 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
622 | remain = args->size; | |
673a394b | 623 | |
05394f39 | 624 | offset = obj->gtt_offset + args->offset; |
673a394b EA |
625 | |
626 | while (remain > 0) { | |
627 | /* Operation in this page | |
628 | * | |
0839ccb8 KP |
629 | * page_base = page offset within aperture |
630 | * page_offset = offset within page | |
631 | * page_length = bytes to copy for this page | |
673a394b | 632 | */ |
c8cbbb8b CW |
633 | page_base = offset & PAGE_MASK; |
634 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
635 | page_length = remain; |
636 | if ((page_offset + remain) > PAGE_SIZE) | |
637 | page_length = PAGE_SIZE - page_offset; | |
638 | ||
0839ccb8 | 639 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
640 | * source page isn't available. Return the error and we'll |
641 | * retry in the slow path. | |
0839ccb8 | 642 | */ |
fbd5a26d | 643 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
935aaa69 DV |
644 | page_offset, user_data, page_length)) { |
645 | ret = -EFAULT; | |
646 | goto out_unpin; | |
647 | } | |
673a394b | 648 | |
0839ccb8 KP |
649 | remain -= page_length; |
650 | user_data += page_length; | |
651 | offset += page_length; | |
673a394b | 652 | } |
673a394b | 653 | |
935aaa69 DV |
654 | out_unpin: |
655 | i915_gem_object_unpin(obj); | |
656 | out: | |
3de09aa3 | 657 | return ret; |
673a394b EA |
658 | } |
659 | ||
d174bd64 DV |
660 | /* Per-page copy function for the shmem pwrite fastpath. |
661 | * Flushes invalid cachelines before writing to the target if | |
662 | * needs_clflush_before is set and flushes out any written cachelines after | |
663 | * writing if needs_clflush is set. */ | |
3043c60c | 664 | static int |
d174bd64 DV |
665 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
666 | char __user *user_data, | |
667 | bool page_do_bit17_swizzling, | |
668 | bool needs_clflush_before, | |
669 | bool needs_clflush_after) | |
673a394b | 670 | { |
d174bd64 | 671 | char *vaddr; |
673a394b | 672 | int ret; |
3de09aa3 | 673 | |
e7e58eb5 | 674 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 675 | return -EINVAL; |
3de09aa3 | 676 | |
d174bd64 DV |
677 | vaddr = kmap_atomic(page); |
678 | if (needs_clflush_before) | |
679 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
680 | page_length); | |
681 | ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, | |
682 | user_data, | |
683 | page_length); | |
684 | if (needs_clflush_after) | |
685 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
686 | page_length); | |
687 | kunmap_atomic(vaddr); | |
3de09aa3 EA |
688 | |
689 | return ret; | |
690 | } | |
691 | ||
d174bd64 DV |
692 | /* Only difference to the fast-path function is that this can handle bit17 |
693 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 694 | static int |
d174bd64 DV |
695 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
696 | char __user *user_data, | |
697 | bool page_do_bit17_swizzling, | |
698 | bool needs_clflush_before, | |
699 | bool needs_clflush_after) | |
673a394b | 700 | { |
d174bd64 DV |
701 | char *vaddr; |
702 | int ret; | |
e5281ccd | 703 | |
d174bd64 | 704 | vaddr = kmap(page); |
e7e58eb5 | 705 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
706 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
707 | page_length, | |
708 | page_do_bit17_swizzling); | |
d174bd64 DV |
709 | if (page_do_bit17_swizzling) |
710 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
711 | user_data, |
712 | page_length); | |
d174bd64 DV |
713 | else |
714 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
715 | user_data, | |
716 | page_length); | |
717 | if (needs_clflush_after) | |
23c18c71 DV |
718 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
719 | page_length, | |
720 | page_do_bit17_swizzling); | |
d174bd64 | 721 | kunmap(page); |
40123c1f | 722 | |
d174bd64 | 723 | return ret; |
40123c1f EA |
724 | } |
725 | ||
40123c1f | 726 | static int |
e244a443 DV |
727 | i915_gem_shmem_pwrite(struct drm_device *dev, |
728 | struct drm_i915_gem_object *obj, | |
729 | struct drm_i915_gem_pwrite *args, | |
730 | struct drm_file *file) | |
40123c1f | 731 | { |
05394f39 | 732 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
40123c1f | 733 | ssize_t remain; |
8c59967c DV |
734 | loff_t offset; |
735 | char __user *user_data; | |
eb2c0c81 | 736 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 737 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 738 | int hit_slowpath = 0; |
58642885 DV |
739 | int needs_clflush_after = 0; |
740 | int needs_clflush_before = 0; | |
692a576b | 741 | int release_page; |
40123c1f | 742 | |
8c59967c | 743 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
40123c1f EA |
744 | remain = args->size; |
745 | ||
8c59967c | 746 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 747 | |
58642885 DV |
748 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
749 | /* If we're not in the cpu write domain, set ourself into the gtt | |
750 | * write domain and manually flush cachelines (if required). This | |
751 | * optimizes for the case when the gpu will use the data | |
752 | * right away and we therefore have to clflush anyway. */ | |
753 | if (obj->cache_level == I915_CACHE_NONE) | |
754 | needs_clflush_after = 1; | |
755 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
756 | if (ret) | |
757 | return ret; | |
758 | } | |
759 | /* Same trick applies for invalidate partially written cachelines before | |
760 | * writing. */ | |
761 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU) | |
762 | && obj->cache_level == I915_CACHE_NONE) | |
763 | needs_clflush_before = 1; | |
764 | ||
673a394b | 765 | offset = args->offset; |
05394f39 | 766 | obj->dirty = 1; |
673a394b | 767 | |
40123c1f | 768 | while (remain > 0) { |
e5281ccd | 769 | struct page *page; |
58642885 | 770 | int partial_cacheline_write; |
e5281ccd | 771 | |
40123c1f EA |
772 | /* Operation in this page |
773 | * | |
40123c1f | 774 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
775 | * page_length = bytes to copy for this page |
776 | */ | |
c8cbbb8b | 777 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
778 | |
779 | page_length = remain; | |
780 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
781 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 782 | |
58642885 DV |
783 | /* If we don't overwrite a cacheline completely we need to be |
784 | * careful to have up-to-date data by first clflushing. Don't | |
785 | * overcomplicate things and flush the entire patch. */ | |
786 | partial_cacheline_write = needs_clflush_before && | |
787 | ((shmem_page_offset | page_length) | |
788 | & (boot_cpu_data.x86_clflush_size - 1)); | |
789 | ||
692a576b DV |
790 | if (obj->pages) { |
791 | page = obj->pages[offset >> PAGE_SHIFT]; | |
792 | release_page = 0; | |
793 | } else { | |
794 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); | |
795 | if (IS_ERR(page)) { | |
796 | ret = PTR_ERR(page); | |
797 | goto out; | |
798 | } | |
799 | release_page = 1; | |
e5281ccd CW |
800 | } |
801 | ||
8c59967c DV |
802 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
803 | (page_to_phys(page) & (1 << 17)) != 0; | |
804 | ||
d174bd64 DV |
805 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
806 | user_data, page_do_bit17_swizzling, | |
807 | partial_cacheline_write, | |
808 | needs_clflush_after); | |
809 | if (ret == 0) | |
810 | goto next_page; | |
e244a443 DV |
811 | |
812 | hit_slowpath = 1; | |
692a576b | 813 | page_cache_get(page); |
e244a443 DV |
814 | mutex_unlock(&dev->struct_mutex); |
815 | ||
d174bd64 DV |
816 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
817 | user_data, page_do_bit17_swizzling, | |
818 | partial_cacheline_write, | |
819 | needs_clflush_after); | |
40123c1f | 820 | |
e244a443 | 821 | mutex_lock(&dev->struct_mutex); |
692a576b | 822 | page_cache_release(page); |
e244a443 | 823 | next_page: |
e5281ccd CW |
824 | set_page_dirty(page); |
825 | mark_page_accessed(page); | |
692a576b DV |
826 | if (release_page) |
827 | page_cache_release(page); | |
e5281ccd | 828 | |
8c59967c DV |
829 | if (ret) { |
830 | ret = -EFAULT; | |
831 | goto out; | |
832 | } | |
833 | ||
40123c1f | 834 | remain -= page_length; |
8c59967c | 835 | user_data += page_length; |
40123c1f | 836 | offset += page_length; |
673a394b EA |
837 | } |
838 | ||
fbd5a26d | 839 | out: |
e244a443 DV |
840 | if (hit_slowpath) { |
841 | /* Fixup: Kill any reinstated backing storage pages */ | |
842 | if (obj->madv == __I915_MADV_PURGED) | |
843 | i915_gem_object_truncate(obj); | |
844 | /* and flush dirty cachelines in case the object isn't in the cpu write | |
845 | * domain anymore. */ | |
846 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
847 | i915_gem_clflush_object(obj); | |
848 | intel_gtt_chipset_flush(); | |
849 | } | |
8c59967c | 850 | } |
673a394b | 851 | |
58642885 DV |
852 | if (needs_clflush_after) |
853 | intel_gtt_chipset_flush(); | |
854 | ||
40123c1f | 855 | return ret; |
673a394b EA |
856 | } |
857 | ||
858 | /** | |
859 | * Writes data to the object referenced by handle. | |
860 | * | |
861 | * On error, the contents of the buffer that were to be modified are undefined. | |
862 | */ | |
863 | int | |
864 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 865 | struct drm_file *file) |
673a394b EA |
866 | { |
867 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 868 | struct drm_i915_gem_object *obj; |
51311d0a CW |
869 | int ret; |
870 | ||
871 | if (args->size == 0) | |
872 | return 0; | |
873 | ||
874 | if (!access_ok(VERIFY_READ, | |
875 | (char __user *)(uintptr_t)args->data_ptr, | |
876 | args->size)) | |
877 | return -EFAULT; | |
878 | ||
f56f821f DV |
879 | ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr, |
880 | args->size); | |
51311d0a CW |
881 | if (ret) |
882 | return -EFAULT; | |
673a394b | 883 | |
fbd5a26d | 884 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 885 | if (ret) |
fbd5a26d | 886 | return ret; |
1d7cfea1 | 887 | |
05394f39 | 888 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 889 | if (&obj->base == NULL) { |
1d7cfea1 CW |
890 | ret = -ENOENT; |
891 | goto unlock; | |
fbd5a26d | 892 | } |
673a394b | 893 | |
7dcd2499 | 894 | /* Bounds check destination. */ |
05394f39 CW |
895 | if (args->offset > obj->base.size || |
896 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 897 | ret = -EINVAL; |
35b62a89 | 898 | goto out; |
ce9d419d CW |
899 | } |
900 | ||
1286ff73 DV |
901 | /* prime objects have no backing filp to GEM pread/pwrite |
902 | * pages from. | |
903 | */ | |
904 | if (!obj->base.filp) { | |
905 | ret = -EINVAL; | |
906 | goto out; | |
907 | } | |
908 | ||
db53a302 CW |
909 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
910 | ||
935aaa69 | 911 | ret = -EFAULT; |
673a394b EA |
912 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
913 | * it would end up going through the fenced access, and we'll get | |
914 | * different detiling behavior between reading and writing. | |
915 | * pread/pwrite currently are reading and writing from the CPU | |
916 | * perspective, requiring manual detiling by the client. | |
917 | */ | |
5c0480f2 | 918 | if (obj->phys_obj) { |
fbd5a26d | 919 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
5c0480f2 DV |
920 | goto out; |
921 | } | |
922 | ||
923 | if (obj->gtt_space && | |
3ae53783 | 924 | obj->cache_level == I915_CACHE_NONE && |
c07496fa | 925 | obj->tiling_mode == I915_TILING_NONE && |
ffc62976 | 926 | obj->map_and_fenceable && |
5c0480f2 | 927 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
fbd5a26d | 928 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
929 | /* Note that the gtt paths might fail with non-page-backed user |
930 | * pointers (e.g. gtt mappings when moving data between | |
931 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 932 | } |
673a394b | 933 | |
5c0480f2 | 934 | if (ret == -EFAULT) |
935aaa69 | 935 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
5c0480f2 | 936 | |
35b62a89 | 937 | out: |
05394f39 | 938 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 939 | unlock: |
fbd5a26d | 940 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
941 | return ret; |
942 | } | |
943 | ||
944 | /** | |
2ef7eeaa EA |
945 | * Called when user space prepares to use an object with the CPU, either |
946 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
947 | */ |
948 | int | |
949 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 950 | struct drm_file *file) |
673a394b EA |
951 | { |
952 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 953 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
954 | uint32_t read_domains = args->read_domains; |
955 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
956 | int ret; |
957 | ||
2ef7eeaa | 958 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 959 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
960 | return -EINVAL; |
961 | ||
21d509e3 | 962 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
963 | return -EINVAL; |
964 | ||
965 | /* Having something in the write domain implies it's in the read | |
966 | * domain, and only that read domain. Enforce that in the request. | |
967 | */ | |
968 | if (write_domain != 0 && read_domains != write_domain) | |
969 | return -EINVAL; | |
970 | ||
76c1dec1 | 971 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 972 | if (ret) |
76c1dec1 | 973 | return ret; |
1d7cfea1 | 974 | |
05394f39 | 975 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 976 | if (&obj->base == NULL) { |
1d7cfea1 CW |
977 | ret = -ENOENT; |
978 | goto unlock; | |
76c1dec1 | 979 | } |
673a394b | 980 | |
2ef7eeaa EA |
981 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
982 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
983 | |
984 | /* Silently promote "you're not bound, there was nothing to do" | |
985 | * to success, since the client was just asking us to | |
986 | * make sure everything was done. | |
987 | */ | |
988 | if (ret == -EINVAL) | |
989 | ret = 0; | |
2ef7eeaa | 990 | } else { |
e47c68e9 | 991 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
992 | } |
993 | ||
05394f39 | 994 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 995 | unlock: |
673a394b EA |
996 | mutex_unlock(&dev->struct_mutex); |
997 | return ret; | |
998 | } | |
999 | ||
1000 | /** | |
1001 | * Called when user space has done writes to this buffer | |
1002 | */ | |
1003 | int | |
1004 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1005 | struct drm_file *file) |
673a394b EA |
1006 | { |
1007 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1008 | struct drm_i915_gem_object *obj; |
673a394b EA |
1009 | int ret = 0; |
1010 | ||
76c1dec1 | 1011 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1012 | if (ret) |
76c1dec1 | 1013 | return ret; |
1d7cfea1 | 1014 | |
05394f39 | 1015 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1016 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1017 | ret = -ENOENT; |
1018 | goto unlock; | |
673a394b EA |
1019 | } |
1020 | ||
673a394b | 1021 | /* Pinned buffers may be scanout, so flush the cache */ |
05394f39 | 1022 | if (obj->pin_count) |
e47c68e9 EA |
1023 | i915_gem_object_flush_cpu_write_domain(obj); |
1024 | ||
05394f39 | 1025 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1026 | unlock: |
673a394b EA |
1027 | mutex_unlock(&dev->struct_mutex); |
1028 | return ret; | |
1029 | } | |
1030 | ||
1031 | /** | |
1032 | * Maps the contents of an object, returning the address it is mapped | |
1033 | * into. | |
1034 | * | |
1035 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1036 | * imply a ref on the object itself. | |
1037 | */ | |
1038 | int | |
1039 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1040 | struct drm_file *file) |
673a394b EA |
1041 | { |
1042 | struct drm_i915_gem_mmap *args = data; | |
1043 | struct drm_gem_object *obj; | |
673a394b EA |
1044 | unsigned long addr; |
1045 | ||
05394f39 | 1046 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1047 | if (obj == NULL) |
bf79cb91 | 1048 | return -ENOENT; |
673a394b | 1049 | |
1286ff73 DV |
1050 | /* prime objects have no backing filp to GEM mmap |
1051 | * pages from. | |
1052 | */ | |
1053 | if (!obj->filp) { | |
1054 | drm_gem_object_unreference_unlocked(obj); | |
1055 | return -EINVAL; | |
1056 | } | |
1057 | ||
6be5ceb0 | 1058 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1059 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1060 | args->offset); | |
bc9025bd | 1061 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1062 | if (IS_ERR((void *)addr)) |
1063 | return addr; | |
1064 | ||
1065 | args->addr_ptr = (uint64_t) addr; | |
1066 | ||
1067 | return 0; | |
1068 | } | |
1069 | ||
de151cf6 JB |
1070 | /** |
1071 | * i915_gem_fault - fault a page into the GTT | |
1072 | * vma: VMA in question | |
1073 | * vmf: fault info | |
1074 | * | |
1075 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1076 | * from userspace. The fault handler takes care of binding the object to | |
1077 | * the GTT (if needed), allocating and programming a fence register (again, | |
1078 | * only if needed based on whether the old reg is still valid or the object | |
1079 | * is tiled) and inserting a new PTE into the faulting process. | |
1080 | * | |
1081 | * Note that the faulting process may involve evicting existing objects | |
1082 | * from the GTT and/or fence registers to make room. So performance may | |
1083 | * suffer if the GTT working set is large or there are few fence registers | |
1084 | * left. | |
1085 | */ | |
1086 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1087 | { | |
05394f39 CW |
1088 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1089 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1090 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1091 | pgoff_t page_offset; |
1092 | unsigned long pfn; | |
1093 | int ret = 0; | |
0f973f27 | 1094 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1095 | |
1096 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1097 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1098 | PAGE_SHIFT; | |
1099 | ||
d9bc7e9f CW |
1100 | ret = i915_mutex_lock_interruptible(dev); |
1101 | if (ret) | |
1102 | goto out; | |
a00b10c3 | 1103 | |
db53a302 CW |
1104 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1105 | ||
d9bc7e9f | 1106 | /* Now bind it into the GTT if needed */ |
919926ae CW |
1107 | if (!obj->map_and_fenceable) { |
1108 | ret = i915_gem_object_unbind(obj); | |
1109 | if (ret) | |
1110 | goto unlock; | |
a00b10c3 | 1111 | } |
05394f39 | 1112 | if (!obj->gtt_space) { |
75e9e915 | 1113 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
c715089f CW |
1114 | if (ret) |
1115 | goto unlock; | |
de151cf6 | 1116 | |
e92d03bf EA |
1117 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1118 | if (ret) | |
1119 | goto unlock; | |
1120 | } | |
4a684a41 | 1121 | |
74898d7e DV |
1122 | if (!obj->has_global_gtt_mapping) |
1123 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
1124 | ||
06d98131 | 1125 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e CW |
1126 | if (ret) |
1127 | goto unlock; | |
de151cf6 | 1128 | |
05394f39 CW |
1129 | if (i915_gem_object_is_inactive(obj)) |
1130 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
7d1c4804 | 1131 | |
6299f992 CW |
1132 | obj->fault_mappable = true; |
1133 | ||
dd2757f8 | 1134 | pfn = ((dev_priv->mm.gtt_base_addr + obj->gtt_offset) >> PAGE_SHIFT) + |
de151cf6 JB |
1135 | page_offset; |
1136 | ||
1137 | /* Finally, remap it using the new GTT offset */ | |
1138 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1139 | unlock: |
de151cf6 | 1140 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1141 | out: |
de151cf6 | 1142 | switch (ret) { |
d9bc7e9f | 1143 | case -EIO: |
a9340cca DV |
1144 | /* If this -EIO is due to a gpu hang, give the reset code a |
1145 | * chance to clean up the mess. Otherwise return the proper | |
1146 | * SIGBUS. */ | |
1147 | if (!atomic_read(&dev_priv->mm.wedged)) | |
1148 | return VM_FAULT_SIGBUS; | |
045e769a | 1149 | case -EAGAIN: |
d9bc7e9f CW |
1150 | /* Give the error handler a chance to run and move the |
1151 | * objects off the GPU active list. Next time we service the | |
1152 | * fault, we should be able to transition the page into the | |
1153 | * GTT without touching the GPU (and so avoid further | |
1154 | * EIO/EGAIN). If the GPU is wedged, then there is no issue | |
1155 | * with coherency, just lost writes. | |
1156 | */ | |
045e769a | 1157 | set_need_resched(); |
c715089f CW |
1158 | case 0: |
1159 | case -ERESTARTSYS: | |
bed636ab | 1160 | case -EINTR: |
c715089f | 1161 | return VM_FAULT_NOPAGE; |
de151cf6 | 1162 | case -ENOMEM: |
de151cf6 | 1163 | return VM_FAULT_OOM; |
de151cf6 | 1164 | default: |
c715089f | 1165 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1166 | } |
1167 | } | |
1168 | ||
901782b2 CW |
1169 | /** |
1170 | * i915_gem_release_mmap - remove physical page mappings | |
1171 | * @obj: obj in question | |
1172 | * | |
af901ca1 | 1173 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1174 | * relinquish ownership of the pages back to the system. |
1175 | * | |
1176 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1177 | * object through the GTT and then lose the fence register due to | |
1178 | * resource pressure. Similarly if the object has been moved out of the | |
1179 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1180 | * mapping will then trigger a page fault on the next user access, allowing | |
1181 | * fixup by i915_gem_fault(). | |
1182 | */ | |
d05ca301 | 1183 | void |
05394f39 | 1184 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1185 | { |
6299f992 CW |
1186 | if (!obj->fault_mappable) |
1187 | return; | |
901782b2 | 1188 | |
f6e47884 CW |
1189 | if (obj->base.dev->dev_mapping) |
1190 | unmap_mapping_range(obj->base.dev->dev_mapping, | |
1191 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, | |
1192 | obj->base.size, 1); | |
fb7d516a | 1193 | |
6299f992 | 1194 | obj->fault_mappable = false; |
901782b2 CW |
1195 | } |
1196 | ||
92b88aeb | 1197 | static uint32_t |
e28f8711 | 1198 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1199 | { |
e28f8711 | 1200 | uint32_t gtt_size; |
92b88aeb CW |
1201 | |
1202 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1203 | tiling_mode == I915_TILING_NONE) |
1204 | return size; | |
92b88aeb CW |
1205 | |
1206 | /* Previous chips need a power-of-two fence region when tiling */ | |
1207 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1208 | gtt_size = 1024*1024; |
92b88aeb | 1209 | else |
e28f8711 | 1210 | gtt_size = 512*1024; |
92b88aeb | 1211 | |
e28f8711 CW |
1212 | while (gtt_size < size) |
1213 | gtt_size <<= 1; | |
92b88aeb | 1214 | |
e28f8711 | 1215 | return gtt_size; |
92b88aeb CW |
1216 | } |
1217 | ||
de151cf6 JB |
1218 | /** |
1219 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1220 | * @obj: object to check | |
1221 | * | |
1222 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1223 | * potential fence register mapping. |
de151cf6 JB |
1224 | */ |
1225 | static uint32_t | |
e28f8711 CW |
1226 | i915_gem_get_gtt_alignment(struct drm_device *dev, |
1227 | uint32_t size, | |
1228 | int tiling_mode) | |
de151cf6 | 1229 | { |
de151cf6 JB |
1230 | /* |
1231 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1232 | * if a fence register is needed for the object. | |
1233 | */ | |
a00b10c3 | 1234 | if (INTEL_INFO(dev)->gen >= 4 || |
e28f8711 | 1235 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1236 | return 4096; |
1237 | ||
a00b10c3 CW |
1238 | /* |
1239 | * Previous chips need to be aligned to the size of the smallest | |
1240 | * fence register that can contain the object. | |
1241 | */ | |
e28f8711 | 1242 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1243 | } |
1244 | ||
5e783301 DV |
1245 | /** |
1246 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an | |
1247 | * unfenced object | |
e28f8711 CW |
1248 | * @dev: the device |
1249 | * @size: size of the object | |
1250 | * @tiling_mode: tiling mode of the object | |
5e783301 DV |
1251 | * |
1252 | * Return the required GTT alignment for an object, only taking into account | |
1253 | * unfenced tiled surface requirements. | |
1254 | */ | |
467cffba | 1255 | uint32_t |
e28f8711 CW |
1256 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
1257 | uint32_t size, | |
1258 | int tiling_mode) | |
5e783301 | 1259 | { |
5e783301 DV |
1260 | /* |
1261 | * Minimum alignment is 4k (GTT page size) for sane hw. | |
1262 | */ | |
1263 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || | |
e28f8711 | 1264 | tiling_mode == I915_TILING_NONE) |
5e783301 DV |
1265 | return 4096; |
1266 | ||
e28f8711 CW |
1267 | /* Previous hardware however needs to be aligned to a power-of-two |
1268 | * tile height. The simplest method for determining this is to reuse | |
1269 | * the power-of-tile object size. | |
5e783301 | 1270 | */ |
e28f8711 | 1271 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
5e783301 DV |
1272 | } |
1273 | ||
de151cf6 | 1274 | int |
ff72145b DA |
1275 | i915_gem_mmap_gtt(struct drm_file *file, |
1276 | struct drm_device *dev, | |
1277 | uint32_t handle, | |
1278 | uint64_t *offset) | |
de151cf6 | 1279 | { |
da761a6e | 1280 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1281 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1282 | int ret; |
1283 | ||
76c1dec1 | 1284 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1285 | if (ret) |
76c1dec1 | 1286 | return ret; |
de151cf6 | 1287 | |
ff72145b | 1288 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1289 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1290 | ret = -ENOENT; |
1291 | goto unlock; | |
1292 | } | |
de151cf6 | 1293 | |
05394f39 | 1294 | if (obj->base.size > dev_priv->mm.gtt_mappable_end) { |
da761a6e | 1295 | ret = -E2BIG; |
ff56b0bc | 1296 | goto out; |
da761a6e CW |
1297 | } |
1298 | ||
05394f39 | 1299 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1300 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1301 | ret = -EINVAL; |
1302 | goto out; | |
ab18282d CW |
1303 | } |
1304 | ||
05394f39 | 1305 | if (!obj->base.map_list.map) { |
b464e9a2 | 1306 | ret = drm_gem_create_mmap_offset(&obj->base); |
1d7cfea1 CW |
1307 | if (ret) |
1308 | goto out; | |
de151cf6 JB |
1309 | } |
1310 | ||
ff72145b | 1311 | *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1312 | |
1d7cfea1 | 1313 | out: |
05394f39 | 1314 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1315 | unlock: |
de151cf6 | 1316 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1317 | return ret; |
de151cf6 JB |
1318 | } |
1319 | ||
ff72145b DA |
1320 | /** |
1321 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1322 | * @dev: DRM device | |
1323 | * @data: GTT mapping ioctl data | |
1324 | * @file: GEM object info | |
1325 | * | |
1326 | * Simply returns the fake offset to userspace so it can mmap it. | |
1327 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1328 | * up so we can get faults in the handler above. | |
1329 | * | |
1330 | * The fault handler will take care of binding the object into the GTT | |
1331 | * (since it may have been evicted to make room for something), allocating | |
1332 | * a fence register, and mapping the appropriate aperture address into | |
1333 | * userspace. | |
1334 | */ | |
1335 | int | |
1336 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1337 | struct drm_file *file) | |
1338 | { | |
1339 | struct drm_i915_gem_mmap_gtt *args = data; | |
1340 | ||
ff72145b DA |
1341 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
1342 | } | |
1343 | ||
1286ff73 | 1344 | int |
05394f39 | 1345 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj, |
e5281ccd CW |
1346 | gfp_t gfpmask) |
1347 | { | |
e5281ccd CW |
1348 | int page_count, i; |
1349 | struct address_space *mapping; | |
1350 | struct inode *inode; | |
1351 | struct page *page; | |
1352 | ||
1286ff73 DV |
1353 | if (obj->pages || obj->sg_table) |
1354 | return 0; | |
1355 | ||
e5281ccd CW |
1356 | /* Get the list of pages out of our struct file. They'll be pinned |
1357 | * at this point until we release them. | |
1358 | */ | |
05394f39 CW |
1359 | page_count = obj->base.size / PAGE_SIZE; |
1360 | BUG_ON(obj->pages != NULL); | |
1361 | obj->pages = drm_malloc_ab(page_count, sizeof(struct page *)); | |
1362 | if (obj->pages == NULL) | |
e5281ccd CW |
1363 | return -ENOMEM; |
1364 | ||
05394f39 | 1365 | inode = obj->base.filp->f_path.dentry->d_inode; |
e5281ccd | 1366 | mapping = inode->i_mapping; |
5949eac4 HD |
1367 | gfpmask |= mapping_gfp_mask(mapping); |
1368 | ||
e5281ccd | 1369 | for (i = 0; i < page_count; i++) { |
5949eac4 | 1370 | page = shmem_read_mapping_page_gfp(mapping, i, gfpmask); |
e5281ccd CW |
1371 | if (IS_ERR(page)) |
1372 | goto err_pages; | |
1373 | ||
05394f39 | 1374 | obj->pages[i] = page; |
e5281ccd CW |
1375 | } |
1376 | ||
6dacfd2f | 1377 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
1378 | i915_gem_object_do_bit_17_swizzle(obj); |
1379 | ||
1380 | return 0; | |
1381 | ||
1382 | err_pages: | |
1383 | while (i--) | |
05394f39 | 1384 | page_cache_release(obj->pages[i]); |
e5281ccd | 1385 | |
05394f39 CW |
1386 | drm_free_large(obj->pages); |
1387 | obj->pages = NULL; | |
e5281ccd CW |
1388 | return PTR_ERR(page); |
1389 | } | |
1390 | ||
5cdf5881 | 1391 | static void |
05394f39 | 1392 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1393 | { |
05394f39 | 1394 | int page_count = obj->base.size / PAGE_SIZE; |
673a394b EA |
1395 | int i; |
1396 | ||
1286ff73 DV |
1397 | if (!obj->pages) |
1398 | return; | |
1399 | ||
05394f39 | 1400 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1401 | |
6dacfd2f | 1402 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1403 | i915_gem_object_save_bit_17_swizzle(obj); |
1404 | ||
05394f39 CW |
1405 | if (obj->madv == I915_MADV_DONTNEED) |
1406 | obj->dirty = 0; | |
3ef94daa CW |
1407 | |
1408 | for (i = 0; i < page_count; i++) { | |
05394f39 CW |
1409 | if (obj->dirty) |
1410 | set_page_dirty(obj->pages[i]); | |
3ef94daa | 1411 | |
05394f39 CW |
1412 | if (obj->madv == I915_MADV_WILLNEED) |
1413 | mark_page_accessed(obj->pages[i]); | |
3ef94daa | 1414 | |
05394f39 | 1415 | page_cache_release(obj->pages[i]); |
3ef94daa | 1416 | } |
05394f39 | 1417 | obj->dirty = 0; |
673a394b | 1418 | |
05394f39 CW |
1419 | drm_free_large(obj->pages); |
1420 | obj->pages = NULL; | |
673a394b EA |
1421 | } |
1422 | ||
54cf91dc | 1423 | void |
05394f39 | 1424 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
1ec14ad3 CW |
1425 | struct intel_ring_buffer *ring, |
1426 | u32 seqno) | |
673a394b | 1427 | { |
05394f39 | 1428 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1429 | struct drm_i915_private *dev_priv = dev->dev_private; |
617dbe27 | 1430 | |
852835f3 | 1431 | BUG_ON(ring == NULL); |
05394f39 | 1432 | obj->ring = ring; |
673a394b EA |
1433 | |
1434 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1435 | if (!obj->active) { |
1436 | drm_gem_object_reference(&obj->base); | |
1437 | obj->active = 1; | |
673a394b | 1438 | } |
e35a41de | 1439 | |
673a394b | 1440 | /* Move from whatever list we were on to the tail of execution. */ |
05394f39 CW |
1441 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
1442 | list_move_tail(&obj->ring_list, &ring->active_list); | |
caea7476 | 1443 | |
0201f1ec | 1444 | obj->last_read_seqno = seqno; |
caea7476 | 1445 | |
7dd49065 | 1446 | if (obj->fenced_gpu_access) { |
caea7476 | 1447 | obj->last_fenced_seqno = seqno; |
caea7476 | 1448 | |
7dd49065 CW |
1449 | /* Bump MRU to take account of the delayed flush */ |
1450 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1451 | struct drm_i915_fence_reg *reg; | |
1452 | ||
1453 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1454 | list_move_tail(®->lru_list, | |
1455 | &dev_priv->mm.fence_list); | |
1456 | } | |
caea7476 CW |
1457 | } |
1458 | } | |
1459 | ||
1460 | static void | |
1461 | i915_gem_object_move_off_active(struct drm_i915_gem_object *obj) | |
1462 | { | |
1463 | list_del_init(&obj->ring_list); | |
0201f1ec CW |
1464 | obj->last_read_seqno = 0; |
1465 | obj->last_write_seqno = 0; | |
15a13bbd | 1466 | obj->last_fenced_seqno = 0; |
673a394b EA |
1467 | } |
1468 | ||
ce44b0ea | 1469 | static void |
05394f39 | 1470 | i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj) |
ce44b0ea | 1471 | { |
05394f39 | 1472 | struct drm_device *dev = obj->base.dev; |
ce44b0ea | 1473 | drm_i915_private_t *dev_priv = dev->dev_private; |
ce44b0ea | 1474 | |
05394f39 CW |
1475 | BUG_ON(!obj->active); |
1476 | list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list); | |
caea7476 CW |
1477 | |
1478 | i915_gem_object_move_off_active(obj); | |
1479 | } | |
1480 | ||
1481 | static void | |
1482 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) | |
1483 | { | |
1484 | struct drm_device *dev = obj->base.dev; | |
1485 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1486 | ||
1b50247a | 1487 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
caea7476 CW |
1488 | |
1489 | BUG_ON(!list_empty(&obj->gpu_write_list)); | |
1490 | BUG_ON(!obj->active); | |
1491 | obj->ring = NULL; | |
1492 | ||
1493 | i915_gem_object_move_off_active(obj); | |
1494 | obj->fenced_gpu_access = false; | |
caea7476 CW |
1495 | |
1496 | obj->active = 0; | |
1497 | drm_gem_object_unreference(&obj->base); | |
1498 | ||
1499 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 1500 | } |
673a394b | 1501 | |
963b4836 CW |
1502 | /* Immediately discard the backing storage */ |
1503 | static void | |
05394f39 | 1504 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
963b4836 | 1505 | { |
bb6baf76 | 1506 | struct inode *inode; |
963b4836 | 1507 | |
ae9fed6b CW |
1508 | /* Our goal here is to return as much of the memory as |
1509 | * is possible back to the system as we are called from OOM. | |
1510 | * To do this we must instruct the shmfs to drop all of its | |
e2377fe0 | 1511 | * backing pages, *now*. |
ae9fed6b | 1512 | */ |
05394f39 | 1513 | inode = obj->base.filp->f_path.dentry->d_inode; |
e2377fe0 | 1514 | shmem_truncate_range(inode, 0, (loff_t)-1); |
bb6baf76 | 1515 | |
a14917ee CW |
1516 | if (obj->base.map_list.map) |
1517 | drm_gem_free_mmap_offset(&obj->base); | |
1518 | ||
05394f39 | 1519 | obj->madv = __I915_MADV_PURGED; |
963b4836 CW |
1520 | } |
1521 | ||
1522 | static inline int | |
05394f39 | 1523 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
963b4836 | 1524 | { |
05394f39 | 1525 | return obj->madv == I915_MADV_DONTNEED; |
963b4836 CW |
1526 | } |
1527 | ||
63560396 | 1528 | static void |
db53a302 CW |
1529 | i915_gem_process_flushing_list(struct intel_ring_buffer *ring, |
1530 | uint32_t flush_domains) | |
63560396 | 1531 | { |
05394f39 | 1532 | struct drm_i915_gem_object *obj, *next; |
63560396 | 1533 | |
05394f39 | 1534 | list_for_each_entry_safe(obj, next, |
64193406 | 1535 | &ring->gpu_write_list, |
63560396 | 1536 | gpu_write_list) { |
05394f39 CW |
1537 | if (obj->base.write_domain & flush_domains) { |
1538 | uint32_t old_write_domain = obj->base.write_domain; | |
63560396 | 1539 | |
05394f39 CW |
1540 | obj->base.write_domain = 0; |
1541 | list_del_init(&obj->gpu_write_list); | |
1ec14ad3 | 1542 | i915_gem_object_move_to_active(obj, ring, |
db53a302 | 1543 | i915_gem_next_request_seqno(ring)); |
63560396 | 1544 | |
63560396 | 1545 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 1546 | obj->base.read_domains, |
63560396 DV |
1547 | old_write_domain); |
1548 | } | |
1549 | } | |
1550 | } | |
8187a2b7 | 1551 | |
53d227f2 DV |
1552 | static u32 |
1553 | i915_gem_get_seqno(struct drm_device *dev) | |
1554 | { | |
1555 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1556 | u32 seqno = dev_priv->next_seqno; | |
1557 | ||
1558 | /* reserve 0 for non-seqno */ | |
1559 | if (++dev_priv->next_seqno == 0) | |
1560 | dev_priv->next_seqno = 1; | |
1561 | ||
1562 | return seqno; | |
1563 | } | |
1564 | ||
1565 | u32 | |
1566 | i915_gem_next_request_seqno(struct intel_ring_buffer *ring) | |
1567 | { | |
1568 | if (ring->outstanding_lazy_request == 0) | |
1569 | ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev); | |
1570 | ||
1571 | return ring->outstanding_lazy_request; | |
1572 | } | |
1573 | ||
3cce469c | 1574 | int |
db53a302 | 1575 | i915_add_request(struct intel_ring_buffer *ring, |
f787a5f5 | 1576 | struct drm_file *file, |
db53a302 | 1577 | struct drm_i915_gem_request *request) |
673a394b | 1578 | { |
db53a302 | 1579 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
673a394b | 1580 | uint32_t seqno; |
a71d8d94 | 1581 | u32 request_ring_position; |
673a394b | 1582 | int was_empty; |
3cce469c CW |
1583 | int ret; |
1584 | ||
cc889e0f DV |
1585 | /* |
1586 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
1587 | * after having emitted the batchbuffer command. Hence we need to fix | |
1588 | * things up similar to emitting the lazy request. The difference here | |
1589 | * is that the flush _must_ happen before the next request, no matter | |
1590 | * what. | |
1591 | */ | |
1592 | if (ring->gpu_caches_dirty) { | |
1593 | ret = i915_gem_flush_ring(ring, 0, I915_GEM_GPU_DOMAINS); | |
1594 | if (ret) | |
1595 | return ret; | |
1596 | ||
1597 | ring->gpu_caches_dirty = false; | |
1598 | } | |
1599 | ||
3bb73aba CW |
1600 | if (request == NULL) { |
1601 | request = kmalloc(sizeof(*request), GFP_KERNEL); | |
1602 | if (request == NULL) | |
1603 | return -ENOMEM; | |
1604 | } | |
1605 | ||
53d227f2 | 1606 | seqno = i915_gem_next_request_seqno(ring); |
673a394b | 1607 | |
a71d8d94 CW |
1608 | /* Record the position of the start of the request so that |
1609 | * should we detect the updated seqno part-way through the | |
1610 | * GPU processing the request, we never over-estimate the | |
1611 | * position of the head. | |
1612 | */ | |
1613 | request_ring_position = intel_ring_get_tail(ring); | |
1614 | ||
3cce469c | 1615 | ret = ring->add_request(ring, &seqno); |
3bb73aba CW |
1616 | if (ret) { |
1617 | kfree(request); | |
1618 | return ret; | |
1619 | } | |
673a394b | 1620 | |
db53a302 | 1621 | trace_i915_gem_request_add(ring, seqno); |
673a394b EA |
1622 | |
1623 | request->seqno = seqno; | |
852835f3 | 1624 | request->ring = ring; |
a71d8d94 | 1625 | request->tail = request_ring_position; |
673a394b | 1626 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1627 | was_empty = list_empty(&ring->request_list); |
1628 | list_add_tail(&request->list, &ring->request_list); | |
3bb73aba | 1629 | request->file_priv = NULL; |
852835f3 | 1630 | |
db53a302 CW |
1631 | if (file) { |
1632 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1633 | ||
1c25595f | 1634 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 1635 | request->file_priv = file_priv; |
b962442e | 1636 | list_add_tail(&request->client_list, |
f787a5f5 | 1637 | &file_priv->mm.request_list); |
1c25595f | 1638 | spin_unlock(&file_priv->mm.lock); |
b962442e | 1639 | } |
673a394b | 1640 | |
5391d0cf | 1641 | ring->outstanding_lazy_request = 0; |
db53a302 | 1642 | |
f65d9421 | 1643 | if (!dev_priv->mm.suspended) { |
3e0dc6b0 BW |
1644 | if (i915_enable_hangcheck) { |
1645 | mod_timer(&dev_priv->hangcheck_timer, | |
1646 | jiffies + | |
1647 | msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
1648 | } | |
f65d9421 | 1649 | if (was_empty) |
b3b079db CW |
1650 | queue_delayed_work(dev_priv->wq, |
1651 | &dev_priv->mm.retire_work, HZ); | |
f65d9421 | 1652 | } |
cc889e0f DV |
1653 | |
1654 | WARN_ON(!list_empty(&ring->gpu_write_list)); | |
1655 | ||
3cce469c | 1656 | return 0; |
673a394b EA |
1657 | } |
1658 | ||
f787a5f5 CW |
1659 | static inline void |
1660 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 1661 | { |
1c25595f | 1662 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 1663 | |
1c25595f CW |
1664 | if (!file_priv) |
1665 | return; | |
1c5d22f7 | 1666 | |
1c25595f | 1667 | spin_lock(&file_priv->mm.lock); |
09bfa517 HRK |
1668 | if (request->file_priv) { |
1669 | list_del(&request->client_list); | |
1670 | request->file_priv = NULL; | |
1671 | } | |
1c25595f | 1672 | spin_unlock(&file_priv->mm.lock); |
673a394b | 1673 | } |
673a394b | 1674 | |
dfaae392 CW |
1675 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
1676 | struct intel_ring_buffer *ring) | |
9375e446 | 1677 | { |
dfaae392 CW |
1678 | while (!list_empty(&ring->request_list)) { |
1679 | struct drm_i915_gem_request *request; | |
673a394b | 1680 | |
dfaae392 CW |
1681 | request = list_first_entry(&ring->request_list, |
1682 | struct drm_i915_gem_request, | |
1683 | list); | |
de151cf6 | 1684 | |
dfaae392 | 1685 | list_del(&request->list); |
f787a5f5 | 1686 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
1687 | kfree(request); |
1688 | } | |
673a394b | 1689 | |
dfaae392 | 1690 | while (!list_empty(&ring->active_list)) { |
05394f39 | 1691 | struct drm_i915_gem_object *obj; |
9375e446 | 1692 | |
05394f39 CW |
1693 | obj = list_first_entry(&ring->active_list, |
1694 | struct drm_i915_gem_object, | |
1695 | ring_list); | |
9375e446 | 1696 | |
05394f39 CW |
1697 | obj->base.write_domain = 0; |
1698 | list_del_init(&obj->gpu_write_list); | |
1699 | i915_gem_object_move_to_inactive(obj); | |
673a394b EA |
1700 | } |
1701 | } | |
1702 | ||
312817a3 CW |
1703 | static void i915_gem_reset_fences(struct drm_device *dev) |
1704 | { | |
1705 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1706 | int i; | |
1707 | ||
4b9de737 | 1708 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 1709 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 1710 | |
ada726c7 | 1711 | i915_gem_write_fence(dev, i, NULL); |
7d2cb39c | 1712 | |
ada726c7 CW |
1713 | if (reg->obj) |
1714 | i915_gem_object_fence_lost(reg->obj); | |
7d2cb39c | 1715 | |
ada726c7 CW |
1716 | reg->pin_count = 0; |
1717 | reg->obj = NULL; | |
1718 | INIT_LIST_HEAD(®->lru_list); | |
312817a3 | 1719 | } |
ada726c7 CW |
1720 | |
1721 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); | |
312817a3 CW |
1722 | } |
1723 | ||
069efc1d | 1724 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 1725 | { |
77f01230 | 1726 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1727 | struct drm_i915_gem_object *obj; |
b4519513 | 1728 | struct intel_ring_buffer *ring; |
1ec14ad3 | 1729 | int i; |
673a394b | 1730 | |
b4519513 CW |
1731 | for_each_ring(ring, dev_priv, i) |
1732 | i915_gem_reset_ring_lists(dev_priv, ring); | |
dfaae392 CW |
1733 | |
1734 | /* Remove anything from the flushing lists. The GPU cache is likely | |
1735 | * to be lost on reset along with the data, so simply move the | |
1736 | * lost bo to the inactive list. | |
1737 | */ | |
1738 | while (!list_empty(&dev_priv->mm.flushing_list)) { | |
0206e353 | 1739 | obj = list_first_entry(&dev_priv->mm.flushing_list, |
05394f39 CW |
1740 | struct drm_i915_gem_object, |
1741 | mm_list); | |
dfaae392 | 1742 | |
05394f39 CW |
1743 | obj->base.write_domain = 0; |
1744 | list_del_init(&obj->gpu_write_list); | |
1745 | i915_gem_object_move_to_inactive(obj); | |
dfaae392 CW |
1746 | } |
1747 | ||
1748 | /* Move everything out of the GPU domains to ensure we do any | |
1749 | * necessary invalidation upon reuse. | |
1750 | */ | |
05394f39 | 1751 | list_for_each_entry(obj, |
77f01230 | 1752 | &dev_priv->mm.inactive_list, |
69dc4987 | 1753 | mm_list) |
77f01230 | 1754 | { |
05394f39 | 1755 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
77f01230 | 1756 | } |
069efc1d CW |
1757 | |
1758 | /* The fence registers are invalidated so clear them out */ | |
312817a3 | 1759 | i915_gem_reset_fences(dev); |
673a394b EA |
1760 | } |
1761 | ||
1762 | /** | |
1763 | * This function clears the request list as sequence numbers are passed. | |
1764 | */ | |
a71d8d94 | 1765 | void |
db53a302 | 1766 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 1767 | { |
673a394b | 1768 | uint32_t seqno; |
1ec14ad3 | 1769 | int i; |
673a394b | 1770 | |
db53a302 | 1771 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
1772 | return; |
1773 | ||
db53a302 | 1774 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 1775 | |
78501eac | 1776 | seqno = ring->get_seqno(ring); |
1ec14ad3 | 1777 | |
076e2c0e | 1778 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) |
1ec14ad3 CW |
1779 | if (seqno >= ring->sync_seqno[i]) |
1780 | ring->sync_seqno[i] = 0; | |
1781 | ||
852835f3 | 1782 | while (!list_empty(&ring->request_list)) { |
673a394b | 1783 | struct drm_i915_gem_request *request; |
673a394b | 1784 | |
852835f3 | 1785 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1786 | struct drm_i915_gem_request, |
1787 | list); | |
673a394b | 1788 | |
dfaae392 | 1789 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
1790 | break; |
1791 | ||
db53a302 | 1792 | trace_i915_gem_request_retire(ring, request->seqno); |
a71d8d94 CW |
1793 | /* We know the GPU must have read the request to have |
1794 | * sent us the seqno + interrupt, so use the position | |
1795 | * of tail of the request to update the last known position | |
1796 | * of the GPU head. | |
1797 | */ | |
1798 | ring->last_retired_head = request->tail; | |
b84d5f0c CW |
1799 | |
1800 | list_del(&request->list); | |
f787a5f5 | 1801 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
1802 | kfree(request); |
1803 | } | |
673a394b | 1804 | |
b84d5f0c CW |
1805 | /* Move any buffers on the active list that are no longer referenced |
1806 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1807 | */ | |
1808 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 1809 | struct drm_i915_gem_object *obj; |
b84d5f0c | 1810 | |
0206e353 | 1811 | obj = list_first_entry(&ring->active_list, |
05394f39 CW |
1812 | struct drm_i915_gem_object, |
1813 | ring_list); | |
673a394b | 1814 | |
0201f1ec | 1815 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) |
673a394b | 1816 | break; |
b84d5f0c | 1817 | |
05394f39 | 1818 | if (obj->base.write_domain != 0) |
b84d5f0c CW |
1819 | i915_gem_object_move_to_flushing(obj); |
1820 | else | |
1821 | i915_gem_object_move_to_inactive(obj); | |
673a394b | 1822 | } |
9d34e5db | 1823 | |
db53a302 CW |
1824 | if (unlikely(ring->trace_irq_seqno && |
1825 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 1826 | ring->irq_put(ring); |
db53a302 | 1827 | ring->trace_irq_seqno = 0; |
9d34e5db | 1828 | } |
23bc5982 | 1829 | |
db53a302 | 1830 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
1831 | } |
1832 | ||
b09a1fec CW |
1833 | void |
1834 | i915_gem_retire_requests(struct drm_device *dev) | |
1835 | { | |
1836 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 1837 | struct intel_ring_buffer *ring; |
1ec14ad3 | 1838 | int i; |
b09a1fec | 1839 | |
b4519513 CW |
1840 | for_each_ring(ring, dev_priv, i) |
1841 | i915_gem_retire_requests_ring(ring); | |
b09a1fec CW |
1842 | } |
1843 | ||
75ef9da2 | 1844 | static void |
673a394b EA |
1845 | i915_gem_retire_work_handler(struct work_struct *work) |
1846 | { | |
1847 | drm_i915_private_t *dev_priv; | |
1848 | struct drm_device *dev; | |
b4519513 | 1849 | struct intel_ring_buffer *ring; |
0a58705b CW |
1850 | bool idle; |
1851 | int i; | |
673a394b EA |
1852 | |
1853 | dev_priv = container_of(work, drm_i915_private_t, | |
1854 | mm.retire_work.work); | |
1855 | dev = dev_priv->dev; | |
1856 | ||
891b48cf CW |
1857 | /* Come back later if the device is busy... */ |
1858 | if (!mutex_trylock(&dev->struct_mutex)) { | |
1859 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
1860 | return; | |
1861 | } | |
1862 | ||
b09a1fec | 1863 | i915_gem_retire_requests(dev); |
d1b851fc | 1864 | |
0a58705b CW |
1865 | /* Send a periodic flush down the ring so we don't hold onto GEM |
1866 | * objects indefinitely. | |
1867 | */ | |
1868 | idle = true; | |
b4519513 | 1869 | for_each_ring(ring, dev_priv, i) { |
3bb73aba CW |
1870 | if (ring->gpu_caches_dirty) |
1871 | i915_add_request(ring, NULL, NULL); | |
0a58705b CW |
1872 | |
1873 | idle &= list_empty(&ring->request_list); | |
1874 | } | |
1875 | ||
1876 | if (!dev_priv->mm.suspended && !idle) | |
9c9fe1f8 | 1877 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
0a58705b | 1878 | |
673a394b EA |
1879 | mutex_unlock(&dev->struct_mutex); |
1880 | } | |
1881 | ||
d6b2c790 DV |
1882 | int |
1883 | i915_gem_check_wedge(struct drm_i915_private *dev_priv, | |
1884 | bool interruptible) | |
b4aca010 | 1885 | { |
b4aca010 BW |
1886 | if (atomic_read(&dev_priv->mm.wedged)) { |
1887 | struct completion *x = &dev_priv->error_completion; | |
1888 | bool recovery_complete; | |
1889 | unsigned long flags; | |
1890 | ||
1891 | /* Give the error handler a chance to run. */ | |
1892 | spin_lock_irqsave(&x->wait.lock, flags); | |
1893 | recovery_complete = x->done > 0; | |
1894 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
1895 | ||
d6b2c790 DV |
1896 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
1897 | * -EIO unconditionally for these. */ | |
1898 | if (!interruptible) | |
1899 | return -EIO; | |
1900 | ||
1901 | /* Recovery complete, but still wedged means reset failure. */ | |
1902 | if (recovery_complete) | |
1903 | return -EIO; | |
1904 | ||
1905 | return -EAGAIN; | |
b4aca010 BW |
1906 | } |
1907 | ||
1908 | return 0; | |
1909 | } | |
1910 | ||
1911 | /* | |
1912 | * Compare seqno against outstanding lazy request. Emit a request if they are | |
1913 | * equal. | |
1914 | */ | |
1915 | static int | |
1916 | i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) | |
1917 | { | |
3bb73aba | 1918 | int ret; |
b4aca010 BW |
1919 | |
1920 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
1921 | ||
3bb73aba CW |
1922 | ret = 0; |
1923 | if (seqno == ring->outstanding_lazy_request) | |
1924 | ret = i915_add_request(ring, NULL, NULL); | |
b4aca010 BW |
1925 | |
1926 | return ret; | |
1927 | } | |
1928 | ||
5c81fe85 BW |
1929 | /** |
1930 | * __wait_seqno - wait until execution of seqno has finished | |
1931 | * @ring: the ring expected to report seqno | |
1932 | * @seqno: duh! | |
1933 | * @interruptible: do an interruptible wait (normally yes) | |
1934 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
1935 | * | |
1936 | * Returns 0 if the seqno was found within the alloted time. Else returns the | |
1937 | * errno with remaining time filled in timeout argument. | |
1938 | */ | |
604dd3ec | 1939 | static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, |
5c81fe85 | 1940 | bool interruptible, struct timespec *timeout) |
604dd3ec BW |
1941 | { |
1942 | drm_i915_private_t *dev_priv = ring->dev->dev_private; | |
5c81fe85 BW |
1943 | struct timespec before, now, wait_time={1,0}; |
1944 | unsigned long timeout_jiffies; | |
1945 | long end; | |
1946 | bool wait_forever = true; | |
d6b2c790 | 1947 | int ret; |
604dd3ec BW |
1948 | |
1949 | if (i915_seqno_passed(ring->get_seqno(ring), seqno)) | |
1950 | return 0; | |
1951 | ||
1952 | trace_i915_gem_request_wait_begin(ring, seqno); | |
5c81fe85 BW |
1953 | |
1954 | if (timeout != NULL) { | |
1955 | wait_time = *timeout; | |
1956 | wait_forever = false; | |
1957 | } | |
1958 | ||
1959 | timeout_jiffies = timespec_to_jiffies(&wait_time); | |
1960 | ||
604dd3ec BW |
1961 | if (WARN_ON(!ring->irq_get(ring))) |
1962 | return -ENODEV; | |
1963 | ||
5c81fe85 BW |
1964 | /* Record current time in case interrupted by signal, or wedged * */ |
1965 | getrawmonotonic(&before); | |
1966 | ||
604dd3ec BW |
1967 | #define EXIT_COND \ |
1968 | (i915_seqno_passed(ring->get_seqno(ring), seqno) || \ | |
1969 | atomic_read(&dev_priv->mm.wedged)) | |
5c81fe85 BW |
1970 | do { |
1971 | if (interruptible) | |
1972 | end = wait_event_interruptible_timeout(ring->irq_queue, | |
1973 | EXIT_COND, | |
1974 | timeout_jiffies); | |
1975 | else | |
1976 | end = wait_event_timeout(ring->irq_queue, EXIT_COND, | |
1977 | timeout_jiffies); | |
604dd3ec | 1978 | |
d6b2c790 DV |
1979 | ret = i915_gem_check_wedge(dev_priv, interruptible); |
1980 | if (ret) | |
1981 | end = ret; | |
5c81fe85 BW |
1982 | } while (end == 0 && wait_forever); |
1983 | ||
1984 | getrawmonotonic(&now); | |
604dd3ec BW |
1985 | |
1986 | ring->irq_put(ring); | |
1987 | trace_i915_gem_request_wait_end(ring, seqno); | |
1988 | #undef EXIT_COND | |
1989 | ||
5c81fe85 BW |
1990 | if (timeout) { |
1991 | struct timespec sleep_time = timespec_sub(now, before); | |
1992 | *timeout = timespec_sub(*timeout, sleep_time); | |
1993 | } | |
1994 | ||
1995 | switch (end) { | |
eeef9b38 | 1996 | case -EIO: |
5c81fe85 BW |
1997 | case -EAGAIN: /* Wedged */ |
1998 | case -ERESTARTSYS: /* Signal */ | |
1999 | return (int)end; | |
2000 | case 0: /* Timeout */ | |
2001 | if (timeout) | |
2002 | set_normalized_timespec(timeout, 0, 0); | |
2003 | return -ETIME; | |
2004 | default: /* Completed */ | |
2005 | WARN_ON(end < 0); /* We're not aware of other errors */ | |
2006 | return 0; | |
2007 | } | |
604dd3ec BW |
2008 | } |
2009 | ||
db53a302 CW |
2010 | /** |
2011 | * Waits for a sequence number to be signaled, and cleans up the | |
2012 | * request and object lists appropriately for that event. | |
2013 | */ | |
5a5a0c64 | 2014 | int |
199b2bc2 | 2015 | i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) |
673a394b | 2016 | { |
db53a302 | 2017 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
673a394b EA |
2018 | int ret = 0; |
2019 | ||
2020 | BUG_ON(seqno == 0); | |
2021 | ||
d6b2c790 | 2022 | ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible); |
b4aca010 BW |
2023 | if (ret) |
2024 | return ret; | |
3cce469c | 2025 | |
b4aca010 BW |
2026 | ret = i915_gem_check_olr(ring, seqno); |
2027 | if (ret) | |
2028 | return ret; | |
ffed1d09 | 2029 | |
5c81fe85 | 2030 | ret = __wait_seqno(ring, seqno, dev_priv->mm.interruptible, NULL); |
673a394b | 2031 | |
673a394b EA |
2032 | return ret; |
2033 | } | |
2034 | ||
673a394b EA |
2035 | /** |
2036 | * Ensures that all rendering to the object has completed and the object is | |
2037 | * safe to unbind from the GTT or access from the CPU. | |
2038 | */ | |
0201f1ec CW |
2039 | static __must_check int |
2040 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
2041 | bool readonly) | |
673a394b | 2042 | { |
0201f1ec | 2043 | u32 seqno; |
673a394b EA |
2044 | int ret; |
2045 | ||
e47c68e9 EA |
2046 | /* This function only exists to support waiting for existing rendering, |
2047 | * not for emitting required flushes. | |
673a394b | 2048 | */ |
05394f39 | 2049 | BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
2050 | |
2051 | /* If there is rendering queued on the buffer being evicted, wait for | |
2052 | * it. | |
2053 | */ | |
0201f1ec CW |
2054 | if (readonly) |
2055 | seqno = obj->last_write_seqno; | |
2056 | else | |
2057 | seqno = obj->last_read_seqno; | |
2058 | if (seqno == 0) | |
2059 | return 0; | |
2060 | ||
2061 | ret = i915_wait_seqno(obj->ring, seqno); | |
2062 | if (ret) | |
2063 | return ret; | |
2064 | ||
2065 | /* Manually manage the write flush as we may have not yet retired | |
2066 | * the buffer. | |
2067 | */ | |
2068 | if (obj->last_write_seqno && | |
2069 | i915_seqno_passed(seqno, obj->last_write_seqno)) { | |
2070 | obj->last_write_seqno = 0; | |
2071 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
673a394b EA |
2072 | } |
2073 | ||
0201f1ec | 2074 | i915_gem_retire_requests_ring(obj->ring); |
673a394b EA |
2075 | return 0; |
2076 | } | |
2077 | ||
30dfebf3 DV |
2078 | /** |
2079 | * Ensures that an object will eventually get non-busy by flushing any required | |
2080 | * write domains, emitting any outstanding lazy request and retiring and | |
2081 | * completed requests. | |
2082 | */ | |
2083 | static int | |
2084 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2085 | { | |
2086 | int ret; | |
2087 | ||
2088 | if (obj->active) { | |
2089 | ret = i915_gem_object_flush_gpu_write_domain(obj); | |
2090 | if (ret) | |
2091 | return ret; | |
2092 | ||
0201f1ec | 2093 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
30dfebf3 DV |
2094 | if (ret) |
2095 | return ret; | |
0201f1ec | 2096 | |
30dfebf3 DV |
2097 | i915_gem_retire_requests_ring(obj->ring); |
2098 | } | |
2099 | ||
2100 | return 0; | |
2101 | } | |
2102 | ||
23ba4fd0 BW |
2103 | /** |
2104 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2105 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2106 | * | |
2107 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2108 | * the timeout parameter. | |
2109 | * -ETIME: object is still busy after timeout | |
2110 | * -ERESTARTSYS: signal interrupted the wait | |
2111 | * -ENONENT: object doesn't exist | |
2112 | * Also possible, but rare: | |
2113 | * -EAGAIN: GPU wedged | |
2114 | * -ENOMEM: damn | |
2115 | * -ENODEV: Internal IRQ fail | |
2116 | * -E?: The add request failed | |
2117 | * | |
2118 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2119 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2120 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2121 | * without holding struct_mutex the object may become re-busied before this | |
2122 | * function completes. A similar but shorter * race condition exists in the busy | |
2123 | * ioctl | |
2124 | */ | |
2125 | int | |
2126 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2127 | { | |
2128 | struct drm_i915_gem_wait *args = data; | |
2129 | struct drm_i915_gem_object *obj; | |
2130 | struct intel_ring_buffer *ring = NULL; | |
eac1f14f | 2131 | struct timespec timeout_stack, *timeout = NULL; |
23ba4fd0 BW |
2132 | u32 seqno = 0; |
2133 | int ret = 0; | |
2134 | ||
eac1f14f BW |
2135 | if (args->timeout_ns >= 0) { |
2136 | timeout_stack = ns_to_timespec(args->timeout_ns); | |
2137 | timeout = &timeout_stack; | |
2138 | } | |
23ba4fd0 BW |
2139 | |
2140 | ret = i915_mutex_lock_interruptible(dev); | |
2141 | if (ret) | |
2142 | return ret; | |
2143 | ||
2144 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
2145 | if (&obj->base == NULL) { | |
2146 | mutex_unlock(&dev->struct_mutex); | |
2147 | return -ENOENT; | |
2148 | } | |
2149 | ||
30dfebf3 DV |
2150 | /* Need to make sure the object gets inactive eventually. */ |
2151 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
2152 | if (ret) |
2153 | goto out; | |
2154 | ||
2155 | if (obj->active) { | |
0201f1ec | 2156 | seqno = obj->last_read_seqno; |
23ba4fd0 BW |
2157 | ring = obj->ring; |
2158 | } | |
2159 | ||
2160 | if (seqno == 0) | |
2161 | goto out; | |
2162 | ||
23ba4fd0 BW |
2163 | /* Do this after OLR check to make sure we make forward progress polling |
2164 | * on this IOCTL with a 0 timeout (like busy ioctl) | |
2165 | */ | |
2166 | if (!args->timeout_ns) { | |
2167 | ret = -ETIME; | |
2168 | goto out; | |
2169 | } | |
2170 | ||
2171 | drm_gem_object_unreference(&obj->base); | |
2172 | mutex_unlock(&dev->struct_mutex); | |
2173 | ||
eac1f14f BW |
2174 | ret = __wait_seqno(ring, seqno, true, timeout); |
2175 | if (timeout) { | |
2176 | WARN_ON(!timespec_valid(timeout)); | |
2177 | args->timeout_ns = timespec_to_ns(timeout); | |
2178 | } | |
23ba4fd0 BW |
2179 | return ret; |
2180 | ||
2181 | out: | |
2182 | drm_gem_object_unreference(&obj->base); | |
2183 | mutex_unlock(&dev->struct_mutex); | |
2184 | return ret; | |
2185 | } | |
2186 | ||
5816d648 BW |
2187 | /** |
2188 | * i915_gem_object_sync - sync an object to a ring. | |
2189 | * | |
2190 | * @obj: object which may be in use on another ring. | |
2191 | * @to: ring we wish to use the object on. May be NULL. | |
2192 | * | |
2193 | * This code is meant to abstract object synchronization with the GPU. | |
2194 | * Calling with NULL implies synchronizing the object with the CPU | |
2195 | * rather than a particular GPU ring. | |
2196 | * | |
2197 | * Returns 0 if successful, else propagates up the lower layer error. | |
2198 | */ | |
2911a35b BW |
2199 | int |
2200 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
2201 | struct intel_ring_buffer *to) | |
2202 | { | |
2203 | struct intel_ring_buffer *from = obj->ring; | |
2204 | u32 seqno; | |
2205 | int ret, idx; | |
2206 | ||
2207 | if (from == NULL || to == from) | |
2208 | return 0; | |
2209 | ||
5816d648 | 2210 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
0201f1ec | 2211 | return i915_gem_object_wait_rendering(obj, false); |
2911a35b BW |
2212 | |
2213 | idx = intel_ring_sync_index(from, to); | |
2214 | ||
0201f1ec | 2215 | seqno = obj->last_read_seqno; |
2911a35b BW |
2216 | if (seqno <= from->sync_seqno[idx]) |
2217 | return 0; | |
2218 | ||
b4aca010 BW |
2219 | ret = i915_gem_check_olr(obj->ring, seqno); |
2220 | if (ret) | |
2221 | return ret; | |
2911a35b | 2222 | |
1500f7ea | 2223 | ret = to->sync_to(to, from, seqno); |
e3a5a225 BW |
2224 | if (!ret) |
2225 | from->sync_seqno[idx] = seqno; | |
2911a35b | 2226 | |
e3a5a225 | 2227 | return ret; |
2911a35b BW |
2228 | } |
2229 | ||
b5ffc9bc CW |
2230 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2231 | { | |
2232 | u32 old_write_domain, old_read_domains; | |
2233 | ||
b5ffc9bc CW |
2234 | /* Act a barrier for all accesses through the GTT */ |
2235 | mb(); | |
2236 | ||
2237 | /* Force a pagefault for domain tracking on next user access */ | |
2238 | i915_gem_release_mmap(obj); | |
2239 | ||
b97c3d9c KP |
2240 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2241 | return; | |
2242 | ||
b5ffc9bc CW |
2243 | old_read_domains = obj->base.read_domains; |
2244 | old_write_domain = obj->base.write_domain; | |
2245 | ||
2246 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2247 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2248 | ||
2249 | trace_i915_gem_object_change_domain(obj, | |
2250 | old_read_domains, | |
2251 | old_write_domain); | |
2252 | } | |
2253 | ||
673a394b EA |
2254 | /** |
2255 | * Unbinds an object from the GTT aperture. | |
2256 | */ | |
0f973f27 | 2257 | int |
05394f39 | 2258 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
673a394b | 2259 | { |
7bddb01f | 2260 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
673a394b EA |
2261 | int ret = 0; |
2262 | ||
05394f39 | 2263 | if (obj->gtt_space == NULL) |
673a394b EA |
2264 | return 0; |
2265 | ||
31d8d651 CW |
2266 | if (obj->pin_count) |
2267 | return -EBUSY; | |
673a394b | 2268 | |
a8198eea | 2269 | ret = i915_gem_object_finish_gpu(obj); |
1488fc08 | 2270 | if (ret) |
a8198eea CW |
2271 | return ret; |
2272 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2273 | * should be safe and we need to cleanup or else we might | |
2274 | * cause memory corruption through use-after-free. | |
2275 | */ | |
2276 | ||
b5ffc9bc | 2277 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2278 | |
673a394b EA |
2279 | /* Move the object to the CPU domain to ensure that |
2280 | * any possible CPU writes while it's not in the GTT | |
a8198eea | 2281 | * are flushed when we go to remap it. |
673a394b | 2282 | */ |
a8198eea CW |
2283 | if (ret == 0) |
2284 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); | |
8dc1775d | 2285 | if (ret == -ERESTARTSYS) |
673a394b | 2286 | return ret; |
812ed492 | 2287 | if (ret) { |
a8198eea CW |
2288 | /* In the event of a disaster, abandon all caches and |
2289 | * hope for the best. | |
2290 | */ | |
812ed492 | 2291 | i915_gem_clflush_object(obj); |
05394f39 | 2292 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
812ed492 | 2293 | } |
673a394b | 2294 | |
96b47b65 | 2295 | /* release the fence reg _after_ flushing */ |
d9e86c0e | 2296 | ret = i915_gem_object_put_fence(obj); |
1488fc08 | 2297 | if (ret) |
d9e86c0e | 2298 | return ret; |
96b47b65 | 2299 | |
db53a302 CW |
2300 | trace_i915_gem_object_unbind(obj); |
2301 | ||
74898d7e DV |
2302 | if (obj->has_global_gtt_mapping) |
2303 | i915_gem_gtt_unbind_object(obj); | |
7bddb01f DV |
2304 | if (obj->has_aliasing_ppgtt_mapping) { |
2305 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); | |
2306 | obj->has_aliasing_ppgtt_mapping = 0; | |
2307 | } | |
74163907 | 2308 | i915_gem_gtt_finish_object(obj); |
7bddb01f | 2309 | |
e5281ccd | 2310 | i915_gem_object_put_pages_gtt(obj); |
673a394b | 2311 | |
6299f992 | 2312 | list_del_init(&obj->gtt_list); |
05394f39 | 2313 | list_del_init(&obj->mm_list); |
75e9e915 | 2314 | /* Avoid an unnecessary call to unbind on rebind. */ |
05394f39 | 2315 | obj->map_and_fenceable = true; |
673a394b | 2316 | |
05394f39 CW |
2317 | drm_mm_put_block(obj->gtt_space); |
2318 | obj->gtt_space = NULL; | |
2319 | obj->gtt_offset = 0; | |
673a394b | 2320 | |
05394f39 | 2321 | if (i915_gem_object_is_purgeable(obj)) |
963b4836 CW |
2322 | i915_gem_object_truncate(obj); |
2323 | ||
8dc1775d | 2324 | return ret; |
673a394b EA |
2325 | } |
2326 | ||
88241785 | 2327 | int |
db53a302 | 2328 | i915_gem_flush_ring(struct intel_ring_buffer *ring, |
54cf91dc CW |
2329 | uint32_t invalidate_domains, |
2330 | uint32_t flush_domains) | |
2331 | { | |
88241785 CW |
2332 | int ret; |
2333 | ||
36d527de CW |
2334 | if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0) |
2335 | return 0; | |
2336 | ||
db53a302 CW |
2337 | trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains); |
2338 | ||
88241785 CW |
2339 | ret = ring->flush(ring, invalidate_domains, flush_domains); |
2340 | if (ret) | |
2341 | return ret; | |
2342 | ||
36d527de CW |
2343 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
2344 | i915_gem_process_flushing_list(ring, flush_domains); | |
2345 | ||
88241785 | 2346 | return 0; |
54cf91dc CW |
2347 | } |
2348 | ||
b2da9fe5 | 2349 | static int i915_ring_idle(struct intel_ring_buffer *ring) |
a56ba56c | 2350 | { |
88241785 CW |
2351 | int ret; |
2352 | ||
395b70be | 2353 | if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list)) |
64193406 CW |
2354 | return 0; |
2355 | ||
88241785 | 2356 | if (!list_empty(&ring->gpu_write_list)) { |
db53a302 | 2357 | ret = i915_gem_flush_ring(ring, |
0ac74c6b | 2358 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
88241785 CW |
2359 | if (ret) |
2360 | return ret; | |
2361 | } | |
2362 | ||
199b2bc2 | 2363 | return i915_wait_seqno(ring, i915_gem_next_request_seqno(ring)); |
a56ba56c CW |
2364 | } |
2365 | ||
b2da9fe5 | 2366 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 DV |
2367 | { |
2368 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2369 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2370 | int ret, i; |
4df2faf4 | 2371 | |
4df2faf4 | 2372 | /* Flush everything onto the inactive list. */ |
b4519513 CW |
2373 | for_each_ring(ring, dev_priv, i) { |
2374 | ret = i915_ring_idle(ring); | |
1ec14ad3 CW |
2375 | if (ret) |
2376 | return ret; | |
b4519513 CW |
2377 | |
2378 | /* Is the device fubar? */ | |
2379 | if (WARN_ON(!list_empty(&ring->gpu_write_list))) | |
2380 | return -EBUSY; | |
f2ef6eb1 BW |
2381 | |
2382 | ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID); | |
2383 | if (ret) | |
2384 | return ret; | |
1ec14ad3 | 2385 | } |
4df2faf4 | 2386 | |
8a1a49f9 | 2387 | return 0; |
4df2faf4 DV |
2388 | } |
2389 | ||
9ce079e4 CW |
2390 | static void sandybridge_write_fence_reg(struct drm_device *dev, int reg, |
2391 | struct drm_i915_gem_object *obj) | |
4e901fdc | 2392 | { |
4e901fdc | 2393 | drm_i915_private_t *dev_priv = dev->dev_private; |
4e901fdc EA |
2394 | uint64_t val; |
2395 | ||
9ce079e4 CW |
2396 | if (obj) { |
2397 | u32 size = obj->gtt_space->size; | |
4e901fdc | 2398 | |
9ce079e4 CW |
2399 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
2400 | 0xfffff000) << 32; | |
2401 | val |= obj->gtt_offset & 0xfffff000; | |
2402 | val |= (uint64_t)((obj->stride / 128) - 1) << | |
2403 | SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
4e901fdc | 2404 | |
9ce079e4 CW |
2405 | if (obj->tiling_mode == I915_TILING_Y) |
2406 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2407 | val |= I965_FENCE_REG_VALID; | |
2408 | } else | |
2409 | val = 0; | |
c6642782 | 2410 | |
9ce079e4 CW |
2411 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val); |
2412 | POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8); | |
4e901fdc EA |
2413 | } |
2414 | ||
9ce079e4 CW |
2415 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
2416 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2417 | { |
de151cf6 | 2418 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
2419 | uint64_t val; |
2420 | ||
9ce079e4 CW |
2421 | if (obj) { |
2422 | u32 size = obj->gtt_space->size; | |
de151cf6 | 2423 | |
9ce079e4 CW |
2424 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
2425 | 0xfffff000) << 32; | |
2426 | val |= obj->gtt_offset & 0xfffff000; | |
2427 | val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2428 | if (obj->tiling_mode == I915_TILING_Y) | |
2429 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2430 | val |= I965_FENCE_REG_VALID; | |
2431 | } else | |
2432 | val = 0; | |
c6642782 | 2433 | |
9ce079e4 CW |
2434 | I915_WRITE64(FENCE_REG_965_0 + reg * 8, val); |
2435 | POSTING_READ(FENCE_REG_965_0 + reg * 8); | |
de151cf6 JB |
2436 | } |
2437 | ||
9ce079e4 CW |
2438 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
2439 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2440 | { |
de151cf6 | 2441 | drm_i915_private_t *dev_priv = dev->dev_private; |
9ce079e4 | 2442 | u32 val; |
de151cf6 | 2443 | |
9ce079e4 CW |
2444 | if (obj) { |
2445 | u32 size = obj->gtt_space->size; | |
2446 | int pitch_val; | |
2447 | int tile_width; | |
c6642782 | 2448 | |
9ce079e4 CW |
2449 | WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
2450 | (size & -size) != size || | |
2451 | (obj->gtt_offset & (size - 1)), | |
2452 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2453 | obj->gtt_offset, obj->map_and_fenceable, size); | |
c6642782 | 2454 | |
9ce079e4 CW |
2455 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
2456 | tile_width = 128; | |
2457 | else | |
2458 | tile_width = 512; | |
2459 | ||
2460 | /* Note: pitch better be a power of two tile widths */ | |
2461 | pitch_val = obj->stride / tile_width; | |
2462 | pitch_val = ffs(pitch_val) - 1; | |
2463 | ||
2464 | val = obj->gtt_offset; | |
2465 | if (obj->tiling_mode == I915_TILING_Y) | |
2466 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2467 | val |= I915_FENCE_SIZE_BITS(size); | |
2468 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2469 | val |= I830_FENCE_REG_VALID; | |
2470 | } else | |
2471 | val = 0; | |
2472 | ||
2473 | if (reg < 8) | |
2474 | reg = FENCE_REG_830_0 + reg * 4; | |
2475 | else | |
2476 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
2477 | ||
2478 | I915_WRITE(reg, val); | |
2479 | POSTING_READ(reg); | |
de151cf6 JB |
2480 | } |
2481 | ||
9ce079e4 CW |
2482 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
2483 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2484 | { |
de151cf6 | 2485 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 | 2486 | uint32_t val; |
de151cf6 | 2487 | |
9ce079e4 CW |
2488 | if (obj) { |
2489 | u32 size = obj->gtt_space->size; | |
2490 | uint32_t pitch_val; | |
de151cf6 | 2491 | |
9ce079e4 CW |
2492 | WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
2493 | (size & -size) != size || | |
2494 | (obj->gtt_offset & (size - 1)), | |
2495 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", | |
2496 | obj->gtt_offset, size); | |
e76a16de | 2497 | |
9ce079e4 CW |
2498 | pitch_val = obj->stride / 128; |
2499 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2500 | |
9ce079e4 CW |
2501 | val = obj->gtt_offset; |
2502 | if (obj->tiling_mode == I915_TILING_Y) | |
2503 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2504 | val |= I830_FENCE_SIZE_BITS(size); | |
2505 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2506 | val |= I830_FENCE_REG_VALID; | |
2507 | } else | |
2508 | val = 0; | |
c6642782 | 2509 | |
9ce079e4 CW |
2510 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
2511 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
2512 | } | |
2513 | ||
2514 | static void i915_gem_write_fence(struct drm_device *dev, int reg, | |
2515 | struct drm_i915_gem_object *obj) | |
2516 | { | |
2517 | switch (INTEL_INFO(dev)->gen) { | |
2518 | case 7: | |
2519 | case 6: sandybridge_write_fence_reg(dev, reg, obj); break; | |
2520 | case 5: | |
2521 | case 4: i965_write_fence_reg(dev, reg, obj); break; | |
2522 | case 3: i915_write_fence_reg(dev, reg, obj); break; | |
2523 | case 2: i830_write_fence_reg(dev, reg, obj); break; | |
2524 | default: break; | |
2525 | } | |
de151cf6 JB |
2526 | } |
2527 | ||
61050808 CW |
2528 | static inline int fence_number(struct drm_i915_private *dev_priv, |
2529 | struct drm_i915_fence_reg *fence) | |
2530 | { | |
2531 | return fence - dev_priv->fence_regs; | |
2532 | } | |
2533 | ||
2534 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
2535 | struct drm_i915_fence_reg *fence, | |
2536 | bool enable) | |
2537 | { | |
2538 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2539 | int reg = fence_number(dev_priv, fence); | |
2540 | ||
2541 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
2542 | ||
2543 | if (enable) { | |
2544 | obj->fence_reg = reg; | |
2545 | fence->obj = obj; | |
2546 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
2547 | } else { | |
2548 | obj->fence_reg = I915_FENCE_REG_NONE; | |
2549 | fence->obj = NULL; | |
2550 | list_del_init(&fence->lru_list); | |
2551 | } | |
2552 | } | |
2553 | ||
d9e86c0e | 2554 | static int |
a360bb1a | 2555 | i915_gem_object_flush_fence(struct drm_i915_gem_object *obj) |
d9e86c0e CW |
2556 | { |
2557 | int ret; | |
2558 | ||
2559 | if (obj->fenced_gpu_access) { | |
88241785 | 2560 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
1c293ea3 | 2561 | ret = i915_gem_flush_ring(obj->ring, |
88241785 CW |
2562 | 0, obj->base.write_domain); |
2563 | if (ret) | |
2564 | return ret; | |
2565 | } | |
d9e86c0e CW |
2566 | |
2567 | obj->fenced_gpu_access = false; | |
2568 | } | |
2569 | ||
1c293ea3 | 2570 | if (obj->last_fenced_seqno) { |
199b2bc2 | 2571 | ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
18991845 CW |
2572 | if (ret) |
2573 | return ret; | |
d9e86c0e CW |
2574 | |
2575 | obj->last_fenced_seqno = 0; | |
d9e86c0e CW |
2576 | } |
2577 | ||
63256ec5 CW |
2578 | /* Ensure that all CPU reads are completed before installing a fence |
2579 | * and all writes before removing the fence. | |
2580 | */ | |
2581 | if (obj->base.read_domains & I915_GEM_DOMAIN_GTT) | |
2582 | mb(); | |
2583 | ||
d9e86c0e CW |
2584 | return 0; |
2585 | } | |
2586 | ||
2587 | int | |
2588 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
2589 | { | |
61050808 | 2590 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
d9e86c0e CW |
2591 | int ret; |
2592 | ||
a360bb1a | 2593 | ret = i915_gem_object_flush_fence(obj); |
d9e86c0e CW |
2594 | if (ret) |
2595 | return ret; | |
2596 | ||
61050808 CW |
2597 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
2598 | return 0; | |
d9e86c0e | 2599 | |
61050808 CW |
2600 | i915_gem_object_update_fence(obj, |
2601 | &dev_priv->fence_regs[obj->fence_reg], | |
2602 | false); | |
2603 | i915_gem_object_fence_lost(obj); | |
d9e86c0e CW |
2604 | |
2605 | return 0; | |
2606 | } | |
2607 | ||
2608 | static struct drm_i915_fence_reg * | |
a360bb1a | 2609 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 2610 | { |
ae3db24a | 2611 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 2612 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 2613 | int i; |
ae3db24a DV |
2614 | |
2615 | /* First try to find a free reg */ | |
d9e86c0e | 2616 | avail = NULL; |
ae3db24a DV |
2617 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2618 | reg = &dev_priv->fence_regs[i]; | |
2619 | if (!reg->obj) | |
d9e86c0e | 2620 | return reg; |
ae3db24a | 2621 | |
1690e1eb | 2622 | if (!reg->pin_count) |
d9e86c0e | 2623 | avail = reg; |
ae3db24a DV |
2624 | } |
2625 | ||
d9e86c0e CW |
2626 | if (avail == NULL) |
2627 | return NULL; | |
ae3db24a DV |
2628 | |
2629 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 2630 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 2631 | if (reg->pin_count) |
ae3db24a DV |
2632 | continue; |
2633 | ||
8fe301ad | 2634 | return reg; |
ae3db24a DV |
2635 | } |
2636 | ||
8fe301ad | 2637 | return NULL; |
ae3db24a DV |
2638 | } |
2639 | ||
de151cf6 | 2640 | /** |
9a5a53b3 | 2641 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
2642 | * @obj: object to map through a fence reg |
2643 | * | |
2644 | * When mapping objects through the GTT, userspace wants to be able to write | |
2645 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
2646 | * This function walks the fence regs looking for a free one for @obj, |
2647 | * stealing one if it can't find any. | |
2648 | * | |
2649 | * It then sets up the reg based on the object's properties: address, pitch | |
2650 | * and tiling format. | |
9a5a53b3 CW |
2651 | * |
2652 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 2653 | */ |
8c4b8c3f | 2654 | int |
06d98131 | 2655 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 2656 | { |
05394f39 | 2657 | struct drm_device *dev = obj->base.dev; |
79e53945 | 2658 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 2659 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 2660 | struct drm_i915_fence_reg *reg; |
ae3db24a | 2661 | int ret; |
de151cf6 | 2662 | |
14415745 CW |
2663 | /* Have we updated the tiling parameters upon the object and so |
2664 | * will need to serialise the write to the associated fence register? | |
2665 | */ | |
5d82e3e6 | 2666 | if (obj->fence_dirty) { |
14415745 CW |
2667 | ret = i915_gem_object_flush_fence(obj); |
2668 | if (ret) | |
2669 | return ret; | |
2670 | } | |
9a5a53b3 | 2671 | |
d9e86c0e | 2672 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
2673 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2674 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 2675 | if (!obj->fence_dirty) { |
14415745 CW |
2676 | list_move_tail(®->lru_list, |
2677 | &dev_priv->mm.fence_list); | |
2678 | return 0; | |
2679 | } | |
2680 | } else if (enable) { | |
2681 | reg = i915_find_fence_reg(dev); | |
2682 | if (reg == NULL) | |
2683 | return -EDEADLK; | |
d9e86c0e | 2684 | |
14415745 CW |
2685 | if (reg->obj) { |
2686 | struct drm_i915_gem_object *old = reg->obj; | |
2687 | ||
2688 | ret = i915_gem_object_flush_fence(old); | |
29c5a587 CW |
2689 | if (ret) |
2690 | return ret; | |
2691 | ||
14415745 | 2692 | i915_gem_object_fence_lost(old); |
29c5a587 | 2693 | } |
14415745 | 2694 | } else |
a09ba7fa | 2695 | return 0; |
a09ba7fa | 2696 | |
14415745 | 2697 | i915_gem_object_update_fence(obj, reg, enable); |
5d82e3e6 | 2698 | obj->fence_dirty = false; |
14415745 | 2699 | |
9ce079e4 | 2700 | return 0; |
de151cf6 JB |
2701 | } |
2702 | ||
673a394b EA |
2703 | /** |
2704 | * Finds free space in the GTT aperture and binds the object there. | |
2705 | */ | |
2706 | static int | |
05394f39 | 2707 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
920afa77 | 2708 | unsigned alignment, |
75e9e915 | 2709 | bool map_and_fenceable) |
673a394b | 2710 | { |
05394f39 | 2711 | struct drm_device *dev = obj->base.dev; |
673a394b | 2712 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 2713 | struct drm_mm_node *free_space; |
a00b10c3 | 2714 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
5e783301 | 2715 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
75e9e915 | 2716 | bool mappable, fenceable; |
07f73f69 | 2717 | int ret; |
673a394b | 2718 | |
05394f39 | 2719 | if (obj->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2720 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2721 | return -EINVAL; | |
2722 | } | |
2723 | ||
e28f8711 CW |
2724 | fence_size = i915_gem_get_gtt_size(dev, |
2725 | obj->base.size, | |
2726 | obj->tiling_mode); | |
2727 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
2728 | obj->base.size, | |
2729 | obj->tiling_mode); | |
2730 | unfenced_alignment = | |
2731 | i915_gem_get_unfenced_gtt_alignment(dev, | |
2732 | obj->base.size, | |
2733 | obj->tiling_mode); | |
a00b10c3 | 2734 | |
673a394b | 2735 | if (alignment == 0) |
5e783301 DV |
2736 | alignment = map_and_fenceable ? fence_alignment : |
2737 | unfenced_alignment; | |
75e9e915 | 2738 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
2739 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2740 | return -EINVAL; | |
2741 | } | |
2742 | ||
05394f39 | 2743 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 2744 | |
654fc607 CW |
2745 | /* If the object is bigger than the entire aperture, reject it early |
2746 | * before evicting everything in a vain attempt to find space. | |
2747 | */ | |
05394f39 | 2748 | if (obj->base.size > |
75e9e915 | 2749 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
654fc607 CW |
2750 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2751 | return -E2BIG; | |
2752 | } | |
2753 | ||
673a394b | 2754 | search_free: |
75e9e915 | 2755 | if (map_and_fenceable) |
920afa77 DV |
2756 | free_space = |
2757 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, | |
6b9d89b4 CW |
2758 | size, alignment, |
2759 | 0, dev_priv->mm.gtt_mappable_end, | |
920afa77 DV |
2760 | 0); |
2761 | else | |
2762 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2763 | size, alignment, 0); |
920afa77 DV |
2764 | |
2765 | if (free_space != NULL) { | |
75e9e915 | 2766 | if (map_and_fenceable) |
05394f39 | 2767 | obj->gtt_space = |
920afa77 | 2768 | drm_mm_get_block_range_generic(free_space, |
a00b10c3 | 2769 | size, alignment, 0, |
6b9d89b4 | 2770 | 0, dev_priv->mm.gtt_mappable_end, |
920afa77 DV |
2771 | 0); |
2772 | else | |
05394f39 | 2773 | obj->gtt_space = |
a00b10c3 | 2774 | drm_mm_get_block(free_space, size, alignment); |
920afa77 | 2775 | } |
05394f39 | 2776 | if (obj->gtt_space == NULL) { |
673a394b EA |
2777 | /* If the gtt is empty and we're still having trouble |
2778 | * fitting our object in, we're out of memory. | |
2779 | */ | |
75e9e915 DV |
2780 | ret = i915_gem_evict_something(dev, size, alignment, |
2781 | map_and_fenceable); | |
9731129c | 2782 | if (ret) |
673a394b | 2783 | return ret; |
9731129c | 2784 | |
673a394b EA |
2785 | goto search_free; |
2786 | } | |
2787 | ||
e5281ccd | 2788 | ret = i915_gem_object_get_pages_gtt(obj, gfpmask); |
673a394b | 2789 | if (ret) { |
05394f39 CW |
2790 | drm_mm_put_block(obj->gtt_space); |
2791 | obj->gtt_space = NULL; | |
07f73f69 CW |
2792 | |
2793 | if (ret == -ENOMEM) { | |
809b6334 CW |
2794 | /* first try to reclaim some memory by clearing the GTT */ |
2795 | ret = i915_gem_evict_everything(dev, false); | |
07f73f69 | 2796 | if (ret) { |
07f73f69 | 2797 | /* now try to shrink everyone else */ |
4bdadb97 CW |
2798 | if (gfpmask) { |
2799 | gfpmask = 0; | |
2800 | goto search_free; | |
07f73f69 CW |
2801 | } |
2802 | ||
809b6334 | 2803 | return -ENOMEM; |
07f73f69 CW |
2804 | } |
2805 | ||
2806 | goto search_free; | |
2807 | } | |
2808 | ||
673a394b EA |
2809 | return ret; |
2810 | } | |
2811 | ||
74163907 | 2812 | ret = i915_gem_gtt_prepare_object(obj); |
7c2e6fdf | 2813 | if (ret) { |
e5281ccd | 2814 | i915_gem_object_put_pages_gtt(obj); |
05394f39 CW |
2815 | drm_mm_put_block(obj->gtt_space); |
2816 | obj->gtt_space = NULL; | |
07f73f69 | 2817 | |
809b6334 | 2818 | if (i915_gem_evict_everything(dev, false)) |
07f73f69 | 2819 | return ret; |
07f73f69 CW |
2820 | |
2821 | goto search_free; | |
673a394b | 2822 | } |
673a394b | 2823 | |
0ebb9829 DV |
2824 | if (!dev_priv->mm.aliasing_ppgtt) |
2825 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
673a394b | 2826 | |
6299f992 | 2827 | list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list); |
05394f39 | 2828 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
bf1a1092 | 2829 | |
673a394b EA |
2830 | /* Assert that the object is not currently in any GPU domain. As it |
2831 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2832 | * a GPU cache | |
2833 | */ | |
05394f39 CW |
2834 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
2835 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2836 | |
6299f992 | 2837 | obj->gtt_offset = obj->gtt_space->start; |
1c5d22f7 | 2838 | |
75e9e915 | 2839 | fenceable = |
05394f39 | 2840 | obj->gtt_space->size == fence_size && |
0206e353 | 2841 | (obj->gtt_space->start & (fence_alignment - 1)) == 0; |
a00b10c3 | 2842 | |
75e9e915 | 2843 | mappable = |
05394f39 | 2844 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
a00b10c3 | 2845 | |
05394f39 | 2846 | obj->map_and_fenceable = mappable && fenceable; |
75e9e915 | 2847 | |
db53a302 | 2848 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
673a394b EA |
2849 | return 0; |
2850 | } | |
2851 | ||
2852 | void | |
05394f39 | 2853 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
673a394b | 2854 | { |
673a394b EA |
2855 | /* If we don't have a page list set up, then we're not pinned |
2856 | * to GPU, and we can ignore the cache flush because it'll happen | |
2857 | * again at bind time. | |
2858 | */ | |
05394f39 | 2859 | if (obj->pages == NULL) |
673a394b EA |
2860 | return; |
2861 | ||
9c23f7fc CW |
2862 | /* If the GPU is snooping the contents of the CPU cache, |
2863 | * we do not need to manually clear the CPU cache lines. However, | |
2864 | * the caches are only snooped when the render cache is | |
2865 | * flushed/invalidated. As we always have to emit invalidations | |
2866 | * and flushes when moving into and out of the RENDER domain, correct | |
2867 | * snooping behaviour occurs naturally as the result of our domain | |
2868 | * tracking. | |
2869 | */ | |
2870 | if (obj->cache_level != I915_CACHE_NONE) | |
2871 | return; | |
2872 | ||
1c5d22f7 | 2873 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2874 | |
05394f39 | 2875 | drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE); |
673a394b EA |
2876 | } |
2877 | ||
e47c68e9 | 2878 | /** Flushes any GPU write domain for the object if it's dirty. */ |
88241785 | 2879 | static int |
3619df03 | 2880 | i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2881 | { |
05394f39 | 2882 | if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) |
88241785 | 2883 | return 0; |
e47c68e9 EA |
2884 | |
2885 | /* Queue the GPU write cache flushing we need. */ | |
db53a302 | 2886 | return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
e47c68e9 EA |
2887 | } |
2888 | ||
2889 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2890 | static void | |
05394f39 | 2891 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2892 | { |
1c5d22f7 CW |
2893 | uint32_t old_write_domain; |
2894 | ||
05394f39 | 2895 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
2896 | return; |
2897 | ||
63256ec5 | 2898 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
2899 | * to it immediately go to main memory as far as we know, so there's |
2900 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
2901 | * |
2902 | * However, we do have to enforce the order so that all writes through | |
2903 | * the GTT land before any writes to the device, such as updates to | |
2904 | * the GATT itself. | |
e47c68e9 | 2905 | */ |
63256ec5 CW |
2906 | wmb(); |
2907 | ||
05394f39 CW |
2908 | old_write_domain = obj->base.write_domain; |
2909 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2910 | |
2911 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2912 | obj->base.read_domains, |
1c5d22f7 | 2913 | old_write_domain); |
e47c68e9 EA |
2914 | } |
2915 | ||
2916 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2917 | static void | |
05394f39 | 2918 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2919 | { |
1c5d22f7 | 2920 | uint32_t old_write_domain; |
e47c68e9 | 2921 | |
05394f39 | 2922 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
2923 | return; |
2924 | ||
2925 | i915_gem_clflush_object(obj); | |
40ce6575 | 2926 | intel_gtt_chipset_flush(); |
05394f39 CW |
2927 | old_write_domain = obj->base.write_domain; |
2928 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2929 | |
2930 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2931 | obj->base.read_domains, |
1c5d22f7 | 2932 | old_write_domain); |
e47c68e9 EA |
2933 | } |
2934 | ||
2ef7eeaa EA |
2935 | /** |
2936 | * Moves a single object to the GTT read, and possibly write domain. | |
2937 | * | |
2938 | * This function returns when the move is complete, including waiting on | |
2939 | * flushes to occur. | |
2940 | */ | |
79e53945 | 2941 | int |
2021746e | 2942 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 2943 | { |
8325a09d | 2944 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
1c5d22f7 | 2945 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2946 | int ret; |
2ef7eeaa | 2947 | |
02354392 | 2948 | /* Not valid to be called on unbound objects. */ |
05394f39 | 2949 | if (obj->gtt_space == NULL) |
02354392 EA |
2950 | return -EINVAL; |
2951 | ||
8d7e3de1 CW |
2952 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
2953 | return 0; | |
2954 | ||
88241785 CW |
2955 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
2956 | if (ret) | |
2957 | return ret; | |
2958 | ||
0201f1ec CW |
2959 | ret = i915_gem_object_wait_rendering(obj, !write); |
2960 | if (ret) | |
2961 | return ret; | |
2dafb1e0 | 2962 | |
7213342d | 2963 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 2964 | |
05394f39 CW |
2965 | old_write_domain = obj->base.write_domain; |
2966 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 2967 | |
e47c68e9 EA |
2968 | /* It should now be out of any other write domains, and we can update |
2969 | * the domain values for our changes. | |
2970 | */ | |
05394f39 CW |
2971 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
2972 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 2973 | if (write) { |
05394f39 CW |
2974 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
2975 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
2976 | obj->dirty = 1; | |
2ef7eeaa EA |
2977 | } |
2978 | ||
1c5d22f7 CW |
2979 | trace_i915_gem_object_change_domain(obj, |
2980 | old_read_domains, | |
2981 | old_write_domain); | |
2982 | ||
8325a09d CW |
2983 | /* And bump the LRU for this access */ |
2984 | if (i915_gem_object_is_inactive(obj)) | |
2985 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
2986 | ||
e47c68e9 EA |
2987 | return 0; |
2988 | } | |
2989 | ||
e4ffd173 CW |
2990 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
2991 | enum i915_cache_level cache_level) | |
2992 | { | |
7bddb01f DV |
2993 | struct drm_device *dev = obj->base.dev; |
2994 | drm_i915_private_t *dev_priv = dev->dev_private; | |
e4ffd173 CW |
2995 | int ret; |
2996 | ||
2997 | if (obj->cache_level == cache_level) | |
2998 | return 0; | |
2999 | ||
3000 | if (obj->pin_count) { | |
3001 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
3002 | return -EBUSY; | |
3003 | } | |
3004 | ||
3005 | if (obj->gtt_space) { | |
3006 | ret = i915_gem_object_finish_gpu(obj); | |
3007 | if (ret) | |
3008 | return ret; | |
3009 | ||
3010 | i915_gem_object_finish_gtt(obj); | |
3011 | ||
3012 | /* Before SandyBridge, you could not use tiling or fence | |
3013 | * registers with snooped memory, so relinquish any fences | |
3014 | * currently pointing to our region in the aperture. | |
3015 | */ | |
3016 | if (INTEL_INFO(obj->base.dev)->gen < 6) { | |
3017 | ret = i915_gem_object_put_fence(obj); | |
3018 | if (ret) | |
3019 | return ret; | |
3020 | } | |
3021 | ||
74898d7e DV |
3022 | if (obj->has_global_gtt_mapping) |
3023 | i915_gem_gtt_bind_object(obj, cache_level); | |
7bddb01f DV |
3024 | if (obj->has_aliasing_ppgtt_mapping) |
3025 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
3026 | obj, cache_level); | |
e4ffd173 CW |
3027 | } |
3028 | ||
3029 | if (cache_level == I915_CACHE_NONE) { | |
3030 | u32 old_read_domains, old_write_domain; | |
3031 | ||
3032 | /* If we're coming from LLC cached, then we haven't | |
3033 | * actually been tracking whether the data is in the | |
3034 | * CPU cache or not, since we only allow one bit set | |
3035 | * in obj->write_domain and have been skipping the clflushes. | |
3036 | * Just set it to the CPU cache for now. | |
3037 | */ | |
3038 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); | |
3039 | WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); | |
3040 | ||
3041 | old_read_domains = obj->base.read_domains; | |
3042 | old_write_domain = obj->base.write_domain; | |
3043 | ||
3044 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
3045 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
3046 | ||
3047 | trace_i915_gem_object_change_domain(obj, | |
3048 | old_read_domains, | |
3049 | old_write_domain); | |
3050 | } | |
3051 | ||
3052 | obj->cache_level = cache_level; | |
3053 | return 0; | |
3054 | } | |
3055 | ||
b9241ea3 | 3056 | /* |
2da3b9b9 CW |
3057 | * Prepare buffer for display plane (scanout, cursors, etc). |
3058 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3059 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3060 | */ |
3061 | int | |
2da3b9b9 CW |
3062 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3063 | u32 alignment, | |
919926ae | 3064 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 3065 | { |
2da3b9b9 | 3066 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3067 | int ret; |
3068 | ||
88241785 CW |
3069 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
3070 | if (ret) | |
3071 | return ret; | |
3072 | ||
0be73284 | 3073 | if (pipelined != obj->ring) { |
2911a35b BW |
3074 | ret = i915_gem_object_sync(obj, pipelined); |
3075 | if (ret) | |
b9241ea3 ZW |
3076 | return ret; |
3077 | } | |
3078 | ||
a7ef0640 EA |
3079 | /* The display engine is not coherent with the LLC cache on gen6. As |
3080 | * a result, we make sure that the pinning that is about to occur is | |
3081 | * done with uncached PTEs. This is lowest common denominator for all | |
3082 | * chipsets. | |
3083 | * | |
3084 | * However for gen6+, we could do better by using the GFDT bit instead | |
3085 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3086 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3087 | */ | |
3088 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); | |
3089 | if (ret) | |
3090 | return ret; | |
3091 | ||
2da3b9b9 CW |
3092 | /* As the user may map the buffer once pinned in the display plane |
3093 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3094 | * always use map_and_fenceable for all scanout buffers. | |
3095 | */ | |
3096 | ret = i915_gem_object_pin(obj, alignment, true); | |
3097 | if (ret) | |
3098 | return ret; | |
3099 | ||
b118c1e3 CW |
3100 | i915_gem_object_flush_cpu_write_domain(obj); |
3101 | ||
2da3b9b9 | 3102 | old_write_domain = obj->base.write_domain; |
05394f39 | 3103 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3104 | |
3105 | /* It should now be out of any other write domains, and we can update | |
3106 | * the domain values for our changes. | |
3107 | */ | |
e5f1d962 | 3108 | obj->base.write_domain = 0; |
05394f39 | 3109 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3110 | |
3111 | trace_i915_gem_object_change_domain(obj, | |
3112 | old_read_domains, | |
2da3b9b9 | 3113 | old_write_domain); |
b9241ea3 ZW |
3114 | |
3115 | return 0; | |
3116 | } | |
3117 | ||
85345517 | 3118 | int |
a8198eea | 3119 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3120 | { |
88241785 CW |
3121 | int ret; |
3122 | ||
a8198eea | 3123 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
3124 | return 0; |
3125 | ||
88241785 | 3126 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 3127 | ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
88241785 CW |
3128 | if (ret) |
3129 | return ret; | |
3130 | } | |
85345517 | 3131 | |
0201f1ec | 3132 | ret = i915_gem_object_wait_rendering(obj, false); |
c501ae7f CW |
3133 | if (ret) |
3134 | return ret; | |
3135 | ||
a8198eea CW |
3136 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3137 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 3138 | return 0; |
85345517 CW |
3139 | } |
3140 | ||
e47c68e9 EA |
3141 | /** |
3142 | * Moves a single object to the CPU read, and possibly write domain. | |
3143 | * | |
3144 | * This function returns when the move is complete, including waiting on | |
3145 | * flushes to occur. | |
3146 | */ | |
dabdfe02 | 3147 | int |
919926ae | 3148 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3149 | { |
1c5d22f7 | 3150 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3151 | int ret; |
3152 | ||
8d7e3de1 CW |
3153 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3154 | return 0; | |
3155 | ||
88241785 CW |
3156 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
3157 | if (ret) | |
3158 | return ret; | |
3159 | ||
0201f1ec CW |
3160 | ret = i915_gem_object_wait_rendering(obj, !write); |
3161 | if (ret) | |
3162 | return ret; | |
2ef7eeaa | 3163 | |
e47c68e9 | 3164 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3165 | |
05394f39 CW |
3166 | old_write_domain = obj->base.write_domain; |
3167 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3168 | |
e47c68e9 | 3169 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3170 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2ef7eeaa | 3171 | i915_gem_clflush_object(obj); |
2ef7eeaa | 3172 | |
05394f39 | 3173 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3174 | } |
3175 | ||
3176 | /* It should now be out of any other write domains, and we can update | |
3177 | * the domain values for our changes. | |
3178 | */ | |
05394f39 | 3179 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3180 | |
3181 | /* If we're writing through the CPU, then the GPU read domains will | |
3182 | * need to be invalidated at next use. | |
3183 | */ | |
3184 | if (write) { | |
05394f39 CW |
3185 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3186 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3187 | } |
2ef7eeaa | 3188 | |
1c5d22f7 CW |
3189 | trace_i915_gem_object_change_domain(obj, |
3190 | old_read_domains, | |
3191 | old_write_domain); | |
3192 | ||
2ef7eeaa EA |
3193 | return 0; |
3194 | } | |
3195 | ||
673a394b EA |
3196 | /* Throttle our rendering by waiting until the ring has completed our requests |
3197 | * emitted over 20 msec ago. | |
3198 | * | |
b962442e EA |
3199 | * Note that if we were to use the current jiffies each time around the loop, |
3200 | * we wouldn't escape the function with any frames outstanding if the time to | |
3201 | * render a frame was over 20ms. | |
3202 | * | |
673a394b EA |
3203 | * This should get us reasonable parallelism between CPU and GPU but also |
3204 | * relatively low latency when blocking on a particular request to finish. | |
3205 | */ | |
40a5f0de | 3206 | static int |
f787a5f5 | 3207 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3208 | { |
f787a5f5 CW |
3209 | struct drm_i915_private *dev_priv = dev->dev_private; |
3210 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3211 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3212 | struct drm_i915_gem_request *request; |
3213 | struct intel_ring_buffer *ring = NULL; | |
3214 | u32 seqno = 0; | |
3215 | int ret; | |
93533c29 | 3216 | |
e110e8d6 CW |
3217 | if (atomic_read(&dev_priv->mm.wedged)) |
3218 | return -EIO; | |
3219 | ||
1c25595f | 3220 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3221 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3222 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3223 | break; | |
40a5f0de | 3224 | |
f787a5f5 CW |
3225 | ring = request->ring; |
3226 | seqno = request->seqno; | |
b962442e | 3227 | } |
1c25595f | 3228 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3229 | |
f787a5f5 CW |
3230 | if (seqno == 0) |
3231 | return 0; | |
2bc43b5c | 3232 | |
5c81fe85 | 3233 | ret = __wait_seqno(ring, seqno, true, NULL); |
f787a5f5 CW |
3234 | if (ret == 0) |
3235 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3236 | |
3237 | return ret; | |
3238 | } | |
3239 | ||
673a394b | 3240 | int |
05394f39 CW |
3241 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
3242 | uint32_t alignment, | |
75e9e915 | 3243 | bool map_and_fenceable) |
673a394b | 3244 | { |
673a394b EA |
3245 | int ret; |
3246 | ||
05394f39 | 3247 | BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
ac0c6b5a | 3248 | |
05394f39 CW |
3249 | if (obj->gtt_space != NULL) { |
3250 | if ((alignment && obj->gtt_offset & (alignment - 1)) || | |
3251 | (map_and_fenceable && !obj->map_and_fenceable)) { | |
3252 | WARN(obj->pin_count, | |
ae7d49d8 | 3253 | "bo is already pinned with incorrect alignment:" |
75e9e915 DV |
3254 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
3255 | " obj->map_and_fenceable=%d\n", | |
05394f39 | 3256 | obj->gtt_offset, alignment, |
75e9e915 | 3257 | map_and_fenceable, |
05394f39 | 3258 | obj->map_and_fenceable); |
ac0c6b5a CW |
3259 | ret = i915_gem_object_unbind(obj); |
3260 | if (ret) | |
3261 | return ret; | |
3262 | } | |
3263 | } | |
3264 | ||
05394f39 | 3265 | if (obj->gtt_space == NULL) { |
a00b10c3 | 3266 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
75e9e915 | 3267 | map_and_fenceable); |
9731129c | 3268 | if (ret) |
673a394b | 3269 | return ret; |
22c344e9 | 3270 | } |
76446cac | 3271 | |
74898d7e DV |
3272 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
3273 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
3274 | ||
1b50247a | 3275 | obj->pin_count++; |
6299f992 | 3276 | obj->pin_mappable |= map_and_fenceable; |
673a394b EA |
3277 | |
3278 | return 0; | |
3279 | } | |
3280 | ||
3281 | void | |
05394f39 | 3282 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3283 | { |
05394f39 CW |
3284 | BUG_ON(obj->pin_count == 0); |
3285 | BUG_ON(obj->gtt_space == NULL); | |
673a394b | 3286 | |
1b50247a | 3287 | if (--obj->pin_count == 0) |
6299f992 | 3288 | obj->pin_mappable = false; |
673a394b EA |
3289 | } |
3290 | ||
3291 | int | |
3292 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3293 | struct drm_file *file) |
673a394b EA |
3294 | { |
3295 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3296 | struct drm_i915_gem_object *obj; |
673a394b EA |
3297 | int ret; |
3298 | ||
1d7cfea1 CW |
3299 | ret = i915_mutex_lock_interruptible(dev); |
3300 | if (ret) | |
3301 | return ret; | |
673a394b | 3302 | |
05394f39 | 3303 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3304 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3305 | ret = -ENOENT; |
3306 | goto unlock; | |
673a394b | 3307 | } |
673a394b | 3308 | |
05394f39 | 3309 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 3310 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
3311 | ret = -EINVAL; |
3312 | goto out; | |
3ef94daa CW |
3313 | } |
3314 | ||
05394f39 | 3315 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
3316 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3317 | args->handle); | |
1d7cfea1 CW |
3318 | ret = -EINVAL; |
3319 | goto out; | |
79e53945 JB |
3320 | } |
3321 | ||
05394f39 CW |
3322 | obj->user_pin_count++; |
3323 | obj->pin_filp = file; | |
3324 | if (obj->user_pin_count == 1) { | |
75e9e915 | 3325 | ret = i915_gem_object_pin(obj, args->alignment, true); |
1d7cfea1 CW |
3326 | if (ret) |
3327 | goto out; | |
673a394b EA |
3328 | } |
3329 | ||
3330 | /* XXX - flush the CPU caches for pinned objects | |
3331 | * as the X server doesn't manage domains yet | |
3332 | */ | |
e47c68e9 | 3333 | i915_gem_object_flush_cpu_write_domain(obj); |
05394f39 | 3334 | args->offset = obj->gtt_offset; |
1d7cfea1 | 3335 | out: |
05394f39 | 3336 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3337 | unlock: |
673a394b | 3338 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3339 | return ret; |
673a394b EA |
3340 | } |
3341 | ||
3342 | int | |
3343 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3344 | struct drm_file *file) |
673a394b EA |
3345 | { |
3346 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3347 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3348 | int ret; |
673a394b | 3349 | |
1d7cfea1 CW |
3350 | ret = i915_mutex_lock_interruptible(dev); |
3351 | if (ret) | |
3352 | return ret; | |
673a394b | 3353 | |
05394f39 | 3354 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3355 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3356 | ret = -ENOENT; |
3357 | goto unlock; | |
673a394b | 3358 | } |
76c1dec1 | 3359 | |
05394f39 | 3360 | if (obj->pin_filp != file) { |
79e53945 JB |
3361 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3362 | args->handle); | |
1d7cfea1 CW |
3363 | ret = -EINVAL; |
3364 | goto out; | |
79e53945 | 3365 | } |
05394f39 CW |
3366 | obj->user_pin_count--; |
3367 | if (obj->user_pin_count == 0) { | |
3368 | obj->pin_filp = NULL; | |
79e53945 JB |
3369 | i915_gem_object_unpin(obj); |
3370 | } | |
673a394b | 3371 | |
1d7cfea1 | 3372 | out: |
05394f39 | 3373 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3374 | unlock: |
673a394b | 3375 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3376 | return ret; |
673a394b EA |
3377 | } |
3378 | ||
3379 | int | |
3380 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3381 | struct drm_file *file) |
673a394b EA |
3382 | { |
3383 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3384 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3385 | int ret; |
3386 | ||
76c1dec1 | 3387 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3388 | if (ret) |
76c1dec1 | 3389 | return ret; |
673a394b | 3390 | |
05394f39 | 3391 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3392 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3393 | ret = -ENOENT; |
3394 | goto unlock; | |
673a394b | 3395 | } |
d1b851fc | 3396 | |
0be555b6 CW |
3397 | /* Count all active objects as busy, even if they are currently not used |
3398 | * by the gpu. Users of this interface expect objects to eventually | |
3399 | * become non-busy without any further actions, therefore emit any | |
3400 | * necessary flushes here. | |
c4de0a5d | 3401 | */ |
30dfebf3 | 3402 | ret = i915_gem_object_flush_active(obj); |
0be555b6 | 3403 | |
30dfebf3 | 3404 | args->busy = obj->active; |
e9808edd CW |
3405 | if (obj->ring) { |
3406 | BUILD_BUG_ON(I915_NUM_RINGS > 16); | |
3407 | args->busy |= intel_ring_flag(obj->ring) << 16; | |
3408 | } | |
673a394b | 3409 | |
05394f39 | 3410 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3411 | unlock: |
673a394b | 3412 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3413 | return ret; |
673a394b EA |
3414 | } |
3415 | ||
3416 | int | |
3417 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3418 | struct drm_file *file_priv) | |
3419 | { | |
0206e353 | 3420 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3421 | } |
3422 | ||
3ef94daa CW |
3423 | int |
3424 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3425 | struct drm_file *file_priv) | |
3426 | { | |
3427 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 3428 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3429 | int ret; |
3ef94daa CW |
3430 | |
3431 | switch (args->madv) { | |
3432 | case I915_MADV_DONTNEED: | |
3433 | case I915_MADV_WILLNEED: | |
3434 | break; | |
3435 | default: | |
3436 | return -EINVAL; | |
3437 | } | |
3438 | ||
1d7cfea1 CW |
3439 | ret = i915_mutex_lock_interruptible(dev); |
3440 | if (ret) | |
3441 | return ret; | |
3442 | ||
05394f39 | 3443 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 3444 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3445 | ret = -ENOENT; |
3446 | goto unlock; | |
3ef94daa | 3447 | } |
3ef94daa | 3448 | |
05394f39 | 3449 | if (obj->pin_count) { |
1d7cfea1 CW |
3450 | ret = -EINVAL; |
3451 | goto out; | |
3ef94daa CW |
3452 | } |
3453 | ||
05394f39 CW |
3454 | if (obj->madv != __I915_MADV_PURGED) |
3455 | obj->madv = args->madv; | |
3ef94daa | 3456 | |
2d7ef395 | 3457 | /* if the object is no longer bound, discard its backing storage */ |
05394f39 CW |
3458 | if (i915_gem_object_is_purgeable(obj) && |
3459 | obj->gtt_space == NULL) | |
2d7ef395 CW |
3460 | i915_gem_object_truncate(obj); |
3461 | ||
05394f39 | 3462 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 3463 | |
1d7cfea1 | 3464 | out: |
05394f39 | 3465 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3466 | unlock: |
3ef94daa | 3467 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3468 | return ret; |
3ef94daa CW |
3469 | } |
3470 | ||
05394f39 CW |
3471 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
3472 | size_t size) | |
ac52bc56 | 3473 | { |
73aa808f | 3474 | struct drm_i915_private *dev_priv = dev->dev_private; |
c397b908 | 3475 | struct drm_i915_gem_object *obj; |
5949eac4 | 3476 | struct address_space *mapping; |
bed1ea95 | 3477 | u32 mask; |
ac52bc56 | 3478 | |
c397b908 DV |
3479 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
3480 | if (obj == NULL) | |
3481 | return NULL; | |
673a394b | 3482 | |
c397b908 DV |
3483 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
3484 | kfree(obj); | |
3485 | return NULL; | |
3486 | } | |
673a394b | 3487 | |
bed1ea95 CW |
3488 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
3489 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
3490 | /* 965gm cannot relocate objects above 4GiB. */ | |
3491 | mask &= ~__GFP_HIGHMEM; | |
3492 | mask |= __GFP_DMA32; | |
3493 | } | |
3494 | ||
5949eac4 | 3495 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
bed1ea95 | 3496 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 3497 | |
73aa808f CW |
3498 | i915_gem_info_add_obj(dev_priv, size); |
3499 | ||
c397b908 DV |
3500 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3501 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 3502 | |
3d29b842 ED |
3503 | if (HAS_LLC(dev)) { |
3504 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
3505 | * cache) for about a 10% performance improvement |
3506 | * compared to uncached. Graphics requests other than | |
3507 | * display scanout are coherent with the CPU in | |
3508 | * accessing this cache. This means in this mode we | |
3509 | * don't need to clflush on the CPU side, and on the | |
3510 | * GPU side we only need to flush internal caches to | |
3511 | * get data visible to the CPU. | |
3512 | * | |
3513 | * However, we maintain the display planes as UC, and so | |
3514 | * need to rebind when first used as such. | |
3515 | */ | |
3516 | obj->cache_level = I915_CACHE_LLC; | |
3517 | } else | |
3518 | obj->cache_level = I915_CACHE_NONE; | |
3519 | ||
62b8b215 | 3520 | obj->base.driver_private = NULL; |
c397b908 | 3521 | obj->fence_reg = I915_FENCE_REG_NONE; |
69dc4987 | 3522 | INIT_LIST_HEAD(&obj->mm_list); |
93a37f20 | 3523 | INIT_LIST_HEAD(&obj->gtt_list); |
69dc4987 | 3524 | INIT_LIST_HEAD(&obj->ring_list); |
432e58ed | 3525 | INIT_LIST_HEAD(&obj->exec_list); |
c397b908 | 3526 | INIT_LIST_HEAD(&obj->gpu_write_list); |
c397b908 | 3527 | obj->madv = I915_MADV_WILLNEED; |
75e9e915 DV |
3528 | /* Avoid an unnecessary call to unbind on the first bind. */ |
3529 | obj->map_and_fenceable = true; | |
de151cf6 | 3530 | |
05394f39 | 3531 | return obj; |
c397b908 DV |
3532 | } |
3533 | ||
3534 | int i915_gem_init_object(struct drm_gem_object *obj) | |
3535 | { | |
3536 | BUG(); | |
de151cf6 | 3537 | |
673a394b EA |
3538 | return 0; |
3539 | } | |
3540 | ||
1488fc08 | 3541 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 3542 | { |
1488fc08 | 3543 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 3544 | struct drm_device *dev = obj->base.dev; |
be72615b | 3545 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 3546 | |
26e12f89 CW |
3547 | trace_i915_gem_object_destroy(obj); |
3548 | ||
1286ff73 DV |
3549 | if (gem_obj->import_attach) |
3550 | drm_prime_gem_destroy(gem_obj, obj->sg_table); | |
3551 | ||
1488fc08 CW |
3552 | if (obj->phys_obj) |
3553 | i915_gem_detach_phys_object(dev, obj); | |
3554 | ||
3555 | obj->pin_count = 0; | |
3556 | if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) { | |
3557 | bool was_interruptible; | |
3558 | ||
3559 | was_interruptible = dev_priv->mm.interruptible; | |
3560 | dev_priv->mm.interruptible = false; | |
3561 | ||
3562 | WARN_ON(i915_gem_object_unbind(obj)); | |
3563 | ||
3564 | dev_priv->mm.interruptible = was_interruptible; | |
3565 | } | |
3566 | ||
05394f39 | 3567 | if (obj->base.map_list.map) |
b464e9a2 | 3568 | drm_gem_free_mmap_offset(&obj->base); |
de151cf6 | 3569 | |
05394f39 CW |
3570 | drm_gem_object_release(&obj->base); |
3571 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 3572 | |
05394f39 CW |
3573 | kfree(obj->bit_17); |
3574 | kfree(obj); | |
673a394b EA |
3575 | } |
3576 | ||
29105ccc CW |
3577 | int |
3578 | i915_gem_idle(struct drm_device *dev) | |
3579 | { | |
3580 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3581 | int ret; | |
28dfe52a | 3582 | |
29105ccc | 3583 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 3584 | |
87acb0a5 | 3585 | if (dev_priv->mm.suspended) { |
29105ccc CW |
3586 | mutex_unlock(&dev->struct_mutex); |
3587 | return 0; | |
28dfe52a EA |
3588 | } |
3589 | ||
b2da9fe5 | 3590 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
3591 | if (ret) { |
3592 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 3593 | return ret; |
6dbe2772 | 3594 | } |
b2da9fe5 | 3595 | i915_gem_retire_requests(dev); |
673a394b | 3596 | |
29105ccc | 3597 | /* Under UMS, be paranoid and evict. */ |
a39d7efc CW |
3598 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
3599 | i915_gem_evict_everything(dev, false); | |
29105ccc | 3600 | |
312817a3 CW |
3601 | i915_gem_reset_fences(dev); |
3602 | ||
29105ccc CW |
3603 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
3604 | * We need to replace this with a semaphore, or something. | |
3605 | * And not confound mm.suspended! | |
3606 | */ | |
3607 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 3608 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
3609 | |
3610 | i915_kernel_lost_context(dev); | |
6dbe2772 | 3611 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 3612 | |
6dbe2772 KP |
3613 | mutex_unlock(&dev->struct_mutex); |
3614 | ||
29105ccc CW |
3615 | /* Cancel the retire work handler, which should be idle now. */ |
3616 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
3617 | ||
673a394b EA |
3618 | return 0; |
3619 | } | |
3620 | ||
b9524a1e BW |
3621 | void i915_gem_l3_remap(struct drm_device *dev) |
3622 | { | |
3623 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3624 | u32 misccpctl; | |
3625 | int i; | |
3626 | ||
3627 | if (!IS_IVYBRIDGE(dev)) | |
3628 | return; | |
3629 | ||
3630 | if (!dev_priv->mm.l3_remap_info) | |
3631 | return; | |
3632 | ||
3633 | misccpctl = I915_READ(GEN7_MISCCPCTL); | |
3634 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
3635 | POSTING_READ(GEN7_MISCCPCTL); | |
3636 | ||
3637 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { | |
3638 | u32 remap = I915_READ(GEN7_L3LOG_BASE + i); | |
3639 | if (remap && remap != dev_priv->mm.l3_remap_info[i/4]) | |
3640 | DRM_DEBUG("0x%x was already programmed to %x\n", | |
3641 | GEN7_L3LOG_BASE + i, remap); | |
3642 | if (remap && !dev_priv->mm.l3_remap_info[i/4]) | |
3643 | DRM_DEBUG_DRIVER("Clearing remapped register\n"); | |
3644 | I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->mm.l3_remap_info[i/4]); | |
3645 | } | |
3646 | ||
3647 | /* Make sure all the writes land before disabling dop clock gating */ | |
3648 | POSTING_READ(GEN7_L3LOG_BASE); | |
3649 | ||
3650 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); | |
3651 | } | |
3652 | ||
f691e2f4 DV |
3653 | void i915_gem_init_swizzling(struct drm_device *dev) |
3654 | { | |
3655 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3656 | ||
11782b02 | 3657 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
3658 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
3659 | return; | |
3660 | ||
3661 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
3662 | DISP_TILE_SURFACE_SWIZZLING); | |
3663 | ||
11782b02 DV |
3664 | if (IS_GEN5(dev)) |
3665 | return; | |
3666 | ||
f691e2f4 DV |
3667 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
3668 | if (IS_GEN6(dev)) | |
6b26c86d | 3669 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
f691e2f4 | 3670 | else |
6b26c86d | 3671 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
f691e2f4 | 3672 | } |
e21af88d DV |
3673 | |
3674 | void i915_gem_init_ppgtt(struct drm_device *dev) | |
3675 | { | |
3676 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3677 | uint32_t pd_offset; | |
3678 | struct intel_ring_buffer *ring; | |
55a254ac DV |
3679 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
3680 | uint32_t __iomem *pd_addr; | |
3681 | uint32_t pd_entry; | |
e21af88d DV |
3682 | int i; |
3683 | ||
3684 | if (!dev_priv->mm.aliasing_ppgtt) | |
3685 | return; | |
3686 | ||
55a254ac DV |
3687 | |
3688 | pd_addr = dev_priv->mm.gtt->gtt + ppgtt->pd_offset/sizeof(uint32_t); | |
3689 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
3690 | dma_addr_t pt_addr; | |
3691 | ||
3692 | if (dev_priv->mm.gtt->needs_dmar) | |
3693 | pt_addr = ppgtt->pt_dma_addr[i]; | |
3694 | else | |
3695 | pt_addr = page_to_phys(ppgtt->pt_pages[i]); | |
3696 | ||
3697 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
3698 | pd_entry |= GEN6_PDE_VALID; | |
3699 | ||
3700 | writel(pd_entry, pd_addr + i); | |
3701 | } | |
3702 | readl(pd_addr); | |
3703 | ||
3704 | pd_offset = ppgtt->pd_offset; | |
e21af88d DV |
3705 | pd_offset /= 64; /* in cachelines, */ |
3706 | pd_offset <<= 16; | |
3707 | ||
3708 | if (INTEL_INFO(dev)->gen == 6) { | |
48ecfa10 DV |
3709 | uint32_t ecochk, gab_ctl, ecobits; |
3710 | ||
3711 | ecobits = I915_READ(GAC_ECO_BITS); | |
3712 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
be901a5a DV |
3713 | |
3714 | gab_ctl = I915_READ(GAB_CTL); | |
3715 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
3716 | ||
3717 | ecochk = I915_READ(GAM_ECOCHK); | |
e21af88d DV |
3718 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | |
3719 | ECOCHK_PPGTT_CACHE64B); | |
6b26c86d | 3720 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
e21af88d DV |
3721 | } else if (INTEL_INFO(dev)->gen >= 7) { |
3722 | I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B); | |
3723 | /* GFX_MODE is per-ring on gen7+ */ | |
3724 | } | |
3725 | ||
b4519513 | 3726 | for_each_ring(ring, dev_priv, i) { |
e21af88d DV |
3727 | if (INTEL_INFO(dev)->gen >= 7) |
3728 | I915_WRITE(RING_MODE_GEN7(ring), | |
6b26c86d | 3729 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
e21af88d DV |
3730 | |
3731 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
3732 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); | |
3733 | } | |
3734 | } | |
3735 | ||
67b1b571 CW |
3736 | static bool |
3737 | intel_enable_blt(struct drm_device *dev) | |
3738 | { | |
3739 | if (!HAS_BLT(dev)) | |
3740 | return false; | |
3741 | ||
3742 | /* The blitter was dysfunctional on early prototypes */ | |
3743 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { | |
3744 | DRM_INFO("BLT not supported on this pre-production hardware;" | |
3745 | " graphics performance will be degraded.\n"); | |
3746 | return false; | |
3747 | } | |
3748 | ||
3749 | return true; | |
3750 | } | |
3751 | ||
8187a2b7 | 3752 | int |
f691e2f4 | 3753 | i915_gem_init_hw(struct drm_device *dev) |
8187a2b7 ZN |
3754 | { |
3755 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3756 | int ret; | |
68f95ba9 | 3757 | |
8ecd1a66 DV |
3758 | if (!intel_enable_gtt()) |
3759 | return -EIO; | |
3760 | ||
b9524a1e BW |
3761 | i915_gem_l3_remap(dev); |
3762 | ||
f691e2f4 DV |
3763 | i915_gem_init_swizzling(dev); |
3764 | ||
5c1143bb | 3765 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 3766 | if (ret) |
b6913e4b | 3767 | return ret; |
68f95ba9 CW |
3768 | |
3769 | if (HAS_BSD(dev)) { | |
5c1143bb | 3770 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
3771 | if (ret) |
3772 | goto cleanup_render_ring; | |
d1b851fc | 3773 | } |
68f95ba9 | 3774 | |
67b1b571 | 3775 | if (intel_enable_blt(dev)) { |
549f7365 CW |
3776 | ret = intel_init_blt_ring_buffer(dev); |
3777 | if (ret) | |
3778 | goto cleanup_bsd_ring; | |
3779 | } | |
3780 | ||
6f392d54 CW |
3781 | dev_priv->next_seqno = 1; |
3782 | ||
254f965c BW |
3783 | /* |
3784 | * XXX: There was some w/a described somewhere suggesting loading | |
3785 | * contexts before PPGTT. | |
3786 | */ | |
3787 | i915_gem_context_init(dev); | |
e21af88d DV |
3788 | i915_gem_init_ppgtt(dev); |
3789 | ||
68f95ba9 CW |
3790 | return 0; |
3791 | ||
549f7365 | 3792 | cleanup_bsd_ring: |
1ec14ad3 | 3793 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
68f95ba9 | 3794 | cleanup_render_ring: |
1ec14ad3 | 3795 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
8187a2b7 ZN |
3796 | return ret; |
3797 | } | |
3798 | ||
1070a42b CW |
3799 | static bool |
3800 | intel_enable_ppgtt(struct drm_device *dev) | |
3801 | { | |
3802 | if (i915_enable_ppgtt >= 0) | |
3803 | return i915_enable_ppgtt; | |
3804 | ||
3805 | #ifdef CONFIG_INTEL_IOMMU | |
3806 | /* Disable ppgtt on SNB if VT-d is on. */ | |
3807 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) | |
3808 | return false; | |
3809 | #endif | |
3810 | ||
3811 | return true; | |
3812 | } | |
3813 | ||
3814 | int i915_gem_init(struct drm_device *dev) | |
3815 | { | |
3816 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3817 | unsigned long gtt_size, mappable_size; | |
3818 | int ret; | |
3819 | ||
3820 | gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT; | |
3821 | mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; | |
3822 | ||
3823 | mutex_lock(&dev->struct_mutex); | |
3824 | if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { | |
3825 | /* PPGTT pdes are stolen from global gtt ptes, so shrink the | |
3826 | * aperture accordingly when using aliasing ppgtt. */ | |
3827 | gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE; | |
3828 | ||
3829 | i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size); | |
3830 | ||
3831 | ret = i915_gem_init_aliasing_ppgtt(dev); | |
3832 | if (ret) { | |
3833 | mutex_unlock(&dev->struct_mutex); | |
3834 | return ret; | |
3835 | } | |
3836 | } else { | |
3837 | /* Let GEM Manage all of the aperture. | |
3838 | * | |
3839 | * However, leave one page at the end still bound to the scratch | |
3840 | * page. There are a number of places where the hardware | |
3841 | * apparently prefetches past the end of the object, and we've | |
3842 | * seen multiple hangs with the GPU head pointer stuck in a | |
3843 | * batchbuffer bound at the last page of the aperture. One page | |
3844 | * should be enough to keep any prefetching inside of the | |
3845 | * aperture. | |
3846 | */ | |
3847 | i915_gem_init_global_gtt(dev, 0, mappable_size, | |
3848 | gtt_size); | |
3849 | } | |
3850 | ||
3851 | ret = i915_gem_init_hw(dev); | |
3852 | mutex_unlock(&dev->struct_mutex); | |
3853 | if (ret) { | |
3854 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
3855 | return ret; | |
3856 | } | |
3857 | ||
53ca26ca DV |
3858 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
3859 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) | |
3860 | dev_priv->dri1.allow_batchbuffer = 1; | |
1070a42b CW |
3861 | return 0; |
3862 | } | |
3863 | ||
8187a2b7 ZN |
3864 | void |
3865 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
3866 | { | |
3867 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 3868 | struct intel_ring_buffer *ring; |
1ec14ad3 | 3869 | int i; |
8187a2b7 | 3870 | |
b4519513 CW |
3871 | for_each_ring(ring, dev_priv, i) |
3872 | intel_cleanup_ring_buffer(ring); | |
8187a2b7 ZN |
3873 | } |
3874 | ||
673a394b EA |
3875 | int |
3876 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
3877 | struct drm_file *file_priv) | |
3878 | { | |
3879 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 3880 | int ret; |
673a394b | 3881 | |
79e53945 JB |
3882 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3883 | return 0; | |
3884 | ||
ba1234d1 | 3885 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 3886 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 3887 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
3888 | } |
3889 | ||
673a394b | 3890 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
3891 | dev_priv->mm.suspended = 0; |
3892 | ||
f691e2f4 | 3893 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
3894 | if (ret != 0) { |
3895 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 3896 | return ret; |
d816f6ac | 3897 | } |
9bb2d6f9 | 3898 | |
69dc4987 | 3899 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
673a394b EA |
3900 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
3901 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
673a394b | 3902 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 3903 | |
5f35308b CW |
3904 | ret = drm_irq_install(dev); |
3905 | if (ret) | |
3906 | goto cleanup_ringbuffer; | |
dbb19d30 | 3907 | |
673a394b | 3908 | return 0; |
5f35308b CW |
3909 | |
3910 | cleanup_ringbuffer: | |
3911 | mutex_lock(&dev->struct_mutex); | |
3912 | i915_gem_cleanup_ringbuffer(dev); | |
3913 | dev_priv->mm.suspended = 1; | |
3914 | mutex_unlock(&dev->struct_mutex); | |
3915 | ||
3916 | return ret; | |
673a394b EA |
3917 | } |
3918 | ||
3919 | int | |
3920 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
3921 | struct drm_file *file_priv) | |
3922 | { | |
79e53945 JB |
3923 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3924 | return 0; | |
3925 | ||
dbb19d30 | 3926 | drm_irq_uninstall(dev); |
e6890f6f | 3927 | return i915_gem_idle(dev); |
673a394b EA |
3928 | } |
3929 | ||
3930 | void | |
3931 | i915_gem_lastclose(struct drm_device *dev) | |
3932 | { | |
3933 | int ret; | |
673a394b | 3934 | |
e806b495 EA |
3935 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3936 | return; | |
3937 | ||
6dbe2772 KP |
3938 | ret = i915_gem_idle(dev); |
3939 | if (ret) | |
3940 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
3941 | } |
3942 | ||
64193406 CW |
3943 | static void |
3944 | init_ring_lists(struct intel_ring_buffer *ring) | |
3945 | { | |
3946 | INIT_LIST_HEAD(&ring->active_list); | |
3947 | INIT_LIST_HEAD(&ring->request_list); | |
3948 | INIT_LIST_HEAD(&ring->gpu_write_list); | |
3949 | } | |
3950 | ||
673a394b EA |
3951 | void |
3952 | i915_gem_load(struct drm_device *dev) | |
3953 | { | |
b5aa8a0f | 3954 | int i; |
673a394b EA |
3955 | drm_i915_private_t *dev_priv = dev->dev_private; |
3956 | ||
69dc4987 | 3957 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b EA |
3958 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
3959 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); | |
a09ba7fa | 3960 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
93a37f20 | 3961 | INIT_LIST_HEAD(&dev_priv->mm.gtt_list); |
1ec14ad3 CW |
3962 | for (i = 0; i < I915_NUM_RINGS; i++) |
3963 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 3964 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 3965 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
3966 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
3967 | i915_gem_retire_work_handler); | |
30dbf0c0 | 3968 | init_completion(&dev_priv->error_completion); |
31169714 | 3969 | |
94400120 DA |
3970 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
3971 | if (IS_GEN3(dev)) { | |
50743298 DV |
3972 | I915_WRITE(MI_ARB_STATE, |
3973 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
94400120 DA |
3974 | } |
3975 | ||
72bfa19c CW |
3976 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
3977 | ||
de151cf6 | 3978 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
3979 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
3980 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 3981 | |
a6c45cf0 | 3982 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
3983 | dev_priv->num_fence_regs = 16; |
3984 | else | |
3985 | dev_priv->num_fence_regs = 8; | |
3986 | ||
b5aa8a0f | 3987 | /* Initialize fence registers to zero */ |
ada726c7 | 3988 | i915_gem_reset_fences(dev); |
10ed13e4 | 3989 | |
673a394b | 3990 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 3991 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 3992 | |
ce453d81 CW |
3993 | dev_priv->mm.interruptible = true; |
3994 | ||
17250b71 CW |
3995 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
3996 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
3997 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 3998 | } |
71acb5eb DA |
3999 | |
4000 | /* | |
4001 | * Create a physically contiguous memory object for this object | |
4002 | * e.g. for cursor + overlay regs | |
4003 | */ | |
995b6762 CW |
4004 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4005 | int id, int size, int align) | |
71acb5eb DA |
4006 | { |
4007 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4008 | struct drm_i915_gem_phys_object *phys_obj; | |
4009 | int ret; | |
4010 | ||
4011 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4012 | return 0; | |
4013 | ||
9a298b2a | 4014 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4015 | if (!phys_obj) |
4016 | return -ENOMEM; | |
4017 | ||
4018 | phys_obj->id = id; | |
4019 | ||
6eeefaf3 | 4020 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4021 | if (!phys_obj->handle) { |
4022 | ret = -ENOMEM; | |
4023 | goto kfree_obj; | |
4024 | } | |
4025 | #ifdef CONFIG_X86 | |
4026 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4027 | #endif | |
4028 | ||
4029 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4030 | ||
4031 | return 0; | |
4032 | kfree_obj: | |
9a298b2a | 4033 | kfree(phys_obj); |
71acb5eb DA |
4034 | return ret; |
4035 | } | |
4036 | ||
995b6762 | 4037 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4038 | { |
4039 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4040 | struct drm_i915_gem_phys_object *phys_obj; | |
4041 | ||
4042 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4043 | return; | |
4044 | ||
4045 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4046 | if (phys_obj->cur_obj) { | |
4047 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4048 | } | |
4049 | ||
4050 | #ifdef CONFIG_X86 | |
4051 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4052 | #endif | |
4053 | drm_pci_free(dev, phys_obj->handle); | |
4054 | kfree(phys_obj); | |
4055 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4056 | } | |
4057 | ||
4058 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4059 | { | |
4060 | int i; | |
4061 | ||
260883c8 | 4062 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4063 | i915_gem_free_phys_object(dev, i); |
4064 | } | |
4065 | ||
4066 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 4067 | struct drm_i915_gem_object *obj) |
71acb5eb | 4068 | { |
05394f39 | 4069 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
e5281ccd | 4070 | char *vaddr; |
71acb5eb | 4071 | int i; |
71acb5eb DA |
4072 | int page_count; |
4073 | ||
05394f39 | 4074 | if (!obj->phys_obj) |
71acb5eb | 4075 | return; |
05394f39 | 4076 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 4077 | |
05394f39 | 4078 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 4079 | for (i = 0; i < page_count; i++) { |
5949eac4 | 4080 | struct page *page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4081 | if (!IS_ERR(page)) { |
4082 | char *dst = kmap_atomic(page); | |
4083 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
4084 | kunmap_atomic(dst); | |
4085 | ||
4086 | drm_clflush_pages(&page, 1); | |
4087 | ||
4088 | set_page_dirty(page); | |
4089 | mark_page_accessed(page); | |
4090 | page_cache_release(page); | |
4091 | } | |
71acb5eb | 4092 | } |
40ce6575 | 4093 | intel_gtt_chipset_flush(); |
d78b47b9 | 4094 | |
05394f39 CW |
4095 | obj->phys_obj->cur_obj = NULL; |
4096 | obj->phys_obj = NULL; | |
71acb5eb DA |
4097 | } |
4098 | ||
4099 | int | |
4100 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 4101 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
4102 | int id, |
4103 | int align) | |
71acb5eb | 4104 | { |
05394f39 | 4105 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
71acb5eb | 4106 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
4107 | int ret = 0; |
4108 | int page_count; | |
4109 | int i; | |
4110 | ||
4111 | if (id > I915_MAX_PHYS_OBJECT) | |
4112 | return -EINVAL; | |
4113 | ||
05394f39 CW |
4114 | if (obj->phys_obj) { |
4115 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
4116 | return 0; |
4117 | i915_gem_detach_phys_object(dev, obj); | |
4118 | } | |
4119 | ||
71acb5eb DA |
4120 | /* create a new object */ |
4121 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4122 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 4123 | obj->base.size, align); |
71acb5eb | 4124 | if (ret) { |
05394f39 CW |
4125 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
4126 | id, obj->base.size); | |
e5281ccd | 4127 | return ret; |
71acb5eb DA |
4128 | } |
4129 | } | |
4130 | ||
4131 | /* bind to the object */ | |
05394f39 CW |
4132 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
4133 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 4134 | |
05394f39 | 4135 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
4136 | |
4137 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4138 | struct page *page; |
4139 | char *dst, *src; | |
4140 | ||
5949eac4 | 4141 | page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4142 | if (IS_ERR(page)) |
4143 | return PTR_ERR(page); | |
71acb5eb | 4144 | |
ff75b9bc | 4145 | src = kmap_atomic(page); |
05394f39 | 4146 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 4147 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 4148 | kunmap_atomic(src); |
71acb5eb | 4149 | |
e5281ccd CW |
4150 | mark_page_accessed(page); |
4151 | page_cache_release(page); | |
4152 | } | |
d78b47b9 | 4153 | |
71acb5eb | 4154 | return 0; |
71acb5eb DA |
4155 | } |
4156 | ||
4157 | static int | |
05394f39 CW |
4158 | i915_gem_phys_pwrite(struct drm_device *dev, |
4159 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
4160 | struct drm_i915_gem_pwrite *args, |
4161 | struct drm_file *file_priv) | |
4162 | { | |
05394f39 | 4163 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
b47b30cc | 4164 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
71acb5eb | 4165 | |
b47b30cc CW |
4166 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
4167 | unsigned long unwritten; | |
4168 | ||
4169 | /* The physical object once assigned is fixed for the lifetime | |
4170 | * of the obj, so we can safely drop the lock and continue | |
4171 | * to access vaddr. | |
4172 | */ | |
4173 | mutex_unlock(&dev->struct_mutex); | |
4174 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
4175 | mutex_lock(&dev->struct_mutex); | |
4176 | if (unwritten) | |
4177 | return -EFAULT; | |
4178 | } | |
71acb5eb | 4179 | |
40ce6575 | 4180 | intel_gtt_chipset_flush(); |
71acb5eb DA |
4181 | return 0; |
4182 | } | |
b962442e | 4183 | |
f787a5f5 | 4184 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4185 | { |
f787a5f5 | 4186 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4187 | |
4188 | /* Clean up our request list when the client is going away, so that | |
4189 | * later retire_requests won't dereference our soon-to-be-gone | |
4190 | * file_priv. | |
4191 | */ | |
1c25595f | 4192 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4193 | while (!list_empty(&file_priv->mm.request_list)) { |
4194 | struct drm_i915_gem_request *request; | |
4195 | ||
4196 | request = list_first_entry(&file_priv->mm.request_list, | |
4197 | struct drm_i915_gem_request, | |
4198 | client_list); | |
4199 | list_del(&request->client_list); | |
4200 | request->file_priv = NULL; | |
4201 | } | |
1c25595f | 4202 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4203 | } |
31169714 | 4204 | |
1637ef41 CW |
4205 | static int |
4206 | i915_gpu_is_active(struct drm_device *dev) | |
4207 | { | |
4208 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4209 | int lists_empty; | |
4210 | ||
1637ef41 | 4211 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
17250b71 | 4212 | list_empty(&dev_priv->mm.active_list); |
1637ef41 CW |
4213 | |
4214 | return !lists_empty; | |
4215 | } | |
4216 | ||
31169714 | 4217 | static int |
1495f230 | 4218 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 4219 | { |
17250b71 CW |
4220 | struct drm_i915_private *dev_priv = |
4221 | container_of(shrinker, | |
4222 | struct drm_i915_private, | |
4223 | mm.inactive_shrinker); | |
4224 | struct drm_device *dev = dev_priv->dev; | |
4225 | struct drm_i915_gem_object *obj, *next; | |
1495f230 | 4226 | int nr_to_scan = sc->nr_to_scan; |
17250b71 CW |
4227 | int cnt; |
4228 | ||
4229 | if (!mutex_trylock(&dev->struct_mutex)) | |
bbe2e11a | 4230 | return 0; |
31169714 CW |
4231 | |
4232 | /* "fast-path" to count number of available objects */ | |
4233 | if (nr_to_scan == 0) { | |
17250b71 CW |
4234 | cnt = 0; |
4235 | list_for_each_entry(obj, | |
4236 | &dev_priv->mm.inactive_list, | |
4237 | mm_list) | |
4238 | cnt++; | |
4239 | mutex_unlock(&dev->struct_mutex); | |
4240 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 CW |
4241 | } |
4242 | ||
1637ef41 | 4243 | rescan: |
31169714 | 4244 | /* first scan for clean buffers */ |
17250b71 | 4245 | i915_gem_retire_requests(dev); |
31169714 | 4246 | |
17250b71 CW |
4247 | list_for_each_entry_safe(obj, next, |
4248 | &dev_priv->mm.inactive_list, | |
4249 | mm_list) { | |
4250 | if (i915_gem_object_is_purgeable(obj)) { | |
2021746e CW |
4251 | if (i915_gem_object_unbind(obj) == 0 && |
4252 | --nr_to_scan == 0) | |
17250b71 | 4253 | break; |
31169714 | 4254 | } |
31169714 CW |
4255 | } |
4256 | ||
4257 | /* second pass, evict/count anything still on the inactive list */ | |
17250b71 CW |
4258 | cnt = 0; |
4259 | list_for_each_entry_safe(obj, next, | |
4260 | &dev_priv->mm.inactive_list, | |
4261 | mm_list) { | |
2021746e CW |
4262 | if (nr_to_scan && |
4263 | i915_gem_object_unbind(obj) == 0) | |
17250b71 | 4264 | nr_to_scan--; |
2021746e | 4265 | else |
17250b71 CW |
4266 | cnt++; |
4267 | } | |
4268 | ||
4269 | if (nr_to_scan && i915_gpu_is_active(dev)) { | |
1637ef41 CW |
4270 | /* |
4271 | * We are desperate for pages, so as a last resort, wait | |
4272 | * for the GPU to finish and discard whatever we can. | |
4273 | * This has a dramatic impact to reduce the number of | |
4274 | * OOM-killer events whilst running the GPU aggressively. | |
4275 | */ | |
b2da9fe5 | 4276 | if (i915_gpu_idle(dev) == 0) |
1637ef41 CW |
4277 | goto rescan; |
4278 | } | |
17250b71 CW |
4279 | mutex_unlock(&dev->struct_mutex); |
4280 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 | 4281 | } |