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Linux 6.11-rc7
[linux-block.git] / drivers / gpu / drm / i915 / i915_drv.h
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1da177e4
LT		 1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
0d6aa60b 3/*
bc54fd1a 4 *
1da177e4
LT		 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
bc54fd1a
DA		 7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
0d6aa60b 28 */
1da177e4
LT		 29
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
e9b73c67
CW		 33#include <uapi/drm/i915_drm.h>
34
9ee32fea 35#include <linux/pm_qos.h>
e73bdd20 36
d1487389 37#include <drm/ttm/ttm_device.h>
e73bdd20 38
acc855d3 39#include "display/intel_display_limits.h"
3b10f851 40#include "display/intel_display_core.h"
df0566a6 41
6401fafb 42#include "gem/i915_gem_context_types.h"
be80bc36 43#include "gem/i915_gem_shrinker.h"
6401fafb
JN		 44#include "gem/i915_gem_stolen.h"
45
112ed2d3 46#include "gt/intel_engine.h"
e5be5c7a 47#include "gt/intel_gt_types.h"
f178b897 48#include "gt/intel_region_lmem.h"
112ed2d3 49#include "gt/intel_workarounds.h"
0f261b24 50#include "gt/uc/intel_uc.h"
112ed2d3 51
f052febd
JN		 52#include "soc/intel_pch.h"
53
5f0d4d14 54#include "i915_drm_client.h"
4feb2e9e
JN		 55#include "i915_gem.h"
56#include "i915_gpu_error.h"
57#include "i915_params.h"
58#include "i915_perf_types.h"
59#include "i915_scheduler.h"
60#include "i915_utils.h"
b978520d 61#include "intel_device_info.h"
7eb186bb 62#include "intel_memory_region.h"
0d5adc5f 63#include "intel_runtime_pm.h"
7eb186bb 64#include "intel_step.h"
3846a9b1 65#include "intel_uncore.h"
e73bdd20 66
edbb9242 67struct drm_i915_clock_gating_funcs;
2ecf64a0 68struct vlv_s0ix_state;
f67986b0 69struct intel_pxp;
5e5d2e20 70
95086cb9
JN		 71#define GEM_QUIRK_PIN_SWIZZLED_PAGES BIT(0)
72
1eca0778
JN		 73/* Data Stolen Memory (DSM) aka "i915 stolen memory" */
74struct i915_dsm {
75 /*
76 * The start and end of DSM which we can optionally use to create GEM
77 * objects backed by stolen memory.
78 *
79 * Note that usable_size tells us exactly how much of this we are
80 * actually allowed to use, given that some portion of it is in fact
81 * reserved for use by hardware functions.
82 */
83 struct resource stolen;
84
85 /*
86 * Reserved portion of DSM.
87 */
88 struct resource reserved;
89
90 /*
91 * Total size minus reserved ranges.
92 *
93 * DSM is segmented in hardware with different portions offlimits to
94 * certain functions.
95 *
96 * The drm_mm is initialised to the total accessible range, as found
97 * from the PCI config. On Broadwell+, this is further restricted to
98 * avoid the first page! The upper end of DSM is reserved for hardware
99 * functions and similarly removed from the accessible range.
100 */
101 resource_size_t usable_size;
102};
103
f4c956ad 104struct i915_suspend_saved_registers {
e948e994 105 u32 saveDSPARB;
ba8bbcf6
JB		 106 u32 saveSWF0[16];
107 u32 saveSWF1[16];
85fa792b 108 u32 saveSWF3[3];
9f49c376 109 u16 saveGCDGMBUS;
f4c956ad 110};
c85aa885 111
35a85ac6 112#define MAX_L3_SLICES 2
a4da4fa4 113struct intel_l3_parity {
35a85ac6 114 u32 *remap_info[MAX_L3_SLICES];
a4da4fa4 115 struct work_struct error_work;
35a85ac6 116 int which_slice;
a4da4fa4
DV		 117};
118
4b5aed62 119struct i915_gem_mm {
d57d4a1d
CT		 120 /*
121 * Shortcut for the stolen region. This points to either
122 * INTEL_REGION_STOLEN_SMEM for integrated platforms, or
123 * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't
124 * support stolen.
125 */
126 struct intel_memory_region *stolen_region;
4b5aed62
DV		 127 /** Memory allocator for GTT stolen memory */
128 struct drm_mm stolen;
92e97d2f
PZ		 129 /** Protects the usage of the GTT stolen memory allocator. This is
130 * always the inner lock when overlapping with struct_mutex. */
131 struct mutex stolen_lock;
132
f2123818
CW		 133 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
134 spinlock_t obj_lock;
135
4b5aed62 136 /**
ecab9be1 137 * List of objects which are purgeable.
4b5aed62 138 */
ecab9be1
CW		 139 struct list_head purge_list;
140
3b4fa964 141 /**
ecab9be1 142 * List of objects which have allocated pages and are shrinkable.
3b4fa964 143 */
ecab9be1 144 struct list_head shrink_list;
4b5aed62 145
fbbd37b3
CW		 146 /**
147 * List of objects which are pending destruction.
148 */
149 struct llist_head free_list;
2826d447 150 struct work_struct free_work;
c9c70471
CW		 151 /**
152 * Count of objects pending destructions. Used to skip needlessly
153 * waiting on an RCU barrier if no objects are waiting to be freed.
154 */
155 atomic_t free_count;
fbbd37b3 156
465c403c
MA		 157 /**
158 * tmpfs instance used for shmem backed objects
159 */
160 struct vfsmount *gemfs;
161
3aae9d08
AJ		 162 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
163
2cfcd32a 164 struct notifier_block oom_notifier;
e87666b5 165 struct notifier_block vmap_notifier;
583cc9e4 166 struct shrinker *shrinker;
4b5aed62 167
d82b4b26
CW		 168 /* shrinker accounting, also useful for userland debugging */
169 u64 shrink_memory;
170 u32 shrink_count;
4b5aed62
DV		 171};
172
cf9d2890 173struct i915_virtual_gpu {
52988009 174 struct mutex lock; /* serialises sending of g2v_notify command pkts */
cf9d2890 175 bool active;
8a4ab66f 176 u32 caps;
66e7a806
ZW		 177 u32 *initial_mmio;
178 u8 *initial_cfg_space;
8b750bf7 179 struct list_head entry;
cf9d2890
YZ		 180};
181
f05816cb
CW		 182struct i915_selftest_stash {
183 atomic_t counter;
d1487389 184 struct ida mock_region_instances;
f05816cb
CW		 185};
186
77fec556 187struct drm_i915_private {
8f460e2c
CW		 188 struct drm_device drm;
189
3b10f851
JN		 190 struct intel_display display;
191
7fb81e9d
DV		 192 /* FIXME: Device release actions should all be moved to drmm_ */
193 bool do_release;
194
8a25c4be
JN		 195 /* i915 device parameters */
196 struct i915_params params;
197
0c4f52ba 198 const struct intel_device_info *__info; /* Use INTEL_INFO() to access. */
0258404f 199 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
3fed1808 200 struct intel_driver_caps caps;
f4c956ad 201
1eca0778 202 struct i915_dsm dsm;
b1ace601 203
907b28c5 204 struct intel_uncore uncore;
0a9b2630 205 struct intel_uncore_mmio_debug mmio_debug;
f4c956ad 206
cf9d2890
YZ		 207 struct i915_virtual_gpu vgpu;
208
feddf6e8 209 struct intel_gvt *gvt;
0ad35fed 210
9bd5de4a
JN		 211 struct {
212 struct pci_dev *pdev;
213 struct resource mch_res;
214 bool mchbar_need_disable;
215 } gmch;
750e76b4 216
9c303439
MK		 217 /*
218 * Chaining user engines happens in multiple stages, starting with a
219 * simple lock-less linked list created by intel_engine_add_user(),
220 * which later gets sorted and converted to an intermediate regular
221 * list, just to be converted once again to its final rb tree structure
222 * in intel_engines_driver_register().
223 *
224 * Make sure to use the right iterator helper, depending on if the code
225 * in question runs before or after intel_engines_driver_register() --
226 * for_each_uabi_engine() can only be used afterwards!
227 */
228 union {
229 struct llist_head uabi_engines_llist;
230 struct list_head uabi_engines_list;
231 struct rb_root uabi_engines;
232 };
e2d0ff35 233 unsigned int engine_uabi_class_count[I915_LAST_UABI_ENGINE_CLASS + 1];
f4c956ad 234
f4c956ad
DV		 235 /* protects the irq masks */
236 spinlock_t irq_lock;
237
a580516d
VS		 238 /* Sideband mailbox protection */
239 struct mutex sb_lock;
a75d035f 240 struct pm_qos_request sb_qos;
f4c956ad
DV		 241
242 /** Cached value of IMR to avoid reads in updating the bitfield */
f25ae90f 243 u32 irq_mask;
f4c956ad 244
d9ceb816
JB		 245 bool preserve_bios_swizzle;
246
f4c956ad 247 unsigned int fsb_freq, mem_freq, is_ddr3;
8d96561a 248
6bcda4f0 249 unsigned int hpll_freq;
bfa7df01 250 unsigned int czclk_freq;
f4c956ad 251
645416f5
DV		 252 /**
253 * wq - Driver workqueue for GEM.
254 *
255 * NOTE: Work items scheduled here are not allowed to grab any modeset
256 * locks, for otherwise the flushing done in the pageflip code will
257 * result in deadlocks.
258 */
f4c956ad
DV		 259 struct workqueue_struct *wq;
260
848a4e5c
LC		 261 /**
262 * unordered_wq - internal workqueue for unordered work
263 *
264 * This workqueue should be used for all unordered work
265 * scheduling within i915, which used to be scheduled on the
266 * system_wq before moving to a driver instance due
267 * deprecation of flush_scheduled_work().
268 */
269 struct workqueue_struct *unordered_wq;
270
46d8e4a1 271 /* pm private clock gating functions */
eba4b796 272 const struct drm_i915_clock_gating_funcs *clock_gating_funcs;
46d8e4a1 273
f4c956ad
DV		 274 /* PCH chipset type */
275 enum intel_pch pch_type;
17a303ec 276 unsigned short pch_id;
f4c956ad 277
95086cb9 278 unsigned long gem_quirks;
f4c956ad 279
4b5aed62 280 struct i915_gem_mm mm;
8781342d 281
a4da4fa4
DV		 282 struct intel_l3_parity l3_parity;
283
f6ac993f
DCS		 284 /*
285 * edram size in MB.
286 * Cannot be determined by PCIID. You must always read a register.
287 */
288 u32 edram_size_mb;
59124506 289
99584db3 290 struct i915_gpu_error gpu_error;
ae681d96 291
842f1c8b 292 u32 suspend_count;
f4c956ad 293 struct i915_suspend_saved_registers regfile;
1bcd8688 294 struct vlv_s0ix_state *vlv_s0ix_state;
231f42a4 295
cbfa59d4 296 struct dram_info {
66a24509 297 bool wm_lv_0_adjust_needed;
cbfa59d4 298 u8 num_channels;
8a6c5447 299 bool symmetric_memory;
b185a352
VS		 300 enum intel_dram_type {
301 INTEL_DRAM_UNKNOWN,
302 INTEL_DRAM_DDR3,
303 INTEL_DRAM_DDR4,
304 INTEL_DRAM_LPDDR3,
1f1257a6
CT		 305 INTEL_DRAM_LPDDR4,
306 INTEL_DRAM_DDR5,
307 INTEL_DRAM_LPDDR5,
772933b3 308 INTEL_DRAM_GDDR,
b185a352 309 } type;
5d0c938e 310 u8 num_qgv_points;
192fbfb7 311 u8 num_psf_gv_points;
cbfa59d4
MK		 312 } dram_info;
313
1bf676cc 314 struct intel_runtime_pm runtime_pm;
8a187455 315
8f8b1171 316 struct i915_perf perf;
eec688e1 317
b3b088e2
DS		 318 struct i915_hwmon *hwmon;
319
bec68cc9
TU		 320 struct intel_gt *gt[I915_MAX_GT];
321
b770bcfa
AS		 322 struct kobject *sysfs_gt;
323
51aec8bf
MR		 324 /* Quick lookup of media GT (current platforms only have one) */
325 struct intel_gt *media_gt;
326
23c3c3d0 327 struct {
a4e7ccda
CW		 328 struct i915_gem_contexts {
329 spinlock_t lock; /* locks list */
330 struct list_head list;
a4e7ccda 331 } contexts;
f17b8980
CW		 332
333 /*
334 * We replace the local file with a global mappings as the
335 * backing storage for the mmap is on the device and not
336 * on the struct file, and we do not want to prolong the
337 * lifetime of the local fd. To minimise the number of
338 * anonymous inodes we create, we use a global singleton to
339 * share the global mapping.
340 */
341 struct file *mmap_singleton;
23c3c3d0 342 } gem;
a83014d3 343
f67986b0
AP		 344 struct intel_pxp *pxp;
345
ac1723c1
TZ		 346 bool irq_enabled;
347
b46a33e2
TU		 348 struct i915_pmu pmu;
349
d1487389
TH		 350 /* The TTM device structure. */
351 struct ttm_device bdev;
352
f05816cb
CW		 353 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
354
bdf1e7e3
DV		 355 /*
356 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
357 * will be rejected. Instead look for a better place.
358 */
77fec556 359};
1da177e4 360
2c1792a1
CW		 361static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
362{
091387c1 363 return container_of(dev, struct drm_i915_private, drm);
2c1792a1
CW		 364}
365
c49d13ee 366static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
888d0d42 367{
361f9dc2
CW		 368 return dev_get_drvdata(kdev);
369}
370
371static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
372{
373 return pci_get_drvdata(pdev);
888d0d42
ID		 374}
375
39fa9a7d 376static inline struct intel_gt *to_gt(const struct drm_i915_private *i915)
c0f0dab8 377{
14aebb78 378 return i915->gt[0];
c0f0dab8
MW		 379}
380
750e76b4
CW		 381#define rb_to_uabi_engine(rb) \
382 rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
383
384#define for_each_uabi_engine(engine__, i915__) \
385 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
386 (engine__); \
387 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
388
0c4f52ba 389#define INTEL_INFO(i915) ((i915)->__info)
66ca1d8f
AS		 390#define RUNTIME_INFO(i915) (&(i915)->__runtime)
391#define DRIVER_CAPS(i915) (&(i915)->caps)
50a0bc90 392
66ca1d8f 393#define INTEL_DEVID(i915) (RUNTIME_INFO(i915)->device_id)
cae5852d 394
ca6374e2 395#define IP_VER(ver, rel) ((ver) << 8 | (rel))
f3973035 396
f9e932a8
RS		 397#define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.ip.ver)
398#define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.ip.ver, \
399 RUNTIME_INFO(i915)->graphics.ip.rel)
93babb06
LDM		 400#define IS_GRAPHICS_VER(i915, from, until) \
401 (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
402
f9e932a8
RS		 403#define MEDIA_VER(i915) (RUNTIME_INFO(i915)->media.ip.ver)
404#define MEDIA_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
405 RUNTIME_INFO(i915)->media.ip.rel)
93babb06
LDM		 406#define IS_MEDIA_VER(i915, from, until) \
407 (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
408
66ca1d8f 409#define INTEL_REVID(i915) (to_pci_dev((i915)->drm.dev)->revision)
ac657f64 410
26475ca9 411#define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
c1f110ee 412#define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step)
e181fa1d 413#define INTEL_MEDIA_STEP(__i915) (RUNTIME_INFO(__i915)->step.media_step)
8b449f1c 414#define INTEL_BASEDIE_STEP(__i915) (RUNTIME_INFO(__i915)->step.basedie_step)
439c8dcc
JN		 415
416#define IS_DISPLAY_STEP(__i915, since, until) \
417 (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
46b0d709 418 INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until))
439c8dcc 419
c1f110ee
JRS		 420#define IS_GRAPHICS_STEP(__i915, since, until) \
421 (drm_WARN_ON(&(__i915)->drm, INTEL_GRAPHICS_STEP(__i915) == STEP_NONE), \
422 INTEL_GRAPHICS_STEP(__i915) >= (since) && INTEL_GRAPHICS_STEP(__i915) < (until))
439c8dcc 423
e181fa1d
JRS		 424#define IS_MEDIA_STEP(__i915, since, until) \
425 (drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE), \
426 INTEL_MEDIA_STEP(__i915) >= (since) && INTEL_MEDIA_STEP(__i915) < (until))
427
8b449f1c
MR		 428#define IS_BASEDIE_STEP(__i915, since, until) \
429 (drm_WARN_ON(&(__i915)->drm, INTEL_BASEDIE_STEP(__i915) == STEP_NONE), \
430 INTEL_BASEDIE_STEP(__i915) >= (since) && INTEL_BASEDIE_STEP(__i915) < (until))
431
805446c8
TU		 432static __always_inline unsigned int
433__platform_mask_index(const struct intel_runtime_info *info,
434 enum intel_platform p)
435{
436 const unsigned int pbits =
437 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
438
439 /* Expand the platform_mask array if this fails. */
440 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
441 pbits * ARRAY_SIZE(info->platform_mask));
442
443 return p / pbits;
444}
445
446static __always_inline unsigned int
447__platform_mask_bit(const struct intel_runtime_info *info,
448 enum intel_platform p)
449{
450 const unsigned int pbits =
451 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
452
453 return p % pbits + INTEL_SUBPLATFORM_BITS;
454}
455
456static inline u32
457intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
458{
459 const unsigned int pi = __platform_mask_index(info, p);
460
56afa701 461 return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK;
805446c8
TU		 462}
463
464static __always_inline bool
465IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
466{
467 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
468 const unsigned int pi = __platform_mask_index(info, p);
469 const unsigned int pb = __platform_mask_bit(info, p);
470
471 BUILD_BUG_ON(!__builtin_constant_p(p));
472
473 return info->platform_mask[pi] & BIT(pb);
474}
475
476static __always_inline bool
477IS_SUBPLATFORM(const struct drm_i915_private *i915,
478 enum intel_platform p, unsigned int s)
479{
480 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
481 const unsigned int pi = __platform_mask_index(info, p);
482 const unsigned int pb = __platform_mask_bit(info, p);
483 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
484 const u32 mask = info->platform_mask[pi];
485
486 BUILD_BUG_ON(!__builtin_constant_p(p));
487 BUILD_BUG_ON(!__builtin_constant_p(s));
488 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
489
490 /* Shift and test on the MSB position so sign flag can be used. */
491 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
492}
5a127a8c 493
66ca1d8f
AS		 494#define IS_MOBILE(i915) (INTEL_INFO(i915)->is_mobile)
495#define IS_DGFX(i915) (INTEL_INFO(i915)->is_dgfx)
496
497#define IS_I830(i915) IS_PLATFORM(i915, INTEL_I830)
498#define IS_I845G(i915) IS_PLATFORM(i915, INTEL_I845G)
499#define IS_I85X(i915) IS_PLATFORM(i915, INTEL_I85X)
500#define IS_I865G(i915) IS_PLATFORM(i915, INTEL_I865G)
501#define IS_I915G(i915) IS_PLATFORM(i915, INTEL_I915G)
502#define IS_I915GM(i915) IS_PLATFORM(i915, INTEL_I915GM)
503#define IS_I945G(i915) IS_PLATFORM(i915, INTEL_I945G)
504#define IS_I945GM(i915) IS_PLATFORM(i915, INTEL_I945GM)
505#define IS_I965G(i915) IS_PLATFORM(i915, INTEL_I965G)
506#define IS_I965GM(i915) IS_PLATFORM(i915, INTEL_I965GM)
507#define IS_G45(i915) IS_PLATFORM(i915, INTEL_G45)
508#define IS_GM45(i915) IS_PLATFORM(i915, INTEL_GM45)
509#define IS_G4X(i915) (IS_G45(i915) || IS_GM45(i915))
510#define IS_PINEVIEW(i915) IS_PLATFORM(i915, INTEL_PINEVIEW)
511#define IS_G33(i915) IS_PLATFORM(i915, INTEL_G33)
512#define IS_IRONLAKE(i915) IS_PLATFORM(i915, INTEL_IRONLAKE)
513#define IS_IRONLAKE_M(i915) \
514 (IS_PLATFORM(i915, INTEL_IRONLAKE) && IS_MOBILE(i915))
515#define IS_SANDYBRIDGE(i915) IS_PLATFORM(i915, INTEL_SANDYBRIDGE)
516#define IS_IVYBRIDGE(i915) IS_PLATFORM(i915, INTEL_IVYBRIDGE)
517#define IS_IVB_GT1(i915) (IS_IVYBRIDGE(i915) && \
518 INTEL_INFO(i915)->gt == 1)
519#define IS_VALLEYVIEW(i915) IS_PLATFORM(i915, INTEL_VALLEYVIEW)
520#define IS_CHERRYVIEW(i915) IS_PLATFORM(i915, INTEL_CHERRYVIEW)
521#define IS_HASWELL(i915) IS_PLATFORM(i915, INTEL_HASWELL)
522#define IS_BROADWELL(i915) IS_PLATFORM(i915, INTEL_BROADWELL)
523#define IS_SKYLAKE(i915) IS_PLATFORM(i915, INTEL_SKYLAKE)
524#define IS_BROXTON(i915) IS_PLATFORM(i915, INTEL_BROXTON)
525#define IS_KABYLAKE(i915) IS_PLATFORM(i915, INTEL_KABYLAKE)
526#define IS_GEMINILAKE(i915) IS_PLATFORM(i915, INTEL_GEMINILAKE)
527#define IS_COFFEELAKE(i915) IS_PLATFORM(i915, INTEL_COFFEELAKE)
528#define IS_COMETLAKE(i915) IS_PLATFORM(i915, INTEL_COMETLAKE)
529#define IS_ICELAKE(i915) IS_PLATFORM(i915, INTEL_ICELAKE)
0c65dc06
DB		 530#define IS_JASPERLAKE(i915) IS_PLATFORM(i915, INTEL_JASPERLAKE)
531#define IS_ELKHARTLAKE(i915) IS_PLATFORM(i915, INTEL_ELKHARTLAKE)
66ca1d8f
AS		 532#define IS_TIGERLAKE(i915) IS_PLATFORM(i915, INTEL_TIGERLAKE)
533#define IS_ROCKETLAKE(i915) IS_PLATFORM(i915, INTEL_ROCKETLAKE)
534#define IS_DG1(i915) IS_PLATFORM(i915, INTEL_DG1)
535#define IS_ALDERLAKE_S(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_S)
536#define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P)
66ca1d8f 537#define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2)
66ca1d8f 538#define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
37153b0a
BV		 539/*
540 * Display code shared by i915 and Xe relies on macros like IS_LUNARLAKE,
541 * so we need to define these even on platforms that the i915 base driver
542 * doesn't support. Ensure the parameter is used in the definition to
543 * avoid 'unused variable' warnings when compiling the shared display code
544 * for i915.
545 */
546#define IS_LUNARLAKE(i915) (0 && i915)
547#define IS_BATTLEMAGE(i915) (0 && i915)
66ca1d8f 548
2955ae81
JH		 549#define IS_ARROWLAKE(i915) \
550 IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL)
66ca1d8f
AS		 551#define IS_DG2_G10(i915) \
552 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10)
553#define IS_DG2_G11(i915) \
554 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11)
555#define IS_DG2_G12(i915) \
556 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12)
2aa01e4d 557#define IS_RAPTORLAKE_S(i915) \
66ca1d8f 558 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
6373b793 559#define IS_ALDERLAKE_P_N(i915) \
66ca1d8f 560 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
de01a919 561#define IS_RAPTORLAKE_P(i915) \
66ca1d8f 562 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
e5706c04 563#define IS_RAPTORLAKE_U(i915) \
66ca1d8f 564 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
927a8e38 565#define IS_HASWELL_EARLY_SDV(i915) (IS_HASWELL(i915) && \
66ca1d8f 566 (INTEL_DEVID(i915) & 0xFF00) == 0x0C00)
c224d89c 567#define IS_BROADWELL_ULT(i915) \
66ca1d8f 568 IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
c224d89c 569#define IS_BROADWELL_ULX(i915) \
66ca1d8f 570 IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
c224d89c 571#define IS_BROADWELL_GT3(i915) (IS_BROADWELL(i915) && \
66ca1d8f 572 INTEL_INFO(i915)->gt == 3)
927a8e38 573#define IS_HASWELL_ULT(i915) \
66ca1d8f 574 IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
927a8e38 575#define IS_HASWELL_GT3(i915) (IS_HASWELL(i915) && \
66ca1d8f 576 INTEL_INFO(i915)->gt == 3)
927a8e38 577#define IS_HASWELL_GT1(i915) (IS_HASWELL(i915) && \
66ca1d8f 578 INTEL_INFO(i915)->gt == 1)
9bbfd20a 579/* ULX machines are also considered ULT. */
927a8e38 580#define IS_HASWELL_ULX(i915) \
66ca1d8f 581 IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
bd21470f 582#define IS_SKYLAKE_ULT(i915) \
66ca1d8f 583 IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
bd21470f 584#define IS_SKYLAKE_ULX(i915) \
66ca1d8f 585 IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
b1c52560 586#define IS_KABYLAKE_ULT(i915) \
66ca1d8f 587 IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
b1c52560 588#define IS_KABYLAKE_ULX(i915) \
66ca1d8f 589 IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
bd21470f 590#define IS_SKYLAKE_GT2(i915) (IS_SKYLAKE(i915) && \
66ca1d8f 591 INTEL_INFO(i915)->gt == 2)
bd21470f 592#define IS_SKYLAKE_GT3(i915) (IS_SKYLAKE(i915) && \
66ca1d8f 593 INTEL_INFO(i915)->gt == 3)
bd21470f 594#define IS_SKYLAKE_GT4(i915) (IS_SKYLAKE(i915) && \
66ca1d8f 595 INTEL_INFO(i915)->gt == 4)
b1c52560 596#define IS_KABYLAKE_GT2(i915) (IS_KABYLAKE(i915) && \
66ca1d8f 597 INTEL_INFO(i915)->gt == 2)
b1c52560 598#define IS_KABYLAKE_GT3(i915) (IS_KABYLAKE(i915) && \
66ca1d8f 599 INTEL_INFO(i915)->gt == 3)
ac8140db 600#define IS_COFFEELAKE_ULT(i915) \
66ca1d8f 601 IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
ac8140db 602#define IS_COFFEELAKE_ULX(i915) \
66ca1d8f 603 IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
ac8140db 604#define IS_COFFEELAKE_GT2(i915) (IS_COFFEELAKE(i915) && \
66ca1d8f 605 INTEL_INFO(i915)->gt == 2)
ac8140db 606#define IS_COFFEELAKE_GT3(i915) (IS_COFFEELAKE(i915) && \
66ca1d8f
AS		 607 INTEL_INFO(i915)->gt == 3)
608
bd7b8501 609#define IS_COMETLAKE_ULT(i915) \
66ca1d8f 610 IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
bd7b8501 611#define IS_COMETLAKE_ULX(i915) \
66ca1d8f 612 IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
bd7b8501 613#define IS_COMETLAKE_GT2(i915) (IS_COMETLAKE(i915) && \
66ca1d8f
AS		 614 INTEL_INFO(i915)->gt == 2)
615
616#define IS_ICL_WITH_PORT_F(i915) \
617 IS_SUBPLATFORM(i915, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
618
48077b0b 619#define IS_TIGERLAKE_UY(i915) \
66ca1d8f 620 IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
1d3cc7ab 621
66ca1d8f
AS		 622#define IS_LP(i915) (INTEL_INFO(i915)->is_lp)
623#define IS_GEN9_LP(i915) (GRAPHICS_VER(i915) == 9 && IS_LP(i915))
624#define IS_GEN9_BC(i915) (GRAPHICS_VER(i915) == 9 && !IS_LP(i915))
3e4274f8 625
242613af 626#define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
792592e7 627#define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
a19d6ff2 628
472098c8 629#define __ENGINE_INSTANCES_MASK(mask, first, count) ({ \
97ee6e92
DCS		 630 unsigned int first__ = (first); \
631 unsigned int count__ = (count); \
472098c8 632 ((mask) & GENMASK(first__ + count__ - 1, first__)) >> first__; \
97ee6e92 633})
472098c8
DCS		 634
635#define ENGINE_INSTANCES_MASK(gt, first, count) \
636 __ENGINE_INSTANCES_MASK((gt)->info.engine_mask, first, count)
637
f9576e36
MR		 638#define RCS_MASK(gt) \
639 ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)
e41388d5
MR		 640#define BCS_MASK(gt) \
641 ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS)
242613af
DCS		 642#define VDBOX_MASK(gt) \
643 ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
644#define VEBOX_MASK(gt) \
645 ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
505c4857
MR		 646#define CCS_MASK(gt) \
647 ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)
97ee6e92 648
66ca1d8f 649#define HAS_MEDIA_RATIO_MODE(i915) (INTEL_INFO(i915)->has_media_ratio_mode)
85a040bc 650
4f7af194
JB		 651/*
652 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
653 * All later gens can run the final buffer from the ppgtt
654 */
66ca1d8f 655#define CMDPARSER_USES_GGTT(i915) (GRAPHICS_VER(i915) == 7)
4f7af194 656
66ca1d8f 657#define HAS_LLC(i915) (INTEL_INFO(i915)->has_llc)
66ca1d8f
AS		 658#define HAS_SNOOP(i915) (INTEL_INFO(i915)->has_snoop)
659#define HAS_EDRAM(i915) ((i915)->edram_size_mb)
660#define HAS_SECURE_BATCHES(i915) (GRAPHICS_VER(i915) < 6)
661#define HAS_WT(i915) HAS_EDRAM(i915)
cae5852d 662
66ca1d8f 663#define HWS_NEEDS_PHYSICAL(i915) (INTEL_INFO(i915)->hws_needs_physical)
1d2a314c 664
66ca1d8f
AS		 665#define HAS_LOGICAL_RING_CONTEXTS(i915) \
666 (INTEL_INFO(i915)->has_logical_ring_contexts)
667#define HAS_LOGICAL_RING_ELSQ(i915) \
668 (INTEL_INFO(i915)->has_logical_ring_elsq)
fb5c551a 669
66ca1d8f 670#define HAS_EXECLISTS(i915) HAS_LOGICAL_RING_CONTEXTS(i915)
fb5c551a 671
66ca1d8f
AS		 672#define INTEL_PPGTT(i915) (RUNTIME_INFO(i915)->ppgtt_type)
673#define HAS_PPGTT(i915) \
674 (INTEL_PPGTT(i915) != INTEL_PPGTT_NONE)
675#define HAS_FULL_PPGTT(i915) \
676 (INTEL_PPGTT(i915) >= INTEL_PPGTT_FULL)
4bdafb9d 677
66ca1d8f 678#define HAS_PAGE_SIZES(i915, sizes) ({ \
a5c08166 679 GEM_BUG_ON((sizes) == 0); \
66ca1d8f 680 ((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \
a5c08166 681})
0031fb96 682
b45305fc 683/* Early gen2 have a totally busted CS tlb and require pinned batches. */
66ca1d8f 684#define HAS_BROKEN_CS_TLB(i915) (IS_I830(i915) || IS_I845G(i915))
06e668ac 685
66ca1d8f
AS		 686#define NEEDS_RC6_CTX_CORRUPTION_WA(i915) \
687 (IS_BROADWELL(i915) || GRAPHICS_VER(i915) == 9)
2248a283 688
d66047e4 689/* WaRsDisableCoarsePowerGating:skl,cnl */
66ca1d8f 690#define NEEDS_WaRsDisableCoarsePowerGating(i915) \
bd21470f 691 (IS_SKYLAKE_GT3(i915) || IS_SKYLAKE_GT4(i915))
185c66e5 692
cae5852d
ZN		 693/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
694 * rows, which changed the alignment requirements and fence programming.
695 */
66ca1d8f
AS		 696#define HAS_128_BYTE_Y_TILING(i915) (GRAPHICS_VER(i915) != 2 && \
697 !(IS_I915G(i915) || IS_I915GM(i915)))
f5adf94e 698
66ca1d8f
AS		 699#define HAS_RC6(i915) (INTEL_INFO(i915)->has_rc6)
700#define HAS_RC6p(i915) (INTEL_INFO(i915)->has_rc6p)
701#define HAS_RC6pp(i915) (false) /* HW was never validated */
fb6db0f5 702
66ca1d8f 703#define HAS_RPS(i915) (INTEL_INFO(i915)->has_rps)
affa9354 704
66ca1d8f
AS		 705#define HAS_HECI_PXP(i915) \
706 (INTEL_INFO(i915)->has_heci_pxp)
91cbdb83 707
66ca1d8f
AS		 708#define HAS_HECI_GSCFI(i915) \
709 (INTEL_INFO(i915)->has_heci_gscfi)
1e3dc1d8 710
66ca1d8f 711#define HAS_HECI_GSC(i915) (HAS_HECI_PXP(i915) || HAS_HECI_GSCFI(i915))
1e3dc1d8 712
66ca1d8f
AS		 713#define HAS_RUNTIME_PM(i915) (INTEL_INFO(i915)->has_runtime_pm)
714#define HAS_64BIT_RELOC(i915) (INTEL_INFO(i915)->has_64bit_reloc)
1e3dc1d8 715
66ca1d8f
AS		 716#define HAS_OA_BPC_REPORTING(i915) \
717 (INTEL_INFO(i915)->has_oa_bpc_reporting)
718#define HAS_OA_SLICE_CONTRIB_LIMITS(i915) \
719 (INTEL_INFO(i915)->has_oa_slice_contrib_limits)
720#define HAS_OAM(i915) \
721 (INTEL_INFO(i915)->has_oam)
cceb0849 722
c83125bb
SS		 723/*
724 * Set this flag, when platform requires 64K GTT page sizes or larger for
132aaaf0 725 * device local memory access.
c83125bb 726 */
66ca1d8f 727#define HAS_64K_PAGES(i915) (INTEL_INFO(i915)->has_64k_pages)
c83125bb 728
d082c05a
VS		 729#define HAS_REGION(i915, id) (INTEL_INFO(i915)->memory_regions & BIT(id))
730#define HAS_LMEM(i915) HAS_REGION(i915, INTEL_REGION_LMEM_0)
3aae9d08 731
66ca1d8f 732#define HAS_EXTRA_GT_LIST(i915) (INTEL_INFO(i915)->extra_gt_list)
70fff19a 733
5e3094cf
CT		 734/*
735 * Platform has the dedicated compression control state for each lmem surfaces
736 * stored in lmem to support the 3D and media compression formats.
737 */
66ca1d8f 738#define HAS_FLAT_CCS(i915) (INTEL_INFO(i915)->has_flat_ccs)
5e3094cf 739
66ca1d8f 740#define HAS_GT_UC(i915) (INTEL_INFO(i915)->has_gt_uc)
33a732f4 741
66ca1d8f 742#define HAS_POOLED_EU(i915) (RUNTIME_INFO(i915)->has_pooled_eu)
33e141ed 743
66ca1d8f 744#define HAS_GLOBAL_MOCS_REGISTERS(i915) (INTEL_INFO(i915)->has_global_mocs)
a7a7a0e6 745
c2c70752
MR		 746#define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id)
747
9d67edba
AS		 748#define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
749
040d2baa 750/* DPF == dynamic parity feature */
66ca1d8f 751#define HAS_L3_DPF(i915) (INTEL_INFO(i915)->has_l3_dpf)
927a8e38 752#define NUM_L3_SLICES(i915) (IS_HASWELL_GT3(i915) ? \
66ca1d8f 753 2 : HAS_L3_DPF(i915))
e1ef7cc2 754
66ca1d8f
AS		 755#define HAS_GUC_DEPRIVILEGE(i915) \
756 (INTEL_INFO(i915)->has_guc_deprivilege)
db3b3f3e 757
29e66833
JC		 758#define HAS_GUC_TLB_INVALIDATION(i915) (INTEL_INFO(i915)->has_guc_tlb_invalidation)
759
1eb31338
SS		 760#define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline)
761
5ac342ef
MR		 762#define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
763
03eababb
VS		 764#define HAS_LMEMBAR_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
765 GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
dbb2ffbf 766
1da177e4 767#endif
Linux 6.x block layer and io_uring tree(s)