Commit | Line | Data |
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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
e9b73c67 CW |
33 | #include <uapi/drm/i915_drm.h> |
34 | ||
585fb111 | 35 | #include "i915_reg.h" |
79e53945 | 36 | #include "intel_bios.h" |
8187a2b7 | 37 | #include "intel_ringbuffer.h" |
0839ccb8 | 38 | #include <linux/io-mapping.h> |
f899fc64 | 39 | #include <linux/i2c.h> |
c167a6fc | 40 | #include <linux/i2c-algo-bit.h> |
0ade6386 | 41 | #include <drm/intel-gtt.h> |
aaa6fd2a | 42 | #include <linux/backlight.h> |
2911a35b | 43 | #include <linux/intel-iommu.h> |
742cbee8 | 44 | #include <linux/kref.h> |
9ee32fea | 45 | #include <linux/pm_qos.h> |
585fb111 | 46 | |
1da177e4 LT |
47 | /* General customization: |
48 | */ | |
49 | ||
50 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." | |
51 | ||
52 | #define DRIVER_NAME "i915" | |
53 | #define DRIVER_DESC "Intel Graphics" | |
673a394b | 54 | #define DRIVER_DATE "20080730" |
1da177e4 | 55 | |
317c35d1 JB |
56 | enum pipe { |
57 | PIPE_A = 0, | |
58 | PIPE_B, | |
9db4a9c7 JB |
59 | PIPE_C, |
60 | I915_MAX_PIPES | |
317c35d1 | 61 | }; |
9db4a9c7 | 62 | #define pipe_name(p) ((p) + 'A') |
317c35d1 | 63 | |
a5c961d1 PZ |
64 | enum transcoder { |
65 | TRANSCODER_A = 0, | |
66 | TRANSCODER_B, | |
67 | TRANSCODER_C, | |
68 | TRANSCODER_EDP = 0xF, | |
69 | }; | |
70 | #define transcoder_name(t) ((t) + 'A') | |
71 | ||
80824003 JB |
72 | enum plane { |
73 | PLANE_A = 0, | |
74 | PLANE_B, | |
9db4a9c7 | 75 | PLANE_C, |
80824003 | 76 | }; |
9db4a9c7 | 77 | #define plane_name(p) ((p) + 'A') |
52440211 | 78 | |
2b139522 ED |
79 | enum port { |
80 | PORT_A = 0, | |
81 | PORT_B, | |
82 | PORT_C, | |
83 | PORT_D, | |
84 | PORT_E, | |
85 | I915_MAX_PORTS | |
86 | }; | |
87 | #define port_name(p) ((p) + 'A') | |
88 | ||
2a2d5482 CW |
89 | #define I915_GEM_GPU_DOMAINS \ |
90 | (I915_GEM_DOMAIN_RENDER | \ | |
91 | I915_GEM_DOMAIN_SAMPLER | \ | |
92 | I915_GEM_DOMAIN_COMMAND | \ | |
93 | I915_GEM_DOMAIN_INSTRUCTION | \ | |
94 | I915_GEM_DOMAIN_VERTEX) | |
62fdfeaf | 95 | |
9db4a9c7 JB |
96 | #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++) |
97 | ||
6c2b7c12 DV |
98 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
99 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ | |
100 | if ((intel_encoder)->base.crtc == (__crtc)) | |
101 | ||
ee7b9f93 JB |
102 | struct intel_pch_pll { |
103 | int refcount; /* count of number of CRTCs sharing this PLL */ | |
104 | int active; /* count of number of active CRTCs (i.e. DPMS on) */ | |
105 | bool on; /* is the PLL actually active? Disabled during modeset */ | |
106 | int pll_reg; | |
107 | int fp0_reg; | |
108 | int fp1_reg; | |
109 | }; | |
110 | #define I915_NUM_PLLS 2 | |
111 | ||
e69d0bc1 DV |
112 | /* Used by dp and fdi links */ |
113 | struct intel_link_m_n { | |
114 | uint32_t tu; | |
115 | uint32_t gmch_m; | |
116 | uint32_t gmch_n; | |
117 | uint32_t link_m; | |
118 | uint32_t link_n; | |
119 | }; | |
120 | ||
121 | void intel_link_compute_m_n(int bpp, int nlanes, | |
122 | int pixel_clock, int link_clock, | |
123 | struct intel_link_m_n *m_n); | |
124 | ||
6441ab5f PZ |
125 | struct intel_ddi_plls { |
126 | int spll_refcount; | |
127 | int wrpll1_refcount; | |
128 | int wrpll2_refcount; | |
129 | }; | |
130 | ||
1da177e4 LT |
131 | /* Interface history: |
132 | * | |
133 | * 1.1: Original. | |
0d6aa60b DA |
134 | * 1.2: Add Power Management |
135 | * 1.3: Add vblank support | |
de227f5f | 136 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 137 | * 1.5: Add vblank pipe configuration |
2228ed67 MCA |
138 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
139 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
140 | */ |
141 | #define DRIVER_MAJOR 1 | |
2228ed67 | 142 | #define DRIVER_MINOR 6 |
1da177e4 LT |
143 | #define DRIVER_PATCHLEVEL 0 |
144 | ||
673a394b | 145 | #define WATCH_COHERENCY 0 |
23bc5982 | 146 | #define WATCH_LISTS 0 |
42d6ab48 | 147 | #define WATCH_GTT 0 |
673a394b | 148 | |
71acb5eb DA |
149 | #define I915_GEM_PHYS_CURSOR_0 1 |
150 | #define I915_GEM_PHYS_CURSOR_1 2 | |
151 | #define I915_GEM_PHYS_OVERLAY_REGS 3 | |
152 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) | |
153 | ||
154 | struct drm_i915_gem_phys_object { | |
155 | int id; | |
156 | struct page **page_list; | |
157 | drm_dma_handle_t *handle; | |
05394f39 | 158 | struct drm_i915_gem_object *cur_obj; |
71acb5eb DA |
159 | }; |
160 | ||
0a3e67a4 JB |
161 | struct opregion_header; |
162 | struct opregion_acpi; | |
163 | struct opregion_swsci; | |
164 | struct opregion_asle; | |
8d715f00 | 165 | struct drm_i915_private; |
0a3e67a4 | 166 | |
8ee1c3db | 167 | struct intel_opregion { |
5bc4418b BW |
168 | struct opregion_header __iomem *header; |
169 | struct opregion_acpi __iomem *acpi; | |
170 | struct opregion_swsci __iomem *swsci; | |
171 | struct opregion_asle __iomem *asle; | |
172 | void __iomem *vbt; | |
01fe9dbd | 173 | u32 __iomem *lid_state; |
8ee1c3db | 174 | }; |
44834a67 | 175 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 176 | |
6ef3d427 CW |
177 | struct intel_overlay; |
178 | struct intel_overlay_error_state; | |
179 | ||
7c1c2871 DA |
180 | struct drm_i915_master_private { |
181 | drm_local_map_t *sarea; | |
182 | struct _drm_i915_sarea *sarea_priv; | |
183 | }; | |
de151cf6 | 184 | #define I915_FENCE_REG_NONE -1 |
4b9de737 DV |
185 | #define I915_MAX_NUM_FENCES 16 |
186 | /* 16 fences + sign bit for FENCE_REG_NONE */ | |
187 | #define I915_MAX_NUM_FENCE_BITS 5 | |
de151cf6 JB |
188 | |
189 | struct drm_i915_fence_reg { | |
007cc8ac | 190 | struct list_head lru_list; |
caea7476 | 191 | struct drm_i915_gem_object *obj; |
1690e1eb | 192 | int pin_count; |
de151cf6 | 193 | }; |
7c1c2871 | 194 | |
9b9d172d | 195 | struct sdvo_device_mapping { |
e957d772 | 196 | u8 initialized; |
9b9d172d | 197 | u8 dvo_port; |
198 | u8 slave_addr; | |
199 | u8 dvo_wiring; | |
e957d772 | 200 | u8 i2c_pin; |
b1083333 | 201 | u8 ddc_pin; |
9b9d172d | 202 | }; |
203 | ||
c4a1d9e4 CW |
204 | struct intel_display_error_state; |
205 | ||
63eeaf38 | 206 | struct drm_i915_error_state { |
742cbee8 | 207 | struct kref ref; |
63eeaf38 JB |
208 | u32 eir; |
209 | u32 pgtbl_er; | |
be998e2e | 210 | u32 ier; |
b9a3906b | 211 | u32 ccid; |
9574b3fe | 212 | bool waiting[I915_NUM_RINGS]; |
9db4a9c7 | 213 | u32 pipestat[I915_MAX_PIPES]; |
c1cd90ed DV |
214 | u32 tail[I915_NUM_RINGS]; |
215 | u32 head[I915_NUM_RINGS]; | |
d27b1e0e DV |
216 | u32 ipeir[I915_NUM_RINGS]; |
217 | u32 ipehr[I915_NUM_RINGS]; | |
218 | u32 instdone[I915_NUM_RINGS]; | |
219 | u32 acthd[I915_NUM_RINGS]; | |
7e3b8737 | 220 | u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; |
df2b23d9 | 221 | u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1]; |
12f55818 | 222 | u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */ |
7e3b8737 DV |
223 | /* our own tracking of ring head and tail */ |
224 | u32 cpu_ring_head[I915_NUM_RINGS]; | |
225 | u32 cpu_ring_tail[I915_NUM_RINGS]; | |
1d8f38f4 | 226 | u32 error; /* gen6+ */ |
71e172e8 | 227 | u32 err_int; /* gen7 */ |
c1cd90ed DV |
228 | u32 instpm[I915_NUM_RINGS]; |
229 | u32 instps[I915_NUM_RINGS]; | |
050ee91f | 230 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; |
d27b1e0e | 231 | u32 seqno[I915_NUM_RINGS]; |
9df30794 | 232 | u64 bbaddr; |
33f3f518 DV |
233 | u32 fault_reg[I915_NUM_RINGS]; |
234 | u32 done_reg; | |
c1cd90ed | 235 | u32 faddr[I915_NUM_RINGS]; |
4b9de737 | 236 | u64 fence[I915_MAX_NUM_FENCES]; |
63eeaf38 | 237 | struct timeval time; |
52d39a21 CW |
238 | struct drm_i915_error_ring { |
239 | struct drm_i915_error_object { | |
240 | int page_count; | |
241 | u32 gtt_offset; | |
242 | u32 *pages[0]; | |
243 | } *ringbuffer, *batchbuffer; | |
244 | struct drm_i915_error_request { | |
245 | long jiffies; | |
246 | u32 seqno; | |
ee4f42b1 | 247 | u32 tail; |
52d39a21 CW |
248 | } *requests; |
249 | int num_requests; | |
250 | } ring[I915_NUM_RINGS]; | |
9df30794 | 251 | struct drm_i915_error_buffer { |
a779e5ab | 252 | u32 size; |
9df30794 | 253 | u32 name; |
0201f1ec | 254 | u32 rseqno, wseqno; |
9df30794 CW |
255 | u32 gtt_offset; |
256 | u32 read_domains; | |
257 | u32 write_domain; | |
4b9de737 | 258 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
9df30794 CW |
259 | s32 pinned:2; |
260 | u32 tiling:2; | |
261 | u32 dirty:1; | |
262 | u32 purgeable:1; | |
5d1333fc | 263 | s32 ring:4; |
93dfb40c | 264 | u32 cache_level:2; |
c724e8a9 CW |
265 | } *active_bo, *pinned_bo; |
266 | u32 active_bo_count, pinned_bo_count; | |
6ef3d427 | 267 | struct intel_overlay_error_state *overlay; |
c4a1d9e4 | 268 | struct intel_display_error_state *display; |
63eeaf38 JB |
269 | }; |
270 | ||
e70236a8 | 271 | struct drm_i915_display_funcs { |
ee5382ae | 272 | bool (*fbc_enabled)(struct drm_device *dev); |
e70236a8 JB |
273 | void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); |
274 | void (*disable_fbc)(struct drm_device *dev); | |
275 | int (*get_display_clock_speed)(struct drm_device *dev); | |
276 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
d210246a | 277 | void (*update_wm)(struct drm_device *dev); |
b840d907 JB |
278 | void (*update_sprite_wm)(struct drm_device *dev, int pipe, |
279 | uint32_t sprite_width, int pixel_size); | |
1f8eeabf ED |
280 | void (*update_linetime_wm)(struct drm_device *dev, int pipe, |
281 | struct drm_display_mode *mode); | |
47fab737 | 282 | void (*modeset_global_resources)(struct drm_device *dev); |
f564048e EA |
283 | int (*crtc_mode_set)(struct drm_crtc *crtc, |
284 | struct drm_display_mode *mode, | |
285 | struct drm_display_mode *adjusted_mode, | |
286 | int x, int y, | |
287 | struct drm_framebuffer *old_fb); | |
76e5a89c DV |
288 | void (*crtc_enable)(struct drm_crtc *crtc); |
289 | void (*crtc_disable)(struct drm_crtc *crtc); | |
ee7b9f93 | 290 | void (*off)(struct drm_crtc *crtc); |
e0dac65e WF |
291 | void (*write_eld)(struct drm_connector *connector, |
292 | struct drm_crtc *crtc); | |
674cf967 | 293 | void (*fdi_link_train)(struct drm_crtc *crtc); |
6067aaea | 294 | void (*init_clock_gating)(struct drm_device *dev); |
8c9f3aaf JB |
295 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
296 | struct drm_framebuffer *fb, | |
297 | struct drm_i915_gem_object *obj); | |
17638cd6 JB |
298 | int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
299 | int x, int y); | |
20afbda2 | 300 | void (*hpd_irq_setup)(struct drm_device *dev); |
e70236a8 JB |
301 | /* clock updates for mode set */ |
302 | /* cursor updates */ | |
303 | /* render clock increase/decrease */ | |
304 | /* display clock increase/decrease */ | |
305 | /* pll clock increase/decrease */ | |
e70236a8 JB |
306 | }; |
307 | ||
990bbdad CW |
308 | struct drm_i915_gt_funcs { |
309 | void (*force_wake_get)(struct drm_i915_private *dev_priv); | |
310 | void (*force_wake_put)(struct drm_i915_private *dev_priv); | |
311 | }; | |
312 | ||
c96ea64e DV |
313 | #define DEV_INFO_FLAGS \ |
314 | DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \ | |
315 | DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \ | |
316 | DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \ | |
317 | DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \ | |
318 | DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \ | |
319 | DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \ | |
320 | DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \ | |
321 | DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \ | |
322 | DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \ | |
323 | DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \ | |
324 | DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \ | |
325 | DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \ | |
326 | DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \ | |
327 | DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \ | |
328 | DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \ | |
329 | DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \ | |
330 | DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \ | |
331 | DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \ | |
332 | DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \ | |
333 | DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \ | |
334 | DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \ | |
335 | DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \ | |
336 | DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \ | |
337 | DEV_INFO_FLAG(has_llc) | |
338 | ||
cfdf1fa2 | 339 | struct intel_device_info { |
10fce67a | 340 | u32 display_mmio_offset; |
c96c3a8c | 341 | u8 gen; |
0206e353 AJ |
342 | u8 is_mobile:1; |
343 | u8 is_i85x:1; | |
344 | u8 is_i915g:1; | |
345 | u8 is_i945gm:1; | |
346 | u8 is_g33:1; | |
347 | u8 need_gfx_hws:1; | |
348 | u8 is_g4x:1; | |
349 | u8 is_pineview:1; | |
350 | u8 is_broadwater:1; | |
351 | u8 is_crestline:1; | |
352 | u8 is_ivybridge:1; | |
70a3eb7a | 353 | u8 is_valleyview:1; |
b7884eb4 | 354 | u8 has_force_wake:1; |
4cae9ae0 | 355 | u8 is_haswell:1; |
0206e353 AJ |
356 | u8 has_fbc:1; |
357 | u8 has_pipe_cxsr:1; | |
358 | u8 has_hotplug:1; | |
359 | u8 cursor_needs_physical:1; | |
360 | u8 has_overlay:1; | |
361 | u8 overlay_needs_physical:1; | |
362 | u8 supports_tv:1; | |
363 | u8 has_bsd_ring:1; | |
364 | u8 has_blt_ring:1; | |
3d29b842 | 365 | u8 has_llc:1; |
cfdf1fa2 KH |
366 | }; |
367 | ||
7faf1ab2 DV |
368 | enum i915_cache_level { |
369 | I915_CACHE_NONE = 0, | |
370 | I915_CACHE_LLC, | |
371 | I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */ | |
372 | }; | |
373 | ||
5d4545ae BW |
374 | /* The Graphics Translation Table is the way in which GEN hardware translates a |
375 | * Graphics Virtual Address into a Physical Address. In addition to the normal | |
376 | * collateral associated with any va->pa translations GEN hardware also has a | |
377 | * portion of the GTT which can be mapped by the CPU and remain both coherent | |
378 | * and correct (in cases like swizzling). That region is referred to as GMADR in | |
379 | * the spec. | |
380 | */ | |
381 | struct i915_gtt { | |
382 | unsigned long start; /* Start offset of used GTT */ | |
383 | size_t total; /* Total size GTT can map */ | |
baa09f5f | 384 | size_t stolen_size; /* Total size of stolen memory */ |
5d4545ae BW |
385 | |
386 | unsigned long mappable_end; /* End offset that we can CPU map */ | |
387 | struct io_mapping *mappable; /* Mapping to our CPU mappable region */ | |
388 | phys_addr_t mappable_base; /* PA of our GMADR */ | |
389 | ||
390 | /** "Graphics Stolen Memory" holds the global PTEs */ | |
391 | void __iomem *gsm; | |
a81cc00c BW |
392 | |
393 | bool do_idle_maps; | |
9c61a32d BW |
394 | dma_addr_t scratch_page_dma; |
395 | struct page *scratch_page; | |
7faf1ab2 DV |
396 | |
397 | /* global gtt ops */ | |
baa09f5f BW |
398 | int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total, |
399 | size_t *stolen); | |
400 | void (*gtt_remove)(struct drm_device *dev); | |
7faf1ab2 DV |
401 | void (*gtt_clear_range)(struct drm_device *dev, |
402 | unsigned int first_entry, | |
403 | unsigned int num_entries); | |
404 | void (*gtt_insert_entries)(struct drm_device *dev, | |
405 | struct sg_table *st, | |
406 | unsigned int pg_start, | |
407 | enum i915_cache_level cache_level); | |
5d4545ae | 408 | }; |
a54c0c27 | 409 | #define gtt_total_entries(gtt) ((gtt).total >> PAGE_SHIFT) |
5d4545ae | 410 | |
1d2a314c DV |
411 | #define I915_PPGTT_PD_ENTRIES 512 |
412 | #define I915_PPGTT_PT_ENTRIES 1024 | |
413 | struct i915_hw_ppgtt { | |
8f2c59f0 | 414 | struct drm_device *dev; |
1d2a314c DV |
415 | unsigned num_pd_entries; |
416 | struct page **pt_pages; | |
417 | uint32_t pd_offset; | |
418 | dma_addr_t *pt_dma_addr; | |
419 | dma_addr_t scratch_page_dma_addr; | |
def886c3 DV |
420 | |
421 | /* pte functions, mirroring the interface of the global gtt. */ | |
422 | void (*clear_range)(struct i915_hw_ppgtt *ppgtt, | |
423 | unsigned int first_entry, | |
424 | unsigned int num_entries); | |
425 | void (*insert_entries)(struct i915_hw_ppgtt *ppgtt, | |
426 | struct sg_table *st, | |
427 | unsigned int pg_start, | |
428 | enum i915_cache_level cache_level); | |
3440d265 | 429 | void (*cleanup)(struct i915_hw_ppgtt *ppgtt); |
1d2a314c DV |
430 | }; |
431 | ||
40521054 BW |
432 | |
433 | /* This must match up with the value previously used for execbuf2.rsvd1. */ | |
434 | #define DEFAULT_CONTEXT_ID 0 | |
435 | struct i915_hw_context { | |
436 | int id; | |
e0556841 | 437 | bool is_initialized; |
40521054 BW |
438 | struct drm_i915_file_private *file_priv; |
439 | struct intel_ring_buffer *ring; | |
440 | struct drm_i915_gem_object *obj; | |
441 | }; | |
442 | ||
b5e50c3f | 443 | enum no_fbc_reason { |
bed4a673 | 444 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
b5e50c3f JB |
445 | FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ |
446 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ | |
447 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ | |
448 | FBC_BAD_PLANE, /* fbc not supported on plane */ | |
449 | FBC_NOT_TILED, /* buffer not tiled */ | |
9c928d16 | 450 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ |
c1a9f047 | 451 | FBC_MODULE_PARAM, |
b5e50c3f JB |
452 | }; |
453 | ||
3bad0781 | 454 | enum intel_pch { |
f0350830 | 455 | PCH_NONE = 0, /* No PCH present */ |
3bad0781 ZW |
456 | PCH_IBX, /* Ibexpeak PCH */ |
457 | PCH_CPT, /* Cougarpoint PCH */ | |
eb877ebf | 458 | PCH_LPT, /* Lynxpoint PCH */ |
3bad0781 ZW |
459 | }; |
460 | ||
988d6ee8 PZ |
461 | enum intel_sbi_destination { |
462 | SBI_ICLK, | |
463 | SBI_MPHY, | |
464 | }; | |
465 | ||
b690e96c | 466 | #define QUIRK_PIPEA_FORCE (1<<0) |
435793df | 467 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
4dca20ef | 468 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
b690e96c | 469 | |
8be48d92 | 470 | struct intel_fbdev; |
1630fe75 | 471 | struct intel_fbc_work; |
38651674 | 472 | |
c2b9152f DV |
473 | struct intel_gmbus { |
474 | struct i2c_adapter adapter; | |
f2ce9faf | 475 | u32 force_bit; |
c2b9152f | 476 | u32 reg0; |
36c785f0 | 477 | u32 gpio_reg; |
c167a6fc | 478 | struct i2c_algo_bit_data bit_algo; |
c2b9152f DV |
479 | struct drm_i915_private *dev_priv; |
480 | }; | |
481 | ||
f4c956ad | 482 | struct i915_suspend_saved_registers { |
ba8bbcf6 JB |
483 | u8 saveLBB; |
484 | u32 saveDSPACNTR; | |
485 | u32 saveDSPBCNTR; | |
e948e994 | 486 | u32 saveDSPARB; |
ba8bbcf6 JB |
487 | u32 savePIPEACONF; |
488 | u32 savePIPEBCONF; | |
489 | u32 savePIPEASRC; | |
490 | u32 savePIPEBSRC; | |
491 | u32 saveFPA0; | |
492 | u32 saveFPA1; | |
493 | u32 saveDPLL_A; | |
494 | u32 saveDPLL_A_MD; | |
495 | u32 saveHTOTAL_A; | |
496 | u32 saveHBLANK_A; | |
497 | u32 saveHSYNC_A; | |
498 | u32 saveVTOTAL_A; | |
499 | u32 saveVBLANK_A; | |
500 | u32 saveVSYNC_A; | |
501 | u32 saveBCLRPAT_A; | |
5586c8bc | 502 | u32 saveTRANSACONF; |
42048781 ZW |
503 | u32 saveTRANS_HTOTAL_A; |
504 | u32 saveTRANS_HBLANK_A; | |
505 | u32 saveTRANS_HSYNC_A; | |
506 | u32 saveTRANS_VTOTAL_A; | |
507 | u32 saveTRANS_VBLANK_A; | |
508 | u32 saveTRANS_VSYNC_A; | |
0da3ea12 | 509 | u32 savePIPEASTAT; |
ba8bbcf6 JB |
510 | u32 saveDSPASTRIDE; |
511 | u32 saveDSPASIZE; | |
512 | u32 saveDSPAPOS; | |
585fb111 | 513 | u32 saveDSPAADDR; |
ba8bbcf6 JB |
514 | u32 saveDSPASURF; |
515 | u32 saveDSPATILEOFF; | |
516 | u32 savePFIT_PGM_RATIOS; | |
0eb96d6e | 517 | u32 saveBLC_HIST_CTL; |
ba8bbcf6 JB |
518 | u32 saveBLC_PWM_CTL; |
519 | u32 saveBLC_PWM_CTL2; | |
42048781 ZW |
520 | u32 saveBLC_CPU_PWM_CTL; |
521 | u32 saveBLC_CPU_PWM_CTL2; | |
ba8bbcf6 JB |
522 | u32 saveFPB0; |
523 | u32 saveFPB1; | |
524 | u32 saveDPLL_B; | |
525 | u32 saveDPLL_B_MD; | |
526 | u32 saveHTOTAL_B; | |
527 | u32 saveHBLANK_B; | |
528 | u32 saveHSYNC_B; | |
529 | u32 saveVTOTAL_B; | |
530 | u32 saveVBLANK_B; | |
531 | u32 saveVSYNC_B; | |
532 | u32 saveBCLRPAT_B; | |
5586c8bc | 533 | u32 saveTRANSBCONF; |
42048781 ZW |
534 | u32 saveTRANS_HTOTAL_B; |
535 | u32 saveTRANS_HBLANK_B; | |
536 | u32 saveTRANS_HSYNC_B; | |
537 | u32 saveTRANS_VTOTAL_B; | |
538 | u32 saveTRANS_VBLANK_B; | |
539 | u32 saveTRANS_VSYNC_B; | |
0da3ea12 | 540 | u32 savePIPEBSTAT; |
ba8bbcf6 JB |
541 | u32 saveDSPBSTRIDE; |
542 | u32 saveDSPBSIZE; | |
543 | u32 saveDSPBPOS; | |
585fb111 | 544 | u32 saveDSPBADDR; |
ba8bbcf6 JB |
545 | u32 saveDSPBSURF; |
546 | u32 saveDSPBTILEOFF; | |
585fb111 JB |
547 | u32 saveVGA0; |
548 | u32 saveVGA1; | |
549 | u32 saveVGA_PD; | |
ba8bbcf6 JB |
550 | u32 saveVGACNTRL; |
551 | u32 saveADPA; | |
552 | u32 saveLVDS; | |
585fb111 JB |
553 | u32 savePP_ON_DELAYS; |
554 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
555 | u32 saveDVOA; |
556 | u32 saveDVOB; | |
557 | u32 saveDVOC; | |
558 | u32 savePP_ON; | |
559 | u32 savePP_OFF; | |
560 | u32 savePP_CONTROL; | |
585fb111 | 561 | u32 savePP_DIVISOR; |
ba8bbcf6 JB |
562 | u32 savePFIT_CONTROL; |
563 | u32 save_palette_a[256]; | |
564 | u32 save_palette_b[256]; | |
06027f91 | 565 | u32 saveDPFC_CB_BASE; |
ba8bbcf6 JB |
566 | u32 saveFBC_CFB_BASE; |
567 | u32 saveFBC_LL_BASE; | |
568 | u32 saveFBC_CONTROL; | |
569 | u32 saveFBC_CONTROL2; | |
0da3ea12 JB |
570 | u32 saveIER; |
571 | u32 saveIIR; | |
572 | u32 saveIMR; | |
42048781 ZW |
573 | u32 saveDEIER; |
574 | u32 saveDEIMR; | |
575 | u32 saveGTIER; | |
576 | u32 saveGTIMR; | |
577 | u32 saveFDI_RXA_IMR; | |
578 | u32 saveFDI_RXB_IMR; | |
1f84e550 | 579 | u32 saveCACHE_MODE_0; |
1f84e550 | 580 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
581 | u32 saveSWF0[16]; |
582 | u32 saveSWF1[16]; | |
583 | u32 saveSWF2[3]; | |
584 | u8 saveMSR; | |
585 | u8 saveSR[8]; | |
123f794f | 586 | u8 saveGR[25]; |
ba8bbcf6 | 587 | u8 saveAR_INDEX; |
a59e122a | 588 | u8 saveAR[21]; |
ba8bbcf6 | 589 | u8 saveDACMASK; |
a59e122a | 590 | u8 saveCR[37]; |
4b9de737 | 591 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
1fd1c624 EA |
592 | u32 saveCURACNTR; |
593 | u32 saveCURAPOS; | |
594 | u32 saveCURABASE; | |
595 | u32 saveCURBCNTR; | |
596 | u32 saveCURBPOS; | |
597 | u32 saveCURBBASE; | |
598 | u32 saveCURSIZE; | |
a4fc5ed6 KP |
599 | u32 saveDP_B; |
600 | u32 saveDP_C; | |
601 | u32 saveDP_D; | |
602 | u32 savePIPEA_GMCH_DATA_M; | |
603 | u32 savePIPEB_GMCH_DATA_M; | |
604 | u32 savePIPEA_GMCH_DATA_N; | |
605 | u32 savePIPEB_GMCH_DATA_N; | |
606 | u32 savePIPEA_DP_LINK_M; | |
607 | u32 savePIPEB_DP_LINK_M; | |
608 | u32 savePIPEA_DP_LINK_N; | |
609 | u32 savePIPEB_DP_LINK_N; | |
42048781 ZW |
610 | u32 saveFDI_RXA_CTL; |
611 | u32 saveFDI_TXA_CTL; | |
612 | u32 saveFDI_RXB_CTL; | |
613 | u32 saveFDI_TXB_CTL; | |
614 | u32 savePFA_CTL_1; | |
615 | u32 savePFB_CTL_1; | |
616 | u32 savePFA_WIN_SZ; | |
617 | u32 savePFB_WIN_SZ; | |
618 | u32 savePFA_WIN_POS; | |
619 | u32 savePFB_WIN_POS; | |
5586c8bc ZW |
620 | u32 savePCH_DREF_CONTROL; |
621 | u32 saveDISP_ARB_CTL; | |
622 | u32 savePIPEA_DATA_M1; | |
623 | u32 savePIPEA_DATA_N1; | |
624 | u32 savePIPEA_LINK_M1; | |
625 | u32 savePIPEA_LINK_N1; | |
626 | u32 savePIPEB_DATA_M1; | |
627 | u32 savePIPEB_DATA_N1; | |
628 | u32 savePIPEB_LINK_M1; | |
629 | u32 savePIPEB_LINK_N1; | |
b5b72e89 | 630 | u32 saveMCHBAR_RENDER_STANDBY; |
cda2bb78 | 631 | u32 savePCH_PORT_HOTPLUG; |
f4c956ad | 632 | }; |
c85aa885 DV |
633 | |
634 | struct intel_gen6_power_mgmt { | |
635 | struct work_struct work; | |
636 | u32 pm_iir; | |
637 | /* lock - irqsave spinlock that protectects the work_struct and | |
638 | * pm_iir. */ | |
639 | spinlock_t lock; | |
640 | ||
641 | /* The below variables an all the rps hw state are protected by | |
642 | * dev->struct mutext. */ | |
643 | u8 cur_delay; | |
644 | u8 min_delay; | |
645 | u8 max_delay; | |
1a01ab3b JB |
646 | |
647 | struct delayed_work delayed_resume_work; | |
4fc688ce JB |
648 | |
649 | /* | |
650 | * Protects RPS/RC6 register access and PCU communication. | |
651 | * Must be taken after struct_mutex if nested. | |
652 | */ | |
653 | struct mutex hw_lock; | |
c85aa885 DV |
654 | }; |
655 | ||
1a240d4d DV |
656 | /* defined intel_pm.c */ |
657 | extern spinlock_t mchdev_lock; | |
658 | ||
c85aa885 DV |
659 | struct intel_ilk_power_mgmt { |
660 | u8 cur_delay; | |
661 | u8 min_delay; | |
662 | u8 max_delay; | |
663 | u8 fmax; | |
664 | u8 fstart; | |
665 | ||
666 | u64 last_count1; | |
667 | unsigned long last_time1; | |
668 | unsigned long chipset_power; | |
669 | u64 last_count2; | |
670 | struct timespec last_time2; | |
671 | unsigned long gfx_power; | |
672 | u8 corr; | |
673 | ||
674 | int c_m; | |
675 | int r_t; | |
3e373948 DV |
676 | |
677 | struct drm_i915_gem_object *pwrctx; | |
678 | struct drm_i915_gem_object *renderctx; | |
c85aa885 DV |
679 | }; |
680 | ||
231f42a4 DV |
681 | struct i915_dri1_state { |
682 | unsigned allow_batchbuffer : 1; | |
683 | u32 __iomem *gfx_hws_cpu_addr; | |
684 | ||
685 | unsigned int cpp; | |
686 | int back_offset; | |
687 | int front_offset; | |
688 | int current_page; | |
689 | int page_flipping; | |
690 | ||
691 | uint32_t counter; | |
692 | }; | |
693 | ||
a4da4fa4 DV |
694 | struct intel_l3_parity { |
695 | u32 *remap_info; | |
696 | struct work_struct error_work; | |
697 | }; | |
698 | ||
4b5aed62 | 699 | struct i915_gem_mm { |
4b5aed62 DV |
700 | /** Memory allocator for GTT stolen memory */ |
701 | struct drm_mm stolen; | |
702 | /** Memory allocator for GTT */ | |
703 | struct drm_mm gtt_space; | |
704 | /** List of all objects in gtt_space. Used to restore gtt | |
705 | * mappings on resume */ | |
706 | struct list_head bound_list; | |
707 | /** | |
708 | * List of objects which are not bound to the GTT (thus | |
709 | * are idle and not used by the GPU) but still have | |
710 | * (presumably uncached) pages still attached. | |
711 | */ | |
712 | struct list_head unbound_list; | |
713 | ||
714 | /** Usable portion of the GTT for GEM */ | |
715 | unsigned long stolen_base; /* limited to low memory (32-bit) */ | |
716 | ||
717 | int gtt_mtrr; | |
718 | ||
719 | /** PPGTT used for aliasing the PPGTT with the GTT */ | |
720 | struct i915_hw_ppgtt *aliasing_ppgtt; | |
721 | ||
722 | struct shrinker inactive_shrinker; | |
723 | bool shrinker_no_lock_stealing; | |
724 | ||
725 | /** | |
726 | * List of objects currently involved in rendering. | |
727 | * | |
728 | * Includes buffers having the contents of their GPU caches | |
729 | * flushed, not necessarily primitives. last_rendering_seqno | |
730 | * represents when the rendering involved will be completed. | |
731 | * | |
732 | * A reference is held on the buffer while on this list. | |
733 | */ | |
734 | struct list_head active_list; | |
735 | ||
736 | /** | |
737 | * LRU list of objects which are not in the ringbuffer and | |
738 | * are ready to unbind, but are still in the GTT. | |
739 | * | |
740 | * last_rendering_seqno is 0 while an object is in this list. | |
741 | * | |
742 | * A reference is not held on the buffer while on this list, | |
743 | * as merely being GTT-bound shouldn't prevent its being | |
744 | * freed, and we'll pull it off the list in the free path. | |
745 | */ | |
746 | struct list_head inactive_list; | |
747 | ||
748 | /** LRU list of objects with fence regs on them. */ | |
749 | struct list_head fence_list; | |
750 | ||
751 | /** | |
752 | * We leave the user IRQ off as much as possible, | |
753 | * but this means that requests will finish and never | |
754 | * be retired once the system goes idle. Set a timer to | |
755 | * fire periodically while the ring is running. When it | |
756 | * fires, go retire requests. | |
757 | */ | |
758 | struct delayed_work retire_work; | |
759 | ||
760 | /** | |
761 | * Are we in a non-interruptible section of code like | |
762 | * modesetting? | |
763 | */ | |
764 | bool interruptible; | |
765 | ||
766 | /** | |
767 | * Flag if the X Server, and thus DRM, is not currently in | |
768 | * control of the device. | |
769 | * | |
770 | * This is set between LeaveVT and EnterVT. It needs to be | |
771 | * replaced with a semaphore. It also needs to be | |
772 | * transitioned away from for kernel modesetting. | |
773 | */ | |
774 | int suspended; | |
775 | ||
4b5aed62 DV |
776 | /** Bit 6 swizzling required for X tiling */ |
777 | uint32_t bit_6_swizzle_x; | |
778 | /** Bit 6 swizzling required for Y tiling */ | |
779 | uint32_t bit_6_swizzle_y; | |
780 | ||
781 | /* storage for physical objects */ | |
782 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; | |
783 | ||
784 | /* accounting, useful for userland debugging */ | |
785 | size_t object_memory; | |
786 | u32 object_count; | |
787 | }; | |
788 | ||
99584db3 DV |
789 | struct i915_gpu_error { |
790 | /* For hangcheck timer */ | |
791 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ | |
792 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) | |
793 | struct timer_list hangcheck_timer; | |
794 | int hangcheck_count; | |
795 | uint32_t last_acthd[I915_NUM_RINGS]; | |
796 | uint32_t prev_instdone[I915_NUM_INSTDONE_REG]; | |
797 | ||
798 | /* For reset and error_state handling. */ | |
799 | spinlock_t lock; | |
800 | /* Protected by the above dev->gpu_error.lock. */ | |
801 | struct drm_i915_error_state *first_error; | |
802 | struct work_struct work; | |
99584db3 DV |
803 | |
804 | unsigned long last_reset; | |
805 | ||
1f83fee0 | 806 | /** |
f69061be | 807 | * State variable and reset counter controlling the reset flow |
1f83fee0 | 808 | * |
f69061be DV |
809 | * Upper bits are for the reset counter. This counter is used by the |
810 | * wait_seqno code to race-free noticed that a reset event happened and | |
811 | * that it needs to restart the entire ioctl (since most likely the | |
812 | * seqno it waited for won't ever signal anytime soon). | |
813 | * | |
814 | * This is important for lock-free wait paths, where no contended lock | |
815 | * naturally enforces the correct ordering between the bail-out of the | |
816 | * waiter and the gpu reset work code. | |
1f83fee0 DV |
817 | * |
818 | * Lowest bit controls the reset state machine: Set means a reset is in | |
819 | * progress. This state will (presuming we don't have any bugs) decay | |
820 | * into either unset (successful reset) or the special WEDGED value (hw | |
821 | * terminally sour). All waiters on the reset_queue will be woken when | |
822 | * that happens. | |
823 | */ | |
824 | atomic_t reset_counter; | |
825 | ||
826 | /** | |
827 | * Special values/flags for reset_counter | |
828 | * | |
829 | * Note that the code relies on | |
830 | * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG | |
831 | * being true. | |
832 | */ | |
833 | #define I915_RESET_IN_PROGRESS_FLAG 1 | |
834 | #define I915_WEDGED 0xffffffff | |
835 | ||
836 | /** | |
837 | * Waitqueue to signal when the reset has completed. Used by clients | |
838 | * that wait for dev_priv->mm.wedged to settle. | |
839 | */ | |
840 | wait_queue_head_t reset_queue; | |
33196ded | 841 | |
99584db3 DV |
842 | /* For gpu hang simulation. */ |
843 | unsigned int stop_rings; | |
844 | }; | |
845 | ||
f4c956ad DV |
846 | typedef struct drm_i915_private { |
847 | struct drm_device *dev; | |
42dcedd4 | 848 | struct kmem_cache *slab; |
f4c956ad DV |
849 | |
850 | const struct intel_device_info *info; | |
851 | ||
852 | int relative_constants_mode; | |
853 | ||
854 | void __iomem *regs; | |
855 | ||
856 | struct drm_i915_gt_funcs gt; | |
857 | /** gt_fifo_count and the subsequent register write are synchronized | |
858 | * with dev->struct_mutex. */ | |
859 | unsigned gt_fifo_count; | |
860 | /** forcewake_count is protected by gt_lock */ | |
861 | unsigned forcewake_count; | |
862 | /** gt_lock is also taken in irq contexts. */ | |
99057c81 | 863 | spinlock_t gt_lock; |
f4c956ad DV |
864 | |
865 | struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; | |
866 | ||
28c70f16 | 867 | |
f4c956ad DV |
868 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
869 | * controller on different i2c buses. */ | |
870 | struct mutex gmbus_mutex; | |
871 | ||
872 | /** | |
873 | * Base address of the gmbus and gpio block. | |
874 | */ | |
875 | uint32_t gpio_mmio_base; | |
876 | ||
28c70f16 DV |
877 | wait_queue_head_t gmbus_wait_queue; |
878 | ||
f4c956ad DV |
879 | struct pci_dev *bridge_dev; |
880 | struct intel_ring_buffer ring[I915_NUM_RINGS]; | |
f72b3435 | 881 | uint32_t last_seqno, next_seqno; |
f4c956ad DV |
882 | |
883 | drm_dma_handle_t *status_page_dmah; | |
f4c956ad DV |
884 | struct resource mch_res; |
885 | ||
886 | atomic_t irq_received; | |
887 | ||
888 | /* protects the irq masks */ | |
889 | spinlock_t irq_lock; | |
890 | ||
9ee32fea DV |
891 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
892 | struct pm_qos_request pm_qos; | |
893 | ||
f4c956ad | 894 | /* DPIO indirect register protection */ |
09153000 | 895 | struct mutex dpio_lock; |
f4c956ad DV |
896 | |
897 | /** Cached value of IMR to avoid reads in updating the bitfield */ | |
898 | u32 pipestat[2]; | |
899 | u32 irq_mask; | |
900 | u32 gt_irq_mask; | |
f4c956ad DV |
901 | |
902 | u32 hotplug_supported_mask; | |
903 | struct work_struct hotplug_work; | |
52d7eced | 904 | bool enable_hotplug_processing; |
f4c956ad DV |
905 | |
906 | int num_pipe; | |
907 | int num_pch_pll; | |
908 | ||
f4c956ad DV |
909 | unsigned long cfb_size; |
910 | unsigned int cfb_fb; | |
911 | enum plane cfb_plane; | |
912 | int cfb_y; | |
913 | struct intel_fbc_work *fbc_work; | |
914 | ||
915 | struct intel_opregion opregion; | |
916 | ||
917 | /* overlay */ | |
918 | struct intel_overlay *overlay; | |
919 | bool sprite_scaling_enabled; | |
920 | ||
921 | /* LVDS info */ | |
922 | int backlight_level; /* restore backlight to this value */ | |
923 | bool backlight_enabled; | |
924 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ | |
925 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
926 | ||
927 | /* Feature bits from the VBIOS */ | |
928 | unsigned int int_tv_support:1; | |
929 | unsigned int lvds_dither:1; | |
930 | unsigned int lvds_vbt:1; | |
931 | unsigned int int_crt_support:1; | |
932 | unsigned int lvds_use_ssc:1; | |
933 | unsigned int display_clock_mode:1; | |
934 | int lvds_ssc_freq; | |
935 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ | |
f4c956ad DV |
936 | struct { |
937 | int rate; | |
938 | int lanes; | |
939 | int preemphasis; | |
940 | int vswing; | |
941 | ||
942 | bool initialized; | |
943 | bool support; | |
944 | int bpp; | |
945 | struct edp_power_seq pps; | |
946 | } edp; | |
947 | bool no_aux_handshake; | |
948 | ||
949 | int crt_ddc_pin; | |
950 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ | |
951 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ | |
952 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ | |
953 | ||
954 | unsigned int fsb_freq, mem_freq, is_ddr3; | |
955 | ||
f4c956ad DV |
956 | struct workqueue_struct *wq; |
957 | ||
958 | /* Display functions */ | |
959 | struct drm_i915_display_funcs display; | |
960 | ||
961 | /* PCH chipset type */ | |
962 | enum intel_pch pch_type; | |
17a303ec | 963 | unsigned short pch_id; |
f4c956ad DV |
964 | |
965 | unsigned long quirks; | |
966 | ||
967 | /* Register state */ | |
968 | bool modeset_on_lid; | |
673a394b | 969 | |
5d4545ae BW |
970 | struct i915_gtt gtt; |
971 | ||
4b5aed62 | 972 | struct i915_gem_mm mm; |
8781342d | 973 | |
8781342d DV |
974 | /* Kernel Modesetting */ |
975 | ||
9b9d172d | 976 | struct sdvo_device_mapping sdvo_mappings[2]; |
a3e17eb8 ZY |
977 | /* indicate whether the LVDS_BORDER should be enabled or not */ |
978 | unsigned int lvds_border_bits; | |
1d8e1c75 CW |
979 | /* Panel fitter placement and size for Ironlake+ */ |
980 | u32 pch_pf_pos, pch_pf_size; | |
652c393a | 981 | |
27f8227b JB |
982 | struct drm_crtc *plane_to_crtc_mapping[3]; |
983 | struct drm_crtc *pipe_to_crtc_mapping[3]; | |
6b95a207 KH |
984 | wait_queue_head_t pending_flip_queue; |
985 | ||
ee7b9f93 | 986 | struct intel_pch_pll pch_plls[I915_NUM_PLLS]; |
6441ab5f | 987 | struct intel_ddi_plls ddi_plls; |
ee7b9f93 | 988 | |
652c393a JB |
989 | /* Reclocking support */ |
990 | bool render_reclock_avail; | |
991 | bool lvds_downclock_avail; | |
18f9ed12 ZY |
992 | /* indicates the reduced downclock for LVDS*/ |
993 | int lvds_downclock; | |
652c393a | 994 | u16 orig_clock; |
6363ee6f ZY |
995 | int child_dev_num; |
996 | struct child_device_config *child_dev; | |
f97108d1 | 997 | |
c4804411 | 998 | bool mchbar_need_disable; |
f97108d1 | 999 | |
a4da4fa4 DV |
1000 | struct intel_l3_parity l3_parity; |
1001 | ||
c6a828d3 | 1002 | /* gen6+ rps state */ |
c85aa885 | 1003 | struct intel_gen6_power_mgmt rps; |
c6a828d3 | 1004 | |
20e4d407 DV |
1005 | /* ilk-only ips/rps state. Everything in here is protected by the global |
1006 | * mchdev_lock in intel_pm.c */ | |
c85aa885 | 1007 | struct intel_ilk_power_mgmt ips; |
b5e50c3f JB |
1008 | |
1009 | enum no_fbc_reason no_fbc_reason; | |
38651674 | 1010 | |
20bf377e JB |
1011 | struct drm_mm_node *compressed_fb; |
1012 | struct drm_mm_node *compressed_llb; | |
34dc4d44 | 1013 | |
99584db3 | 1014 | struct i915_gpu_error gpu_error; |
ae681d96 | 1015 | |
8be48d92 DA |
1016 | /* list of fbdev register on this device */ |
1017 | struct intel_fbdev *fbdev; | |
e953fd7b | 1018 | |
073f34d9 JB |
1019 | /* |
1020 | * The console may be contended at resume, but we don't | |
1021 | * want it to block on it. | |
1022 | */ | |
1023 | struct work_struct console_resume_work; | |
1024 | ||
aaa6fd2a MG |
1025 | struct backlight_device *backlight; |
1026 | ||
e953fd7b | 1027 | struct drm_property *broadcast_rgb_property; |
3f43c48d | 1028 | struct drm_property *force_audio_property; |
e3689190 | 1029 | |
254f965c BW |
1030 | bool hw_contexts_disabled; |
1031 | uint32_t hw_context_size; | |
f4c956ad | 1032 | |
68d18ad7 PZ |
1033 | bool fdi_rx_polarity_reversed; |
1034 | ||
f4c956ad | 1035 | struct i915_suspend_saved_registers regfile; |
231f42a4 DV |
1036 | |
1037 | /* Old dri1 support infrastructure, beware the dragons ya fools entering | |
1038 | * here! */ | |
1039 | struct i915_dri1_state dri1; | |
1da177e4 LT |
1040 | } drm_i915_private_t; |
1041 | ||
b4519513 CW |
1042 | /* Iterate over initialised rings */ |
1043 | #define for_each_ring(ring__, dev_priv__, i__) \ | |
1044 | for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ | |
1045 | if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) | |
1046 | ||
b1d7e4b4 WF |
1047 | enum hdmi_force_audio { |
1048 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ | |
1049 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ | |
1050 | HDMI_AUDIO_AUTO, /* trust EDID */ | |
1051 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ | |
1052 | }; | |
1053 | ||
ed2f3452 CW |
1054 | #define I915_GTT_RESERVED ((struct drm_mm_node *)0x1) |
1055 | ||
37e680a1 CW |
1056 | struct drm_i915_gem_object_ops { |
1057 | /* Interface between the GEM object and its backing storage. | |
1058 | * get_pages() is called once prior to the use of the associated set | |
1059 | * of pages before to binding them into the GTT, and put_pages() is | |
1060 | * called after we no longer need them. As we expect there to be | |
1061 | * associated cost with migrating pages between the backing storage | |
1062 | * and making them available for the GPU (e.g. clflush), we may hold | |
1063 | * onto the pages after they are no longer referenced by the GPU | |
1064 | * in case they may be used again shortly (for example migrating the | |
1065 | * pages to a different memory domain within the GTT). put_pages() | |
1066 | * will therefore most likely be called when the object itself is | |
1067 | * being released or under memory pressure (where we attempt to | |
1068 | * reap pages for the shrinker). | |
1069 | */ | |
1070 | int (*get_pages)(struct drm_i915_gem_object *); | |
1071 | void (*put_pages)(struct drm_i915_gem_object *); | |
1072 | }; | |
1073 | ||
673a394b | 1074 | struct drm_i915_gem_object { |
c397b908 | 1075 | struct drm_gem_object base; |
673a394b | 1076 | |
37e680a1 CW |
1077 | const struct drm_i915_gem_object_ops *ops; |
1078 | ||
673a394b EA |
1079 | /** Current space allocated to this object in the GTT, if any. */ |
1080 | struct drm_mm_node *gtt_space; | |
c1ad11fc CW |
1081 | /** Stolen memory for this object, instead of being backed by shmem. */ |
1082 | struct drm_mm_node *stolen; | |
93a37f20 | 1083 | struct list_head gtt_list; |
673a394b | 1084 | |
65ce3027 | 1085 | /** This object's place on the active/inactive lists */ |
69dc4987 CW |
1086 | struct list_head ring_list; |
1087 | struct list_head mm_list; | |
432e58ed CW |
1088 | /** This object's place in the batchbuffer or on the eviction list */ |
1089 | struct list_head exec_list; | |
673a394b EA |
1090 | |
1091 | /** | |
65ce3027 CW |
1092 | * This is set if the object is on the active lists (has pending |
1093 | * rendering and so a non-zero seqno), and is not set if it i s on | |
1094 | * inactive (ready to be unbound) list. | |
673a394b | 1095 | */ |
0206e353 | 1096 | unsigned int active:1; |
673a394b EA |
1097 | |
1098 | /** | |
1099 | * This is set if the object has been written to since last bound | |
1100 | * to the GTT | |
1101 | */ | |
0206e353 | 1102 | unsigned int dirty:1; |
778c3544 DV |
1103 | |
1104 | /** | |
1105 | * Fence register bits (if any) for this object. Will be set | |
1106 | * as needed when mapped into the GTT. | |
1107 | * Protected by dev->struct_mutex. | |
778c3544 | 1108 | */ |
4b9de737 | 1109 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
778c3544 | 1110 | |
778c3544 DV |
1111 | /** |
1112 | * Advice: are the backing pages purgeable? | |
1113 | */ | |
0206e353 | 1114 | unsigned int madv:2; |
778c3544 | 1115 | |
778c3544 DV |
1116 | /** |
1117 | * Current tiling mode for the object. | |
1118 | */ | |
0206e353 | 1119 | unsigned int tiling_mode:2; |
5d82e3e6 CW |
1120 | /** |
1121 | * Whether the tiling parameters for the currently associated fence | |
1122 | * register have changed. Note that for the purposes of tracking | |
1123 | * tiling changes we also treat the unfenced register, the register | |
1124 | * slot that the object occupies whilst it executes a fenced | |
1125 | * command (such as BLT on gen2/3), as a "fence". | |
1126 | */ | |
1127 | unsigned int fence_dirty:1; | |
778c3544 DV |
1128 | |
1129 | /** How many users have pinned this object in GTT space. The following | |
1130 | * users can each hold at most one reference: pwrite/pread, pin_ioctl | |
1131 | * (via user_pin_count), execbuffer (objects are not allowed multiple | |
1132 | * times for the same batchbuffer), and the framebuffer code. When | |
1133 | * switching/pageflipping, the framebuffer code has at most two buffers | |
1134 | * pinned per crtc. | |
1135 | * | |
1136 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 | |
1137 | * bits with absolutely no headroom. So use 4 bits. */ | |
0206e353 | 1138 | unsigned int pin_count:4; |
778c3544 | 1139 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf |
673a394b | 1140 | |
75e9e915 DV |
1141 | /** |
1142 | * Is the object at the current location in the gtt mappable and | |
1143 | * fenceable? Used to avoid costly recalculations. | |
1144 | */ | |
0206e353 | 1145 | unsigned int map_and_fenceable:1; |
75e9e915 | 1146 | |
fb7d516a DV |
1147 | /** |
1148 | * Whether the current gtt mapping needs to be mappable (and isn't just | |
1149 | * mappable by accident). Track pin and fault separate for a more | |
1150 | * accurate mappable working set. | |
1151 | */ | |
0206e353 AJ |
1152 | unsigned int fault_mappable:1; |
1153 | unsigned int pin_mappable:1; | |
fb7d516a | 1154 | |
caea7476 CW |
1155 | /* |
1156 | * Is the GPU currently using a fence to access this buffer, | |
1157 | */ | |
1158 | unsigned int pending_fenced_gpu_access:1; | |
1159 | unsigned int fenced_gpu_access:1; | |
1160 | ||
93dfb40c CW |
1161 | unsigned int cache_level:2; |
1162 | ||
7bddb01f | 1163 | unsigned int has_aliasing_ppgtt_mapping:1; |
74898d7e | 1164 | unsigned int has_global_gtt_mapping:1; |
9da3da66 | 1165 | unsigned int has_dma_mapping:1; |
7bddb01f | 1166 | |
9da3da66 | 1167 | struct sg_table *pages; |
a5570178 | 1168 | int pages_pin_count; |
673a394b | 1169 | |
1286ff73 | 1170 | /* prime dma-buf support */ |
9a70cc2a DA |
1171 | void *dma_buf_vmapping; |
1172 | int vmapping_count; | |
1173 | ||
67731b87 CW |
1174 | /** |
1175 | * Used for performing relocations during execbuffer insertion. | |
1176 | */ | |
1177 | struct hlist_node exec_node; | |
1178 | unsigned long exec_handle; | |
6fe4f140 | 1179 | struct drm_i915_gem_exec_object2 *exec_entry; |
67731b87 | 1180 | |
673a394b EA |
1181 | /** |
1182 | * Current offset of the object in GTT space. | |
1183 | * | |
1184 | * This is the same as gtt_space->start | |
1185 | */ | |
1186 | uint32_t gtt_offset; | |
e67b8ce1 | 1187 | |
caea7476 CW |
1188 | struct intel_ring_buffer *ring; |
1189 | ||
1c293ea3 | 1190 | /** Breadcrumb of last rendering to the buffer. */ |
0201f1ec CW |
1191 | uint32_t last_read_seqno; |
1192 | uint32_t last_write_seqno; | |
caea7476 CW |
1193 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
1194 | uint32_t last_fenced_seqno; | |
673a394b | 1195 | |
778c3544 | 1196 | /** Current tiling stride for the object, if it's tiled. */ |
de151cf6 | 1197 | uint32_t stride; |
673a394b | 1198 | |
280b713b | 1199 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 1200 | unsigned long *bit_17; |
280b713b | 1201 | |
79e53945 JB |
1202 | /** User space pin count and filp owning the pin */ |
1203 | uint32_t user_pin_count; | |
1204 | struct drm_file *pin_filp; | |
71acb5eb DA |
1205 | |
1206 | /** for phy allocated objects */ | |
1207 | struct drm_i915_gem_phys_object *phys_obj; | |
b70d11da | 1208 | |
6b95a207 KH |
1209 | /** |
1210 | * Number of crtcs where this object is currently the fb, but | |
1211 | * will be page flipped away on the next vblank. When it | |
1212 | * reaches 0, dev_priv->pending_flip_queue will be woken up. | |
1213 | */ | |
1214 | atomic_t pending_flip; | |
673a394b | 1215 | }; |
b45305fc | 1216 | #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base) |
673a394b | 1217 | |
62b8b215 | 1218 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
23010e43 | 1219 | |
673a394b EA |
1220 | /** |
1221 | * Request queue structure. | |
1222 | * | |
1223 | * The request queue allows us to note sequence numbers that have been emitted | |
1224 | * and may be associated with active buffers to be retired. | |
1225 | * | |
1226 | * By keeping this list, we can avoid having to do questionable | |
1227 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate | |
1228 | * an emission time with seqnos for tracking how far ahead of the GPU we are. | |
1229 | */ | |
1230 | struct drm_i915_gem_request { | |
852835f3 ZN |
1231 | /** On Which ring this request was generated */ |
1232 | struct intel_ring_buffer *ring; | |
1233 | ||
673a394b EA |
1234 | /** GEM sequence number associated with this request. */ |
1235 | uint32_t seqno; | |
1236 | ||
a71d8d94 CW |
1237 | /** Postion in the ringbuffer of the end of the request */ |
1238 | u32 tail; | |
1239 | ||
673a394b EA |
1240 | /** Time at which this request was emitted, in jiffies. */ |
1241 | unsigned long emitted_jiffies; | |
1242 | ||
b962442e | 1243 | /** global list entry for this request */ |
673a394b | 1244 | struct list_head list; |
b962442e | 1245 | |
f787a5f5 | 1246 | struct drm_i915_file_private *file_priv; |
b962442e EA |
1247 | /** file_priv list entry for this request */ |
1248 | struct list_head client_list; | |
673a394b EA |
1249 | }; |
1250 | ||
1251 | struct drm_i915_file_private { | |
1252 | struct { | |
99057c81 | 1253 | spinlock_t lock; |
b962442e | 1254 | struct list_head request_list; |
673a394b | 1255 | } mm; |
40521054 | 1256 | struct idr context_idr; |
673a394b EA |
1257 | }; |
1258 | ||
cae5852d ZN |
1259 | #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) |
1260 | ||
1261 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) | |
1262 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) | |
1263 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) | |
1264 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) | |
1265 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) | |
1266 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) | |
1267 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) | |
1268 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) | |
1269 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) | |
1270 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
1271 | #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) | |
1272 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) | |
1273 | #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) | |
1274 | #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) | |
1275 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) | |
1276 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
1277 | #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) | |
1278 | #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) | |
4b65177b | 1279 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
8ab43976 JB |
1280 | #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \ |
1281 | (dev)->pci_device == 0x0152 || \ | |
1282 | (dev)->pci_device == 0x015a) | |
6547fbdb DV |
1283 | #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \ |
1284 | (dev)->pci_device == 0x0106 || \ | |
1285 | (dev)->pci_device == 0x010A) | |
70a3eb7a | 1286 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
4cae9ae0 | 1287 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
cae5852d | 1288 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
d567b07f PZ |
1289 | #define IS_ULT(dev) (IS_HASWELL(dev) && \ |
1290 | ((dev)->pci_device & 0xFF00) == 0x0A00) | |
cae5852d | 1291 | |
85436696 JB |
1292 | /* |
1293 | * The genX designation typically refers to the render engine, so render | |
1294 | * capability related checks should use IS_GEN, while display and other checks | |
1295 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
1296 | * chips, etc.). | |
1297 | */ | |
cae5852d ZN |
1298 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
1299 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) | |
1300 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) | |
1301 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) | |
1302 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) | |
85436696 | 1303 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
cae5852d ZN |
1304 | |
1305 | #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) | |
1306 | #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) | |
3d29b842 | 1307 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) |
cae5852d ZN |
1308 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
1309 | ||
254f965c | 1310 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) |
93553609 | 1311 | #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev)) |
1d2a314c | 1312 | |
05394f39 | 1313 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
cae5852d ZN |
1314 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
1315 | ||
b45305fc DV |
1316 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
1317 | #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) | |
1318 | ||
cae5852d ZN |
1319 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
1320 | * rows, which changed the alignment requirements and fence programming. | |
1321 | */ | |
1322 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ | |
1323 | IS_I915GM(dev))) | |
1324 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) | |
1325 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
1326 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
1327 | #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) | |
1328 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) | |
1329 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) | |
1330 | /* dsparb controlled by hw only */ | |
1331 | #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) | |
1332 | ||
1333 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) | |
1334 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) | |
1335 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) | |
cae5852d | 1336 | |
eceae481 | 1337 | #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) |
cae5852d | 1338 | |
affa9354 PZ |
1339 | #define HAS_DDI(dev) (IS_HASWELL(dev)) |
1340 | ||
17a303ec PZ |
1341 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
1342 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 | |
1343 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 | |
1344 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 | |
1345 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 | |
1346 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 | |
1347 | ||
cae5852d | 1348 | #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) |
eb877ebf | 1349 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
cae5852d ZN |
1350 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
1351 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) | |
45e6e3a1 | 1352 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
cae5852d | 1353 | |
b7884eb4 DV |
1354 | #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake) |
1355 | ||
f27b9265 | 1356 | #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
e1ef7cc2 | 1357 | |
c8735b0c BW |
1358 | #define GT_FREQUENCY_MULTIPLIER 50 |
1359 | ||
05394f39 CW |
1360 | #include "i915_trace.h" |
1361 | ||
83b7f9ac ED |
1362 | /** |
1363 | * RC6 is a special power stage which allows the GPU to enter an very | |
1364 | * low-voltage mode when idle, using down to 0V while at this stage. This | |
1365 | * stage is entered automatically when the GPU is idle when RC6 support is | |
1366 | * enabled, and as soon as new workload arises GPU wakes up automatically as well. | |
1367 | * | |
1368 | * There are different RC6 modes available in Intel GPU, which differentiate | |
1369 | * among each other with the latency required to enter and leave RC6 and | |
1370 | * voltage consumed by the GPU in different states. | |
1371 | * | |
1372 | * The combination of the following flags define which states GPU is allowed | |
1373 | * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and | |
1374 | * RC6pp is deepest RC6. Their support by hardware varies according to the | |
1375 | * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one | |
1376 | * which brings the most power savings; deeper states save more power, but | |
1377 | * require higher latency to switch to and wake up. | |
1378 | */ | |
1379 | #define INTEL_RC6_ENABLE (1<<0) | |
1380 | #define INTEL_RC6p_ENABLE (1<<1) | |
1381 | #define INTEL_RC6pp_ENABLE (1<<2) | |
1382 | ||
c153f45f | 1383 | extern struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 | 1384 | extern int i915_max_ioctl; |
a35d9d3c BW |
1385 | extern unsigned int i915_fbpercrtc __always_unused; |
1386 | extern int i915_panel_ignore_lid __read_mostly; | |
1387 | extern unsigned int i915_powersave __read_mostly; | |
f45b5557 | 1388 | extern int i915_semaphores __read_mostly; |
a35d9d3c | 1389 | extern unsigned int i915_lvds_downclock __read_mostly; |
121d527a | 1390 | extern int i915_lvds_channel_mode __read_mostly; |
4415e63b | 1391 | extern int i915_panel_use_ssc __read_mostly; |
a35d9d3c | 1392 | extern int i915_vbt_sdvo_panel_type __read_mostly; |
c0f372b3 | 1393 | extern int i915_enable_rc6 __read_mostly; |
4415e63b | 1394 | extern int i915_enable_fbc __read_mostly; |
a35d9d3c | 1395 | extern bool i915_enable_hangcheck __read_mostly; |
650dc07e | 1396 | extern int i915_enable_ppgtt __read_mostly; |
0a3af268 | 1397 | extern unsigned int i915_preliminary_hw_support __read_mostly; |
b3a83639 | 1398 | |
6a9ee8af DA |
1399 | extern int i915_suspend(struct drm_device *dev, pm_message_t state); |
1400 | extern int i915_resume(struct drm_device *dev); | |
7c1c2871 DA |
1401 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
1402 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); | |
1403 | ||
1da177e4 | 1404 | /* i915_dma.c */ |
d05c617e | 1405 | void i915_update_dri1_breadcrumb(struct drm_device *dev); |
84b1fd10 | 1406 | extern void i915_kernel_lost_context(struct drm_device * dev); |
22eae947 | 1407 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 1408 | extern int i915_driver_unload(struct drm_device *); |
673a394b | 1409 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
84b1fd10 | 1410 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac EA |
1411 | extern void i915_driver_preclose(struct drm_device *dev, |
1412 | struct drm_file *file_priv); | |
673a394b EA |
1413 | extern void i915_driver_postclose(struct drm_device *dev, |
1414 | struct drm_file *file_priv); | |
84b1fd10 | 1415 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
c43b5634 | 1416 | #ifdef CONFIG_COMPAT |
0d6aa60b DA |
1417 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
1418 | unsigned long arg); | |
c43b5634 | 1419 | #endif |
673a394b | 1420 | extern int i915_emit_box(struct drm_device *dev, |
c4e7a414 CW |
1421 | struct drm_clip_rect *box, |
1422 | int DR1, int DR4); | |
8e96d9c4 | 1423 | extern int intel_gpu_reset(struct drm_device *dev); |
d4b8bb2a | 1424 | extern int i915_reset(struct drm_device *dev); |
7648fa99 JB |
1425 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
1426 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
1427 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
1428 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
1429 | ||
073f34d9 | 1430 | extern void intel_console_resume(struct work_struct *work); |
af6061af | 1431 | |
1da177e4 | 1432 | /* i915_irq.c */ |
f65d9421 | 1433 | void i915_hangcheck_elapsed(unsigned long data); |
527f9e90 | 1434 | void i915_handle_error(struct drm_device *dev, bool wedged); |
1da177e4 | 1435 | |
f71d4af4 | 1436 | extern void intel_irq_init(struct drm_device *dev); |
20afbda2 | 1437 | extern void intel_hpd_init(struct drm_device *dev); |
990bbdad | 1438 | extern void intel_gt_init(struct drm_device *dev); |
16995a9f | 1439 | extern void intel_gt_reset(struct drm_device *dev); |
b1f14ad0 | 1440 | |
742cbee8 DV |
1441 | void i915_error_state_free(struct kref *error_ref); |
1442 | ||
7c463586 KP |
1443 | void |
1444 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
1445 | ||
1446 | void | |
1447 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
1448 | ||
0206e353 | 1449 | void intel_enable_asle(struct drm_device *dev); |
01c66889 | 1450 | |
3bd3c932 CW |
1451 | #ifdef CONFIG_DEBUG_FS |
1452 | extern void i915_destroy_error_state(struct drm_device *dev); | |
1453 | #else | |
1454 | #define i915_destroy_error_state(x) | |
1455 | #endif | |
1456 | ||
7c463586 | 1457 | |
673a394b EA |
1458 | /* i915_gem.c */ |
1459 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
1460 | struct drm_file *file_priv); | |
1461 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
1462 | struct drm_file *file_priv); | |
1463 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
1464 | struct drm_file *file_priv); | |
1465 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
1466 | struct drm_file *file_priv); | |
1467 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1468 | struct drm_file *file_priv); | |
de151cf6 JB |
1469 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
1470 | struct drm_file *file_priv); | |
673a394b EA |
1471 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
1472 | struct drm_file *file_priv); | |
1473 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1474 | struct drm_file *file_priv); | |
1475 | int i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1476 | struct drm_file *file_priv); | |
76446cac JB |
1477 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
1478 | struct drm_file *file_priv); | |
673a394b EA |
1479 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
1480 | struct drm_file *file_priv); | |
1481 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
1482 | struct drm_file *file_priv); | |
1483 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
1484 | struct drm_file *file_priv); | |
199adf40 BW |
1485 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
1486 | struct drm_file *file); | |
1487 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, | |
1488 | struct drm_file *file); | |
673a394b EA |
1489 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
1490 | struct drm_file *file_priv); | |
3ef94daa CW |
1491 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
1492 | struct drm_file *file_priv); | |
673a394b EA |
1493 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
1494 | struct drm_file *file_priv); | |
1495 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
1496 | struct drm_file *file_priv); | |
1497 | int i915_gem_set_tiling(struct drm_device *dev, void *data, | |
1498 | struct drm_file *file_priv); | |
1499 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
1500 | struct drm_file *file_priv); | |
5a125c3c EA |
1501 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
1502 | struct drm_file *file_priv); | |
23ba4fd0 BW |
1503 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
1504 | struct drm_file *file_priv); | |
673a394b | 1505 | void i915_gem_load(struct drm_device *dev); |
42dcedd4 CW |
1506 | void *i915_gem_object_alloc(struct drm_device *dev); |
1507 | void i915_gem_object_free(struct drm_i915_gem_object *obj); | |
673a394b | 1508 | int i915_gem_init_object(struct drm_gem_object *obj); |
37e680a1 CW |
1509 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
1510 | const struct drm_i915_gem_object_ops *ops); | |
05394f39 CW |
1511 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
1512 | size_t size); | |
673a394b | 1513 | void i915_gem_free_object(struct drm_gem_object *obj); |
42dcedd4 | 1514 | |
2021746e CW |
1515 | int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, |
1516 | uint32_t alignment, | |
86a1ee26 CW |
1517 | bool map_and_fenceable, |
1518 | bool nonblocking); | |
05394f39 | 1519 | void i915_gem_object_unpin(struct drm_i915_gem_object *obj); |
2021746e | 1520 | int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj); |
dd624afd | 1521 | int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); |
05394f39 | 1522 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
673a394b | 1523 | void i915_gem_lastclose(struct drm_device *dev); |
f787a5f5 | 1524 | |
37e680a1 | 1525 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
9da3da66 CW |
1526 | static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) |
1527 | { | |
1528 | struct scatterlist *sg = obj->pages->sgl; | |
1cf83789 CW |
1529 | int nents = obj->pages->nents; |
1530 | while (nents > SG_MAX_SINGLE_ALLOC) { | |
1531 | if (n < SG_MAX_SINGLE_ALLOC - 1) | |
1532 | break; | |
1533 | ||
9da3da66 CW |
1534 | sg = sg_chain_ptr(sg + SG_MAX_SINGLE_ALLOC - 1); |
1535 | n -= SG_MAX_SINGLE_ALLOC - 1; | |
1cf83789 | 1536 | nents -= SG_MAX_SINGLE_ALLOC - 1; |
9da3da66 CW |
1537 | } |
1538 | return sg_page(sg+n); | |
1539 | } | |
a5570178 CW |
1540 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
1541 | { | |
1542 | BUG_ON(obj->pages == NULL); | |
1543 | obj->pages_pin_count++; | |
1544 | } | |
1545 | static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) | |
1546 | { | |
1547 | BUG_ON(obj->pages_pin_count == 0); | |
1548 | obj->pages_pin_count--; | |
1549 | } | |
1550 | ||
54cf91dc | 1551 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
2911a35b BW |
1552 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
1553 | struct intel_ring_buffer *to); | |
54cf91dc | 1554 | void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
9d773091 | 1555 | struct intel_ring_buffer *ring); |
54cf91dc | 1556 | |
ff72145b DA |
1557 | int i915_gem_dumb_create(struct drm_file *file_priv, |
1558 | struct drm_device *dev, | |
1559 | struct drm_mode_create_dumb *args); | |
1560 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, | |
1561 | uint32_t handle, uint64_t *offset); | |
1562 | int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, | |
0206e353 | 1563 | uint32_t handle); |
f787a5f5 CW |
1564 | /** |
1565 | * Returns true if seq1 is later than seq2. | |
1566 | */ | |
1567 | static inline bool | |
1568 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) | |
1569 | { | |
1570 | return (int32_t)(seq1 - seq2) >= 0; | |
1571 | } | |
1572 | ||
fca26bb4 MK |
1573 | int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); |
1574 | int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); | |
06d98131 | 1575 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); |
d9e86c0e | 1576 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); |
2021746e | 1577 | |
9a5a53b3 | 1578 | static inline bool |
1690e1eb CW |
1579 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) |
1580 | { | |
1581 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1582 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1583 | dev_priv->fence_regs[obj->fence_reg].pin_count++; | |
9a5a53b3 CW |
1584 | return true; |
1585 | } else | |
1586 | return false; | |
1690e1eb CW |
1587 | } |
1588 | ||
1589 | static inline void | |
1590 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) | |
1591 | { | |
1592 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1593 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1594 | dev_priv->fence_regs[obj->fence_reg].pin_count--; | |
1595 | } | |
1596 | } | |
1597 | ||
b09a1fec | 1598 | void i915_gem_retire_requests(struct drm_device *dev); |
a71d8d94 | 1599 | void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); |
33196ded | 1600 | int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, |
d6b2c790 | 1601 | bool interruptible); |
1f83fee0 DV |
1602 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) |
1603 | { | |
1604 | return unlikely(atomic_read(&error->reset_counter) | |
1605 | & I915_RESET_IN_PROGRESS_FLAG); | |
1606 | } | |
1607 | ||
1608 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) | |
1609 | { | |
1610 | return atomic_read(&error->reset_counter) == I915_WEDGED; | |
1611 | } | |
a71d8d94 | 1612 | |
069efc1d | 1613 | void i915_gem_reset(struct drm_device *dev); |
05394f39 | 1614 | void i915_gem_clflush_object(struct drm_i915_gem_object *obj); |
2021746e CW |
1615 | int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj, |
1616 | uint32_t read_domains, | |
1617 | uint32_t write_domain); | |
a8198eea | 1618 | int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); |
1070a42b | 1619 | int __must_check i915_gem_init(struct drm_device *dev); |
f691e2f4 | 1620 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
b9524a1e | 1621 | void i915_gem_l3_remap(struct drm_device *dev); |
f691e2f4 | 1622 | void i915_gem_init_swizzling(struct drm_device *dev); |
e21af88d | 1623 | void i915_gem_init_ppgtt(struct drm_device *dev); |
79e53945 | 1624 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
b2da9fe5 | 1625 | int __must_check i915_gpu_idle(struct drm_device *dev); |
2021746e | 1626 | int __must_check i915_gem_idle(struct drm_device *dev); |
3bb73aba CW |
1627 | int i915_add_request(struct intel_ring_buffer *ring, |
1628 | struct drm_file *file, | |
acb868d3 | 1629 | u32 *seqno); |
199b2bc2 BW |
1630 | int __must_check i915_wait_seqno(struct intel_ring_buffer *ring, |
1631 | uint32_t seqno); | |
de151cf6 | 1632 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
2021746e CW |
1633 | int __must_check |
1634 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, | |
1635 | bool write); | |
1636 | int __must_check | |
dabdfe02 CW |
1637 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
1638 | int __must_check | |
2da3b9b9 CW |
1639 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
1640 | u32 alignment, | |
2021746e | 1641 | struct intel_ring_buffer *pipelined); |
71acb5eb | 1642 | int i915_gem_attach_phys_object(struct drm_device *dev, |
05394f39 | 1643 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
1644 | int id, |
1645 | int align); | |
71acb5eb | 1646 | void i915_gem_detach_phys_object(struct drm_device *dev, |
05394f39 | 1647 | struct drm_i915_gem_object *obj); |
71acb5eb | 1648 | void i915_gem_free_all_phys_object(struct drm_device *dev); |
05394f39 | 1649 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 1650 | |
0fa87796 ID |
1651 | uint32_t |
1652 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); | |
467cffba | 1653 | uint32_t |
d865110c ID |
1654 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
1655 | int tiling_mode, bool fenced); | |
467cffba | 1656 | |
e4ffd173 CW |
1657 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
1658 | enum i915_cache_level cache_level); | |
1659 | ||
1286ff73 DV |
1660 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
1661 | struct dma_buf *dma_buf); | |
1662 | ||
1663 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, | |
1664 | struct drm_gem_object *gem_obj, int flags); | |
1665 | ||
254f965c BW |
1666 | /* i915_gem_context.c */ |
1667 | void i915_gem_context_init(struct drm_device *dev); | |
1668 | void i915_gem_context_fini(struct drm_device *dev); | |
254f965c | 1669 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); |
e0556841 BW |
1670 | int i915_switch_context(struct intel_ring_buffer *ring, |
1671 | struct drm_file *file, int to_id); | |
84624813 BW |
1672 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
1673 | struct drm_file *file); | |
1674 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
1675 | struct drm_file *file); | |
1286ff73 | 1676 | |
76aaf220 | 1677 | /* i915_gem_gtt.c */ |
1d2a314c | 1678 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); |
7bddb01f DV |
1679 | void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, |
1680 | struct drm_i915_gem_object *obj, | |
1681 | enum i915_cache_level cache_level); | |
1682 | void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, | |
1683 | struct drm_i915_gem_object *obj); | |
1d2a314c | 1684 | |
76aaf220 | 1685 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); |
74163907 DV |
1686 | int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); |
1687 | void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, | |
e4ffd173 | 1688 | enum i915_cache_level cache_level); |
05394f39 | 1689 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); |
74163907 | 1690 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); |
d7e5008f BW |
1691 | void i915_gem_init_global_gtt(struct drm_device *dev); |
1692 | void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start, | |
1693 | unsigned long mappable_end, unsigned long end); | |
e76e9aeb | 1694 | int i915_gem_gtt_init(struct drm_device *dev); |
d09105c6 | 1695 | static inline void i915_gem_chipset_flush(struct drm_device *dev) |
e76e9aeb BW |
1696 | { |
1697 | if (INTEL_INFO(dev)->gen < 6) | |
1698 | intel_gtt_chipset_flush(); | |
1699 | } | |
1700 | ||
76aaf220 | 1701 | |
b47eb4a2 | 1702 | /* i915_gem_evict.c */ |
2021746e | 1703 | int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size, |
42d6ab48 CW |
1704 | unsigned alignment, |
1705 | unsigned cache_level, | |
86a1ee26 CW |
1706 | bool mappable, |
1707 | bool nonblock); | |
6c085a72 | 1708 | int i915_gem_evict_everything(struct drm_device *dev); |
b47eb4a2 | 1709 | |
9797fbfb CW |
1710 | /* i915_gem_stolen.c */ |
1711 | int i915_gem_init_stolen(struct drm_device *dev); | |
11be49eb CW |
1712 | int i915_gem_stolen_setup_compression(struct drm_device *dev, int size); |
1713 | void i915_gem_stolen_cleanup_compression(struct drm_device *dev); | |
9797fbfb | 1714 | void i915_gem_cleanup_stolen(struct drm_device *dev); |
0104fdbb CW |
1715 | struct drm_i915_gem_object * |
1716 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); | |
1717 | void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj); | |
9797fbfb | 1718 | |
673a394b | 1719 | /* i915_gem_tiling.c */ |
e9b73c67 CW |
1720 | inline static bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
1721 | { | |
1722 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; | |
1723 | ||
1724 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
1725 | obj->tiling_mode != I915_TILING_NONE; | |
1726 | } | |
1727 | ||
673a394b | 1728 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
05394f39 CW |
1729 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
1730 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
673a394b EA |
1731 | |
1732 | /* i915_gem_debug.c */ | |
05394f39 | 1733 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, |
673a394b | 1734 | const char *where, uint32_t mark); |
23bc5982 CW |
1735 | #if WATCH_LISTS |
1736 | int i915_verify_lists(struct drm_device *dev); | |
673a394b | 1737 | #else |
23bc5982 | 1738 | #define i915_verify_lists(dev) 0 |
673a394b | 1739 | #endif |
05394f39 CW |
1740 | void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj, |
1741 | int handle); | |
1742 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, | |
673a394b | 1743 | const char *where, uint32_t mark); |
1da177e4 | 1744 | |
2017263e | 1745 | /* i915_debugfs.c */ |
27c202ad BG |
1746 | int i915_debugfs_init(struct drm_minor *minor); |
1747 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
2017263e | 1748 | |
317c35d1 JB |
1749 | /* i915_suspend.c */ |
1750 | extern int i915_save_state(struct drm_device *dev); | |
1751 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 | 1752 | |
d8157a36 DV |
1753 | /* i915_ums.c */ |
1754 | void i915_save_display_reg(struct drm_device *dev); | |
1755 | void i915_restore_display_reg(struct drm_device *dev); | |
317c35d1 | 1756 | |
0136db58 BW |
1757 | /* i915_sysfs.c */ |
1758 | void i915_setup_sysfs(struct drm_device *dev_priv); | |
1759 | void i915_teardown_sysfs(struct drm_device *dev_priv); | |
1760 | ||
f899fc64 CW |
1761 | /* intel_i2c.c */ |
1762 | extern int intel_setup_gmbus(struct drm_device *dev); | |
1763 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
3bd7d909 DK |
1764 | extern inline bool intel_gmbus_is_port_valid(unsigned port) |
1765 | { | |
2ed06c93 | 1766 | return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); |
3bd7d909 DK |
1767 | } |
1768 | ||
1769 | extern struct i2c_adapter *intel_gmbus_get_adapter( | |
1770 | struct drm_i915_private *dev_priv, unsigned port); | |
e957d772 CW |
1771 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
1772 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
b8232e90 CW |
1773 | extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
1774 | { | |
1775 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
1776 | } | |
f899fc64 CW |
1777 | extern void intel_i2c_reset(struct drm_device *dev); |
1778 | ||
3b617967 | 1779 | /* intel_opregion.c */ |
44834a67 CW |
1780 | extern int intel_opregion_setup(struct drm_device *dev); |
1781 | #ifdef CONFIG_ACPI | |
1782 | extern void intel_opregion_init(struct drm_device *dev); | |
1783 | extern void intel_opregion_fini(struct drm_device *dev); | |
3b617967 CW |
1784 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
1785 | extern void intel_opregion_gse_intr(struct drm_device *dev); | |
1786 | extern void intel_opregion_enable_asle(struct drm_device *dev); | |
65e082c9 | 1787 | #else |
44834a67 CW |
1788 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
1789 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } | |
3b617967 CW |
1790 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
1791 | static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; } | |
1792 | static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; } | |
65e082c9 | 1793 | #endif |
8ee1c3db | 1794 | |
723bfd70 JB |
1795 | /* intel_acpi.c */ |
1796 | #ifdef CONFIG_ACPI | |
1797 | extern void intel_register_dsm_handler(void); | |
1798 | extern void intel_unregister_dsm_handler(void); | |
1799 | #else | |
1800 | static inline void intel_register_dsm_handler(void) { return; } | |
1801 | static inline void intel_unregister_dsm_handler(void) { return; } | |
1802 | #endif /* CONFIG_ACPI */ | |
1803 | ||
79e53945 | 1804 | /* modesetting */ |
f817586c | 1805 | extern void intel_modeset_init_hw(struct drm_device *dev); |
79e53945 | 1806 | extern void intel_modeset_init(struct drm_device *dev); |
2c7111db | 1807 | extern void intel_modeset_gem_init(struct drm_device *dev); |
79e53945 | 1808 | extern void intel_modeset_cleanup(struct drm_device *dev); |
28d52043 | 1809 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
45e2b5f6 DV |
1810 | extern void intel_modeset_setup_hw_state(struct drm_device *dev, |
1811 | bool force_restore); | |
44cec740 | 1812 | extern void i915_redisable_vga(struct drm_device *dev); |
ee5382ae | 1813 | extern bool intel_fbc_enabled(struct drm_device *dev); |
43a9539f | 1814 | extern void intel_disable_fbc(struct drm_device *dev); |
7648fa99 | 1815 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
dde86e2d | 1816 | extern void intel_init_pch_refclk(struct drm_device *dev); |
3b8d8d91 | 1817 | extern void gen6_set_rps(struct drm_device *dev, u8 val); |
0206e353 AJ |
1818 | extern void intel_detect_pch(struct drm_device *dev); |
1819 | extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); | |
0136db58 | 1820 | extern int intel_enable_rc6(const struct drm_device *dev); |
3bad0781 | 1821 | |
2911a35b | 1822 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); |
c0c7babc BW |
1823 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
1824 | struct drm_file *file); | |
575155a9 | 1825 | |
6ef3d427 | 1826 | /* overlay */ |
3bd3c932 | 1827 | #ifdef CONFIG_DEBUG_FS |
6ef3d427 CW |
1828 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); |
1829 | extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error); | |
c4a1d9e4 CW |
1830 | |
1831 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); | |
1832 | extern void intel_display_print_error_state(struct seq_file *m, | |
1833 | struct drm_device *dev, | |
1834 | struct intel_display_error_state *error); | |
3bd3c932 | 1835 | #endif |
6ef3d427 | 1836 | |
b7287d80 BW |
1837 | /* On SNB platform, before reading ring registers forcewake bit |
1838 | * must be set to prevent GT core from power down and stale values being | |
1839 | * returned. | |
1840 | */ | |
fcca7926 BW |
1841 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); |
1842 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); | |
67a3744f | 1843 | int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); |
b7287d80 | 1844 | |
42c0526c BW |
1845 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); |
1846 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); | |
1847 | ||
5f75377d | 1848 | #define __i915_read(x, y) \ |
f7000883 | 1849 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); |
fcca7926 | 1850 | |
5f75377d KP |
1851 | __i915_read(8, b) |
1852 | __i915_read(16, w) | |
1853 | __i915_read(32, l) | |
1854 | __i915_read(64, q) | |
1855 | #undef __i915_read | |
1856 | ||
1857 | #define __i915_write(x, y) \ | |
f7000883 AK |
1858 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val); |
1859 | ||
5f75377d KP |
1860 | __i915_write(8, b) |
1861 | __i915_write(16, w) | |
1862 | __i915_write(32, l) | |
1863 | __i915_write(64, q) | |
1864 | #undef __i915_write | |
1865 | ||
1866 | #define I915_READ8(reg) i915_read8(dev_priv, (reg)) | |
1867 | #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) | |
1868 | ||
1869 | #define I915_READ16(reg) i915_read16(dev_priv, (reg)) | |
1870 | #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) | |
1871 | #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg)) | |
1872 | #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg)) | |
1873 | ||
1874 | #define I915_READ(reg) i915_read32(dev_priv, (reg)) | |
1875 | #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) | |
cae5852d ZN |
1876 | #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg)) |
1877 | #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg)) | |
5f75377d KP |
1878 | |
1879 | #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) | |
1880 | #define I915_READ64(reg) i915_read64(dev_priv, (reg)) | |
cae5852d ZN |
1881 | |
1882 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) | |
1883 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
1884 | ||
55bc60db VS |
1885 | /* "Broadcast RGB" property */ |
1886 | #define INTEL_BROADCAST_RGB_AUTO 0 | |
1887 | #define INTEL_BROADCAST_RGB_FULL 1 | |
1888 | #define INTEL_BROADCAST_RGB_LIMITED 2 | |
ba4f01a3 | 1889 | |
1da177e4 | 1890 | #endif |