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drm/i915: Implement IS_* macros using static tables
[linux-2.6-block.git] / drivers / gpu / drm / i915 / i915_drv.h
CommitLineData
1da177e4
LT		 1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
0d6aa60b 3/*
bc54fd1a 4 *
1da177e4
LT		 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
bc54fd1a
DA		 7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
0d6aa60b 28 */
1da177e4
LT		 29
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
585fb111 33#include "i915_reg.h"
79e53945 34#include "intel_bios.h"
0839ccb8 35#include <linux/io-mapping.h>
585fb111 36
1da177e4
LT		 37/* General customization:
38 */
39
40#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
41
42#define DRIVER_NAME "i915"
43#define DRIVER_DESC "Intel Graphics"
673a394b 44#define DRIVER_DATE "20080730"
1da177e4 45
317c35d1
JB		 46enum pipe {
47 PIPE_A = 0,
48 PIPE_B,
49};
50
80824003
JB		 51enum plane {
52 PLANE_A = 0,
53 PLANE_B,
54};
55
52440211
KP		 56#define I915_NUM_PIPE 2
57
1da177e4
LT		 58/* Interface history:
59 *
60 * 1.1: Original.
0d6aa60b
DA		 61 * 1.2: Add Power Management
62 * 1.3: Add vblank support
de227f5f 63 * 1.4: Fix cmdbuffer path, add heap destroy
702880f2 64 * 1.5: Add vblank pipe configuration
2228ed67
MCA		 65 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
66 * - Support vertical blank on secondary display pipe
1da177e4
LT		 67 */
68#define DRIVER_MAJOR 1
2228ed67 69#define DRIVER_MINOR 6
1da177e4
LT		 70#define DRIVER_PATCHLEVEL 0
71
673a394b
EA		 72#define WATCH_COHERENCY 0
73#define WATCH_BUF 0
74#define WATCH_EXEC 0
75#define WATCH_LRU 0
76#define WATCH_RELOC 0
77#define WATCH_INACTIVE 0
78#define WATCH_PWRITE 0
79
71acb5eb
DA		 80#define I915_GEM_PHYS_CURSOR_0 1
81#define I915_GEM_PHYS_CURSOR_1 2
82#define I915_GEM_PHYS_OVERLAY_REGS 3
83#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
84
85struct drm_i915_gem_phys_object {
86 int id;
87 struct page **page_list;
88 drm_dma_handle_t *handle;
89 struct drm_gem_object *cur_obj;
90};
91
1da177e4 92typedef struct _drm_i915_ring_buffer {
1da177e4
LT		 93 unsigned long Size;
94 u8 *virtual_start;
95 int head;
96 int tail;
97 int space;
98 drm_local_map_t map;
673a394b 99 struct drm_gem_object *ring_obj;
1da177e4
LT		 100} drm_i915_ring_buffer_t;
101
102struct mem_block {
103 struct mem_block *next;
104 struct mem_block *prev;
105 int start;
106 int size;
6c340eac 107 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
1da177e4
LT		 108};
109
0a3e67a4
JB		 110struct opregion_header;
111struct opregion_acpi;
112struct opregion_swsci;
113struct opregion_asle;
114
8ee1c3db
MG		 115struct intel_opregion {
116 struct opregion_header *header;
117 struct opregion_acpi *acpi;
118 struct opregion_swsci *swsci;
119 struct opregion_asle *asle;
120 int enabled;
121};
122
7c1c2871
DA		 123struct drm_i915_master_private {
124 drm_local_map_t *sarea;
125 struct _drm_i915_sarea *sarea_priv;
126};
de151cf6
JB		 127#define I915_FENCE_REG_NONE -1
128
129struct drm_i915_fence_reg {
130 struct drm_gem_object *obj;
131};
7c1c2871 132
9b9d172d 133struct sdvo_device_mapping {
134 u8 dvo_port;
135 u8 slave_addr;
136 u8 dvo_wiring;
137 u8 initialized;
138};
139
63eeaf38
JB		 140struct drm_i915_error_state {
141 u32 eir;
142 u32 pgtbl_er;
143 u32 pipeastat;
144 u32 pipebstat;
145 u32 ipeir;
146 u32 ipehr;
147 u32 instdone;
148 u32 acthd;
149 u32 instpm;
150 u32 instps;
151 u32 instdone1;
152 u32 seqno;
153 struct timeval time;
154};
155
e70236a8
JB		 156struct drm_i915_display_funcs {
157 void (*dpms)(struct drm_crtc *crtc, int mode);
158 bool (*fbc_enabled)(struct drm_crtc *crtc);
159 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
160 void (*disable_fbc)(struct drm_device *dev);
161 int (*get_display_clock_speed)(struct drm_device *dev);
162 int (*get_fifo_size)(struct drm_device *dev, int plane);
163 void (*update_wm)(struct drm_device *dev, int planea_clock,
164 int planeb_clock, int sr_hdisplay, int pixel_size);
165 /* clock updates for mode set */
166 /* cursor updates */
167 /* render clock increase/decrease */
168 /* display clock increase/decrease */
169 /* pll clock increase/decrease */
170 /* clock gating init */
171};
172
02e792fb
DV		 173struct intel_overlay;
174
cfdf1fa2
KH		 175struct intel_device_info {
176 u8 is_mobile : 1;
177 u8 is_i8xx : 1;
178 u8 is_i915g : 1;
179 u8 is_i9xx : 1;
180 u8 is_i945gm : 1;
181 u8 is_i965g : 1;
182 u8 is_i965gm : 1;
183 u8 is_g33 : 1;
184 u8 need_gfx_hws : 1;
185 u8 is_g4x : 1;
186 u8 is_pineview : 1;
187 u8 is_ironlake : 1;
188 u8 has_fbc : 1;
189 u8 has_rc6 : 1;
190 u8 has_pipe_cxsr : 1;
191 u8 has_hotplug : 1;
192};
193
1da177e4 194typedef struct drm_i915_private {
673a394b
EA		 195 struct drm_device *dev;
196
cfdf1fa2
KH		 197 const struct intel_device_info *info;
198
ac5c4e76
DA		 199 int has_gem;
200
3043c60c 201 void __iomem *regs;
1da177e4 202
ec2a4c3f 203 struct pci_dev *bridge_dev;
1da177e4
LT		 204 drm_i915_ring_buffer_t ring;
205
9c8da5eb 206 drm_dma_handle_t *status_page_dmah;
1da177e4 207 void *hw_status_page;
1da177e4 208 dma_addr_t dma_status_page;
0a3e67a4 209 uint32_t counter;
dc7a9319
WZ		 210 unsigned int status_gfx_addr;
211 drm_local_map_t hws_map;
673a394b 212 struct drm_gem_object *hws_obj;
97f5ab66 213 struct drm_gem_object *pwrctx;
1da177e4 214
d7658989
JB		 215 struct resource mch_res;
216
a6b54f3f 217 unsigned int cpp;
1da177e4
LT		 218 int back_offset;
219 int front_offset;
220 int current_page;
221 int page_flipping;
1da177e4
LT		 222
223 wait_queue_head_t irq_queue;
224 atomic_t irq_received;
ed4cb414
EA		 225 /** Protects user_irq_refcount and irq_mask_reg */
226 spinlock_t user_irq_lock;
227 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
228 int user_irq_refcount;
9d34e5db 229 u32 trace_irq_seqno;
ed4cb414
EA		 230 /** Cached value of IMR to avoid reads in updating the bitfield */
231 u32 irq_mask_reg;
7c463586 232 u32 pipestat[2];
f2b115e6 233 /** splitted irq regs for graphics and display engine on Ironlake,
036a4a7d
ZW		 234 irq_mask_reg is still used for display irq. */
235 u32 gt_irq_mask_reg;
236 u32 gt_irq_enable_reg;
237 u32 de_irq_enable_reg;
c650156a
ZW		 238 u32 pch_irq_mask_reg;
239 u32 pch_irq_enable_reg;
1da177e4 240
5ca58282
JB		 241 u32 hotplug_supported_mask;
242 struct work_struct hotplug_work;
243
1da177e4
LT		 244 int tex_lru_log_granularity;
245 int allow_batchbuffer;
246 struct mem_block *agp_heap;
0d6aa60b 247 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
702880f2 248 int vblank_pipe;
a6b54f3f 249
f65d9421
BG		 250 /* For hangcheck timer */
251#define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */
252 struct timer_list hangcheck_timer;
253 int hangcheck_count;
254 uint32_t last_acthd;
255
79e53945
JB		 256 bool cursor_needs_physical;
257
258 struct drm_mm vram;
259
80824003
JB		 260 unsigned long cfb_size;
261 unsigned long cfb_pitch;
262 int cfb_fence;
263 int cfb_plane;
264
79e53945
JB		 265 int irq_enabled;
266
8ee1c3db
MG		 267 struct intel_opregion opregion;
268
02e792fb
DV		 269 /* overlay */
270 struct intel_overlay *overlay;
271
79e53945
JB		 272 /* LVDS info */
273 int backlight_duty_cycle; /* restore backlight to this value */
274 bool panel_wants_dither;
275 struct drm_display_mode *panel_fixed_mode;
88631706
ML		 276 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
277 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
79e53945
JB		 278
279 /* Feature bits from the VBIOS */
95281e35
HE		 280 unsigned int int_tv_support:1;
281 unsigned int lvds_dither:1;
282 unsigned int lvds_vbt:1;
283 unsigned int int_crt_support:1;
43565a06 284 unsigned int lvds_use_ssc:1;
32f9d658 285 unsigned int edp_support:1;
43565a06 286 int lvds_ssc_freq;
79e53945 287
c1c7af60
JB		 288 struct notifier_block lid_notifier;
289
29874f44 290 int crt_ddc_bus; /* 0 = unknown, else GPIO to use for CRT DDC */
de151cf6
JB		 291 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
292 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
293 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
294
7662c8bd
SL		 295 unsigned int fsb_freq, mem_freq;
296
63eeaf38
JB		 297 spinlock_t error_lock;
298 struct drm_i915_error_state *first_error;
8a905236 299 struct work_struct error_work;
9c9fe1f8 300 struct workqueue_struct *wq;
63eeaf38 301
e70236a8
JB		 302 /* Display functions */
303 struct drm_i915_display_funcs display;
304
ba8bbcf6 305 /* Register state */
c9354c85 306 bool modeset_on_lid;
ba8bbcf6
JB		 307 u8 saveLBB;
308 u32 saveDSPACNTR;
309 u32 saveDSPBCNTR;
e948e994 310 u32 saveDSPARB;
881ee988 311 u32 saveRENDERSTANDBY;
97f5ab66 312 u32 savePWRCTXA;
461cba2d 313 u32 saveHWS;
ba8bbcf6
JB		 314 u32 savePIPEACONF;
315 u32 savePIPEBCONF;
316 u32 savePIPEASRC;
317 u32 savePIPEBSRC;
318 u32 saveFPA0;
319 u32 saveFPA1;
320 u32 saveDPLL_A;
321 u32 saveDPLL_A_MD;
322 u32 saveHTOTAL_A;
323 u32 saveHBLANK_A;
324 u32 saveHSYNC_A;
325 u32 saveVTOTAL_A;
326 u32 saveVBLANK_A;
327 u32 saveVSYNC_A;
328 u32 saveBCLRPAT_A;
5586c8bc 329 u32 saveTRANSACONF;
42048781
ZW		 330 u32 saveTRANS_HTOTAL_A;
331 u32 saveTRANS_HBLANK_A;
332 u32 saveTRANS_HSYNC_A;
333 u32 saveTRANS_VTOTAL_A;
334 u32 saveTRANS_VBLANK_A;
335 u32 saveTRANS_VSYNC_A;
0da3ea12 336 u32 savePIPEASTAT;
ba8bbcf6
JB		 337 u32 saveDSPASTRIDE;
338 u32 saveDSPASIZE;
339 u32 saveDSPAPOS;
585fb111 340 u32 saveDSPAADDR;
ba8bbcf6
JB		 341 u32 saveDSPASURF;
342 u32 saveDSPATILEOFF;
343 u32 savePFIT_PGM_RATIOS;
0eb96d6e 344 u32 saveBLC_HIST_CTL;
ba8bbcf6
JB		 345 u32 saveBLC_PWM_CTL;
346 u32 saveBLC_PWM_CTL2;
42048781
ZW		 347 u32 saveBLC_CPU_PWM_CTL;
348 u32 saveBLC_CPU_PWM_CTL2;
ba8bbcf6
JB		 349 u32 saveFPB0;
350 u32 saveFPB1;
351 u32 saveDPLL_B;
352 u32 saveDPLL_B_MD;
353 u32 saveHTOTAL_B;
354 u32 saveHBLANK_B;
355 u32 saveHSYNC_B;
356 u32 saveVTOTAL_B;
357 u32 saveVBLANK_B;
358 u32 saveVSYNC_B;
359 u32 saveBCLRPAT_B;
5586c8bc 360 u32 saveTRANSBCONF;
42048781
ZW		 361 u32 saveTRANS_HTOTAL_B;
362 u32 saveTRANS_HBLANK_B;
363 u32 saveTRANS_HSYNC_B;
364 u32 saveTRANS_VTOTAL_B;
365 u32 saveTRANS_VBLANK_B;
366 u32 saveTRANS_VSYNC_B;
0da3ea12 367 u32 savePIPEBSTAT;
ba8bbcf6
JB		 368 u32 saveDSPBSTRIDE;
369 u32 saveDSPBSIZE;
370 u32 saveDSPBPOS;
585fb111 371 u32 saveDSPBADDR;
ba8bbcf6
JB		 372 u32 saveDSPBSURF;
373 u32 saveDSPBTILEOFF;
585fb111
JB		 374 u32 saveVGA0;
375 u32 saveVGA1;
376 u32 saveVGA_PD;
ba8bbcf6
JB		 377 u32 saveVGACNTRL;
378 u32 saveADPA;
379 u32 saveLVDS;
585fb111
JB		 380 u32 savePP_ON_DELAYS;
381 u32 savePP_OFF_DELAYS;
ba8bbcf6
JB		 382 u32 saveDVOA;
383 u32 saveDVOB;
384 u32 saveDVOC;
385 u32 savePP_ON;
386 u32 savePP_OFF;
387 u32 savePP_CONTROL;
585fb111 388 u32 savePP_DIVISOR;
ba8bbcf6
JB		 389 u32 savePFIT_CONTROL;
390 u32 save_palette_a[256];
391 u32 save_palette_b[256];
06027f91 392 u32 saveDPFC_CB_BASE;
ba8bbcf6
JB		 393 u32 saveFBC_CFB_BASE;
394 u32 saveFBC_LL_BASE;
395 u32 saveFBC_CONTROL;
396 u32 saveFBC_CONTROL2;
0da3ea12
JB		 397 u32 saveIER;
398 u32 saveIIR;
399 u32 saveIMR;
42048781
ZW		 400 u32 saveDEIER;
401 u32 saveDEIMR;
402 u32 saveGTIER;
403 u32 saveGTIMR;
404 u32 saveFDI_RXA_IMR;
405 u32 saveFDI_RXB_IMR;
1f84e550 406 u32 saveCACHE_MODE_0;
1f84e550 407 u32 saveMI_ARB_STATE;
ba8bbcf6
JB		 408 u32 saveSWF0[16];
409 u32 saveSWF1[16];
410 u32 saveSWF2[3];
411 u8 saveMSR;
412 u8 saveSR[8];
123f794f 413 u8 saveGR[25];
ba8bbcf6 414 u8 saveAR_INDEX;
a59e122a 415 u8 saveAR[21];
ba8bbcf6 416 u8 saveDACMASK;
a59e122a 417 u8 saveCR[37];
79f11c19 418 uint64_t saveFENCE[16];
1fd1c624
EA		 419 u32 saveCURACNTR;
420 u32 saveCURAPOS;
421 u32 saveCURABASE;
422 u32 saveCURBCNTR;
423 u32 saveCURBPOS;
424 u32 saveCURBBASE;
425 u32 saveCURSIZE;
a4fc5ed6
KP		 426 u32 saveDP_B;
427 u32 saveDP_C;
428 u32 saveDP_D;
429 u32 savePIPEA_GMCH_DATA_M;
430 u32 savePIPEB_GMCH_DATA_M;
431 u32 savePIPEA_GMCH_DATA_N;
432 u32 savePIPEB_GMCH_DATA_N;
433 u32 savePIPEA_DP_LINK_M;
434 u32 savePIPEB_DP_LINK_M;
435 u32 savePIPEA_DP_LINK_N;
436 u32 savePIPEB_DP_LINK_N;
42048781
ZW		 437 u32 saveFDI_RXA_CTL;
438 u32 saveFDI_TXA_CTL;
439 u32 saveFDI_RXB_CTL;
440 u32 saveFDI_TXB_CTL;
441 u32 savePFA_CTL_1;
442 u32 savePFB_CTL_1;
443 u32 savePFA_WIN_SZ;
444 u32 savePFB_WIN_SZ;
445 u32 savePFA_WIN_POS;
446 u32 savePFB_WIN_POS;
5586c8bc
ZW		 447 u32 savePCH_DREF_CONTROL;
448 u32 saveDISP_ARB_CTL;
449 u32 savePIPEA_DATA_M1;
450 u32 savePIPEA_DATA_N1;
451 u32 savePIPEA_LINK_M1;
452 u32 savePIPEA_LINK_N1;
453 u32 savePIPEB_DATA_M1;
454 u32 savePIPEB_DATA_N1;
455 u32 savePIPEB_LINK_M1;
456 u32 savePIPEB_LINK_N1;
673a394b
EA		 457
458 struct {
459 struct drm_mm gtt_space;
460
0839ccb8 461 struct io_mapping *gtt_mapping;
ab657db1 462 int gtt_mtrr;
0839ccb8 463
31169714
CW		 464 /**
465 * Membership on list of all loaded devices, used to evict
466 * inactive buffers under memory pressure.
467 *
468 * Modifications should only be done whilst holding the
469 * shrink_list_lock spinlock.
470 */
471 struct list_head shrink_list;
472
673a394b
EA		 473 /**
474 * List of objects currently involved in rendering from the
475 * ringbuffer.
476 *
ce44b0ea
EA		 477 * Includes buffers having the contents of their GPU caches
478 * flushed, not necessarily primitives. last_rendering_seqno
479 * represents when the rendering involved will be completed.
480 *
673a394b
EA		 481 * A reference is held on the buffer while on this list.
482 */
5e118f41 483 spinlock_t active_list_lock;
673a394b
EA		 484 struct list_head active_list;
485
486 /**
487 * List of objects which are not in the ringbuffer but which
488 * still have a write_domain which needs to be flushed before
489 * unbinding.
490 *
ce44b0ea
EA		 491 * last_rendering_seqno is 0 while an object is in this list.
492 *
673a394b
EA		 493 * A reference is held on the buffer while on this list.
494 */
495 struct list_head flushing_list;
496
497 /**
498 * LRU list of objects which are not in the ringbuffer and
499 * are ready to unbind, but are still in the GTT.
500 *
ce44b0ea
EA		 501 * last_rendering_seqno is 0 while an object is in this list.
502 *
673a394b
EA		 503 * A reference is not held on the buffer while on this list,
504 * as merely being GTT-bound shouldn't prevent its being
505 * freed, and we'll pull it off the list in the free path.
506 */
507 struct list_head inactive_list;
508
a09ba7fa
EA		 509 /** LRU list of objects with fence regs on them. */
510 struct list_head fence_list;
511
673a394b
EA		 512 /**
513 * List of breadcrumbs associated with GPU requests currently
514 * outstanding.
515 */
516 struct list_head request_list;
517
518 /**
519 * We leave the user IRQ off as much as possible,
520 * but this means that requests will finish and never
521 * be retired once the system goes idle. Set a timer to
522 * fire periodically while the ring is running. When it
523 * fires, go retire requests.
524 */
525 struct delayed_work retire_work;
526
527 uint32_t next_gem_seqno;
528
529 /**
530 * Waiting sequence number, if any
531 */
532 uint32_t waiting_gem_seqno;
533
534 /**
535 * Last seq seen at irq time
536 */
537 uint32_t irq_gem_seqno;
538
539 /**
540 * Flag if the X Server, and thus DRM, is not currently in
541 * control of the device.
542 *
543 * This is set between LeaveVT and EnterVT. It needs to be
544 * replaced with a semaphore. It also needs to be
545 * transitioned away from for kernel modesetting.
546 */
547 int suspended;
548
549 /**
550 * Flag if the hardware appears to be wedged.
551 *
552 * This is set when attempts to idle the device timeout.
553 * It prevents command submission from occuring and makes
554 * every pending request fail
555 */
ba1234d1 556 atomic_t wedged;
673a394b
EA		 557
558 /** Bit 6 swizzling required for X tiling */
559 uint32_t bit_6_swizzle_x;
560 /** Bit 6 swizzling required for Y tiling */
561 uint32_t bit_6_swizzle_y;
71acb5eb
DA		 562
563 /* storage for physical objects */
564 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
673a394b 565 } mm;
9b9d172d 566 struct sdvo_device_mapping sdvo_mappings[2];
a3e17eb8
ZY		 567 /* indicate whether the LVDS_BORDER should be enabled or not */
568 unsigned int lvds_border_bits;
652c393a 569
6b95a207
KH		 570 struct drm_crtc *plane_to_crtc_mapping[2];
571 struct drm_crtc *pipe_to_crtc_mapping[2];
572 wait_queue_head_t pending_flip_queue;
573
652c393a
JB		 574 /* Reclocking support */
575 bool render_reclock_avail;
576 bool lvds_downclock_avail;
18f9ed12
ZY		 577 /* indicates the reduced downclock for LVDS*/
578 int lvds_downclock;
652c393a
JB		 579 struct work_struct idle_work;
580 struct timer_list idle_timer;
581 bool busy;
582 u16 orig_clock;
6363ee6f
ZY		 583 int child_dev_num;
584 struct child_device_config *child_dev;
a2565377 585 struct drm_connector *int_lvds_connector;
1da177e4
LT		 586} drm_i915_private_t;
587
673a394b
EA		 588/** driver private structure attached to each drm_gem_object */
589struct drm_i915_gem_object {
590 struct drm_gem_object *obj;
591
592 /** Current space allocated to this object in the GTT, if any. */
593 struct drm_mm_node *gtt_space;
594
595 /** This object's place on the active/flushing/inactive lists */
596 struct list_head list;
597
a09ba7fa
EA		 598 /** This object's place on the fenced object LRU */
599 struct list_head fence_list;
600
673a394b
EA		 601 /**
602 * This is set if the object is on the active or flushing lists
603 * (has pending rendering), and is not set if it's on inactive (ready
604 * to be unbound).
605 */
606 int active;
607
608 /**
609 * This is set if the object has been written to since last bound
610 * to the GTT
611 */
612 int dirty;
613
614 /** AGP memory structure for our GTT binding. */
615 DRM_AGP_MEM *agp_mem;
616
856fa198
EA		 617 struct page **pages;
618 int pages_refcount;
673a394b
EA		 619
620 /**
621 * Current offset of the object in GTT space.
622 *
623 * This is the same as gtt_space->start
624 */
625 uint32_t gtt_offset;
e67b8ce1 626
de151cf6
JB		 627 /**
628 * Fake offset for use by mmap(2)
629 */
630 uint64_t mmap_offset;
631
632 /**
633 * Fence register bits (if any) for this object. Will be set
634 * as needed when mapped into the GTT.
635 * Protected by dev->struct_mutex.
636 */
637 int fence_reg;
673a394b 638
673a394b
EA		 639 /** How many users have pinned this object in GTT space */
640 int pin_count;
641
642 /** Breadcrumb of last rendering to the buffer. */
643 uint32_t last_rendering_seqno;
644
645 /** Current tiling mode for the object. */
646 uint32_t tiling_mode;
de151cf6 647 uint32_t stride;
673a394b 648
280b713b
EA		 649 /** Record of address bit 17 of each page at last unbind. */
650 long *bit_17;
651
ba1eb1d8
KP		 652 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
653 uint32_t agp_type;
654
673a394b 655 /**
e47c68e9
EA		 656 * If present, while GEM_DOMAIN_CPU is in the read domain this array
657 * flags which individual pages are valid.
673a394b
EA		 658 */
659 uint8_t *page_cpu_valid;
79e53945
JB		 660
661 /** User space pin count and filp owning the pin */
662 uint32_t user_pin_count;
663 struct drm_file *pin_filp;
71acb5eb
DA		 664
665 /** for phy allocated objects */
666 struct drm_i915_gem_phys_object *phys_obj;
b70d11da
KH		 667
668 /**
669 * Used for checking the object doesn't appear more than once
670 * in an execbuffer object list.
671 */
672 int in_execbuffer;
3ef94daa
CW		 673
674 /**
675 * Advice: are the backing pages purgeable?
676 */
677 int madv;
6b95a207
KH		 678
679 /**
680 * Number of crtcs where this object is currently the fb, but
681 * will be page flipped away on the next vblank. When it
682 * reaches 0, dev_priv->pending_flip_queue will be woken up.
683 */
684 atomic_t pending_flip;
673a394b
EA		 685};
686
687/**
688 * Request queue structure.
689 *
690 * The request queue allows us to note sequence numbers that have been emitted
691 * and may be associated with active buffers to be retired.
692 *
693 * By keeping this list, we can avoid having to do questionable
694 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
695 * an emission time with seqnos for tracking how far ahead of the GPU we are.
696 */
697struct drm_i915_gem_request {
698 /** GEM sequence number associated with this request. */
699 uint32_t seqno;
700
701 /** Time at which this request was emitted, in jiffies. */
702 unsigned long emitted_jiffies;
703
b962442e 704 /** global list entry for this request */
673a394b 705 struct list_head list;
b962442e
EA		 706
707 /** file_priv list entry for this request */
708 struct list_head client_list;
673a394b
EA		 709};
710
711struct drm_i915_file_private {
712 struct {
b962442e 713 struct list_head request_list;
673a394b
EA		 714 } mm;
715};
716
79e53945
JB		 717enum intel_chip_family {
718 CHIP_I8XX = 0x01,
719 CHIP_I9XX = 0x02,
720 CHIP_I915 = 0x04,
721 CHIP_I965 = 0x08,
722};
723
c153f45f 724extern struct drm_ioctl_desc i915_ioctls[];
b3a83639 725extern int i915_max_ioctl;
79e53945 726extern unsigned int i915_fbpercrtc;
652c393a 727extern unsigned int i915_powersave;
b3a83639 728
1341d655
BG		 729extern void i915_save_display(struct drm_device *dev);
730extern void i915_restore_display(struct drm_device *dev);
7c1c2871
DA		 731extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
732extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
733
1da177e4 734 /* i915_dma.c */
84b1fd10 735extern void i915_kernel_lost_context(struct drm_device * dev);
22eae947 736extern int i915_driver_load(struct drm_device *, unsigned long flags);
ba8bbcf6 737extern int i915_driver_unload(struct drm_device *);
673a394b 738extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
84b1fd10 739extern void i915_driver_lastclose(struct drm_device * dev);
6c340eac
EA		 740extern void i915_driver_preclose(struct drm_device *dev,
741 struct drm_file *file_priv);
673a394b
EA		 742extern void i915_driver_postclose(struct drm_device *dev,
743 struct drm_file *file_priv);
84b1fd10 744extern int i915_driver_device_is_agp(struct drm_device * dev);
0d6aa60b
DA		 745extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
746 unsigned long arg);
673a394b 747extern int i915_emit_box(struct drm_device *dev,
201361a5 748 struct drm_clip_rect *boxes,
673a394b 749 int i, int DR1, int DR4);
11ed50ec 750extern int i965_reset(struct drm_device *dev, u8 flags);
af6061af 751
1da177e4 752/* i915_irq.c */
f65d9421 753void i915_hangcheck_elapsed(unsigned long data);
c153f45f
EA		 754extern int i915_irq_emit(struct drm_device *dev, void *data,
755 struct drm_file *file_priv);
756extern int i915_irq_wait(struct drm_device *dev, void *data,
757 struct drm_file *file_priv);
673a394b 758void i915_user_irq_get(struct drm_device *dev);
9d34e5db 759void i915_trace_irq_get(struct drm_device *dev, u32 seqno);
673a394b 760void i915_user_irq_put(struct drm_device *dev);
79e53945 761extern void i915_enable_interrupt (struct drm_device *dev);
1da177e4
LT		 762
763extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
84b1fd10 764extern void i915_driver_irq_preinstall(struct drm_device * dev);
0a3e67a4 765extern int i915_driver_irq_postinstall(struct drm_device *dev);
84b1fd10 766extern void i915_driver_irq_uninstall(struct drm_device * dev);
c153f45f
EA		 767extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
768 struct drm_file *file_priv);
769extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
770 struct drm_file *file_priv);
0a3e67a4
JB		 771extern int i915_enable_vblank(struct drm_device *dev, int crtc);
772extern void i915_disable_vblank(struct drm_device *dev, int crtc);
773extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
9880b7a5 774extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
c153f45f
EA		 775extern int i915_vblank_swap(struct drm_device *dev, void *data,
776 struct drm_file *file_priv);
8ee1c3db 777extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
1da177e4 778
7c463586
KP		 779void
780i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
781
782void
783i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
784
01c66889
ZY		 785void intel_enable_asle (struct drm_device *dev);
786
7c463586 787
1da177e4 788/* i915_mem.c */
c153f45f
EA		 789extern int i915_mem_alloc(struct drm_device *dev, void *data,
790 struct drm_file *file_priv);
791extern int i915_mem_free(struct drm_device *dev, void *data,
792 struct drm_file *file_priv);
793extern int i915_mem_init_heap(struct drm_device *dev, void *data,
794 struct drm_file *file_priv);
795extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
796 struct drm_file *file_priv);
1da177e4 797extern void i915_mem_takedown(struct mem_block **heap);
84b1fd10 798extern void i915_mem_release(struct drm_device * dev,
6c340eac 799 struct drm_file *file_priv, struct mem_block *heap);
673a394b
EA		 800/* i915_gem.c */
801int i915_gem_init_ioctl(struct drm_device *dev, void *data,
802 struct drm_file *file_priv);
803int i915_gem_create_ioctl(struct drm_device *dev, void *data,
804 struct drm_file *file_priv);
805int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
806 struct drm_file *file_priv);
807int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
808 struct drm_file *file_priv);
809int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
810 struct drm_file *file_priv);
de151cf6
JB		 811int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
812 struct drm_file *file_priv);
673a394b
EA		 813int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
814 struct drm_file *file_priv);
815int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
816 struct drm_file *file_priv);
817int i915_gem_execbuffer(struct drm_device *dev, void *data,
818 struct drm_file *file_priv);
819int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
820 struct drm_file *file_priv);
821int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
822 struct drm_file *file_priv);
823int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
824 struct drm_file *file_priv);
825int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
826 struct drm_file *file_priv);
3ef94daa
CW		 827int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
828 struct drm_file *file_priv);
673a394b
EA		 829int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
830 struct drm_file *file_priv);
831int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
832 struct drm_file *file_priv);
833int i915_gem_set_tiling(struct drm_device *dev, void *data,
834 struct drm_file *file_priv);
835int i915_gem_get_tiling(struct drm_device *dev, void *data,
836 struct drm_file *file_priv);
5a125c3c
EA		 837int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
838 struct drm_file *file_priv);
673a394b 839void i915_gem_load(struct drm_device *dev);
673a394b
EA		 840int i915_gem_init_object(struct drm_gem_object *obj);
841void i915_gem_free_object(struct drm_gem_object *obj);
842int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
843void i915_gem_object_unpin(struct drm_gem_object *obj);
0f973f27 844int i915_gem_object_unbind(struct drm_gem_object *obj);
d05ca301 845void i915_gem_release_mmap(struct drm_gem_object *obj);
673a394b
EA		 846void i915_gem_lastclose(struct drm_device *dev);
847uint32_t i915_get_gem_seqno(struct drm_device *dev);
22be1724 848bool i915_seqno_passed(uint32_t seq1, uint32_t seq2);
8c4b8c3f 849int i915_gem_object_get_fence_reg(struct drm_gem_object *obj);
52dc7d32 850int i915_gem_object_put_fence_reg(struct drm_gem_object *obj);
673a394b
EA		 851void i915_gem_retire_requests(struct drm_device *dev);
852void i915_gem_retire_work_handler(struct work_struct *work);
853void i915_gem_clflush_object(struct drm_gem_object *obj);
79e53945
JB		 854int i915_gem_object_set_domain(struct drm_gem_object *obj,
855 uint32_t read_domains,
856 uint32_t write_domain);
857int i915_gem_init_ringbuffer(struct drm_device *dev);
858void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
859int i915_gem_do_init(struct drm_device *dev, unsigned long start,
860 unsigned long end);
5669fcac 861int i915_gem_idle(struct drm_device *dev);
5a5a0c64
DV		 862uint32_t i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
863 uint32_t flush_domains);
864int i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible);
de151cf6 865int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
79e53945
JB		 866int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
867 int write);
71acb5eb
DA		 868int i915_gem_attach_phys_object(struct drm_device *dev,
869 struct drm_gem_object *obj, int id);
870void i915_gem_detach_phys_object(struct drm_device *dev,
871 struct drm_gem_object *obj);
872void i915_gem_free_all_phys_object(struct drm_device *dev);
6911a9b8
BG		 873int i915_gem_object_get_pages(struct drm_gem_object *obj);
874void i915_gem_object_put_pages(struct drm_gem_object *obj);
1fd1c624 875void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
6b95a207 876void i915_gem_object_flush_write_domain(struct drm_gem_object *obj);
673a394b 877
31169714
CW		 878void i915_gem_shrinker_init(void);
879void i915_gem_shrinker_exit(void);
880
673a394b
EA		 881/* i915_gem_tiling.c */
882void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
280b713b
EA		 883void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
884void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
673a394b
EA		 885
886/* i915_gem_debug.c */
887void i915_gem_dump_object(struct drm_gem_object *obj, int len,
888 const char *where, uint32_t mark);
889#if WATCH_INACTIVE
890void i915_verify_inactive(struct drm_device *dev, char *file, int line);
891#else
892#define i915_verify_inactive(dev, file, line)
893#endif
894void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
895void i915_gem_dump_object(struct drm_gem_object *obj, int len,
896 const char *where, uint32_t mark);
897void i915_dump_lru(struct drm_device *dev, const char *where);
1da177e4 898
2017263e 899/* i915_debugfs.c */
27c202ad
BG		 900int i915_debugfs_init(struct drm_minor *minor);
901void i915_debugfs_cleanup(struct drm_minor *minor);
2017263e 902
317c35d1
JB		 903/* i915_suspend.c */
904extern int i915_save_state(struct drm_device *dev);
905extern int i915_restore_state(struct drm_device *dev);
0a3e67a4
JB		 906
907/* i915_suspend.c */
908extern int i915_save_state(struct drm_device *dev);
909extern int i915_restore_state(struct drm_device *dev);
317c35d1 910
65e082c9 911#ifdef CONFIG_ACPI
8ee1c3db 912/* i915_opregion.c */
74a365b3 913extern int intel_opregion_init(struct drm_device *dev, int resume);
3b1c1c11 914extern void intel_opregion_free(struct drm_device *dev, int suspend);
8ee1c3db 915extern void opregion_asle_intr(struct drm_device *dev);
01c66889 916extern void ironlake_opregion_gse_intr(struct drm_device *dev);
8ee1c3db 917extern void opregion_enable_asle(struct drm_device *dev);
65e082c9 918#else
03ae61dd 919static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; }
3b1c1c11 920static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; }
65e082c9 921static inline void opregion_asle_intr(struct drm_device *dev) { return; }
01c66889 922static inline void ironlake_opregion_gse_intr(struct drm_device *dev) { return; }
65e082c9
LB		 923static inline void opregion_enable_asle(struct drm_device *dev) { return; }
924#endif
8ee1c3db 925
79e53945
JB		 926/* modesetting */
927extern void intel_modeset_init(struct drm_device *dev);
928extern void intel_modeset_cleanup(struct drm_device *dev);
28d52043 929extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
80824003 930extern void i8xx_disable_fbc(struct drm_device *dev);
74dff282 931extern void g4x_disable_fbc(struct drm_device *dev);
79e53945 932
546b0974
EA		 933/**
934 * Lock test for when it's just for synchronization of ring access.
935 *
936 * In that case, we don't need to do it when GEM is initialized as nobody else
937 * has access to the ring.
938 */
939#define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
940 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
941 LOCK_TEST_WITH_RETURN(dev, file_priv); \
942} while (0)
943
3043c60c
EA		 944#define I915_READ(reg) readl(dev_priv->regs + (reg))
945#define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
946#define I915_READ16(reg) readw(dev_priv->regs + (reg))
947#define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
948#define I915_READ8(reg) readb(dev_priv->regs + (reg))
949#define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
de151cf6 950#define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
049ef7e4 951#define I915_READ64(reg) readq(dev_priv->regs + (reg))
7d57382e 952#define POSTING_READ(reg) (void)I915_READ(reg)
1da177e4
LT		 953
954#define I915_VERBOSE 0
955
0ef82af7
CW		 956#define RING_LOCALS volatile unsigned int *ring_virt__;
957
958#define BEGIN_LP_RING(n) do { \
959 int bytes__ = 4*(n); \
960 if (I915_VERBOSE) DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
961 /* a wrap must occur between instructions so pad beforehand */ \
962 if (unlikely (dev_priv->ring.tail + bytes__ > dev_priv->ring.Size)) \
963 i915_wrap_ring(dev); \
964 if (unlikely (dev_priv->ring.space < bytes__)) \
965 i915_wait_ring(dev, bytes__, __func__); \
966 ring_virt__ = (unsigned int *) \
967 (dev_priv->ring.virtual_start + dev_priv->ring.tail); \
968 dev_priv->ring.tail += bytes__; \
969 dev_priv->ring.tail &= dev_priv->ring.Size - 1; \
970 dev_priv->ring.space -= bytes__; \
1da177e4
LT		 971} while (0)
972
0ef82af7 973#define OUT_RING(n) do { \
1da177e4 974 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
0ef82af7 975 *ring_virt__++ = (n); \
1da177e4
LT		 976} while (0)
977
978#define ADVANCE_LP_RING() do { \
0ef82af7
CW		 979 if (I915_VERBOSE) \
980 DRM_DEBUG("ADVANCE_LP_RING %x\n", dev_priv->ring.tail); \
981 I915_WRITE(PRB0_TAIL, dev_priv->ring.tail); \
1da177e4
LT		 982} while(0)
983
ba8bbcf6 984/**
585fb111
JB		 985 * Reads a dword out of the status page, which is written to from the command
986 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
987 * MI_STORE_DATA_IMM.
ba8bbcf6 988 *
585fb111 989 * The following dwords have a reserved meaning:
0cdad7e8
KP		 990 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
991 * 0x04: ring 0 head pointer
992 * 0x05: ring 1 head pointer (915-class)
993 * 0x06: ring 2 head pointer (915-class)
994 * 0x10-0x1b: Context status DWords (GM45)
995 * 0x1f: Last written status offset. (GM45)
ba8bbcf6 996 *
0cdad7e8 997 * The area from dword 0x20 to 0x3ff is available for driver usage.
ba8bbcf6 998 */
585fb111 999#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
0baf823a 1000#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
0cdad7e8 1001#define I915_GEM_HWS_INDEX 0x20
0baf823a 1002#define I915_BREADCRUMB_INDEX 0x21
ba8bbcf6 1003
0ef82af7 1004extern int i915_wrap_ring(struct drm_device * dev);
585fb111 1005extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
ba8bbcf6 1006
cfdf1fa2
KH		 1007#define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1008
1009#define IS_I830(dev) ((dev)->pci_device == 0x3577)
1010#define IS_845G(dev) ((dev)->pci_device == 0x2562)
1011#define IS_I85X(dev) ((dev)->pci_device == 0x3582)
1012#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1013#define IS_I8XX(dev) (INTEL_INFO(dev)->is_i8xx)
1014#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1015#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1016#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1017#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1018#define IS_I965G(dev) (INTEL_INFO(dev)->is_i965g)
1019#define IS_I965GM(dev) (INTEL_INFO(dev)->is_i965gm)
1020#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1021#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1022#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1023#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1024#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1025#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
f2b115e6
AJ		 1026#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1027#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
cfdf1fa2
KH		 1028#define IS_IRONLAKE(dev) (INTEL_INFO(dev)->is_ironlake)
1029#define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx)
1030#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
ba8bbcf6 1031
cfdf1fa2 1032#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
ba8bbcf6 1033
0f973f27
JB		 1034/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1035 * rows, which changed the alignment requirements and fence programming.
1036 */
1037#define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
1038 IS_I915GM(dev)))
f2b115e6
AJ		 1039#define SUPPORTS_DIGITAL_OUTPUTS(dev) (IS_I9XX(dev) && !IS_PINEVIEW(dev))
1040#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1041#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1042#define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
103a196f 1043#define SUPPORTS_TV(dev) (IS_I9XX(dev) && IS_MOBILE(dev) && \
f2b115e6 1044 !IS_IRONLAKE(dev) && !IS_PINEVIEW(dev))
cfdf1fa2 1045#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
7662c8bd 1046/* dsparb controlled by hw only */
f2b115e6 1047#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
b39d50e5 1048
f2b115e6 1049#define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev))
cfdf1fa2
KH		 1050#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1051#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1052#define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
652c393a 1053
ba8bbcf6 1054#define PRIMARY_RINGBUFFER_SIZE (128*1024)
0d6aa60b 1055
1da177e4 1056#endif
Linux 6.x block layer and io_uring tree(s)