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drm: GEM mmap support
[linux-2.6-block.git] / drivers / gpu / drm / i915 / i915_drv.h
CommitLineData
1da177e4
LT		 1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
0d6aa60b 3/*
bc54fd1a 4 *
1da177e4
LT		 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
bc54fd1a
DA		 7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
0d6aa60b 28 */
1da177e4
LT		 29
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
585fb111 33#include "i915_reg.h"
0839ccb8 34#include <linux/io-mapping.h>
585fb111 35
1da177e4
LT		 36/* General customization:
37 */
38
39#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
40
41#define DRIVER_NAME "i915"
42#define DRIVER_DESC "Intel Graphics"
673a394b 43#define DRIVER_DATE "20080730"
1da177e4 44
317c35d1
JB		 45enum pipe {
46 PIPE_A = 0,
47 PIPE_B,
48};
49
52440211
KP		 50#define I915_NUM_PIPE 2
51
1da177e4
LT		 52/* Interface history:
53 *
54 * 1.1: Original.
0d6aa60b
DA		 55 * 1.2: Add Power Management
56 * 1.3: Add vblank support
de227f5f 57 * 1.4: Fix cmdbuffer path, add heap destroy
702880f2 58 * 1.5: Add vblank pipe configuration
2228ed67
MCA		 59 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
60 * - Support vertical blank on secondary display pipe
1da177e4
LT		 61 */
62#define DRIVER_MAJOR 1
2228ed67 63#define DRIVER_MINOR 6
1da177e4
LT		 64#define DRIVER_PATCHLEVEL 0
65
673a394b
EA		 66#define WATCH_COHERENCY 0
67#define WATCH_BUF 0
68#define WATCH_EXEC 0
69#define WATCH_LRU 0
70#define WATCH_RELOC 0
71#define WATCH_INACTIVE 0
72#define WATCH_PWRITE 0
73
1da177e4
LT		 74typedef struct _drm_i915_ring_buffer {
75 int tail_mask;
1da177e4
LT		 76 unsigned long Size;
77 u8 *virtual_start;
78 int head;
79 int tail;
80 int space;
81 drm_local_map_t map;
673a394b 82 struct drm_gem_object *ring_obj;
1da177e4
LT		 83} drm_i915_ring_buffer_t;
84
85struct mem_block {
86 struct mem_block *next;
87 struct mem_block *prev;
88 int start;
89 int size;
6c340eac 90 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
1da177e4
LT		 91};
92
0a3e67a4
JB		 93struct opregion_header;
94struct opregion_acpi;
95struct opregion_swsci;
96struct opregion_asle;
97
8ee1c3db
MG		 98struct intel_opregion {
99 struct opregion_header *header;
100 struct opregion_acpi *acpi;
101 struct opregion_swsci *swsci;
102 struct opregion_asle *asle;
103 int enabled;
104};
105
7c1c2871
DA		 106struct drm_i915_master_private {
107 drm_local_map_t *sarea;
108 struct _drm_i915_sarea *sarea_priv;
109};
110
1da177e4 111typedef struct drm_i915_private {
673a394b
EA		 112 struct drm_device *dev;
113
ac5c4e76
DA		 114 int has_gem;
115
3043c60c 116 void __iomem *regs;
1da177e4 117
1da177e4
LT		 118 drm_i915_ring_buffer_t ring;
119
9c8da5eb 120 drm_dma_handle_t *status_page_dmah;
1da177e4 121 void *hw_status_page;
1da177e4 122 dma_addr_t dma_status_page;
0a3e67a4 123 uint32_t counter;
dc7a9319
WZ		 124 unsigned int status_gfx_addr;
125 drm_local_map_t hws_map;
673a394b 126 struct drm_gem_object *hws_obj;
1da177e4 127
a6b54f3f 128 unsigned int cpp;
1da177e4
LT		 129 int back_offset;
130 int front_offset;
131 int current_page;
132 int page_flipping;
1da177e4
LT		 133
134 wait_queue_head_t irq_queue;
135 atomic_t irq_received;
ed4cb414
EA		 136 /** Protects user_irq_refcount and irq_mask_reg */
137 spinlock_t user_irq_lock;
138 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
139 int user_irq_refcount;
140 /** Cached value of IMR to avoid reads in updating the bitfield */
141 u32 irq_mask_reg;
7c463586 142 u32 pipestat[2];
1da177e4
LT		 143
144 int tex_lru_log_granularity;
145 int allow_batchbuffer;
146 struct mem_block *agp_heap;
0d6aa60b 147 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
702880f2 148 int vblank_pipe;
a6b54f3f 149
8ee1c3db
MG		 150 struct intel_opregion opregion;
151
ba8bbcf6
JB		 152 /* Register state */
153 u8 saveLBB;
154 u32 saveDSPACNTR;
155 u32 saveDSPBCNTR;
e948e994 156 u32 saveDSPARB;
881ee988 157 u32 saveRENDERSTANDBY;
461cba2d 158 u32 saveHWS;
ba8bbcf6
JB		 159 u32 savePIPEACONF;
160 u32 savePIPEBCONF;
161 u32 savePIPEASRC;
162 u32 savePIPEBSRC;
163 u32 saveFPA0;
164 u32 saveFPA1;
165 u32 saveDPLL_A;
166 u32 saveDPLL_A_MD;
167 u32 saveHTOTAL_A;
168 u32 saveHBLANK_A;
169 u32 saveHSYNC_A;
170 u32 saveVTOTAL_A;
171 u32 saveVBLANK_A;
172 u32 saveVSYNC_A;
173 u32 saveBCLRPAT_A;
0da3ea12 174 u32 savePIPEASTAT;
ba8bbcf6
JB		 175 u32 saveDSPASTRIDE;
176 u32 saveDSPASIZE;
177 u32 saveDSPAPOS;
585fb111 178 u32 saveDSPAADDR;
ba8bbcf6
JB		 179 u32 saveDSPASURF;
180 u32 saveDSPATILEOFF;
181 u32 savePFIT_PGM_RATIOS;
182 u32 saveBLC_PWM_CTL;
183 u32 saveBLC_PWM_CTL2;
184 u32 saveFPB0;
185 u32 saveFPB1;
186 u32 saveDPLL_B;
187 u32 saveDPLL_B_MD;
188 u32 saveHTOTAL_B;
189 u32 saveHBLANK_B;
190 u32 saveHSYNC_B;
191 u32 saveVTOTAL_B;
192 u32 saveVBLANK_B;
193 u32 saveVSYNC_B;
194 u32 saveBCLRPAT_B;
0da3ea12 195 u32 savePIPEBSTAT;
ba8bbcf6
JB		 196 u32 saveDSPBSTRIDE;
197 u32 saveDSPBSIZE;
198 u32 saveDSPBPOS;
585fb111 199 u32 saveDSPBADDR;
ba8bbcf6
JB		 200 u32 saveDSPBSURF;
201 u32 saveDSPBTILEOFF;
585fb111
JB		 202 u32 saveVGA0;
203 u32 saveVGA1;
204 u32 saveVGA_PD;
ba8bbcf6
JB		 205 u32 saveVGACNTRL;
206 u32 saveADPA;
207 u32 saveLVDS;
585fb111
JB		 208 u32 savePP_ON_DELAYS;
209 u32 savePP_OFF_DELAYS;
ba8bbcf6
JB		 210 u32 saveDVOA;
211 u32 saveDVOB;
212 u32 saveDVOC;
213 u32 savePP_ON;
214 u32 savePP_OFF;
215 u32 savePP_CONTROL;
585fb111 216 u32 savePP_DIVISOR;
ba8bbcf6
JB		 217 u32 savePFIT_CONTROL;
218 u32 save_palette_a[256];
219 u32 save_palette_b[256];
220 u32 saveFBC_CFB_BASE;
221 u32 saveFBC_LL_BASE;
222 u32 saveFBC_CONTROL;
223 u32 saveFBC_CONTROL2;
0da3ea12
JB		 224 u32 saveIER;
225 u32 saveIIR;
226 u32 saveIMR;
1f84e550 227 u32 saveCACHE_MODE_0;
e948e994 228 u32 saveD_STATE;
585fb111 229 u32 saveCG_2D_DIS;
1f84e550 230 u32 saveMI_ARB_STATE;
ba8bbcf6
JB		 231 u32 saveSWF0[16];
232 u32 saveSWF1[16];
233 u32 saveSWF2[3];
234 u8 saveMSR;
235 u8 saveSR[8];
123f794f 236 u8 saveGR[25];
ba8bbcf6 237 u8 saveAR_INDEX;
a59e122a 238 u8 saveAR[21];
ba8bbcf6
JB		 239 u8 saveDACMASK;
240 u8 saveDACDATA[256*3]; /* 256 3-byte colors */
a59e122a 241 u8 saveCR[37];
673a394b
EA		 242
243 struct {
244 struct drm_mm gtt_space;
245
0839ccb8
KP		 246 struct io_mapping *gtt_mapping;
247
673a394b
EA		 248 /**
249 * List of objects currently involved in rendering from the
250 * ringbuffer.
251 *
ce44b0ea
EA		 252 * Includes buffers having the contents of their GPU caches
253 * flushed, not necessarily primitives. last_rendering_seqno
254 * represents when the rendering involved will be completed.
255 *
673a394b
EA		 256 * A reference is held on the buffer while on this list.
257 */
258 struct list_head active_list;
259
260 /**
261 * List of objects which are not in the ringbuffer but which
262 * still have a write_domain which needs to be flushed before
263 * unbinding.
264 *
ce44b0ea
EA		 265 * last_rendering_seqno is 0 while an object is in this list.
266 *
673a394b
EA		 267 * A reference is held on the buffer while on this list.
268 */
269 struct list_head flushing_list;
270
271 /**
272 * LRU list of objects which are not in the ringbuffer and
273 * are ready to unbind, but are still in the GTT.
274 *
ce44b0ea
EA		 275 * last_rendering_seqno is 0 while an object is in this list.
276 *
673a394b
EA		 277 * A reference is not held on the buffer while on this list,
278 * as merely being GTT-bound shouldn't prevent its being
279 * freed, and we'll pull it off the list in the free path.
280 */
281 struct list_head inactive_list;
282
283 /**
284 * List of breadcrumbs associated with GPU requests currently
285 * outstanding.
286 */
287 struct list_head request_list;
288
289 /**
290 * We leave the user IRQ off as much as possible,
291 * but this means that requests will finish and never
292 * be retired once the system goes idle. Set a timer to
293 * fire periodically while the ring is running. When it
294 * fires, go retire requests.
295 */
296 struct delayed_work retire_work;
297
298 uint32_t next_gem_seqno;
299
300 /**
301 * Waiting sequence number, if any
302 */
303 uint32_t waiting_gem_seqno;
304
305 /**
306 * Last seq seen at irq time
307 */
308 uint32_t irq_gem_seqno;
309
310 /**
311 * Flag if the X Server, and thus DRM, is not currently in
312 * control of the device.
313 *
314 * This is set between LeaveVT and EnterVT. It needs to be
315 * replaced with a semaphore. It also needs to be
316 * transitioned away from for kernel modesetting.
317 */
318 int suspended;
319
320 /**
321 * Flag if the hardware appears to be wedged.
322 *
323 * This is set when attempts to idle the device timeout.
324 * It prevents command submission from occuring and makes
325 * every pending request fail
326 */
327 int wedged;
328
329 /** Bit 6 swizzling required for X tiling */
330 uint32_t bit_6_swizzle_x;
331 /** Bit 6 swizzling required for Y tiling */
332 uint32_t bit_6_swizzle_y;
333 } mm;
1da177e4
LT		 334} drm_i915_private_t;
335
673a394b
EA		 336/** driver private structure attached to each drm_gem_object */
337struct drm_i915_gem_object {
338 struct drm_gem_object *obj;
339
340 /** Current space allocated to this object in the GTT, if any. */
341 struct drm_mm_node *gtt_space;
342
343 /** This object's place on the active/flushing/inactive lists */
344 struct list_head list;
345
346 /**
347 * This is set if the object is on the active or flushing lists
348 * (has pending rendering), and is not set if it's on inactive (ready
349 * to be unbound).
350 */
351 int active;
352
353 /**
354 * This is set if the object has been written to since last bound
355 * to the GTT
356 */
357 int dirty;
358
359 /** AGP memory structure for our GTT binding. */
360 DRM_AGP_MEM *agp_mem;
361
362 struct page **page_list;
363
364 /**
365 * Current offset of the object in GTT space.
366 *
367 * This is the same as gtt_space->start
368 */
369 uint32_t gtt_offset;
370
371 /** Boolean whether this object has a valid gtt offset. */
372 int gtt_bound;
373
374 /** How many users have pinned this object in GTT space */
375 int pin_count;
376
377 /** Breadcrumb of last rendering to the buffer. */
378 uint32_t last_rendering_seqno;
379
380 /** Current tiling mode for the object. */
381 uint32_t tiling_mode;
382
ba1eb1d8
KP		 383 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
384 uint32_t agp_type;
385
673a394b 386 /**
e47c68e9
EA		 387 * If present, while GEM_DOMAIN_CPU is in the read domain this array
388 * flags which individual pages are valid.
673a394b
EA		 389 */
390 uint8_t *page_cpu_valid;
391};
392
393/**
394 * Request queue structure.
395 *
396 * The request queue allows us to note sequence numbers that have been emitted
397 * and may be associated with active buffers to be retired.
398 *
399 * By keeping this list, we can avoid having to do questionable
400 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
401 * an emission time with seqnos for tracking how far ahead of the GPU we are.
402 */
403struct drm_i915_gem_request {
404 /** GEM sequence number associated with this request. */
405 uint32_t seqno;
406
407 /** Time at which this request was emitted, in jiffies. */
408 unsigned long emitted_jiffies;
409
673a394b
EA		 410 struct list_head list;
411};
412
413struct drm_i915_file_private {
414 struct {
415 uint32_t last_gem_seqno;
416 uint32_t last_gem_throttle_seqno;
417 } mm;
418};
419
c153f45f 420extern struct drm_ioctl_desc i915_ioctls[];
b3a83639
DA		 421extern int i915_max_ioctl;
422
7c1c2871
DA		 423extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
424extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
425
1da177e4 426 /* i915_dma.c */
84b1fd10 427extern void i915_kernel_lost_context(struct drm_device * dev);
22eae947 428extern int i915_driver_load(struct drm_device *, unsigned long flags);
ba8bbcf6 429extern int i915_driver_unload(struct drm_device *);
673a394b 430extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
84b1fd10 431extern void i915_driver_lastclose(struct drm_device * dev);
6c340eac
EA		 432extern void i915_driver_preclose(struct drm_device *dev,
433 struct drm_file *file_priv);
673a394b
EA		 434extern void i915_driver_postclose(struct drm_device *dev,
435 struct drm_file *file_priv);
84b1fd10 436extern int i915_driver_device_is_agp(struct drm_device * dev);
0d6aa60b
DA		 437extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
438 unsigned long arg);
673a394b
EA		 439extern int i915_emit_box(struct drm_device *dev,
440 struct drm_clip_rect __user *boxes,
441 int i, int DR1, int DR4);
af6061af 442
1da177e4 443/* i915_irq.c */
c153f45f
EA		 444extern int i915_irq_emit(struct drm_device *dev, void *data,
445 struct drm_file *file_priv);
446extern int i915_irq_wait(struct drm_device *dev, void *data,
447 struct drm_file *file_priv);
673a394b
EA		 448void i915_user_irq_get(struct drm_device *dev);
449void i915_user_irq_put(struct drm_device *dev);
1da177e4
LT		 450
451extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
84b1fd10 452extern void i915_driver_irq_preinstall(struct drm_device * dev);
0a3e67a4 453extern int i915_driver_irq_postinstall(struct drm_device *dev);
84b1fd10 454extern void i915_driver_irq_uninstall(struct drm_device * dev);
c153f45f
EA		 455extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
456 struct drm_file *file_priv);
457extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
458 struct drm_file *file_priv);
0a3e67a4
JB		 459extern int i915_enable_vblank(struct drm_device *dev, int crtc);
460extern void i915_disable_vblank(struct drm_device *dev, int crtc);
461extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
c153f45f
EA		 462extern int i915_vblank_swap(struct drm_device *dev, void *data,
463 struct drm_file *file_priv);
8ee1c3db 464extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
1da177e4 465
7c463586
KP		 466void
467i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
468
469void
470i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
471
472
1da177e4 473/* i915_mem.c */
c153f45f
EA		 474extern int i915_mem_alloc(struct drm_device *dev, void *data,
475 struct drm_file *file_priv);
476extern int i915_mem_free(struct drm_device *dev, void *data,
477 struct drm_file *file_priv);
478extern int i915_mem_init_heap(struct drm_device *dev, void *data,
479 struct drm_file *file_priv);
480extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
481 struct drm_file *file_priv);
1da177e4 482extern void i915_mem_takedown(struct mem_block **heap);
84b1fd10 483extern void i915_mem_release(struct drm_device * dev,
6c340eac 484 struct drm_file *file_priv, struct mem_block *heap);
673a394b
EA		 485/* i915_gem.c */
486int i915_gem_init_ioctl(struct drm_device *dev, void *data,
487 struct drm_file *file_priv);
488int i915_gem_create_ioctl(struct drm_device *dev, void *data,
489 struct drm_file *file_priv);
490int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
491 struct drm_file *file_priv);
492int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
493 struct drm_file *file_priv);
494int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
495 struct drm_file *file_priv);
496int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
497 struct drm_file *file_priv);
498int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
499 struct drm_file *file_priv);
500int i915_gem_execbuffer(struct drm_device *dev, void *data,
501 struct drm_file *file_priv);
502int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
503 struct drm_file *file_priv);
504int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
505 struct drm_file *file_priv);
506int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
507 struct drm_file *file_priv);
508int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
509 struct drm_file *file_priv);
510int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
511 struct drm_file *file_priv);
512int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
513 struct drm_file *file_priv);
514int i915_gem_set_tiling(struct drm_device *dev, void *data,
515 struct drm_file *file_priv);
516int i915_gem_get_tiling(struct drm_device *dev, void *data,
517 struct drm_file *file_priv);
5a125c3c
EA		 518int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
519 struct drm_file *file_priv);
673a394b
EA		 520void i915_gem_load(struct drm_device *dev);
521int i915_gem_proc_init(struct drm_minor *minor);
522void i915_gem_proc_cleanup(struct drm_minor *minor);
523int i915_gem_init_object(struct drm_gem_object *obj);
524void i915_gem_free_object(struct drm_gem_object *obj);
525int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
526void i915_gem_object_unpin(struct drm_gem_object *obj);
527void i915_gem_lastclose(struct drm_device *dev);
528uint32_t i915_get_gem_seqno(struct drm_device *dev);
529void i915_gem_retire_requests(struct drm_device *dev);
530void i915_gem_retire_work_handler(struct work_struct *work);
531void i915_gem_clflush_object(struct drm_gem_object *obj);
532
533/* i915_gem_tiling.c */
534void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
535
536/* i915_gem_debug.c */
537void i915_gem_dump_object(struct drm_gem_object *obj, int len,
538 const char *where, uint32_t mark);
539#if WATCH_INACTIVE
540void i915_verify_inactive(struct drm_device *dev, char *file, int line);
541#else
542#define i915_verify_inactive(dev, file, line)
543#endif
544void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
545void i915_gem_dump_object(struct drm_gem_object *obj, int len,
546 const char *where, uint32_t mark);
547void i915_dump_lru(struct drm_device *dev, const char *where);
1da177e4 548
317c35d1
JB		 549/* i915_suspend.c */
550extern int i915_save_state(struct drm_device *dev);
551extern int i915_restore_state(struct drm_device *dev);
0a3e67a4
JB		 552
553/* i915_suspend.c */
554extern int i915_save_state(struct drm_device *dev);
555extern int i915_restore_state(struct drm_device *dev);
317c35d1 556
65e082c9 557#ifdef CONFIG_ACPI
8ee1c3db
MG		 558/* i915_opregion.c */
559extern int intel_opregion_init(struct drm_device *dev);
560extern void intel_opregion_free(struct drm_device *dev);
561extern void opregion_asle_intr(struct drm_device *dev);
562extern void opregion_enable_asle(struct drm_device *dev);
65e082c9
LB		 563#else
564static inline int intel_opregion_init(struct drm_device *dev) { return 0; }
565static inline void intel_opregion_free(struct drm_device *dev) { return; }
566static inline void opregion_asle_intr(struct drm_device *dev) { return; }
567static inline void opregion_enable_asle(struct drm_device *dev) { return; }
568#endif
8ee1c3db 569
546b0974
EA		 570/**
571 * Lock test for when it's just for synchronization of ring access.
572 *
573 * In that case, we don't need to do it when GEM is initialized as nobody else
574 * has access to the ring.
575 */
576#define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
577 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
578 LOCK_TEST_WITH_RETURN(dev, file_priv); \
579} while (0)
580
3043c60c
EA		 581#define I915_READ(reg) readl(dev_priv->regs + (reg))
582#define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
583#define I915_READ16(reg) readw(dev_priv->regs + (reg))
584#define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
585#define I915_READ8(reg) readb(dev_priv->regs + (reg))
586#define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
1da177e4
LT		 587
588#define I915_VERBOSE 0
589
590#define RING_LOCALS unsigned int outring, ringmask, outcount; \
591 volatile char *virt;
592
593#define BEGIN_LP_RING(n) do { \
594 if (I915_VERBOSE) \
3e684eae
MN		 595 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
596 if (dev_priv->ring.space < (n)*4) \
bf9d8929 597 i915_wait_ring(dev, (n)*4, __func__); \
1da177e4
LT		 598 outcount = 0; \
599 outring = dev_priv->ring.tail; \
600 ringmask = dev_priv->ring.tail_mask; \
601 virt = dev_priv->ring.virtual_start; \
602} while (0)
603
604#define OUT_RING(n) do { \
605 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
c29b669c 606 *(volatile unsigned int *)(virt + outring) = (n); \
1da177e4
LT		 607 outcount++; \
608 outring += 4; \
609 outring &= ringmask; \
610} while (0)
611
612#define ADVANCE_LP_RING() do { \
613 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
614 dev_priv->ring.tail = outring; \
615 dev_priv->ring.space -= outcount * 4; \
585fb111 616 I915_WRITE(PRB0_TAIL, outring); \
1da177e4
LT		 617} while(0)
618
ba8bbcf6 619/**
585fb111
JB		 620 * Reads a dword out of the status page, which is written to from the command
621 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
622 * MI_STORE_DATA_IMM.
ba8bbcf6 623 *
585fb111 624 * The following dwords have a reserved meaning:
0cdad7e8
KP		 625 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
626 * 0x04: ring 0 head pointer
627 * 0x05: ring 1 head pointer (915-class)
628 * 0x06: ring 2 head pointer (915-class)
629 * 0x10-0x1b: Context status DWords (GM45)
630 * 0x1f: Last written status offset. (GM45)
ba8bbcf6 631 *
0cdad7e8 632 * The area from dword 0x20 to 0x3ff is available for driver usage.
ba8bbcf6 633 */
585fb111 634#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
0baf823a 635#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
0cdad7e8 636#define I915_GEM_HWS_INDEX 0x20
0baf823a 637#define I915_BREADCRUMB_INDEX 0x21
ba8bbcf6 638
585fb111 639extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
ba8bbcf6
JB		 640
641#define IS_I830(dev) ((dev)->pci_device == 0x3577)
642#define IS_845G(dev) ((dev)->pci_device == 0x2562)
643#define IS_I85X(dev) ((dev)->pci_device == 0x3582)
644#define IS_I855(dev) ((dev)->pci_device == 0x3582)
645#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
646
4d1f7888 647#define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
ba8bbcf6
JB		 648#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
649#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
3bf48468
JB		 650#define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
651 (dev)->pci_device == 0x27AE)
ba8bbcf6
JB		 652#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
653 (dev)->pci_device == 0x2982 || \
654 (dev)->pci_device == 0x2992 || \
655 (dev)->pci_device == 0x29A2 || \
656 (dev)->pci_device == 0x2A02 || \
5f5f9d4c 657 (dev)->pci_device == 0x2A12 || \
d3adbc0c
ZW		 658 (dev)->pci_device == 0x2A42 || \
659 (dev)->pci_device == 0x2E02 || \
660 (dev)->pci_device == 0x2E12 || \
661 (dev)->pci_device == 0x2E22)
ba8bbcf6
JB		 662
663#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
664
b9bfdfe6 665#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
5f5f9d4c 666
d3adbc0c
ZW		 667#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
668 (dev)->pci_device == 0x2E12 || \
669 (dev)->pci_device == 0x2E22)
670
ba8bbcf6
JB		 671#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
672 (dev)->pci_device == 0x29B2 || \
673 (dev)->pci_device == 0x29D2)
674
675#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
676 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))
677
678#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
b9bfdfe6 679 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev))
ba8bbcf6 680
b9bfdfe6 681#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev))
b39d50e5 682
ba8bbcf6 683#define PRIMARY_RINGBUFFER_SIZE (128*1024)
0d6aa60b 684
1da177e4 685#endif
Linux 6.x block layer and io_uring tree(s)