Commit | Line | Data |
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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
e9b73c67 | 33 | #include <uapi/drm/i915_drm.h> |
93b81f51 | 34 | #include <uapi/drm/drm_fourcc.h> |
e9b73c67 | 35 | |
0839ccb8 | 36 | #include <linux/io-mapping.h> |
f899fc64 | 37 | #include <linux/i2c.h> |
c167a6fc | 38 | #include <linux/i2c-algo-bit.h> |
aaa6fd2a | 39 | #include <linux/backlight.h> |
5cc9ed4b | 40 | #include <linux/hashtable.h> |
2911a35b | 41 | #include <linux/intel-iommu.h> |
742cbee8 | 42 | #include <linux/kref.h> |
9ee32fea | 43 | #include <linux/pm_qos.h> |
e73bdd20 CW |
44 | #include <linux/shmem_fs.h> |
45 | ||
46 | #include <drm/drmP.h> | |
47 | #include <drm/intel-gtt.h> | |
48 | #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ | |
49 | #include <drm/drm_gem.h> | |
50 | ||
51 | #include "i915_params.h" | |
52 | #include "i915_reg.h" | |
53 | ||
54 | #include "intel_bios.h" | |
ac7f11c6 | 55 | #include "intel_dpll_mgr.h" |
e73bdd20 CW |
56 | #include "intel_guc.h" |
57 | #include "intel_lrc.h" | |
58 | #include "intel_ringbuffer.h" | |
59 | ||
d501b1d2 | 60 | #include "i915_gem.h" |
e73bdd20 CW |
61 | #include "i915_gem_gtt.h" |
62 | #include "i915_gem_render_state.h" | |
585fb111 | 63 | |
1da177e4 LT |
64 | /* General customization: |
65 | */ | |
66 | ||
1da177e4 LT |
67 | #define DRIVER_NAME "i915" |
68 | #define DRIVER_DESC "Intel Graphics" | |
2a55135c | 69 | #define DRIVER_DATE "20160508" |
1da177e4 | 70 | |
c883ef1b | 71 | #undef WARN_ON |
5f77eeb0 DV |
72 | /* Many gcc seem to no see through this and fall over :( */ |
73 | #if 0 | |
74 | #define WARN_ON(x) ({ \ | |
75 | bool __i915_warn_cond = (x); \ | |
76 | if (__builtin_constant_p(__i915_warn_cond)) \ | |
77 | BUILD_BUG_ON(__i915_warn_cond); \ | |
78 | WARN(__i915_warn_cond, "WARN_ON(" #x ")"); }) | |
79 | #else | |
152b2262 | 80 | #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")") |
5f77eeb0 DV |
81 | #endif |
82 | ||
cd9bfacb | 83 | #undef WARN_ON_ONCE |
152b2262 | 84 | #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")") |
cd9bfacb | 85 | |
5f77eeb0 DV |
86 | #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \ |
87 | (long) (x), __func__); | |
c883ef1b | 88 | |
e2c719b7 RC |
89 | /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and |
90 | * WARN_ON()) for hw state sanity checks to check for unexpected conditions | |
91 | * which may not necessarily be a user visible problem. This will either | |
92 | * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to | |
93 | * enable distros and users to tailor their preferred amount of i915 abrt | |
94 | * spam. | |
95 | */ | |
96 | #define I915_STATE_WARN(condition, format...) ({ \ | |
97 | int __ret_warn_on = !!(condition); \ | |
32753cb8 JL |
98 | if (unlikely(__ret_warn_on)) \ |
99 | if (!WARN(i915.verbose_state_checks, format)) \ | |
e2c719b7 | 100 | DRM_ERROR(format); \ |
e2c719b7 RC |
101 | unlikely(__ret_warn_on); \ |
102 | }) | |
103 | ||
152b2262 JL |
104 | #define I915_STATE_WARN_ON(x) \ |
105 | I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")") | |
c883ef1b | 106 | |
4fec15d1 ID |
107 | bool __i915_inject_load_failure(const char *func, int line); |
108 | #define i915_inject_load_failure() \ | |
109 | __i915_inject_load_failure(__func__, __LINE__) | |
110 | ||
42a8ca4c JN |
111 | static inline const char *yesno(bool v) |
112 | { | |
113 | return v ? "yes" : "no"; | |
114 | } | |
115 | ||
87ad3212 JN |
116 | static inline const char *onoff(bool v) |
117 | { | |
118 | return v ? "on" : "off"; | |
119 | } | |
120 | ||
317c35d1 | 121 | enum pipe { |
752aa88a | 122 | INVALID_PIPE = -1, |
317c35d1 JB |
123 | PIPE_A = 0, |
124 | PIPE_B, | |
9db4a9c7 | 125 | PIPE_C, |
a57c774a AK |
126 | _PIPE_EDP, |
127 | I915_MAX_PIPES = _PIPE_EDP | |
317c35d1 | 128 | }; |
9db4a9c7 | 129 | #define pipe_name(p) ((p) + 'A') |
317c35d1 | 130 | |
a5c961d1 PZ |
131 | enum transcoder { |
132 | TRANSCODER_A = 0, | |
133 | TRANSCODER_B, | |
134 | TRANSCODER_C, | |
a57c774a | 135 | TRANSCODER_EDP, |
4d1de975 JN |
136 | TRANSCODER_DSI_A, |
137 | TRANSCODER_DSI_C, | |
a57c774a | 138 | I915_MAX_TRANSCODERS |
a5c961d1 | 139 | }; |
da205630 JN |
140 | |
141 | static inline const char *transcoder_name(enum transcoder transcoder) | |
142 | { | |
143 | switch (transcoder) { | |
144 | case TRANSCODER_A: | |
145 | return "A"; | |
146 | case TRANSCODER_B: | |
147 | return "B"; | |
148 | case TRANSCODER_C: | |
149 | return "C"; | |
150 | case TRANSCODER_EDP: | |
151 | return "EDP"; | |
4d1de975 JN |
152 | case TRANSCODER_DSI_A: |
153 | return "DSI A"; | |
154 | case TRANSCODER_DSI_C: | |
155 | return "DSI C"; | |
da205630 JN |
156 | default: |
157 | return "<invalid>"; | |
158 | } | |
159 | } | |
a5c961d1 | 160 | |
4d1de975 JN |
161 | static inline bool transcoder_is_dsi(enum transcoder transcoder) |
162 | { | |
163 | return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C; | |
164 | } | |
165 | ||
84139d1e | 166 | /* |
31409e97 MR |
167 | * I915_MAX_PLANES in the enum below is the maximum (across all platforms) |
168 | * number of planes per CRTC. Not all platforms really have this many planes, | |
169 | * which means some arrays of size I915_MAX_PLANES may have unused entries | |
170 | * between the topmost sprite plane and the cursor plane. | |
84139d1e | 171 | */ |
80824003 JB |
172 | enum plane { |
173 | PLANE_A = 0, | |
174 | PLANE_B, | |
9db4a9c7 | 175 | PLANE_C, |
31409e97 MR |
176 | PLANE_CURSOR, |
177 | I915_MAX_PLANES, | |
80824003 | 178 | }; |
9db4a9c7 | 179 | #define plane_name(p) ((p) + 'A') |
52440211 | 180 | |
d615a166 | 181 | #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A') |
06da8da2 | 182 | |
2b139522 ED |
183 | enum port { |
184 | PORT_A = 0, | |
185 | PORT_B, | |
186 | PORT_C, | |
187 | PORT_D, | |
188 | PORT_E, | |
189 | I915_MAX_PORTS | |
190 | }; | |
191 | #define port_name(p) ((p) + 'A') | |
192 | ||
a09caddd | 193 | #define I915_NUM_PHYS_VLV 2 |
e4607fcf CML |
194 | |
195 | enum dpio_channel { | |
196 | DPIO_CH0, | |
197 | DPIO_CH1 | |
198 | }; | |
199 | ||
200 | enum dpio_phy { | |
201 | DPIO_PHY0, | |
202 | DPIO_PHY1 | |
203 | }; | |
204 | ||
b97186f0 PZ |
205 | enum intel_display_power_domain { |
206 | POWER_DOMAIN_PIPE_A, | |
207 | POWER_DOMAIN_PIPE_B, | |
208 | POWER_DOMAIN_PIPE_C, | |
209 | POWER_DOMAIN_PIPE_A_PANEL_FITTER, | |
210 | POWER_DOMAIN_PIPE_B_PANEL_FITTER, | |
211 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, | |
212 | POWER_DOMAIN_TRANSCODER_A, | |
213 | POWER_DOMAIN_TRANSCODER_B, | |
214 | POWER_DOMAIN_TRANSCODER_C, | |
f52e353e | 215 | POWER_DOMAIN_TRANSCODER_EDP, |
4d1de975 JN |
216 | POWER_DOMAIN_TRANSCODER_DSI_A, |
217 | POWER_DOMAIN_TRANSCODER_DSI_C, | |
6331a704 PJ |
218 | POWER_DOMAIN_PORT_DDI_A_LANES, |
219 | POWER_DOMAIN_PORT_DDI_B_LANES, | |
220 | POWER_DOMAIN_PORT_DDI_C_LANES, | |
221 | POWER_DOMAIN_PORT_DDI_D_LANES, | |
222 | POWER_DOMAIN_PORT_DDI_E_LANES, | |
319be8ae ID |
223 | POWER_DOMAIN_PORT_DSI, |
224 | POWER_DOMAIN_PORT_CRT, | |
225 | POWER_DOMAIN_PORT_OTHER, | |
cdf8dd7f | 226 | POWER_DOMAIN_VGA, |
fbeeaa23 | 227 | POWER_DOMAIN_AUDIO, |
bd2bb1b9 | 228 | POWER_DOMAIN_PLLS, |
1407121a S |
229 | POWER_DOMAIN_AUX_A, |
230 | POWER_DOMAIN_AUX_B, | |
231 | POWER_DOMAIN_AUX_C, | |
232 | POWER_DOMAIN_AUX_D, | |
f0ab43e6 | 233 | POWER_DOMAIN_GMBUS, |
dfa57627 | 234 | POWER_DOMAIN_MODESET, |
baa70707 | 235 | POWER_DOMAIN_INIT, |
bddc7645 ID |
236 | |
237 | POWER_DOMAIN_NUM, | |
b97186f0 PZ |
238 | }; |
239 | ||
240 | #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) | |
241 | #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ | |
242 | ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) | |
f52e353e ID |
243 | #define POWER_DOMAIN_TRANSCODER(tran) \ |
244 | ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ | |
245 | (tran) + POWER_DOMAIN_TRANSCODER_A) | |
b97186f0 | 246 | |
1d843f9d EE |
247 | enum hpd_pin { |
248 | HPD_NONE = 0, | |
1d843f9d EE |
249 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ |
250 | HPD_CRT, | |
251 | HPD_SDVO_B, | |
252 | HPD_SDVO_C, | |
cc24fcdc | 253 | HPD_PORT_A, |
1d843f9d EE |
254 | HPD_PORT_B, |
255 | HPD_PORT_C, | |
256 | HPD_PORT_D, | |
26951caf | 257 | HPD_PORT_E, |
1d843f9d EE |
258 | HPD_NUM_PINS |
259 | }; | |
260 | ||
c91711f9 JN |
261 | #define for_each_hpd_pin(__pin) \ |
262 | for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) | |
263 | ||
5fcece80 JN |
264 | struct i915_hotplug { |
265 | struct work_struct hotplug_work; | |
266 | ||
267 | struct { | |
268 | unsigned long last_jiffies; | |
269 | int count; | |
270 | enum { | |
271 | HPD_ENABLED = 0, | |
272 | HPD_DISABLED = 1, | |
273 | HPD_MARK_DISABLED = 2 | |
274 | } state; | |
275 | } stats[HPD_NUM_PINS]; | |
276 | u32 event_bits; | |
277 | struct delayed_work reenable_work; | |
278 | ||
279 | struct intel_digital_port *irq_port[I915_MAX_PORTS]; | |
280 | u32 long_port_mask; | |
281 | u32 short_port_mask; | |
282 | struct work_struct dig_port_work; | |
283 | ||
284 | /* | |
285 | * if we get a HPD irq from DP and a HPD irq from non-DP | |
286 | * the non-DP HPD could block the workqueue on a mode config | |
287 | * mutex getting, that userspace may have taken. However | |
288 | * userspace is waiting on the DP workqueue to run which is | |
289 | * blocked behind the non-DP one. | |
290 | */ | |
291 | struct workqueue_struct *dp_wq; | |
292 | }; | |
293 | ||
2a2d5482 CW |
294 | #define I915_GEM_GPU_DOMAINS \ |
295 | (I915_GEM_DOMAIN_RENDER | \ | |
296 | I915_GEM_DOMAIN_SAMPLER | \ | |
297 | I915_GEM_DOMAIN_COMMAND | \ | |
298 | I915_GEM_DOMAIN_INSTRUCTION | \ | |
299 | I915_GEM_DOMAIN_VERTEX) | |
62fdfeaf | 300 | |
055e393f DL |
301 | #define for_each_pipe(__dev_priv, __p) \ |
302 | for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) | |
6831f3e3 VS |
303 | #define for_each_pipe_masked(__dev_priv, __p, __mask) \ |
304 | for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \ | |
305 | for_each_if ((__mask) & (1 << (__p))) | |
dd740780 DL |
306 | #define for_each_plane(__dev_priv, __pipe, __p) \ |
307 | for ((__p) = 0; \ | |
308 | (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ | |
309 | (__p)++) | |
3bdcfc0c DL |
310 | #define for_each_sprite(__dev_priv, __p, __s) \ |
311 | for ((__s) = 0; \ | |
312 | (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \ | |
313 | (__s)++) | |
9db4a9c7 | 314 | |
c3aeadc8 JN |
315 | #define for_each_port_masked(__port, __ports_mask) \ |
316 | for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \ | |
317 | for_each_if ((__ports_mask) & (1 << (__port))) | |
318 | ||
d79b814d DL |
319 | #define for_each_crtc(dev, crtc) \ |
320 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) | |
321 | ||
27321ae8 ML |
322 | #define for_each_intel_plane(dev, intel_plane) \ |
323 | list_for_each_entry(intel_plane, \ | |
324 | &dev->mode_config.plane_list, \ | |
325 | base.head) | |
326 | ||
262cd2e1 VS |
327 | #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ |
328 | list_for_each_entry(intel_plane, \ | |
329 | &(dev)->mode_config.plane_list, \ | |
330 | base.head) \ | |
95150bdf | 331 | for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe) |
262cd2e1 | 332 | |
d063ae48 DL |
333 | #define for_each_intel_crtc(dev, intel_crtc) \ |
334 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) | |
335 | ||
b2784e15 DL |
336 | #define for_each_intel_encoder(dev, intel_encoder) \ |
337 | list_for_each_entry(intel_encoder, \ | |
338 | &(dev)->mode_config.encoder_list, \ | |
339 | base.head) | |
340 | ||
3a3371ff ACO |
341 | #define for_each_intel_connector(dev, intel_connector) \ |
342 | list_for_each_entry(intel_connector, \ | |
343 | &dev->mode_config.connector_list, \ | |
344 | base.head) | |
345 | ||
6c2b7c12 DV |
346 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
347 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ | |
95150bdf | 348 | for_each_if ((intel_encoder)->base.crtc == (__crtc)) |
6c2b7c12 | 349 | |
53f5e3ca JB |
350 | #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ |
351 | list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ | |
95150bdf | 352 | for_each_if ((intel_connector)->base.encoder == (__encoder)) |
53f5e3ca | 353 | |
b04c5bd6 BF |
354 | #define for_each_power_domain(domain, mask) \ |
355 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
95150bdf | 356 | for_each_if ((1 << (domain)) & (mask)) |
b04c5bd6 | 357 | |
e7b903d2 | 358 | struct drm_i915_private; |
ad46cb53 | 359 | struct i915_mm_struct; |
5cc9ed4b | 360 | struct i915_mmu_object; |
e7b903d2 | 361 | |
a6f766f3 CW |
362 | struct drm_i915_file_private { |
363 | struct drm_i915_private *dev_priv; | |
364 | struct drm_file *file; | |
365 | ||
366 | struct { | |
367 | spinlock_t lock; | |
368 | struct list_head request_list; | |
d0bc54f2 CW |
369 | /* 20ms is a fairly arbitrary limit (greater than the average frame time) |
370 | * chosen to prevent the CPU getting more than a frame ahead of the GPU | |
371 | * (when using lax throttling for the frontbuffer). We also use it to | |
372 | * offer free GPU waitboosts for severely congested workloads. | |
373 | */ | |
374 | #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20) | |
a6f766f3 CW |
375 | } mm; |
376 | struct idr context_idr; | |
377 | ||
2e1b8730 CW |
378 | struct intel_rps_client { |
379 | struct list_head link; | |
380 | unsigned boosts; | |
381 | } rps; | |
a6f766f3 | 382 | |
de1add36 | 383 | unsigned int bsd_ring; |
a6f766f3 CW |
384 | }; |
385 | ||
e69d0bc1 DV |
386 | /* Used by dp and fdi links */ |
387 | struct intel_link_m_n { | |
388 | uint32_t tu; | |
389 | uint32_t gmch_m; | |
390 | uint32_t gmch_n; | |
391 | uint32_t link_m; | |
392 | uint32_t link_n; | |
393 | }; | |
394 | ||
395 | void intel_link_compute_m_n(int bpp, int nlanes, | |
396 | int pixel_clock, int link_clock, | |
397 | struct intel_link_m_n *m_n); | |
398 | ||
1da177e4 LT |
399 | /* Interface history: |
400 | * | |
401 | * 1.1: Original. | |
0d6aa60b DA |
402 | * 1.2: Add Power Management |
403 | * 1.3: Add vblank support | |
de227f5f | 404 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 405 | * 1.5: Add vblank pipe configuration |
2228ed67 MCA |
406 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
407 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
408 | */ |
409 | #define DRIVER_MAJOR 1 | |
2228ed67 | 410 | #define DRIVER_MINOR 6 |
1da177e4 LT |
411 | #define DRIVER_PATCHLEVEL 0 |
412 | ||
23bc5982 | 413 | #define WATCH_LISTS 0 |
673a394b | 414 | |
0a3e67a4 JB |
415 | struct opregion_header; |
416 | struct opregion_acpi; | |
417 | struct opregion_swsci; | |
418 | struct opregion_asle; | |
419 | ||
8ee1c3db | 420 | struct intel_opregion { |
115719fc WD |
421 | struct opregion_header *header; |
422 | struct opregion_acpi *acpi; | |
423 | struct opregion_swsci *swsci; | |
ebde53c7 JN |
424 | u32 swsci_gbda_sub_functions; |
425 | u32 swsci_sbcb_sub_functions; | |
115719fc | 426 | struct opregion_asle *asle; |
04ebaadb | 427 | void *rvda; |
82730385 | 428 | const void *vbt; |
ada8f955 | 429 | u32 vbt_size; |
115719fc | 430 | u32 *lid_state; |
91a60f20 | 431 | struct work_struct asle_work; |
8ee1c3db | 432 | }; |
44834a67 | 433 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 434 | |
6ef3d427 CW |
435 | struct intel_overlay; |
436 | struct intel_overlay_error_state; | |
437 | ||
de151cf6 | 438 | #define I915_FENCE_REG_NONE -1 |
42b5aeab VS |
439 | #define I915_MAX_NUM_FENCES 32 |
440 | /* 32 fences + sign bit for FENCE_REG_NONE */ | |
441 | #define I915_MAX_NUM_FENCE_BITS 6 | |
de151cf6 JB |
442 | |
443 | struct drm_i915_fence_reg { | |
007cc8ac | 444 | struct list_head lru_list; |
caea7476 | 445 | struct drm_i915_gem_object *obj; |
1690e1eb | 446 | int pin_count; |
de151cf6 | 447 | }; |
7c1c2871 | 448 | |
9b9d172d | 449 | struct sdvo_device_mapping { |
e957d772 | 450 | u8 initialized; |
9b9d172d | 451 | u8 dvo_port; |
452 | u8 slave_addr; | |
453 | u8 dvo_wiring; | |
e957d772 | 454 | u8 i2c_pin; |
b1083333 | 455 | u8 ddc_pin; |
9b9d172d | 456 | }; |
457 | ||
c4a1d9e4 CW |
458 | struct intel_display_error_state; |
459 | ||
63eeaf38 | 460 | struct drm_i915_error_state { |
742cbee8 | 461 | struct kref ref; |
585b0288 BW |
462 | struct timeval time; |
463 | ||
cb383002 | 464 | char error_msg[128]; |
eb5be9d0 | 465 | int iommu; |
48b031e3 | 466 | u32 reset_count; |
62d5d69b | 467 | u32 suspend_count; |
cb383002 | 468 | |
585b0288 | 469 | /* Generic register state */ |
63eeaf38 JB |
470 | u32 eir; |
471 | u32 pgtbl_er; | |
be998e2e | 472 | u32 ier; |
885ea5a8 | 473 | u32 gtier[4]; |
b9a3906b | 474 | u32 ccid; |
0f3b6849 CW |
475 | u32 derrmr; |
476 | u32 forcewake; | |
585b0288 BW |
477 | u32 error; /* gen6+ */ |
478 | u32 err_int; /* gen7 */ | |
6c826f34 MK |
479 | u32 fault_data0; /* gen8, gen9 */ |
480 | u32 fault_data1; /* gen8, gen9 */ | |
585b0288 | 481 | u32 done_reg; |
91ec5d11 BW |
482 | u32 gac_eco; |
483 | u32 gam_ecochk; | |
484 | u32 gab_ctl; | |
485 | u32 gfx_mode; | |
585b0288 | 486 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; |
585b0288 BW |
487 | u64 fence[I915_MAX_NUM_FENCES]; |
488 | struct intel_overlay_error_state *overlay; | |
489 | struct intel_display_error_state *display; | |
0ca36d78 | 490 | struct drm_i915_error_object *semaphore_obj; |
585b0288 | 491 | |
52d39a21 | 492 | struct drm_i915_error_ring { |
372fbb8e | 493 | bool valid; |
362b8af7 BW |
494 | /* Software tracked state */ |
495 | bool waiting; | |
496 | int hangcheck_score; | |
497 | enum intel_ring_hangcheck_action hangcheck_action; | |
498 | int num_requests; | |
499 | ||
500 | /* our own tracking of ring head and tail */ | |
501 | u32 cpu_ring_head; | |
502 | u32 cpu_ring_tail; | |
503 | ||
14fd0d6d | 504 | u32 last_seqno; |
666796da | 505 | u32 semaphore_seqno[I915_NUM_ENGINES - 1]; |
362b8af7 BW |
506 | |
507 | /* Register state */ | |
94f8cf10 | 508 | u32 start; |
362b8af7 BW |
509 | u32 tail; |
510 | u32 head; | |
511 | u32 ctl; | |
512 | u32 hws; | |
513 | u32 ipeir; | |
514 | u32 ipehr; | |
515 | u32 instdone; | |
362b8af7 BW |
516 | u32 bbstate; |
517 | u32 instpm; | |
518 | u32 instps; | |
519 | u32 seqno; | |
520 | u64 bbaddr; | |
50877445 | 521 | u64 acthd; |
362b8af7 | 522 | u32 fault_reg; |
13ffadd1 | 523 | u64 faddr; |
362b8af7 | 524 | u32 rc_psmi; /* sleep state */ |
666796da | 525 | u32 semaphore_mboxes[I915_NUM_ENGINES - 1]; |
362b8af7 | 526 | |
52d39a21 CW |
527 | struct drm_i915_error_object { |
528 | int page_count; | |
e1f12325 | 529 | u64 gtt_offset; |
52d39a21 | 530 | u32 *pages[0]; |
ab0e7ff9 | 531 | } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; |
362b8af7 | 532 | |
f85db059 | 533 | struct drm_i915_error_object *wa_ctx; |
534 | ||
52d39a21 CW |
535 | struct drm_i915_error_request { |
536 | long jiffies; | |
537 | u32 seqno; | |
ee4f42b1 | 538 | u32 tail; |
52d39a21 | 539 | } *requests; |
6c7a01ec BW |
540 | |
541 | struct { | |
542 | u32 gfx_mode; | |
543 | union { | |
544 | u64 pdp[4]; | |
545 | u32 pp_dir_base; | |
546 | }; | |
547 | } vm_info; | |
ab0e7ff9 CW |
548 | |
549 | pid_t pid; | |
550 | char comm[TASK_COMM_LEN]; | |
666796da | 551 | } ring[I915_NUM_ENGINES]; |
3a448734 | 552 | |
9df30794 | 553 | struct drm_i915_error_buffer { |
a779e5ab | 554 | u32 size; |
9df30794 | 555 | u32 name; |
666796da | 556 | u32 rseqno[I915_NUM_ENGINES], wseqno; |
e1f12325 | 557 | u64 gtt_offset; |
9df30794 CW |
558 | u32 read_domains; |
559 | u32 write_domain; | |
4b9de737 | 560 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
9df30794 CW |
561 | s32 pinned:2; |
562 | u32 tiling:2; | |
563 | u32 dirty:1; | |
564 | u32 purgeable:1; | |
5cc9ed4b | 565 | u32 userptr:1; |
5d1333fc | 566 | s32 ring:4; |
f56383cb | 567 | u32 cache_level:3; |
95f5301d | 568 | } **active_bo, **pinned_bo; |
6c7a01ec | 569 | |
95f5301d | 570 | u32 *active_bo_count, *pinned_bo_count; |
3a448734 | 571 | u32 vm_count; |
63eeaf38 JB |
572 | }; |
573 | ||
7bd688cd | 574 | struct intel_connector; |
820d2d77 | 575 | struct intel_encoder; |
5cec258b | 576 | struct intel_crtc_state; |
5724dbd1 | 577 | struct intel_initial_plane_config; |
0e8ffe1b | 578 | struct intel_crtc; |
ee9300bb DV |
579 | struct intel_limit; |
580 | struct dpll; | |
b8cecdf5 | 581 | |
e70236a8 | 582 | struct drm_i915_display_funcs { |
e70236a8 JB |
583 | int (*get_display_clock_speed)(struct drm_device *dev); |
584 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
e3bddded | 585 | int (*compute_pipe_wm)(struct intel_crtc_state *cstate); |
ed4a6a7c MR |
586 | int (*compute_intermediate_wm)(struct drm_device *dev, |
587 | struct intel_crtc *intel_crtc, | |
588 | struct intel_crtc_state *newstate); | |
589 | void (*initial_watermarks)(struct intel_crtc_state *cstate); | |
590 | void (*optimize_watermarks)(struct intel_crtc_state *cstate); | |
46ba614c | 591 | void (*update_wm)(struct drm_crtc *crtc); |
27c329ed ML |
592 | int (*modeset_calc_cdclk)(struct drm_atomic_state *state); |
593 | void (*modeset_commit_cdclk)(struct drm_atomic_state *state); | |
0e8ffe1b DV |
594 | /* Returns the active state of the crtc, and if the crtc is active, |
595 | * fills out the pipe-config with the hw state. */ | |
596 | bool (*get_pipe_config)(struct intel_crtc *, | |
5cec258b | 597 | struct intel_crtc_state *); |
5724dbd1 DL |
598 | void (*get_initial_plane_config)(struct intel_crtc *, |
599 | struct intel_initial_plane_config *); | |
190f68c5 ACO |
600 | int (*crtc_compute_clock)(struct intel_crtc *crtc, |
601 | struct intel_crtc_state *crtc_state); | |
76e5a89c DV |
602 | void (*crtc_enable)(struct drm_crtc *crtc); |
603 | void (*crtc_disable)(struct drm_crtc *crtc); | |
69bfe1a9 JN |
604 | void (*audio_codec_enable)(struct drm_connector *connector, |
605 | struct intel_encoder *encoder, | |
5e7234c9 | 606 | const struct drm_display_mode *adjusted_mode); |
69bfe1a9 | 607 | void (*audio_codec_disable)(struct intel_encoder *encoder); |
674cf967 | 608 | void (*fdi_link_train)(struct drm_crtc *crtc); |
6067aaea | 609 | void (*init_clock_gating)(struct drm_device *dev); |
8c9f3aaf JB |
610 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
611 | struct drm_framebuffer *fb, | |
ed8d1975 | 612 | struct drm_i915_gem_object *obj, |
6258fbe2 | 613 | struct drm_i915_gem_request *req, |
ed8d1975 | 614 | uint32_t flags); |
91d14251 | 615 | void (*hpd_irq_setup)(struct drm_i915_private *dev_priv); |
e70236a8 JB |
616 | /* clock updates for mode set */ |
617 | /* cursor updates */ | |
618 | /* render clock increase/decrease */ | |
619 | /* display clock increase/decrease */ | |
620 | /* pll clock increase/decrease */ | |
8563b1e8 | 621 | |
b95c5321 ML |
622 | void (*load_csc_matrix)(struct drm_crtc_state *crtc_state); |
623 | void (*load_luts)(struct drm_crtc_state *crtc_state); | |
e70236a8 JB |
624 | }; |
625 | ||
48c1026a MK |
626 | enum forcewake_domain_id { |
627 | FW_DOMAIN_ID_RENDER = 0, | |
628 | FW_DOMAIN_ID_BLITTER, | |
629 | FW_DOMAIN_ID_MEDIA, | |
630 | ||
631 | FW_DOMAIN_ID_COUNT | |
632 | }; | |
633 | ||
634 | enum forcewake_domains { | |
635 | FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER), | |
636 | FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER), | |
637 | FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA), | |
638 | FORCEWAKE_ALL = (FORCEWAKE_RENDER | | |
639 | FORCEWAKE_BLITTER | | |
640 | FORCEWAKE_MEDIA) | |
641 | }; | |
642 | ||
3756685a TU |
643 | #define FW_REG_READ (1) |
644 | #define FW_REG_WRITE (2) | |
645 | ||
646 | enum forcewake_domains | |
647 | intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv, | |
648 | i915_reg_t reg, unsigned int op); | |
649 | ||
907b28c5 | 650 | struct intel_uncore_funcs { |
c8d9a590 | 651 | void (*force_wake_get)(struct drm_i915_private *dev_priv, |
48c1026a | 652 | enum forcewake_domains domains); |
c8d9a590 | 653 | void (*force_wake_put)(struct drm_i915_private *dev_priv, |
48c1026a | 654 | enum forcewake_domains domains); |
0b274481 | 655 | |
f0f59a00 VS |
656 | uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); |
657 | uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); | |
658 | uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); | |
659 | uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); | |
0b274481 | 660 | |
f0f59a00 | 661 | void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r, |
0b274481 | 662 | uint8_t val, bool trace); |
f0f59a00 | 663 | void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r, |
0b274481 | 664 | uint16_t val, bool trace); |
f0f59a00 | 665 | void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r, |
0b274481 | 666 | uint32_t val, bool trace); |
f0f59a00 | 667 | void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r, |
0b274481 | 668 | uint64_t val, bool trace); |
990bbdad CW |
669 | }; |
670 | ||
907b28c5 CW |
671 | struct intel_uncore { |
672 | spinlock_t lock; /** lock is also taken in irq contexts. */ | |
673 | ||
674 | struct intel_uncore_funcs funcs; | |
675 | ||
676 | unsigned fifo_count; | |
48c1026a | 677 | enum forcewake_domains fw_domains; |
b2cff0db CW |
678 | |
679 | struct intel_uncore_forcewake_domain { | |
680 | struct drm_i915_private *i915; | |
48c1026a | 681 | enum forcewake_domain_id id; |
33c582c1 | 682 | enum forcewake_domains mask; |
b2cff0db | 683 | unsigned wake_count; |
a57a4a67 | 684 | struct hrtimer timer; |
f0f59a00 | 685 | i915_reg_t reg_set; |
05a2fb15 MK |
686 | u32 val_set; |
687 | u32 val_clear; | |
f0f59a00 VS |
688 | i915_reg_t reg_ack; |
689 | i915_reg_t reg_post; | |
05a2fb15 | 690 | u32 val_reset; |
b2cff0db | 691 | } fw_domain[FW_DOMAIN_ID_COUNT]; |
75714940 MK |
692 | |
693 | int unclaimed_mmio_check; | |
b2cff0db CW |
694 | }; |
695 | ||
696 | /* Iterate over initialised fw domains */ | |
33c582c1 TU |
697 | #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \ |
698 | for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \ | |
699 | (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \ | |
700 | (domain__)++) \ | |
701 | for_each_if ((mask__) & (domain__)->mask) | |
702 | ||
703 | #define for_each_fw_domain(domain__, dev_priv__) \ | |
704 | for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__) | |
907b28c5 | 705 | |
b6e7d894 DL |
706 | #define CSR_VERSION(major, minor) ((major) << 16 | (minor)) |
707 | #define CSR_VERSION_MAJOR(version) ((version) >> 16) | |
708 | #define CSR_VERSION_MINOR(version) ((version) & 0xffff) | |
709 | ||
eb805623 | 710 | struct intel_csr { |
8144ac59 | 711 | struct work_struct work; |
eb805623 | 712 | const char *fw_path; |
a7f749f9 | 713 | uint32_t *dmc_payload; |
eb805623 | 714 | uint32_t dmc_fw_size; |
b6e7d894 | 715 | uint32_t version; |
eb805623 | 716 | uint32_t mmio_count; |
f0f59a00 | 717 | i915_reg_t mmioaddr[8]; |
eb805623 | 718 | uint32_t mmiodata[8]; |
832dba88 | 719 | uint32_t dc_state; |
a37baf3b | 720 | uint32_t allowed_dc_mask; |
eb805623 DV |
721 | }; |
722 | ||
79fc46df DL |
723 | #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ |
724 | func(is_mobile) sep \ | |
725 | func(is_i85x) sep \ | |
726 | func(is_i915g) sep \ | |
727 | func(is_i945gm) sep \ | |
728 | func(is_g33) sep \ | |
729 | func(need_gfx_hws) sep \ | |
730 | func(is_g4x) sep \ | |
731 | func(is_pineview) sep \ | |
732 | func(is_broadwater) sep \ | |
733 | func(is_crestline) sep \ | |
734 | func(is_ivybridge) sep \ | |
735 | func(is_valleyview) sep \ | |
666a4537 | 736 | func(is_cherryview) sep \ |
79fc46df | 737 | func(is_haswell) sep \ |
7201c0b3 | 738 | func(is_skylake) sep \ |
7526ac19 | 739 | func(is_broxton) sep \ |
ef11bdb3 | 740 | func(is_kabylake) sep \ |
b833d685 | 741 | func(is_preliminary) sep \ |
79fc46df DL |
742 | func(has_fbc) sep \ |
743 | func(has_pipe_cxsr) sep \ | |
744 | func(has_hotplug) sep \ | |
745 | func(cursor_needs_physical) sep \ | |
746 | func(has_overlay) sep \ | |
747 | func(overlay_needs_physical) sep \ | |
748 | func(supports_tv) sep \ | |
dd93be58 | 749 | func(has_llc) sep \ |
ca377809 | 750 | func(has_snoop) sep \ |
30568c45 DL |
751 | func(has_ddi) sep \ |
752 | func(has_fpga_dbg) | |
c96ea64e | 753 | |
a587f779 DL |
754 | #define DEFINE_FLAG(name) u8 name:1 |
755 | #define SEP_SEMICOLON ; | |
c96ea64e | 756 | |
cfdf1fa2 | 757 | struct intel_device_info { |
10fce67a | 758 | u32 display_mmio_offset; |
87f1f465 | 759 | u16 device_id; |
7eb552ae | 760 | u8 num_pipes:3; |
d615a166 | 761 | u8 num_sprites[I915_MAX_PIPES]; |
c96c3a8c | 762 | u8 gen; |
73ae478c | 763 | u8 ring_mask; /* Rings supported by the HW */ |
a587f779 | 764 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); |
a57c774a AK |
765 | /* Register offsets for the various display pipes and transcoders */ |
766 | int pipe_offsets[I915_MAX_TRANSCODERS]; | |
767 | int trans_offsets[I915_MAX_TRANSCODERS]; | |
a57c774a | 768 | int palette_offsets[I915_MAX_PIPES]; |
5efb3e28 | 769 | int cursor_offsets[I915_MAX_PIPES]; |
3873218f JM |
770 | |
771 | /* Slice/subslice/EU info */ | |
772 | u8 slice_total; | |
773 | u8 subslice_total; | |
774 | u8 subslice_per_slice; | |
775 | u8 eu_total; | |
776 | u8 eu_per_subslice; | |
b7668791 DL |
777 | /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ |
778 | u8 subslice_7eu[3]; | |
3873218f JM |
779 | u8 has_slice_pg:1; |
780 | u8 has_subslice_pg:1; | |
781 | u8 has_eu_pg:1; | |
82cf435b LL |
782 | |
783 | struct color_luts { | |
784 | u16 degamma_lut_size; | |
785 | u16 gamma_lut_size; | |
786 | } color; | |
cfdf1fa2 KH |
787 | }; |
788 | ||
a587f779 DL |
789 | #undef DEFINE_FLAG |
790 | #undef SEP_SEMICOLON | |
791 | ||
7faf1ab2 DV |
792 | enum i915_cache_level { |
793 | I915_CACHE_NONE = 0, | |
350ec881 CW |
794 | I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ |
795 | I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc | |
796 | caches, eg sampler/render caches, and the | |
797 | large Last-Level-Cache. LLC is coherent with | |
798 | the CPU, but L3 is only visible to the GPU. */ | |
651d794f | 799 | I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ |
7faf1ab2 DV |
800 | }; |
801 | ||
e59ec13d MK |
802 | struct i915_ctx_hang_stats { |
803 | /* This context had batch pending when hang was declared */ | |
804 | unsigned batch_pending; | |
805 | ||
806 | /* This context had batch active when hang was declared */ | |
807 | unsigned batch_active; | |
be62acb4 MK |
808 | |
809 | /* Time when this context was last blamed for a GPU reset */ | |
810 | unsigned long guilty_ts; | |
811 | ||
676fa572 CW |
812 | /* If the contexts causes a second GPU hang within this time, |
813 | * it is permanently banned from submitting any more work. | |
814 | */ | |
815 | unsigned long ban_period_seconds; | |
816 | ||
be62acb4 MK |
817 | /* This context is banned to submit more work */ |
818 | bool banned; | |
e59ec13d | 819 | }; |
40521054 BW |
820 | |
821 | /* This must match up with the value previously used for execbuf2.rsvd1. */ | |
821d66dd | 822 | #define DEFAULT_CONTEXT_HANDLE 0 |
b1b38278 DW |
823 | |
824 | #define CONTEXT_NO_ZEROMAP (1<<0) | |
31b7a88d OM |
825 | /** |
826 | * struct intel_context - as the name implies, represents a context. | |
827 | * @ref: reference count. | |
828 | * @user_handle: userspace tracking identity for this context. | |
829 | * @remap_slice: l3 row remapping information. | |
b1b38278 DW |
830 | * @flags: context specific flags: |
831 | * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0. | |
31b7a88d OM |
832 | * @file_priv: filp associated with this context (NULL for global default |
833 | * context). | |
834 | * @hang_stats: information about the role of this context in possible GPU | |
835 | * hangs. | |
7df113e4 | 836 | * @ppgtt: virtual memory space used by this context. |
31b7a88d OM |
837 | * @legacy_hw_ctx: render context backing object and whether it is correctly |
838 | * initialized (legacy ring submission mechanism only). | |
839 | * @link: link in the global list of contexts. | |
840 | * | |
841 | * Contexts are memory images used by the hardware to store copies of their | |
842 | * internal state. | |
843 | */ | |
273497e5 | 844 | struct intel_context { |
dce3271b | 845 | struct kref ref; |
821d66dd | 846 | int user_handle; |
3ccfd19d | 847 | uint8_t remap_slice; |
9ea4feec | 848 | struct drm_i915_private *i915; |
b1b38278 | 849 | int flags; |
40521054 | 850 | struct drm_i915_file_private *file_priv; |
e59ec13d | 851 | struct i915_ctx_hang_stats hang_stats; |
ae6c4806 | 852 | struct i915_hw_ppgtt *ppgtt; |
a33afea5 | 853 | |
5d1808ec CW |
854 | /* Unique identifier for this context, used by the hw for tracking */ |
855 | unsigned hw_id; | |
856 | ||
c9e003af | 857 | /* Legacy ring buffer submission */ |
ea0c76f8 OM |
858 | struct { |
859 | struct drm_i915_gem_object *rcs_state; | |
860 | bool initialized; | |
861 | } legacy_hw_ctx; | |
862 | ||
c9e003af OM |
863 | /* Execlists */ |
864 | struct { | |
865 | struct drm_i915_gem_object *state; | |
84c2377f | 866 | struct intel_ringbuffer *ringbuf; |
a7cbedec | 867 | int pin_count; |
ca82580c TU |
868 | struct i915_vma *lrc_vma; |
869 | u64 lrc_desc; | |
82352e90 | 870 | uint32_t *lrc_reg_state; |
24f1d3cc | 871 | bool initialised; |
666796da | 872 | } engine[I915_NUM_ENGINES]; |
c9e003af | 873 | |
a33afea5 | 874 | struct list_head link; |
40521054 BW |
875 | }; |
876 | ||
a4001f1b PZ |
877 | enum fb_op_origin { |
878 | ORIGIN_GTT, | |
879 | ORIGIN_CPU, | |
880 | ORIGIN_CS, | |
881 | ORIGIN_FLIP, | |
74b4ea1e | 882 | ORIGIN_DIRTYFB, |
a4001f1b PZ |
883 | }; |
884 | ||
ab34a7e8 | 885 | struct intel_fbc { |
25ad93fd PZ |
886 | /* This is always the inner lock when overlapping with struct_mutex and |
887 | * it's the outer lock when overlapping with stolen_lock. */ | |
888 | struct mutex lock; | |
5e59f717 | 889 | unsigned threshold; |
dbef0f15 PZ |
890 | unsigned int possible_framebuffer_bits; |
891 | unsigned int busy_bits; | |
010cf73d | 892 | unsigned int visible_pipes_mask; |
e35fef21 | 893 | struct intel_crtc *crtc; |
5c3fe8b0 | 894 | |
c4213885 | 895 | struct drm_mm_node compressed_fb; |
5c3fe8b0 BW |
896 | struct drm_mm_node *compressed_llb; |
897 | ||
da46f936 RV |
898 | bool false_color; |
899 | ||
d029bcad | 900 | bool enabled; |
0e631adc | 901 | bool active; |
9adccc60 | 902 | |
aaf78d27 PZ |
903 | struct intel_fbc_state_cache { |
904 | struct { | |
905 | unsigned int mode_flags; | |
906 | uint32_t hsw_bdw_pixel_rate; | |
907 | } crtc; | |
908 | ||
909 | struct { | |
910 | unsigned int rotation; | |
911 | int src_w; | |
912 | int src_h; | |
913 | bool visible; | |
914 | } plane; | |
915 | ||
916 | struct { | |
917 | u64 ilk_ggtt_offset; | |
aaf78d27 PZ |
918 | uint32_t pixel_format; |
919 | unsigned int stride; | |
920 | int fence_reg; | |
921 | unsigned int tiling_mode; | |
922 | } fb; | |
923 | } state_cache; | |
924 | ||
b183b3f1 PZ |
925 | struct intel_fbc_reg_params { |
926 | struct { | |
927 | enum pipe pipe; | |
928 | enum plane plane; | |
929 | unsigned int fence_y_offset; | |
930 | } crtc; | |
931 | ||
932 | struct { | |
933 | u64 ggtt_offset; | |
b183b3f1 PZ |
934 | uint32_t pixel_format; |
935 | unsigned int stride; | |
936 | int fence_reg; | |
937 | } fb; | |
938 | ||
939 | int cfb_size; | |
940 | } params; | |
941 | ||
5c3fe8b0 | 942 | struct intel_fbc_work { |
128d7356 | 943 | bool scheduled; |
ca18d51d | 944 | u32 scheduled_vblank; |
128d7356 | 945 | struct work_struct work; |
128d7356 | 946 | } work; |
5c3fe8b0 | 947 | |
bf6189c6 | 948 | const char *no_fbc_reason; |
b5e50c3f JB |
949 | }; |
950 | ||
96178eeb VK |
951 | /** |
952 | * HIGH_RR is the highest eDP panel refresh rate read from EDID | |
953 | * LOW_RR is the lowest eDP panel refresh rate found from EDID | |
954 | * parsing for same resolution. | |
955 | */ | |
956 | enum drrs_refresh_rate_type { | |
957 | DRRS_HIGH_RR, | |
958 | DRRS_LOW_RR, | |
959 | DRRS_MAX_RR, /* RR count */ | |
960 | }; | |
961 | ||
962 | enum drrs_support_type { | |
963 | DRRS_NOT_SUPPORTED = 0, | |
964 | STATIC_DRRS_SUPPORT = 1, | |
965 | SEAMLESS_DRRS_SUPPORT = 2 | |
439d7ac0 PB |
966 | }; |
967 | ||
2807cf69 | 968 | struct intel_dp; |
96178eeb VK |
969 | struct i915_drrs { |
970 | struct mutex mutex; | |
971 | struct delayed_work work; | |
972 | struct intel_dp *dp; | |
973 | unsigned busy_frontbuffer_bits; | |
974 | enum drrs_refresh_rate_type refresh_rate_type; | |
975 | enum drrs_support_type type; | |
976 | }; | |
977 | ||
a031d709 | 978 | struct i915_psr { |
f0355c4a | 979 | struct mutex lock; |
a031d709 RV |
980 | bool sink_support; |
981 | bool source_ok; | |
2807cf69 | 982 | struct intel_dp *enabled; |
7c8f8a70 RV |
983 | bool active; |
984 | struct delayed_work work; | |
9ca15301 | 985 | unsigned busy_frontbuffer_bits; |
474d1ec4 SJ |
986 | bool psr2_support; |
987 | bool aux_frame_sync; | |
60e5ffe3 | 988 | bool link_standby; |
3f51e471 | 989 | }; |
5c3fe8b0 | 990 | |
3bad0781 | 991 | enum intel_pch { |
f0350830 | 992 | PCH_NONE = 0, /* No PCH present */ |
3bad0781 ZW |
993 | PCH_IBX, /* Ibexpeak PCH */ |
994 | PCH_CPT, /* Cougarpoint PCH */ | |
eb877ebf | 995 | PCH_LPT, /* Lynxpoint PCH */ |
e7e7ea20 | 996 | PCH_SPT, /* Sunrisepoint PCH */ |
40c7ead9 | 997 | PCH_NOP, |
3bad0781 ZW |
998 | }; |
999 | ||
988d6ee8 PZ |
1000 | enum intel_sbi_destination { |
1001 | SBI_ICLK, | |
1002 | SBI_MPHY, | |
1003 | }; | |
1004 | ||
b690e96c | 1005 | #define QUIRK_PIPEA_FORCE (1<<0) |
435793df | 1006 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
4dca20ef | 1007 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
9c72cc6f | 1008 | #define QUIRK_BACKLIGHT_PRESENT (1<<3) |
b6b5d049 | 1009 | #define QUIRK_PIPEB_FORCE (1<<4) |
656bfa3a | 1010 | #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) |
b690e96c | 1011 | |
8be48d92 | 1012 | struct intel_fbdev; |
1630fe75 | 1013 | struct intel_fbc_work; |
38651674 | 1014 | |
c2b9152f DV |
1015 | struct intel_gmbus { |
1016 | struct i2c_adapter adapter; | |
3e4d44e0 | 1017 | #define GMBUS_FORCE_BIT_RETRY (1U << 31) |
f2ce9faf | 1018 | u32 force_bit; |
c2b9152f | 1019 | u32 reg0; |
f0f59a00 | 1020 | i915_reg_t gpio_reg; |
c167a6fc | 1021 | struct i2c_algo_bit_data bit_algo; |
c2b9152f DV |
1022 | struct drm_i915_private *dev_priv; |
1023 | }; | |
1024 | ||
f4c956ad | 1025 | struct i915_suspend_saved_registers { |
e948e994 | 1026 | u32 saveDSPARB; |
ba8bbcf6 | 1027 | u32 saveLVDS; |
585fb111 JB |
1028 | u32 savePP_ON_DELAYS; |
1029 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
1030 | u32 savePP_ON; |
1031 | u32 savePP_OFF; | |
1032 | u32 savePP_CONTROL; | |
585fb111 | 1033 | u32 savePP_DIVISOR; |
ba8bbcf6 | 1034 | u32 saveFBC_CONTROL; |
1f84e550 | 1035 | u32 saveCACHE_MODE_0; |
1f84e550 | 1036 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
1037 | u32 saveSWF0[16]; |
1038 | u32 saveSWF1[16]; | |
85fa792b | 1039 | u32 saveSWF3[3]; |
4b9de737 | 1040 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
cda2bb78 | 1041 | u32 savePCH_PORT_HOTPLUG; |
9f49c376 | 1042 | u16 saveGCDGMBUS; |
f4c956ad | 1043 | }; |
c85aa885 | 1044 | |
ddeea5b0 ID |
1045 | struct vlv_s0ix_state { |
1046 | /* GAM */ | |
1047 | u32 wr_watermark; | |
1048 | u32 gfx_prio_ctrl; | |
1049 | u32 arb_mode; | |
1050 | u32 gfx_pend_tlb0; | |
1051 | u32 gfx_pend_tlb1; | |
1052 | u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; | |
1053 | u32 media_max_req_count; | |
1054 | u32 gfx_max_req_count; | |
1055 | u32 render_hwsp; | |
1056 | u32 ecochk; | |
1057 | u32 bsd_hwsp; | |
1058 | u32 blt_hwsp; | |
1059 | u32 tlb_rd_addr; | |
1060 | ||
1061 | /* MBC */ | |
1062 | u32 g3dctl; | |
1063 | u32 gsckgctl; | |
1064 | u32 mbctl; | |
1065 | ||
1066 | /* GCP */ | |
1067 | u32 ucgctl1; | |
1068 | u32 ucgctl3; | |
1069 | u32 rcgctl1; | |
1070 | u32 rcgctl2; | |
1071 | u32 rstctl; | |
1072 | u32 misccpctl; | |
1073 | ||
1074 | /* GPM */ | |
1075 | u32 gfxpause; | |
1076 | u32 rpdeuhwtc; | |
1077 | u32 rpdeuc; | |
1078 | u32 ecobus; | |
1079 | u32 pwrdwnupctl; | |
1080 | u32 rp_down_timeout; | |
1081 | u32 rp_deucsw; | |
1082 | u32 rcubmabdtmr; | |
1083 | u32 rcedata; | |
1084 | u32 spare2gh; | |
1085 | ||
1086 | /* Display 1 CZ domain */ | |
1087 | u32 gt_imr; | |
1088 | u32 gt_ier; | |
1089 | u32 pm_imr; | |
1090 | u32 pm_ier; | |
1091 | u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; | |
1092 | ||
1093 | /* GT SA CZ domain */ | |
1094 | u32 tilectl; | |
1095 | u32 gt_fifoctl; | |
1096 | u32 gtlc_wake_ctrl; | |
1097 | u32 gtlc_survive; | |
1098 | u32 pmwgicz; | |
1099 | ||
1100 | /* Display 2 CZ domain */ | |
1101 | u32 gu_ctl0; | |
1102 | u32 gu_ctl1; | |
9c25210f | 1103 | u32 pcbr; |
ddeea5b0 ID |
1104 | u32 clock_gate_dis2; |
1105 | }; | |
1106 | ||
bf225f20 CW |
1107 | struct intel_rps_ei { |
1108 | u32 cz_clock; | |
1109 | u32 render_c0; | |
1110 | u32 media_c0; | |
31685c25 D |
1111 | }; |
1112 | ||
c85aa885 | 1113 | struct intel_gen6_power_mgmt { |
d4d70aa5 ID |
1114 | /* |
1115 | * work, interrupts_enabled and pm_iir are protected by | |
1116 | * dev_priv->irq_lock | |
1117 | */ | |
c85aa885 | 1118 | struct work_struct work; |
d4d70aa5 | 1119 | bool interrupts_enabled; |
c85aa885 | 1120 | u32 pm_iir; |
59cdb63d | 1121 | |
b39fb297 BW |
1122 | /* Frequencies are stored in potentially platform dependent multiples. |
1123 | * In other words, *_freq needs to be multiplied by X to be interesting. | |
1124 | * Soft limits are those which are used for the dynamic reclocking done | |
1125 | * by the driver (raise frequencies under heavy loads, and lower for | |
1126 | * lighter loads). Hard limits are those imposed by the hardware. | |
1127 | * | |
1128 | * A distinction is made for overclocking, which is never enabled by | |
1129 | * default, and is considered to be above the hard limit if it's | |
1130 | * possible at all. | |
1131 | */ | |
1132 | u8 cur_freq; /* Current frequency (cached, may not == HW) */ | |
1133 | u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ | |
1134 | u8 max_freq_softlimit; /* Max frequency permitted by the driver */ | |
1135 | u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ | |
1136 | u8 min_freq; /* AKA RPn. Minimum frequency */ | |
aed242ff | 1137 | u8 idle_freq; /* Frequency to request when we are idle */ |
b39fb297 BW |
1138 | u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ |
1139 | u8 rp1_freq; /* "less than" RP0 power/freqency */ | |
1140 | u8 rp0_freq; /* Non-overclocked max frequency. */ | |
c30fec65 | 1141 | u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */ |
1a01ab3b | 1142 | |
8fb55197 CW |
1143 | u8 up_threshold; /* Current %busy required to uplock */ |
1144 | u8 down_threshold; /* Current %busy required to downclock */ | |
1145 | ||
dd75fdc8 CW |
1146 | int last_adj; |
1147 | enum { LOW_POWER, BETWEEN, HIGH_POWER } power; | |
1148 | ||
8d3afd7d CW |
1149 | spinlock_t client_lock; |
1150 | struct list_head clients; | |
1151 | bool client_boost; | |
1152 | ||
c0951f0c | 1153 | bool enabled; |
1a01ab3b | 1154 | struct delayed_work delayed_resume_work; |
1854d5ca | 1155 | unsigned boosts; |
4fc688ce | 1156 | |
2e1b8730 | 1157 | struct intel_rps_client semaphores, mmioflips; |
a6f766f3 | 1158 | |
bf225f20 CW |
1159 | /* manual wa residency calculations */ |
1160 | struct intel_rps_ei up_ei, down_ei; | |
1161 | ||
4fc688ce JB |
1162 | /* |
1163 | * Protects RPS/RC6 register access and PCU communication. | |
8d3afd7d CW |
1164 | * Must be taken after struct_mutex if nested. Note that |
1165 | * this lock may be held for long periods of time when | |
1166 | * talking to hw - so only take it when talking to hw! | |
4fc688ce JB |
1167 | */ |
1168 | struct mutex hw_lock; | |
c85aa885 DV |
1169 | }; |
1170 | ||
1a240d4d DV |
1171 | /* defined intel_pm.c */ |
1172 | extern spinlock_t mchdev_lock; | |
1173 | ||
c85aa885 DV |
1174 | struct intel_ilk_power_mgmt { |
1175 | u8 cur_delay; | |
1176 | u8 min_delay; | |
1177 | u8 max_delay; | |
1178 | u8 fmax; | |
1179 | u8 fstart; | |
1180 | ||
1181 | u64 last_count1; | |
1182 | unsigned long last_time1; | |
1183 | unsigned long chipset_power; | |
1184 | u64 last_count2; | |
5ed0bdf2 | 1185 | u64 last_time2; |
c85aa885 DV |
1186 | unsigned long gfx_power; |
1187 | u8 corr; | |
1188 | ||
1189 | int c_m; | |
1190 | int r_t; | |
1191 | }; | |
1192 | ||
c6cb582e ID |
1193 | struct drm_i915_private; |
1194 | struct i915_power_well; | |
1195 | ||
1196 | struct i915_power_well_ops { | |
1197 | /* | |
1198 | * Synchronize the well's hw state to match the current sw state, for | |
1199 | * example enable/disable it based on the current refcount. Called | |
1200 | * during driver init and resume time, possibly after first calling | |
1201 | * the enable/disable handlers. | |
1202 | */ | |
1203 | void (*sync_hw)(struct drm_i915_private *dev_priv, | |
1204 | struct i915_power_well *power_well); | |
1205 | /* | |
1206 | * Enable the well and resources that depend on it (for example | |
1207 | * interrupts located on the well). Called after the 0->1 refcount | |
1208 | * transition. | |
1209 | */ | |
1210 | void (*enable)(struct drm_i915_private *dev_priv, | |
1211 | struct i915_power_well *power_well); | |
1212 | /* | |
1213 | * Disable the well and resources that depend on it. Called after | |
1214 | * the 1->0 refcount transition. | |
1215 | */ | |
1216 | void (*disable)(struct drm_i915_private *dev_priv, | |
1217 | struct i915_power_well *power_well); | |
1218 | /* Returns the hw enabled state. */ | |
1219 | bool (*is_enabled)(struct drm_i915_private *dev_priv, | |
1220 | struct i915_power_well *power_well); | |
1221 | }; | |
1222 | ||
a38911a3 WX |
1223 | /* Power well structure for haswell */ |
1224 | struct i915_power_well { | |
c1ca727f | 1225 | const char *name; |
6f3ef5dd | 1226 | bool always_on; |
a38911a3 WX |
1227 | /* power well enable/disable usage count */ |
1228 | int count; | |
bfafe93a ID |
1229 | /* cached hw enabled state */ |
1230 | bool hw_enabled; | |
c1ca727f | 1231 | unsigned long domains; |
77961eb9 | 1232 | unsigned long data; |
c6cb582e | 1233 | const struct i915_power_well_ops *ops; |
a38911a3 WX |
1234 | }; |
1235 | ||
83c00f55 | 1236 | struct i915_power_domains { |
baa70707 ID |
1237 | /* |
1238 | * Power wells needed for initialization at driver init and suspend | |
1239 | * time are on. They are kept on until after the first modeset. | |
1240 | */ | |
1241 | bool init_power_on; | |
0d116a29 | 1242 | bool initializing; |
c1ca727f | 1243 | int power_well_count; |
baa70707 | 1244 | |
83c00f55 | 1245 | struct mutex lock; |
1da51581 | 1246 | int domain_use_count[POWER_DOMAIN_NUM]; |
c1ca727f | 1247 | struct i915_power_well *power_wells; |
83c00f55 ID |
1248 | }; |
1249 | ||
35a85ac6 | 1250 | #define MAX_L3_SLICES 2 |
a4da4fa4 | 1251 | struct intel_l3_parity { |
35a85ac6 | 1252 | u32 *remap_info[MAX_L3_SLICES]; |
a4da4fa4 | 1253 | struct work_struct error_work; |
35a85ac6 | 1254 | int which_slice; |
a4da4fa4 DV |
1255 | }; |
1256 | ||
4b5aed62 | 1257 | struct i915_gem_mm { |
4b5aed62 DV |
1258 | /** Memory allocator for GTT stolen memory */ |
1259 | struct drm_mm stolen; | |
92e97d2f PZ |
1260 | /** Protects the usage of the GTT stolen memory allocator. This is |
1261 | * always the inner lock when overlapping with struct_mutex. */ | |
1262 | struct mutex stolen_lock; | |
1263 | ||
4b5aed62 DV |
1264 | /** List of all objects in gtt_space. Used to restore gtt |
1265 | * mappings on resume */ | |
1266 | struct list_head bound_list; | |
1267 | /** | |
1268 | * List of objects which are not bound to the GTT (thus | |
1269 | * are idle and not used by the GPU) but still have | |
1270 | * (presumably uncached) pages still attached. | |
1271 | */ | |
1272 | struct list_head unbound_list; | |
1273 | ||
1274 | /** Usable portion of the GTT for GEM */ | |
1275 | unsigned long stolen_base; /* limited to low memory (32-bit) */ | |
1276 | ||
4b5aed62 DV |
1277 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
1278 | struct i915_hw_ppgtt *aliasing_ppgtt; | |
1279 | ||
2cfcd32a | 1280 | struct notifier_block oom_notifier; |
e87666b5 | 1281 | struct notifier_block vmap_notifier; |
ceabbba5 | 1282 | struct shrinker shrinker; |
4b5aed62 DV |
1283 | bool shrinker_no_lock_stealing; |
1284 | ||
4b5aed62 DV |
1285 | /** LRU list of objects with fence regs on them. */ |
1286 | struct list_head fence_list; | |
1287 | ||
1288 | /** | |
1289 | * We leave the user IRQ off as much as possible, | |
1290 | * but this means that requests will finish and never | |
1291 | * be retired once the system goes idle. Set a timer to | |
1292 | * fire periodically while the ring is running. When it | |
1293 | * fires, go retire requests. | |
1294 | */ | |
1295 | struct delayed_work retire_work; | |
1296 | ||
b29c19b6 CW |
1297 | /** |
1298 | * When we detect an idle GPU, we want to turn on | |
1299 | * powersaving features. So once we see that there | |
1300 | * are no more requests outstanding and no more | |
1301 | * arrive within a small period of time, we fire | |
1302 | * off the idle_work. | |
1303 | */ | |
1304 | struct delayed_work idle_work; | |
1305 | ||
4b5aed62 DV |
1306 | /** |
1307 | * Are we in a non-interruptible section of code like | |
1308 | * modesetting? | |
1309 | */ | |
1310 | bool interruptible; | |
1311 | ||
f62a0076 CW |
1312 | /** |
1313 | * Is the GPU currently considered idle, or busy executing userspace | |
1314 | * requests? Whilst idle, we attempt to power down the hardware and | |
1315 | * display clocks. In order to reduce the effect on performance, there | |
1316 | * is a slight delay before we do so. | |
1317 | */ | |
1318 | bool busy; | |
1319 | ||
bdf1e7e3 | 1320 | /* the indicator for dispatch video commands on two BSD rings */ |
de1add36 | 1321 | unsigned int bsd_ring_dispatch_index; |
bdf1e7e3 | 1322 | |
4b5aed62 DV |
1323 | /** Bit 6 swizzling required for X tiling */ |
1324 | uint32_t bit_6_swizzle_x; | |
1325 | /** Bit 6 swizzling required for Y tiling */ | |
1326 | uint32_t bit_6_swizzle_y; | |
1327 | ||
4b5aed62 | 1328 | /* accounting, useful for userland debugging */ |
c20e8355 | 1329 | spinlock_t object_stat_lock; |
4b5aed62 DV |
1330 | size_t object_memory; |
1331 | u32 object_count; | |
1332 | }; | |
1333 | ||
edc3d884 | 1334 | struct drm_i915_error_state_buf { |
0a4cd7c8 | 1335 | struct drm_i915_private *i915; |
edc3d884 MK |
1336 | unsigned bytes; |
1337 | unsigned size; | |
1338 | int err; | |
1339 | u8 *buf; | |
1340 | loff_t start; | |
1341 | loff_t pos; | |
1342 | }; | |
1343 | ||
fc16b48b MK |
1344 | struct i915_error_state_file_priv { |
1345 | struct drm_device *dev; | |
1346 | struct drm_i915_error_state *error; | |
1347 | }; | |
1348 | ||
99584db3 DV |
1349 | struct i915_gpu_error { |
1350 | /* For hangcheck timer */ | |
1351 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ | |
1352 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) | |
be62acb4 MK |
1353 | /* Hang gpu twice in this window and your context gets banned */ |
1354 | #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) | |
1355 | ||
737b1506 CW |
1356 | struct workqueue_struct *hangcheck_wq; |
1357 | struct delayed_work hangcheck_work; | |
99584db3 DV |
1358 | |
1359 | /* For reset and error_state handling. */ | |
1360 | spinlock_t lock; | |
1361 | /* Protected by the above dev->gpu_error.lock. */ | |
1362 | struct drm_i915_error_state *first_error; | |
094f9a54 CW |
1363 | |
1364 | unsigned long missed_irq_rings; | |
1365 | ||
1f83fee0 | 1366 | /** |
2ac0f450 | 1367 | * State variable controlling the reset flow and count |
1f83fee0 | 1368 | * |
2ac0f450 MK |
1369 | * This is a counter which gets incremented when reset is triggered, |
1370 | * and again when reset has been handled. So odd values (lowest bit set) | |
1371 | * means that reset is in progress and even values that | |
1372 | * (reset_counter >> 1):th reset was successfully completed. | |
1373 | * | |
1374 | * If reset is not completed succesfully, the I915_WEDGE bit is | |
1375 | * set meaning that hardware is terminally sour and there is no | |
1376 | * recovery. All waiters on the reset_queue will be woken when | |
1377 | * that happens. | |
1378 | * | |
1379 | * This counter is used by the wait_seqno code to notice that reset | |
1380 | * event happened and it needs to restart the entire ioctl (since most | |
1381 | * likely the seqno it waited for won't ever signal anytime soon). | |
f69061be DV |
1382 | * |
1383 | * This is important for lock-free wait paths, where no contended lock | |
1384 | * naturally enforces the correct ordering between the bail-out of the | |
1385 | * waiter and the gpu reset work code. | |
1f83fee0 DV |
1386 | */ |
1387 | atomic_t reset_counter; | |
1388 | ||
1f83fee0 | 1389 | #define I915_RESET_IN_PROGRESS_FLAG 1 |
2ac0f450 | 1390 | #define I915_WEDGED (1 << 31) |
1f83fee0 DV |
1391 | |
1392 | /** | |
1393 | * Waitqueue to signal when the reset has completed. Used by clients | |
1394 | * that wait for dev_priv->mm.wedged to settle. | |
1395 | */ | |
1396 | wait_queue_head_t reset_queue; | |
33196ded | 1397 | |
88b4aa87 MK |
1398 | /* Userspace knobs for gpu hang simulation; |
1399 | * combines both a ring mask, and extra flags | |
1400 | */ | |
1401 | u32 stop_rings; | |
1402 | #define I915_STOP_RING_ALLOW_BAN (1 << 31) | |
1403 | #define I915_STOP_RING_ALLOW_WARN (1 << 30) | |
094f9a54 CW |
1404 | |
1405 | /* For missed irq/seqno simulation. */ | |
1406 | unsigned int test_irq_rings; | |
99584db3 DV |
1407 | }; |
1408 | ||
b8efb17b ZR |
1409 | enum modeset_restore { |
1410 | MODESET_ON_LID_OPEN, | |
1411 | MODESET_DONE, | |
1412 | MODESET_SUSPENDED, | |
1413 | }; | |
1414 | ||
500ea70d RV |
1415 | #define DP_AUX_A 0x40 |
1416 | #define DP_AUX_B 0x10 | |
1417 | #define DP_AUX_C 0x20 | |
1418 | #define DP_AUX_D 0x30 | |
1419 | ||
11c1b657 XZ |
1420 | #define DDC_PIN_B 0x05 |
1421 | #define DDC_PIN_C 0x04 | |
1422 | #define DDC_PIN_D 0x06 | |
1423 | ||
6acab15a | 1424 | struct ddi_vbt_port_info { |
ce4dd49e DL |
1425 | /* |
1426 | * This is an index in the HDMI/DVI DDI buffer translation table. | |
1427 | * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't | |
1428 | * populate this field. | |
1429 | */ | |
1430 | #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff | |
6acab15a | 1431 | uint8_t hdmi_level_shift; |
311a2094 PZ |
1432 | |
1433 | uint8_t supports_dvi:1; | |
1434 | uint8_t supports_hdmi:1; | |
1435 | uint8_t supports_dp:1; | |
500ea70d RV |
1436 | |
1437 | uint8_t alternate_aux_channel; | |
11c1b657 | 1438 | uint8_t alternate_ddc_pin; |
75067dde AK |
1439 | |
1440 | uint8_t dp_boost_level; | |
1441 | uint8_t hdmi_boost_level; | |
6acab15a PZ |
1442 | }; |
1443 | ||
bfd7ebda RV |
1444 | enum psr_lines_to_wait { |
1445 | PSR_0_LINES_TO_WAIT = 0, | |
1446 | PSR_1_LINE_TO_WAIT, | |
1447 | PSR_4_LINES_TO_WAIT, | |
1448 | PSR_8_LINES_TO_WAIT | |
83a7280e PB |
1449 | }; |
1450 | ||
41aa3448 RV |
1451 | struct intel_vbt_data { |
1452 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ | |
1453 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
1454 | ||
1455 | /* Feature bits */ | |
1456 | unsigned int int_tv_support:1; | |
1457 | unsigned int lvds_dither:1; | |
1458 | unsigned int lvds_vbt:1; | |
1459 | unsigned int int_crt_support:1; | |
1460 | unsigned int lvds_use_ssc:1; | |
1461 | unsigned int display_clock_mode:1; | |
1462 | unsigned int fdi_rx_polarity_inverted:1; | |
3e845c7a | 1463 | unsigned int panel_type:4; |
41aa3448 RV |
1464 | int lvds_ssc_freq; |
1465 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ | |
1466 | ||
83a7280e PB |
1467 | enum drrs_support_type drrs_type; |
1468 | ||
6aa23e65 JN |
1469 | struct { |
1470 | int rate; | |
1471 | int lanes; | |
1472 | int preemphasis; | |
1473 | int vswing; | |
06411f08 | 1474 | bool low_vswing; |
6aa23e65 JN |
1475 | bool initialized; |
1476 | bool support; | |
1477 | int bpp; | |
1478 | struct edp_power_seq pps; | |
1479 | } edp; | |
41aa3448 | 1480 | |
bfd7ebda RV |
1481 | struct { |
1482 | bool full_link; | |
1483 | bool require_aux_wakeup; | |
1484 | int idle_frames; | |
1485 | enum psr_lines_to_wait lines_to_wait; | |
1486 | int tp1_wakeup_time; | |
1487 | int tp2_tp3_wakeup_time; | |
1488 | } psr; | |
1489 | ||
f00076d2 JN |
1490 | struct { |
1491 | u16 pwm_freq_hz; | |
39fbc9c8 | 1492 | bool present; |
f00076d2 | 1493 | bool active_low_pwm; |
1de6068e | 1494 | u8 min_brightness; /* min_brightness/255 of max */ |
9a41e17d | 1495 | enum intel_backlight_type type; |
f00076d2 JN |
1496 | } backlight; |
1497 | ||
d17c5443 SK |
1498 | /* MIPI DSI */ |
1499 | struct { | |
1500 | u16 panel_id; | |
d3b542fc SK |
1501 | struct mipi_config *config; |
1502 | struct mipi_pps_data *pps; | |
1503 | u8 seq_version; | |
1504 | u32 size; | |
1505 | u8 *data; | |
8d3ed2f3 | 1506 | const u8 *sequence[MIPI_SEQ_MAX]; |
d17c5443 SK |
1507 | } dsi; |
1508 | ||
41aa3448 RV |
1509 | int crt_ddc_pin; |
1510 | ||
1511 | int child_dev_num; | |
768f69c9 | 1512 | union child_device_config *child_dev; |
6acab15a PZ |
1513 | |
1514 | struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; | |
9d6c875d | 1515 | struct sdvo_device_mapping sdvo_mappings[2]; |
41aa3448 RV |
1516 | }; |
1517 | ||
77c122bc VS |
1518 | enum intel_ddb_partitioning { |
1519 | INTEL_DDB_PART_1_2, | |
1520 | INTEL_DDB_PART_5_6, /* IVB+ */ | |
1521 | }; | |
1522 | ||
1fd527cc VS |
1523 | struct intel_wm_level { |
1524 | bool enable; | |
1525 | uint32_t pri_val; | |
1526 | uint32_t spr_val; | |
1527 | uint32_t cur_val; | |
1528 | uint32_t fbc_val; | |
1529 | }; | |
1530 | ||
820c1980 | 1531 | struct ilk_wm_values { |
609cedef VS |
1532 | uint32_t wm_pipe[3]; |
1533 | uint32_t wm_lp[3]; | |
1534 | uint32_t wm_lp_spr[3]; | |
1535 | uint32_t wm_linetime[3]; | |
1536 | bool enable_fbc_wm; | |
1537 | enum intel_ddb_partitioning partitioning; | |
1538 | }; | |
1539 | ||
262cd2e1 VS |
1540 | struct vlv_pipe_wm { |
1541 | uint16_t primary; | |
1542 | uint16_t sprite[2]; | |
1543 | uint8_t cursor; | |
1544 | }; | |
ae80152d | 1545 | |
262cd2e1 VS |
1546 | struct vlv_sr_wm { |
1547 | uint16_t plane; | |
1548 | uint8_t cursor; | |
1549 | }; | |
ae80152d | 1550 | |
262cd2e1 VS |
1551 | struct vlv_wm_values { |
1552 | struct vlv_pipe_wm pipe[3]; | |
1553 | struct vlv_sr_wm sr; | |
0018fda1 VS |
1554 | struct { |
1555 | uint8_t cursor; | |
1556 | uint8_t sprite[2]; | |
1557 | uint8_t primary; | |
1558 | } ddl[3]; | |
6eb1a681 VS |
1559 | uint8_t level; |
1560 | bool cxsr; | |
0018fda1 VS |
1561 | }; |
1562 | ||
c193924e | 1563 | struct skl_ddb_entry { |
16160e3d | 1564 | uint16_t start, end; /* in number of blocks, 'end' is exclusive */ |
c193924e DL |
1565 | }; |
1566 | ||
1567 | static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry) | |
1568 | { | |
16160e3d | 1569 | return entry->end - entry->start; |
c193924e DL |
1570 | } |
1571 | ||
08db6652 DL |
1572 | static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, |
1573 | const struct skl_ddb_entry *e2) | |
1574 | { | |
1575 | if (e1->start == e2->start && e1->end == e2->end) | |
1576 | return true; | |
1577 | ||
1578 | return false; | |
1579 | } | |
1580 | ||
c193924e | 1581 | struct skl_ddb_allocation { |
34bb56af | 1582 | struct skl_ddb_entry pipe[I915_MAX_PIPES]; |
2cd601c6 | 1583 | struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */ |
4969d33e | 1584 | struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; |
c193924e DL |
1585 | }; |
1586 | ||
2ac96d2a PB |
1587 | struct skl_wm_values { |
1588 | bool dirty[I915_MAX_PIPES]; | |
c193924e | 1589 | struct skl_ddb_allocation ddb; |
2ac96d2a PB |
1590 | uint32_t wm_linetime[I915_MAX_PIPES]; |
1591 | uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8]; | |
2ac96d2a | 1592 | uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES]; |
2ac96d2a PB |
1593 | }; |
1594 | ||
1595 | struct skl_wm_level { | |
1596 | bool plane_en[I915_MAX_PLANES]; | |
1597 | uint16_t plane_res_b[I915_MAX_PLANES]; | |
1598 | uint8_t plane_res_l[I915_MAX_PLANES]; | |
2ac96d2a PB |
1599 | }; |
1600 | ||
c67a470b | 1601 | /* |
765dab67 PZ |
1602 | * This struct helps tracking the state needed for runtime PM, which puts the |
1603 | * device in PCI D3 state. Notice that when this happens, nothing on the | |
1604 | * graphics device works, even register access, so we don't get interrupts nor | |
1605 | * anything else. | |
c67a470b | 1606 | * |
765dab67 PZ |
1607 | * Every piece of our code that needs to actually touch the hardware needs to |
1608 | * either call intel_runtime_pm_get or call intel_display_power_get with the | |
1609 | * appropriate power domain. | |
a8a8bd54 | 1610 | * |
765dab67 PZ |
1611 | * Our driver uses the autosuspend delay feature, which means we'll only really |
1612 | * suspend if we stay with zero refcount for a certain amount of time. The | |
f458ebbc | 1613 | * default value is currently very conservative (see intel_runtime_pm_enable), but |
765dab67 | 1614 | * it can be changed with the standard runtime PM files from sysfs. |
c67a470b PZ |
1615 | * |
1616 | * The irqs_disabled variable becomes true exactly after we disable the IRQs and | |
1617 | * goes back to false exactly before we reenable the IRQs. We use this variable | |
1618 | * to check if someone is trying to enable/disable IRQs while they're supposed | |
1619 | * to be disabled. This shouldn't happen and we'll print some error messages in | |
730488b2 | 1620 | * case it happens. |
c67a470b | 1621 | * |
765dab67 | 1622 | * For more, read the Documentation/power/runtime_pm.txt. |
c67a470b | 1623 | */ |
5d584b2e | 1624 | struct i915_runtime_pm { |
1f814dac | 1625 | atomic_t wakeref_count; |
2b19efeb | 1626 | atomic_t atomic_seq; |
5d584b2e | 1627 | bool suspended; |
2aeb7d3a | 1628 | bool irqs_enabled; |
c67a470b PZ |
1629 | }; |
1630 | ||
926321d5 DV |
1631 | enum intel_pipe_crc_source { |
1632 | INTEL_PIPE_CRC_SOURCE_NONE, | |
1633 | INTEL_PIPE_CRC_SOURCE_PLANE1, | |
1634 | INTEL_PIPE_CRC_SOURCE_PLANE2, | |
1635 | INTEL_PIPE_CRC_SOURCE_PF, | |
5b3a856b | 1636 | INTEL_PIPE_CRC_SOURCE_PIPE, |
3d099a05 DV |
1637 | /* TV/DP on pre-gen5/vlv can't use the pipe source. */ |
1638 | INTEL_PIPE_CRC_SOURCE_TV, | |
1639 | INTEL_PIPE_CRC_SOURCE_DP_B, | |
1640 | INTEL_PIPE_CRC_SOURCE_DP_C, | |
1641 | INTEL_PIPE_CRC_SOURCE_DP_D, | |
46a19188 | 1642 | INTEL_PIPE_CRC_SOURCE_AUTO, |
926321d5 DV |
1643 | INTEL_PIPE_CRC_SOURCE_MAX, |
1644 | }; | |
1645 | ||
8bf1e9f1 | 1646 | struct intel_pipe_crc_entry { |
ac2300d4 | 1647 | uint32_t frame; |
8bf1e9f1 SH |
1648 | uint32_t crc[5]; |
1649 | }; | |
1650 | ||
b2c88f5b | 1651 | #define INTEL_PIPE_CRC_ENTRIES_NR 128 |
8bf1e9f1 | 1652 | struct intel_pipe_crc { |
d538bbdf DL |
1653 | spinlock_t lock; |
1654 | bool opened; /* exclusive access to the result file */ | |
e5f75aca | 1655 | struct intel_pipe_crc_entry *entries; |
926321d5 | 1656 | enum intel_pipe_crc_source source; |
d538bbdf | 1657 | int head, tail; |
07144428 | 1658 | wait_queue_head_t wq; |
8bf1e9f1 SH |
1659 | }; |
1660 | ||
f99d7069 DV |
1661 | struct i915_frontbuffer_tracking { |
1662 | struct mutex lock; | |
1663 | ||
1664 | /* | |
1665 | * Tracking bits for delayed frontbuffer flushing du to gpu activity or | |
1666 | * scheduled flips. | |
1667 | */ | |
1668 | unsigned busy_bits; | |
1669 | unsigned flip_bits; | |
1670 | }; | |
1671 | ||
7225342a | 1672 | struct i915_wa_reg { |
f0f59a00 | 1673 | i915_reg_t addr; |
7225342a MK |
1674 | u32 value; |
1675 | /* bitmask representing WA bits */ | |
1676 | u32 mask; | |
1677 | }; | |
1678 | ||
33136b06 AS |
1679 | /* |
1680 | * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only | |
1681 | * allowing it for RCS as we don't foresee any requirement of having | |
1682 | * a whitelist for other engines. When it is really required for | |
1683 | * other engines then the limit need to be increased. | |
1684 | */ | |
1685 | #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS) | |
7225342a MK |
1686 | |
1687 | struct i915_workarounds { | |
1688 | struct i915_wa_reg reg[I915_MAX_WA_REGS]; | |
1689 | u32 count; | |
666796da | 1690 | u32 hw_whitelist_count[I915_NUM_ENGINES]; |
7225342a MK |
1691 | }; |
1692 | ||
cf9d2890 YZ |
1693 | struct i915_virtual_gpu { |
1694 | bool active; | |
1695 | }; | |
1696 | ||
5f19e2bf JH |
1697 | struct i915_execbuffer_params { |
1698 | struct drm_device *dev; | |
1699 | struct drm_file *file; | |
1700 | uint32_t dispatch_flags; | |
1701 | uint32_t args_batch_start_offset; | |
af98714e | 1702 | uint64_t batch_obj_vm_offset; |
4a570db5 | 1703 | struct intel_engine_cs *engine; |
5f19e2bf JH |
1704 | struct drm_i915_gem_object *batch_obj; |
1705 | struct intel_context *ctx; | |
6a6ae79a | 1706 | struct drm_i915_gem_request *request; |
5f19e2bf JH |
1707 | }; |
1708 | ||
aa363136 MR |
1709 | /* used in computing the new watermarks state */ |
1710 | struct intel_wm_config { | |
1711 | unsigned int num_pipes_active; | |
1712 | bool sprites_enabled; | |
1713 | bool sprites_scaled; | |
1714 | }; | |
1715 | ||
77fec556 | 1716 | struct drm_i915_private { |
f4c956ad | 1717 | struct drm_device *dev; |
efab6d8d | 1718 | struct kmem_cache *objects; |
e20d2ab7 | 1719 | struct kmem_cache *vmas; |
efab6d8d | 1720 | struct kmem_cache *requests; |
f4c956ad | 1721 | |
5c969aa7 | 1722 | const struct intel_device_info info; |
f4c956ad DV |
1723 | |
1724 | int relative_constants_mode; | |
1725 | ||
1726 | void __iomem *regs; | |
1727 | ||
907b28c5 | 1728 | struct intel_uncore uncore; |
f4c956ad | 1729 | |
cf9d2890 YZ |
1730 | struct i915_virtual_gpu vgpu; |
1731 | ||
33a732f4 AD |
1732 | struct intel_guc guc; |
1733 | ||
eb805623 DV |
1734 | struct intel_csr csr; |
1735 | ||
5ea6e5e3 | 1736 | struct intel_gmbus gmbus[GMBUS_NUM_PINS]; |
28c70f16 | 1737 | |
f4c956ad DV |
1738 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
1739 | * controller on different i2c buses. */ | |
1740 | struct mutex gmbus_mutex; | |
1741 | ||
1742 | /** | |
1743 | * Base address of the gmbus and gpio block. | |
1744 | */ | |
1745 | uint32_t gpio_mmio_base; | |
1746 | ||
b6fdd0f2 SS |
1747 | /* MMIO base address for MIPI regs */ |
1748 | uint32_t mipi_mmio_base; | |
1749 | ||
443a389f VS |
1750 | uint32_t psr_mmio_base; |
1751 | ||
28c70f16 DV |
1752 | wait_queue_head_t gmbus_wait_queue; |
1753 | ||
f4c956ad | 1754 | struct pci_dev *bridge_dev; |
666796da | 1755 | struct intel_engine_cs engine[I915_NUM_ENGINES]; |
3e78998a | 1756 | struct drm_i915_gem_object *semaphore_obj; |
f72b3435 | 1757 | uint32_t last_seqno, next_seqno; |
f4c956ad | 1758 | |
ba8286fa | 1759 | struct drm_dma_handle *status_page_dmah; |
f4c956ad DV |
1760 | struct resource mch_res; |
1761 | ||
f4c956ad DV |
1762 | /* protects the irq masks */ |
1763 | spinlock_t irq_lock; | |
1764 | ||
84c33a64 SG |
1765 | /* protects the mmio flip data */ |
1766 | spinlock_t mmio_flip_lock; | |
1767 | ||
f8b79e58 ID |
1768 | bool display_irqs_enabled; |
1769 | ||
9ee32fea DV |
1770 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
1771 | struct pm_qos_request pm_qos; | |
1772 | ||
a580516d VS |
1773 | /* Sideband mailbox protection */ |
1774 | struct mutex sb_lock; | |
f4c956ad DV |
1775 | |
1776 | /** Cached value of IMR to avoid reads in updating the bitfield */ | |
abd58f01 BW |
1777 | union { |
1778 | u32 irq_mask; | |
1779 | u32 de_irq_mask[I915_MAX_PIPES]; | |
1780 | }; | |
f4c956ad | 1781 | u32 gt_irq_mask; |
605cd25b | 1782 | u32 pm_irq_mask; |
a6706b45 | 1783 | u32 pm_rps_events; |
91d181dd | 1784 | u32 pipestat_irq_mask[I915_MAX_PIPES]; |
f4c956ad | 1785 | |
5fcece80 | 1786 | struct i915_hotplug hotplug; |
ab34a7e8 | 1787 | struct intel_fbc fbc; |
439d7ac0 | 1788 | struct i915_drrs drrs; |
f4c956ad | 1789 | struct intel_opregion opregion; |
41aa3448 | 1790 | struct intel_vbt_data vbt; |
f4c956ad | 1791 | |
d9ceb816 JB |
1792 | bool preserve_bios_swizzle; |
1793 | ||
f4c956ad DV |
1794 | /* overlay */ |
1795 | struct intel_overlay *overlay; | |
f4c956ad | 1796 | |
58c68779 | 1797 | /* backlight registers and fields in struct intel_panel */ |
07f11d49 | 1798 | struct mutex backlight_lock; |
31ad8ec6 | 1799 | |
f4c956ad | 1800 | /* LVDS info */ |
f4c956ad DV |
1801 | bool no_aux_handshake; |
1802 | ||
e39b999a VS |
1803 | /* protects panel power sequencer state */ |
1804 | struct mutex pps_mutex; | |
1805 | ||
f4c956ad | 1806 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
f4c956ad DV |
1807 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ |
1808 | ||
1809 | unsigned int fsb_freq, mem_freq, is_ddr3; | |
5d96d8af | 1810 | unsigned int skl_boot_cdclk; |
1a617b77 | 1811 | unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq; |
adafdc6f | 1812 | unsigned int max_dotclk_freq; |
e7dc33f3 | 1813 | unsigned int rawclk_freq; |
6bcda4f0 | 1814 | unsigned int hpll_freq; |
bfa7df01 | 1815 | unsigned int czclk_freq; |
f4c956ad | 1816 | |
645416f5 DV |
1817 | /** |
1818 | * wq - Driver workqueue for GEM. | |
1819 | * | |
1820 | * NOTE: Work items scheduled here are not allowed to grab any modeset | |
1821 | * locks, for otherwise the flushing done in the pageflip code will | |
1822 | * result in deadlocks. | |
1823 | */ | |
f4c956ad DV |
1824 | struct workqueue_struct *wq; |
1825 | ||
1826 | /* Display functions */ | |
1827 | struct drm_i915_display_funcs display; | |
1828 | ||
1829 | /* PCH chipset type */ | |
1830 | enum intel_pch pch_type; | |
17a303ec | 1831 | unsigned short pch_id; |
f4c956ad DV |
1832 | |
1833 | unsigned long quirks; | |
1834 | ||
b8efb17b ZR |
1835 | enum modeset_restore modeset_restore; |
1836 | struct mutex modeset_restore_lock; | |
e2c8b870 | 1837 | struct drm_atomic_state *modeset_restore_state; |
673a394b | 1838 | |
a7bbbd63 | 1839 | struct list_head vm_list; /* Global list of all address spaces */ |
62106b4f | 1840 | struct i915_ggtt ggtt; /* VM representing the global address space */ |
5d4545ae | 1841 | |
4b5aed62 | 1842 | struct i915_gem_mm mm; |
ad46cb53 CW |
1843 | DECLARE_HASHTABLE(mm_structs, 7); |
1844 | struct mutex mm_lock; | |
8781342d | 1845 | |
5d1808ec CW |
1846 | /* The hw wants to have a stable context identifier for the lifetime |
1847 | * of the context (for OA, PASID, faults, etc). This is limited | |
1848 | * in execlists to 21 bits. | |
1849 | */ | |
1850 | struct ida context_hw_ida; | |
1851 | #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */ | |
1852 | ||
8781342d DV |
1853 | /* Kernel Modesetting */ |
1854 | ||
76c4ac04 DL |
1855 | struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; |
1856 | struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; | |
6b95a207 KH |
1857 | wait_queue_head_t pending_flip_queue; |
1858 | ||
c4597872 DV |
1859 | #ifdef CONFIG_DEBUG_FS |
1860 | struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; | |
1861 | #endif | |
1862 | ||
565602d7 | 1863 | /* dpll and cdclk state is protected by connection_mutex */ |
e72f9fbf DV |
1864 | int num_shared_dpll; |
1865 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; | |
f9476a6c | 1866 | const struct intel_dpll_mgr *dpll_mgr; |
565602d7 | 1867 | |
fbf6d879 ML |
1868 | /* |
1869 | * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll. | |
1870 | * Must be global rather than per dpll, because on some platforms | |
1871 | * plls share registers. | |
1872 | */ | |
1873 | struct mutex dpll_lock; | |
1874 | ||
565602d7 ML |
1875 | unsigned int active_crtcs; |
1876 | unsigned int min_pixclk[I915_MAX_PIPES]; | |
1877 | ||
e4607fcf | 1878 | int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; |
ee7b9f93 | 1879 | |
7225342a | 1880 | struct i915_workarounds workarounds; |
888b5995 | 1881 | |
f99d7069 DV |
1882 | struct i915_frontbuffer_tracking fb_tracking; |
1883 | ||
652c393a | 1884 | u16 orig_clock; |
f97108d1 | 1885 | |
c4804411 | 1886 | bool mchbar_need_disable; |
f97108d1 | 1887 | |
a4da4fa4 DV |
1888 | struct intel_l3_parity l3_parity; |
1889 | ||
59124506 | 1890 | /* Cannot be determined by PCIID. You must always read a register. */ |
3accaf7e | 1891 | u32 edram_cap; |
59124506 | 1892 | |
c6a828d3 | 1893 | /* gen6+ rps state */ |
c85aa885 | 1894 | struct intel_gen6_power_mgmt rps; |
c6a828d3 | 1895 | |
20e4d407 DV |
1896 | /* ilk-only ips/rps state. Everything in here is protected by the global |
1897 | * mchdev_lock in intel_pm.c */ | |
c85aa885 | 1898 | struct intel_ilk_power_mgmt ips; |
b5e50c3f | 1899 | |
83c00f55 | 1900 | struct i915_power_domains power_domains; |
a38911a3 | 1901 | |
a031d709 | 1902 | struct i915_psr psr; |
3f51e471 | 1903 | |
99584db3 | 1904 | struct i915_gpu_error gpu_error; |
ae681d96 | 1905 | |
c9cddffc JB |
1906 | struct drm_i915_gem_object *vlv_pctx; |
1907 | ||
0695726e | 1908 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
8be48d92 DA |
1909 | /* list of fbdev register on this device */ |
1910 | struct intel_fbdev *fbdev; | |
82e3b8c1 | 1911 | struct work_struct fbdev_suspend_work; |
4520f53a | 1912 | #endif |
e953fd7b CW |
1913 | |
1914 | struct drm_property *broadcast_rgb_property; | |
3f43c48d | 1915 | struct drm_property *force_audio_property; |
e3689190 | 1916 | |
58fddc28 | 1917 | /* hda/i915 audio component */ |
51e1d83c | 1918 | struct i915_audio_component *audio_component; |
58fddc28 | 1919 | bool audio_component_registered; |
4a21ef7d LY |
1920 | /** |
1921 | * av_mutex - mutex for audio/video sync | |
1922 | * | |
1923 | */ | |
1924 | struct mutex av_mutex; | |
58fddc28 | 1925 | |
254f965c | 1926 | uint32_t hw_context_size; |
a33afea5 | 1927 | struct list_head context_list; |
f4c956ad | 1928 | |
3e68320e | 1929 | u32 fdi_rx_config; |
68d18ad7 | 1930 | |
c231775c | 1931 | /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */ |
70722468 | 1932 | u32 chv_phy_control; |
c231775c VS |
1933 | /* |
1934 | * Shadows for CHV DPLL_MD regs to keep the state | |
1935 | * checker somewhat working in the presence hardware | |
1936 | * crappiness (can't read out DPLL_MD for pipes B & C). | |
1937 | */ | |
1938 | u32 chv_dpll_md[I915_MAX_PIPES]; | |
adc7f04b | 1939 | u32 bxt_phy_grc; |
70722468 | 1940 | |
842f1c8b | 1941 | u32 suspend_count; |
bc87229f | 1942 | bool suspended_to_idle; |
f4c956ad | 1943 | struct i915_suspend_saved_registers regfile; |
ddeea5b0 | 1944 | struct vlv_s0ix_state vlv_s0ix_state; |
231f42a4 | 1945 | |
53615a5e VS |
1946 | struct { |
1947 | /* | |
1948 | * Raw watermark latency values: | |
1949 | * in 0.1us units for WM0, | |
1950 | * in 0.5us units for WM1+. | |
1951 | */ | |
1952 | /* primary */ | |
1953 | uint16_t pri_latency[5]; | |
1954 | /* sprite */ | |
1955 | uint16_t spr_latency[5]; | |
1956 | /* cursor */ | |
1957 | uint16_t cur_latency[5]; | |
2af30a5c PB |
1958 | /* |
1959 | * Raw watermark memory latency values | |
1960 | * for SKL for all 8 levels | |
1961 | * in 1us units. | |
1962 | */ | |
1963 | uint16_t skl_latency[8]; | |
609cedef | 1964 | |
aa363136 MR |
1965 | /* Committed wm config */ |
1966 | struct intel_wm_config config; | |
1967 | ||
2d41c0b5 PB |
1968 | /* |
1969 | * The skl_wm_values structure is a bit too big for stack | |
1970 | * allocation, so we keep the staging struct where we store | |
1971 | * intermediate results here instead. | |
1972 | */ | |
1973 | struct skl_wm_values skl_results; | |
1974 | ||
609cedef | 1975 | /* current hardware state */ |
2d41c0b5 PB |
1976 | union { |
1977 | struct ilk_wm_values hw; | |
1978 | struct skl_wm_values skl_hw; | |
0018fda1 | 1979 | struct vlv_wm_values vlv; |
2d41c0b5 | 1980 | }; |
58590c14 VS |
1981 | |
1982 | uint8_t max_level; | |
ed4a6a7c MR |
1983 | |
1984 | /* | |
1985 | * Should be held around atomic WM register writing; also | |
1986 | * protects * intel_crtc->wm.active and | |
1987 | * cstate->wm.need_postvbl_update. | |
1988 | */ | |
1989 | struct mutex wm_mutex; | |
53615a5e VS |
1990 | } wm; |
1991 | ||
8a187455 PZ |
1992 | struct i915_runtime_pm pm; |
1993 | ||
a83014d3 OM |
1994 | /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ |
1995 | struct { | |
5f19e2bf | 1996 | int (*execbuf_submit)(struct i915_execbuffer_params *params, |
f3dc74c0 | 1997 | struct drm_i915_gem_execbuffer2 *args, |
5f19e2bf | 1998 | struct list_head *vmas); |
117897f4 TU |
1999 | int (*init_engines)(struct drm_device *dev); |
2000 | void (*cleanup_engine)(struct intel_engine_cs *engine); | |
2001 | void (*stop_engine)(struct intel_engine_cs *engine); | |
a83014d3 OM |
2002 | } gt; |
2003 | ||
ed54c1a1 DG |
2004 | struct intel_context *kernel_context; |
2005 | ||
3be60de9 VS |
2006 | /* perform PHY state sanity checks? */ |
2007 | bool chv_phy_assert[2]; | |
2008 | ||
0bdf5a05 TI |
2009 | struct intel_encoder *dig_port_map[I915_MAX_PORTS]; |
2010 | ||
bdf1e7e3 DV |
2011 | /* |
2012 | * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch | |
2013 | * will be rejected. Instead look for a better place. | |
2014 | */ | |
77fec556 | 2015 | }; |
1da177e4 | 2016 | |
2c1792a1 CW |
2017 | static inline struct drm_i915_private *to_i915(const struct drm_device *dev) |
2018 | { | |
2019 | return dev->dev_private; | |
2020 | } | |
2021 | ||
888d0d42 ID |
2022 | static inline struct drm_i915_private *dev_to_i915(struct device *dev) |
2023 | { | |
2024 | return to_i915(dev_get_drvdata(dev)); | |
2025 | } | |
2026 | ||
33a732f4 AD |
2027 | static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc) |
2028 | { | |
2029 | return container_of(guc, struct drm_i915_private, guc); | |
2030 | } | |
2031 | ||
b4ac5afc DG |
2032 | /* Simple iterator over all initialised engines */ |
2033 | #define for_each_engine(engine__, dev_priv__) \ | |
2034 | for ((engine__) = &(dev_priv__)->engine[0]; \ | |
2035 | (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \ | |
2036 | (engine__)++) \ | |
2037 | for_each_if (intel_engine_initialized(engine__)) | |
b4519513 | 2038 | |
c3232b18 DG |
2039 | /* Iterator with engine_id */ |
2040 | #define for_each_engine_id(engine__, dev_priv__, id__) \ | |
2041 | for ((engine__) = &(dev_priv__)->engine[0], (id__) = 0; \ | |
2042 | (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \ | |
2043 | (engine__)++) \ | |
2044 | for_each_if (((id__) = (engine__)->id, \ | |
2045 | intel_engine_initialized(engine__))) | |
2046 | ||
2047 | /* Iterator over subset of engines selected by mask */ | |
ee4b6faf | 2048 | #define for_each_engine_masked(engine__, dev_priv__, mask__) \ |
b4ac5afc DG |
2049 | for ((engine__) = &(dev_priv__)->engine[0]; \ |
2050 | (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \ | |
2051 | (engine__)++) \ | |
2052 | for_each_if (((mask__) & intel_engine_flag(engine__)) && \ | |
2053 | intel_engine_initialized(engine__)) | |
ee4b6faf | 2054 | |
b1d7e4b4 WF |
2055 | enum hdmi_force_audio { |
2056 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ | |
2057 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ | |
2058 | HDMI_AUDIO_AUTO, /* trust EDID */ | |
2059 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ | |
2060 | }; | |
2061 | ||
190d6cd5 | 2062 | #define I915_GTT_OFFSET_NONE ((u32)-1) |
ed2f3452 | 2063 | |
37e680a1 | 2064 | struct drm_i915_gem_object_ops { |
de472664 CW |
2065 | unsigned int flags; |
2066 | #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1 | |
2067 | ||
37e680a1 CW |
2068 | /* Interface between the GEM object and its backing storage. |
2069 | * get_pages() is called once prior to the use of the associated set | |
2070 | * of pages before to binding them into the GTT, and put_pages() is | |
2071 | * called after we no longer need them. As we expect there to be | |
2072 | * associated cost with migrating pages between the backing storage | |
2073 | * and making them available for the GPU (e.g. clflush), we may hold | |
2074 | * onto the pages after they are no longer referenced by the GPU | |
2075 | * in case they may be used again shortly (for example migrating the | |
2076 | * pages to a different memory domain within the GTT). put_pages() | |
2077 | * will therefore most likely be called when the object itself is | |
2078 | * being released or under memory pressure (where we attempt to | |
2079 | * reap pages for the shrinker). | |
2080 | */ | |
2081 | int (*get_pages)(struct drm_i915_gem_object *); | |
2082 | void (*put_pages)(struct drm_i915_gem_object *); | |
de472664 | 2083 | |
5cc9ed4b CW |
2084 | int (*dmabuf_export)(struct drm_i915_gem_object *); |
2085 | void (*release)(struct drm_i915_gem_object *); | |
37e680a1 CW |
2086 | }; |
2087 | ||
a071fa00 DV |
2088 | /* |
2089 | * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is | |
d1b9d039 | 2090 | * considered to be the frontbuffer for the given plane interface-wise. This |
a071fa00 DV |
2091 | * doesn't mean that the hw necessarily already scans it out, but that any |
2092 | * rendering (by the cpu or gpu) will land in the frontbuffer eventually. | |
2093 | * | |
2094 | * We have one bit per pipe and per scanout plane type. | |
2095 | */ | |
d1b9d039 SAK |
2096 | #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5 |
2097 | #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8 | |
a071fa00 DV |
2098 | #define INTEL_FRONTBUFFER_BITS \ |
2099 | (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES) | |
2100 | #define INTEL_FRONTBUFFER_PRIMARY(pipe) \ | |
2101 | (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) | |
2102 | #define INTEL_FRONTBUFFER_CURSOR(pipe) \ | |
d1b9d039 SAK |
2103 | (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) |
2104 | #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \ | |
2105 | (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
a071fa00 | 2106 | #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ |
d1b9d039 | 2107 | (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) |
cc36513c | 2108 | #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ |
d1b9d039 | 2109 | (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) |
a071fa00 | 2110 | |
673a394b | 2111 | struct drm_i915_gem_object { |
c397b908 | 2112 | struct drm_gem_object base; |
673a394b | 2113 | |
37e680a1 CW |
2114 | const struct drm_i915_gem_object_ops *ops; |
2115 | ||
2f633156 BW |
2116 | /** List of VMAs backed by this object */ |
2117 | struct list_head vma_list; | |
2118 | ||
c1ad11fc CW |
2119 | /** Stolen memory for this object, instead of being backed by shmem. */ |
2120 | struct drm_mm_node *stolen; | |
35c20a60 | 2121 | struct list_head global_list; |
673a394b | 2122 | |
117897f4 | 2123 | struct list_head engine_list[I915_NUM_ENGINES]; |
b25cb2f8 BW |
2124 | /** Used in execbuf to temporarily hold a ref */ |
2125 | struct list_head obj_exec_link; | |
673a394b | 2126 | |
8d9d5744 | 2127 | struct list_head batch_pool_link; |
493018dc | 2128 | |
673a394b | 2129 | /** |
65ce3027 CW |
2130 | * This is set if the object is on the active lists (has pending |
2131 | * rendering and so a non-zero seqno), and is not set if it i s on | |
2132 | * inactive (ready to be unbound) list. | |
673a394b | 2133 | */ |
666796da | 2134 | unsigned int active:I915_NUM_ENGINES; |
673a394b EA |
2135 | |
2136 | /** | |
2137 | * This is set if the object has been written to since last bound | |
2138 | * to the GTT | |
2139 | */ | |
0206e353 | 2140 | unsigned int dirty:1; |
778c3544 DV |
2141 | |
2142 | /** | |
2143 | * Fence register bits (if any) for this object. Will be set | |
2144 | * as needed when mapped into the GTT. | |
2145 | * Protected by dev->struct_mutex. | |
778c3544 | 2146 | */ |
4b9de737 | 2147 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
778c3544 | 2148 | |
778c3544 DV |
2149 | /** |
2150 | * Advice: are the backing pages purgeable? | |
2151 | */ | |
0206e353 | 2152 | unsigned int madv:2; |
778c3544 | 2153 | |
778c3544 DV |
2154 | /** |
2155 | * Current tiling mode for the object. | |
2156 | */ | |
0206e353 | 2157 | unsigned int tiling_mode:2; |
5d82e3e6 CW |
2158 | /** |
2159 | * Whether the tiling parameters for the currently associated fence | |
2160 | * register have changed. Note that for the purposes of tracking | |
2161 | * tiling changes we also treat the unfenced register, the register | |
2162 | * slot that the object occupies whilst it executes a fenced | |
2163 | * command (such as BLT on gen2/3), as a "fence". | |
2164 | */ | |
2165 | unsigned int fence_dirty:1; | |
778c3544 | 2166 | |
75e9e915 DV |
2167 | /** |
2168 | * Is the object at the current location in the gtt mappable and | |
2169 | * fenceable? Used to avoid costly recalculations. | |
2170 | */ | |
0206e353 | 2171 | unsigned int map_and_fenceable:1; |
75e9e915 | 2172 | |
fb7d516a DV |
2173 | /** |
2174 | * Whether the current gtt mapping needs to be mappable (and isn't just | |
2175 | * mappable by accident). Track pin and fault separate for a more | |
2176 | * accurate mappable working set. | |
2177 | */ | |
0206e353 | 2178 | unsigned int fault_mappable:1; |
fb7d516a | 2179 | |
24f3a8cf AG |
2180 | /* |
2181 | * Is the object to be mapped as read-only to the GPU | |
2182 | * Only honoured if hardware has relevant pte bit | |
2183 | */ | |
2184 | unsigned long gt_ro:1; | |
651d794f | 2185 | unsigned int cache_level:3; |
0f71979a | 2186 | unsigned int cache_dirty:1; |
93dfb40c | 2187 | |
a071fa00 DV |
2188 | unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS; |
2189 | ||
8a0c39b1 TU |
2190 | unsigned int pin_display; |
2191 | ||
9da3da66 | 2192 | struct sg_table *pages; |
a5570178 | 2193 | int pages_pin_count; |
ee286370 CW |
2194 | struct get_page { |
2195 | struct scatterlist *sg; | |
2196 | int last; | |
2197 | } get_page; | |
0a798eb9 | 2198 | void *mapping; |
9a70cc2a | 2199 | |
b4716185 CW |
2200 | /** Breadcrumb of last rendering to the buffer. |
2201 | * There can only be one writer, but we allow for multiple readers. | |
2202 | * If there is a writer that necessarily implies that all other | |
2203 | * read requests are complete - but we may only be lazily clearing | |
2204 | * the read requests. A read request is naturally the most recent | |
2205 | * request on a ring, so we may have two different write and read | |
2206 | * requests on one ring where the write request is older than the | |
2207 | * read request. This allows for the CPU to read from an active | |
2208 | * buffer by only waiting for the write to complete. | |
2209 | * */ | |
666796da | 2210 | struct drm_i915_gem_request *last_read_req[I915_NUM_ENGINES]; |
97b2a6a1 | 2211 | struct drm_i915_gem_request *last_write_req; |
caea7476 | 2212 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
97b2a6a1 | 2213 | struct drm_i915_gem_request *last_fenced_req; |
673a394b | 2214 | |
778c3544 | 2215 | /** Current tiling stride for the object, if it's tiled. */ |
de151cf6 | 2216 | uint32_t stride; |
673a394b | 2217 | |
80075d49 DV |
2218 | /** References from framebuffers, locks out tiling changes. */ |
2219 | unsigned long framebuffer_references; | |
2220 | ||
280b713b | 2221 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 2222 | unsigned long *bit_17; |
280b713b | 2223 | |
5cc9ed4b | 2224 | union { |
6a2c4232 CW |
2225 | /** for phy allocated objects */ |
2226 | struct drm_dma_handle *phys_handle; | |
2227 | ||
5cc9ed4b CW |
2228 | struct i915_gem_userptr { |
2229 | uintptr_t ptr; | |
2230 | unsigned read_only :1; | |
2231 | unsigned workers :4; | |
2232 | #define I915_GEM_USERPTR_MAX_WORKERS 15 | |
2233 | ||
ad46cb53 CW |
2234 | struct i915_mm_struct *mm; |
2235 | struct i915_mmu_object *mmu_object; | |
5cc9ed4b CW |
2236 | struct work_struct *work; |
2237 | } userptr; | |
2238 | }; | |
2239 | }; | |
62b8b215 | 2240 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
23010e43 | 2241 | |
a071fa00 DV |
2242 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
2243 | struct drm_i915_gem_object *new, | |
2244 | unsigned frontbuffer_bits); | |
2245 | ||
673a394b EA |
2246 | /** |
2247 | * Request queue structure. | |
2248 | * | |
2249 | * The request queue allows us to note sequence numbers that have been emitted | |
2250 | * and may be associated with active buffers to be retired. | |
2251 | * | |
97b2a6a1 JH |
2252 | * By keeping this list, we can avoid having to do questionable sequence |
2253 | * number comparisons on buffer last_read|write_seqno. It also allows an | |
2254 | * emission time to be associated with the request for tracking how far ahead | |
2255 | * of the GPU the submission is. | |
b3a38998 NH |
2256 | * |
2257 | * The requests are reference counted, so upon creation they should have an | |
2258 | * initial reference taken using kref_init | |
673a394b EA |
2259 | */ |
2260 | struct drm_i915_gem_request { | |
abfe262a JH |
2261 | struct kref ref; |
2262 | ||
852835f3 | 2263 | /** On Which ring this request was generated */ |
efab6d8d | 2264 | struct drm_i915_private *i915; |
4a570db5 | 2265 | struct intel_engine_cs *engine; |
299259a3 | 2266 | unsigned reset_counter; |
852835f3 | 2267 | |
821485dc CW |
2268 | /** GEM sequence number associated with the previous request, |
2269 | * when the HWS breadcrumb is equal to this the GPU is processing | |
2270 | * this request. | |
2271 | */ | |
2272 | u32 previous_seqno; | |
2273 | ||
2274 | /** GEM sequence number associated with this request, | |
2275 | * when the HWS breadcrumb is equal or greater than this the GPU | |
2276 | * has finished processing this request. | |
2277 | */ | |
2278 | u32 seqno; | |
673a394b | 2279 | |
7d736f4f MK |
2280 | /** Position in the ringbuffer of the start of the request */ |
2281 | u32 head; | |
2282 | ||
72f95afa NH |
2283 | /** |
2284 | * Position in the ringbuffer of the start of the postfix. | |
2285 | * This is required to calculate the maximum available ringbuffer | |
2286 | * space without overwriting the postfix. | |
2287 | */ | |
2288 | u32 postfix; | |
2289 | ||
2290 | /** Position in the ringbuffer of the end of the whole request */ | |
a71d8d94 CW |
2291 | u32 tail; |
2292 | ||
0251a963 CW |
2293 | /** Preallocate space in the ringbuffer for the emitting the request */ |
2294 | u32 reserved_space; | |
2295 | ||
b3a38998 | 2296 | /** |
a8c6ecb3 | 2297 | * Context and ring buffer related to this request |
b3a38998 NH |
2298 | * Contexts are refcounted, so when this request is associated with a |
2299 | * context, we must increment the context's refcount, to guarantee that | |
2300 | * it persists while any request is linked to it. Requests themselves | |
2301 | * are also refcounted, so the request will only be freed when the last | |
2302 | * reference to it is dismissed, and the code in | |
2303 | * i915_gem_request_free() will then decrement the refcount on the | |
2304 | * context. | |
2305 | */ | |
273497e5 | 2306 | struct intel_context *ctx; |
98e1bd4a | 2307 | struct intel_ringbuffer *ringbuf; |
0e50e96b | 2308 | |
a16a4052 CW |
2309 | /** |
2310 | * Context related to the previous request. | |
2311 | * As the contexts are accessed by the hardware until the switch is | |
2312 | * completed to a new context, the hardware may still be writing | |
2313 | * to the context object after the breadcrumb is visible. We must | |
2314 | * not unpin/unbind/prune that object whilst still active and so | |
2315 | * we keep the previous context pinned until the following (this) | |
2316 | * request is retired. | |
2317 | */ | |
2318 | struct intel_context *previous_context; | |
2319 | ||
dc4be607 JH |
2320 | /** Batch buffer related to this request if any (used for |
2321 | error state dump only) */ | |
7d736f4f MK |
2322 | struct drm_i915_gem_object *batch_obj; |
2323 | ||
673a394b EA |
2324 | /** Time at which this request was emitted, in jiffies. */ |
2325 | unsigned long emitted_jiffies; | |
2326 | ||
b962442e | 2327 | /** global list entry for this request */ |
673a394b | 2328 | struct list_head list; |
b962442e | 2329 | |
f787a5f5 | 2330 | struct drm_i915_file_private *file_priv; |
b962442e EA |
2331 | /** file_priv list entry for this request */ |
2332 | struct list_head client_list; | |
67e2937b | 2333 | |
071c92de MK |
2334 | /** process identifier submitting this request */ |
2335 | struct pid *pid; | |
2336 | ||
6d3d8274 NH |
2337 | /** |
2338 | * The ELSP only accepts two elements at a time, so we queue | |
2339 | * context/tail pairs on a given queue (ring->execlist_queue) until the | |
2340 | * hardware is available. The queue serves a double purpose: we also use | |
2341 | * it to keep track of the up to 2 contexts currently in the hardware | |
2342 | * (usually one in execution and the other queued up by the GPU): We | |
2343 | * only remove elements from the head of the queue when the hardware | |
2344 | * informs us that an element has been completed. | |
2345 | * | |
2346 | * All accesses to the queue are mediated by a spinlock | |
2347 | * (ring->execlist_lock). | |
2348 | */ | |
2349 | ||
2350 | /** Execlist link in the submission queue.*/ | |
2351 | struct list_head execlist_link; | |
2352 | ||
2353 | /** Execlists no. of times this request has been sent to the ELSP */ | |
2354 | int elsp_submitted; | |
2355 | ||
a3d12761 TU |
2356 | /** Execlists context hardware id. */ |
2357 | unsigned ctx_hw_id; | |
673a394b EA |
2358 | }; |
2359 | ||
26827088 DG |
2360 | struct drm_i915_gem_request * __must_check |
2361 | i915_gem_request_alloc(struct intel_engine_cs *engine, | |
2362 | struct intel_context *ctx); | |
abfe262a | 2363 | void i915_gem_request_free(struct kref *req_ref); |
fcfa423c JH |
2364 | int i915_gem_request_add_to_client(struct drm_i915_gem_request *req, |
2365 | struct drm_file *file); | |
abfe262a | 2366 | |
b793a00a JH |
2367 | static inline uint32_t |
2368 | i915_gem_request_get_seqno(struct drm_i915_gem_request *req) | |
2369 | { | |
2370 | return req ? req->seqno : 0; | |
2371 | } | |
2372 | ||
2373 | static inline struct intel_engine_cs * | |
666796da | 2374 | i915_gem_request_get_engine(struct drm_i915_gem_request *req) |
b793a00a | 2375 | { |
4a570db5 | 2376 | return req ? req->engine : NULL; |
b793a00a JH |
2377 | } |
2378 | ||
b2cfe0ab | 2379 | static inline struct drm_i915_gem_request * |
abfe262a JH |
2380 | i915_gem_request_reference(struct drm_i915_gem_request *req) |
2381 | { | |
b2cfe0ab CW |
2382 | if (req) |
2383 | kref_get(&req->ref); | |
2384 | return req; | |
abfe262a JH |
2385 | } |
2386 | ||
2387 | static inline void | |
2388 | i915_gem_request_unreference(struct drm_i915_gem_request *req) | |
2389 | { | |
2390 | kref_put(&req->ref, i915_gem_request_free); | |
2391 | } | |
2392 | ||
2393 | static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst, | |
2394 | struct drm_i915_gem_request *src) | |
2395 | { | |
2396 | if (src) | |
2397 | i915_gem_request_reference(src); | |
2398 | ||
2399 | if (*pdst) | |
2400 | i915_gem_request_unreference(*pdst); | |
2401 | ||
2402 | *pdst = src; | |
2403 | } | |
2404 | ||
1b5a433a JH |
2405 | /* |
2406 | * XXX: i915_gem_request_completed should be here but currently needs the | |
2407 | * definition of i915_seqno_passed() which is below. It will be moved in | |
2408 | * a later patch when the call to i915_seqno_passed() is obsoleted... | |
2409 | */ | |
2410 | ||
351e3db2 BV |
2411 | /* |
2412 | * A command that requires special handling by the command parser. | |
2413 | */ | |
2414 | struct drm_i915_cmd_descriptor { | |
2415 | /* | |
2416 | * Flags describing how the command parser processes the command. | |
2417 | * | |
2418 | * CMD_DESC_FIXED: The command has a fixed length if this is set, | |
2419 | * a length mask if not set | |
2420 | * CMD_DESC_SKIP: The command is allowed but does not follow the | |
2421 | * standard length encoding for the opcode range in | |
2422 | * which it falls | |
2423 | * CMD_DESC_REJECT: The command is never allowed | |
2424 | * CMD_DESC_REGISTER: The command should be checked against the | |
2425 | * register whitelist for the appropriate ring | |
2426 | * CMD_DESC_MASTER: The command is allowed if the submitting process | |
2427 | * is the DRM master | |
2428 | */ | |
2429 | u32 flags; | |
2430 | #define CMD_DESC_FIXED (1<<0) | |
2431 | #define CMD_DESC_SKIP (1<<1) | |
2432 | #define CMD_DESC_REJECT (1<<2) | |
2433 | #define CMD_DESC_REGISTER (1<<3) | |
2434 | #define CMD_DESC_BITMASK (1<<4) | |
2435 | #define CMD_DESC_MASTER (1<<5) | |
2436 | ||
2437 | /* | |
2438 | * The command's unique identification bits and the bitmask to get them. | |
2439 | * This isn't strictly the opcode field as defined in the spec and may | |
2440 | * also include type, subtype, and/or subop fields. | |
2441 | */ | |
2442 | struct { | |
2443 | u32 value; | |
2444 | u32 mask; | |
2445 | } cmd; | |
2446 | ||
2447 | /* | |
2448 | * The command's length. The command is either fixed length (i.e. does | |
2449 | * not include a length field) or has a length field mask. The flag | |
2450 | * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has | |
2451 | * a length mask. All command entries in a command table must include | |
2452 | * length information. | |
2453 | */ | |
2454 | union { | |
2455 | u32 fixed; | |
2456 | u32 mask; | |
2457 | } length; | |
2458 | ||
2459 | /* | |
2460 | * Describes where to find a register address in the command to check | |
2461 | * against the ring's register whitelist. Only valid if flags has the | |
2462 | * CMD_DESC_REGISTER bit set. | |
6a65c5b9 FJ |
2463 | * |
2464 | * A non-zero step value implies that the command may access multiple | |
2465 | * registers in sequence (e.g. LRI), in that case step gives the | |
2466 | * distance in dwords between individual offset fields. | |
351e3db2 BV |
2467 | */ |
2468 | struct { | |
2469 | u32 offset; | |
2470 | u32 mask; | |
6a65c5b9 | 2471 | u32 step; |
351e3db2 BV |
2472 | } reg; |
2473 | ||
2474 | #define MAX_CMD_DESC_BITMASKS 3 | |
2475 | /* | |
2476 | * Describes command checks where a particular dword is masked and | |
2477 | * compared against an expected value. If the command does not match | |
2478 | * the expected value, the parser rejects it. Only valid if flags has | |
2479 | * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero | |
2480 | * are valid. | |
d4d48035 BV |
2481 | * |
2482 | * If the check specifies a non-zero condition_mask then the parser | |
2483 | * only performs the check when the bits specified by condition_mask | |
2484 | * are non-zero. | |
351e3db2 BV |
2485 | */ |
2486 | struct { | |
2487 | u32 offset; | |
2488 | u32 mask; | |
2489 | u32 expected; | |
d4d48035 BV |
2490 | u32 condition_offset; |
2491 | u32 condition_mask; | |
351e3db2 BV |
2492 | } bits[MAX_CMD_DESC_BITMASKS]; |
2493 | }; | |
2494 | ||
2495 | /* | |
2496 | * A table of commands requiring special handling by the command parser. | |
2497 | * | |
2498 | * Each ring has an array of tables. Each table consists of an array of command | |
2499 | * descriptors, which must be sorted with command opcodes in ascending order. | |
2500 | */ | |
2501 | struct drm_i915_cmd_table { | |
2502 | const struct drm_i915_cmd_descriptor *table; | |
2503 | int count; | |
2504 | }; | |
2505 | ||
dbbe9127 | 2506 | /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */ |
7312e2dd CW |
2507 | #define __I915__(p) ({ \ |
2508 | struct drm_i915_private *__p; \ | |
2509 | if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \ | |
2510 | __p = (struct drm_i915_private *)p; \ | |
2511 | else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \ | |
2512 | __p = to_i915((struct drm_device *)p); \ | |
2513 | else \ | |
2514 | BUILD_BUG(); \ | |
2515 | __p; \ | |
2516 | }) | |
dbbe9127 | 2517 | #define INTEL_INFO(p) (&__I915__(p)->info) |
3f10e82f | 2518 | #define INTEL_GEN(p) (INTEL_INFO(p)->gen) |
87f1f465 | 2519 | #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id) |
e90a21d4 | 2520 | #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision) |
cae5852d | 2521 | |
e87a005d JN |
2522 | #define REVID_FOREVER 0xff |
2523 | /* | |
2524 | * Return true if revision is in range [since,until] inclusive. | |
2525 | * | |
2526 | * Use 0 for open-ended since, and REVID_FOREVER for open-ended until. | |
2527 | */ | |
2528 | #define IS_REVID(p, since, until) \ | |
2529 | (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) | |
2530 | ||
87f1f465 CW |
2531 | #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577) |
2532 | #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562) | |
cae5852d | 2533 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
87f1f465 | 2534 | #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572) |
cae5852d | 2535 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
87f1f465 CW |
2536 | #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592) |
2537 | #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772) | |
cae5852d ZN |
2538 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) |
2539 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) | |
2540 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
87f1f465 | 2541 | #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42) |
cae5852d | 2542 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) |
87f1f465 CW |
2543 | #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001) |
2544 | #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011) | |
cae5852d ZN |
2545 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) |
2546 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
87f1f465 | 2547 | #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046) |
4b65177b | 2548 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
87f1f465 CW |
2549 | #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \ |
2550 | INTEL_DEVID(dev) == 0x0152 || \ | |
2551 | INTEL_DEVID(dev) == 0x015a) | |
70a3eb7a | 2552 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
666a4537 | 2553 | #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview) |
4cae9ae0 | 2554 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
666a4537 | 2555 | #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_cherryview && IS_GEN8(dev)) |
7201c0b3 | 2556 | #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake) |
7526ac19 | 2557 | #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton) |
ef11bdb3 | 2558 | #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake) |
cae5852d | 2559 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
ed1c9e2c | 2560 | #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2561 | (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) |
5dd8c4c3 | 2562 | #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ |
6b96d705 | 2563 | ((INTEL_DEVID(dev) & 0xf) == 0x6 || \ |
0dc6f20b | 2564 | (INTEL_DEVID(dev) & 0xf) == 0xb || \ |
87f1f465 | 2565 | (INTEL_DEVID(dev) & 0xf) == 0xe)) |
ebb72aad VS |
2566 | /* ULX machines are also considered ULT. */ |
2567 | #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \ | |
2568 | (INTEL_DEVID(dev) & 0xf) == 0xe) | |
a0fcbd95 RV |
2569 | #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \ |
2570 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) | |
5dd8c4c3 | 2571 | #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2572 | (INTEL_DEVID(dev) & 0xFF00) == 0x0A00) |
9435373e | 2573 | #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2574 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) |
9bbfd20a | 2575 | /* ULX machines are also considered ULT. */ |
87f1f465 CW |
2576 | #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \ |
2577 | INTEL_DEVID(dev) == 0x0A1E) | |
f8896f5d DW |
2578 | #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \ |
2579 | INTEL_DEVID(dev) == 0x1913 || \ | |
2580 | INTEL_DEVID(dev) == 0x1916 || \ | |
2581 | INTEL_DEVID(dev) == 0x1921 || \ | |
2582 | INTEL_DEVID(dev) == 0x1926) | |
2583 | #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \ | |
2584 | INTEL_DEVID(dev) == 0x1915 || \ | |
2585 | INTEL_DEVID(dev) == 0x191E) | |
a5b7991c RV |
2586 | #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \ |
2587 | INTEL_DEVID(dev) == 0x5913 || \ | |
2588 | INTEL_DEVID(dev) == 0x5916 || \ | |
2589 | INTEL_DEVID(dev) == 0x5921 || \ | |
2590 | INTEL_DEVID(dev) == 0x5926) | |
2591 | #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \ | |
2592 | INTEL_DEVID(dev) == 0x5915 || \ | |
2593 | INTEL_DEVID(dev) == 0x591E) | |
7a58bad0 SAK |
2594 | #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \ |
2595 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) | |
2596 | #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \ | |
2597 | (INTEL_DEVID(dev) & 0x00F0) == 0x0030) | |
2598 | ||
b833d685 | 2599 | #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) |
cae5852d | 2600 | |
ef712bb4 JN |
2601 | #define SKL_REVID_A0 0x0 |
2602 | #define SKL_REVID_B0 0x1 | |
2603 | #define SKL_REVID_C0 0x2 | |
2604 | #define SKL_REVID_D0 0x3 | |
2605 | #define SKL_REVID_E0 0x4 | |
2606 | #define SKL_REVID_F0 0x5 | |
2607 | ||
e87a005d JN |
2608 | #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until)) |
2609 | ||
ef712bb4 | 2610 | #define BXT_REVID_A0 0x0 |
fffda3f4 | 2611 | #define BXT_REVID_A1 0x1 |
ef712bb4 JN |
2612 | #define BXT_REVID_B0 0x3 |
2613 | #define BXT_REVID_C0 0x9 | |
6c74c87f | 2614 | |
e87a005d JN |
2615 | #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until)) |
2616 | ||
85436696 JB |
2617 | /* |
2618 | * The genX designation typically refers to the render engine, so render | |
2619 | * capability related checks should use IS_GEN, while display and other checks | |
2620 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
2621 | * chips, etc.). | |
2622 | */ | |
cae5852d ZN |
2623 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
2624 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) | |
2625 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) | |
2626 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) | |
2627 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) | |
85436696 | 2628 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
d2980845 | 2629 | #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8) |
b71252dc | 2630 | #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9) |
cae5852d | 2631 | |
73ae478c BW |
2632 | #define RENDER_RING (1<<RCS) |
2633 | #define BSD_RING (1<<VCS) | |
2634 | #define BLT_RING (1<<BCS) | |
2635 | #define VEBOX_RING (1<<VECS) | |
845f74a7 | 2636 | #define BSD2_RING (1<<VCS2) |
ee4b6faf MK |
2637 | #define ALL_ENGINES (~0) |
2638 | ||
63c42e56 | 2639 | #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) |
845f74a7 | 2640 | #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING) |
63c42e56 BW |
2641 | #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) |
2642 | #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) | |
2643 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) | |
ca377809 | 2644 | #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop) |
3accaf7e | 2645 | #define HAS_EDRAM(dev) (__I915__(dev)->edram_cap & EDRAM_ENABLED) |
63c42e56 | 2646 | #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ |
3accaf7e | 2647 | HAS_EDRAM(dev)) |
cae5852d ZN |
2648 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
2649 | ||
254f965c | 2650 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) |
d7f621e5 | 2651 | #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8) |
692ef70c | 2652 | #define USES_PPGTT(dev) (i915.enable_ppgtt) |
81ba8aef MT |
2653 | #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2) |
2654 | #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3) | |
1d2a314c | 2655 | |
05394f39 | 2656 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
cae5852d ZN |
2657 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
2658 | ||
b45305fc DV |
2659 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
2660 | #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) | |
06e668ac MK |
2661 | |
2662 | /* WaRsDisableCoarsePowerGating:skl,bxt */ | |
2663 | #define NEEDS_WaRsDisableCoarsePowerGating(dev) (IS_BXT_REVID(dev, 0, BXT_REVID_A1) || \ | |
185c66e5 MK |
2664 | IS_SKL_GT3(dev) || \ |
2665 | IS_SKL_GT4(dev)) | |
2666 | ||
4e6b788c DV |
2667 | /* |
2668 | * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts | |
2669 | * even when in MSI mode. This results in spurious interrupt warnings if the | |
2670 | * legacy irq no. is shared with another device. The kernel then disables that | |
2671 | * interrupt source and so prevents the other device from working properly. | |
2672 | */ | |
2673 | #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) | |
2674 | #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) | |
b45305fc | 2675 | |
cae5852d ZN |
2676 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
2677 | * rows, which changed the alignment requirements and fence programming. | |
2678 | */ | |
2679 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ | |
2680 | IS_I915GM(dev))) | |
cae5852d ZN |
2681 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) |
2682 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) | |
cae5852d ZN |
2683 | |
2684 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) | |
2685 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) | |
3a77c4c4 | 2686 | #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
cae5852d | 2687 | |
dbf7786e | 2688 | #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev)) |
f5adf94e | 2689 | |
0c9b3715 JN |
2690 | #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ |
2691 | INTEL_INFO(dev)->gen >= 9) | |
2692 | ||
dd93be58 | 2693 | #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) |
30568c45 | 2694 | #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) |
b32c6f48 | 2695 | #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ |
e3d99845 | 2696 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \ |
ef11bdb3 | 2697 | IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
6157d3c8 | 2698 | #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ |
00776511 | 2699 | IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \ |
666a4537 | 2700 | IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \ |
8f6d855c | 2701 | IS_KABYLAKE(dev) || IS_BROXTON(dev)) |
58abf1da RV |
2702 | #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6) |
2703 | #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev)) | |
affa9354 | 2704 | |
7b403ffb | 2705 | #define HAS_CSR(dev) (IS_GEN9(dev)) |
eb805623 | 2706 | |
2b81b844 RV |
2707 | #define HAS_GUC_UCODE(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev)) |
2708 | #define HAS_GUC_SCHED(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev)) | |
33a732f4 | 2709 | |
a9ed33ca AJ |
2710 | #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \ |
2711 | INTEL_INFO(dev)->gen >= 8) | |
2712 | ||
97d3308a | 2713 | #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \ |
666a4537 WB |
2714 | !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \ |
2715 | !IS_BROXTON(dev)) | |
97d3308a | 2716 | |
17a303ec PZ |
2717 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
2718 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 | |
2719 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 | |
2720 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 | |
2721 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 | |
2722 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 | |
e7e7ea20 S |
2723 | #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 |
2724 | #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 | |
30c964a6 | 2725 | #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100 |
1844a66b | 2726 | #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000 |
39bfcd52 | 2727 | #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */ |
17a303ec | 2728 | |
f2fbc690 | 2729 | #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type) |
e7e7ea20 | 2730 | #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT) |
eb877ebf | 2731 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
c2699524 | 2732 | #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) |
56f5f700 | 2733 | #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) |
cae5852d ZN |
2734 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
2735 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) | |
40c7ead9 | 2736 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) |
45e6e3a1 | 2737 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
cae5852d | 2738 | |
666a4537 WB |
2739 | #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \ |
2740 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) | |
5fafe292 | 2741 | |
040d2baa BW |
2742 | /* DPF == dynamic parity feature */ |
2743 | #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
2744 | #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) | |
e1ef7cc2 | 2745 | |
c8735b0c | 2746 | #define GT_FREQUENCY_MULTIPLIER 50 |
de43ae9d | 2747 | #define GEN9_FREQ_SCALER 3 |
c8735b0c | 2748 | |
05394f39 CW |
2749 | #include "i915_trace.h" |
2750 | ||
baa70943 | 2751 | extern const struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 DA |
2752 | extern int i915_max_ioctl; |
2753 | ||
1751fcf9 ML |
2754 | extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state); |
2755 | extern int i915_resume_switcheroo(struct drm_device *dev); | |
7c1c2871 | 2756 | |
0e4ca100 CW |
2757 | int intel_sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt); |
2758 | ||
c838d719 | 2759 | /* i915_dma.c */ |
d15d7538 ID |
2760 | void __printf(3, 4) |
2761 | __i915_printk(struct drm_i915_private *dev_priv, const char *level, | |
2762 | const char *fmt, ...); | |
2763 | ||
2764 | #define i915_report_error(dev_priv, fmt, ...) \ | |
2765 | __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__) | |
2766 | ||
22eae947 | 2767 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 2768 | extern int i915_driver_unload(struct drm_device *); |
2885f6ac | 2769 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file); |
84b1fd10 | 2770 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac | 2771 | extern void i915_driver_preclose(struct drm_device *dev, |
2885f6ac | 2772 | struct drm_file *file); |
673a394b | 2773 | extern void i915_driver_postclose(struct drm_device *dev, |
2885f6ac | 2774 | struct drm_file *file); |
c43b5634 | 2775 | #ifdef CONFIG_COMPAT |
0d6aa60b DA |
2776 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
2777 | unsigned long arg); | |
c43b5634 | 2778 | #endif |
ee4b6faf | 2779 | extern int intel_gpu_reset(struct drm_device *dev, u32 engine_mask); |
49e4d842 | 2780 | extern bool intel_has_gpu_reset(struct drm_device *dev); |
d4b8bb2a | 2781 | extern int i915_reset(struct drm_device *dev); |
6b332fa2 | 2782 | extern int intel_guc_reset(struct drm_i915_private *dev_priv); |
fc0768ce | 2783 | extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine); |
7648fa99 JB |
2784 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
2785 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
2786 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
2787 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
650ad970 | 2788 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); |
7648fa99 | 2789 | |
77913b39 | 2790 | /* intel_hotplug.c */ |
91d14251 TU |
2791 | void intel_hpd_irq_handler(struct drm_i915_private *dev_priv, |
2792 | u32 pin_mask, u32 long_mask); | |
77913b39 JN |
2793 | void intel_hpd_init(struct drm_i915_private *dev_priv); |
2794 | void intel_hpd_init_work(struct drm_i915_private *dev_priv); | |
2795 | void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); | |
cc24fcdc | 2796 | bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port); |
77913b39 | 2797 | |
1da177e4 | 2798 | /* i915_irq.c */ |
10cd45b6 | 2799 | void i915_queue_hangcheck(struct drm_device *dev); |
58174462 | 2800 | __printf(3, 4) |
14b730fc | 2801 | void i915_handle_error(struct drm_device *dev, u32 engine_mask, |
58174462 | 2802 | const char *fmt, ...); |
1da177e4 | 2803 | |
b963291c | 2804 | extern void intel_irq_init(struct drm_i915_private *dev_priv); |
2aeb7d3a DV |
2805 | int intel_irq_install(struct drm_i915_private *dev_priv); |
2806 | void intel_irq_uninstall(struct drm_i915_private *dev_priv); | |
907b28c5 CW |
2807 | |
2808 | extern void intel_uncore_sanitize(struct drm_device *dev); | |
10018603 ID |
2809 | extern void intel_uncore_early_sanitize(struct drm_device *dev, |
2810 | bool restore_forcewake); | |
907b28c5 | 2811 | extern void intel_uncore_init(struct drm_device *dev); |
fc97618b | 2812 | extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv); |
bc3b9346 | 2813 | extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv); |
aec347ab | 2814 | extern void intel_uncore_fini(struct drm_device *dev); |
156c7ca0 | 2815 | extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore); |
48c1026a | 2816 | const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id); |
59bad947 | 2817 | void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, |
48c1026a | 2818 | enum forcewake_domains domains); |
59bad947 | 2819 | void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, |
48c1026a | 2820 | enum forcewake_domains domains); |
a6111f7b CW |
2821 | /* Like above but the caller must manage the uncore.lock itself. |
2822 | * Must be used with I915_READ_FW and friends. | |
2823 | */ | |
2824 | void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv, | |
2825 | enum forcewake_domains domains); | |
2826 | void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv, | |
2827 | enum forcewake_domains domains); | |
3accaf7e MK |
2828 | u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv); |
2829 | ||
59bad947 | 2830 | void assert_forcewakes_inactive(struct drm_i915_private *dev_priv); |
cf9d2890 YZ |
2831 | static inline bool intel_vgpu_active(struct drm_device *dev) |
2832 | { | |
2833 | return to_i915(dev)->vgpu.active; | |
2834 | } | |
b1f14ad0 | 2835 | |
7c463586 | 2836 | void |
50227e1c | 2837 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 2838 | u32 status_mask); |
7c463586 KP |
2839 | |
2840 | void | |
50227e1c | 2841 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 2842 | u32 status_mask); |
7c463586 | 2843 | |
f8b79e58 ID |
2844 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); |
2845 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); | |
0706f17c EE |
2846 | void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, |
2847 | uint32_t mask, | |
2848 | uint32_t bits); | |
fbdedaea VS |
2849 | void ilk_update_display_irq(struct drm_i915_private *dev_priv, |
2850 | uint32_t interrupt_mask, | |
2851 | uint32_t enabled_irq_mask); | |
2852 | static inline void | |
2853 | ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) | |
2854 | { | |
2855 | ilk_update_display_irq(dev_priv, bits, bits); | |
2856 | } | |
2857 | static inline void | |
2858 | ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) | |
2859 | { | |
2860 | ilk_update_display_irq(dev_priv, bits, 0); | |
2861 | } | |
013d3752 VS |
2862 | void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, |
2863 | enum pipe pipe, | |
2864 | uint32_t interrupt_mask, | |
2865 | uint32_t enabled_irq_mask); | |
2866 | static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv, | |
2867 | enum pipe pipe, uint32_t bits) | |
2868 | { | |
2869 | bdw_update_pipe_irq(dev_priv, pipe, bits, bits); | |
2870 | } | |
2871 | static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv, | |
2872 | enum pipe pipe, uint32_t bits) | |
2873 | { | |
2874 | bdw_update_pipe_irq(dev_priv, pipe, bits, 0); | |
2875 | } | |
47339cd9 DV |
2876 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
2877 | uint32_t interrupt_mask, | |
2878 | uint32_t enabled_irq_mask); | |
14443261 VS |
2879 | static inline void |
2880 | ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) | |
2881 | { | |
2882 | ibx_display_interrupt_update(dev_priv, bits, bits); | |
2883 | } | |
2884 | static inline void | |
2885 | ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) | |
2886 | { | |
2887 | ibx_display_interrupt_update(dev_priv, bits, 0); | |
2888 | } | |
2889 | ||
f8b79e58 | 2890 | |
673a394b | 2891 | /* i915_gem.c */ |
673a394b EA |
2892 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
2893 | struct drm_file *file_priv); | |
2894 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
2895 | struct drm_file *file_priv); | |
2896 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
2897 | struct drm_file *file_priv); | |
2898 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
2899 | struct drm_file *file_priv); | |
de151cf6 JB |
2900 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
2901 | struct drm_file *file_priv); | |
673a394b EA |
2902 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
2903 | struct drm_file *file_priv); | |
2904 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
2905 | struct drm_file *file_priv); | |
ba8b7ccb | 2906 | void i915_gem_execbuffer_move_to_active(struct list_head *vmas, |
8a8edb59 | 2907 | struct drm_i915_gem_request *req); |
5f19e2bf | 2908 | int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params, |
a83014d3 | 2909 | struct drm_i915_gem_execbuffer2 *args, |
5f19e2bf | 2910 | struct list_head *vmas); |
673a394b EA |
2911 | int i915_gem_execbuffer(struct drm_device *dev, void *data, |
2912 | struct drm_file *file_priv); | |
76446cac JB |
2913 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
2914 | struct drm_file *file_priv); | |
673a394b EA |
2915 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
2916 | struct drm_file *file_priv); | |
199adf40 BW |
2917 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
2918 | struct drm_file *file); | |
2919 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, | |
2920 | struct drm_file *file); | |
673a394b EA |
2921 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
2922 | struct drm_file *file_priv); | |
3ef94daa CW |
2923 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
2924 | struct drm_file *file_priv); | |
673a394b EA |
2925 | int i915_gem_set_tiling(struct drm_device *dev, void *data, |
2926 | struct drm_file *file_priv); | |
2927 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
2928 | struct drm_file *file_priv); | |
5cc9ed4b CW |
2929 | int i915_gem_init_userptr(struct drm_device *dev); |
2930 | int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, | |
2931 | struct drm_file *file); | |
5a125c3c EA |
2932 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
2933 | struct drm_file *file_priv); | |
23ba4fd0 BW |
2934 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
2935 | struct drm_file *file_priv); | |
d64aa096 ID |
2936 | void i915_gem_load_init(struct drm_device *dev); |
2937 | void i915_gem_load_cleanup(struct drm_device *dev); | |
40ae4e16 | 2938 | void i915_gem_load_init_fences(struct drm_i915_private *dev_priv); |
42dcedd4 CW |
2939 | void *i915_gem_object_alloc(struct drm_device *dev); |
2940 | void i915_gem_object_free(struct drm_i915_gem_object *obj); | |
37e680a1 CW |
2941 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
2942 | const struct drm_i915_gem_object_ops *ops); | |
d37cd8a8 | 2943 | struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev, |
05394f39 | 2944 | size_t size); |
ea70299d DG |
2945 | struct drm_i915_gem_object *i915_gem_object_create_from_data( |
2946 | struct drm_device *dev, const void *data, size_t size); | |
673a394b | 2947 | void i915_gem_free_object(struct drm_gem_object *obj); |
2f633156 | 2948 | void i915_gem_vma_destroy(struct i915_vma *vma); |
42dcedd4 | 2949 | |
0875546c DV |
2950 | /* Flags used by pin/bind&friends. */ |
2951 | #define PIN_MAPPABLE (1<<0) | |
2952 | #define PIN_NONBLOCK (1<<1) | |
2953 | #define PIN_GLOBAL (1<<2) | |
2954 | #define PIN_OFFSET_BIAS (1<<3) | |
2955 | #define PIN_USER (1<<4) | |
2956 | #define PIN_UPDATE (1<<5) | |
101b506a MT |
2957 | #define PIN_ZONE_4G (1<<6) |
2958 | #define PIN_HIGH (1<<7) | |
506a8e87 | 2959 | #define PIN_OFFSET_FIXED (1<<8) |
d23db88c | 2960 | #define PIN_OFFSET_MASK (~4095) |
ec7adb6e JL |
2961 | int __must_check |
2962 | i915_gem_object_pin(struct drm_i915_gem_object *obj, | |
2963 | struct i915_address_space *vm, | |
2964 | uint32_t alignment, | |
2965 | uint64_t flags); | |
2966 | int __must_check | |
2967 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, | |
2968 | const struct i915_ggtt_view *view, | |
2969 | uint32_t alignment, | |
2970 | uint64_t flags); | |
fe14d5f4 TU |
2971 | |
2972 | int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, | |
2973 | u32 flags); | |
d0710abb | 2974 | void __i915_vma_set_map_and_fenceable(struct i915_vma *vma); |
07fe0b12 | 2975 | int __must_check i915_vma_unbind(struct i915_vma *vma); |
e9f24d5f TU |
2976 | /* |
2977 | * BEWARE: Do not use the function below unless you can _absolutely_ | |
2978 | * _guarantee_ VMA in question is _not in use_ anywhere. | |
2979 | */ | |
2980 | int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma); | |
dd624afd | 2981 | int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); |
48018a57 | 2982 | void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); |
05394f39 | 2983 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
f787a5f5 | 2984 | |
4c914c0c BV |
2985 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, |
2986 | int *needs_clflush); | |
2987 | ||
37e680a1 | 2988 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
ee286370 CW |
2989 | |
2990 | static inline int __sg_page_count(struct scatterlist *sg) | |
9da3da66 | 2991 | { |
ee286370 CW |
2992 | return sg->length >> PAGE_SHIFT; |
2993 | } | |
67d5a50c | 2994 | |
033908ae DG |
2995 | struct page * |
2996 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n); | |
2997 | ||
ee286370 CW |
2998 | static inline struct page * |
2999 | i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) | |
9da3da66 | 3000 | { |
ee286370 CW |
3001 | if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT)) |
3002 | return NULL; | |
67d5a50c | 3003 | |
ee286370 CW |
3004 | if (n < obj->get_page.last) { |
3005 | obj->get_page.sg = obj->pages->sgl; | |
3006 | obj->get_page.last = 0; | |
3007 | } | |
67d5a50c | 3008 | |
ee286370 CW |
3009 | while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) { |
3010 | obj->get_page.last += __sg_page_count(obj->get_page.sg++); | |
3011 | if (unlikely(sg_is_chain(obj->get_page.sg))) | |
3012 | obj->get_page.sg = sg_chain_ptr(obj->get_page.sg); | |
3013 | } | |
67d5a50c | 3014 | |
ee286370 | 3015 | return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last); |
9da3da66 | 3016 | } |
ee286370 | 3017 | |
a5570178 CW |
3018 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
3019 | { | |
3020 | BUG_ON(obj->pages == NULL); | |
3021 | obj->pages_pin_count++; | |
3022 | } | |
0a798eb9 | 3023 | |
a5570178 CW |
3024 | static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) |
3025 | { | |
3026 | BUG_ON(obj->pages_pin_count == 0); | |
3027 | obj->pages_pin_count--; | |
3028 | } | |
3029 | ||
0a798eb9 CW |
3030 | /** |
3031 | * i915_gem_object_pin_map - return a contiguous mapping of the entire object | |
3032 | * @obj - the object to map into kernel address space | |
3033 | * | |
3034 | * Calls i915_gem_object_pin_pages() to prevent reaping of the object's | |
3035 | * pages and then returns a contiguous mapping of the backing storage into | |
3036 | * the kernel address space. | |
3037 | * | |
8305216f DG |
3038 | * The caller must hold the struct_mutex, and is responsible for calling |
3039 | * i915_gem_object_unpin_map() when the mapping is no longer required. | |
0a798eb9 | 3040 | * |
8305216f DG |
3041 | * Returns the pointer through which to access the mapped object, or an |
3042 | * ERR_PTR() on error. | |
0a798eb9 CW |
3043 | */ |
3044 | void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj); | |
3045 | ||
3046 | /** | |
3047 | * i915_gem_object_unpin_map - releases an earlier mapping | |
3048 | * @obj - the object to unmap | |
3049 | * | |
3050 | * After pinning the object and mapping its pages, once you are finished | |
3051 | * with your access, call i915_gem_object_unpin_map() to release the pin | |
3052 | * upon the mapping. Once the pin count reaches zero, that mapping may be | |
3053 | * removed. | |
3054 | * | |
3055 | * The caller must hold the struct_mutex. | |
3056 | */ | |
3057 | static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj) | |
3058 | { | |
3059 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
3060 | i915_gem_object_unpin_pages(obj); | |
3061 | } | |
3062 | ||
54cf91dc | 3063 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
2911a35b | 3064 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
91af127f JH |
3065 | struct intel_engine_cs *to, |
3066 | struct drm_i915_gem_request **to_req); | |
e2d05a8b | 3067 | void i915_vma_move_to_active(struct i915_vma *vma, |
b2af0376 | 3068 | struct drm_i915_gem_request *req); |
ff72145b DA |
3069 | int i915_gem_dumb_create(struct drm_file *file_priv, |
3070 | struct drm_device *dev, | |
3071 | struct drm_mode_create_dumb *args); | |
da6b51d0 DA |
3072 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, |
3073 | uint32_t handle, uint64_t *offset); | |
f787a5f5 CW |
3074 | /** |
3075 | * Returns true if seq1 is later than seq2. | |
3076 | */ | |
3077 | static inline bool | |
3078 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) | |
3079 | { | |
3080 | return (int32_t)(seq1 - seq2) >= 0; | |
3081 | } | |
3082 | ||
821485dc CW |
3083 | static inline bool i915_gem_request_started(struct drm_i915_gem_request *req, |
3084 | bool lazy_coherency) | |
3085 | { | |
c04e0f3b CW |
3086 | if (!lazy_coherency && req->engine->irq_seqno_barrier) |
3087 | req->engine->irq_seqno_barrier(req->engine); | |
3088 | return i915_seqno_passed(req->engine->get_seqno(req->engine), | |
3089 | req->previous_seqno); | |
821485dc CW |
3090 | } |
3091 | ||
1b5a433a JH |
3092 | static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req, |
3093 | bool lazy_coherency) | |
3094 | { | |
c04e0f3b CW |
3095 | if (!lazy_coherency && req->engine->irq_seqno_barrier) |
3096 | req->engine->irq_seqno_barrier(req->engine); | |
3097 | return i915_seqno_passed(req->engine->get_seqno(req->engine), | |
3098 | req->seqno); | |
1b5a433a JH |
3099 | } |
3100 | ||
fca26bb4 MK |
3101 | int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); |
3102 | int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); | |
1690e1eb | 3103 | |
8d9fc7fd | 3104 | struct drm_i915_gem_request * |
0bc40be8 | 3105 | i915_gem_find_active_request(struct intel_engine_cs *engine); |
8d9fc7fd | 3106 | |
b29c19b6 | 3107 | bool i915_gem_retire_requests(struct drm_device *dev); |
0bc40be8 | 3108 | void i915_gem_retire_requests_ring(struct intel_engine_cs *engine); |
84c33a64 | 3109 | |
c19ae989 CW |
3110 | static inline u32 i915_reset_counter(struct i915_gpu_error *error) |
3111 | { | |
3112 | return atomic_read(&error->reset_counter); | |
3113 | } | |
3114 | ||
3115 | static inline bool __i915_reset_in_progress(u32 reset) | |
3116 | { | |
3117 | return unlikely(reset & I915_RESET_IN_PROGRESS_FLAG); | |
3118 | } | |
3119 | ||
3120 | static inline bool __i915_reset_in_progress_or_wedged(u32 reset) | |
3121 | { | |
3122 | return unlikely(reset & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); | |
3123 | } | |
3124 | ||
3125 | static inline bool __i915_terminally_wedged(u32 reset) | |
3126 | { | |
3127 | return unlikely(reset & I915_WEDGED); | |
3128 | } | |
3129 | ||
1f83fee0 DV |
3130 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) |
3131 | { | |
c19ae989 CW |
3132 | return __i915_reset_in_progress(i915_reset_counter(error)); |
3133 | } | |
3134 | ||
3135 | static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error) | |
3136 | { | |
3137 | return __i915_reset_in_progress_or_wedged(i915_reset_counter(error)); | |
1f83fee0 DV |
3138 | } |
3139 | ||
3140 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) | |
3141 | { | |
c19ae989 | 3142 | return __i915_terminally_wedged(i915_reset_counter(error)); |
2ac0f450 MK |
3143 | } |
3144 | ||
3145 | static inline u32 i915_reset_count(struct i915_gpu_error *error) | |
3146 | { | |
c19ae989 | 3147 | return ((i915_reset_counter(error) & ~I915_WEDGED) + 1) / 2; |
1f83fee0 | 3148 | } |
a71d8d94 | 3149 | |
88b4aa87 MK |
3150 | static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv) |
3151 | { | |
3152 | return dev_priv->gpu_error.stop_rings == 0 || | |
3153 | dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN; | |
3154 | } | |
3155 | ||
3156 | static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv) | |
3157 | { | |
3158 | return dev_priv->gpu_error.stop_rings == 0 || | |
3159 | dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN; | |
3160 | } | |
3161 | ||
069efc1d | 3162 | void i915_gem_reset(struct drm_device *dev); |
000433b6 | 3163 | bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); |
1070a42b | 3164 | int __must_check i915_gem_init(struct drm_device *dev); |
117897f4 | 3165 | int i915_gem_init_engines(struct drm_device *dev); |
f691e2f4 DV |
3166 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
3167 | void i915_gem_init_swizzling(struct drm_device *dev); | |
117897f4 | 3168 | void i915_gem_cleanup_engines(struct drm_device *dev); |
b2da9fe5 | 3169 | int __must_check i915_gpu_idle(struct drm_device *dev); |
45c5f202 | 3170 | int __must_check i915_gem_suspend(struct drm_device *dev); |
75289874 | 3171 | void __i915_add_request(struct drm_i915_gem_request *req, |
5b4a60c2 JH |
3172 | struct drm_i915_gem_object *batch_obj, |
3173 | bool flush_caches); | |
75289874 | 3174 | #define i915_add_request(req) \ |
fcfa423c | 3175 | __i915_add_request(req, NULL, true) |
75289874 | 3176 | #define i915_add_request_no_flush(req) \ |
fcfa423c | 3177 | __i915_add_request(req, NULL, false) |
9c654818 | 3178 | int __i915_wait_request(struct drm_i915_gem_request *req, |
16e9a21f ACO |
3179 | bool interruptible, |
3180 | s64 *timeout, | |
2e1b8730 | 3181 | struct intel_rps_client *rps); |
a4b3a571 | 3182 | int __must_check i915_wait_request(struct drm_i915_gem_request *req); |
de151cf6 | 3183 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
2021746e | 3184 | int __must_check |
2e2f351d CW |
3185 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
3186 | bool readonly); | |
3187 | int __must_check | |
2021746e CW |
3188 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, |
3189 | bool write); | |
3190 | int __must_check | |
dabdfe02 CW |
3191 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
3192 | int __must_check | |
2da3b9b9 CW |
3193 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3194 | u32 alignment, | |
e6617330 TU |
3195 | const struct i915_ggtt_view *view); |
3196 | void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, | |
3197 | const struct i915_ggtt_view *view); | |
00731155 | 3198 | int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, |
6eeefaf3 | 3199 | int align); |
b29c19b6 | 3200 | int i915_gem_open(struct drm_device *dev, struct drm_file *file); |
05394f39 | 3201 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 3202 | |
0fa87796 ID |
3203 | uint32_t |
3204 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); | |
467cffba | 3205 | uint32_t |
d865110c ID |
3206 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
3207 | int tiling_mode, bool fenced); | |
467cffba | 3208 | |
e4ffd173 CW |
3209 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3210 | enum i915_cache_level cache_level); | |
3211 | ||
1286ff73 DV |
3212 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
3213 | struct dma_buf *dma_buf); | |
3214 | ||
3215 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, | |
3216 | struct drm_gem_object *gem_obj, int flags); | |
3217 | ||
088e0df4 MT |
3218 | u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, |
3219 | const struct i915_ggtt_view *view); | |
3220 | u64 i915_gem_obj_offset(struct drm_i915_gem_object *o, | |
3221 | struct i915_address_space *vm); | |
3222 | static inline u64 | |
ec7adb6e | 3223 | i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o) |
fe14d5f4 | 3224 | { |
9abc4648 | 3225 | return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal); |
fe14d5f4 | 3226 | } |
ec7adb6e | 3227 | |
a70a3148 | 3228 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o); |
ec7adb6e | 3229 | bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o, |
9abc4648 | 3230 | const struct i915_ggtt_view *view); |
a70a3148 | 3231 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, |
ec7adb6e | 3232 | struct i915_address_space *vm); |
fe14d5f4 | 3233 | |
fe14d5f4 | 3234 | struct i915_vma * |
ec7adb6e JL |
3235 | i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
3236 | struct i915_address_space *vm); | |
3237 | struct i915_vma * | |
3238 | i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj, | |
3239 | const struct i915_ggtt_view *view); | |
fe14d5f4 | 3240 | |
accfef2e BW |
3241 | struct i915_vma * |
3242 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
ec7adb6e JL |
3243 | struct i915_address_space *vm); |
3244 | struct i915_vma * | |
3245 | i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj, | |
3246 | const struct i915_ggtt_view *view); | |
5c2abbea | 3247 | |
ec7adb6e JL |
3248 | static inline struct i915_vma * |
3249 | i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) | |
3250 | { | |
3251 | return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal); | |
d7f46fc4 | 3252 | } |
ec7adb6e | 3253 | bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj); |
5c2abbea | 3254 | |
a70a3148 | 3255 | /* Some GGTT VM helpers */ |
841cd773 DV |
3256 | static inline struct i915_hw_ppgtt * |
3257 | i915_vm_to_ppgtt(struct i915_address_space *vm) | |
3258 | { | |
841cd773 DV |
3259 | return container_of(vm, struct i915_hw_ppgtt, base); |
3260 | } | |
3261 | ||
3262 | ||
a70a3148 BW |
3263 | static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) |
3264 | { | |
9abc4648 | 3265 | return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal); |
a70a3148 BW |
3266 | } |
3267 | ||
8da32727 TU |
3268 | unsigned long |
3269 | i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj); | |
c37e2204 BW |
3270 | |
3271 | static inline int __must_check | |
3272 | i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, | |
3273 | uint32_t alignment, | |
1ec9e26d | 3274 | unsigned flags) |
c37e2204 | 3275 | { |
72e96d64 JL |
3276 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
3277 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
3278 | ||
3279 | return i915_gem_object_pin(obj, &ggtt->base, | |
5dc383b0 | 3280 | alignment, flags | PIN_GLOBAL); |
c37e2204 | 3281 | } |
a70a3148 | 3282 | |
e6617330 TU |
3283 | void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj, |
3284 | const struct i915_ggtt_view *view); | |
3285 | static inline void | |
3286 | i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj) | |
3287 | { | |
3288 | i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal); | |
3289 | } | |
b287110e | 3290 | |
41a36b73 DV |
3291 | /* i915_gem_fence.c */ |
3292 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); | |
3293 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); | |
3294 | ||
3295 | bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj); | |
3296 | void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj); | |
3297 | ||
3298 | void i915_gem_restore_fences(struct drm_device *dev); | |
3299 | ||
7f96ecaf DV |
3300 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
3301 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
3302 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
3303 | ||
254f965c | 3304 | /* i915_gem_context.c */ |
8245be31 | 3305 | int __must_check i915_gem_context_init(struct drm_device *dev); |
b2e862d0 | 3306 | void i915_gem_context_lost(struct drm_i915_private *dev_priv); |
254f965c | 3307 | void i915_gem_context_fini(struct drm_device *dev); |
acce9ffa | 3308 | void i915_gem_context_reset(struct drm_device *dev); |
e422b888 | 3309 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file); |
254f965c | 3310 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); |
ba01cc93 | 3311 | int i915_switch_context(struct drm_i915_gem_request *req); |
273497e5 | 3312 | struct intel_context * |
41bde553 | 3313 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id); |
dce3271b | 3314 | void i915_gem_context_free(struct kref *ctx_ref); |
8c857917 OM |
3315 | struct drm_i915_gem_object * |
3316 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size); | |
273497e5 | 3317 | static inline void i915_gem_context_reference(struct intel_context *ctx) |
dce3271b | 3318 | { |
691e6415 | 3319 | kref_get(&ctx->ref); |
dce3271b MK |
3320 | } |
3321 | ||
273497e5 | 3322 | static inline void i915_gem_context_unreference(struct intel_context *ctx) |
dce3271b | 3323 | { |
691e6415 | 3324 | kref_put(&ctx->ref, i915_gem_context_free); |
dce3271b MK |
3325 | } |
3326 | ||
273497e5 | 3327 | static inline bool i915_gem_context_is_default(const struct intel_context *c) |
3fac8978 | 3328 | { |
821d66dd | 3329 | return c->user_handle == DEFAULT_CONTEXT_HANDLE; |
3fac8978 MK |
3330 | } |
3331 | ||
84624813 BW |
3332 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
3333 | struct drm_file *file); | |
3334 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
3335 | struct drm_file *file); | |
c9dc0f35 CW |
3336 | int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, |
3337 | struct drm_file *file_priv); | |
3338 | int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, | |
3339 | struct drm_file *file_priv); | |
1286ff73 | 3340 | |
679845ed BW |
3341 | /* i915_gem_evict.c */ |
3342 | int __must_check i915_gem_evict_something(struct drm_device *dev, | |
3343 | struct i915_address_space *vm, | |
3344 | int min_size, | |
3345 | unsigned alignment, | |
3346 | unsigned cache_level, | |
d23db88c CW |
3347 | unsigned long start, |
3348 | unsigned long end, | |
1ec9e26d | 3349 | unsigned flags); |
506a8e87 | 3350 | int __must_check i915_gem_evict_for_vma(struct i915_vma *target); |
679845ed | 3351 | int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); |
1d2a314c | 3352 | |
0260c420 | 3353 | /* belongs in i915_gem_gtt.h */ |
d09105c6 | 3354 | static inline void i915_gem_chipset_flush(struct drm_device *dev) |
e76e9aeb BW |
3355 | { |
3356 | if (INTEL_INFO(dev)->gen < 6) | |
3357 | intel_gtt_chipset_flush(); | |
3358 | } | |
246cbfb5 | 3359 | |
9797fbfb | 3360 | /* i915_gem_stolen.c */ |
d713fd49 PZ |
3361 | int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv, |
3362 | struct drm_mm_node *node, u64 size, | |
3363 | unsigned alignment); | |
a9da512b PZ |
3364 | int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv, |
3365 | struct drm_mm_node *node, u64 size, | |
3366 | unsigned alignment, u64 start, | |
3367 | u64 end); | |
d713fd49 PZ |
3368 | void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv, |
3369 | struct drm_mm_node *node); | |
9797fbfb CW |
3370 | int i915_gem_init_stolen(struct drm_device *dev); |
3371 | void i915_gem_cleanup_stolen(struct drm_device *dev); | |
0104fdbb CW |
3372 | struct drm_i915_gem_object * |
3373 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); | |
866d12b4 CW |
3374 | struct drm_i915_gem_object * |
3375 | i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, | |
3376 | u32 stolen_offset, | |
3377 | u32 gtt_offset, | |
3378 | u32 size); | |
9797fbfb | 3379 | |
be6a0376 DV |
3380 | /* i915_gem_shrinker.c */ |
3381 | unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv, | |
14387540 | 3382 | unsigned long target, |
be6a0376 DV |
3383 | unsigned flags); |
3384 | #define I915_SHRINK_PURGEABLE 0x1 | |
3385 | #define I915_SHRINK_UNBOUND 0x2 | |
3386 | #define I915_SHRINK_BOUND 0x4 | |
5763ff04 | 3387 | #define I915_SHRINK_ACTIVE 0x8 |
eae2c43b | 3388 | #define I915_SHRINK_VMAPS 0x10 |
be6a0376 DV |
3389 | unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); |
3390 | void i915_gem_shrinker_init(struct drm_i915_private *dev_priv); | |
a8a40589 | 3391 | void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv); |
be6a0376 DV |
3392 | |
3393 | ||
673a394b | 3394 | /* i915_gem_tiling.c */ |
2c1792a1 | 3395 | static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
e9b73c67 | 3396 | { |
50227e1c | 3397 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e9b73c67 CW |
3398 | |
3399 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
3400 | obj->tiling_mode != I915_TILING_NONE; | |
3401 | } | |
3402 | ||
673a394b | 3403 | /* i915_gem_debug.c */ |
23bc5982 CW |
3404 | #if WATCH_LISTS |
3405 | int i915_verify_lists(struct drm_device *dev); | |
673a394b | 3406 | #else |
23bc5982 | 3407 | #define i915_verify_lists(dev) 0 |
673a394b | 3408 | #endif |
1da177e4 | 3409 | |
2017263e | 3410 | /* i915_debugfs.c */ |
27c202ad BG |
3411 | int i915_debugfs_init(struct drm_minor *minor); |
3412 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
f8c168fa | 3413 | #ifdef CONFIG_DEBUG_FS |
249e87de | 3414 | int i915_debugfs_connector_add(struct drm_connector *connector); |
07144428 DL |
3415 | void intel_display_crc_init(struct drm_device *dev); |
3416 | #else | |
101057fa DV |
3417 | static inline int i915_debugfs_connector_add(struct drm_connector *connector) |
3418 | { return 0; } | |
f8c168fa | 3419 | static inline void intel_display_crc_init(struct drm_device *dev) {} |
07144428 | 3420 | #endif |
84734a04 MK |
3421 | |
3422 | /* i915_gpu_error.c */ | |
edc3d884 MK |
3423 | __printf(2, 3) |
3424 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); | |
fc16b48b MK |
3425 | int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, |
3426 | const struct i915_error_state_file_priv *error); | |
4dc955f7 | 3427 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, |
0a4cd7c8 | 3428 | struct drm_i915_private *i915, |
4dc955f7 MK |
3429 | size_t count, loff_t pos); |
3430 | static inline void i915_error_state_buf_release( | |
3431 | struct drm_i915_error_state_buf *eb) | |
3432 | { | |
3433 | kfree(eb->buf); | |
3434 | } | |
14b730fc | 3435 | void i915_capture_error_state(struct drm_device *dev, u32 engine_mask, |
58174462 | 3436 | const char *error_msg); |
84734a04 MK |
3437 | void i915_error_state_get(struct drm_device *dev, |
3438 | struct i915_error_state_file_priv *error_priv); | |
3439 | void i915_error_state_put(struct i915_error_state_file_priv *error_priv); | |
3440 | void i915_destroy_error_state(struct drm_device *dev); | |
3441 | ||
3442 | void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); | |
0a4cd7c8 | 3443 | const char *i915_cache_level_str(struct drm_i915_private *i915, int type); |
2017263e | 3444 | |
351e3db2 | 3445 | /* i915_cmd_parser.c */ |
1ca3712c | 3446 | int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv); |
0bc40be8 TU |
3447 | int i915_cmd_parser_init_ring(struct intel_engine_cs *engine); |
3448 | void i915_cmd_parser_fini_ring(struct intel_engine_cs *engine); | |
3449 | bool i915_needs_cmd_parser(struct intel_engine_cs *engine); | |
3450 | int i915_parse_cmds(struct intel_engine_cs *engine, | |
351e3db2 | 3451 | struct drm_i915_gem_object *batch_obj, |
78a42377 | 3452 | struct drm_i915_gem_object *shadow_batch_obj, |
351e3db2 | 3453 | u32 batch_start_offset, |
b9ffd80e | 3454 | u32 batch_len, |
351e3db2 BV |
3455 | bool is_master); |
3456 | ||
317c35d1 JB |
3457 | /* i915_suspend.c */ |
3458 | extern int i915_save_state(struct drm_device *dev); | |
3459 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 | 3460 | |
0136db58 BW |
3461 | /* i915_sysfs.c */ |
3462 | void i915_setup_sysfs(struct drm_device *dev_priv); | |
3463 | void i915_teardown_sysfs(struct drm_device *dev_priv); | |
3464 | ||
f899fc64 CW |
3465 | /* intel_i2c.c */ |
3466 | extern int intel_setup_gmbus(struct drm_device *dev); | |
3467 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
88ac7939 JN |
3468 | extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, |
3469 | unsigned int pin); | |
3bd7d909 | 3470 | |
0184df46 JN |
3471 | extern struct i2c_adapter * |
3472 | intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin); | |
e957d772 CW |
3473 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
3474 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
8f375e10 | 3475 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
b8232e90 CW |
3476 | { |
3477 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
3478 | } | |
f899fc64 CW |
3479 | extern void intel_i2c_reset(struct drm_device *dev); |
3480 | ||
8b8e1a89 | 3481 | /* intel_bios.c */ |
98f3a1dc | 3482 | int intel_bios_init(struct drm_i915_private *dev_priv); |
f0067a31 | 3483 | bool intel_bios_is_valid_vbt(const void *buf, size_t size); |
3bdd14d5 | 3484 | bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv); |
5a69d13d | 3485 | bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin); |
951d9efe | 3486 | bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port); |
d6199256 | 3487 | bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port); |
7137aec1 | 3488 | bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port); |
d252bf68 SS |
3489 | bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv, |
3490 | enum port port); | |
8b8e1a89 | 3491 | |
3b617967 | 3492 | /* intel_opregion.c */ |
44834a67 | 3493 | #ifdef CONFIG_ACPI |
27d50c82 | 3494 | extern int intel_opregion_setup(struct drm_device *dev); |
44834a67 CW |
3495 | extern void intel_opregion_init(struct drm_device *dev); |
3496 | extern void intel_opregion_fini(struct drm_device *dev); | |
91d14251 | 3497 | extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv); |
9c4b0a68 JN |
3498 | extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, |
3499 | bool enable); | |
ecbc5cf3 JN |
3500 | extern int intel_opregion_notify_adapter(struct drm_device *dev, |
3501 | pci_power_t state); | |
a0562819 | 3502 | extern int intel_opregion_get_panel_type(struct drm_device *dev); |
65e082c9 | 3503 | #else |
27d50c82 | 3504 | static inline int intel_opregion_setup(struct drm_device *dev) { return 0; } |
44834a67 CW |
3505 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
3506 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } | |
91d14251 TU |
3507 | static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv) |
3508 | { | |
3509 | } | |
9c4b0a68 JN |
3510 | static inline int |
3511 | intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) | |
3512 | { | |
3513 | return 0; | |
3514 | } | |
ecbc5cf3 JN |
3515 | static inline int |
3516 | intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state) | |
3517 | { | |
3518 | return 0; | |
3519 | } | |
a0562819 VS |
3520 | static inline int intel_opregion_get_panel_type(struct drm_device *dev) |
3521 | { | |
3522 | return -ENODEV; | |
3523 | } | |
65e082c9 | 3524 | #endif |
8ee1c3db | 3525 | |
723bfd70 JB |
3526 | /* intel_acpi.c */ |
3527 | #ifdef CONFIG_ACPI | |
3528 | extern void intel_register_dsm_handler(void); | |
3529 | extern void intel_unregister_dsm_handler(void); | |
3530 | #else | |
3531 | static inline void intel_register_dsm_handler(void) { return; } | |
3532 | static inline void intel_unregister_dsm_handler(void) { return; } | |
3533 | #endif /* CONFIG_ACPI */ | |
3534 | ||
79e53945 | 3535 | /* modesetting */ |
f817586c | 3536 | extern void intel_modeset_init_hw(struct drm_device *dev); |
79e53945 | 3537 | extern void intel_modeset_init(struct drm_device *dev); |
2c7111db | 3538 | extern void intel_modeset_gem_init(struct drm_device *dev); |
79e53945 | 3539 | extern void intel_modeset_cleanup(struct drm_device *dev); |
4932e2c3 | 3540 | extern void intel_connector_unregister(struct intel_connector *); |
28d52043 | 3541 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
043e9bda | 3542 | extern void intel_display_resume(struct drm_device *dev); |
44cec740 | 3543 | extern void i915_redisable_vga(struct drm_device *dev); |
04098753 | 3544 | extern void i915_redisable_vga_power_on(struct drm_device *dev); |
91d14251 | 3545 | extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val); |
dde86e2d | 3546 | extern void intel_init_pch_refclk(struct drm_device *dev); |
ffe02b40 | 3547 | extern void intel_set_rps(struct drm_device *dev, u8 val); |
5209b1f4 ID |
3548 | extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, |
3549 | bool enable); | |
0206e353 | 3550 | extern void intel_detect_pch(struct drm_device *dev); |
0136db58 | 3551 | extern int intel_enable_rc6(const struct drm_device *dev); |
3bad0781 | 3552 | |
2911a35b | 3553 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); |
c0c7babc BW |
3554 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
3555 | struct drm_file *file); | |
b6359918 MK |
3556 | int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data, |
3557 | struct drm_file *file); | |
575155a9 | 3558 | |
6ef3d427 CW |
3559 | /* overlay */ |
3560 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); | |
edc3d884 MK |
3561 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, |
3562 | struct intel_overlay_error_state *error); | |
c4a1d9e4 CW |
3563 | |
3564 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); | |
edc3d884 | 3565 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, |
c4a1d9e4 CW |
3566 | struct drm_device *dev, |
3567 | struct intel_display_error_state *error); | |
6ef3d427 | 3568 | |
151a49d0 TR |
3569 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); |
3570 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val); | |
59de0813 JN |
3571 | |
3572 | /* intel_sideband.c */ | |
707b6e3d D |
3573 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr); |
3574 | void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val); | |
64936258 | 3575 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); |
dfb19ed2 D |
3576 | u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg); |
3577 | void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val); | |
e9f882a3 JN |
3578 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); |
3579 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
3580 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); | |
3581 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
f3419158 JB |
3582 | u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); |
3583 | void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
5e69f97f CML |
3584 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); |
3585 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); | |
59de0813 JN |
3586 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
3587 | enum intel_sbi_destination destination); | |
3588 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, | |
3589 | enum intel_sbi_destination destination); | |
e9fe51c6 SK |
3590 | u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); |
3591 | void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
0a073b84 | 3592 | |
b7fa22d8 ACO |
3593 | /* intel_dpio_phy.c */ |
3594 | void chv_set_phy_signal_level(struct intel_encoder *encoder, | |
3595 | u32 deemph_reg_value, u32 margin_reg_value, | |
3596 | bool uniq_trans_scale); | |
844b2f9a ACO |
3597 | void chv_data_lane_soft_reset(struct intel_encoder *encoder, |
3598 | bool reset); | |
419b1b7a | 3599 | void chv_phy_pre_pll_enable(struct intel_encoder *encoder); |
e7d2a717 ACO |
3600 | void chv_phy_pre_encoder_enable(struct intel_encoder *encoder); |
3601 | void chv_phy_release_cl2_override(struct intel_encoder *encoder); | |
204970b5 | 3602 | void chv_phy_post_pll_disable(struct intel_encoder *encoder); |
b7fa22d8 | 3603 | |
53d98725 ACO |
3604 | void vlv_set_phy_signal_level(struct intel_encoder *encoder, |
3605 | u32 demph_reg_value, u32 preemph_reg_value, | |
3606 | u32 uniqtranscale_reg_value, u32 tx3_demph); | |
6da2e616 | 3607 | void vlv_phy_pre_pll_enable(struct intel_encoder *encoder); |
5f68c275 | 3608 | void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder); |
0f572ebe | 3609 | void vlv_phy_reset_lanes(struct intel_encoder *encoder); |
53d98725 | 3610 | |
616bc820 VS |
3611 | int intel_gpu_freq(struct drm_i915_private *dev_priv, int val); |
3612 | int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); | |
c8d9a590 | 3613 | |
0b274481 BW |
3614 | #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) |
3615 | #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) | |
3616 | ||
3617 | #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) | |
3618 | #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) | |
3619 | #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) | |
3620 | #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) | |
3621 | ||
3622 | #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) | |
3623 | #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) | |
3624 | #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) | |
3625 | #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) | |
3626 | ||
698b3135 CW |
3627 | /* Be very careful with read/write 64-bit values. On 32-bit machines, they |
3628 | * will be implemented using 2 32-bit writes in an arbitrary order with | |
3629 | * an arbitrary delay between them. This can cause the hardware to | |
3630 | * act upon the intermediate value, possibly leading to corruption and | |
3631 | * machine death. You have been warned. | |
3632 | */ | |
0b274481 BW |
3633 | #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) |
3634 | #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) | |
cae5852d | 3635 | |
50877445 | 3636 | #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ |
acd29f7b CW |
3637 | u32 upper, lower, old_upper, loop = 0; \ |
3638 | upper = I915_READ(upper_reg); \ | |
ee0a227b | 3639 | do { \ |
acd29f7b | 3640 | old_upper = upper; \ |
ee0a227b | 3641 | lower = I915_READ(lower_reg); \ |
acd29f7b CW |
3642 | upper = I915_READ(upper_reg); \ |
3643 | } while (upper != old_upper && loop++ < 2); \ | |
ee0a227b | 3644 | (u64)upper << 32 | lower; }) |
50877445 | 3645 | |
cae5852d ZN |
3646 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
3647 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
3648 | ||
75aa3f63 VS |
3649 | #define __raw_read(x, s) \ |
3650 | static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \ | |
f0f59a00 | 3651 | i915_reg_t reg) \ |
75aa3f63 | 3652 | { \ |
f0f59a00 | 3653 | return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \ |
75aa3f63 VS |
3654 | } |
3655 | ||
3656 | #define __raw_write(x, s) \ | |
3657 | static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \ | |
f0f59a00 | 3658 | i915_reg_t reg, uint##x##_t val) \ |
75aa3f63 | 3659 | { \ |
f0f59a00 | 3660 | write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \ |
75aa3f63 VS |
3661 | } |
3662 | __raw_read(8, b) | |
3663 | __raw_read(16, w) | |
3664 | __raw_read(32, l) | |
3665 | __raw_read(64, q) | |
3666 | ||
3667 | __raw_write(8, b) | |
3668 | __raw_write(16, w) | |
3669 | __raw_write(32, l) | |
3670 | __raw_write(64, q) | |
3671 | ||
3672 | #undef __raw_read | |
3673 | #undef __raw_write | |
3674 | ||
a6111f7b CW |
3675 | /* These are untraced mmio-accessors that are only valid to be used inside |
3676 | * criticial sections inside IRQ handlers where forcewake is explicitly | |
3677 | * controlled. | |
3678 | * Think twice, and think again, before using these. | |
3679 | * Note: Should only be used between intel_uncore_forcewake_irqlock() and | |
3680 | * intel_uncore_forcewake_irqunlock(). | |
3681 | */ | |
75aa3f63 VS |
3682 | #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__)) |
3683 | #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__)) | |
a6111f7b CW |
3684 | #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__) |
3685 | ||
55bc60db VS |
3686 | /* "Broadcast RGB" property */ |
3687 | #define INTEL_BROADCAST_RGB_AUTO 0 | |
3688 | #define INTEL_BROADCAST_RGB_FULL 1 | |
3689 | #define INTEL_BROADCAST_RGB_LIMITED 2 | |
ba4f01a3 | 3690 | |
f0f59a00 | 3691 | static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev) |
766aa1c4 | 3692 | { |
666a4537 | 3693 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
766aa1c4 | 3694 | return VLV_VGACNTRL; |
92e23b99 SJ |
3695 | else if (INTEL_INFO(dev)->gen >= 5) |
3696 | return CPU_VGACNTRL; | |
766aa1c4 VS |
3697 | else |
3698 | return VGACNTRL; | |
3699 | } | |
3700 | ||
2bb4629a VS |
3701 | static inline void __user *to_user_ptr(u64 address) |
3702 | { | |
3703 | return (void __user *)(uintptr_t)address; | |
3704 | } | |
3705 | ||
df97729f ID |
3706 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) |
3707 | { | |
3708 | unsigned long j = msecs_to_jiffies(m); | |
3709 | ||
3710 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
3711 | } | |
3712 | ||
7bd0e226 DV |
3713 | static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) |
3714 | { | |
3715 | return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); | |
3716 | } | |
3717 | ||
df97729f ID |
3718 | static inline unsigned long |
3719 | timespec_to_jiffies_timeout(const struct timespec *value) | |
3720 | { | |
3721 | unsigned long j = timespec_to_jiffies(value); | |
3722 | ||
3723 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
3724 | } | |
3725 | ||
dce56b3c PZ |
3726 | /* |
3727 | * If you need to wait X milliseconds between events A and B, but event B | |
3728 | * doesn't happen exactly after event A, you record the timestamp (jiffies) of | |
3729 | * when event A happened, then just before event B you call this function and | |
3730 | * pass the timestamp as the first argument, and X as the second argument. | |
3731 | */ | |
3732 | static inline void | |
3733 | wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) | |
3734 | { | |
ec5e0cfb | 3735 | unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; |
dce56b3c PZ |
3736 | |
3737 | /* | |
3738 | * Don't re-read the value of "jiffies" every time since it may change | |
3739 | * behind our back and break the math. | |
3740 | */ | |
3741 | tmp_jiffies = jiffies; | |
3742 | target_jiffies = timestamp_jiffies + | |
3743 | msecs_to_jiffies_timeout(to_wait_ms); | |
3744 | ||
3745 | if (time_after(target_jiffies, tmp_jiffies)) { | |
ec5e0cfb ID |
3746 | remaining_jiffies = target_jiffies - tmp_jiffies; |
3747 | while (remaining_jiffies) | |
3748 | remaining_jiffies = | |
3749 | schedule_timeout_uninterruptible(remaining_jiffies); | |
dce56b3c PZ |
3750 | } |
3751 | } | |
3752 | ||
0bc40be8 | 3753 | static inline void i915_trace_irq_get(struct intel_engine_cs *engine, |
581c26e8 JH |
3754 | struct drm_i915_gem_request *req) |
3755 | { | |
0bc40be8 TU |
3756 | if (engine->trace_irq_req == NULL && engine->irq_get(engine)) |
3757 | i915_gem_request_assign(&engine->trace_irq_req, req); | |
581c26e8 JH |
3758 | } |
3759 | ||
1da177e4 | 3760 | #endif |