[linux-2.6-block.git] / drivers / gpu / drm / i915 / i915_drv.h

/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
 */
/*
 *
 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#ifndef _I915_DRV_H_
#define _I915_DRV_H_

#include "i915_reg.h"

/* General customization:
 */

#define DRIVER_AUTHOR		"Tungsten Graphics, Inc."

#define DRIVER_NAME		"i915"
#define DRIVER_DESC		"Intel Graphics"
#define DRIVER_DATE		"20060119"

enum pipe {
	PIPE_A = 0,
	PIPE_B,
};

/* Interface history:
 *
 * 1.1: Original.
 * 1.2: Add Power Management
 * 1.3: Add vblank support
 * 1.4: Fix cmdbuffer path, add heap destroy
 * 1.5: Add vblank pipe configuration
 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 *      - Support vertical blank on secondary display pipe
 */
#define DRIVER_MAJOR		1
#define DRIVER_MINOR		6
#define DRIVER_PATCHLEVEL	0

typedef struct _drm_i915_ring_buffer {
	int tail_mask;
	unsigned long Start;
	unsigned long End;
	unsigned long Size;
	u8 *virtual_start;
	int head;
	int tail;
	int space;
	drm_local_map_t map;
} drm_i915_ring_buffer_t;

struct mem_block {
	struct mem_block *next;
	struct mem_block *prev;
	int start;
	int size;
	struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
};

typedef struct _drm_i915_vbl_swap {
	struct list_head head;
	drm_drawable_t drw_id;
	unsigned int pipe;
	unsigned int sequence;
} drm_i915_vbl_swap_t;

struct intel_opregion {
	struct opregion_header *header;
	struct opregion_acpi *acpi;
	struct opregion_swsci *swsci;
	struct opregion_asle *asle;
	int enabled;
};

typedef struct drm_i915_private {
	drm_local_map_t *sarea;
	drm_local_map_t *mmio_map;

	drm_i915_sarea_t *sarea_priv;
	drm_i915_ring_buffer_t ring;

	drm_dma_handle_t *status_page_dmah;
	void *hw_status_page;
	dma_addr_t dma_status_page;
	unsigned long counter;
	unsigned int status_gfx_addr;
	drm_local_map_t hws_map;

	unsigned int cpp;
	int back_offset;
	int front_offset;
	int current_page;
	int page_flipping;

	wait_queue_head_t irq_queue;
	atomic_t irq_received;
	atomic_t irq_emitted;
	/** Protects user_irq_refcount and irq_mask_reg */
	spinlock_t user_irq_lock;
	/** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
	int user_irq_refcount;
	/** Cached value of IMR to avoid reads in updating the bitfield */
	u32 irq_mask_reg;

	int tex_lru_log_granularity;
	int allow_batchbuffer;
	struct mem_block *agp_heap;
	unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
	int vblank_pipe;

	spinlock_t swaps_lock;
	drm_i915_vbl_swap_t vbl_swaps;
	unsigned int swaps_pending;

	struct intel_opregion opregion;

	/* Register state */
	u8 saveLBB;
	u32 saveDSPACNTR;
	u32 saveDSPBCNTR;
	u32 saveDSPARB;
	u32 savePIPEACONF;
	u32 savePIPEBCONF;
	u32 savePIPEASRC;
	u32 savePIPEBSRC;
	u32 saveFPA0;
	u32 saveFPA1;
	u32 saveDPLL_A;
	u32 saveDPLL_A_MD;
	u32 saveHTOTAL_A;
	u32 saveHBLANK_A;
	u32 saveHSYNC_A;
	u32 saveVTOTAL_A;
	u32 saveVBLANK_A;
	u32 saveVSYNC_A;
	u32 saveBCLRPAT_A;
	u32 savePIPEASTAT;
	u32 saveDSPASTRIDE;
	u32 saveDSPASIZE;
	u32 saveDSPAPOS;
	u32 saveDSPAADDR;
	u32 saveDSPASURF;
	u32 saveDSPATILEOFF;
	u32 savePFIT_PGM_RATIOS;
	u32 saveBLC_PWM_CTL;
	u32 saveBLC_PWM_CTL2;
	u32 saveFPB0;
	u32 saveFPB1;
	u32 saveDPLL_B;
	u32 saveDPLL_B_MD;
	u32 saveHTOTAL_B;
	u32 saveHBLANK_B;
	u32 saveHSYNC_B;
	u32 saveVTOTAL_B;
	u32 saveVBLANK_B;
	u32 saveVSYNC_B;
	u32 saveBCLRPAT_B;
	u32 savePIPEBSTAT;
	u32 saveDSPBSTRIDE;
	u32 saveDSPBSIZE;
	u32 saveDSPBPOS;
	u32 saveDSPBADDR;
	u32 saveDSPBSURF;
	u32 saveDSPBTILEOFF;
	u32 saveVGA0;
	u32 saveVGA1;
	u32 saveVGA_PD;
	u32 saveVGACNTRL;
	u32 saveADPA;
	u32 saveLVDS;
	u32 savePP_ON_DELAYS;
	u32 savePP_OFF_DELAYS;
	u32 saveDVOA;
	u32 saveDVOB;
	u32 saveDVOC;
	u32 savePP_ON;
	u32 savePP_OFF;
	u32 savePP_CONTROL;
	u32 savePP_DIVISOR;
	u32 savePFIT_CONTROL;
	u32 save_palette_a[256];
	u32 save_palette_b[256];
	u32 saveFBC_CFB_BASE;
	u32 saveFBC_LL_BASE;
	u32 saveFBC_CONTROL;
	u32 saveFBC_CONTROL2;
	u32 saveIER;
	u32 saveIIR;
	u32 saveIMR;
	u32 saveCACHE_MODE_0;
	u32 saveD_STATE;
	u32 saveCG_2D_DIS;
	u32 saveMI_ARB_STATE;
	u32 saveSWF0[16];
	u32 saveSWF1[16];
	u32 saveSWF2[3];
	u8 saveMSR;
	u8 saveSR[8];
	u8 saveGR[25];
	u8 saveAR_INDEX;
	u8 saveAR[21];
	u8 saveDACMASK;
	u8 saveDACDATA[256*3]; /* 256 3-byte colors */
	u8 saveCR[37];
} drm_i915_private_t;

extern struct drm_ioctl_desc i915_ioctls[];
extern int i915_max_ioctl;

				/* i915_dma.c */
extern void i915_kernel_lost_context(struct drm_device * dev);
extern int i915_driver_load(struct drm_device *, unsigned long flags);
extern int i915_driver_unload(struct drm_device *);
extern void i915_driver_lastclose(struct drm_device * dev);
extern void i915_driver_preclose(struct drm_device *dev,
				 struct drm_file *file_priv);
extern int i915_driver_device_is_agp(struct drm_device * dev);
extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
			      unsigned long arg);

/* i915_irq.c */
extern int i915_irq_emit(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
extern int i915_irq_wait(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);

extern int i915_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence);
extern int i915_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
extern void i915_driver_irq_preinstall(struct drm_device * dev);
extern void i915_driver_irq_postinstall(struct drm_device * dev);
extern void i915_driver_irq_uninstall(struct drm_device * dev);
extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
extern int i915_vblank_swap(struct drm_device *dev, void *data,
			    struct drm_file *file_priv);
extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);

/* i915_mem.c */
extern int i915_mem_alloc(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
extern int i915_mem_free(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
extern int i915_mem_init_heap(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
				 struct drm_file *file_priv);
extern void i915_mem_takedown(struct mem_block **heap);
extern void i915_mem_release(struct drm_device * dev,
			     struct drm_file *file_priv, struct mem_block *heap);

/* i915_suspend.c */
extern int i915_save_state(struct drm_device *dev);
extern int i915_restore_state(struct drm_device *dev);

/* i915_opregion.c */
extern int intel_opregion_init(struct drm_device *dev);
extern void intel_opregion_free(struct drm_device *dev);
extern void opregion_asle_intr(struct drm_device *dev);
extern void opregion_enable_asle(struct drm_device *dev);

#define I915_READ(reg)          DRM_READ32(dev_priv->mmio_map, (reg))
#define I915_WRITE(reg,val)     DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
#define I915_READ16(reg)	DRM_READ16(dev_priv->mmio_map, (reg))
#define I915_WRITE16(reg,val)	DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
#define I915_READ8(reg)		DRM_READ8(dev_priv->mmio_map, (reg))
#define I915_WRITE8(reg,val)	DRM_WRITE8(dev_priv->mmio_map, (reg), (val))

#define I915_VERBOSE 0

#define RING_LOCALS	unsigned int outring, ringmask, outcount; \
                        volatile char *virt;

#define BEGIN_LP_RING(n) do {				\
	if (I915_VERBOSE)				\
		DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n));	\
	if (dev_priv->ring.space < (n)*4)		\
		i915_wait_ring(dev, (n)*4, __func__);		\
	outcount = 0;					\
	outring = dev_priv->ring.tail;			\
	ringmask = dev_priv->ring.tail_mask;		\
	virt = dev_priv->ring.virtual_start;		\
} while (0)

#define OUT_RING(n) do {					\
	if (I915_VERBOSE) DRM_DEBUG("   OUT_RING %x\n", (int)(n));	\
	*(volatile unsigned int *)(virt + outring) = (n);	\
        outcount++;						\
	outring += 4;						\
	outring &= ringmask;					\
} while (0)

#define ADVANCE_LP_RING() do {						\
	if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring);	\
	dev_priv->ring.tail = outring;					\
	dev_priv->ring.space -= outcount * 4;				\
	I915_WRITE(PRB0_TAIL, outring);			\
} while(0)

/**
 * Reads a dword out of the status page, which is written to from the command
 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
 * MI_STORE_DATA_IMM.
 *
 * The following dwords have a reserved meaning:
 * 0: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
 * 4: ring 0 head pointer
 * 5: ring 1 head pointer (915-class)
 * 6: ring 2 head pointer (915-class)
 *
 * The area from dword 0x10 to 0x3ff is available for driver usage.
 */
#define READ_HWSP(dev_priv, reg)  (((volatile u32*)(dev_priv->hw_status_page))[reg])
#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, 5)

extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);

#define IS_I830(dev) ((dev)->pci_device == 0x3577)
#define IS_845G(dev) ((dev)->pci_device == 0x2562)
#define IS_I85X(dev) ((dev)->pci_device == 0x3582)
#define IS_I855(dev) ((dev)->pci_device == 0x3582)
#define IS_I865G(dev) ((dev)->pci_device == 0x2572)

#define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
#define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
		        (dev)->pci_device == 0x27AE)
#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
		       (dev)->pci_device == 0x2982 || \
		       (dev)->pci_device == 0x2992 || \
		       (dev)->pci_device == 0x29A2 || \
		       (dev)->pci_device == 0x2A02 || \
		       (dev)->pci_device == 0x2A12 || \
		       (dev)->pci_device == 0x2A42 || \
		       (dev)->pci_device == 0x2E02 || \
		       (dev)->pci_device == 0x2E12 || \
		       (dev)->pci_device == 0x2E22)

#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)

#define IS_IGD_GM(dev) ((dev)->pci_device == 0x2A42)

#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
		     (dev)->pci_device == 0x2E12 || \
		     (dev)->pci_device == 0x2E22)

#define IS_G33(dev)    ((dev)->pci_device == 0x29C2 ||	\
			(dev)->pci_device == 0x29B2 ||	\
			(dev)->pci_device == 0x29D2)

#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
		      IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))

#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
			IS_I945GM(dev) || IS_I965GM(dev) || IS_IGD_GM(dev))

#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_IGD_GM(dev) || IS_G4X(dev))

#define PRIMARY_RINGBUFFER_SIZE         (128*1024)

#endif
Commit	Line	Data
1da177e4 LT	1	/* i915_drv.h -- Private header for the I915 driver -- linux-c --
1da177e4 LT	2	*/
0d6aa60b	3	/*
bc54fd1a	4	*
1da177e4 LT	5	* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
1da177e4 LT	6	* All Rights Reserved.
bc54fd1a DA	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a
	9	* copy of this software and associated documentation files (the
	10	* "Software"), to deal in the Software without restriction, including
	11	* without limitation the rights to use, copy, modify, merge, publish,
	12	* distribute, sub license, and/or sell copies of the Software, and to
	13	* permit persons to whom the Software is furnished to do so, subject to
	14	* the following conditions:
	15	*
	16	* The above copyright notice and this permission notice (including the
	17	* next paragraph) shall be included in all copies or substantial portions
	18	* of the Software.
	19	*
	20	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
	21	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	22	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
	23	* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
	24	* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
	25	* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
	26	* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	27	*
0d6aa60b	28	*/
1da177e4 LT	29
	30	#ifndef _I915_DRV_H_
	31	#define _I915_DRV_H_
	32
585fb111 JB	33	#include "i915_reg.h"
585fb111 JB	34
1da177e4 LT	35	/* General customization:
	36	*/
	37
	38	#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
	39
	40	#define DRIVER_NAME "i915"
	41	#define DRIVER_DESC "Intel Graphics"
de227f5f	42	#define DRIVER_DATE "20060119"
1da177e4	43
317c35d1 JB	44	enum pipe {
	45	PIPE_A = 0,
	46	PIPE_B,
	47	};
	48
1da177e4 LT	49	/* Interface history:
	50	*
	51	* 1.1: Original.
0d6aa60b DA	52	* 1.2: Add Power Management
0d6aa60b DA	53	* 1.3: Add vblank support
de227f5f	54	* 1.4: Fix cmdbuffer path, add heap destroy
702880f2	55	* 1.5: Add vblank pipe configuration
2228ed67 MCA	56	* 1.6: - New ioctl for scheduling buffer swaps on vertical blank
2228ed67 MCA	57	* - Support vertical blank on secondary display pipe
1da177e4 LT	58	*/
1da177e4 LT	59	#define DRIVER_MAJOR 1
2228ed67	60	#define DRIVER_MINOR 6
1da177e4 LT	61	#define DRIVER_PATCHLEVEL 0
1da177e4 LT	62
1da177e4 LT	63	typedef struct _drm_i915_ring_buffer {
	64	int tail_mask;
	65	unsigned long Start;
	66	unsigned long End;
	67	unsigned long Size;
	68	u8 *virtual_start;
	69	int head;
	70	int tail;
	71	int space;
	72	drm_local_map_t map;
	73	} drm_i915_ring_buffer_t;
	74
	75	struct mem_block {
	76	struct mem_block *next;
	77	struct mem_block *prev;
	78	int start;
	79	int size;
6c340eac	80	struct drm_file file_priv; / NULL: free, -1: heap, other: real files */
1da177e4 LT	81	};
1da177e4 LT	82
a6b54f3f MCA	83	typedef struct _drm_i915_vbl_swap {
	84	struct list_head head;
	85	drm_drawable_t drw_id;
af6061af	86	unsigned int pipe;
a6b54f3f MCA	87	unsigned int sequence;
	88	} drm_i915_vbl_swap_t;
	89
8ee1c3db MG	90	struct intel_opregion {
	91	struct opregion_header *header;
	92	struct opregion_acpi *acpi;
	93	struct opregion_swsci *swsci;
	94	struct opregion_asle *asle;
	95	int enabled;
	96	};
	97
1da177e4 LT	98	typedef struct drm_i915_private {
	99	drm_local_map_t *sarea;
	100	drm_local_map_t *mmio_map;
	101
	102	drm_i915_sarea_t *sarea_priv;
	103	drm_i915_ring_buffer_t ring;
	104
9c8da5eb	105	drm_dma_handle_t *status_page_dmah;
1da177e4	106	void *hw_status_page;
1da177e4	107	dma_addr_t dma_status_page;
af6061af	108	unsigned long counter;
dc7a9319 WZ	109	unsigned int status_gfx_addr;
dc7a9319 WZ	110	drm_local_map_t hws_map;
1da177e4	111
a6b54f3f	112	unsigned int cpp;
1da177e4 LT	113	int back_offset;
	114	int front_offset;
	115	int current_page;
	116	int page_flipping;
1da177e4 LT	117
	118	wait_queue_head_t irq_queue;
	119	atomic_t irq_received;
af6061af	120	atomic_t irq_emitted;
ed4cb414 EA	121	/** Protects user_irq_refcount and irq_mask_reg */
	122	spinlock_t user_irq_lock;
	123	/** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
	124	int user_irq_refcount;
	125	/** Cached value of IMR to avoid reads in updating the bitfield */
	126	u32 irq_mask_reg;
1da177e4 LT	127
	128	int tex_lru_log_granularity;
	129	int allow_batchbuffer;
	130	struct mem_block *agp_heap;
0d6aa60b	131	unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
702880f2	132	int vblank_pipe;
a6b54f3f MCA	133
	134	spinlock_t swaps_lock;
	135	drm_i915_vbl_swap_t vbl_swaps;
	136	unsigned int swaps_pending;
ba8bbcf6	137
8ee1c3db MG	138	struct intel_opregion opregion;
8ee1c3db MG	139
ba8bbcf6 JB	140	/* Register state */
	141	u8 saveLBB;
	142	u32 saveDSPACNTR;
	143	u32 saveDSPBCNTR;
e948e994	144	u32 saveDSPARB;
ba8bbcf6 JB	145	u32 savePIPEACONF;
	146	u32 savePIPEBCONF;
	147	u32 savePIPEASRC;
	148	u32 savePIPEBSRC;
	149	u32 saveFPA0;
	150	u32 saveFPA1;
	151	u32 saveDPLL_A;
	152	u32 saveDPLL_A_MD;
	153	u32 saveHTOTAL_A;
	154	u32 saveHBLANK_A;
	155	u32 saveHSYNC_A;
	156	u32 saveVTOTAL_A;
	157	u32 saveVBLANK_A;
	158	u32 saveVSYNC_A;
	159	u32 saveBCLRPAT_A;
0da3ea12	160	u32 savePIPEASTAT;
ba8bbcf6 JB	161	u32 saveDSPASTRIDE;
	162	u32 saveDSPASIZE;
	163	u32 saveDSPAPOS;
585fb111	164	u32 saveDSPAADDR;
ba8bbcf6 JB	165	u32 saveDSPASURF;
	166	u32 saveDSPATILEOFF;
	167	u32 savePFIT_PGM_RATIOS;
	168	u32 saveBLC_PWM_CTL;
	169	u32 saveBLC_PWM_CTL2;
	170	u32 saveFPB0;
	171	u32 saveFPB1;
	172	u32 saveDPLL_B;
	173	u32 saveDPLL_B_MD;
	174	u32 saveHTOTAL_B;
	175	u32 saveHBLANK_B;
	176	u32 saveHSYNC_B;
	177	u32 saveVTOTAL_B;
	178	u32 saveVBLANK_B;
	179	u32 saveVSYNC_B;
	180	u32 saveBCLRPAT_B;
0da3ea12	181	u32 savePIPEBSTAT;
ba8bbcf6 JB	182	u32 saveDSPBSTRIDE;
	183	u32 saveDSPBSIZE;
	184	u32 saveDSPBPOS;
585fb111	185	u32 saveDSPBADDR;
ba8bbcf6 JB	186	u32 saveDSPBSURF;
ba8bbcf6 JB	187	u32 saveDSPBTILEOFF;
585fb111 JB	188	u32 saveVGA0;
	189	u32 saveVGA1;
	190	u32 saveVGA_PD;
ba8bbcf6 JB	191	u32 saveVGACNTRL;
	192	u32 saveADPA;
	193	u32 saveLVDS;
585fb111 JB	194	u32 savePP_ON_DELAYS;
585fb111 JB	195	u32 savePP_OFF_DELAYS;
ba8bbcf6 JB	196	u32 saveDVOA;
	197	u32 saveDVOB;
	198	u32 saveDVOC;
	199	u32 savePP_ON;
	200	u32 savePP_OFF;
	201	u32 savePP_CONTROL;
585fb111	202	u32 savePP_DIVISOR;
ba8bbcf6 JB	203	u32 savePFIT_CONTROL;
	204	u32 save_palette_a[256];
	205	u32 save_palette_b[256];
	206	u32 saveFBC_CFB_BASE;
	207	u32 saveFBC_LL_BASE;
	208	u32 saveFBC_CONTROL;
	209	u32 saveFBC_CONTROL2;
0da3ea12 JB	210	u32 saveIER;
	211	u32 saveIIR;
	212	u32 saveIMR;
1f84e550	213	u32 saveCACHE_MODE_0;
e948e994	214	u32 saveD_STATE;
585fb111	215	u32 saveCG_2D_DIS;
1f84e550	216	u32 saveMI_ARB_STATE;
ba8bbcf6 JB	217	u32 saveSWF0[16];
	218	u32 saveSWF1[16];
	219	u32 saveSWF2[3];
	220	u8 saveMSR;
	221	u8 saveSR[8];
123f794f	222	u8 saveGR[25];
ba8bbcf6	223	u8 saveAR_INDEX;
a59e122a	224	u8 saveAR[21];
ba8bbcf6 JB	225	u8 saveDACMASK;
ba8bbcf6 JB	226	u8 saveDACDATA[2563]; / 256 3-byte colors */
a59e122a	227	u8 saveCR[37];
1da177e4 LT	228	} drm_i915_private_t;
1da177e4 LT	229
c153f45f	230	extern struct drm_ioctl_desc i915_ioctls[];
b3a83639 DA	231	extern int i915_max_ioctl;
b3a83639 DA	232
1da177e4	233	/* i915_dma.c */
84b1fd10	234	extern void i915_kernel_lost_context(struct drm_device * dev);
22eae947	235	extern int i915_driver_load(struct drm_device *, unsigned long flags);
ba8bbcf6	236	extern int i915_driver_unload(struct drm_device *);
84b1fd10	237	extern void i915_driver_lastclose(struct drm_device * dev);
6c340eac EA	238	extern void i915_driver_preclose(struct drm_device *dev,
6c340eac EA	239	struct drm_file *file_priv);
84b1fd10	240	extern int i915_driver_device_is_agp(struct drm_device * dev);
0d6aa60b DA	241	extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
0d6aa60b DA	242	unsigned long arg);
af6061af	243
1da177e4	244	/* i915_irq.c */
c153f45f EA	245	extern int i915_irq_emit(struct drm_device dev, void data,
	246	struct drm_file *file_priv);
	247	extern int i915_irq_wait(struct drm_device dev, void data,
	248	struct drm_file *file_priv);
1da177e4	249
84b1fd10 DA	250	extern int i915_driver_vblank_wait(struct drm_device dev, unsigned int sequence);
84b1fd10 DA	251	extern int i915_driver_vblank_wait2(struct drm_device dev, unsigned int sequence);
1da177e4	252	extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
84b1fd10	253	extern void i915_driver_irq_preinstall(struct drm_device * dev);
af6061af	254	extern void i915_driver_irq_postinstall(struct drm_device * dev);
84b1fd10	255	extern void i915_driver_irq_uninstall(struct drm_device * dev);
c153f45f EA	256	extern int i915_vblank_pipe_set(struct drm_device dev, void data,
	257	struct drm_file *file_priv);
	258	extern int i915_vblank_pipe_get(struct drm_device dev, void data,
	259	struct drm_file *file_priv);
	260	extern int i915_vblank_swap(struct drm_device dev, void data,
	261	struct drm_file *file_priv);
8ee1c3db	262	extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
1da177e4 LT	263
1da177e4 LT	264	/* i915_mem.c */
c153f45f EA	265	extern int i915_mem_alloc(struct drm_device dev, void data,
	266	struct drm_file *file_priv);
	267	extern int i915_mem_free(struct drm_device dev, void data,
	268	struct drm_file *file_priv);
	269	extern int i915_mem_init_heap(struct drm_device dev, void data,
	270	struct drm_file *file_priv);
	271	extern int i915_mem_destroy_heap(struct drm_device dev, void data,
	272	struct drm_file *file_priv);
1da177e4	273	extern void i915_mem_takedown(struct mem_block **heap);
84b1fd10	274	extern void i915_mem_release(struct drm_device * dev,
6c340eac	275	struct drm_file file_priv, struct mem_block heap);
1da177e4	276
317c35d1 JB	277	/* i915_suspend.c */
	278	extern int i915_save_state(struct drm_device *dev);
	279	extern int i915_restore_state(struct drm_device *dev);
	280
8ee1c3db MG	281	/* i915_opregion.c */
	282	extern int intel_opregion_init(struct drm_device *dev);
	283	extern void intel_opregion_free(struct drm_device *dev);
	284	extern void opregion_asle_intr(struct drm_device *dev);
	285	extern void opregion_enable_asle(struct drm_device *dev);
	286
0d6aa60b DA	287	#define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg))
0d6aa60b DA	288	#define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
bc5f4523	289	#define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg))
0d6aa60b	290	#define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
317c35d1 JB	291	#define I915_READ8(reg) DRM_READ8(dev_priv->mmio_map, (reg))
317c35d1 JB	292	#define I915_WRITE8(reg,val) DRM_WRITE8(dev_priv->mmio_map, (reg), (val))
1da177e4 LT	293
	294	#define I915_VERBOSE 0
	295
	296	#define RING_LOCALS unsigned int outring, ringmask, outcount; \
	297	volatile char *virt;
	298
	299	#define BEGIN_LP_RING(n) do { \
	300	if (I915_VERBOSE) \
3e684eae MN	301	DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
3e684eae MN	302	if (dev_priv->ring.space < (n)*4) \
bf9d8929	303	i915_wait_ring(dev, (n)*4, __func__); \
1da177e4 LT	304	outcount = 0; \
	305	outring = dev_priv->ring.tail; \
	306	ringmask = dev_priv->ring.tail_mask; \
	307	virt = dev_priv->ring.virtual_start; \
	308	} while (0)
	309
	310	#define OUT_RING(n) do { \
	311	if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
c29b669c	312	(volatile unsigned int )(virt + outring) = (n); \
1da177e4 LT	313	outcount++; \
	314	outring += 4; \
	315	outring &= ringmask; \
	316	} while (0)
	317
	318	#define ADVANCE_LP_RING() do { \
	319	if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
	320	dev_priv->ring.tail = outring; \
	321	dev_priv->ring.space -= outcount * 4; \
585fb111	322	I915_WRITE(PRB0_TAIL, outring); \
1da177e4 LT	323	} while(0)
1da177e4 LT	324
ba8bbcf6	325	/**
585fb111 JB	326	* Reads a dword out of the status page, which is written to from the command
	327	* queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
	328	* MI_STORE_DATA_IMM.
ba8bbcf6	329	*
585fb111 JB	330	* The following dwords have a reserved meaning:
	331	* 0: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
	332	* 4: ring 0 head pointer
	333	* 5: ring 1 head pointer (915-class)
	334	* 6: ring 2 head pointer (915-class)
ba8bbcf6	335	*
585fb111	336	* The area from dword 0x10 to 0x3ff is available for driver usage.
ba8bbcf6	337	*/
585fb111 JB	338	#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
585fb111 JB	339	#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, 5)
ba8bbcf6	340
585fb111	341	extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
ba8bbcf6 JB	342
	343	#define IS_I830(dev) ((dev)->pci_device == 0x3577)
	344	#define IS_845G(dev) ((dev)->pci_device == 0x2562)
	345	#define IS_I85X(dev) ((dev)->pci_device == 0x3582)
	346	#define IS_I855(dev) ((dev)->pci_device == 0x3582)
	347	#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
	348
4d1f7888	349	#define IS_I915G(dev) ((dev)->pci_device == 0x2582 \|\| (dev)->pci_device == 0x258a)
ba8bbcf6 JB	350	#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
ba8bbcf6 JB	351	#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
3bf48468 JB	352	#define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 \|\|\
3bf48468 JB	353	(dev)->pci_device == 0x27AE)
ba8bbcf6 JB	354	#define IS_I965G(dev) ((dev)->pci_device == 0x2972 \|\| \
	355	(dev)->pci_device == 0x2982 \|\| \
	356	(dev)->pci_device == 0x2992 \|\| \
	357	(dev)->pci_device == 0x29A2 \|\| \
	358	(dev)->pci_device == 0x2A02 \|\| \
5f5f9d4c	359	(dev)->pci_device == 0x2A12 \|\| \
d3adbc0c ZW	360	(dev)->pci_device == 0x2A42 \|\| \
	361	(dev)->pci_device == 0x2E02 \|\| \
	362	(dev)->pci_device == 0x2E12 \|\| \
	363	(dev)->pci_device == 0x2E22)
ba8bbcf6 JB	364
	365	#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
	366
5f5f9d4c ZW	367	#define IS_IGD_GM(dev) ((dev)->pci_device == 0x2A42)
5f5f9d4c ZW	368
d3adbc0c ZW	369	#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 \|\| \
	370	(dev)->pci_device == 0x2E12 \|\| \
	371	(dev)->pci_device == 0x2E22)
	372
ba8bbcf6 JB	373	#define IS_G33(dev) ((dev)->pci_device == 0x29C2 \|\| \
	374	(dev)->pci_device == 0x29B2 \|\| \
	375	(dev)->pci_device == 0x29D2)
	376
	377	#define IS_I9XX(dev) (IS_I915G(dev) \|\| IS_I915GM(dev) \|\| IS_I945G(dev) \|\| \
	378	IS_I945GM(dev) \|\| IS_I965G(dev) \|\| IS_G33(dev))
	379
	380	#define IS_MOBILE(dev) (IS_I830(dev) \|\| IS_I85X(dev) \|\| IS_I915GM(dev) \|\| \
5f5f9d4c	381	IS_I945GM(dev) \|\| IS_I965GM(dev) \|\| IS_IGD_GM(dev))
ba8bbcf6	382
d3adbc0c	383	#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) \|\| IS_IGD_GM(dev) \|\| IS_G4X(dev))
b39d50e5	384
ba8bbcf6	385	#define PRIMARY_RINGBUFFER_SIZE (128*1024)
0d6aa60b	386
1da177e4	387	#endif