Commit | Line | Data |
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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
585fb111 | 33 | #include "i915_reg.h" |
79e53945 | 34 | #include "intel_bios.h" |
8187a2b7 | 35 | #include "intel_ringbuffer.h" |
0839ccb8 | 36 | #include <linux/io-mapping.h> |
585fb111 | 37 | |
1da177e4 LT |
38 | /* General customization: |
39 | */ | |
40 | ||
41 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." | |
42 | ||
43 | #define DRIVER_NAME "i915" | |
44 | #define DRIVER_DESC "Intel Graphics" | |
673a394b | 45 | #define DRIVER_DATE "20080730" |
1da177e4 | 46 | |
317c35d1 JB |
47 | enum pipe { |
48 | PIPE_A = 0, | |
49 | PIPE_B, | |
50 | }; | |
51 | ||
80824003 JB |
52 | enum plane { |
53 | PLANE_A = 0, | |
54 | PLANE_B, | |
55 | }; | |
56 | ||
52440211 KP |
57 | #define I915_NUM_PIPE 2 |
58 | ||
62fdfeaf EA |
59 | #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) |
60 | ||
1da177e4 LT |
61 | /* Interface history: |
62 | * | |
63 | * 1.1: Original. | |
0d6aa60b DA |
64 | * 1.2: Add Power Management |
65 | * 1.3: Add vblank support | |
de227f5f | 66 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 67 | * 1.5: Add vblank pipe configuration |
2228ed67 MCA |
68 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
69 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
70 | */ |
71 | #define DRIVER_MAJOR 1 | |
2228ed67 | 72 | #define DRIVER_MINOR 6 |
1da177e4 LT |
73 | #define DRIVER_PATCHLEVEL 0 |
74 | ||
673a394b EA |
75 | #define WATCH_COHERENCY 0 |
76 | #define WATCH_BUF 0 | |
77 | #define WATCH_EXEC 0 | |
78 | #define WATCH_LRU 0 | |
79 | #define WATCH_RELOC 0 | |
80 | #define WATCH_INACTIVE 0 | |
81 | #define WATCH_PWRITE 0 | |
82 | ||
71acb5eb DA |
83 | #define I915_GEM_PHYS_CURSOR_0 1 |
84 | #define I915_GEM_PHYS_CURSOR_1 2 | |
85 | #define I915_GEM_PHYS_OVERLAY_REGS 3 | |
86 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) | |
87 | ||
88 | struct drm_i915_gem_phys_object { | |
89 | int id; | |
90 | struct page **page_list; | |
91 | drm_dma_handle_t *handle; | |
92 | struct drm_gem_object *cur_obj; | |
93 | }; | |
94 | ||
1da177e4 LT |
95 | struct mem_block { |
96 | struct mem_block *next; | |
97 | struct mem_block *prev; | |
98 | int start; | |
99 | int size; | |
6c340eac | 100 | struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ |
1da177e4 LT |
101 | }; |
102 | ||
0a3e67a4 JB |
103 | struct opregion_header; |
104 | struct opregion_acpi; | |
105 | struct opregion_swsci; | |
106 | struct opregion_asle; | |
107 | ||
8ee1c3db MG |
108 | struct intel_opregion { |
109 | struct opregion_header *header; | |
110 | struct opregion_acpi *acpi; | |
111 | struct opregion_swsci *swsci; | |
112 | struct opregion_asle *asle; | |
44834a67 | 113 | void *vbt; |
8ee1c3db | 114 | }; |
44834a67 | 115 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 116 | |
6ef3d427 CW |
117 | struct intel_overlay; |
118 | struct intel_overlay_error_state; | |
119 | ||
7c1c2871 DA |
120 | struct drm_i915_master_private { |
121 | drm_local_map_t *sarea; | |
122 | struct _drm_i915_sarea *sarea_priv; | |
123 | }; | |
de151cf6 JB |
124 | #define I915_FENCE_REG_NONE -1 |
125 | ||
126 | struct drm_i915_fence_reg { | |
127 | struct drm_gem_object *obj; | |
007cc8ac | 128 | struct list_head lru_list; |
de151cf6 | 129 | }; |
7c1c2871 | 130 | |
9b9d172d | 131 | struct sdvo_device_mapping { |
132 | u8 dvo_port; | |
133 | u8 slave_addr; | |
134 | u8 dvo_wiring; | |
135 | u8 initialized; | |
b1083333 | 136 | u8 ddc_pin; |
9b9d172d | 137 | }; |
138 | ||
63eeaf38 JB |
139 | struct drm_i915_error_state { |
140 | u32 eir; | |
141 | u32 pgtbl_er; | |
142 | u32 pipeastat; | |
143 | u32 pipebstat; | |
144 | u32 ipeir; | |
145 | u32 ipehr; | |
146 | u32 instdone; | |
147 | u32 acthd; | |
148 | u32 instpm; | |
149 | u32 instps; | |
150 | u32 instdone1; | |
151 | u32 seqno; | |
9df30794 | 152 | u64 bbaddr; |
63eeaf38 | 153 | struct timeval time; |
9df30794 CW |
154 | struct drm_i915_error_object { |
155 | int page_count; | |
156 | u32 gtt_offset; | |
157 | u32 *pages[0]; | |
158 | } *ringbuffer, *batchbuffer[2]; | |
159 | struct drm_i915_error_buffer { | |
160 | size_t size; | |
161 | u32 name; | |
162 | u32 seqno; | |
163 | u32 gtt_offset; | |
164 | u32 read_domains; | |
165 | u32 write_domain; | |
166 | u32 fence_reg; | |
167 | s32 pinned:2; | |
168 | u32 tiling:2; | |
169 | u32 dirty:1; | |
170 | u32 purgeable:1; | |
171 | } *active_bo; | |
172 | u32 active_bo_count; | |
6ef3d427 | 173 | struct intel_overlay_error_state *overlay; |
63eeaf38 JB |
174 | }; |
175 | ||
e70236a8 JB |
176 | struct drm_i915_display_funcs { |
177 | void (*dpms)(struct drm_crtc *crtc, int mode); | |
ee5382ae | 178 | bool (*fbc_enabled)(struct drm_device *dev); |
e70236a8 JB |
179 | void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); |
180 | void (*disable_fbc)(struct drm_device *dev); | |
181 | int (*get_display_clock_speed)(struct drm_device *dev); | |
182 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
183 | void (*update_wm)(struct drm_device *dev, int planea_clock, | |
fa143215 ZY |
184 | int planeb_clock, int sr_hdisplay, int sr_htotal, |
185 | int pixel_size); | |
e70236a8 JB |
186 | /* clock updates for mode set */ |
187 | /* cursor updates */ | |
188 | /* render clock increase/decrease */ | |
189 | /* display clock increase/decrease */ | |
190 | /* pll clock increase/decrease */ | |
191 | /* clock gating init */ | |
192 | }; | |
193 | ||
cfdf1fa2 | 194 | struct intel_device_info { |
c96c3a8c | 195 | u8 gen; |
cfdf1fa2 KH |
196 | u8 is_mobile : 1; |
197 | u8 is_i8xx : 1; | |
5ce8ba7c | 198 | u8 is_i85x : 1; |
cfdf1fa2 KH |
199 | u8 is_i915g : 1; |
200 | u8 is_i9xx : 1; | |
201 | u8 is_i945gm : 1; | |
202 | u8 is_i965g : 1; | |
203 | u8 is_i965gm : 1; | |
204 | u8 is_g33 : 1; | |
205 | u8 need_gfx_hws : 1; | |
206 | u8 is_g4x : 1; | |
207 | u8 is_pineview : 1; | |
534843da CW |
208 | u8 is_broadwater : 1; |
209 | u8 is_crestline : 1; | |
cfdf1fa2 KH |
210 | u8 is_ironlake : 1; |
211 | u8 has_fbc : 1; | |
212 | u8 has_rc6 : 1; | |
213 | u8 has_pipe_cxsr : 1; | |
214 | u8 has_hotplug : 1; | |
b295d1b6 | 215 | u8 cursor_needs_physical : 1; |
cfdf1fa2 KH |
216 | }; |
217 | ||
b5e50c3f JB |
218 | enum no_fbc_reason { |
219 | FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ | |
220 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ | |
221 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ | |
222 | FBC_BAD_PLANE, /* fbc not supported on plane */ | |
223 | FBC_NOT_TILED, /* buffer not tiled */ | |
9c928d16 | 224 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ |
b5e50c3f JB |
225 | }; |
226 | ||
3bad0781 ZW |
227 | enum intel_pch { |
228 | PCH_IBX, /* Ibexpeak PCH */ | |
229 | PCH_CPT, /* Cougarpoint PCH */ | |
230 | }; | |
231 | ||
b690e96c JB |
232 | #define QUIRK_PIPEA_FORCE (1<<0) |
233 | ||
8be48d92 | 234 | struct intel_fbdev; |
38651674 | 235 | |
1da177e4 | 236 | typedef struct drm_i915_private { |
673a394b EA |
237 | struct drm_device *dev; |
238 | ||
cfdf1fa2 KH |
239 | const struct intel_device_info *info; |
240 | ||
ac5c4e76 DA |
241 | int has_gem; |
242 | ||
3043c60c | 243 | void __iomem *regs; |
1da177e4 | 244 | |
ec2a4c3f | 245 | struct pci_dev *bridge_dev; |
8187a2b7 | 246 | struct intel_ring_buffer render_ring; |
d1b851fc | 247 | struct intel_ring_buffer bsd_ring; |
6f392d54 | 248 | uint32_t next_seqno; |
1da177e4 | 249 | |
9c8da5eb | 250 | drm_dma_handle_t *status_page_dmah; |
e552eb70 | 251 | void *seqno_page; |
1da177e4 | 252 | dma_addr_t dma_status_page; |
0a3e67a4 | 253 | uint32_t counter; |
e552eb70 | 254 | unsigned int seqno_gfx_addr; |
dc7a9319 | 255 | drm_local_map_t hws_map; |
e552eb70 | 256 | struct drm_gem_object *seqno_obj; |
97f5ab66 | 257 | struct drm_gem_object *pwrctx; |
aa40d6bb | 258 | struct drm_gem_object *renderctx; |
1da177e4 | 259 | |
d7658989 JB |
260 | struct resource mch_res; |
261 | ||
a6b54f3f | 262 | unsigned int cpp; |
1da177e4 LT |
263 | int back_offset; |
264 | int front_offset; | |
265 | int current_page; | |
266 | int page_flipping; | |
be282fd4 JB |
267 | #define I915_DEBUG_READ (1<<0) |
268 | #define I915_DEBUG_WRITE (1<<1) | |
269 | unsigned long debug_flags; | |
1da177e4 LT |
270 | |
271 | wait_queue_head_t irq_queue; | |
272 | atomic_t irq_received; | |
ed4cb414 EA |
273 | /** Protects user_irq_refcount and irq_mask_reg */ |
274 | spinlock_t user_irq_lock; | |
9d34e5db | 275 | u32 trace_irq_seqno; |
ed4cb414 EA |
276 | /** Cached value of IMR to avoid reads in updating the bitfield */ |
277 | u32 irq_mask_reg; | |
7c463586 | 278 | u32 pipestat[2]; |
f2b115e6 | 279 | /** splitted irq regs for graphics and display engine on Ironlake, |
036a4a7d ZW |
280 | irq_mask_reg is still used for display irq. */ |
281 | u32 gt_irq_mask_reg; | |
282 | u32 gt_irq_enable_reg; | |
283 | u32 de_irq_enable_reg; | |
c650156a ZW |
284 | u32 pch_irq_mask_reg; |
285 | u32 pch_irq_enable_reg; | |
1da177e4 | 286 | |
5ca58282 JB |
287 | u32 hotplug_supported_mask; |
288 | struct work_struct hotplug_work; | |
289 | ||
1da177e4 LT |
290 | int tex_lru_log_granularity; |
291 | int allow_batchbuffer; | |
292 | struct mem_block *agp_heap; | |
0d6aa60b | 293 | unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; |
702880f2 | 294 | int vblank_pipe; |
a3524f1b | 295 | int num_pipe; |
a6b54f3f | 296 | |
f65d9421 BG |
297 | /* For hangcheck timer */ |
298 | #define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */ | |
299 | struct timer_list hangcheck_timer; | |
300 | int hangcheck_count; | |
301 | uint32_t last_acthd; | |
cbb465e7 CW |
302 | uint32_t last_instdone; |
303 | uint32_t last_instdone1; | |
f65d9421 | 304 | |
79e53945 JB |
305 | struct drm_mm vram; |
306 | ||
80824003 JB |
307 | unsigned long cfb_size; |
308 | unsigned long cfb_pitch; | |
309 | int cfb_fence; | |
310 | int cfb_plane; | |
311 | ||
79e53945 JB |
312 | int irq_enabled; |
313 | ||
8ee1c3db MG |
314 | struct intel_opregion opregion; |
315 | ||
02e792fb DV |
316 | /* overlay */ |
317 | struct intel_overlay *overlay; | |
318 | ||
79e53945 JB |
319 | /* LVDS info */ |
320 | int backlight_duty_cycle; /* restore backlight to this value */ | |
321 | bool panel_wants_dither; | |
322 | struct drm_display_mode *panel_fixed_mode; | |
88631706 ML |
323 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
324 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
79e53945 JB |
325 | |
326 | /* Feature bits from the VBIOS */ | |
95281e35 HE |
327 | unsigned int int_tv_support:1; |
328 | unsigned int lvds_dither:1; | |
329 | unsigned int lvds_vbt:1; | |
330 | unsigned int int_crt_support:1; | |
43565a06 | 331 | unsigned int lvds_use_ssc:1; |
32f9d658 | 332 | unsigned int edp_support:1; |
43565a06 | 333 | int lvds_ssc_freq; |
500a8cc4 | 334 | int edp_bpp; |
79e53945 | 335 | |
c1c7af60 JB |
336 | struct notifier_block lid_notifier; |
337 | ||
29874f44 | 338 | int crt_ddc_bus; /* 0 = unknown, else GPIO to use for CRT DDC */ |
de151cf6 JB |
339 | struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */ |
340 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ | |
341 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ | |
342 | ||
95534263 | 343 | unsigned int fsb_freq, mem_freq, is_ddr3; |
7662c8bd | 344 | |
63eeaf38 JB |
345 | spinlock_t error_lock; |
346 | struct drm_i915_error_state *first_error; | |
8a905236 | 347 | struct work_struct error_work; |
9c9fe1f8 | 348 | struct workqueue_struct *wq; |
63eeaf38 | 349 | |
e70236a8 JB |
350 | /* Display functions */ |
351 | struct drm_i915_display_funcs display; | |
352 | ||
3bad0781 ZW |
353 | /* PCH chipset type */ |
354 | enum intel_pch pch_type; | |
355 | ||
b690e96c JB |
356 | unsigned long quirks; |
357 | ||
ba8bbcf6 | 358 | /* Register state */ |
c9354c85 | 359 | bool modeset_on_lid; |
ba8bbcf6 JB |
360 | u8 saveLBB; |
361 | u32 saveDSPACNTR; | |
362 | u32 saveDSPBCNTR; | |
e948e994 | 363 | u32 saveDSPARB; |
461cba2d | 364 | u32 saveHWS; |
ba8bbcf6 JB |
365 | u32 savePIPEACONF; |
366 | u32 savePIPEBCONF; | |
367 | u32 savePIPEASRC; | |
368 | u32 savePIPEBSRC; | |
369 | u32 saveFPA0; | |
370 | u32 saveFPA1; | |
371 | u32 saveDPLL_A; | |
372 | u32 saveDPLL_A_MD; | |
373 | u32 saveHTOTAL_A; | |
374 | u32 saveHBLANK_A; | |
375 | u32 saveHSYNC_A; | |
376 | u32 saveVTOTAL_A; | |
377 | u32 saveVBLANK_A; | |
378 | u32 saveVSYNC_A; | |
379 | u32 saveBCLRPAT_A; | |
5586c8bc | 380 | u32 saveTRANSACONF; |
42048781 ZW |
381 | u32 saveTRANS_HTOTAL_A; |
382 | u32 saveTRANS_HBLANK_A; | |
383 | u32 saveTRANS_HSYNC_A; | |
384 | u32 saveTRANS_VTOTAL_A; | |
385 | u32 saveTRANS_VBLANK_A; | |
386 | u32 saveTRANS_VSYNC_A; | |
0da3ea12 | 387 | u32 savePIPEASTAT; |
ba8bbcf6 JB |
388 | u32 saveDSPASTRIDE; |
389 | u32 saveDSPASIZE; | |
390 | u32 saveDSPAPOS; | |
585fb111 | 391 | u32 saveDSPAADDR; |
ba8bbcf6 JB |
392 | u32 saveDSPASURF; |
393 | u32 saveDSPATILEOFF; | |
394 | u32 savePFIT_PGM_RATIOS; | |
0eb96d6e | 395 | u32 saveBLC_HIST_CTL; |
ba8bbcf6 JB |
396 | u32 saveBLC_PWM_CTL; |
397 | u32 saveBLC_PWM_CTL2; | |
42048781 ZW |
398 | u32 saveBLC_CPU_PWM_CTL; |
399 | u32 saveBLC_CPU_PWM_CTL2; | |
ba8bbcf6 JB |
400 | u32 saveFPB0; |
401 | u32 saveFPB1; | |
402 | u32 saveDPLL_B; | |
403 | u32 saveDPLL_B_MD; | |
404 | u32 saveHTOTAL_B; | |
405 | u32 saveHBLANK_B; | |
406 | u32 saveHSYNC_B; | |
407 | u32 saveVTOTAL_B; | |
408 | u32 saveVBLANK_B; | |
409 | u32 saveVSYNC_B; | |
410 | u32 saveBCLRPAT_B; | |
5586c8bc | 411 | u32 saveTRANSBCONF; |
42048781 ZW |
412 | u32 saveTRANS_HTOTAL_B; |
413 | u32 saveTRANS_HBLANK_B; | |
414 | u32 saveTRANS_HSYNC_B; | |
415 | u32 saveTRANS_VTOTAL_B; | |
416 | u32 saveTRANS_VBLANK_B; | |
417 | u32 saveTRANS_VSYNC_B; | |
0da3ea12 | 418 | u32 savePIPEBSTAT; |
ba8bbcf6 JB |
419 | u32 saveDSPBSTRIDE; |
420 | u32 saveDSPBSIZE; | |
421 | u32 saveDSPBPOS; | |
585fb111 | 422 | u32 saveDSPBADDR; |
ba8bbcf6 JB |
423 | u32 saveDSPBSURF; |
424 | u32 saveDSPBTILEOFF; | |
585fb111 JB |
425 | u32 saveVGA0; |
426 | u32 saveVGA1; | |
427 | u32 saveVGA_PD; | |
ba8bbcf6 JB |
428 | u32 saveVGACNTRL; |
429 | u32 saveADPA; | |
430 | u32 saveLVDS; | |
585fb111 JB |
431 | u32 savePP_ON_DELAYS; |
432 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
433 | u32 saveDVOA; |
434 | u32 saveDVOB; | |
435 | u32 saveDVOC; | |
436 | u32 savePP_ON; | |
437 | u32 savePP_OFF; | |
438 | u32 savePP_CONTROL; | |
585fb111 | 439 | u32 savePP_DIVISOR; |
ba8bbcf6 JB |
440 | u32 savePFIT_CONTROL; |
441 | u32 save_palette_a[256]; | |
442 | u32 save_palette_b[256]; | |
06027f91 | 443 | u32 saveDPFC_CB_BASE; |
ba8bbcf6 JB |
444 | u32 saveFBC_CFB_BASE; |
445 | u32 saveFBC_LL_BASE; | |
446 | u32 saveFBC_CONTROL; | |
447 | u32 saveFBC_CONTROL2; | |
0da3ea12 JB |
448 | u32 saveIER; |
449 | u32 saveIIR; | |
450 | u32 saveIMR; | |
42048781 ZW |
451 | u32 saveDEIER; |
452 | u32 saveDEIMR; | |
453 | u32 saveGTIER; | |
454 | u32 saveGTIMR; | |
455 | u32 saveFDI_RXA_IMR; | |
456 | u32 saveFDI_RXB_IMR; | |
1f84e550 | 457 | u32 saveCACHE_MODE_0; |
1f84e550 | 458 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
459 | u32 saveSWF0[16]; |
460 | u32 saveSWF1[16]; | |
461 | u32 saveSWF2[3]; | |
462 | u8 saveMSR; | |
463 | u8 saveSR[8]; | |
123f794f | 464 | u8 saveGR[25]; |
ba8bbcf6 | 465 | u8 saveAR_INDEX; |
a59e122a | 466 | u8 saveAR[21]; |
ba8bbcf6 | 467 | u8 saveDACMASK; |
a59e122a | 468 | u8 saveCR[37]; |
79f11c19 | 469 | uint64_t saveFENCE[16]; |
1fd1c624 EA |
470 | u32 saveCURACNTR; |
471 | u32 saveCURAPOS; | |
472 | u32 saveCURABASE; | |
473 | u32 saveCURBCNTR; | |
474 | u32 saveCURBPOS; | |
475 | u32 saveCURBBASE; | |
476 | u32 saveCURSIZE; | |
a4fc5ed6 KP |
477 | u32 saveDP_B; |
478 | u32 saveDP_C; | |
479 | u32 saveDP_D; | |
480 | u32 savePIPEA_GMCH_DATA_M; | |
481 | u32 savePIPEB_GMCH_DATA_M; | |
482 | u32 savePIPEA_GMCH_DATA_N; | |
483 | u32 savePIPEB_GMCH_DATA_N; | |
484 | u32 savePIPEA_DP_LINK_M; | |
485 | u32 savePIPEB_DP_LINK_M; | |
486 | u32 savePIPEA_DP_LINK_N; | |
487 | u32 savePIPEB_DP_LINK_N; | |
42048781 ZW |
488 | u32 saveFDI_RXA_CTL; |
489 | u32 saveFDI_TXA_CTL; | |
490 | u32 saveFDI_RXB_CTL; | |
491 | u32 saveFDI_TXB_CTL; | |
492 | u32 savePFA_CTL_1; | |
493 | u32 savePFB_CTL_1; | |
494 | u32 savePFA_WIN_SZ; | |
495 | u32 savePFB_WIN_SZ; | |
496 | u32 savePFA_WIN_POS; | |
497 | u32 savePFB_WIN_POS; | |
5586c8bc ZW |
498 | u32 savePCH_DREF_CONTROL; |
499 | u32 saveDISP_ARB_CTL; | |
500 | u32 savePIPEA_DATA_M1; | |
501 | u32 savePIPEA_DATA_N1; | |
502 | u32 savePIPEA_LINK_M1; | |
503 | u32 savePIPEA_LINK_N1; | |
504 | u32 savePIPEB_DATA_M1; | |
505 | u32 savePIPEB_DATA_N1; | |
506 | u32 savePIPEB_LINK_M1; | |
507 | u32 savePIPEB_LINK_N1; | |
b5b72e89 | 508 | u32 saveMCHBAR_RENDER_STANDBY; |
673a394b EA |
509 | |
510 | struct { | |
511 | struct drm_mm gtt_space; | |
512 | ||
0839ccb8 | 513 | struct io_mapping *gtt_mapping; |
ab657db1 | 514 | int gtt_mtrr; |
0839ccb8 | 515 | |
31169714 CW |
516 | /** |
517 | * Membership on list of all loaded devices, used to evict | |
518 | * inactive buffers under memory pressure. | |
519 | * | |
520 | * Modifications should only be done whilst holding the | |
521 | * shrink_list_lock spinlock. | |
522 | */ | |
523 | struct list_head shrink_list; | |
524 | ||
5e118f41 | 525 | spinlock_t active_list_lock; |
673a394b EA |
526 | |
527 | /** | |
528 | * List of objects which are not in the ringbuffer but which | |
529 | * still have a write_domain which needs to be flushed before | |
530 | * unbinding. | |
531 | * | |
ce44b0ea EA |
532 | * last_rendering_seqno is 0 while an object is in this list. |
533 | * | |
673a394b EA |
534 | * A reference is held on the buffer while on this list. |
535 | */ | |
536 | struct list_head flushing_list; | |
537 | ||
99fcb766 DV |
538 | /** |
539 | * List of objects currently pending a GPU write flush. | |
540 | * | |
541 | * All elements on this list will belong to either the | |
542 | * active_list or flushing_list, last_rendering_seqno can | |
543 | * be used to differentiate between the two elements. | |
544 | */ | |
545 | struct list_head gpu_write_list; | |
546 | ||
673a394b EA |
547 | /** |
548 | * LRU list of objects which are not in the ringbuffer and | |
549 | * are ready to unbind, but are still in the GTT. | |
550 | * | |
ce44b0ea EA |
551 | * last_rendering_seqno is 0 while an object is in this list. |
552 | * | |
673a394b EA |
553 | * A reference is not held on the buffer while on this list, |
554 | * as merely being GTT-bound shouldn't prevent its being | |
555 | * freed, and we'll pull it off the list in the free path. | |
556 | */ | |
557 | struct list_head inactive_list; | |
558 | ||
a09ba7fa EA |
559 | /** LRU list of objects with fence regs on them. */ |
560 | struct list_head fence_list; | |
561 | ||
be72615b CW |
562 | /** |
563 | * List of objects currently pending being freed. | |
564 | * | |
565 | * These objects are no longer in use, but due to a signal | |
566 | * we were prevented from freeing them at the appointed time. | |
567 | */ | |
568 | struct list_head deferred_free_list; | |
569 | ||
673a394b EA |
570 | /** |
571 | * We leave the user IRQ off as much as possible, | |
572 | * but this means that requests will finish and never | |
573 | * be retired once the system goes idle. Set a timer to | |
574 | * fire periodically while the ring is running. When it | |
575 | * fires, go retire requests. | |
576 | */ | |
577 | struct delayed_work retire_work; | |
578 | ||
673a394b EA |
579 | /** |
580 | * Waiting sequence number, if any | |
581 | */ | |
582 | uint32_t waiting_gem_seqno; | |
583 | ||
584 | /** | |
585 | * Last seq seen at irq time | |
586 | */ | |
587 | uint32_t irq_gem_seqno; | |
588 | ||
589 | /** | |
590 | * Flag if the X Server, and thus DRM, is not currently in | |
591 | * control of the device. | |
592 | * | |
593 | * This is set between LeaveVT and EnterVT. It needs to be | |
594 | * replaced with a semaphore. It also needs to be | |
595 | * transitioned away from for kernel modesetting. | |
596 | */ | |
597 | int suspended; | |
598 | ||
599 | /** | |
600 | * Flag if the hardware appears to be wedged. | |
601 | * | |
602 | * This is set when attempts to idle the device timeout. | |
603 | * It prevents command submission from occuring and makes | |
604 | * every pending request fail | |
605 | */ | |
ba1234d1 | 606 | atomic_t wedged; |
673a394b EA |
607 | |
608 | /** Bit 6 swizzling required for X tiling */ | |
609 | uint32_t bit_6_swizzle_x; | |
610 | /** Bit 6 swizzling required for Y tiling */ | |
611 | uint32_t bit_6_swizzle_y; | |
71acb5eb DA |
612 | |
613 | /* storage for physical objects */ | |
614 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; | |
673a394b | 615 | } mm; |
9b9d172d | 616 | struct sdvo_device_mapping sdvo_mappings[2]; |
a3e17eb8 ZY |
617 | /* indicate whether the LVDS_BORDER should be enabled or not */ |
618 | unsigned int lvds_border_bits; | |
1d8e1c75 CW |
619 | /* Panel fitter placement and size for Ironlake+ */ |
620 | u32 pch_pf_pos, pch_pf_size; | |
652c393a | 621 | |
6b95a207 KH |
622 | struct drm_crtc *plane_to_crtc_mapping[2]; |
623 | struct drm_crtc *pipe_to_crtc_mapping[2]; | |
624 | wait_queue_head_t pending_flip_queue; | |
1afe3e9d | 625 | bool flip_pending_is_done; |
6b95a207 | 626 | |
652c393a JB |
627 | /* Reclocking support */ |
628 | bool render_reclock_avail; | |
629 | bool lvds_downclock_avail; | |
bfac4d67 ZY |
630 | /* indicate whether the LVDS EDID is OK */ |
631 | bool lvds_edid_good; | |
18f9ed12 ZY |
632 | /* indicates the reduced downclock for LVDS*/ |
633 | int lvds_downclock; | |
652c393a JB |
634 | struct work_struct idle_work; |
635 | struct timer_list idle_timer; | |
636 | bool busy; | |
637 | u16 orig_clock; | |
6363ee6f ZY |
638 | int child_dev_num; |
639 | struct child_device_config *child_dev; | |
a2565377 | 640 | struct drm_connector *int_lvds_connector; |
f97108d1 | 641 | |
c4804411 | 642 | bool mchbar_need_disable; |
f97108d1 JB |
643 | |
644 | u8 cur_delay; | |
645 | u8 min_delay; | |
646 | u8 max_delay; | |
7648fa99 JB |
647 | u8 fmax; |
648 | u8 fstart; | |
649 | ||
650 | u64 last_count1; | |
651 | unsigned long last_time1; | |
652 | u64 last_count2; | |
653 | struct timespec last_time2; | |
654 | unsigned long gfx_power; | |
655 | int c_m; | |
656 | int r_t; | |
657 | u8 corr; | |
658 | spinlock_t *mchdev_lock; | |
b5e50c3f JB |
659 | |
660 | enum no_fbc_reason no_fbc_reason; | |
38651674 | 661 | |
20bf377e JB |
662 | struct drm_mm_node *compressed_fb; |
663 | struct drm_mm_node *compressed_llb; | |
34dc4d44 | 664 | |
8be48d92 DA |
665 | /* list of fbdev register on this device */ |
666 | struct intel_fbdev *fbdev; | |
1da177e4 LT |
667 | } drm_i915_private_t; |
668 | ||
673a394b EA |
669 | /** driver private structure attached to each drm_gem_object */ |
670 | struct drm_i915_gem_object { | |
c397b908 | 671 | struct drm_gem_object base; |
673a394b EA |
672 | |
673 | /** Current space allocated to this object in the GTT, if any. */ | |
674 | struct drm_mm_node *gtt_space; | |
675 | ||
676 | /** This object's place on the active/flushing/inactive lists */ | |
677 | struct list_head list; | |
99fcb766 DV |
678 | /** This object's place on GPU write list */ |
679 | struct list_head gpu_write_list; | |
cd377ea9 CW |
680 | /** This object's place on eviction list */ |
681 | struct list_head evict_list; | |
673a394b EA |
682 | |
683 | /** | |
684 | * This is set if the object is on the active or flushing lists | |
685 | * (has pending rendering), and is not set if it's on inactive (ready | |
686 | * to be unbound). | |
687 | */ | |
778c3544 | 688 | unsigned int active : 1; |
673a394b EA |
689 | |
690 | /** | |
691 | * This is set if the object has been written to since last bound | |
692 | * to the GTT | |
693 | */ | |
778c3544 DV |
694 | unsigned int dirty : 1; |
695 | ||
696 | /** | |
697 | * Fence register bits (if any) for this object. Will be set | |
698 | * as needed when mapped into the GTT. | |
699 | * Protected by dev->struct_mutex. | |
700 | * | |
701 | * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE) | |
702 | */ | |
11824e8c | 703 | signed int fence_reg : 5; |
778c3544 DV |
704 | |
705 | /** | |
706 | * Used for checking the object doesn't appear more than once | |
707 | * in an execbuffer object list. | |
708 | */ | |
709 | unsigned int in_execbuffer : 1; | |
710 | ||
711 | /** | |
712 | * Advice: are the backing pages purgeable? | |
713 | */ | |
714 | unsigned int madv : 2; | |
715 | ||
716 | /** | |
717 | * Refcount for the pages array. With the current locking scheme, there | |
718 | * are at most two concurrent users: Binding a bo to the gtt and | |
719 | * pwrite/pread using physical addresses. So two bits for a maximum | |
720 | * of two users are enough. | |
721 | */ | |
722 | unsigned int pages_refcount : 2; | |
723 | #define DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT 0x3 | |
724 | ||
725 | /** | |
726 | * Current tiling mode for the object. | |
727 | */ | |
728 | unsigned int tiling_mode : 2; | |
729 | ||
730 | /** How many users have pinned this object in GTT space. The following | |
731 | * users can each hold at most one reference: pwrite/pread, pin_ioctl | |
732 | * (via user_pin_count), execbuffer (objects are not allowed multiple | |
733 | * times for the same batchbuffer), and the framebuffer code. When | |
734 | * switching/pageflipping, the framebuffer code has at most two buffers | |
735 | * pinned per crtc. | |
736 | * | |
737 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 | |
738 | * bits with absolutely no headroom. So use 4 bits. */ | |
11824e8c | 739 | unsigned int pin_count : 4; |
778c3544 | 740 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf |
673a394b EA |
741 | |
742 | /** AGP memory structure for our GTT binding. */ | |
743 | DRM_AGP_MEM *agp_mem; | |
744 | ||
856fa198 | 745 | struct page **pages; |
673a394b EA |
746 | |
747 | /** | |
748 | * Current offset of the object in GTT space. | |
749 | * | |
750 | * This is the same as gtt_space->start | |
751 | */ | |
752 | uint32_t gtt_offset; | |
e67b8ce1 | 753 | |
852835f3 ZN |
754 | /* Which ring is refering to is this object */ |
755 | struct intel_ring_buffer *ring; | |
756 | ||
de151cf6 JB |
757 | /** |
758 | * Fake offset for use by mmap(2) | |
759 | */ | |
760 | uint64_t mmap_offset; | |
761 | ||
673a394b EA |
762 | /** Breadcrumb of last rendering to the buffer. */ |
763 | uint32_t last_rendering_seqno; | |
764 | ||
778c3544 | 765 | /** Current tiling stride for the object, if it's tiled. */ |
de151cf6 | 766 | uint32_t stride; |
673a394b | 767 | |
280b713b | 768 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 769 | unsigned long *bit_17; |
280b713b | 770 | |
ba1eb1d8 KP |
771 | /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */ |
772 | uint32_t agp_type; | |
773 | ||
673a394b | 774 | /** |
e47c68e9 EA |
775 | * If present, while GEM_DOMAIN_CPU is in the read domain this array |
776 | * flags which individual pages are valid. | |
673a394b EA |
777 | */ |
778 | uint8_t *page_cpu_valid; | |
79e53945 JB |
779 | |
780 | /** User space pin count and filp owning the pin */ | |
781 | uint32_t user_pin_count; | |
782 | struct drm_file *pin_filp; | |
71acb5eb DA |
783 | |
784 | /** for phy allocated objects */ | |
785 | struct drm_i915_gem_phys_object *phys_obj; | |
b70d11da | 786 | |
6b95a207 KH |
787 | /** |
788 | * Number of crtcs where this object is currently the fb, but | |
789 | * will be page flipped away on the next vblank. When it | |
790 | * reaches 0, dev_priv->pending_flip_queue will be woken up. | |
791 | */ | |
792 | atomic_t pending_flip; | |
673a394b EA |
793 | }; |
794 | ||
62b8b215 | 795 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
23010e43 | 796 | |
673a394b EA |
797 | /** |
798 | * Request queue structure. | |
799 | * | |
800 | * The request queue allows us to note sequence numbers that have been emitted | |
801 | * and may be associated with active buffers to be retired. | |
802 | * | |
803 | * By keeping this list, we can avoid having to do questionable | |
804 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate | |
805 | * an emission time with seqnos for tracking how far ahead of the GPU we are. | |
806 | */ | |
807 | struct drm_i915_gem_request { | |
852835f3 ZN |
808 | /** On Which ring this request was generated */ |
809 | struct intel_ring_buffer *ring; | |
810 | ||
673a394b EA |
811 | /** GEM sequence number associated with this request. */ |
812 | uint32_t seqno; | |
813 | ||
814 | /** Time at which this request was emitted, in jiffies. */ | |
815 | unsigned long emitted_jiffies; | |
816 | ||
b962442e | 817 | /** global list entry for this request */ |
673a394b | 818 | struct list_head list; |
b962442e EA |
819 | |
820 | /** file_priv list entry for this request */ | |
821 | struct list_head client_list; | |
673a394b EA |
822 | }; |
823 | ||
824 | struct drm_i915_file_private { | |
825 | struct { | |
b962442e | 826 | struct list_head request_list; |
673a394b EA |
827 | } mm; |
828 | }; | |
829 | ||
79e53945 JB |
830 | enum intel_chip_family { |
831 | CHIP_I8XX = 0x01, | |
832 | CHIP_I9XX = 0x02, | |
833 | CHIP_I915 = 0x04, | |
834 | CHIP_I965 = 0x08, | |
835 | }; | |
836 | ||
c153f45f | 837 | extern struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 | 838 | extern int i915_max_ioctl; |
79e53945 | 839 | extern unsigned int i915_fbpercrtc; |
652c393a | 840 | extern unsigned int i915_powersave; |
33814341 | 841 | extern unsigned int i915_lvds_downclock; |
b3a83639 | 842 | |
6a9ee8af DA |
843 | extern int i915_suspend(struct drm_device *dev, pm_message_t state); |
844 | extern int i915_resume(struct drm_device *dev); | |
1341d655 BG |
845 | extern void i915_save_display(struct drm_device *dev); |
846 | extern void i915_restore_display(struct drm_device *dev); | |
7c1c2871 DA |
847 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
848 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); | |
849 | ||
1da177e4 | 850 | /* i915_dma.c */ |
84b1fd10 | 851 | extern void i915_kernel_lost_context(struct drm_device * dev); |
22eae947 | 852 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 853 | extern int i915_driver_unload(struct drm_device *); |
673a394b | 854 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
84b1fd10 | 855 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac EA |
856 | extern void i915_driver_preclose(struct drm_device *dev, |
857 | struct drm_file *file_priv); | |
673a394b EA |
858 | extern void i915_driver_postclose(struct drm_device *dev, |
859 | struct drm_file *file_priv); | |
84b1fd10 | 860 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
0d6aa60b DA |
861 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
862 | unsigned long arg); | |
673a394b | 863 | extern int i915_emit_box(struct drm_device *dev, |
201361a5 | 864 | struct drm_clip_rect *boxes, |
673a394b | 865 | int i, int DR1, int DR4); |
11ed50ec | 866 | extern int i965_reset(struct drm_device *dev, u8 flags); |
7648fa99 JB |
867 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
868 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
869 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
870 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
871 | ||
af6061af | 872 | |
1da177e4 | 873 | /* i915_irq.c */ |
f65d9421 | 874 | void i915_hangcheck_elapsed(unsigned long data); |
9df30794 | 875 | void i915_destroy_error_state(struct drm_device *dev); |
c153f45f EA |
876 | extern int i915_irq_emit(struct drm_device *dev, void *data, |
877 | struct drm_file *file_priv); | |
878 | extern int i915_irq_wait(struct drm_device *dev, void *data, | |
879 | struct drm_file *file_priv); | |
9d34e5db | 880 | void i915_trace_irq_get(struct drm_device *dev, u32 seqno); |
79e53945 | 881 | extern void i915_enable_interrupt (struct drm_device *dev); |
1da177e4 LT |
882 | |
883 | extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); | |
84b1fd10 | 884 | extern void i915_driver_irq_preinstall(struct drm_device * dev); |
0a3e67a4 | 885 | extern int i915_driver_irq_postinstall(struct drm_device *dev); |
84b1fd10 | 886 | extern void i915_driver_irq_uninstall(struct drm_device * dev); |
c153f45f EA |
887 | extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
888 | struct drm_file *file_priv); | |
889 | extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, | |
890 | struct drm_file *file_priv); | |
0a3e67a4 JB |
891 | extern int i915_enable_vblank(struct drm_device *dev, int crtc); |
892 | extern void i915_disable_vblank(struct drm_device *dev, int crtc); | |
893 | extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc); | |
9880b7a5 | 894 | extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc); |
c153f45f EA |
895 | extern int i915_vblank_swap(struct drm_device *dev, void *data, |
896 | struct drm_file *file_priv); | |
8ee1c3db | 897 | extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask); |
62fdfeaf | 898 | extern void i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask); |
8187a2b7 ZN |
899 | extern void ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, |
900 | u32 mask); | |
901 | extern void ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, | |
902 | u32 mask); | |
1da177e4 | 903 | |
7c463586 KP |
904 | void |
905 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
906 | ||
907 | void | |
908 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
909 | ||
01c66889 ZY |
910 | void intel_enable_asle (struct drm_device *dev); |
911 | ||
7c463586 | 912 | |
1da177e4 | 913 | /* i915_mem.c */ |
c153f45f EA |
914 | extern int i915_mem_alloc(struct drm_device *dev, void *data, |
915 | struct drm_file *file_priv); | |
916 | extern int i915_mem_free(struct drm_device *dev, void *data, | |
917 | struct drm_file *file_priv); | |
918 | extern int i915_mem_init_heap(struct drm_device *dev, void *data, | |
919 | struct drm_file *file_priv); | |
920 | extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, | |
921 | struct drm_file *file_priv); | |
1da177e4 | 922 | extern void i915_mem_takedown(struct mem_block **heap); |
84b1fd10 | 923 | extern void i915_mem_release(struct drm_device * dev, |
6c340eac | 924 | struct drm_file *file_priv, struct mem_block *heap); |
673a394b EA |
925 | /* i915_gem.c */ |
926 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
927 | struct drm_file *file_priv); | |
928 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
929 | struct drm_file *file_priv); | |
930 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
931 | struct drm_file *file_priv); | |
932 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
933 | struct drm_file *file_priv); | |
934 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
935 | struct drm_file *file_priv); | |
de151cf6 JB |
936 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
937 | struct drm_file *file_priv); | |
673a394b EA |
938 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
939 | struct drm_file *file_priv); | |
940 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
941 | struct drm_file *file_priv); | |
942 | int i915_gem_execbuffer(struct drm_device *dev, void *data, | |
943 | struct drm_file *file_priv); | |
76446cac JB |
944 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
945 | struct drm_file *file_priv); | |
673a394b EA |
946 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
947 | struct drm_file *file_priv); | |
948 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
949 | struct drm_file *file_priv); | |
950 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
951 | struct drm_file *file_priv); | |
952 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
953 | struct drm_file *file_priv); | |
3ef94daa CW |
954 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
955 | struct drm_file *file_priv); | |
673a394b EA |
956 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
957 | struct drm_file *file_priv); | |
958 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
959 | struct drm_file *file_priv); | |
960 | int i915_gem_set_tiling(struct drm_device *dev, void *data, | |
961 | struct drm_file *file_priv); | |
962 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
963 | struct drm_file *file_priv); | |
5a125c3c EA |
964 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
965 | struct drm_file *file_priv); | |
673a394b | 966 | void i915_gem_load(struct drm_device *dev); |
673a394b | 967 | int i915_gem_init_object(struct drm_gem_object *obj); |
ac52bc56 DV |
968 | struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev, |
969 | size_t size); | |
673a394b EA |
970 | void i915_gem_free_object(struct drm_gem_object *obj); |
971 | int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment); | |
972 | void i915_gem_object_unpin(struct drm_gem_object *obj); | |
0f973f27 | 973 | int i915_gem_object_unbind(struct drm_gem_object *obj); |
d05ca301 | 974 | void i915_gem_release_mmap(struct drm_gem_object *obj); |
673a394b | 975 | void i915_gem_lastclose(struct drm_device *dev); |
852835f3 ZN |
976 | uint32_t i915_get_gem_seqno(struct drm_device *dev, |
977 | struct intel_ring_buffer *ring); | |
22be1724 | 978 | bool i915_seqno_passed(uint32_t seq1, uint32_t seq2); |
8c4b8c3f | 979 | int i915_gem_object_get_fence_reg(struct drm_gem_object *obj); |
52dc7d32 | 980 | int i915_gem_object_put_fence_reg(struct drm_gem_object *obj); |
b09a1fec | 981 | void i915_gem_retire_requests(struct drm_device *dev); |
673a394b | 982 | void i915_gem_clflush_object(struct drm_gem_object *obj); |
79e53945 JB |
983 | int i915_gem_object_set_domain(struct drm_gem_object *obj, |
984 | uint32_t read_domains, | |
985 | uint32_t write_domain); | |
986 | int i915_gem_init_ringbuffer(struct drm_device *dev); | |
987 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); | |
988 | int i915_gem_do_init(struct drm_device *dev, unsigned long start, | |
989 | unsigned long end); | |
b47eb4a2 | 990 | int i915_gpu_idle(struct drm_device *dev); |
5669fcac | 991 | int i915_gem_idle(struct drm_device *dev); |
852835f3 ZN |
992 | uint32_t i915_add_request(struct drm_device *dev, |
993 | struct drm_file *file_priv, | |
852835f3 ZN |
994 | struct intel_ring_buffer *ring); |
995 | int i915_do_wait_request(struct drm_device *dev, | |
8a1a49f9 DV |
996 | uint32_t seqno, |
997 | bool interruptible, | |
998 | struct intel_ring_buffer *ring); | |
de151cf6 | 999 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
8a1a49f9 DV |
1000 | void i915_gem_process_flushing_list(struct drm_device *dev, |
1001 | uint32_t flush_domains, | |
1002 | struct intel_ring_buffer *ring); | |
79e53945 JB |
1003 | int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, |
1004 | int write); | |
b9241ea3 | 1005 | int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj); |
71acb5eb | 1006 | int i915_gem_attach_phys_object(struct drm_device *dev, |
6eeefaf3 CW |
1007 | struct drm_gem_object *obj, |
1008 | int id, | |
1009 | int align); | |
71acb5eb DA |
1010 | void i915_gem_detach_phys_object(struct drm_device *dev, |
1011 | struct drm_gem_object *obj); | |
1012 | void i915_gem_free_all_phys_object(struct drm_device *dev); | |
4bdadb97 | 1013 | int i915_gem_object_get_pages(struct drm_gem_object *obj, gfp_t gfpmask); |
6911a9b8 | 1014 | void i915_gem_object_put_pages(struct drm_gem_object *obj); |
1fd1c624 | 1015 | void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv); |
2dafb1e0 | 1016 | int i915_gem_object_flush_write_domain(struct drm_gem_object *obj); |
673a394b | 1017 | |
31169714 CW |
1018 | void i915_gem_shrinker_init(void); |
1019 | void i915_gem_shrinker_exit(void); | |
1020 | ||
b47eb4a2 CW |
1021 | /* i915_gem_evict.c */ |
1022 | int i915_gem_evict_something(struct drm_device *dev, int min_size, unsigned alignment); | |
1023 | int i915_gem_evict_everything(struct drm_device *dev); | |
1024 | int i915_gem_evict_inactive(struct drm_device *dev); | |
1025 | ||
673a394b EA |
1026 | /* i915_gem_tiling.c */ |
1027 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); | |
280b713b EA |
1028 | void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj); |
1029 | void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj); | |
76446cac JB |
1030 | bool i915_tiling_ok(struct drm_device *dev, int stride, int size, |
1031 | int tiling_mode); | |
f590d279 OA |
1032 | bool i915_gem_object_fence_offset_ok(struct drm_gem_object *obj, |
1033 | int tiling_mode); | |
673a394b EA |
1034 | |
1035 | /* i915_gem_debug.c */ | |
1036 | void i915_gem_dump_object(struct drm_gem_object *obj, int len, | |
1037 | const char *where, uint32_t mark); | |
1038 | #if WATCH_INACTIVE | |
1039 | void i915_verify_inactive(struct drm_device *dev, char *file, int line); | |
1040 | #else | |
1041 | #define i915_verify_inactive(dev, file, line) | |
1042 | #endif | |
1043 | void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle); | |
1044 | void i915_gem_dump_object(struct drm_gem_object *obj, int len, | |
1045 | const char *where, uint32_t mark); | |
1046 | void i915_dump_lru(struct drm_device *dev, const char *where); | |
1da177e4 | 1047 | |
2017263e | 1048 | /* i915_debugfs.c */ |
27c202ad BG |
1049 | int i915_debugfs_init(struct drm_minor *minor); |
1050 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
2017263e | 1051 | |
317c35d1 JB |
1052 | /* i915_suspend.c */ |
1053 | extern int i915_save_state(struct drm_device *dev); | |
1054 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 JB |
1055 | |
1056 | /* i915_suspend.c */ | |
1057 | extern int i915_save_state(struct drm_device *dev); | |
1058 | extern int i915_restore_state(struct drm_device *dev); | |
317c35d1 | 1059 | |
3b617967 | 1060 | /* intel_opregion.c */ |
44834a67 CW |
1061 | extern int intel_opregion_setup(struct drm_device *dev); |
1062 | #ifdef CONFIG_ACPI | |
1063 | extern void intel_opregion_init(struct drm_device *dev); | |
1064 | extern void intel_opregion_fini(struct drm_device *dev); | |
3b617967 CW |
1065 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
1066 | extern void intel_opregion_gse_intr(struct drm_device *dev); | |
1067 | extern void intel_opregion_enable_asle(struct drm_device *dev); | |
65e082c9 | 1068 | #else |
44834a67 CW |
1069 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
1070 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } | |
3b617967 CW |
1071 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
1072 | static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; } | |
1073 | static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; } | |
65e082c9 | 1074 | #endif |
8ee1c3db | 1075 | |
79e53945 JB |
1076 | /* modesetting */ |
1077 | extern void intel_modeset_init(struct drm_device *dev); | |
1078 | extern void intel_modeset_cleanup(struct drm_device *dev); | |
28d52043 | 1079 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
80824003 | 1080 | extern void i8xx_disable_fbc(struct drm_device *dev); |
74dff282 | 1081 | extern void g4x_disable_fbc(struct drm_device *dev); |
b52eb4dc | 1082 | extern void ironlake_disable_fbc(struct drm_device *dev); |
ee5382ae AJ |
1083 | extern void intel_disable_fbc(struct drm_device *dev); |
1084 | extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval); | |
1085 | extern bool intel_fbc_enabled(struct drm_device *dev); | |
7648fa99 | 1086 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
3bad0781 | 1087 | extern void intel_detect_pch (struct drm_device *dev); |
e3421a18 | 1088 | extern int intel_trans_dp_port_sel (struct drm_crtc *crtc); |
3bad0781 | 1089 | |
6ef3d427 CW |
1090 | /* overlay */ |
1091 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); | |
1092 | extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error); | |
1093 | ||
546b0974 EA |
1094 | /** |
1095 | * Lock test for when it's just for synchronization of ring access. | |
1096 | * | |
1097 | * In that case, we don't need to do it when GEM is initialized as nobody else | |
1098 | * has access to the ring. | |
1099 | */ | |
1100 | #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \ | |
8187a2b7 ZN |
1101 | if (((drm_i915_private_t *)dev->dev_private)->render_ring.gem_object \ |
1102 | == NULL) \ | |
546b0974 EA |
1103 | LOCK_TEST_WITH_RETURN(dev, file_priv); \ |
1104 | } while (0) | |
1105 | ||
be282fd4 JB |
1106 | static inline u32 i915_read(struct drm_i915_private *dev_priv, u32 reg) |
1107 | { | |
1108 | u32 val; | |
1109 | ||
1110 | val = readl(dev_priv->regs + reg); | |
1111 | if (dev_priv->debug_flags & I915_DEBUG_READ) | |
1112 | printk(KERN_ERR "read 0x%08x from 0x%08x\n", val, reg); | |
1113 | return val; | |
1114 | } | |
1115 | ||
1116 | static inline void i915_write(struct drm_i915_private *dev_priv, u32 reg, | |
1117 | u32 val) | |
1118 | { | |
1119 | writel(val, dev_priv->regs + reg); | |
1120 | if (dev_priv->debug_flags & I915_DEBUG_WRITE) | |
1121 | printk(KERN_ERR "wrote 0x%08x to 0x%08x\n", val, reg); | |
1122 | } | |
1123 | ||
1124 | #define I915_READ(reg) i915_read(dev_priv, (reg)) | |
1125 | #define I915_WRITE(reg, val) i915_write(dev_priv, (reg), (val)) | |
3043c60c EA |
1126 | #define I915_READ16(reg) readw(dev_priv->regs + (reg)) |
1127 | #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg)) | |
1128 | #define I915_READ8(reg) readb(dev_priv->regs + (reg)) | |
1129 | #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg)) | |
de151cf6 | 1130 | #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg)) |
049ef7e4 | 1131 | #define I915_READ64(reg) readq(dev_priv->regs + (reg)) |
7d57382e | 1132 | #define POSTING_READ(reg) (void)I915_READ(reg) |
7648fa99 | 1133 | #define POSTING_READ16(reg) (void)I915_READ16(reg) |
1da177e4 | 1134 | |
be282fd4 JB |
1135 | #define I915_DEBUG_ENABLE_IO() (dev_priv->debug_flags |= I915_DEBUG_READ | \ |
1136 | I915_DEBUG_WRITE) | |
1137 | #define I915_DEBUG_DISABLE_IO() (dev_priv->debug_flags &= ~(I915_DEBUG_READ | \ | |
1138 | I915_DEBUG_WRITE)) | |
1139 | ||
1da177e4 LT |
1140 | #define I915_VERBOSE 0 |
1141 | ||
8187a2b7 | 1142 | #define BEGIN_LP_RING(n) do { \ |
dbd7ac96 | 1143 | drm_i915_private_t *dev_priv__ = dev->dev_private; \ |
8187a2b7 ZN |
1144 | if (I915_VERBOSE) \ |
1145 | DRM_DEBUG(" BEGIN_LP_RING %x\n", (int)(n)); \ | |
dbd7ac96 | 1146 | intel_ring_begin(dev, &dev_priv__->render_ring, (n)); \ |
1da177e4 LT |
1147 | } while (0) |
1148 | ||
8187a2b7 ZN |
1149 | |
1150 | #define OUT_RING(x) do { \ | |
dbd7ac96 | 1151 | drm_i915_private_t *dev_priv__ = dev->dev_private; \ |
8187a2b7 ZN |
1152 | if (I915_VERBOSE) \ |
1153 | DRM_DEBUG(" OUT_RING %x\n", (int)(x)); \ | |
dbd7ac96 | 1154 | intel_ring_emit(dev, &dev_priv__->render_ring, x); \ |
1da177e4 LT |
1155 | } while (0) |
1156 | ||
1157 | #define ADVANCE_LP_RING() do { \ | |
dbd7ac96 | 1158 | drm_i915_private_t *dev_priv__ = dev->dev_private; \ |
0ef82af7 | 1159 | if (I915_VERBOSE) \ |
8187a2b7 | 1160 | DRM_DEBUG("ADVANCE_LP_RING %x\n", \ |
dbd7ac96 CW |
1161 | dev_priv__->render_ring.tail); \ |
1162 | intel_ring_advance(dev, &dev_priv__->render_ring); \ | |
1da177e4 LT |
1163 | } while(0) |
1164 | ||
ba8bbcf6 | 1165 | /** |
585fb111 JB |
1166 | * Reads a dword out of the status page, which is written to from the command |
1167 | * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or | |
1168 | * MI_STORE_DATA_IMM. | |
ba8bbcf6 | 1169 | * |
585fb111 | 1170 | * The following dwords have a reserved meaning: |
0cdad7e8 KP |
1171 | * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. |
1172 | * 0x04: ring 0 head pointer | |
1173 | * 0x05: ring 1 head pointer (915-class) | |
1174 | * 0x06: ring 2 head pointer (915-class) | |
1175 | * 0x10-0x1b: Context status DWords (GM45) | |
1176 | * 0x1f: Last written status offset. (GM45) | |
ba8bbcf6 | 1177 | * |
0cdad7e8 | 1178 | * The area from dword 0x20 to 0x3ff is available for driver usage. |
ba8bbcf6 | 1179 | */ |
8187a2b7 ZN |
1180 | #define READ_HWSP(dev_priv, reg) (((volatile u32 *)\ |
1181 | (dev_priv->render_ring.status_page.page_addr))[reg]) | |
0baf823a | 1182 | #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) |
0cdad7e8 | 1183 | #define I915_GEM_HWS_INDEX 0x20 |
0baf823a | 1184 | #define I915_BREADCRUMB_INDEX 0x21 |
ba8bbcf6 | 1185 | |
cfdf1fa2 KH |
1186 | #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) |
1187 | ||
1188 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) | |
1189 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) | |
5ce8ba7c | 1190 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
cfdf1fa2 | 1191 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) |
cfdf1fa2 KH |
1192 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
1193 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) | |
1194 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) | |
1195 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) | |
1196 | #define IS_I965G(dev) (INTEL_INFO(dev)->is_i965g) | |
1197 | #define IS_I965GM(dev) (INTEL_INFO(dev)->is_i965gm) | |
534843da CW |
1198 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) |
1199 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
cfdf1fa2 KH |
1200 | #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) |
1201 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) | |
1202 | #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) | |
1203 | #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) | |
1204 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) | |
1205 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
f2b115e6 AJ |
1206 | #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) |
1207 | #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) | |
cfdf1fa2 KH |
1208 | #define IS_IRONLAKE(dev) (INTEL_INFO(dev)->is_ironlake) |
1209 | #define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx) | |
1210 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) | |
ba8bbcf6 | 1211 | |
c96c3a8c CW |
1212 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
1213 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) | |
1214 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) | |
1215 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) | |
1216 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) | |
bad720ff | 1217 | |
d1b851fc | 1218 | #define HAS_BSD(dev) (IS_IRONLAKE(dev) || IS_G4X(dev)) |
cfdf1fa2 | 1219 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
ba8bbcf6 | 1220 | |
0f973f27 JB |
1221 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
1222 | * rows, which changed the alignment requirements and fence programming. | |
1223 | */ | |
1224 | #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \ | |
1225 | IS_I915GM(dev))) | |
f2b115e6 AJ |
1226 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (IS_I9XX(dev) && !IS_PINEVIEW(dev)) |
1227 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) | |
1228 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) | |
1229 | #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) | |
103a196f | 1230 | #define SUPPORTS_TV(dev) (IS_I9XX(dev) && IS_MOBILE(dev) && \ |
7da9f6cb ZW |
1231 | !IS_IRONLAKE(dev) && !IS_PINEVIEW(dev) && \ |
1232 | !IS_GEN6(dev)) | |
cfdf1fa2 | 1233 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) |
7662c8bd | 1234 | /* dsparb controlled by hw only */ |
f2b115e6 | 1235 | #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) |
b39d50e5 | 1236 | |
f2b115e6 | 1237 | #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev)) |
cfdf1fa2 KH |
1238 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) |
1239 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) | |
1240 | #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6) | |
652c393a | 1241 | |
bad720ff EA |
1242 | #define HAS_PCH_SPLIT(dev) (IS_IRONLAKE(dev) || \ |
1243 | IS_GEN6(dev)) | |
e552eb70 | 1244 | #define HAS_PIPE_CONTROL(dev) (IS_IRONLAKE(dev) || IS_GEN6(dev)) |
bad720ff | 1245 | |
3bad0781 ZW |
1246 | #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) |
1247 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) | |
1248 | ||
ba8bbcf6 | 1249 | #define PRIMARY_RINGBUFFER_SIZE (128*1024) |
0d6aa60b | 1250 | |
1da177e4 | 1251 | #endif |