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drm/i915: i8xx interrupt handler
[linux-2.6-block.git] / drivers / gpu / drm / i915 / i915_drv.c
CommitLineData
1da177e4
LT		 1/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
0d6aa60b 3/*
bc54fd1a 4 *
1da177e4
LT		 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
bc54fd1a
DA		 7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
0d6aa60b 28 */
1da177e4 29
5669fcac 30#include <linux/device.h>
1da177e4
LT		 31#include "drmP.h"
32#include "drm.h"
33#include "i915_drm.h"
34#include "i915_drv.h"
f49f0586 35#include "intel_drv.h"
1da177e4 36
79e53945 37#include <linux/console.h>
e0cd3608 38#include <linux/module.h>
354ff967 39#include "drm_crtc_helper.h"
79e53945 40
a35d9d3c 41static int i915_modeset __read_mostly = -1;
79e53945 42module_param_named(modeset, i915_modeset, int, 0400);
6e96e775
BW		 43MODULE_PARM_DESC(modeset,
44 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
45 "1=on, -1=force vga console preference [default])");
79e53945 46
a35d9d3c 47unsigned int i915_fbpercrtc __always_unused = 0;
79e53945 48module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
1da177e4 49
a35d9d3c 50int i915_panel_ignore_lid __read_mostly = 0;
fca87409 51module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
6e96e775
BW		 52MODULE_PARM_DESC(panel_ignore_lid,
53 "Override lid status (0=autodetect [default], 1=lid open, "
54 "-1=lid closed)");
fca87409 55
a35d9d3c 56unsigned int i915_powersave __read_mostly = 1;
0aa99277 57module_param_named(powersave, i915_powersave, int, 0600);
6e96e775
BW		 58MODULE_PARM_DESC(powersave,
59 "Enable powersavings, fbc, downclocking, etc. (default: true)");
652c393a 60
f45b5557 61int i915_semaphores __read_mostly = -1;
a1656b90 62module_param_named(semaphores, i915_semaphores, int, 0600);
6e96e775 63MODULE_PARM_DESC(semaphores,
f45b5557 64 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
a1656b90 65
c0f372b3 66int i915_enable_rc6 __read_mostly = -1;
f57f9c16 67module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
6e96e775 68MODULE_PARM_DESC(i915_enable_rc6,
83b7f9ac
ED		 69 "Enable power-saving render C-state 6. "
70 "Different stages can be selected via bitmask values "
71 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
72 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
73 "default: -1 (use per-chip default)");
ac668088 74
4415e63b 75int i915_enable_fbc __read_mostly = -1;
c1a9f047 76module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
6e96e775
BW		 77MODULE_PARM_DESC(i915_enable_fbc,
78 "Enable frame buffer compression for power savings "
cd0de039 79 "(default: -1 (use per-chip default))");
c1a9f047 80
a35d9d3c 81unsigned int i915_lvds_downclock __read_mostly = 0;
33814341 82module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
6e96e775
BW		 83MODULE_PARM_DESC(lvds_downclock,
84 "Use panel (LVDS/eDP) downclocking for power savings "
85 "(default: false)");
33814341 86
121d527a
TI		 87int i915_lvds_channel_mode __read_mostly;
88module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
89MODULE_PARM_DESC(lvds_channel_mode,
90 "Specify LVDS channel mode "
91 "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
92
4415e63b 93int i915_panel_use_ssc __read_mostly = -1;
a7615030 94module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
6e96e775
BW		 95MODULE_PARM_DESC(lvds_use_ssc,
96 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
72bbe58c 97 "(default: auto from VBT)");
a7615030 98
a35d9d3c 99int i915_vbt_sdvo_panel_type __read_mostly = -1;
5a1e5b6c 100module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
6e96e775 101MODULE_PARM_DESC(vbt_sdvo_panel_type,
c10e408a
MF		 102 "Override/Ignore selection of SDVO panel mode in the VBT "
103 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
5a1e5b6c 104
a35d9d3c 105static bool i915_try_reset __read_mostly = true;
d78cb50b 106module_param_named(reset, i915_try_reset, bool, 0600);
6e96e775 107MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
d78cb50b 108
a35d9d3c 109bool i915_enable_hangcheck __read_mostly = true;
3e0dc6b0 110module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
6e96e775
BW		 111MODULE_PARM_DESC(enable_hangcheck,
112 "Periodically check GPU activity for detecting hangs. "
113 "WARNING: Disabling this can cause system wide hangs. "
114 "(default: true)");
3e0dc6b0 115
650dc07e
DV		 116int i915_enable_ppgtt __read_mostly = -1;
117module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
e21af88d
DV		 118MODULE_PARM_DESC(i915_enable_ppgtt,
119 "Enable PPGTT (default: true)");
120
112b715e 121static struct drm_driver driver;
1f7a6e37 122extern int intel_agp_enabled;
112b715e 123
cfdf1fa2 124#define INTEL_VGA_DEVICE(id, info) { \
80a2901d 125 .class = PCI_BASE_CLASS_DISPLAY << 16, \
934f992c 126 .class_mask = 0xff0000, \
49ae35f2
KH		 127 .vendor = 0x8086, \
128 .device = id, \
129 .subvendor = PCI_ANY_ID, \
130 .subdevice = PCI_ANY_ID, \
cfdf1fa2
KH		 131 .driver_data = (unsigned long) info }
132
9a7e8492 133static const struct intel_device_info intel_i830_info = {
a6c45cf0 134 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
31578148 135 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2
KH		 136};
137
9a7e8492 138static const struct intel_device_info intel_845g_info = {
a6c45cf0 139 .gen = 2,
31578148 140 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2
KH		 141};
142
9a7e8492 143static const struct intel_device_info intel_i85x_info = {
a6c45cf0 144 .gen = 2, .is_i85x = 1, .is_mobile = 1,
5ce8ba7c 145 .cursor_needs_physical = 1,
31578148 146 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2
KH		 147};
148
9a7e8492 149static const struct intel_device_info intel_i865g_info = {
a6c45cf0 150 .gen = 2,
31578148 151 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2
KH		 152};
153
9a7e8492 154static const struct intel_device_info intel_i915g_info = {
a6c45cf0 155 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
31578148 156 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2 157};
9a7e8492 158static const struct intel_device_info intel_i915gm_info = {
a6c45cf0 159 .gen = 3, .is_mobile = 1,
b295d1b6 160 .cursor_needs_physical = 1,
31578148 161 .has_overlay = 1, .overlay_needs_physical = 1,
a6c45cf0 162 .supports_tv = 1,
cfdf1fa2 163};
9a7e8492 164static const struct intel_device_info intel_i945g_info = {
a6c45cf0 165 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
31578148 166 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2 167};
9a7e8492 168static const struct intel_device_info intel_i945gm_info = {
a6c45cf0 169 .gen = 3, .is_i945gm = 1, .is_mobile = 1,
b295d1b6 170 .has_hotplug = 1, .cursor_needs_physical = 1,
31578148 171 .has_overlay = 1, .overlay_needs_physical = 1,
a6c45cf0 172 .supports_tv = 1,
cfdf1fa2
KH		 173};
174
9a7e8492 175static const struct intel_device_info intel_i965g_info = {
a6c45cf0 176 .gen = 4, .is_broadwater = 1,
c96c3a8c 177 .has_hotplug = 1,
31578148 178 .has_overlay = 1,
cfdf1fa2
KH		 179};
180
9a7e8492 181static const struct intel_device_info intel_i965gm_info = {
a6c45cf0 182 .gen = 4, .is_crestline = 1,
e3c4e5dd 183 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
31578148 184 .has_overlay = 1,
a6c45cf0 185 .supports_tv = 1,
cfdf1fa2
KH		 186};
187
9a7e8492 188static const struct intel_device_info intel_g33_info = {
a6c45cf0 189 .gen = 3, .is_g33 = 1,
c96c3a8c 190 .need_gfx_hws = 1, .has_hotplug = 1,
31578148 191 .has_overlay = 1,
cfdf1fa2
KH		 192};
193
9a7e8492 194static const struct intel_device_info intel_g45_info = {
a6c45cf0 195 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
c96c3a8c 196 .has_pipe_cxsr = 1, .has_hotplug = 1,
92f49d9c 197 .has_bsd_ring = 1,
cfdf1fa2
KH		 198};
199
9a7e8492 200static const struct intel_device_info intel_gm45_info = {
a6c45cf0 201 .gen = 4, .is_g4x = 1,
e3c4e5dd 202 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
c96c3a8c 203 .has_pipe_cxsr = 1, .has_hotplug = 1,
a6c45cf0 204 .supports_tv = 1,
92f49d9c 205 .has_bsd_ring = 1,
cfdf1fa2
KH		 206};
207
9a7e8492 208static const struct intel_device_info intel_pineview_info = {
a6c45cf0 209 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
c96c3a8c 210 .need_gfx_hws = 1, .has_hotplug = 1,
31578148 211 .has_overlay = 1,
cfdf1fa2
KH		 212};
213
9a7e8492 214static const struct intel_device_info intel_ironlake_d_info = {
f00a3ddf 215 .gen = 5,
5a117db7 216 .need_gfx_hws = 1, .has_hotplug = 1,
92f49d9c 217 .has_bsd_ring = 1,
7e508a27 218 .has_pch_split = 1,
cfdf1fa2
KH		 219};
220
9a7e8492 221static const struct intel_device_info intel_ironlake_m_info = {
f00a3ddf 222 .gen = 5, .is_mobile = 1,
e3c4e5dd 223 .need_gfx_hws = 1, .has_hotplug = 1,
c1a9f047 224 .has_fbc = 1,
92f49d9c 225 .has_bsd_ring = 1,
7e508a27 226 .has_pch_split = 1,
cfdf1fa2
KH		 227};
228
9a7e8492 229static const struct intel_device_info intel_sandybridge_d_info = {
a6c45cf0 230 .gen = 6,
c96c3a8c 231 .need_gfx_hws = 1, .has_hotplug = 1,
881f47b6 232 .has_bsd_ring = 1,
549f7365 233 .has_blt_ring = 1,
3d29b842 234 .has_llc = 1,
7e508a27 235 .has_pch_split = 1,
f6e450a6
EA		 236};
237
9a7e8492 238static const struct intel_device_info intel_sandybridge_m_info = {
a6c45cf0 239 .gen = 6, .is_mobile = 1,
c96c3a8c 240 .need_gfx_hws = 1, .has_hotplug = 1,
9c04f015 241 .has_fbc = 1,
881f47b6 242 .has_bsd_ring = 1,
549f7365 243 .has_blt_ring = 1,
3d29b842 244 .has_llc = 1,
7e508a27 245 .has_pch_split = 1,
a13e4093
EA		 246};
247
c76b615c
JB		 248static const struct intel_device_info intel_ivybridge_d_info = {
249 .is_ivybridge = 1, .gen = 7,
250 .need_gfx_hws = 1, .has_hotplug = 1,
251 .has_bsd_ring = 1,
252 .has_blt_ring = 1,
3d29b842 253 .has_llc = 1,
7e508a27 254 .has_pch_split = 1,
c76b615c
JB		 255};
256
257static const struct intel_device_info intel_ivybridge_m_info = {
258 .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
259 .need_gfx_hws = 1, .has_hotplug = 1,
260 .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */
261 .has_bsd_ring = 1,
262 .has_blt_ring = 1,
3d29b842 263 .has_llc = 1,
7e508a27 264 .has_pch_split = 1,
c76b615c
JB		 265};
266
70a3eb7a
JB		 267static const struct intel_device_info intel_valleyview_m_info = {
268 .gen = 7, .is_mobile = 1,
269 .need_gfx_hws = 1, .has_hotplug = 1,
270 .has_fbc = 0,
271 .has_bsd_ring = 1,
272 .has_blt_ring = 1,
273 .is_valleyview = 1,
274};
275
276static const struct intel_device_info intel_valleyview_d_info = {
277 .gen = 7,
278 .need_gfx_hws = 1, .has_hotplug = 1,
279 .has_fbc = 0,
280 .has_bsd_ring = 1,
281 .has_blt_ring = 1,
282 .is_valleyview = 1,
283};
284
4cae9ae0
ED		 285static const struct intel_device_info intel_haswell_d_info = {
286 .is_haswell = 1, .gen = 7,
287 .need_gfx_hws = 1, .has_hotplug = 1,
288 .has_bsd_ring = 1,
289 .has_blt_ring = 1,
290 .has_llc = 1,
291 .has_pch_split = 1,
292};
293
294static const struct intel_device_info intel_haswell_m_info = {
295 .is_haswell = 1, .gen = 7, .is_mobile = 1,
296 .need_gfx_hws = 1, .has_hotplug = 1,
297 .has_bsd_ring = 1,
298 .has_blt_ring = 1,
299 .has_llc = 1,
300 .has_pch_split = 1,
c76b615c
JB		 301};
302
6103da0d
CW		 303static const struct pci_device_id pciidlist[] = { /* aka */
304 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
305 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
306 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
5ce8ba7c 307 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
6103da0d
CW		 308 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
309 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
310 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
311 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
312 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
313 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
314 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
315 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
316 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
317 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
318 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
319 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
320 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
321 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
322 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
323 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
324 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
325 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
326 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
327 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
328 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
329 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
41a51428 330 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
cfdf1fa2
KH		 331 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
332 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
333 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
334 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
f6e450a6 335 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
85540480
ZW		 336 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
337 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
a13e4093 338 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
85540480 339 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
4fefe435 340 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
85540480 341 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
c76b615c
JB		 342 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
343 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
344 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
345 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
346 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
cc22a938 347 INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
49ae35f2 348 {0, 0, 0}
1da177e4
LT		 349};
350
79e53945
JB		 351#if defined(CONFIG_DRM_I915_KMS)
352MODULE_DEVICE_TABLE(pci, pciidlist);
353#endif
354
3bad0781 355#define INTEL_PCH_DEVICE_ID_MASK 0xff00
90711d50 356#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
3bad0781 357#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
c792513b 358#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
eb877ebf 359#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
3bad0781 360
0206e353 361void intel_detect_pch(struct drm_device *dev)
3bad0781
ZW		 362{
363 struct drm_i915_private *dev_priv = dev->dev_private;
364 struct pci_dev *pch;
365
366 /*
367 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
368 * make graphics device passthrough work easy for VMM, that only
369 * need to expose ISA bridge to let driver know the real hardware
370 * underneath. This is a requirement from virtualization team.
371 */
372 pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
373 if (pch) {
374 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
375 int id;
376 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
377
90711d50
JB		 378 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
379 dev_priv->pch_type = PCH_IBX;
380 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
381 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
3bad0781
ZW		 382 dev_priv->pch_type = PCH_CPT;
383 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
c792513b
JB		 384 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
385 /* PantherPoint is CPT compatible */
386 dev_priv->pch_type = PCH_CPT;
387 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
eb877ebf
ED		 388 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
389 dev_priv->pch_type = PCH_LPT;
390 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
3bad0781
ZW		 391 }
392 }
393 pci_dev_put(pch);
394 }
395}
396
2911a35b
BW		 397bool i915_semaphore_is_enabled(struct drm_device *dev)
398{
399 if (INTEL_INFO(dev)->gen < 6)
400 return 0;
401
402 if (i915_semaphores >= 0)
403 return i915_semaphores;
404
405 /* Enable semaphores on SNB when IO remapping is off */
406 if (INTEL_INFO(dev)->gen == 6)
407 return !intel_iommu_enabled;
408
409 return 1;
410}
411
8d715f00 412void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
eb43f4af
CW		 413{
414 int count;
415
416 count = 0;
417 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
418 udelay(10);
419
420 I915_WRITE_NOTRACE(FORCEWAKE, 1);
421 POSTING_READ(FORCEWAKE);
422
423 count = 0;
424 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
425 udelay(10);
426}
427
8d715f00
KP		 428void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
429{
430 int count;
431
432 count = 0;
433 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))
434 udelay(10);
435
436 I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 1);
437 POSTING_READ(FORCEWAKE_MT);
438
439 count = 0;
440 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)
441 udelay(10);
442}
443
fcca7926
BW		 444/*
445 * Generally this is called implicitly by the register read function. However,
446 * if some sequence requires the GT to not power down then this function should
447 * be called at the beginning of the sequence followed by a call to
448 * gen6_gt_force_wake_put() at the end of the sequence.
449 */
450void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
451{
9f1f46a4 452 unsigned long irqflags;
fcca7926 453
9f1f46a4
DV		 454 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
455 if (dev_priv->forcewake_count++ == 0)
8d715f00 456 dev_priv->display.force_wake_get(dev_priv);
9f1f46a4 457 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
fcca7926
BW		 458}
459
ee64cbdb
BW		 460static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
461{
462 u32 gtfifodbg;
463 gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
464 if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
465 "MMIO read or write has been dropped %x\n", gtfifodbg))
466 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
467}
468
8d715f00 469void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
eb43f4af
CW		 470{
471 I915_WRITE_NOTRACE(FORCEWAKE, 0);
ee64cbdb
BW		 472 /* The below doubles as a POSTING_READ */
473 gen6_gt_check_fifodbg(dev_priv);
eb43f4af
CW		 474}
475
8d715f00
KP		 476void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
477{
478 I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 0);
ee64cbdb
BW		 479 /* The below doubles as a POSTING_READ */
480 gen6_gt_check_fifodbg(dev_priv);
8d715f00
KP		 481}
482
fcca7926
BW		 483/*
484 * see gen6_gt_force_wake_get()
485 */
486void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
487{
9f1f46a4 488 unsigned long irqflags;
fcca7926 489
9f1f46a4
DV		 490 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
491 if (--dev_priv->forcewake_count == 0)
8d715f00 492 dev_priv->display.force_wake_put(dev_priv);
9f1f46a4 493 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
fcca7926
BW		 494}
495
67a3744f 496int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
91355834 497{
67a3744f
BW		 498 int ret = 0;
499
0206e353 500 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
95736720
CW		 501 int loop = 500;
502 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
503 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
504 udelay(10);
505 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
506 }
67a3744f
BW		 507 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
508 ++ret;
95736720 509 dev_priv->gt_fifo_count = fifo;
91355834 510 }
95736720 511 dev_priv->gt_fifo_count--;
67a3744f
BW		 512
513 return ret;
91355834
CW		 514}
515
575155a9
JB		 516void vlv_force_wake_get(struct drm_i915_private *dev_priv)
517{
518 int count;
519
520 count = 0;
521
522 /* Already awake? */
523 if ((I915_READ(0x130094) & 0xa1) == 0xa1)
524 return;
525
526 I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffffffff);
527 POSTING_READ(FORCEWAKE_VLV);
528
529 count = 0;
530 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0)
531 udelay(10);
532}
533
534void vlv_force_wake_put(struct drm_i915_private *dev_priv)
535{
536 I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffff0000);
537 /* FIXME: confirm VLV behavior with Punit folks */
538 POSTING_READ(FORCEWAKE_VLV);
539}
540
84b79f8d 541static int i915_drm_freeze(struct drm_device *dev)
ba8bbcf6 542{
61caf87c
RW		 543 struct drm_i915_private *dev_priv = dev->dev_private;
544
5bcf719b
DA		 545 drm_kms_helper_poll_disable(dev);
546
ba8bbcf6 547 pci_save_state(dev->pdev);
ba8bbcf6 548
5669fcac 549 /* If KMS is active, we do the leavevt stuff here */
226485e9 550 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
84b79f8d
RW		 551 int error = i915_gem_idle(dev);
552 if (error) {
226485e9 553 dev_err(&dev->pdev->dev,
84b79f8d
RW		 554 "GEM idle failed, resume might fail\n");
555 return error;
556 }
226485e9 557 drm_irq_uninstall(dev);
5669fcac
JB		 558 }
559
9e06dd39
JB		 560 i915_save_state(dev);
561
44834a67 562 intel_opregion_fini(dev);
8ee1c3db 563
84b79f8d
RW		 564 /* Modeset on resume, not lid events */
565 dev_priv->modeset_on_lid = 0;
61caf87c 566
3fa016a0
DA		 567 console_lock();
568 intel_fbdev_set_suspend(dev, 1);
569 console_unlock();
570
61caf87c 571 return 0;
84b79f8d
RW		 572}
573
6a9ee8af 574int i915_suspend(struct drm_device *dev, pm_message_t state)
84b79f8d
RW		 575{
576 int error;
577
578 if (!dev || !dev->dev_private) {
579 DRM_ERROR("dev: %p\n", dev);
580 DRM_ERROR("DRM not initialized, aborting suspend.\n");
581 return -ENODEV;
582 }
583
584 if (state.event == PM_EVENT_PRETHAW)
585 return 0;
586
5bcf719b
DA		 587
588 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
589 return 0;
6eecba33 590
84b79f8d
RW		 591 error = i915_drm_freeze(dev);
592 if (error)
593 return error;
594
b932ccb5
DA		 595 if (state.event == PM_EVENT_SUSPEND) {
596 /* Shut down the device */
597 pci_disable_device(dev->pdev);
598 pci_set_power_state(dev->pdev, PCI_D3hot);
599 }
ba8bbcf6
JB		 600
601 return 0;
602}
603
84b79f8d 604static int i915_drm_thaw(struct drm_device *dev)
ba8bbcf6 605{
5669fcac 606 struct drm_i915_private *dev_priv = dev->dev_private;
84b79f8d 607 int error = 0;
8ee1c3db 608
d1c3b177
CW		 609 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
610 mutex_lock(&dev->struct_mutex);
611 i915_gem_restore_gtt_mappings(dev);
612 mutex_unlock(&dev->struct_mutex);
613 }
614
61caf87c 615 i915_restore_state(dev);
44834a67 616 intel_opregion_setup(dev);
61caf87c 617
5669fcac
JB		 618 /* KMS EnterVT equivalent */
619 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
620 mutex_lock(&dev->struct_mutex);
621 dev_priv->mm.suspended = 0;
622
f691e2f4 623 error = i915_gem_init_hw(dev);
5669fcac 624 mutex_unlock(&dev->struct_mutex);
226485e9 625
9fb526db
KP		 626 if (HAS_PCH_SPLIT(dev))
627 ironlake_init_pch_refclk(dev);
628
500f7147 629 drm_mode_config_reset(dev);
226485e9 630 drm_irq_install(dev);
84b79f8d 631
354ff967 632 /* Resume the modeset for every activated CRTC */
927a2f11 633 mutex_lock(&dev->mode_config.mutex);
354ff967 634 drm_helper_resume_force_mode(dev);
927a2f11 635 mutex_unlock(&dev->mode_config.mutex);
5669fcac 636
ac668088 637 if (IS_IRONLAKE_M(dev))
d5bb081b
JB		 638 ironlake_enable_rc6(dev);
639 }
1daed3fb 640
44834a67
CW		 641 intel_opregion_init(dev);
642
c9354c85 643 dev_priv->modeset_on_lid = 0;
06891e27 644
3fa016a0
DA		 645 console_lock();
646 intel_fbdev_set_suspend(dev, 0);
647 console_unlock();
84b79f8d
RW		 648 return error;
649}
650
6a9ee8af 651int i915_resume(struct drm_device *dev)
84b79f8d 652{
6eecba33
CW		 653 int ret;
654
5bcf719b
DA		 655 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
656 return 0;
657
84b79f8d
RW		 658 if (pci_enable_device(dev->pdev))
659 return -EIO;
660
661 pci_set_master(dev->pdev);
662
6eecba33
CW		 663 ret = i915_drm_thaw(dev);
664 if (ret)
665 return ret;
666
667 drm_kms_helper_poll_enable(dev);
668 return 0;
ba8bbcf6
JB		 669}
670
dc96e9b8
CW		 671static int i8xx_do_reset(struct drm_device *dev, u8 flags)
672{
673 struct drm_i915_private *dev_priv = dev->dev_private;
674
675 if (IS_I85X(dev))
676 return -ENODEV;
677
678 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
679 POSTING_READ(D_STATE);
680
681 if (IS_I830(dev) || IS_845G(dev)) {
682 I915_WRITE(DEBUG_RESET_I830,
683 DEBUG_RESET_DISPLAY |
684 DEBUG_RESET_RENDER |
685 DEBUG_RESET_FULL);
686 POSTING_READ(DEBUG_RESET_I830);
687 msleep(1);
688
689 I915_WRITE(DEBUG_RESET_I830, 0);
690 POSTING_READ(DEBUG_RESET_I830);
691 }
692
693 msleep(1);
694
695 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
696 POSTING_READ(D_STATE);
697
698 return 0;
699}
700
f49f0586
KG		 701static int i965_reset_complete(struct drm_device *dev)
702{
703 u8 gdrst;
eeccdcac 704 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
f49f0586
KG		 705 return gdrst & 0x1;
706}
707
0573ed4a
KG		 708static int i965_do_reset(struct drm_device *dev, u8 flags)
709{
710 u8 gdrst;
711
ae681d96
CW		 712 /*
713 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
714 * well as the reset bit (GR/bit 0). Setting the GR bit
715 * triggers the reset; when done, the hardware will clear it.
716 */
0573ed4a
KG		 717 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
718 pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1);
719
720 return wait_for(i965_reset_complete(dev), 500);
721}
722
723static int ironlake_do_reset(struct drm_device *dev, u8 flags)
724{
725 struct drm_i915_private *dev_priv = dev->dev_private;
726 u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
727 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1);
728 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
ba8bbcf6
JB		 729}
730
cff458c2
EA		 731static int gen6_do_reset(struct drm_device *dev, u8 flags)
732{
733 struct drm_i915_private *dev_priv = dev->dev_private;
b6e45f86
KP		 734 int ret;
735 unsigned long irqflags;
cff458c2 736
286fed41
KP		 737 /* Hold gt_lock across reset to prevent any register access
738 * with forcewake not set correctly
739 */
b6e45f86 740 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
286fed41
KP		 741
742 /* Reset the chip */
743
744 /* GEN6_GDRST is not in the gt power well, no need to check
745 * for fifo space for the write or forcewake the chip for
746 * the read
747 */
748 I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
749
750 /* Spin waiting for the device to ack the reset request */
751 ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
752
753 /* If reset with a user forcewake, try to restore, otherwise turn it off */
b6e45f86
KP		 754 if (dev_priv->forcewake_count)
755 dev_priv->display.force_wake_get(dev_priv);
286fed41
KP		 756 else
757 dev_priv->display.force_wake_put(dev_priv);
758
759 /* Restore fifo count */
760 dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
761
b6e45f86
KP		 762 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
763 return ret;
cff458c2
EA		 764}
765
11ed50ec 766/**
f3953dcb 767 * i915_reset - reset chip after a hang
11ed50ec
BG		 768 * @dev: drm device to reset
769 * @flags: reset domains
770 *
771 * Reset the chip. Useful if a hang is detected. Returns zero on successful
772 * reset or otherwise an error code.
773 *
774 * Procedure is fairly simple:
775 * - reset the chip using the reset reg
776 * - re-init context state
777 * - re-init hardware status page
778 * - re-init ring buffer
779 * - re-init interrupt state
780 * - re-init display
781 */
f803aa55 782int i915_reset(struct drm_device *dev, u8 flags)
11ed50ec
BG		 783{
784 drm_i915_private_t *dev_priv = dev->dev_private;
11ed50ec
BG		 785 /*
786 * We really should only reset the display subsystem if we actually
787 * need to
788 */
789 bool need_display = true;
0573ed4a 790 int ret;
11ed50ec 791
d78cb50b
CW		 792 if (!i915_try_reset)
793 return 0;
794
340479aa
CW		 795 if (!mutex_trylock(&dev->struct_mutex))
796 return -EBUSY;
11ed50ec 797
069efc1d 798 i915_gem_reset(dev);
77f01230 799
f803aa55 800 ret = -ENODEV;
ae681d96
CW		 801 if (get_seconds() - dev_priv->last_gpu_reset < 5) {
802 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
803 } else switch (INTEL_INFO(dev)->gen) {
1083694a 804 case 7:
cff458c2
EA		 805 case 6:
806 ret = gen6_do_reset(dev, flags);
807 break;
f803aa55 808 case 5:
0573ed4a 809 ret = ironlake_do_reset(dev, flags);
f803aa55
CW		 810 break;
811 case 4:
0573ed4a 812 ret = i965_do_reset(dev, flags);
f803aa55 813 break;
dc96e9b8
CW		 814 case 2:
815 ret = i8xx_do_reset(dev, flags);
816 break;
f803aa55 817 }
ae681d96 818 dev_priv->last_gpu_reset = get_seconds();
0573ed4a 819 if (ret) {
f803aa55 820 DRM_ERROR("Failed to reset chip.\n");
f953c935 821 mutex_unlock(&dev->struct_mutex);
f803aa55 822 return ret;
11ed50ec
BG		 823 }
824
825 /* Ok, now get things going again... */
826
827 /*
828 * Everything depends on having the GTT running, so we need to start
829 * there. Fortunately we don't need to do this unless we reset the
830 * chip at a PCI level.
831 *
832 * Next we need to restore the context, but we don't use those
833 * yet either...
834 *
835 * Ring buffer needs to be re-initialized in the KMS case, or if X
836 * was running at the time of the reset (i.e. we weren't VT
837 * switched away).
838 */
839 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
8187a2b7 840 !dev_priv->mm.suspended) {
11ed50ec 841 dev_priv->mm.suspended = 0;
75a6898f 842
f691e2f4
DV		 843 i915_gem_init_swizzling(dev);
844
1ec14ad3 845 dev_priv->ring[RCS].init(&dev_priv->ring[RCS]);
75a6898f 846 if (HAS_BSD(dev))
1ec14ad3 847 dev_priv->ring[VCS].init(&dev_priv->ring[VCS]);
75a6898f 848 if (HAS_BLT(dev))
1ec14ad3 849 dev_priv->ring[BCS].init(&dev_priv->ring[BCS]);
75a6898f 850
e21af88d
DV		 851 i915_gem_init_ppgtt(dev);
852
11ed50ec 853 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 854
855 if (drm_core_check_feature(dev, DRIVER_MODESET))
856 intel_modeset_init_hw(dev);
857
11ed50ec 858 drm_irq_uninstall(dev);
500f7147 859 drm_mode_config_reset(dev);
11ed50ec 860 drm_irq_install(dev);
f817586c 861
11ed50ec
BG		 862 mutex_lock(&dev->struct_mutex);
863 }
864
9fd98141
CW		 865 mutex_unlock(&dev->struct_mutex);
866
11ed50ec 867 /*
9fd98141
CW		 868 * Perform a full modeset as on later generations, e.g. Ironlake, we may
869 * need to retrain the display link and cannot just restore the register
870 * values.
11ed50ec 871 */
9fd98141
CW		 872 if (need_display) {
873 mutex_lock(&dev->mode_config.mutex);
874 drm_helper_resume_force_mode(dev);
875 mutex_unlock(&dev->mode_config.mutex);
876 }
11ed50ec 877
11ed50ec
BG		 878 return 0;
879}
880
881
112b715e
KH		 882static int __devinit
883i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
884{
5fe49d86
CW		 885 /* Only bind to function 0 of the device. Early generations
886 * used function 1 as a placeholder for multi-head. This causes
887 * us confusion instead, especially on the systems where both
888 * functions have the same PCI-ID!
889 */
890 if (PCI_FUNC(pdev->devfn))
891 return -ENODEV;
892
dcdb1674 893 return drm_get_pci_dev(pdev, ent, &driver);
112b715e
KH		 894}
895
896static void
897i915_pci_remove(struct pci_dev *pdev)
898{
899 struct drm_device *dev = pci_get_drvdata(pdev);
900
901 drm_put_dev(dev);
902}
903
84b79f8d 904static int i915_pm_suspend(struct device *dev)
112b715e 905{
84b79f8d
RW		 906 struct pci_dev *pdev = to_pci_dev(dev);
907 struct drm_device *drm_dev = pci_get_drvdata(pdev);
908 int error;
112b715e 909
84b79f8d
RW		 910 if (!drm_dev || !drm_dev->dev_private) {
911 dev_err(dev, "DRM not initialized, aborting suspend.\n");
912 return -ENODEV;
913 }
112b715e 914
5bcf719b
DA		 915 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
916 return 0;
917
84b79f8d
RW		 918 error = i915_drm_freeze(drm_dev);
919 if (error)
920 return error;
112b715e 921
84b79f8d
RW		 922 pci_disable_device(pdev);
923 pci_set_power_state(pdev, PCI_D3hot);
cbda12d7 924
84b79f8d 925 return 0;
cbda12d7
ZW		 926}
927
84b79f8d 928static int i915_pm_resume(struct device *dev)
cbda12d7 929{
84b79f8d
RW		 930 struct pci_dev *pdev = to_pci_dev(dev);
931 struct drm_device *drm_dev = pci_get_drvdata(pdev);
932
933 return i915_resume(drm_dev);
cbda12d7
ZW		 934}
935
84b79f8d 936static int i915_pm_freeze(struct device *dev)
cbda12d7 937{
84b79f8d
RW		 938 struct pci_dev *pdev = to_pci_dev(dev);
939 struct drm_device *drm_dev = pci_get_drvdata(pdev);
940
941 if (!drm_dev || !drm_dev->dev_private) {
942 dev_err(dev, "DRM not initialized, aborting suspend.\n");
943 return -ENODEV;
944 }
945
946 return i915_drm_freeze(drm_dev);
cbda12d7
ZW		 947}
948
84b79f8d 949static int i915_pm_thaw(struct device *dev)
cbda12d7 950{
84b79f8d
RW		 951 struct pci_dev *pdev = to_pci_dev(dev);
952 struct drm_device *drm_dev = pci_get_drvdata(pdev);
953
954 return i915_drm_thaw(drm_dev);
cbda12d7
ZW		 955}
956
84b79f8d 957static int i915_pm_poweroff(struct device *dev)
cbda12d7 958{
84b79f8d
RW		 959 struct pci_dev *pdev = to_pci_dev(dev);
960 struct drm_device *drm_dev = pci_get_drvdata(pdev);
84b79f8d 961
61caf87c 962 return i915_drm_freeze(drm_dev);
cbda12d7
ZW		 963}
964
b4b78d12 965static const struct dev_pm_ops i915_pm_ops = {
0206e353
AJ		 966 .suspend = i915_pm_suspend,
967 .resume = i915_pm_resume,
968 .freeze = i915_pm_freeze,
969 .thaw = i915_pm_thaw,
970 .poweroff = i915_pm_poweroff,
971 .restore = i915_pm_resume,
cbda12d7
ZW		 972};
973
de151cf6
JB		 974static struct vm_operations_struct i915_gem_vm_ops = {
975 .fault = i915_gem_fault,
ab00b3e5
JB		 976 .open = drm_gem_vm_open,
977 .close = drm_gem_vm_close,
de151cf6
JB		 978};
979
e08e96de
AV		 980static const struct file_operations i915_driver_fops = {
981 .owner = THIS_MODULE,
982 .open = drm_open,
983 .release = drm_release,
984 .unlocked_ioctl = drm_ioctl,
985 .mmap = drm_gem_mmap,
986 .poll = drm_poll,
987 .fasync = drm_fasync,
988 .read = drm_read,
989#ifdef CONFIG_COMPAT
990 .compat_ioctl = i915_compat_ioctl,
991#endif
992 .llseek = noop_llseek,
993};
994
1da177e4 995static struct drm_driver driver = {
0c54781b
MW		 996 /* Don't use MTRRs here; the Xserver or userspace app should
997 * deal with them for Intel hardware.
792d2b9a 998 */
673a394b
EA		 999 .driver_features =
1000 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
1001 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
22eae947 1002 .load = i915_driver_load,
ba8bbcf6 1003 .unload = i915_driver_unload,
673a394b 1004 .open = i915_driver_open,
22eae947
DA		 1005 .lastclose = i915_driver_lastclose,
1006 .preclose = i915_driver_preclose,
673a394b 1007 .postclose = i915_driver_postclose,
d8e29209
RW		 1008
1009 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1010 .suspend = i915_suspend,
1011 .resume = i915_resume,
1012
cda17380 1013 .device_is_agp = i915_driver_device_is_agp,
1da177e4 1014 .reclaim_buffers = drm_core_reclaim_buffers,
7c1c2871
DA		 1015 .master_create = i915_master_create,
1016 .master_destroy = i915_master_destroy,
955b12de 1017#if defined(CONFIG_DEBUG_FS)
27c202ad
BG		 1018 .debugfs_init = i915_debugfs_init,
1019 .debugfs_cleanup = i915_debugfs_cleanup,
955b12de 1020#endif
673a394b
EA		 1021 .gem_init_object = i915_gem_init_object,
1022 .gem_free_object = i915_gem_free_object,
de151cf6 1023 .gem_vm_ops = &i915_gem_vm_ops,
ff72145b
DA		 1024 .dumb_create = i915_gem_dumb_create,
1025 .dumb_map_offset = i915_gem_mmap_gtt,
1026 .dumb_destroy = i915_gem_dumb_destroy,
1da177e4 1027 .ioctls = i915_ioctls,
e08e96de 1028 .fops = &i915_driver_fops,
22eae947
DA		 1029 .name = DRIVER_NAME,
1030 .desc = DRIVER_DESC,
1031 .date = DRIVER_DATE,
1032 .major = DRIVER_MAJOR,
1033 .minor = DRIVER_MINOR,
1034 .patchlevel = DRIVER_PATCHLEVEL,
1da177e4
LT		 1035};
1036
8410ea3b
DA		 1037static struct pci_driver i915_pci_driver = {
1038 .name = DRIVER_NAME,
1039 .id_table = pciidlist,
1040 .probe = i915_pci_probe,
1041 .remove = i915_pci_remove,
1042 .driver.pm = &i915_pm_ops,
1043};
1044
1da177e4
LT		 1045static int __init i915_init(void)
1046{
1f7a6e37
ZW		 1047 if (!intel_agp_enabled) {
1048 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
1049 return -ENODEV;
1050 }
1051
1da177e4 1052 driver.num_ioctls = i915_max_ioctl;
79e53945
JB		 1053
1054 /*
1055 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1056 * explicitly disabled with the module pararmeter.
1057 *
1058 * Otherwise, just follow the parameter (defaulting to off).
1059 *
1060 * Allow optional vga_text_mode_force boot option to override
1061 * the default behavior.
1062 */
1063#if defined(CONFIG_DRM_I915_KMS)
1064 if (i915_modeset != 0)
1065 driver.driver_features |= DRIVER_MODESET;
1066#endif
1067 if (i915_modeset == 1)
1068 driver.driver_features |= DRIVER_MODESET;
1069
1070#ifdef CONFIG_VGA_CONSOLE
1071 if (vgacon_text_force() && i915_modeset == -1)
1072 driver.driver_features &= ~DRIVER_MODESET;
1073#endif
1074
3885c6bb
CW		 1075 if (!(driver.driver_features & DRIVER_MODESET))
1076 driver.get_vblank_timestamp = NULL;
1077
8410ea3b 1078 return drm_pci_init(&driver, &i915_pci_driver);
1da177e4
LT		 1079}
1080
1081static void __exit i915_exit(void)
1082{
8410ea3b 1083 drm_pci_exit(&driver, &i915_pci_driver);
1da177e4
LT		 1084}
1085
1086module_init(i915_init);
1087module_exit(i915_exit);
1088
b5e89ed5
DA		 1089MODULE_AUTHOR(DRIVER_AUTHOR);
1090MODULE_DESCRIPTION(DRIVER_DESC);
1da177e4 1091MODULE_LICENSE("GPL and additional rights");
f7000883 1092
b7d84096
JB		 1093/* We give fast paths for the really cool registers */
1094#define NEEDS_FORCE_WAKE(dev_priv, reg) \
1095 (((dev_priv)->info->gen >= 6) && \
1096 ((reg) < 0x40000) && \
575155a9
JB		 1097 ((reg) != FORCEWAKE)) && \
1098 (!IS_VALLEYVIEW((dev_priv)->dev))
b7d84096 1099
f7000883
AK		 1100#define __i915_read(x, y) \
1101u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1102 u##x val = 0; \
1103 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
c937504e
KP		 1104 unsigned long irqflags; \
1105 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1106 if (dev_priv->forcewake_count == 0) \
1107 dev_priv->display.force_wake_get(dev_priv); \
f7000883 1108 val = read##y(dev_priv->regs + reg); \
c937504e
KP		 1109 if (dev_priv->forcewake_count == 0) \
1110 dev_priv->display.force_wake_put(dev_priv); \
1111 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
f7000883
AK		 1112 } else { \
1113 val = read##y(dev_priv->regs + reg); \
1114 } \
1115 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1116 return val; \
1117}
1118
1119__i915_read(8, b)
1120__i915_read(16, w)
1121__i915_read(32, l)
1122__i915_read(64, q)
1123#undef __i915_read
1124
1125#define __i915_write(x, y) \
1126void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
67a3744f 1127 u32 __fifo_ret = 0; \
f7000883
AK		 1128 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1129 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
67a3744f 1130 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
f7000883
AK		 1131 } \
1132 write##y(val, dev_priv->regs + reg); \
67a3744f
BW		 1133 if (unlikely(__fifo_ret)) { \
1134 gen6_gt_check_fifodbg(dev_priv); \
1135 } \
f7000883
AK		 1136}
1137__i915_write(8, b)
1138__i915_write(16, w)
1139__i915_write(32, l)
1140__i915_write(64, q)
1141#undef __i915_write
Linux 6.x block layer and io_uring tree(s)