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1da177e4 LT |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 | 29 | |
5669fcac | 30 | #include <linux/device.h> |
e5747e3a | 31 | #include <linux/acpi.h> |
760285e7 DH |
32 | #include <drm/drmP.h> |
33 | #include <drm/i915_drm.h> | |
1da177e4 | 34 | #include "i915_drv.h" |
990bbdad | 35 | #include "i915_trace.h" |
f49f0586 | 36 | #include "intel_drv.h" |
1da177e4 | 37 | |
704ab614 | 38 | #include <linux/apple-gmux.h> |
79e53945 | 39 | #include <linux/console.h> |
e0cd3608 | 40 | #include <linux/module.h> |
d6102977 | 41 | #include <linux/pm_runtime.h> |
704ab614 LW |
42 | #include <linux/vgaarb.h> |
43 | #include <linux/vga_switcheroo.h> | |
760285e7 | 44 | #include <drm/drm_crtc_helper.h> |
79e53945 | 45 | |
112b715e KH |
46 | static struct drm_driver driver; |
47 | ||
a57c774a AK |
48 | #define GEN_DEFAULT_PIPEOFFSETS \ |
49 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ | |
50 | PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \ | |
51 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ | |
52 | TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \ | |
a57c774a AK |
53 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET } |
54 | ||
84fd4f4e RB |
55 | #define GEN_CHV_PIPEOFFSETS \ |
56 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ | |
57 | CHV_PIPE_C_OFFSET }, \ | |
58 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ | |
59 | CHV_TRANSCODER_C_OFFSET, }, \ | |
84fd4f4e RB |
60 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \ |
61 | CHV_PALETTE_C_OFFSET } | |
a57c774a | 62 | |
5efb3e28 VS |
63 | #define CURSOR_OFFSETS \ |
64 | .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET } | |
65 | ||
66 | #define IVB_CURSOR_OFFSETS \ | |
67 | .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET } | |
68 | ||
9a7e8492 | 69 | static const struct intel_device_info intel_i830_info = { |
7eb552ae | 70 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 71 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 72 | .ring_mask = RENDER_RING, |
a57c774a | 73 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 74 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
75 | }; |
76 | ||
9a7e8492 | 77 | static const struct intel_device_info intel_845g_info = { |
7eb552ae | 78 | .gen = 2, .num_pipes = 1, |
31578148 | 79 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 80 | .ring_mask = RENDER_RING, |
a57c774a | 81 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 82 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
83 | }; |
84 | ||
9a7e8492 | 85 | static const struct intel_device_info intel_i85x_info = { |
7eb552ae | 86 | .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2, |
5ce8ba7c | 87 | .cursor_needs_physical = 1, |
31578148 | 88 | .has_overlay = 1, .overlay_needs_physical = 1, |
fd70d52a | 89 | .has_fbc = 1, |
73ae478c | 90 | .ring_mask = RENDER_RING, |
a57c774a | 91 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 92 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
93 | }; |
94 | ||
9a7e8492 | 95 | static const struct intel_device_info intel_i865g_info = { |
7eb552ae | 96 | .gen = 2, .num_pipes = 1, |
31578148 | 97 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 98 | .ring_mask = RENDER_RING, |
a57c774a | 99 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 100 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
101 | }; |
102 | ||
9a7e8492 | 103 | static const struct intel_device_info intel_i915g_info = { |
7eb552ae | 104 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 105 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 106 | .ring_mask = RENDER_RING, |
a57c774a | 107 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 108 | CURSOR_OFFSETS, |
cfdf1fa2 | 109 | }; |
9a7e8492 | 110 | static const struct intel_device_info intel_i915gm_info = { |
7eb552ae | 111 | .gen = 3, .is_mobile = 1, .num_pipes = 2, |
b295d1b6 | 112 | .cursor_needs_physical = 1, |
31578148 | 113 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 114 | .supports_tv = 1, |
fd70d52a | 115 | .has_fbc = 1, |
73ae478c | 116 | .ring_mask = RENDER_RING, |
a57c774a | 117 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 118 | CURSOR_OFFSETS, |
cfdf1fa2 | 119 | }; |
9a7e8492 | 120 | static const struct intel_device_info intel_i945g_info = { |
7eb552ae | 121 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 122 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 123 | .ring_mask = RENDER_RING, |
a57c774a | 124 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 125 | CURSOR_OFFSETS, |
cfdf1fa2 | 126 | }; |
9a7e8492 | 127 | static const struct intel_device_info intel_i945gm_info = { |
7eb552ae | 128 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2, |
b295d1b6 | 129 | .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 130 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 131 | .supports_tv = 1, |
fd70d52a | 132 | .has_fbc = 1, |
73ae478c | 133 | .ring_mask = RENDER_RING, |
a57c774a | 134 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 135 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
136 | }; |
137 | ||
9a7e8492 | 138 | static const struct intel_device_info intel_i965g_info = { |
7eb552ae | 139 | .gen = 4, .is_broadwater = 1, .num_pipes = 2, |
c96c3a8c | 140 | .has_hotplug = 1, |
31578148 | 141 | .has_overlay = 1, |
73ae478c | 142 | .ring_mask = RENDER_RING, |
a57c774a | 143 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 144 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
145 | }; |
146 | ||
9a7e8492 | 147 | static const struct intel_device_info intel_i965gm_info = { |
7eb552ae | 148 | .gen = 4, .is_crestline = 1, .num_pipes = 2, |
e3c4e5dd | 149 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
31578148 | 150 | .has_overlay = 1, |
a6c45cf0 | 151 | .supports_tv = 1, |
73ae478c | 152 | .ring_mask = RENDER_RING, |
a57c774a | 153 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 154 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
155 | }; |
156 | ||
9a7e8492 | 157 | static const struct intel_device_info intel_g33_info = { |
7eb552ae | 158 | .gen = 3, .is_g33 = 1, .num_pipes = 2, |
c96c3a8c | 159 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 160 | .has_overlay = 1, |
73ae478c | 161 | .ring_mask = RENDER_RING, |
a57c774a | 162 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 163 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
164 | }; |
165 | ||
9a7e8492 | 166 | static const struct intel_device_info intel_g45_info = { |
7eb552ae | 167 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2, |
c96c3a8c | 168 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
73ae478c | 169 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 170 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 171 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
172 | }; |
173 | ||
9a7e8492 | 174 | static const struct intel_device_info intel_gm45_info = { |
7eb552ae | 175 | .gen = 4, .is_g4x = 1, .num_pipes = 2, |
e3c4e5dd | 176 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
c96c3a8c | 177 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
a6c45cf0 | 178 | .supports_tv = 1, |
73ae478c | 179 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 180 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 181 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
182 | }; |
183 | ||
9a7e8492 | 184 | static const struct intel_device_info intel_pineview_info = { |
7eb552ae | 185 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2, |
c96c3a8c | 186 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 187 | .has_overlay = 1, |
a57c774a | 188 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 189 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
190 | }; |
191 | ||
9a7e8492 | 192 | static const struct intel_device_info intel_ironlake_d_info = { |
7eb552ae | 193 | .gen = 5, .num_pipes = 2, |
5a117db7 | 194 | .need_gfx_hws = 1, .has_hotplug = 1, |
73ae478c | 195 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 196 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 197 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
198 | }; |
199 | ||
9a7e8492 | 200 | static const struct intel_device_info intel_ironlake_m_info = { |
7eb552ae | 201 | .gen = 5, .is_mobile = 1, .num_pipes = 2, |
e3c4e5dd | 202 | .need_gfx_hws = 1, .has_hotplug = 1, |
c1a9f047 | 203 | .has_fbc = 1, |
73ae478c | 204 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 205 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 206 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
207 | }; |
208 | ||
9a7e8492 | 209 | static const struct intel_device_info intel_sandybridge_d_info = { |
7eb552ae | 210 | .gen = 6, .num_pipes = 2, |
c96c3a8c | 211 | .need_gfx_hws = 1, .has_hotplug = 1, |
cbaef0f1 | 212 | .has_fbc = 1, |
73ae478c | 213 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, |
3d29b842 | 214 | .has_llc = 1, |
a57c774a | 215 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 216 | CURSOR_OFFSETS, |
f6e450a6 EA |
217 | }; |
218 | ||
9a7e8492 | 219 | static const struct intel_device_info intel_sandybridge_m_info = { |
7eb552ae | 220 | .gen = 6, .is_mobile = 1, .num_pipes = 2, |
c96c3a8c | 221 | .need_gfx_hws = 1, .has_hotplug = 1, |
9c04f015 | 222 | .has_fbc = 1, |
73ae478c | 223 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, |
3d29b842 | 224 | .has_llc = 1, |
a57c774a | 225 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 226 | CURSOR_OFFSETS, |
a13e4093 EA |
227 | }; |
228 | ||
219f4fdb BW |
229 | #define GEN7_FEATURES \ |
230 | .gen = 7, .num_pipes = 3, \ | |
231 | .need_gfx_hws = 1, .has_hotplug = 1, \ | |
cbaef0f1 | 232 | .has_fbc = 1, \ |
73ae478c | 233 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ |
6a8beeff WB |
234 | .has_llc = 1, \ |
235 | GEN_DEFAULT_PIPEOFFSETS, \ | |
236 | IVB_CURSOR_OFFSETS | |
219f4fdb | 237 | |
c76b615c | 238 | static const struct intel_device_info intel_ivybridge_d_info = { |
219f4fdb BW |
239 | GEN7_FEATURES, |
240 | .is_ivybridge = 1, | |
c76b615c JB |
241 | }; |
242 | ||
243 | static const struct intel_device_info intel_ivybridge_m_info = { | |
219f4fdb BW |
244 | GEN7_FEATURES, |
245 | .is_ivybridge = 1, | |
246 | .is_mobile = 1, | |
c76b615c JB |
247 | }; |
248 | ||
999bcdea BW |
249 | static const struct intel_device_info intel_ivybridge_q_info = { |
250 | GEN7_FEATURES, | |
251 | .is_ivybridge = 1, | |
252 | .num_pipes = 0, /* legal, last one wins */ | |
253 | }; | |
254 | ||
6a8beeff WB |
255 | #define VLV_FEATURES \ |
256 | .gen = 7, .num_pipes = 2, \ | |
257 | .need_gfx_hws = 1, .has_hotplug = 1, \ | |
258 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ | |
259 | .display_mmio_offset = VLV_DISPLAY_BASE, \ | |
260 | GEN_DEFAULT_PIPEOFFSETS, \ | |
261 | CURSOR_OFFSETS | |
262 | ||
70a3eb7a | 263 | static const struct intel_device_info intel_valleyview_m_info = { |
6a8beeff | 264 | VLV_FEATURES, |
70a3eb7a | 265 | .is_valleyview = 1, |
6a8beeff | 266 | .is_mobile = 1, |
70a3eb7a JB |
267 | }; |
268 | ||
269 | static const struct intel_device_info intel_valleyview_d_info = { | |
6a8beeff | 270 | VLV_FEATURES, |
70a3eb7a JB |
271 | .is_valleyview = 1, |
272 | }; | |
273 | ||
6a8beeff WB |
274 | #define HSW_FEATURES \ |
275 | GEN7_FEATURES, \ | |
276 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ | |
277 | .has_ddi = 1, \ | |
278 | .has_fpga_dbg = 1 | |
279 | ||
4cae9ae0 | 280 | static const struct intel_device_info intel_haswell_d_info = { |
6a8beeff | 281 | HSW_FEATURES, |
219f4fdb | 282 | .is_haswell = 1, |
4cae9ae0 ED |
283 | }; |
284 | ||
285 | static const struct intel_device_info intel_haswell_m_info = { | |
6a8beeff | 286 | HSW_FEATURES, |
219f4fdb BW |
287 | .is_haswell = 1, |
288 | .is_mobile = 1, | |
c76b615c JB |
289 | }; |
290 | ||
4d4dead6 | 291 | static const struct intel_device_info intel_broadwell_d_info = { |
6a8beeff WB |
292 | HSW_FEATURES, |
293 | .gen = 8, | |
4d4dead6 BW |
294 | }; |
295 | ||
296 | static const struct intel_device_info intel_broadwell_m_info = { | |
6a8beeff WB |
297 | HSW_FEATURES, |
298 | .gen = 8, .is_mobile = 1, | |
4d4dead6 BW |
299 | }; |
300 | ||
fd3c269f | 301 | static const struct intel_device_info intel_broadwell_gt3d_info = { |
6a8beeff WB |
302 | HSW_FEATURES, |
303 | .gen = 8, | |
845f74a7 | 304 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
fd3c269f ZY |
305 | }; |
306 | ||
307 | static const struct intel_device_info intel_broadwell_gt3m_info = { | |
6a8beeff WB |
308 | HSW_FEATURES, |
309 | .gen = 8, .is_mobile = 1, | |
845f74a7 | 310 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
fd3c269f ZY |
311 | }; |
312 | ||
7d87a7f7 | 313 | static const struct intel_device_info intel_cherryview_info = { |
07fddb14 | 314 | .gen = 8, .num_pipes = 3, |
7d87a7f7 VS |
315 | .need_gfx_hws = 1, .has_hotplug = 1, |
316 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
666a4537 | 317 | .is_cherryview = 1, |
7d87a7f7 | 318 | .display_mmio_offset = VLV_DISPLAY_BASE, |
84fd4f4e | 319 | GEN_CHV_PIPEOFFSETS, |
5efb3e28 | 320 | CURSOR_OFFSETS, |
7d87a7f7 VS |
321 | }; |
322 | ||
72bbf0af | 323 | static const struct intel_device_info intel_skylake_info = { |
6a8beeff | 324 | HSW_FEATURES, |
7201c0b3 | 325 | .is_skylake = 1, |
6a8beeff | 326 | .gen = 9, |
72bbf0af DL |
327 | }; |
328 | ||
719388e1 | 329 | static const struct intel_device_info intel_skylake_gt3_info = { |
a9287dbc | 330 | HSW_FEATURES, |
719388e1 | 331 | .is_skylake = 1, |
6a8beeff | 332 | .gen = 9, |
719388e1 | 333 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
719388e1 DL |
334 | }; |
335 | ||
1347f5b4 DL |
336 | static const struct intel_device_info intel_broxton_info = { |
337 | .is_preliminary = 1, | |
7526ac19 | 338 | .is_broxton = 1, |
1347f5b4 DL |
339 | .gen = 9, |
340 | .need_gfx_hws = 1, .has_hotplug = 1, | |
341 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
342 | .num_pipes = 3, | |
343 | .has_ddi = 1, | |
6c908bf4 | 344 | .has_fpga_dbg = 1, |
ce89db2e | 345 | .has_fbc = 1, |
1347f5b4 DL |
346 | GEN_DEFAULT_PIPEOFFSETS, |
347 | IVB_CURSOR_OFFSETS, | |
348 | }; | |
349 | ||
ef11bdb3 | 350 | static const struct intel_device_info intel_kabylake_info = { |
6a8beeff | 351 | HSW_FEATURES, |
ef11bdb3 RV |
352 | .is_preliminary = 1, |
353 | .is_kabylake = 1, | |
354 | .gen = 9, | |
ef11bdb3 RV |
355 | }; |
356 | ||
357 | static const struct intel_device_info intel_kabylake_gt3_info = { | |
6a8beeff | 358 | HSW_FEATURES, |
ef11bdb3 RV |
359 | .is_preliminary = 1, |
360 | .is_kabylake = 1, | |
361 | .gen = 9, | |
ef11bdb3 | 362 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
ef11bdb3 RV |
363 | }; |
364 | ||
a0a18075 JB |
365 | /* |
366 | * Make sure any device matches here are from most specific to most | |
367 | * general. For example, since the Quanta match is based on the subsystem | |
368 | * and subvendor IDs, we need it to come before the more general IVB | |
369 | * PCI ID matches, otherwise we'll use the wrong info struct above. | |
370 | */ | |
3cb27f38 JN |
371 | static const struct pci_device_id pciidlist[] = { |
372 | INTEL_I830_IDS(&intel_i830_info), | |
373 | INTEL_I845G_IDS(&intel_845g_info), | |
374 | INTEL_I85X_IDS(&intel_i85x_info), | |
375 | INTEL_I865G_IDS(&intel_i865g_info), | |
376 | INTEL_I915G_IDS(&intel_i915g_info), | |
377 | INTEL_I915GM_IDS(&intel_i915gm_info), | |
378 | INTEL_I945G_IDS(&intel_i945g_info), | |
379 | INTEL_I945GM_IDS(&intel_i945gm_info), | |
380 | INTEL_I965G_IDS(&intel_i965g_info), | |
381 | INTEL_G33_IDS(&intel_g33_info), | |
382 | INTEL_I965GM_IDS(&intel_i965gm_info), | |
383 | INTEL_GM45_IDS(&intel_gm45_info), | |
384 | INTEL_G45_IDS(&intel_g45_info), | |
385 | INTEL_PINEVIEW_IDS(&intel_pineview_info), | |
386 | INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), | |
387 | INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), | |
388 | INTEL_SNB_D_IDS(&intel_sandybridge_d_info), | |
389 | INTEL_SNB_M_IDS(&intel_sandybridge_m_info), | |
390 | INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ | |
391 | INTEL_IVB_M_IDS(&intel_ivybridge_m_info), | |
392 | INTEL_IVB_D_IDS(&intel_ivybridge_d_info), | |
393 | INTEL_HSW_D_IDS(&intel_haswell_d_info), | |
394 | INTEL_HSW_M_IDS(&intel_haswell_m_info), | |
395 | INTEL_VLV_M_IDS(&intel_valleyview_m_info), | |
396 | INTEL_VLV_D_IDS(&intel_valleyview_d_info), | |
397 | INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), | |
398 | INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), | |
399 | INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), | |
400 | INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), | |
401 | INTEL_CHV_IDS(&intel_cherryview_info), | |
402 | INTEL_SKL_GT1_IDS(&intel_skylake_info), | |
403 | INTEL_SKL_GT2_IDS(&intel_skylake_info), | |
404 | INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), | |
15620206 | 405 | INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info), |
3cb27f38 | 406 | INTEL_BXT_IDS(&intel_broxton_info), |
d97044b6 D |
407 | INTEL_KBL_GT1_IDS(&intel_kabylake_info), |
408 | INTEL_KBL_GT2_IDS(&intel_kabylake_info), | |
409 | INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info), | |
8b10c0cf | 410 | INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info), |
49ae35f2 | 411 | {0, 0, 0} |
1da177e4 LT |
412 | }; |
413 | ||
79e53945 | 414 | MODULE_DEVICE_TABLE(pci, pciidlist); |
79e53945 | 415 | |
30c964a6 RB |
416 | static enum intel_pch intel_virt_detect_pch(struct drm_device *dev) |
417 | { | |
418 | enum intel_pch ret = PCH_NOP; | |
419 | ||
420 | /* | |
421 | * In a virtualized passthrough environment we can be in a | |
422 | * setup where the ISA bridge is not able to be passed through. | |
423 | * In this case, a south bridge can be emulated and we have to | |
424 | * make an educated guess as to which PCH is really there. | |
425 | */ | |
426 | ||
427 | if (IS_GEN5(dev)) { | |
428 | ret = PCH_IBX; | |
429 | DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n"); | |
430 | } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) { | |
431 | ret = PCH_CPT; | |
432 | DRM_DEBUG_KMS("Assuming CouarPoint PCH\n"); | |
433 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
434 | ret = PCH_LPT; | |
435 | DRM_DEBUG_KMS("Assuming LynxPoint PCH\n"); | |
ef11bdb3 | 436 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
30c964a6 RB |
437 | ret = PCH_SPT; |
438 | DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n"); | |
439 | } | |
440 | ||
441 | return ret; | |
442 | } | |
443 | ||
0206e353 | 444 | void intel_detect_pch(struct drm_device *dev) |
3bad0781 ZW |
445 | { |
446 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bcdb72ac | 447 | struct pci_dev *pch = NULL; |
3bad0781 | 448 | |
ce1bb329 BW |
449 | /* In all current cases, num_pipes is equivalent to the PCH_NOP setting |
450 | * (which really amounts to a PCH but no South Display). | |
451 | */ | |
452 | if (INTEL_INFO(dev)->num_pipes == 0) { | |
453 | dev_priv->pch_type = PCH_NOP; | |
ce1bb329 BW |
454 | return; |
455 | } | |
456 | ||
3bad0781 ZW |
457 | /* |
458 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to | |
459 | * make graphics device passthrough work easy for VMM, that only | |
460 | * need to expose ISA bridge to let driver know the real hardware | |
461 | * underneath. This is a requirement from virtualization team. | |
6a9c4b35 RG |
462 | * |
463 | * In some virtualized environments (e.g. XEN), there is irrelevant | |
464 | * ISA bridge in the system. To work reliably, we should scan trhough | |
465 | * all the ISA bridge devices and check for the first match, instead | |
466 | * of only checking the first one. | |
3bad0781 | 467 | */ |
bcdb72ac | 468 | while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) { |
3bad0781 | 469 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { |
bcdb72ac | 470 | unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK; |
17a303ec | 471 | dev_priv->pch_id = id; |
3bad0781 | 472 | |
90711d50 JB |
473 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
474 | dev_priv->pch_type = PCH_IBX; | |
475 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); | |
7fcb83cd | 476 | WARN_ON(!IS_GEN5(dev)); |
90711d50 | 477 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { |
3bad0781 ZW |
478 | dev_priv->pch_type = PCH_CPT; |
479 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); | |
7fcb83cd | 480 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
c792513b JB |
481 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
482 | /* PantherPoint is CPT compatible */ | |
483 | dev_priv->pch_type = PCH_CPT; | |
492ab669 | 484 | DRM_DEBUG_KMS("Found PantherPoint PCH\n"); |
7fcb83cd | 485 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
eb877ebf ED |
486 | } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
487 | dev_priv->pch_type = PCH_LPT; | |
488 | DRM_DEBUG_KMS("Found LynxPoint PCH\n"); | |
a35cc9d0 RV |
489 | WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev)); |
490 | WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev)); | |
e76e0634 BW |
491 | } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
492 | dev_priv->pch_type = PCH_LPT; | |
493 | DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); | |
a35cc9d0 RV |
494 | WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev)); |
495 | WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev)); | |
e7e7ea20 S |
496 | } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) { |
497 | dev_priv->pch_type = PCH_SPT; | |
498 | DRM_DEBUG_KMS("Found SunrisePoint PCH\n"); | |
ef11bdb3 RV |
499 | WARN_ON(!IS_SKYLAKE(dev) && |
500 | !IS_KABYLAKE(dev)); | |
e7e7ea20 S |
501 | } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) { |
502 | dev_priv->pch_type = PCH_SPT; | |
503 | DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n"); | |
ef11bdb3 RV |
504 | WARN_ON(!IS_SKYLAKE(dev) && |
505 | !IS_KABYLAKE(dev)); | |
39bfcd52 | 506 | } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) || |
f2e30510 GH |
507 | ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) && |
508 | pch->subsystem_vendor == 0x1af4 && | |
509 | pch->subsystem_device == 0x1100)) { | |
30c964a6 | 510 | dev_priv->pch_type = intel_virt_detect_pch(dev); |
bcdb72ac ID |
511 | } else |
512 | continue; | |
513 | ||
6a9c4b35 | 514 | break; |
3bad0781 | 515 | } |
3bad0781 | 516 | } |
6a9c4b35 | 517 | if (!pch) |
bcdb72ac ID |
518 | DRM_DEBUG_KMS("No PCH found.\n"); |
519 | ||
520 | pci_dev_put(pch); | |
3bad0781 ZW |
521 | } |
522 | ||
2911a35b BW |
523 | bool i915_semaphore_is_enabled(struct drm_device *dev) |
524 | { | |
525 | if (INTEL_INFO(dev)->gen < 6) | |
a08acaf2 | 526 | return false; |
2911a35b | 527 | |
d330a953 JN |
528 | if (i915.semaphores >= 0) |
529 | return i915.semaphores; | |
2911a35b | 530 | |
71386ef9 OM |
531 | /* TODO: make semaphores and Execlists play nicely together */ |
532 | if (i915.enable_execlists) | |
533 | return false; | |
534 | ||
be71eabe RV |
535 | /* Until we get further testing... */ |
536 | if (IS_GEN8(dev)) | |
537 | return false; | |
538 | ||
59de3295 | 539 | #ifdef CONFIG_INTEL_IOMMU |
2911a35b | 540 | /* Enable semaphores on SNB when IO remapping is off */ |
59de3295 DV |
541 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) |
542 | return false; | |
543 | #endif | |
2911a35b | 544 | |
a08acaf2 | 545 | return true; |
2911a35b BW |
546 | } |
547 | ||
07f9cd0b ID |
548 | static void intel_suspend_encoders(struct drm_i915_private *dev_priv) |
549 | { | |
550 | struct drm_device *dev = dev_priv->dev; | |
19c8054c | 551 | struct intel_encoder *encoder; |
07f9cd0b ID |
552 | |
553 | drm_modeset_lock_all(dev); | |
19c8054c JN |
554 | for_each_intel_encoder(dev, encoder) |
555 | if (encoder->suspend) | |
556 | encoder->suspend(encoder); | |
07f9cd0b ID |
557 | drm_modeset_unlock_all(dev); |
558 | } | |
559 | ||
ebc32824 | 560 | static int intel_suspend_complete(struct drm_i915_private *dev_priv); |
1a5df187 PZ |
561 | static int vlv_resume_prepare(struct drm_i915_private *dev_priv, |
562 | bool rpm_resume); | |
a9a6b73a | 563 | static int bxt_resume_prepare(struct drm_i915_private *dev_priv); |
f75a1985 | 564 | |
bc87229f ID |
565 | static bool suspend_to_idle(struct drm_i915_private *dev_priv) |
566 | { | |
567 | #if IS_ENABLED(CONFIG_ACPI_SLEEP) | |
568 | if (acpi_target_system_state() < ACPI_STATE_S3) | |
569 | return true; | |
570 | #endif | |
571 | return false; | |
572 | } | |
ebc32824 | 573 | |
5e365c39 | 574 | static int i915_drm_suspend(struct drm_device *dev) |
ba8bbcf6 | 575 | { |
61caf87c | 576 | struct drm_i915_private *dev_priv = dev->dev_private; |
e5747e3a | 577 | pci_power_t opregion_target_state; |
d5818938 | 578 | int error; |
61caf87c | 579 | |
b8efb17b ZR |
580 | /* ignore lid events during suspend */ |
581 | mutex_lock(&dev_priv->modeset_restore_lock); | |
582 | dev_priv->modeset_restore = MODESET_SUSPENDED; | |
583 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
584 | ||
1f814dac ID |
585 | disable_rpm_wakeref_asserts(dev_priv); |
586 | ||
c67a470b PZ |
587 | /* We do a lot of poking in a lot of registers, make sure they work |
588 | * properly. */ | |
da7e29bd | 589 | intel_display_set_init_power(dev_priv, true); |
cb10799c | 590 | |
5bcf719b DA |
591 | drm_kms_helper_poll_disable(dev); |
592 | ||
ba8bbcf6 | 593 | pci_save_state(dev->pdev); |
ba8bbcf6 | 594 | |
d5818938 DV |
595 | error = i915_gem_suspend(dev); |
596 | if (error) { | |
597 | dev_err(&dev->pdev->dev, | |
598 | "GEM idle failed, resume might fail\n"); | |
1f814dac | 599 | goto out; |
d5818938 | 600 | } |
db1b76ca | 601 | |
a1c41994 AD |
602 | intel_guc_suspend(dev); |
603 | ||
d5818938 | 604 | intel_suspend_gt_powersave(dev); |
a261b246 | 605 | |
6b72d486 | 606 | intel_display_suspend(dev); |
2eb5252e | 607 | |
d5818938 | 608 | intel_dp_mst_suspend(dev); |
7d708ee4 | 609 | |
d5818938 DV |
610 | intel_runtime_pm_disable_interrupts(dev_priv); |
611 | intel_hpd_cancel_work(dev_priv); | |
09b64267 | 612 | |
d5818938 | 613 | intel_suspend_encoders(dev_priv); |
0e32b39c | 614 | |
d5818938 | 615 | intel_suspend_hw(dev); |
5669fcac | 616 | |
828c7908 BW |
617 | i915_gem_suspend_gtt_mappings(dev); |
618 | ||
9e06dd39 JB |
619 | i915_save_state(dev); |
620 | ||
bc87229f | 621 | opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold; |
e5747e3a JB |
622 | intel_opregion_notify_adapter(dev, opregion_target_state); |
623 | ||
156c7ca0 | 624 | intel_uncore_forcewake_reset(dev, false); |
44834a67 | 625 | intel_opregion_fini(dev); |
8ee1c3db | 626 | |
82e3b8c1 | 627 | intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true); |
3fa016a0 | 628 | |
62d5d69b MK |
629 | dev_priv->suspend_count++; |
630 | ||
85e90679 KCA |
631 | intel_display_set_init_power(dev_priv, false); |
632 | ||
f514c2d8 ID |
633 | if (HAS_CSR(dev_priv)) |
634 | flush_work(&dev_priv->csr.work); | |
635 | ||
1f814dac ID |
636 | out: |
637 | enable_rpm_wakeref_asserts(dev_priv); | |
638 | ||
639 | return error; | |
84b79f8d RW |
640 | } |
641 | ||
ab3be73f | 642 | static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation) |
c3c09c95 ID |
643 | { |
644 | struct drm_i915_private *dev_priv = drm_dev->dev_private; | |
bc87229f | 645 | bool fw_csr; |
c3c09c95 ID |
646 | int ret; |
647 | ||
1f814dac ID |
648 | disable_rpm_wakeref_asserts(dev_priv); |
649 | ||
bc87229f ID |
650 | fw_csr = suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload; |
651 | /* | |
652 | * In case of firmware assisted context save/restore don't manually | |
653 | * deinit the power domains. This also means the CSR/DMC firmware will | |
654 | * stay active, it will power down any HW resources as required and | |
655 | * also enable deeper system power states that would be blocked if the | |
656 | * firmware was inactive. | |
657 | */ | |
658 | if (!fw_csr) | |
659 | intel_power_domains_suspend(dev_priv); | |
73dfc227 | 660 | |
c3c09c95 ID |
661 | ret = intel_suspend_complete(dev_priv); |
662 | ||
663 | if (ret) { | |
664 | DRM_ERROR("Suspend complete failed: %d\n", ret); | |
bc87229f ID |
665 | if (!fw_csr) |
666 | intel_power_domains_init_hw(dev_priv, true); | |
c3c09c95 | 667 | |
1f814dac | 668 | goto out; |
c3c09c95 ID |
669 | } |
670 | ||
671 | pci_disable_device(drm_dev->pdev); | |
ab3be73f | 672 | /* |
54875571 | 673 | * During hibernation on some platforms the BIOS may try to access |
ab3be73f ID |
674 | * the device even though it's already in D3 and hang the machine. So |
675 | * leave the device in D0 on those platforms and hope the BIOS will | |
54875571 ID |
676 | * power down the device properly. The issue was seen on multiple old |
677 | * GENs with different BIOS vendors, so having an explicit blacklist | |
678 | * is inpractical; apply the workaround on everything pre GEN6. The | |
679 | * platforms where the issue was seen: | |
680 | * Lenovo Thinkpad X301, X61s, X60, T60, X41 | |
681 | * Fujitsu FSC S7110 | |
682 | * Acer Aspire 1830T | |
ab3be73f | 683 | */ |
54875571 | 684 | if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6)) |
ab3be73f | 685 | pci_set_power_state(drm_dev->pdev, PCI_D3hot); |
c3c09c95 | 686 | |
bc87229f ID |
687 | dev_priv->suspended_to_idle = suspend_to_idle(dev_priv); |
688 | ||
1f814dac ID |
689 | out: |
690 | enable_rpm_wakeref_asserts(dev_priv); | |
691 | ||
692 | return ret; | |
c3c09c95 ID |
693 | } |
694 | ||
1751fcf9 | 695 | int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state) |
84b79f8d RW |
696 | { |
697 | int error; | |
698 | ||
699 | if (!dev || !dev->dev_private) { | |
700 | DRM_ERROR("dev: %p\n", dev); | |
701 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); | |
702 | return -ENODEV; | |
703 | } | |
704 | ||
0b14cbd2 ID |
705 | if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND && |
706 | state.event != PM_EVENT_FREEZE)) | |
707 | return -EINVAL; | |
5bcf719b DA |
708 | |
709 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
710 | return 0; | |
6eecba33 | 711 | |
5e365c39 | 712 | error = i915_drm_suspend(dev); |
84b79f8d RW |
713 | if (error) |
714 | return error; | |
715 | ||
ab3be73f | 716 | return i915_drm_suspend_late(dev, false); |
ba8bbcf6 JB |
717 | } |
718 | ||
5e365c39 | 719 | static int i915_drm_resume(struct drm_device *dev) |
76c4b250 ID |
720 | { |
721 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9d49c0ef | 722 | |
1f814dac ID |
723 | disable_rpm_wakeref_asserts(dev_priv); |
724 | ||
d5818938 DV |
725 | mutex_lock(&dev->struct_mutex); |
726 | i915_gem_restore_gtt_mappings(dev); | |
727 | mutex_unlock(&dev->struct_mutex); | |
9d49c0ef | 728 | |
61caf87c | 729 | i915_restore_state(dev); |
44834a67 | 730 | intel_opregion_setup(dev); |
61caf87c | 731 | |
d5818938 DV |
732 | intel_init_pch_refclk(dev); |
733 | drm_mode_config_reset(dev); | |
1833b134 | 734 | |
364aece0 PA |
735 | /* |
736 | * Interrupts have to be enabled before any batches are run. If not the | |
737 | * GPU will hang. i915_gem_init_hw() will initiate batches to | |
738 | * update/restore the context. | |
739 | * | |
740 | * Modeset enabling in intel_modeset_init_hw() also needs working | |
741 | * interrupts. | |
742 | */ | |
743 | intel_runtime_pm_enable_interrupts(dev_priv); | |
744 | ||
d5818938 DV |
745 | mutex_lock(&dev->struct_mutex); |
746 | if (i915_gem_init_hw(dev)) { | |
747 | DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n"); | |
805de8f4 | 748 | atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter); |
d5818938 DV |
749 | } |
750 | mutex_unlock(&dev->struct_mutex); | |
226485e9 | 751 | |
a1c41994 AD |
752 | intel_guc_resume(dev); |
753 | ||
d5818938 | 754 | intel_modeset_init_hw(dev); |
24576d23 | 755 | |
d5818938 DV |
756 | spin_lock_irq(&dev_priv->irq_lock); |
757 | if (dev_priv->display.hpd_irq_setup) | |
758 | dev_priv->display.hpd_irq_setup(dev); | |
759 | spin_unlock_irq(&dev_priv->irq_lock); | |
0e32b39c | 760 | |
d5818938 | 761 | intel_dp_mst_resume(dev); |
e7d6f7d7 | 762 | |
1e8817b7 L |
763 | intel_display_resume(dev); |
764 | ||
d5818938 DV |
765 | /* |
766 | * ... but also need to make sure that hotplug processing | |
767 | * doesn't cause havoc. Like in the driver load code we don't | |
768 | * bother with the tiny race here where we might loose hotplug | |
769 | * notifications. | |
770 | * */ | |
771 | intel_hpd_init(dev_priv); | |
772 | /* Config may have changed between suspend and resume */ | |
773 | drm_helper_hpd_irq_event(dev); | |
1daed3fb | 774 | |
44834a67 CW |
775 | intel_opregion_init(dev); |
776 | ||
82e3b8c1 | 777 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false); |
073f34d9 | 778 | |
b8efb17b ZR |
779 | mutex_lock(&dev_priv->modeset_restore_lock); |
780 | dev_priv->modeset_restore = MODESET_DONE; | |
781 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
8a187455 | 782 | |
e5747e3a JB |
783 | intel_opregion_notify_adapter(dev, PCI_D0); |
784 | ||
ee6f280e ID |
785 | drm_kms_helper_poll_enable(dev); |
786 | ||
1f814dac ID |
787 | enable_rpm_wakeref_asserts(dev_priv); |
788 | ||
074c6ada | 789 | return 0; |
84b79f8d RW |
790 | } |
791 | ||
5e365c39 | 792 | static int i915_drm_resume_early(struct drm_device *dev) |
84b79f8d | 793 | { |
36d61e67 | 794 | struct drm_i915_private *dev_priv = dev->dev_private; |
dab9a266 | 795 | int ret; |
36d61e67 | 796 | |
76c4b250 ID |
797 | /* |
798 | * We have a resume ordering issue with the snd-hda driver also | |
799 | * requiring our device to be power up. Due to the lack of a | |
800 | * parent/child relationship we currently solve this with an early | |
801 | * resume hook. | |
802 | * | |
803 | * FIXME: This should be solved with a special hdmi sink device or | |
804 | * similar so that power domains can be employed. | |
805 | */ | |
dab9a266 ID |
806 | |
807 | /* | |
808 | * Note that we need to set the power state explicitly, since we | |
809 | * powered off the device during freeze and the PCI core won't power | |
810 | * it back up for us during thaw. Powering off the device during | |
811 | * freeze is not a hard requirement though, and during the | |
812 | * suspend/resume phases the PCI core makes sure we get here with the | |
813 | * device powered on. So in case we change our freeze logic and keep | |
814 | * the device powered we can also remove the following set power state | |
815 | * call. | |
816 | */ | |
817 | ret = pci_set_power_state(dev->pdev, PCI_D0); | |
818 | if (ret) { | |
819 | DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret); | |
820 | goto out; | |
821 | } | |
822 | ||
823 | /* | |
824 | * Note that pci_enable_device() first enables any parent bridge | |
825 | * device and only then sets the power state for this device. The | |
826 | * bridge enabling is a nop though, since bridge devices are resumed | |
827 | * first. The order of enabling power and enabling the device is | |
828 | * imposed by the PCI core as described above, so here we preserve the | |
829 | * same order for the freeze/thaw phases. | |
830 | * | |
831 | * TODO: eventually we should remove pci_disable_device() / | |
832 | * pci_enable_enable_device() from suspend/resume. Due to how they | |
833 | * depend on the device enable refcount we can't anyway depend on them | |
834 | * disabling/enabling the device. | |
835 | */ | |
bc87229f ID |
836 | if (pci_enable_device(dev->pdev)) { |
837 | ret = -EIO; | |
838 | goto out; | |
839 | } | |
84b79f8d RW |
840 | |
841 | pci_set_master(dev->pdev); | |
842 | ||
1f814dac ID |
843 | disable_rpm_wakeref_asserts(dev_priv); |
844 | ||
666a4537 | 845 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
1a5df187 | 846 | ret = vlv_resume_prepare(dev_priv, false); |
36d61e67 | 847 | if (ret) |
ff0b187f DL |
848 | DRM_ERROR("Resume prepare failed: %d, continuing anyway\n", |
849 | ret); | |
36d61e67 ID |
850 | |
851 | intel_uncore_early_sanitize(dev, true); | |
efee833a | 852 | |
a9a6b73a DL |
853 | if (IS_BROXTON(dev)) |
854 | ret = bxt_resume_prepare(dev_priv); | |
a9a6b73a DL |
855 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
856 | hsw_disable_pc8(dev_priv); | |
efee833a | 857 | |
36d61e67 | 858 | intel_uncore_sanitize(dev); |
bc87229f ID |
859 | |
860 | if (!(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload)) | |
861 | intel_power_domains_init_hw(dev_priv, true); | |
862 | ||
863 | out: | |
864 | dev_priv->suspended_to_idle = false; | |
36d61e67 | 865 | |
1f814dac ID |
866 | enable_rpm_wakeref_asserts(dev_priv); |
867 | ||
36d61e67 | 868 | return ret; |
76c4b250 ID |
869 | } |
870 | ||
1751fcf9 | 871 | int i915_resume_switcheroo(struct drm_device *dev) |
76c4b250 | 872 | { |
50a0072f | 873 | int ret; |
76c4b250 | 874 | |
097dd837 ID |
875 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
876 | return 0; | |
877 | ||
5e365c39 | 878 | ret = i915_drm_resume_early(dev); |
50a0072f ID |
879 | if (ret) |
880 | return ret; | |
881 | ||
5a17514e ID |
882 | return i915_drm_resume(dev); |
883 | } | |
884 | ||
11ed50ec | 885 | /** |
f3953dcb | 886 | * i915_reset - reset chip after a hang |
11ed50ec | 887 | * @dev: drm device to reset |
11ed50ec BG |
888 | * |
889 | * Reset the chip. Useful if a hang is detected. Returns zero on successful | |
890 | * reset or otherwise an error code. | |
891 | * | |
892 | * Procedure is fairly simple: | |
893 | * - reset the chip using the reset reg | |
894 | * - re-init context state | |
895 | * - re-init hardware status page | |
896 | * - re-init ring buffer | |
897 | * - re-init interrupt state | |
898 | * - re-init display | |
899 | */ | |
d4b8bb2a | 900 | int i915_reset(struct drm_device *dev) |
11ed50ec | 901 | { |
50227e1c | 902 | struct drm_i915_private *dev_priv = dev->dev_private; |
2e7c8ee7 | 903 | bool simulated; |
0573ed4a | 904 | int ret; |
11ed50ec | 905 | |
dbea3cea ID |
906 | intel_reset_gt_powersave(dev); |
907 | ||
d54a02c0 | 908 | mutex_lock(&dev->struct_mutex); |
11ed50ec | 909 | |
069efc1d | 910 | i915_gem_reset(dev); |
77f01230 | 911 | |
2e7c8ee7 CW |
912 | simulated = dev_priv->gpu_error.stop_rings != 0; |
913 | ||
be62acb4 MK |
914 | ret = intel_gpu_reset(dev); |
915 | ||
916 | /* Also reset the gpu hangman. */ | |
917 | if (simulated) { | |
918 | DRM_INFO("Simulated gpu hang, resetting stop_rings\n"); | |
919 | dev_priv->gpu_error.stop_rings = 0; | |
920 | if (ret == -ENODEV) { | |
f2d91a2c DV |
921 | DRM_INFO("Reset not implemented, but ignoring " |
922 | "error for simulated gpu hangs\n"); | |
be62acb4 MK |
923 | ret = 0; |
924 | } | |
2e7c8ee7 | 925 | } |
be62acb4 | 926 | |
d8f2716a DV |
927 | if (i915_stop_ring_allow_warn(dev_priv)) |
928 | pr_notice("drm/i915: Resetting chip after gpu hang\n"); | |
929 | ||
0573ed4a | 930 | if (ret) { |
f2d91a2c | 931 | DRM_ERROR("Failed to reset chip: %i\n", ret); |
f953c935 | 932 | mutex_unlock(&dev->struct_mutex); |
f803aa55 | 933 | return ret; |
11ed50ec BG |
934 | } |
935 | ||
1362b776 VS |
936 | intel_overlay_reset(dev_priv); |
937 | ||
11ed50ec BG |
938 | /* Ok, now get things going again... */ |
939 | ||
940 | /* | |
941 | * Everything depends on having the GTT running, so we need to start | |
942 | * there. Fortunately we don't need to do this unless we reset the | |
943 | * chip at a PCI level. | |
944 | * | |
945 | * Next we need to restore the context, but we don't use those | |
946 | * yet either... | |
947 | * | |
948 | * Ring buffer needs to be re-initialized in the KMS case, or if X | |
949 | * was running at the time of the reset (i.e. we weren't VT | |
950 | * switched away). | |
951 | */ | |
6689c167 | 952 | |
33d30a9c DV |
953 | /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */ |
954 | dev_priv->gpu_error.reload_in_reset = true; | |
6689c167 | 955 | |
33d30a9c | 956 | ret = i915_gem_init_hw(dev); |
6689c167 | 957 | |
33d30a9c | 958 | dev_priv->gpu_error.reload_in_reset = false; |
f817586c | 959 | |
33d30a9c DV |
960 | mutex_unlock(&dev->struct_mutex); |
961 | if (ret) { | |
962 | DRM_ERROR("Failed hw init on reset %d\n", ret); | |
963 | return ret; | |
11ed50ec BG |
964 | } |
965 | ||
33d30a9c DV |
966 | /* |
967 | * rps/rc6 re-init is necessary to restore state lost after the | |
968 | * reset and the re-install of gt irqs. Skip for ironlake per | |
969 | * previous concerns that it doesn't respond well to some forms | |
970 | * of re-init after reset. | |
971 | */ | |
972 | if (INTEL_INFO(dev)->gen > 5) | |
973 | intel_enable_gt_powersave(dev); | |
974 | ||
11ed50ec BG |
975 | return 0; |
976 | } | |
977 | ||
56550d94 | 978 | static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
112b715e | 979 | { |
01a06850 DV |
980 | struct intel_device_info *intel_info = |
981 | (struct intel_device_info *) ent->driver_data; | |
982 | ||
d330a953 | 983 | if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) { |
b833d685 BW |
984 | DRM_INFO("This hardware requires preliminary hardware support.\n" |
985 | "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n"); | |
986 | return -ENODEV; | |
987 | } | |
988 | ||
5fe49d86 CW |
989 | /* Only bind to function 0 of the device. Early generations |
990 | * used function 1 as a placeholder for multi-head. This causes | |
991 | * us confusion instead, especially on the systems where both | |
992 | * functions have the same PCI-ID! | |
993 | */ | |
994 | if (PCI_FUNC(pdev->devfn)) | |
995 | return -ENODEV; | |
996 | ||
704ab614 LW |
997 | /* |
998 | * apple-gmux is needed on dual GPU MacBook Pro | |
999 | * to probe the panel if we're the inactive GPU. | |
1000 | */ | |
1001 | if (IS_ENABLED(CONFIG_VGA_ARB) && IS_ENABLED(CONFIG_VGA_SWITCHEROO) && | |
1002 | apple_gmux_present() && pdev != vga_default_device() && | |
1003 | !vga_switcheroo_handler_flags()) | |
1004 | return -EPROBE_DEFER; | |
1005 | ||
dcdb1674 | 1006 | return drm_get_pci_dev(pdev, ent, &driver); |
112b715e KH |
1007 | } |
1008 | ||
1009 | static void | |
1010 | i915_pci_remove(struct pci_dev *pdev) | |
1011 | { | |
1012 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1013 | ||
1014 | drm_put_dev(dev); | |
1015 | } | |
1016 | ||
84b79f8d | 1017 | static int i915_pm_suspend(struct device *dev) |
112b715e | 1018 | { |
84b79f8d RW |
1019 | struct pci_dev *pdev = to_pci_dev(dev); |
1020 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
112b715e | 1021 | |
84b79f8d RW |
1022 | if (!drm_dev || !drm_dev->dev_private) { |
1023 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
1024 | return -ENODEV; | |
1025 | } | |
112b715e | 1026 | |
5bcf719b DA |
1027 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
1028 | return 0; | |
1029 | ||
5e365c39 | 1030 | return i915_drm_suspend(drm_dev); |
76c4b250 ID |
1031 | } |
1032 | ||
1033 | static int i915_pm_suspend_late(struct device *dev) | |
1034 | { | |
888d0d42 | 1035 | struct drm_device *drm_dev = dev_to_i915(dev)->dev; |
76c4b250 ID |
1036 | |
1037 | /* | |
c965d995 | 1038 | * We have a suspend ordering issue with the snd-hda driver also |
76c4b250 ID |
1039 | * requiring our device to be power up. Due to the lack of a |
1040 | * parent/child relationship we currently solve this with an late | |
1041 | * suspend hook. | |
1042 | * | |
1043 | * FIXME: This should be solved with a special hdmi sink device or | |
1044 | * similar so that power domains can be employed. | |
1045 | */ | |
1046 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
1047 | return 0; | |
112b715e | 1048 | |
ab3be73f ID |
1049 | return i915_drm_suspend_late(drm_dev, false); |
1050 | } | |
1051 | ||
1052 | static int i915_pm_poweroff_late(struct device *dev) | |
1053 | { | |
1054 | struct drm_device *drm_dev = dev_to_i915(dev)->dev; | |
1055 | ||
1056 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
1057 | return 0; | |
1058 | ||
1059 | return i915_drm_suspend_late(drm_dev, true); | |
cbda12d7 ZW |
1060 | } |
1061 | ||
76c4b250 ID |
1062 | static int i915_pm_resume_early(struct device *dev) |
1063 | { | |
888d0d42 | 1064 | struct drm_device *drm_dev = dev_to_i915(dev)->dev; |
76c4b250 | 1065 | |
097dd837 ID |
1066 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
1067 | return 0; | |
1068 | ||
5e365c39 | 1069 | return i915_drm_resume_early(drm_dev); |
76c4b250 ID |
1070 | } |
1071 | ||
84b79f8d | 1072 | static int i915_pm_resume(struct device *dev) |
cbda12d7 | 1073 | { |
888d0d42 | 1074 | struct drm_device *drm_dev = dev_to_i915(dev)->dev; |
84b79f8d | 1075 | |
097dd837 ID |
1076 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
1077 | return 0; | |
1078 | ||
5a17514e | 1079 | return i915_drm_resume(drm_dev); |
cbda12d7 ZW |
1080 | } |
1081 | ||
ebc32824 | 1082 | static int hsw_suspend_complete(struct drm_i915_private *dev_priv) |
97bea207 | 1083 | { |
414de7a0 | 1084 | hsw_enable_pc8(dev_priv); |
0ab9cfeb ID |
1085 | |
1086 | return 0; | |
97bea207 PZ |
1087 | } |
1088 | ||
31335cec SS |
1089 | static int bxt_suspend_complete(struct drm_i915_private *dev_priv) |
1090 | { | |
1091 | struct drm_device *dev = dev_priv->dev; | |
1092 | ||
1093 | /* TODO: when DC5 support is added disable DC5 here. */ | |
1094 | ||
1095 | broxton_ddi_phy_uninit(dev); | |
1096 | broxton_uninit_cdclk(dev); | |
1097 | bxt_enable_dc9(dev_priv); | |
1098 | ||
1099 | return 0; | |
1100 | } | |
1101 | ||
1102 | static int bxt_resume_prepare(struct drm_i915_private *dev_priv) | |
1103 | { | |
1104 | struct drm_device *dev = dev_priv->dev; | |
1105 | ||
1106 | /* TODO: when CSR FW support is added make sure the FW is loaded */ | |
1107 | ||
1108 | bxt_disable_dc9(dev_priv); | |
1109 | ||
1110 | /* | |
1111 | * TODO: when DC5 support is added enable DC5 here if the CSR FW | |
1112 | * is available. | |
1113 | */ | |
1114 | broxton_init_cdclk(dev); | |
1115 | broxton_ddi_phy_init(dev); | |
31335cec SS |
1116 | |
1117 | return 0; | |
1118 | } | |
1119 | ||
ddeea5b0 ID |
1120 | /* |
1121 | * Save all Gunit registers that may be lost after a D3 and a subsequent | |
1122 | * S0i[R123] transition. The list of registers needing a save/restore is | |
1123 | * defined in the VLV2_S0IXRegs document. This documents marks all Gunit | |
1124 | * registers in the following way: | |
1125 | * - Driver: saved/restored by the driver | |
1126 | * - Punit : saved/restored by the Punit firmware | |
1127 | * - No, w/o marking: no need to save/restore, since the register is R/O or | |
1128 | * used internally by the HW in a way that doesn't depend | |
1129 | * keeping the content across a suspend/resume. | |
1130 | * - Debug : used for debugging | |
1131 | * | |
1132 | * We save/restore all registers marked with 'Driver', with the following | |
1133 | * exceptions: | |
1134 | * - Registers out of use, including also registers marked with 'Debug'. | |
1135 | * These have no effect on the driver's operation, so we don't save/restore | |
1136 | * them to reduce the overhead. | |
1137 | * - Registers that are fully setup by an initialization function called from | |
1138 | * the resume path. For example many clock gating and RPS/RC6 registers. | |
1139 | * - Registers that provide the right functionality with their reset defaults. | |
1140 | * | |
1141 | * TODO: Except for registers that based on the above 3 criteria can be safely | |
1142 | * ignored, we save/restore all others, practically treating the HW context as | |
1143 | * a black-box for the driver. Further investigation is needed to reduce the | |
1144 | * saved/restored registers even further, by following the same 3 criteria. | |
1145 | */ | |
1146 | static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv) | |
1147 | { | |
1148 | struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; | |
1149 | int i; | |
1150 | ||
1151 | /* GAM 0x4000-0x4770 */ | |
1152 | s->wr_watermark = I915_READ(GEN7_WR_WATERMARK); | |
1153 | s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL); | |
1154 | s->arb_mode = I915_READ(ARB_MODE); | |
1155 | s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0); | |
1156 | s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1); | |
1157 | ||
1158 | for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) | |
22dfe79f | 1159 | s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i)); |
ddeea5b0 ID |
1160 | |
1161 | s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); | |
b5f1c97f | 1162 | s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT); |
ddeea5b0 ID |
1163 | |
1164 | s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7); | |
1165 | s->ecochk = I915_READ(GAM_ECOCHK); | |
1166 | s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7); | |
1167 | s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7); | |
1168 | ||
1169 | s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR); | |
1170 | ||
1171 | /* MBC 0x9024-0x91D0, 0x8500 */ | |
1172 | s->g3dctl = I915_READ(VLV_G3DCTL); | |
1173 | s->gsckgctl = I915_READ(VLV_GSCKGCTL); | |
1174 | s->mbctl = I915_READ(GEN6_MBCTL); | |
1175 | ||
1176 | /* GCP 0x9400-0x9424, 0x8100-0x810C */ | |
1177 | s->ucgctl1 = I915_READ(GEN6_UCGCTL1); | |
1178 | s->ucgctl3 = I915_READ(GEN6_UCGCTL3); | |
1179 | s->rcgctl1 = I915_READ(GEN6_RCGCTL1); | |
1180 | s->rcgctl2 = I915_READ(GEN6_RCGCTL2); | |
1181 | s->rstctl = I915_READ(GEN6_RSTCTL); | |
1182 | s->misccpctl = I915_READ(GEN7_MISCCPCTL); | |
1183 | ||
1184 | /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ | |
1185 | s->gfxpause = I915_READ(GEN6_GFXPAUSE); | |
1186 | s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC); | |
1187 | s->rpdeuc = I915_READ(GEN6_RPDEUC); | |
1188 | s->ecobus = I915_READ(ECOBUS); | |
1189 | s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL); | |
1190 | s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT); | |
1191 | s->rp_deucsw = I915_READ(GEN6_RPDEUCSW); | |
1192 | s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR); | |
1193 | s->rcedata = I915_READ(VLV_RCEDATA); | |
1194 | s->spare2gh = I915_READ(VLV_SPAREG2H); | |
1195 | ||
1196 | /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ | |
1197 | s->gt_imr = I915_READ(GTIMR); | |
1198 | s->gt_ier = I915_READ(GTIER); | |
1199 | s->pm_imr = I915_READ(GEN6_PMIMR); | |
1200 | s->pm_ier = I915_READ(GEN6_PMIER); | |
1201 | ||
1202 | for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) | |
22dfe79f | 1203 | s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i)); |
ddeea5b0 ID |
1204 | |
1205 | /* GT SA CZ domain, 0x100000-0x138124 */ | |
1206 | s->tilectl = I915_READ(TILECTL); | |
1207 | s->gt_fifoctl = I915_READ(GTFIFOCTL); | |
1208 | s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL); | |
1209 | s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1210 | s->pmwgicz = I915_READ(VLV_PMWGICZ); | |
1211 | ||
1212 | /* Gunit-Display CZ domain, 0x182028-0x1821CF */ | |
1213 | s->gu_ctl0 = I915_READ(VLV_GU_CTL0); | |
1214 | s->gu_ctl1 = I915_READ(VLV_GU_CTL1); | |
9c25210f | 1215 | s->pcbr = I915_READ(VLV_PCBR); |
ddeea5b0 ID |
1216 | s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2); |
1217 | ||
1218 | /* | |
1219 | * Not saving any of: | |
1220 | * DFT, 0x9800-0x9EC0 | |
1221 | * SARB, 0xB000-0xB1FC | |
1222 | * GAC, 0x5208-0x524C, 0x14000-0x14C000 | |
1223 | * PCI CFG | |
1224 | */ | |
1225 | } | |
1226 | ||
1227 | static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv) | |
1228 | { | |
1229 | struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; | |
1230 | u32 val; | |
1231 | int i; | |
1232 | ||
1233 | /* GAM 0x4000-0x4770 */ | |
1234 | I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark); | |
1235 | I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl); | |
1236 | I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16)); | |
1237 | I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0); | |
1238 | I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1); | |
1239 | ||
1240 | for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) | |
22dfe79f | 1241 | I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]); |
ddeea5b0 ID |
1242 | |
1243 | I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count); | |
b5f1c97f | 1244 | I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count); |
ddeea5b0 ID |
1245 | |
1246 | I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp); | |
1247 | I915_WRITE(GAM_ECOCHK, s->ecochk); | |
1248 | I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp); | |
1249 | I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp); | |
1250 | ||
1251 | I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr); | |
1252 | ||
1253 | /* MBC 0x9024-0x91D0, 0x8500 */ | |
1254 | I915_WRITE(VLV_G3DCTL, s->g3dctl); | |
1255 | I915_WRITE(VLV_GSCKGCTL, s->gsckgctl); | |
1256 | I915_WRITE(GEN6_MBCTL, s->mbctl); | |
1257 | ||
1258 | /* GCP 0x9400-0x9424, 0x8100-0x810C */ | |
1259 | I915_WRITE(GEN6_UCGCTL1, s->ucgctl1); | |
1260 | I915_WRITE(GEN6_UCGCTL3, s->ucgctl3); | |
1261 | I915_WRITE(GEN6_RCGCTL1, s->rcgctl1); | |
1262 | I915_WRITE(GEN6_RCGCTL2, s->rcgctl2); | |
1263 | I915_WRITE(GEN6_RSTCTL, s->rstctl); | |
1264 | I915_WRITE(GEN7_MISCCPCTL, s->misccpctl); | |
1265 | ||
1266 | /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ | |
1267 | I915_WRITE(GEN6_GFXPAUSE, s->gfxpause); | |
1268 | I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc); | |
1269 | I915_WRITE(GEN6_RPDEUC, s->rpdeuc); | |
1270 | I915_WRITE(ECOBUS, s->ecobus); | |
1271 | I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl); | |
1272 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout); | |
1273 | I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw); | |
1274 | I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr); | |
1275 | I915_WRITE(VLV_RCEDATA, s->rcedata); | |
1276 | I915_WRITE(VLV_SPAREG2H, s->spare2gh); | |
1277 | ||
1278 | /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ | |
1279 | I915_WRITE(GTIMR, s->gt_imr); | |
1280 | I915_WRITE(GTIER, s->gt_ier); | |
1281 | I915_WRITE(GEN6_PMIMR, s->pm_imr); | |
1282 | I915_WRITE(GEN6_PMIER, s->pm_ier); | |
1283 | ||
1284 | for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) | |
22dfe79f | 1285 | I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]); |
ddeea5b0 ID |
1286 | |
1287 | /* GT SA CZ domain, 0x100000-0x138124 */ | |
1288 | I915_WRITE(TILECTL, s->tilectl); | |
1289 | I915_WRITE(GTFIFOCTL, s->gt_fifoctl); | |
1290 | /* | |
1291 | * Preserve the GT allow wake and GFX force clock bit, they are not | |
1292 | * be restored, as they are used to control the s0ix suspend/resume | |
1293 | * sequence by the caller. | |
1294 | */ | |
1295 | val = I915_READ(VLV_GTLC_WAKE_CTRL); | |
1296 | val &= VLV_GTLC_ALLOWWAKEREQ; | |
1297 | val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ; | |
1298 | I915_WRITE(VLV_GTLC_WAKE_CTRL, val); | |
1299 | ||
1300 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1301 | val &= VLV_GFX_CLK_FORCE_ON_BIT; | |
1302 | val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT; | |
1303 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); | |
1304 | ||
1305 | I915_WRITE(VLV_PMWGICZ, s->pmwgicz); | |
1306 | ||
1307 | /* Gunit-Display CZ domain, 0x182028-0x1821CF */ | |
1308 | I915_WRITE(VLV_GU_CTL0, s->gu_ctl0); | |
1309 | I915_WRITE(VLV_GU_CTL1, s->gu_ctl1); | |
9c25210f | 1310 | I915_WRITE(VLV_PCBR, s->pcbr); |
ddeea5b0 ID |
1311 | I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2); |
1312 | } | |
1313 | ||
650ad970 ID |
1314 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on) |
1315 | { | |
1316 | u32 val; | |
1317 | int err; | |
1318 | ||
650ad970 | 1319 | #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT) |
650ad970 ID |
1320 | |
1321 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1322 | val &= ~VLV_GFX_CLK_FORCE_ON_BIT; | |
1323 | if (force_on) | |
1324 | val |= VLV_GFX_CLK_FORCE_ON_BIT; | |
1325 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); | |
1326 | ||
1327 | if (!force_on) | |
1328 | return 0; | |
1329 | ||
8d4eee9c | 1330 | err = wait_for(COND, 20); |
650ad970 ID |
1331 | if (err) |
1332 | DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n", | |
1333 | I915_READ(VLV_GTLC_SURVIVABILITY_REG)); | |
1334 | ||
1335 | return err; | |
1336 | #undef COND | |
1337 | } | |
1338 | ||
ddeea5b0 ID |
1339 | static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow) |
1340 | { | |
1341 | u32 val; | |
1342 | int err = 0; | |
1343 | ||
1344 | val = I915_READ(VLV_GTLC_WAKE_CTRL); | |
1345 | val &= ~VLV_GTLC_ALLOWWAKEREQ; | |
1346 | if (allow) | |
1347 | val |= VLV_GTLC_ALLOWWAKEREQ; | |
1348 | I915_WRITE(VLV_GTLC_WAKE_CTRL, val); | |
1349 | POSTING_READ(VLV_GTLC_WAKE_CTRL); | |
1350 | ||
1351 | #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \ | |
1352 | allow) | |
1353 | err = wait_for(COND, 1); | |
1354 | if (err) | |
1355 | DRM_ERROR("timeout disabling GT waking\n"); | |
1356 | return err; | |
1357 | #undef COND | |
1358 | } | |
1359 | ||
1360 | static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv, | |
1361 | bool wait_for_on) | |
1362 | { | |
1363 | u32 mask; | |
1364 | u32 val; | |
1365 | int err; | |
1366 | ||
1367 | mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK; | |
1368 | val = wait_for_on ? mask : 0; | |
1369 | #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val) | |
1370 | if (COND) | |
1371 | return 0; | |
1372 | ||
1373 | DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n", | |
87ad3212 JN |
1374 | onoff(wait_for_on), |
1375 | I915_READ(VLV_GTLC_PW_STATUS)); | |
ddeea5b0 ID |
1376 | |
1377 | /* | |
1378 | * RC6 transitioning can be delayed up to 2 msec (see | |
1379 | * valleyview_enable_rps), use 3 msec for safety. | |
1380 | */ | |
1381 | err = wait_for(COND, 3); | |
1382 | if (err) | |
1383 | DRM_ERROR("timeout waiting for GT wells to go %s\n", | |
87ad3212 | 1384 | onoff(wait_for_on)); |
ddeea5b0 ID |
1385 | |
1386 | return err; | |
1387 | #undef COND | |
1388 | } | |
1389 | ||
1390 | static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv) | |
1391 | { | |
1392 | if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR)) | |
1393 | return; | |
1394 | ||
6fa283b0 | 1395 | DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n"); |
ddeea5b0 ID |
1396 | I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR); |
1397 | } | |
1398 | ||
ebc32824 | 1399 | static int vlv_suspend_complete(struct drm_i915_private *dev_priv) |
ddeea5b0 ID |
1400 | { |
1401 | u32 mask; | |
1402 | int err; | |
1403 | ||
1404 | /* | |
1405 | * Bspec defines the following GT well on flags as debug only, so | |
1406 | * don't treat them as hard failures. | |
1407 | */ | |
1408 | (void)vlv_wait_for_gt_wells(dev_priv, false); | |
1409 | ||
1410 | mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS; | |
1411 | WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask); | |
1412 | ||
1413 | vlv_check_no_gt_access(dev_priv); | |
1414 | ||
1415 | err = vlv_force_gfx_clock(dev_priv, true); | |
1416 | if (err) | |
1417 | goto err1; | |
1418 | ||
1419 | err = vlv_allow_gt_wake(dev_priv, false); | |
1420 | if (err) | |
1421 | goto err2; | |
98711167 D |
1422 | |
1423 | if (!IS_CHERRYVIEW(dev_priv->dev)) | |
1424 | vlv_save_gunit_s0ix_state(dev_priv); | |
ddeea5b0 ID |
1425 | |
1426 | err = vlv_force_gfx_clock(dev_priv, false); | |
1427 | if (err) | |
1428 | goto err2; | |
1429 | ||
1430 | return 0; | |
1431 | ||
1432 | err2: | |
1433 | /* For safety always re-enable waking and disable gfx clock forcing */ | |
1434 | vlv_allow_gt_wake(dev_priv, true); | |
1435 | err1: | |
1436 | vlv_force_gfx_clock(dev_priv, false); | |
1437 | ||
1438 | return err; | |
1439 | } | |
1440 | ||
016970be SK |
1441 | static int vlv_resume_prepare(struct drm_i915_private *dev_priv, |
1442 | bool rpm_resume) | |
ddeea5b0 ID |
1443 | { |
1444 | struct drm_device *dev = dev_priv->dev; | |
1445 | int err; | |
1446 | int ret; | |
1447 | ||
1448 | /* | |
1449 | * If any of the steps fail just try to continue, that's the best we | |
1450 | * can do at this point. Return the first error code (which will also | |
1451 | * leave RPM permanently disabled). | |
1452 | */ | |
1453 | ret = vlv_force_gfx_clock(dev_priv, true); | |
1454 | ||
98711167 D |
1455 | if (!IS_CHERRYVIEW(dev_priv->dev)) |
1456 | vlv_restore_gunit_s0ix_state(dev_priv); | |
ddeea5b0 ID |
1457 | |
1458 | err = vlv_allow_gt_wake(dev_priv, true); | |
1459 | if (!ret) | |
1460 | ret = err; | |
1461 | ||
1462 | err = vlv_force_gfx_clock(dev_priv, false); | |
1463 | if (!ret) | |
1464 | ret = err; | |
1465 | ||
1466 | vlv_check_no_gt_access(dev_priv); | |
1467 | ||
016970be SK |
1468 | if (rpm_resume) { |
1469 | intel_init_clock_gating(dev); | |
1470 | i915_gem_restore_fences(dev); | |
1471 | } | |
ddeea5b0 ID |
1472 | |
1473 | return ret; | |
1474 | } | |
1475 | ||
97bea207 | 1476 | static int intel_runtime_suspend(struct device *device) |
8a187455 PZ |
1477 | { |
1478 | struct pci_dev *pdev = to_pci_dev(device); | |
1479 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1480 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0ab9cfeb | 1481 | int ret; |
8a187455 | 1482 | |
aeab0b5a | 1483 | if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev)))) |
c6df39b5 ID |
1484 | return -ENODEV; |
1485 | ||
604effb7 ID |
1486 | if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev))) |
1487 | return -ENODEV; | |
1488 | ||
8a187455 PZ |
1489 | DRM_DEBUG_KMS("Suspending device\n"); |
1490 | ||
d6102977 ID |
1491 | /* |
1492 | * We could deadlock here in case another thread holding struct_mutex | |
1493 | * calls RPM suspend concurrently, since the RPM suspend will wait | |
1494 | * first for this RPM suspend to finish. In this case the concurrent | |
1495 | * RPM resume will be followed by its RPM suspend counterpart. Still | |
1496 | * for consistency return -EAGAIN, which will reschedule this suspend. | |
1497 | */ | |
1498 | if (!mutex_trylock(&dev->struct_mutex)) { | |
1499 | DRM_DEBUG_KMS("device lock contention, deffering suspend\n"); | |
1500 | /* | |
1501 | * Bump the expiration timestamp, otherwise the suspend won't | |
1502 | * be rescheduled. | |
1503 | */ | |
1504 | pm_runtime_mark_last_busy(device); | |
1505 | ||
1506 | return -EAGAIN; | |
1507 | } | |
1f814dac ID |
1508 | |
1509 | disable_rpm_wakeref_asserts(dev_priv); | |
1510 | ||
d6102977 ID |
1511 | /* |
1512 | * We are safe here against re-faults, since the fault handler takes | |
1513 | * an RPM reference. | |
1514 | */ | |
1515 | i915_gem_release_all_mmaps(dev_priv); | |
1516 | mutex_unlock(&dev->struct_mutex); | |
1517 | ||
825f2728 JL |
1518 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
1519 | ||
a1c41994 AD |
1520 | intel_guc_suspend(dev); |
1521 | ||
fac6adb0 | 1522 | intel_suspend_gt_powersave(dev); |
2eb5252e | 1523 | intel_runtime_pm_disable_interrupts(dev_priv); |
b5478bcd | 1524 | |
ebc32824 | 1525 | ret = intel_suspend_complete(dev_priv); |
0ab9cfeb ID |
1526 | if (ret) { |
1527 | DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret); | |
b963291c | 1528 | intel_runtime_pm_enable_interrupts(dev_priv); |
0ab9cfeb | 1529 | |
1f814dac ID |
1530 | enable_rpm_wakeref_asserts(dev_priv); |
1531 | ||
0ab9cfeb ID |
1532 | return ret; |
1533 | } | |
a8a8bd54 | 1534 | |
dc9fb09c | 1535 | intel_uncore_forcewake_reset(dev, false); |
1f814dac ID |
1536 | |
1537 | enable_rpm_wakeref_asserts(dev_priv); | |
1538 | WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count)); | |
55ec45c2 | 1539 | |
bc3b9346 | 1540 | if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv)) |
55ec45c2 MK |
1541 | DRM_ERROR("Unclaimed access detected prior to suspending\n"); |
1542 | ||
8a187455 | 1543 | dev_priv->pm.suspended = true; |
1fb2362b KCA |
1544 | |
1545 | /* | |
c8a0bd42 PZ |
1546 | * FIXME: We really should find a document that references the arguments |
1547 | * used below! | |
1fb2362b | 1548 | */ |
d37ae19a PZ |
1549 | if (IS_BROADWELL(dev)) { |
1550 | /* | |
1551 | * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop | |
1552 | * being detected, and the call we do at intel_runtime_resume() | |
1553 | * won't be able to restore them. Since PCI_D3hot matches the | |
1554 | * actual specification and appears to be working, use it. | |
1555 | */ | |
1556 | intel_opregion_notify_adapter(dev, PCI_D3hot); | |
1557 | } else { | |
c8a0bd42 PZ |
1558 | /* |
1559 | * current versions of firmware which depend on this opregion | |
1560 | * notification have repurposed the D1 definition to mean | |
1561 | * "runtime suspended" vs. what you would normally expect (D3) | |
1562 | * to distinguish it from notifications that might be sent via | |
1563 | * the suspend path. | |
1564 | */ | |
1565 | intel_opregion_notify_adapter(dev, PCI_D1); | |
c8a0bd42 | 1566 | } |
8a187455 | 1567 | |
59bad947 | 1568 | assert_forcewakes_inactive(dev_priv); |
dc9fb09c | 1569 | |
a8a8bd54 | 1570 | DRM_DEBUG_KMS("Device suspended\n"); |
8a187455 PZ |
1571 | return 0; |
1572 | } | |
1573 | ||
97bea207 | 1574 | static int intel_runtime_resume(struct device *device) |
8a187455 PZ |
1575 | { |
1576 | struct pci_dev *pdev = to_pci_dev(device); | |
1577 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1578 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1a5df187 | 1579 | int ret = 0; |
8a187455 | 1580 | |
604effb7 ID |
1581 | if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev))) |
1582 | return -ENODEV; | |
8a187455 PZ |
1583 | |
1584 | DRM_DEBUG_KMS("Resuming device\n"); | |
1585 | ||
1f814dac ID |
1586 | WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count)); |
1587 | disable_rpm_wakeref_asserts(dev_priv); | |
1588 | ||
cd2e9e90 | 1589 | intel_opregion_notify_adapter(dev, PCI_D0); |
8a187455 | 1590 | dev_priv->pm.suspended = false; |
55ec45c2 MK |
1591 | if (intel_uncore_unclaimed_mmio(dev_priv)) |
1592 | DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n"); | |
8a187455 | 1593 | |
a1c41994 AD |
1594 | intel_guc_resume(dev); |
1595 | ||
1a5df187 PZ |
1596 | if (IS_GEN6(dev_priv)) |
1597 | intel_init_pch_refclk(dev); | |
31335cec SS |
1598 | |
1599 | if (IS_BROXTON(dev)) | |
1600 | ret = bxt_resume_prepare(dev_priv); | |
1a5df187 PZ |
1601 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
1602 | hsw_disable_pc8(dev_priv); | |
666a4537 | 1603 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
1a5df187 PZ |
1604 | ret = vlv_resume_prepare(dev_priv, true); |
1605 | ||
0ab9cfeb ID |
1606 | /* |
1607 | * No point of rolling back things in case of an error, as the best | |
1608 | * we can do is to hope that things will still work (and disable RPM). | |
1609 | */ | |
92b806d3 ID |
1610 | i915_gem_init_swizzling(dev); |
1611 | gen6_update_ring_freq(dev); | |
1612 | ||
b963291c | 1613 | intel_runtime_pm_enable_interrupts(dev_priv); |
08d8a232 VS |
1614 | |
1615 | /* | |
1616 | * On VLV/CHV display interrupts are part of the display | |
1617 | * power well, so hpd is reinitialized from there. For | |
1618 | * everyone else do it here. | |
1619 | */ | |
666a4537 | 1620 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) |
08d8a232 VS |
1621 | intel_hpd_init(dev_priv); |
1622 | ||
fac6adb0 | 1623 | intel_enable_gt_powersave(dev); |
b5478bcd | 1624 | |
1f814dac ID |
1625 | enable_rpm_wakeref_asserts(dev_priv); |
1626 | ||
0ab9cfeb ID |
1627 | if (ret) |
1628 | DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret); | |
1629 | else | |
1630 | DRM_DEBUG_KMS("Device resumed\n"); | |
1631 | ||
1632 | return ret; | |
8a187455 PZ |
1633 | } |
1634 | ||
016970be SK |
1635 | /* |
1636 | * This function implements common functionality of runtime and system | |
1637 | * suspend sequence. | |
1638 | */ | |
ebc32824 SK |
1639 | static int intel_suspend_complete(struct drm_i915_private *dev_priv) |
1640 | { | |
ebc32824 SK |
1641 | int ret; |
1642 | ||
16e44e3e | 1643 | if (IS_BROXTON(dev_priv)) |
31335cec | 1644 | ret = bxt_suspend_complete(dev_priv); |
16e44e3e | 1645 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ebc32824 | 1646 | ret = hsw_suspend_complete(dev_priv); |
666a4537 | 1647 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
ebc32824 | 1648 | ret = vlv_suspend_complete(dev_priv); |
604effb7 ID |
1649 | else |
1650 | ret = 0; | |
ebc32824 SK |
1651 | |
1652 | return ret; | |
1653 | } | |
1654 | ||
b4b78d12 | 1655 | static const struct dev_pm_ops i915_pm_ops = { |
5545dbbf ID |
1656 | /* |
1657 | * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, | |
1658 | * PMSG_RESUME] | |
1659 | */ | |
0206e353 | 1660 | .suspend = i915_pm_suspend, |
76c4b250 ID |
1661 | .suspend_late = i915_pm_suspend_late, |
1662 | .resume_early = i915_pm_resume_early, | |
0206e353 | 1663 | .resume = i915_pm_resume, |
5545dbbf ID |
1664 | |
1665 | /* | |
1666 | * S4 event handlers | |
1667 | * @freeze, @freeze_late : called (1) before creating the | |
1668 | * hibernation image [PMSG_FREEZE] and | |
1669 | * (2) after rebooting, before restoring | |
1670 | * the image [PMSG_QUIESCE] | |
1671 | * @thaw, @thaw_early : called (1) after creating the hibernation | |
1672 | * image, before writing it [PMSG_THAW] | |
1673 | * and (2) after failing to create or | |
1674 | * restore the image [PMSG_RECOVER] | |
1675 | * @poweroff, @poweroff_late: called after writing the hibernation | |
1676 | * image, before rebooting [PMSG_HIBERNATE] | |
1677 | * @restore, @restore_early : called after rebooting and restoring the | |
1678 | * hibernation image [PMSG_RESTORE] | |
1679 | */ | |
36d61e67 ID |
1680 | .freeze = i915_pm_suspend, |
1681 | .freeze_late = i915_pm_suspend_late, | |
1682 | .thaw_early = i915_pm_resume_early, | |
1683 | .thaw = i915_pm_resume, | |
1684 | .poweroff = i915_pm_suspend, | |
ab3be73f | 1685 | .poweroff_late = i915_pm_poweroff_late, |
76c4b250 | 1686 | .restore_early = i915_pm_resume_early, |
0206e353 | 1687 | .restore = i915_pm_resume, |
5545dbbf ID |
1688 | |
1689 | /* S0ix (via runtime suspend) event handlers */ | |
97bea207 PZ |
1690 | .runtime_suspend = intel_runtime_suspend, |
1691 | .runtime_resume = intel_runtime_resume, | |
cbda12d7 ZW |
1692 | }; |
1693 | ||
78b68556 | 1694 | static const struct vm_operations_struct i915_gem_vm_ops = { |
de151cf6 | 1695 | .fault = i915_gem_fault, |
ab00b3e5 JB |
1696 | .open = drm_gem_vm_open, |
1697 | .close = drm_gem_vm_close, | |
de151cf6 JB |
1698 | }; |
1699 | ||
e08e96de AV |
1700 | static const struct file_operations i915_driver_fops = { |
1701 | .owner = THIS_MODULE, | |
1702 | .open = drm_open, | |
1703 | .release = drm_release, | |
1704 | .unlocked_ioctl = drm_ioctl, | |
1705 | .mmap = drm_gem_mmap, | |
1706 | .poll = drm_poll, | |
e08e96de AV |
1707 | .read = drm_read, |
1708 | #ifdef CONFIG_COMPAT | |
1709 | .compat_ioctl = i915_compat_ioctl, | |
1710 | #endif | |
1711 | .llseek = noop_llseek, | |
1712 | }; | |
1713 | ||
1da177e4 | 1714 | static struct drm_driver driver = { |
0c54781b MW |
1715 | /* Don't use MTRRs here; the Xserver or userspace app should |
1716 | * deal with them for Intel hardware. | |
792d2b9a | 1717 | */ |
673a394b | 1718 | .driver_features = |
10ba5012 | 1719 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME | |
1751fcf9 | 1720 | DRIVER_RENDER | DRIVER_MODESET, |
22eae947 | 1721 | .load = i915_driver_load, |
ba8bbcf6 | 1722 | .unload = i915_driver_unload, |
673a394b | 1723 | .open = i915_driver_open, |
22eae947 DA |
1724 | .lastclose = i915_driver_lastclose, |
1725 | .preclose = i915_driver_preclose, | |
673a394b | 1726 | .postclose = i915_driver_postclose, |
915b4d11 | 1727 | .set_busid = drm_pci_set_busid, |
d8e29209 | 1728 | |
955b12de | 1729 | #if defined(CONFIG_DEBUG_FS) |
27c202ad BG |
1730 | .debugfs_init = i915_debugfs_init, |
1731 | .debugfs_cleanup = i915_debugfs_cleanup, | |
955b12de | 1732 | #endif |
673a394b | 1733 | .gem_free_object = i915_gem_free_object, |
de151cf6 | 1734 | .gem_vm_ops = &i915_gem_vm_ops, |
1286ff73 DV |
1735 | |
1736 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
1737 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
1738 | .gem_prime_export = i915_gem_prime_export, | |
1739 | .gem_prime_import = i915_gem_prime_import, | |
1740 | ||
ff72145b | 1741 | .dumb_create = i915_gem_dumb_create, |
da6b51d0 | 1742 | .dumb_map_offset = i915_gem_mmap_gtt, |
43387b37 | 1743 | .dumb_destroy = drm_gem_dumb_destroy, |
1da177e4 | 1744 | .ioctls = i915_ioctls, |
e08e96de | 1745 | .fops = &i915_driver_fops, |
22eae947 DA |
1746 | .name = DRIVER_NAME, |
1747 | .desc = DRIVER_DESC, | |
1748 | .date = DRIVER_DATE, | |
1749 | .major = DRIVER_MAJOR, | |
1750 | .minor = DRIVER_MINOR, | |
1751 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 LT |
1752 | }; |
1753 | ||
8410ea3b DA |
1754 | static struct pci_driver i915_pci_driver = { |
1755 | .name = DRIVER_NAME, | |
1756 | .id_table = pciidlist, | |
1757 | .probe = i915_pci_probe, | |
1758 | .remove = i915_pci_remove, | |
1759 | .driver.pm = &i915_pm_ops, | |
1760 | }; | |
1761 | ||
1da177e4 LT |
1762 | static int __init i915_init(void) |
1763 | { | |
1764 | driver.num_ioctls = i915_max_ioctl; | |
79e53945 JB |
1765 | |
1766 | /* | |
fd930478 CW |
1767 | * Enable KMS by default, unless explicitly overriden by |
1768 | * either the i915.modeset prarameter or by the | |
1769 | * vga_text_mode_force boot option. | |
79e53945 | 1770 | */ |
fd930478 CW |
1771 | |
1772 | if (i915.modeset == 0) | |
1773 | driver.driver_features &= ~DRIVER_MODESET; | |
79e53945 JB |
1774 | |
1775 | #ifdef CONFIG_VGA_CONSOLE | |
d330a953 | 1776 | if (vgacon_text_force() && i915.modeset == -1) |
79e53945 JB |
1777 | driver.driver_features &= ~DRIVER_MODESET; |
1778 | #endif | |
1779 | ||
b30324ad | 1780 | if (!(driver.driver_features & DRIVER_MODESET)) { |
b30324ad | 1781 | /* Silently fail loading to not upset userspace. */ |
c9cd7b65 | 1782 | DRM_DEBUG_DRIVER("KMS and UMS disabled.\n"); |
b30324ad | 1783 | return 0; |
b30324ad | 1784 | } |
3885c6bb | 1785 | |
c5b852f3 | 1786 | if (i915.nuclear_pageflip) |
b2e7723b MR |
1787 | driver.driver_features |= DRIVER_ATOMIC; |
1788 | ||
8410ea3b | 1789 | return drm_pci_init(&driver, &i915_pci_driver); |
1da177e4 LT |
1790 | } |
1791 | ||
1792 | static void __exit i915_exit(void) | |
1793 | { | |
b33ecdd1 DV |
1794 | if (!(driver.driver_features & DRIVER_MODESET)) |
1795 | return; /* Never loaded a driver. */ | |
b33ecdd1 | 1796 | |
8410ea3b | 1797 | drm_pci_exit(&driver, &i915_pci_driver); |
1da177e4 LT |
1798 | } |
1799 | ||
1800 | module_init(i915_init); | |
1801 | module_exit(i915_exit); | |
1802 | ||
0a6d1631 | 1803 | MODULE_AUTHOR("Tungsten Graphics, Inc."); |
1eab9234 | 1804 | MODULE_AUTHOR("Intel Corporation"); |
0a6d1631 | 1805 | |
b5e89ed5 | 1806 | MODULE_DESCRIPTION(DRIVER_DESC); |
1da177e4 | 1807 | MODULE_LICENSE("GPL and additional rights"); |