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Linux 4.16-rc1
[linux-2.6-block.git] / drivers / gpu / drm / i915 / i915_drv.c
CommitLineData
1da177e4
LT		 1/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
0d6aa60b 3/*
bc54fd1a 4 *
1da177e4
LT		 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
bc54fd1a
DA		 7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
0d6aa60b 28 */
1da177e4 29
e5747e3a 30#include <linux/acpi.h>
0673ad47
CW		 31#include <linux/device.h>
32#include <linux/oom.h>
e0cd3608 33#include <linux/module.h>
0673ad47
CW		 34#include <linux/pci.h>
35#include <linux/pm.h>
d6102977 36#include <linux/pm_runtime.h>
0673ad47
CW		 37#include <linux/pnp.h>
38#include <linux/slab.h>
39#include <linux/vgaarb.h>
704ab614 40#include <linux/vga_switcheroo.h>
0673ad47
CW		 41#include <linux/vt.h>
42#include <acpi/video.h>
43
44#include <drm/drmP.h>
760285e7 45#include <drm/drm_crtc_helper.h>
a667fb40 46#include <drm/drm_atomic_helper.h>
0673ad47
CW		 47#include <drm/i915_drm.h>
48
49#include "i915_drv.h"
50#include "i915_trace.h"
b46a33e2 51#include "i915_pmu.h"
0673ad47
CW		 52#include "i915_vgpu.h"
53#include "intel_drv.h"
5464cd65 54#include "intel_uc.h"
79e53945 55
112b715e
KH		 56static struct drm_driver driver;
57
0673ad47
CW		 58static unsigned int i915_load_fail_count;
59
60bool __i915_inject_load_failure(const char *func, int line)
61{
4f044a88 62 if (i915_load_fail_count >= i915_modparams.inject_load_failure)
0673ad47
CW		 63 return false;
64
4f044a88 65 if (++i915_load_fail_count == i915_modparams.inject_load_failure) {
0673ad47 66 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
4f044a88 67 i915_modparams.inject_load_failure, func, line);
0673ad47
CW		 68 return true;
69 }
70
71 return false;
72}
73
74#define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
75#define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
76 "providing the dmesg log by booting with drm.debug=0xf"
77
78void
79__i915_printk(struct drm_i915_private *dev_priv, const char *level,
80 const char *fmt, ...)
81{
82 static bool shown_bug_once;
c49d13ee 83 struct device *kdev = dev_priv->drm.dev;
0673ad47
CW		 84 bool is_error = level[1] <= KERN_ERR[1];
85 bool is_debug = level[1] == KERN_DEBUG[1];
86 struct va_format vaf;
87 va_list args;
88
89 if (is_debug && !(drm_debug & DRM_UT_DRIVER))
90 return;
91
92 va_start(args, fmt);
93
94 vaf.fmt = fmt;
95 vaf.va = &args;
96
c49d13ee 97 dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
0673ad47
CW		 98 __builtin_return_address(0), &vaf);
99
100 if (is_error && !shown_bug_once) {
c49d13ee 101 dev_notice(kdev, "%s", FDO_BUG_MSG);
0673ad47
CW		 102 shown_bug_once = true;
103 }
104
105 va_end(args);
106}
107
108static bool i915_error_injected(struct drm_i915_private *dev_priv)
109{
4f044a88
MW		 110 return i915_modparams.inject_load_failure &&
111 i915_load_fail_count == i915_modparams.inject_load_failure;
0673ad47
CW		 112}
113
114#define i915_load_error(dev_priv, fmt, ...) \
115 __i915_printk(dev_priv, \
116 i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
117 fmt, ##__VA_ARGS__)
118
119
fd6b8f43 120static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
0673ad47
CW		 121{
122 enum intel_pch ret = PCH_NOP;
123
124 /*
125 * In a virtualized passthrough environment we can be in a
126 * setup where the ISA bridge is not able to be passed through.
127 * In this case, a south bridge can be emulated and we have to
128 * make an educated guess as to which PCH is really there.
129 */
130
fd6b8f43 131 if (IS_GEN5(dev_priv)) {
0673ad47
CW		 132 ret = PCH_IBX;
133 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
fd6b8f43 134 } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
0673ad47 135 ret = PCH_CPT;
aa032130 136 DRM_DEBUG_KMS("Assuming CougarPoint PCH\n");
fd6b8f43 137 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
0673ad47 138 ret = PCH_LPT;
817aef5d
XZ		 139 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
140 dev_priv->pch_id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
141 else
142 dev_priv->pch_id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
0673ad47 143 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
fd6b8f43 144 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
0673ad47
CW		 145 ret = PCH_SPT;
146 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
80937819 147 } else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
acf1dba6 148 ret = PCH_CNP;
80937819 149 DRM_DEBUG_KMS("Assuming CannonPoint PCH\n");
0673ad47
CW		 150 }
151
152 return ret;
153}
154
da5f53bf 155static void intel_detect_pch(struct drm_i915_private *dev_priv)
0673ad47 156{
0673ad47
CW		 157 struct pci_dev *pch = NULL;
158
159 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
160 * (which really amounts to a PCH but no South Display).
161 */
b7f05d4a 162 if (INTEL_INFO(dev_priv)->num_pipes == 0) {
0673ad47
CW		 163 dev_priv->pch_type = PCH_NOP;
164 return;
165 }
166
167 /*
168 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
169 * make graphics device passthrough work easy for VMM, that only
170 * need to expose ISA bridge to let driver know the real hardware
171 * underneath. This is a requirement from virtualization team.
172 *
173 * In some virtualized environments (e.g. XEN), there is irrelevant
174 * ISA bridge in the system. To work reliably, we should scan trhough
175 * all the ISA bridge devices and check for the first match, instead
176 * of only checking the first one.
177 */
178 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
179 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
180 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
c5e855d0
VS		 181
182 dev_priv->pch_id = id;
ec7e0bb3 183
0673ad47
CW		 184 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
185 dev_priv->pch_type = PCH_IBX;
186 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
5db94019 187 WARN_ON(!IS_GEN5(dev_priv));
0673ad47
CW		 188 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
189 dev_priv->pch_type = PCH_CPT;
190 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
d4cdbf03
VS		 191 WARN_ON(!IS_GEN6(dev_priv) &&
192 !IS_IVYBRIDGE(dev_priv));
0673ad47
CW		 193 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
194 /* PantherPoint is CPT compatible */
195 dev_priv->pch_type = PCH_CPT;
196 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
d4cdbf03
VS		 197 WARN_ON(!IS_GEN6(dev_priv) &&
198 !IS_IVYBRIDGE(dev_priv));
0673ad47
CW		 199 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
200 dev_priv->pch_type = PCH_LPT;
201 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
8652744b
TU		 202 WARN_ON(!IS_HASWELL(dev_priv) &&
203 !IS_BROADWELL(dev_priv));
50a0bc90
TU		 204 WARN_ON(IS_HSW_ULT(dev_priv) ||
205 IS_BDW_ULT(dev_priv));
0673ad47
CW		 206 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
207 dev_priv->pch_type = PCH_LPT;
208 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
8652744b
TU		 209 WARN_ON(!IS_HASWELL(dev_priv) &&
210 !IS_BROADWELL(dev_priv));
50a0bc90
TU		 211 WARN_ON(!IS_HSW_ULT(dev_priv) &&
212 !IS_BDW_ULT(dev_priv));
c5e855d0
VS		 213 } else if (id == INTEL_PCH_WPT_DEVICE_ID_TYPE) {
214 /* WildcatPoint is LPT compatible */
215 dev_priv->pch_type = PCH_LPT;
216 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
217 WARN_ON(!IS_HASWELL(dev_priv) &&
218 !IS_BROADWELL(dev_priv));
219 WARN_ON(IS_HSW_ULT(dev_priv) ||
220 IS_BDW_ULT(dev_priv));
221 } else if (id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE) {
222 /* WildcatPoint is LPT compatible */
223 dev_priv->pch_type = PCH_LPT;
224 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
225 WARN_ON(!IS_HASWELL(dev_priv) &&
226 !IS_BROADWELL(dev_priv));
227 WARN_ON(!IS_HSW_ULT(dev_priv) &&
228 !IS_BDW_ULT(dev_priv));
0673ad47
CW		 229 } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
230 dev_priv->pch_type = PCH_SPT;
231 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
0853723b
TU		 232 WARN_ON(!IS_SKYLAKE(dev_priv) &&
233 !IS_KABYLAKE(dev_priv));
c5e855d0 234 } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
0673ad47
CW		 235 dev_priv->pch_type = PCH_SPT;
236 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
0853723b
TU		 237 WARN_ON(!IS_SKYLAKE(dev_priv) &&
238 !IS_KABYLAKE(dev_priv));
22dea0be
RV		 239 } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
240 dev_priv->pch_type = PCH_KBP;
23247d71 241 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
85327748 242 WARN_ON(!IS_SKYLAKE(dev_priv) &&
eb371933
RV		 243 !IS_KABYLAKE(dev_priv) &&
244 !IS_COFFEELAKE(dev_priv));
7b22b8c4
RV		 245 } else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
246 dev_priv->pch_type = PCH_CNP;
23247d71 247 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
80937819
RV		 248 WARN_ON(!IS_CANNONLAKE(dev_priv) &&
249 !IS_COFFEELAKE(dev_priv));
c5e855d0 250 } else if (id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
ec7e0bb3 251 dev_priv->pch_type = PCH_CNP;
23247d71 252 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
80937819
RV		 253 WARN_ON(!IS_CANNONLAKE(dev_priv) &&
254 !IS_COFFEELAKE(dev_priv));
d4cdbf03
VS		 255 } else if (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
256 id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
257 (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
0673ad47
CW		 258 pch->subsystem_vendor ==
259 PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
260 pch->subsystem_device ==
261 PCI_SUBDEVICE_ID_QEMU)) {
fd6b8f43
TU		 262 dev_priv->pch_type =
263 intel_virt_detect_pch(dev_priv);
0673ad47
CW		 264 } else
265 continue;
266
267 break;
268 }
269 }
270 if (!pch)
271 DRM_DEBUG_KMS("No PCH found.\n");
272
273 pci_dev_put(pch);
274}
275
0673ad47
CW		 276static int i915_getparam(struct drm_device *dev, void *data,
277 struct drm_file *file_priv)
278{
fac5e23e 279 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 280 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 281 drm_i915_getparam_t *param = data;
282 int value;
283
284 switch (param->param) {
285 case I915_PARAM_IRQ_ACTIVE:
286 case I915_PARAM_ALLOW_BATCHBUFFER:
287 case I915_PARAM_LAST_DISPATCH:
ef0f411f 288 case I915_PARAM_HAS_EXEC_CONSTANTS:
0673ad47
CW		 289 /* Reject all old ums/dri params. */
290 return -ENODEV;
291 case I915_PARAM_CHIPSET_ID:
52a05c30 292 value = pdev->device;
0673ad47
CW		 293 break;
294 case I915_PARAM_REVISION:
52a05c30 295 value = pdev->revision;
0673ad47 296 break;
0673ad47
CW		 297 case I915_PARAM_NUM_FENCES_AVAIL:
298 value = dev_priv->num_fence_regs;
299 break;
300 case I915_PARAM_HAS_OVERLAY:
301 value = dev_priv->overlay ? 1 : 0;
302 break;
0673ad47 303 case I915_PARAM_HAS_BSD:
3b3f1650 304 value = !!dev_priv->engine[VCS];
0673ad47
CW		 305 break;
306 case I915_PARAM_HAS_BLT:
3b3f1650 307 value = !!dev_priv->engine[BCS];
0673ad47
CW		 308 break;
309 case I915_PARAM_HAS_VEBOX:
3b3f1650 310 value = !!dev_priv->engine[VECS];
0673ad47
CW		 311 break;
312 case I915_PARAM_HAS_BSD2:
3b3f1650 313 value = !!dev_priv->engine[VCS2];
0673ad47 314 break;
0673ad47 315 case I915_PARAM_HAS_LLC:
16162470 316 value = HAS_LLC(dev_priv);
0673ad47
CW		 317 break;
318 case I915_PARAM_HAS_WT:
16162470 319 value = HAS_WT(dev_priv);
0673ad47
CW		 320 break;
321 case I915_PARAM_HAS_ALIASING_PPGTT:
16162470 322 value = USES_PPGTT(dev_priv);
0673ad47
CW		 323 break;
324 case I915_PARAM_HAS_SEMAPHORES:
93c6e966 325 value = HAS_LEGACY_SEMAPHORES(dev_priv);
0673ad47 326 break;
0673ad47
CW		 327 case I915_PARAM_HAS_SECURE_BATCHES:
328 value = capable(CAP_SYS_ADMIN);
329 break;
0673ad47
CW		 330 case I915_PARAM_CMD_PARSER_VERSION:
331 value = i915_cmd_parser_get_version(dev_priv);
332 break;
0673ad47 333 case I915_PARAM_SUBSLICE_TOTAL:
57ec171e 334 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
0673ad47
CW		 335 if (!value)
336 return -ENODEV;
337 break;
338 case I915_PARAM_EU_TOTAL:
43b67998 339 value = INTEL_INFO(dev_priv)->sseu.eu_total;
0673ad47
CW		 340 if (!value)
341 return -ENODEV;
342 break;
343 case I915_PARAM_HAS_GPU_RESET:
4f044a88
MW		 344 value = i915_modparams.enable_hangcheck &&
345 intel_has_gpu_reset(dev_priv);
142bc7d9
MT		 346 if (value && intel_has_reset_engine(dev_priv))
347 value = 2;
0673ad47
CW		 348 break;
349 case I915_PARAM_HAS_RESOURCE_STREAMER:
16162470 350 value = HAS_RESOURCE_STREAMER(dev_priv);
0673ad47 351 break;
37f501af 352 case I915_PARAM_HAS_POOLED_EU:
16162470 353 value = HAS_POOLED_EU(dev_priv);
37f501af 354 break;
355 case I915_PARAM_MIN_EU_IN_POOL:
43b67998 356 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
37f501af 357 break;
5464cd65 358 case I915_PARAM_HUC_STATUS:
3582ad13 359 intel_runtime_pm_get(dev_priv);
5464cd65 360 value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
3582ad13 361 intel_runtime_pm_put(dev_priv);
5464cd65 362 break;
4cc69075
CW		 363 case I915_PARAM_MMAP_GTT_VERSION:
364 /* Though we've started our numbering from 1, and so class all
365 * earlier versions as 0, in effect their value is undefined as
366 * the ioctl will report EINVAL for the unknown param!
367 */
368 value = i915_gem_mmap_gtt_version();
369 break;
0de9136d 370 case I915_PARAM_HAS_SCHEDULER:
bf64e0b0 371 value = 0;
beecec90 372 if (dev_priv->engine[RCS] && dev_priv->engine[RCS]->schedule) {
bf64e0b0 373 value |= I915_SCHEDULER_CAP_ENABLED;
ac14fbd4 374 value |= I915_SCHEDULER_CAP_PRIORITY;
fb5c551a 375 if (HAS_LOGICAL_RING_PREEMPTION(dev_priv))
beecec90
CW		 376 value |= I915_SCHEDULER_CAP_PREEMPTION;
377 }
0de9136d 378 break;
beecec90 379
16162470
DW		 380 case I915_PARAM_MMAP_VERSION:
381 /* Remember to bump this if the version changes! */
382 case I915_PARAM_HAS_GEM:
383 case I915_PARAM_HAS_PAGEFLIPPING:
384 case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
385 case I915_PARAM_HAS_RELAXED_FENCING:
386 case I915_PARAM_HAS_COHERENT_RINGS:
387 case I915_PARAM_HAS_RELAXED_DELTA:
388 case I915_PARAM_HAS_GEN7_SOL_RESET:
389 case I915_PARAM_HAS_WAIT_TIMEOUT:
390 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
391 case I915_PARAM_HAS_PINNED_BATCHES:
392 case I915_PARAM_HAS_EXEC_NO_RELOC:
393 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
394 case I915_PARAM_HAS_COHERENT_PHYS_GTT:
395 case I915_PARAM_HAS_EXEC_SOFTPIN:
77ae9957 396 case I915_PARAM_HAS_EXEC_ASYNC:
fec0445c 397 case I915_PARAM_HAS_EXEC_FENCE:
b0fd47ad 398 case I915_PARAM_HAS_EXEC_CAPTURE:
1a71cf2f 399 case I915_PARAM_HAS_EXEC_BATCH_FIRST:
cf6e7bac 400 case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
16162470
DW		 401 /* For the time being all of these are always true;
402 * if some supported hardware does not have one of these
403 * features this value needs to be provided from
404 * INTEL_INFO(), a feature macro, or similar.
405 */
406 value = 1;
407 break;
d2b4b979
CW		 408 case I915_PARAM_HAS_CONTEXT_ISOLATION:
409 value = intel_engines_has_context_isolation(dev_priv);
410 break;
7fed555c
RB		 411 case I915_PARAM_SLICE_MASK:
412 value = INTEL_INFO(dev_priv)->sseu.slice_mask;
413 if (!value)
414 return -ENODEV;
415 break;
f5320233
RB		 416 case I915_PARAM_SUBSLICE_MASK:
417 value = INTEL_INFO(dev_priv)->sseu.subslice_mask;
418 if (!value)
419 return -ENODEV;
420 break;
dab91783 421 case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
f577a03b 422 value = 1000 * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz;
dab91783 423 break;
0673ad47
CW		 424 default:
425 DRM_DEBUG("Unknown parameter %d\n", param->param);
426 return -EINVAL;
427 }
428
dda33009 429 if (put_user(value, param->value))
0673ad47 430 return -EFAULT;
0673ad47
CW		 431
432 return 0;
433}
434
da5f53bf 435static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
0673ad47 436{
0673ad47
CW		 437 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
438 if (!dev_priv->bridge_dev) {
439 DRM_ERROR("bridge device not found\n");
440 return -1;
441 }
442 return 0;
443}
444
445/* Allocate space for the MCH regs if needed, return nonzero on error */
446static int
da5f53bf 447intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
0673ad47 448{
514e1d64 449 int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
0673ad47
CW		 450 u32 temp_lo, temp_hi = 0;
451 u64 mchbar_addr;
452 int ret;
453
514e1d64 454 if (INTEL_GEN(dev_priv) >= 4)
0673ad47
CW		 455 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
456 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
457 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
458
459 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
460#ifdef CONFIG_PNP
461 if (mchbar_addr &&
462 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
463 return 0;
464#endif
465
466 /* Get some space for it */
467 dev_priv->mch_res.name = "i915 MCHBAR";
468 dev_priv->mch_res.flags = IORESOURCE_MEM;
469 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
470 &dev_priv->mch_res,
471 MCHBAR_SIZE, MCHBAR_SIZE,
472 PCIBIOS_MIN_MEM,
473 0, pcibios_align_resource,
474 dev_priv->bridge_dev);
475 if (ret) {
476 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
477 dev_priv->mch_res.start = 0;
478 return ret;
479 }
480
514e1d64 481 if (INTEL_GEN(dev_priv) >= 4)
0673ad47
CW		 482 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
483 upper_32_bits(dev_priv->mch_res.start));
484
485 pci_write_config_dword(dev_priv->bridge_dev, reg,
486 lower_32_bits(dev_priv->mch_res.start));
487 return 0;
488}
489
490/* Setup MCHBAR if possible, return true if we should disable it again */
491static void
da5f53bf 492intel_setup_mchbar(struct drm_i915_private *dev_priv)
0673ad47 493{
514e1d64 494 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
0673ad47
CW		 495 u32 temp;
496 bool enabled;
497
920a14b2 498 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
0673ad47
CW		 499 return;
500
501 dev_priv->mchbar_need_disable = false;
502
50a0bc90 503 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
0673ad47
CW		 504 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
505 enabled = !!(temp & DEVEN_MCHBAR_EN);
506 } else {
507 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
508 enabled = temp & 1;
509 }
510
511 /* If it's already enabled, don't have to do anything */
512 if (enabled)
513 return;
514
da5f53bf 515 if (intel_alloc_mchbar_resource(dev_priv))
0673ad47
CW		 516 return;
517
518 dev_priv->mchbar_need_disable = true;
519
520 /* Space is allocated or reserved, so enable it. */
50a0bc90 521 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
0673ad47
CW		 522 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
523 temp | DEVEN_MCHBAR_EN);
524 } else {
525 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
526 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
527 }
528}
529
530static void
da5f53bf 531intel_teardown_mchbar(struct drm_i915_private *dev_priv)
0673ad47 532{
514e1d64 533 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
0673ad47
CW		 534
535 if (dev_priv->mchbar_need_disable) {
50a0bc90 536 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
0673ad47
CW		 537 u32 deven_val;
538
539 pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
540 &deven_val);
541 deven_val &= ~DEVEN_MCHBAR_EN;
542 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
543 deven_val);
544 } else {
545 u32 mchbar_val;
546
547 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
548 &mchbar_val);
549 mchbar_val &= ~1;
550 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
551 mchbar_val);
552 }
553 }
554
555 if (dev_priv->mch_res.start)
556 release_resource(&dev_priv->mch_res);
557}
558
559/* true = enable decode, false = disable decoder */
560static unsigned int i915_vga_set_decode(void *cookie, bool state)
561{
da5f53bf 562 struct drm_i915_private *dev_priv = cookie;
0673ad47 563
da5f53bf 564 intel_modeset_vga_set_state(dev_priv, state);
0673ad47
CW		 565 if (state)
566 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
567 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
568 else
569 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
570}
571
7f26cb88
TU		 572static int i915_resume_switcheroo(struct drm_device *dev);
573static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
574
0673ad47
CW		 575static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
576{
577 struct drm_device *dev = pci_get_drvdata(pdev);
578 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
579
580 if (state == VGA_SWITCHEROO_ON) {
581 pr_info("switched on\n");
582 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
583 /* i915 resume handler doesn't set to D0 */
52a05c30 584 pci_set_power_state(pdev, PCI_D0);
0673ad47
CW		 585 i915_resume_switcheroo(dev);
586 dev->switch_power_state = DRM_SWITCH_POWER_ON;
587 } else {
588 pr_info("switched off\n");
589 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
590 i915_suspend_switcheroo(dev, pmm);
591 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
592 }
593}
594
595static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
596{
597 struct drm_device *dev = pci_get_drvdata(pdev);
598
599 /*
600 * FIXME: open_count is protected by drm_global_mutex but that would lead to
601 * locking inversion with the driver load path. And the access here is
602 * completely racy anyway. So don't bother with locking for now.
603 */
604 return dev->open_count == 0;
605}
606
607static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
608 .set_gpu_state = i915_switcheroo_set_state,
609 .reprobe = NULL,
610 .can_switch = i915_switcheroo_can_switch,
611};
612
fbbd37b3 613static void i915_gem_fini(struct drm_i915_private *dev_priv)
0673ad47 614{
3b19f16a
CW		 615 /* Flush any outstanding unpin_work. */
616 i915_gem_drain_workqueue(dev_priv);
5f09a9c8 617
fbbd37b3 618 mutex_lock(&dev_priv->drm.struct_mutex);
b8991403 619 intel_uc_fini_hw(dev_priv);
61b5c158 620 intel_uc_fini(dev_priv);
cb15d9f8 621 i915_gem_cleanup_engines(dev_priv);
829a0af2 622 i915_gem_contexts_fini(dev_priv);
fbbd37b3 623 mutex_unlock(&dev_priv->drm.struct_mutex);
0673ad47 624
3176ff49 625 intel_uc_fini_wq(dev_priv);
7c781423
CW		 626 i915_gem_cleanup_userptr(dev_priv);
627
bdeb9785 628 i915_gem_drain_freed_objects(dev_priv);
fbbd37b3 629
829a0af2 630 WARN_ON(!list_empty(&dev_priv->contexts.list));
0673ad47
CW		 631}
632
633static int i915_load_modeset_init(struct drm_device *dev)
634{
fac5e23e 635 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 636 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 637 int ret;
638
639 if (i915_inject_load_failure())
640 return -ENODEV;
641
66578857 642 intel_bios_init(dev_priv);
0673ad47
CW		 643
644 /* If we have > 1 VGA cards, then we need to arbitrate access
645 * to the common VGA resources.
646 *
647 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
648 * then we do not take part in VGA arbitration and the
649 * vga_client_register() fails with -ENODEV.
650 */
da5f53bf 651 ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
0673ad47
CW		 652 if (ret && ret != -ENODEV)
653 goto out;
654
655 intel_register_dsm_handler();
656
52a05c30 657 ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
0673ad47
CW		 658 if (ret)
659 goto cleanup_vga_client;
660
661 /* must happen before intel_power_domains_init_hw() on VLV/CHV */
662 intel_update_rawclk(dev_priv);
663
664 intel_power_domains_init_hw(dev_priv, false);
665
666 intel_csr_ucode_init(dev_priv);
667
668 ret = intel_irq_install(dev_priv);
669 if (ret)
670 goto cleanup_csr;
671
40196446 672 intel_setup_gmbus(dev_priv);
0673ad47
CW		 673
674 /* Important: The output setup functions called by modeset_init need
675 * working irqs for e.g. gmbus and dp aux transfers. */
b079bd17
VS		 676 ret = intel_modeset_init(dev);
677 if (ret)
678 goto cleanup_irq;
0673ad47 679
29ad6a30 680 intel_uc_init_fw(dev_priv);
0673ad47 681
bf9e8429 682 ret = i915_gem_init(dev_priv);
0673ad47 683 if (ret)
3950bf3d 684 goto cleanup_uc;
0673ad47 685
d378a3ef 686 intel_setup_overlay(dev_priv);
0673ad47 687
b7f05d4a 688 if (INTEL_INFO(dev_priv)->num_pipes == 0)
0673ad47
CW		 689 return 0;
690
691 ret = intel_fbdev_init(dev);
692 if (ret)
693 goto cleanup_gem;
694
695 /* Only enable hotplug handling once the fbdev is fully set up. */
696 intel_hpd_init(dev_priv);
697
0673ad47
CW		 698 return 0;
699
700cleanup_gem:
bf9e8429 701 if (i915_gem_suspend(dev_priv))
1c777c5d 702 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
fbbd37b3 703 i915_gem_fini(dev_priv);
3950bf3d
OM		 704cleanup_uc:
705 intel_uc_fini_fw(dev_priv);
0673ad47 706cleanup_irq:
0673ad47 707 drm_irq_uninstall(dev);
40196446 708 intel_teardown_gmbus(dev_priv);
0673ad47
CW		 709cleanup_csr:
710 intel_csr_ucode_fini(dev_priv);
711 intel_power_domains_fini(dev_priv);
52a05c30 712 vga_switcheroo_unregister_client(pdev);
0673ad47 713cleanup_vga_client:
52a05c30 714 vga_client_register(pdev, NULL, NULL, NULL);
0673ad47
CW		 715out:
716 return ret;
717}
718
0673ad47
CW		 719static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
720{
721 struct apertures_struct *ap;
91c8a326 722 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 723 struct i915_ggtt *ggtt = &dev_priv->ggtt;
724 bool primary;
725 int ret;
726
727 ap = alloc_apertures(1);
728 if (!ap)
729 return -ENOMEM;
730
73ebd503 731 ap->ranges[0].base = ggtt->gmadr.start;
0673ad47
CW		 732 ap->ranges[0].size = ggtt->mappable_end;
733
734 primary =
735 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
736
44adece5 737 ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
0673ad47
CW		 738
739 kfree(ap);
740
741 return ret;
742}
0673ad47
CW		 743
744#if !defined(CONFIG_VGA_CONSOLE)
745static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
746{
747 return 0;
748}
749#elif !defined(CONFIG_DUMMY_CONSOLE)
750static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
751{
752 return -ENODEV;
753}
754#else
755static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
756{
757 int ret = 0;
758
759 DRM_INFO("Replacing VGA console driver\n");
760
761 console_lock();
762 if (con_is_bound(&vga_con))
763 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
764 if (ret == 0) {
765 ret = do_unregister_con_driver(&vga_con);
766
767 /* Ignore "already unregistered". */
768 if (ret == -ENODEV)
769 ret = 0;
770 }
771 console_unlock();
772
773 return ret;
774}
775#endif
776
0673ad47
CW		 777static void intel_init_dpio(struct drm_i915_private *dev_priv)
778{
779 /*
780 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
781 * CHV x1 PHY (DP/HDMI D)
782 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
783 */
784 if (IS_CHERRYVIEW(dev_priv)) {
785 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
786 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
787 } else if (IS_VALLEYVIEW(dev_priv)) {
788 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
789 }
790}
791
792static int i915_workqueues_init(struct drm_i915_private *dev_priv)
793{
794 /*
795 * The i915 workqueue is primarily used for batched retirement of
796 * requests (and thus managing bo) once the task has been completed
797 * by the GPU. i915_gem_retire_requests() is called directly when we
798 * need high-priority retirement, such as waiting for an explicit
799 * bo.
800 *
801 * It is also used for periodic low-priority events, such as
802 * idle-timers and recording error state.
803 *
804 * All tasks on the workqueue are expected to acquire the dev mutex
805 * so there is no point in running more than one instance of the
806 * workqueue at any time. Use an ordered one.
807 */
808 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
809 if (dev_priv->wq == NULL)
810 goto out_err;
811
812 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
813 if (dev_priv->hotplug.dp_wq == NULL)
814 goto out_free_wq;
815
0673ad47
CW		 816 return 0;
817
0673ad47
CW		 818out_free_wq:
819 destroy_workqueue(dev_priv->wq);
820out_err:
821 DRM_ERROR("Failed to allocate workqueues.\n");
822
823 return -ENOMEM;
824}
825
bb8f0f5a
CW		 826static void i915_engines_cleanup(struct drm_i915_private *i915)
827{
828 struct intel_engine_cs *engine;
829 enum intel_engine_id id;
830
831 for_each_engine(engine, i915, id)
832 kfree(engine);
833}
834
0673ad47
CW		 835static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
836{
0673ad47
CW		 837 destroy_workqueue(dev_priv->hotplug.dp_wq);
838 destroy_workqueue(dev_priv->wq);
839}
840
4fc7e845
PZ		 841/*
842 * We don't keep the workarounds for pre-production hardware, so we expect our
843 * driver to fail on these machines in one way or another. A little warning on
844 * dmesg may help both the user and the bug triagers.
6a7a6a98
CW		 845 *
846 * Our policy for removing pre-production workarounds is to keep the
847 * current gen workarounds as a guide to the bring-up of the next gen
848 * (workarounds have a habit of persisting!). Anything older than that
849 * should be removed along with the complications they introduce.
4fc7e845
PZ		 850 */
851static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
852{
248a124d
CW		 853 bool pre = false;
854
855 pre |= IS_HSW_EARLY_SDV(dev_priv);
856 pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
0102ba1f 857 pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
248a124d 858
7c5ff4a2 859 if (pre) {
4fc7e845
PZ		 860 DRM_ERROR("This is a pre-production stepping. "
861 "It may not be fully functional.\n");
7c5ff4a2
CW		 862 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
863 }
4fc7e845
PZ		 864}
865
0673ad47
CW		 866/**
867 * i915_driver_init_early - setup state not requiring device access
868 * @dev_priv: device private
869 *
870 * Initialize everything that is a "SW-only" state, that is state not
871 * requiring accessing the device or exposing the driver via kernel internal
872 * or userspace interfaces. Example steps belonging here: lock initialization,
873 * system memory allocation, setting up device specific attributes and
874 * function hooks not requiring accessing the device.
875 */
876static int i915_driver_init_early(struct drm_i915_private *dev_priv,
877 const struct pci_device_id *ent)
878{
879 const struct intel_device_info *match_info =
880 (struct intel_device_info *)ent->driver_data;
881 struct intel_device_info *device_info;
882 int ret = 0;
883
884 if (i915_inject_load_failure())
885 return -ENODEV;
886
887 /* Setup the write-once "constant" device info */
94b4f3ba 888 device_info = mkwrite_device_info(dev_priv);
0673ad47
CW		 889 memcpy(device_info, match_info, sizeof(*device_info));
890 device_info->device_id = dev_priv->drm.pdev->device;
891
ae7617f0
TU		 892 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
893 sizeof(device_info->platform_mask) * BITS_PER_BYTE);
894 device_info->platform_mask = BIT(device_info->platform);
895
0673ad47
CW		 896 BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
897 device_info->gen_mask = BIT(device_info->gen - 1);
898
899 spin_lock_init(&dev_priv->irq_lock);
900 spin_lock_init(&dev_priv->gpu_error.lock);
901 mutex_init(&dev_priv->backlight_lock);
902 spin_lock_init(&dev_priv->uncore.lock);
317eaa95 903
0673ad47
CW		 904 mutex_init(&dev_priv->sb_lock);
905 mutex_init(&dev_priv->modeset_restore_lock);
906 mutex_init(&dev_priv->av_mutex);
907 mutex_init(&dev_priv->wm.wm_mutex);
908 mutex_init(&dev_priv->pps_mutex);
909
413e8fdb 910 intel_uc_init_early(dev_priv);
0b1de5d5
CW		 911 i915_memcpy_init_early(dev_priv);
912
0673ad47
CW		 913 ret = i915_workqueues_init(dev_priv);
914 if (ret < 0)
bb8f0f5a 915 goto err_engines;
0673ad47 916
0673ad47 917 /* This must be called before any calls to HAS_PCH_* */
da5f53bf 918 intel_detect_pch(dev_priv);
0673ad47 919
192aa181 920 intel_pm_setup(dev_priv);
0673ad47
CW		 921 intel_init_dpio(dev_priv);
922 intel_power_domains_init(dev_priv);
923 intel_irq_init(dev_priv);
3ac168a7 924 intel_hangcheck_init(dev_priv);
0673ad47
CW		 925 intel_init_display_hooks(dev_priv);
926 intel_init_clock_gating_hooks(dev_priv);
927 intel_init_audio_hooks(dev_priv);
cb15d9f8 928 ret = i915_gem_load_init(dev_priv);
73cb9701 929 if (ret < 0)
cefcff8f 930 goto err_irq;
0673ad47 931
36cdd013 932 intel_display_crc_init(dev_priv);
0673ad47 933
4fc7e845 934 intel_detect_preproduction_hw(dev_priv);
0673ad47
CW		 935
936 return 0;
937
cefcff8f
JL		 938err_irq:
939 intel_irq_fini(dev_priv);
0673ad47 940 i915_workqueues_cleanup(dev_priv);
bb8f0f5a
CW		 941err_engines:
942 i915_engines_cleanup(dev_priv);
0673ad47
CW		 943 return ret;
944}
945
946/**
947 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
948 * @dev_priv: device private
949 */
950static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
951{
cb15d9f8 952 i915_gem_load_cleanup(dev_priv);
cefcff8f 953 intel_irq_fini(dev_priv);
0673ad47 954 i915_workqueues_cleanup(dev_priv);
bb8f0f5a 955 i915_engines_cleanup(dev_priv);
0673ad47
CW		 956}
957
da5f53bf 958static int i915_mmio_setup(struct drm_i915_private *dev_priv)
0673ad47 959{
52a05c30 960 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 961 int mmio_bar;
962 int mmio_size;
963
5db94019 964 mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
0673ad47
CW		 965 /*
966 * Before gen4, the registers and the GTT are behind different BARs.
967 * However, from gen4 onwards, the registers and the GTT are shared
968 * in the same BAR, so we want to restrict this ioremap from
969 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
970 * the register BAR remains the same size for all the earlier
971 * generations up to Ironlake.
972 */
514e1d64 973 if (INTEL_GEN(dev_priv) < 5)
0673ad47
CW		 974 mmio_size = 512 * 1024;
975 else
976 mmio_size = 2 * 1024 * 1024;
52a05c30 977 dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
0673ad47
CW		 978 if (dev_priv->regs == NULL) {
979 DRM_ERROR("failed to map registers\n");
980
981 return -EIO;
982 }
983
984 /* Try to make sure MCHBAR is enabled before poking at it */
da5f53bf 985 intel_setup_mchbar(dev_priv);
0673ad47
CW		 986
987 return 0;
988}
989
da5f53bf 990static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
0673ad47 991{
52a05c30 992 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47 993
da5f53bf 994 intel_teardown_mchbar(dev_priv);
52a05c30 995 pci_iounmap(pdev, dev_priv->regs);
0673ad47
CW		 996}
997
998/**
999 * i915_driver_init_mmio - setup device MMIO
1000 * @dev_priv: device private
1001 *
1002 * Setup minimal device state necessary for MMIO accesses later in the
1003 * initialization sequence. The setup here should avoid any other device-wide
1004 * side effects or exposing the driver via kernel internal or user space
1005 * interfaces.
1006 */
1007static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
1008{
0673ad47
CW		 1009 int ret;
1010
1011 if (i915_inject_load_failure())
1012 return -ENODEV;
1013
da5f53bf 1014 if (i915_get_bridge_dev(dev_priv))
0673ad47
CW		 1015 return -EIO;
1016
da5f53bf 1017 ret = i915_mmio_setup(dev_priv);
0673ad47 1018 if (ret < 0)
63ffbcda 1019 goto err_bridge;
0673ad47
CW		 1020
1021 intel_uncore_init(dev_priv);
63ffbcda 1022
1fc556fa
SAK		 1023 intel_uc_init_mmio(dev_priv);
1024
63ffbcda
JL		 1025 ret = intel_engines_init_mmio(dev_priv);
1026 if (ret)
1027 goto err_uncore;
1028
24145517 1029 i915_gem_init_mmio(dev_priv);
0673ad47
CW		 1030
1031 return 0;
1032
63ffbcda
JL		 1033err_uncore:
1034 intel_uncore_fini(dev_priv);
1035err_bridge:
0673ad47
CW		 1036 pci_dev_put(dev_priv->bridge_dev);
1037
1038 return ret;
1039}
1040
1041/**
1042 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1043 * @dev_priv: device private
1044 */
1045static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1046{
0673ad47 1047 intel_uncore_fini(dev_priv);
da5f53bf 1048 i915_mmio_cleanup(dev_priv);
0673ad47
CW		 1049 pci_dev_put(dev_priv->bridge_dev);
1050}
1051
94b4f3ba
CW		 1052static void intel_sanitize_options(struct drm_i915_private *dev_priv)
1053{
94b4f3ba
CW		 1054 /*
1055 * i915.enable_ppgtt is read-only, so do an early pass to validate the
1056 * user's requested state against the hardware/driver capabilities. We
1057 * do this now so that we can print out any log messages once rather
1058 * than every time we check intel_enable_ppgtt().
1059 */
4f044a88
MW		 1060 i915_modparams.enable_ppgtt =
1061 intel_sanitize_enable_ppgtt(dev_priv,
1062 i915_modparams.enable_ppgtt);
1063 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
39df9190 1064
d2be9f2f 1065 intel_uc_sanitize_options(dev_priv);
67b7f33e
CD		 1066
1067 intel_gvt_sanitize_options(dev_priv);
94b4f3ba
CW		 1068}
1069
0673ad47
CW		 1070/**
1071 * i915_driver_init_hw - setup state requiring device access
1072 * @dev_priv: device private
1073 *
1074 * Setup state that requires accessing the device, but doesn't require
1075 * exposing the driver via kernel internal or userspace interfaces.
1076 */
1077static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1078{
52a05c30 1079 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 1080 int ret;
1081
1082 if (i915_inject_load_failure())
1083 return -ENODEV;
1084
6a7e51f3 1085 intel_device_info_runtime_init(mkwrite_device_info(dev_priv));
94b4f3ba
CW		 1086
1087 intel_sanitize_options(dev_priv);
0673ad47 1088
9f9b2792
LL		 1089 i915_perf_init(dev_priv);
1090
97d6d7ab 1091 ret = i915_ggtt_probe_hw(dev_priv);
0673ad47
CW		 1092 if (ret)
1093 return ret;
1094
0673ad47
CW		 1095 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1096 * otherwise the vga fbdev driver falls over. */
1097 ret = i915_kick_out_firmware_fb(dev_priv);
1098 if (ret) {
1099 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1100 goto out_ggtt;
1101 }
1102
1103 ret = i915_kick_out_vgacon(dev_priv);
1104 if (ret) {
1105 DRM_ERROR("failed to remove conflicting VGA console\n");
1106 goto out_ggtt;
1107 }
1108
97d6d7ab 1109 ret = i915_ggtt_init_hw(dev_priv);
0088e522
CW		 1110 if (ret)
1111 return ret;
1112
97d6d7ab 1113 ret = i915_ggtt_enable_hw(dev_priv);
0088e522
CW		 1114 if (ret) {
1115 DRM_ERROR("failed to enable GGTT\n");
1116 goto out_ggtt;
1117 }
1118
52a05c30 1119 pci_set_master(pdev);
0673ad47
CW		 1120
1121 /* overlay on gen2 is broken and can't address above 1G */
5db94019 1122 if (IS_GEN2(dev_priv)) {
52a05c30 1123 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
0673ad47
CW		 1124 if (ret) {
1125 DRM_ERROR("failed to set DMA mask\n");
1126
1127 goto out_ggtt;
1128 }
1129 }
1130
0673ad47
CW		 1131 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1132 * using 32bit addressing, overwriting memory if HWS is located
1133 * above 4GB.
1134 *
1135 * The documentation also mentions an issue with undefined
1136 * behaviour if any general state is accessed within a page above 4GB,
1137 * which also needs to be handled carefully.
1138 */
c0f86832 1139 if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
52a05c30 1140 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
0673ad47
CW		 1141
1142 if (ret) {
1143 DRM_ERROR("failed to set DMA mask\n");
1144
1145 goto out_ggtt;
1146 }
1147 }
1148
0673ad47
CW		 1149 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1150 PM_QOS_DEFAULT_VALUE);
1151
1152 intel_uncore_sanitize(dev_priv);
1153
1154 intel_opregion_setup(dev_priv);
1155
1156 i915_gem_load_init_fences(dev_priv);
1157
1158 /* On the 945G/GM, the chipset reports the MSI capability on the
1159 * integrated graphics even though the support isn't actually there
1160 * according to the published specs. It doesn't appear to function
1161 * correctly in testing on 945G.
1162 * This may be a side effect of MSI having been made available for PEG
1163 * and the registers being closely associated.
1164 *
1165 * According to chipset errata, on the 965GM, MSI interrupts may
e38c2da0
VS		 1166 * be lost or delayed, and was defeatured. MSI interrupts seem to
1167 * get lost on g4x as well, and interrupt delivery seems to stay
1168 * properly dead afterwards. So we'll just disable them for all
1169 * pre-gen5 chipsets.
0673ad47 1170 */
e38c2da0 1171 if (INTEL_GEN(dev_priv) >= 5) {
52a05c30 1172 if (pci_enable_msi(pdev) < 0)
0673ad47
CW		 1173 DRM_DEBUG_DRIVER("can't enable MSI");
1174 }
1175
26f837e8
ZW		 1176 ret = intel_gvt_init(dev_priv);
1177 if (ret)
1178 goto out_ggtt;
1179
0673ad47
CW		 1180 return 0;
1181
1182out_ggtt:
97d6d7ab 1183 i915_ggtt_cleanup_hw(dev_priv);
0673ad47
CW		 1184
1185 return ret;
1186}
1187
1188/**
1189 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1190 * @dev_priv: device private
1191 */
1192static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1193{
52a05c30 1194 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47 1195
9f9b2792
LL		 1196 i915_perf_fini(dev_priv);
1197
52a05c30
DW		 1198 if (pdev->msi_enabled)
1199 pci_disable_msi(pdev);
0673ad47
CW		 1200
1201 pm_qos_remove_request(&dev_priv->pm_qos);
97d6d7ab 1202 i915_ggtt_cleanup_hw(dev_priv);
0673ad47
CW		 1203}
1204
1205/**
1206 * i915_driver_register - register the driver with the rest of the system
1207 * @dev_priv: device private
1208 *
1209 * Perform any steps necessary to make the driver available via kernel
1210 * internal or userspace interfaces.
1211 */
1212static void i915_driver_register(struct drm_i915_private *dev_priv)
1213{
91c8a326 1214 struct drm_device *dev = &dev_priv->drm;
0673ad47 1215
848b365d 1216 i915_gem_shrinker_register(dev_priv);
b46a33e2 1217 i915_pmu_register(dev_priv);
0673ad47
CW		 1218
1219 /*
1220 * Notify a valid surface after modesetting,
1221 * when running inside a VM.
1222 */
1223 if (intel_vgpu_active(dev_priv))
1224 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1225
1226 /* Reveal our presence to userspace */
1227 if (drm_dev_register(dev, 0) == 0) {
1228 i915_debugfs_register(dev_priv);
f9cda048 1229 i915_guc_log_register(dev_priv);
694c2828 1230 i915_setup_sysfs(dev_priv);
442b8c06
RB		 1231
1232 /* Depends on sysfs having been initialized */
1233 i915_perf_register(dev_priv);
0673ad47
CW		 1234 } else
1235 DRM_ERROR("Failed to register driver for userspace access!\n");
1236
1237 if (INTEL_INFO(dev_priv)->num_pipes) {
1238 /* Must be done after probing outputs */
1239 intel_opregion_register(dev_priv);
1240 acpi_video_register();
1241 }
1242
1243 if (IS_GEN5(dev_priv))
1244 intel_gpu_ips_init(dev_priv);
1245
eef57324 1246 intel_audio_init(dev_priv);
0673ad47
CW		 1247
1248 /*
1249 * Some ports require correctly set-up hpd registers for detection to
1250 * work properly (leading to ghost connected connector status), e.g. VGA
1251 * on gm45. Hence we can only set up the initial fbdev config after hpd
1252 * irqs are fully enabled. We do it last so that the async config
1253 * cannot run before the connectors are registered.
1254 */
1255 intel_fbdev_initial_config_async(dev);
448aa911
CW		 1256
1257 /*
1258 * We need to coordinate the hotplugs with the asynchronous fbdev
1259 * configuration, for which we use the fbdev->async_cookie.
1260 */
1261 if (INTEL_INFO(dev_priv)->num_pipes)
1262 drm_kms_helper_poll_init(dev);
0673ad47
CW		 1263}
1264
1265/**
1266 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1267 * @dev_priv: device private
1268 */
1269static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1270{
4f256d82 1271 intel_fbdev_unregister(dev_priv);
eef57324 1272 intel_audio_deinit(dev_priv);
0673ad47 1273
448aa911
CW		 1274 /*
1275 * After flushing the fbdev (incl. a late async config which will
1276 * have delayed queuing of a hotplug event), then flush the hotplug
1277 * events.
1278 */
1279 drm_kms_helper_poll_fini(&dev_priv->drm);
1280
0673ad47
CW		 1281 intel_gpu_ips_teardown();
1282 acpi_video_unregister();
1283 intel_opregion_unregister(dev_priv);
1284
442b8c06 1285 i915_perf_unregister(dev_priv);
b46a33e2 1286 i915_pmu_unregister(dev_priv);
442b8c06 1287
694c2828 1288 i915_teardown_sysfs(dev_priv);
f9cda048 1289 i915_guc_log_unregister(dev_priv);
91c8a326 1290 drm_dev_unregister(&dev_priv->drm);
0673ad47 1291
848b365d 1292 i915_gem_shrinker_unregister(dev_priv);
0673ad47
CW		 1293}
1294
27d558a1
MW		 1295static void i915_welcome_messages(struct drm_i915_private *dev_priv)
1296{
1297 if (drm_debug & DRM_UT_DRIVER) {
1298 struct drm_printer p = drm_debug_printer("i915 device info:");
1299
1300 intel_device_info_dump(&dev_priv->info, &p);
1301 intel_device_info_dump_runtime(&dev_priv->info, &p);
1302 }
1303
1304 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1305 DRM_INFO("DRM_I915_DEBUG enabled\n");
1306 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1307 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1308}
1309
0673ad47
CW		 1310/**
1311 * i915_driver_load - setup chip and create an initial config
d2ad3ae4
JL		 1312 * @pdev: PCI device
1313 * @ent: matching PCI ID entry
0673ad47
CW		 1314 *
1315 * The driver load routine has to do several things:
1316 * - drive output discovery via intel_modeset_init()
1317 * - initialize the memory manager
1318 * - allocate initial config memory
1319 * - setup the DRM framebuffer with the allocated memory
1320 */
42f5551d 1321int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
0673ad47 1322{
8d2b47dd
ML		 1323 const struct intel_device_info *match_info =
1324 (struct intel_device_info *)ent->driver_data;
0673ad47
CW		 1325 struct drm_i915_private *dev_priv;
1326 int ret;
7d87a7f7 1327
ff4c3b76 1328 /* Enable nuclear pageflip on ILK+ */
4f044a88 1329 if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
8d2b47dd 1330 driver.driver_features &= ~DRIVER_ATOMIC;
a09d0ba1 1331
0673ad47
CW		 1332 ret = -ENOMEM;
1333 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1334 if (dev_priv)
1335 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1336 if (ret) {
87a6752c 1337 DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
cad3688f 1338 goto out_free;
0673ad47 1339 }
72bbf0af 1340
0673ad47
CW		 1341 dev_priv->drm.pdev = pdev;
1342 dev_priv->drm.dev_private = dev_priv;
719388e1 1343
0673ad47
CW		 1344 ret = pci_enable_device(pdev);
1345 if (ret)
cad3688f 1346 goto out_fini;
1347f5b4 1347
0673ad47 1348 pci_set_drvdata(pdev, &dev_priv->drm);
adfdf85d
ID		 1349 /*
1350 * Disable the system suspend direct complete optimization, which can
1351 * leave the device suspended skipping the driver's suspend handlers
1352 * if the device was already runtime suspended. This is needed due to
1353 * the difference in our runtime and system suspend sequence and
1354 * becaue the HDA driver may require us to enable the audio power
1355 * domain during system suspend.
1356 */
c2eac4d3 1357 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP);
ef11bdb3 1358
0673ad47
CW		 1359 ret = i915_driver_init_early(dev_priv, ent);
1360 if (ret < 0)
1361 goto out_pci_disable;
ef11bdb3 1362
0673ad47 1363 intel_runtime_pm_get(dev_priv);
1da177e4 1364
0673ad47
CW		 1365 ret = i915_driver_init_mmio(dev_priv);
1366 if (ret < 0)
1367 goto out_runtime_pm_put;
79e53945 1368
0673ad47
CW		 1369 ret = i915_driver_init_hw(dev_priv);
1370 if (ret < 0)
1371 goto out_cleanup_mmio;
30c964a6
RB		 1372
1373 /*
0673ad47
CW		 1374 * TODO: move the vblank init and parts of modeset init steps into one
1375 * of the i915_driver_init_/i915_driver_register functions according
1376 * to the role/effect of the given init step.
30c964a6 1377 */
0673ad47 1378 if (INTEL_INFO(dev_priv)->num_pipes) {
91c8a326 1379 ret = drm_vblank_init(&dev_priv->drm,
0673ad47
CW		 1380 INTEL_INFO(dev_priv)->num_pipes);
1381 if (ret)
1382 goto out_cleanup_hw;
30c964a6
RB		 1383 }
1384
91c8a326 1385 ret = i915_load_modeset_init(&dev_priv->drm);
0673ad47 1386 if (ret < 0)
baf54385 1387 goto out_cleanup_hw;
0673ad47
CW		 1388
1389 i915_driver_register(dev_priv);
1390
1391 intel_runtime_pm_enable(dev_priv);
1392
2503a0fe 1393 intel_init_ipc(dev_priv);
a3a8986c 1394
0673ad47
CW		 1395 intel_runtime_pm_put(dev_priv);
1396
27d558a1
MW		 1397 i915_welcome_messages(dev_priv);
1398
0673ad47
CW		 1399 return 0;
1400
0673ad47
CW		 1401out_cleanup_hw:
1402 i915_driver_cleanup_hw(dev_priv);
1403out_cleanup_mmio:
1404 i915_driver_cleanup_mmio(dev_priv);
1405out_runtime_pm_put:
1406 intel_runtime_pm_put(dev_priv);
1407 i915_driver_cleanup_early(dev_priv);
1408out_pci_disable:
1409 pci_disable_device(pdev);
cad3688f 1410out_fini:
0673ad47 1411 i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
cad3688f
CW		 1412 drm_dev_fini(&dev_priv->drm);
1413out_free:
1414 kfree(dev_priv);
30c964a6
RB		 1415 return ret;
1416}
1417
42f5551d 1418void i915_driver_unload(struct drm_device *dev)
3bad0781 1419{
fac5e23e 1420 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 1421 struct pci_dev *pdev = dev_priv->drm.pdev;
3bad0781 1422
99c539be
DV		 1423 i915_driver_unregister(dev_priv);
1424
bf9e8429 1425 if (i915_gem_suspend(dev_priv))
42f5551d 1426 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
ce1bb329 1427
0673ad47
CW		 1428 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1429
18dddadc 1430 drm_atomic_helper_shutdown(dev);
a667fb40 1431
26f837e8
ZW		 1432 intel_gvt_cleanup(dev_priv);
1433
0673ad47
CW		 1434 intel_modeset_cleanup(dev);
1435
3bad0781 1436 /*
0673ad47
CW		 1437 * free the memory space allocated for the child device
1438 * config parsed from VBT
3bad0781 1439 */
0673ad47
CW		 1440 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1441 kfree(dev_priv->vbt.child_dev);
1442 dev_priv->vbt.child_dev = NULL;
1443 dev_priv->vbt.child_dev_num = 0;
1444 }
1445 kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1446 dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1447 kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1448 dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
3bad0781 1449
52a05c30
DW		 1450 vga_switcheroo_unregister_client(pdev);
1451 vga_client_register(pdev, NULL, NULL, NULL);
bcdb72ac 1452
0673ad47 1453 intel_csr_ucode_fini(dev_priv);
bcdb72ac 1454
0673ad47
CW		 1455 /* Free error state after interrupts are fully disabled. */
1456 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
5a4c6f1b 1457 i915_reset_error_state(dev_priv);
0673ad47 1458
fbbd37b3 1459 i915_gem_fini(dev_priv);
3950bf3d 1460 intel_uc_fini_fw(dev_priv);
0673ad47
CW		 1461 intel_fbc_cleanup_cfb(dev_priv);
1462
1463 intel_power_domains_fini(dev_priv);
1464
1465 i915_driver_cleanup_hw(dev_priv);
1466 i915_driver_cleanup_mmio(dev_priv);
1467
1468 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
cad3688f
CW		 1469}
1470
1471static void i915_driver_release(struct drm_device *dev)
1472{
1473 struct drm_i915_private *dev_priv = to_i915(dev);
0673ad47
CW		 1474
1475 i915_driver_cleanup_early(dev_priv);
cad3688f
CW		 1476 drm_dev_fini(&dev_priv->drm);
1477
1478 kfree(dev_priv);
3bad0781
ZW		 1479}
1480
0673ad47 1481static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
2911a35b 1482{
829a0af2 1483 struct drm_i915_private *i915 = to_i915(dev);
0673ad47 1484 int ret;
2911a35b 1485
829a0af2 1486 ret = i915_gem_open(i915, file);
0673ad47
CW		 1487 if (ret)
1488 return ret;
2911a35b 1489
0673ad47
CW		 1490 return 0;
1491}
71386ef9 1492
0673ad47
CW		 1493/**
1494 * i915_driver_lastclose - clean up after all DRM clients have exited
1495 * @dev: DRM device
1496 *
1497 * Take care of cleaning up after all DRM clients have exited. In the
1498 * mode setting case, we want to restore the kernel's initial mode (just
1499 * in case the last client left us in a bad state).
1500 *
1501 * Additionally, in the non-mode setting case, we'll tear down the GTT
1502 * and DMA structures, since the kernel won't be using them, and clea
1503 * up any GEM state.
1504 */
1505static void i915_driver_lastclose(struct drm_device *dev)
1506{
1507 intel_fbdev_restore_mode(dev);
1508 vga_switcheroo_process_delayed_switch();
1509}
2911a35b 1510
7d2ec881 1511static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
0673ad47 1512{
7d2ec881
DV		 1513 struct drm_i915_file_private *file_priv = file->driver_priv;
1514
0673ad47 1515 mutex_lock(&dev->struct_mutex);
829a0af2 1516 i915_gem_context_close(file);
0673ad47
CW		 1517 i915_gem_release(dev, file);
1518 mutex_unlock(&dev->struct_mutex);
0673ad47
CW		 1519
1520 kfree(file_priv);
2911a35b
BW		 1521}
1522
07f9cd0b
ID		 1523static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1524{
91c8a326 1525 struct drm_device *dev = &dev_priv->drm;
19c8054c 1526 struct intel_encoder *encoder;
07f9cd0b
ID		 1527
1528 drm_modeset_lock_all(dev);
19c8054c
JN		 1529 for_each_intel_encoder(dev, encoder)
1530 if (encoder->suspend)
1531 encoder->suspend(encoder);
07f9cd0b
ID		 1532 drm_modeset_unlock_all(dev);
1533}
1534
1a5df187
PZ		 1535static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1536 bool rpm_resume);
507e126e 1537static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
f75a1985 1538
bc87229f
ID		 1539static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1540{
1541#if IS_ENABLED(CONFIG_ACPI_SLEEP)
1542 if (acpi_target_system_state() < ACPI_STATE_S3)
1543 return true;
1544#endif
1545 return false;
1546}
ebc32824 1547
5e365c39 1548static int i915_drm_suspend(struct drm_device *dev)
ba8bbcf6 1549{
fac5e23e 1550 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 1551 struct pci_dev *pdev = dev_priv->drm.pdev;
e5747e3a 1552 pci_power_t opregion_target_state;
d5818938 1553 int error;
61caf87c 1554
b8efb17b
ZR		 1555 /* ignore lid events during suspend */
1556 mutex_lock(&dev_priv->modeset_restore_lock);
1557 dev_priv->modeset_restore = MODESET_SUSPENDED;
1558 mutex_unlock(&dev_priv->modeset_restore_lock);
1559
1f814dac
ID		 1560 disable_rpm_wakeref_asserts(dev_priv);
1561
c67a470b
PZ		 1562 /* We do a lot of poking in a lot of registers, make sure they work
1563 * properly. */
da7e29bd 1564 intel_display_set_init_power(dev_priv, true);
cb10799c 1565
5bcf719b
DA		 1566 drm_kms_helper_poll_disable(dev);
1567
52a05c30 1568 pci_save_state(pdev);
ba8bbcf6 1569
bf9e8429 1570 error = i915_gem_suspend(dev_priv);
d5818938 1571 if (error) {
52a05c30 1572 dev_err(&pdev->dev,
d5818938 1573 "GEM idle failed, resume might fail\n");
1f814dac 1574 goto out;
d5818938 1575 }
db1b76ca 1576
6b72d486 1577 intel_display_suspend(dev);
2eb5252e 1578
d5818938 1579 intel_dp_mst_suspend(dev);
7d708ee4 1580
d5818938
DV		 1581 intel_runtime_pm_disable_interrupts(dev_priv);
1582 intel_hpd_cancel_work(dev_priv);
09b64267 1583
d5818938 1584 intel_suspend_encoders(dev_priv);
0e32b39c 1585
712bf364 1586 intel_suspend_hw(dev_priv);
5669fcac 1587
275a991c 1588 i915_gem_suspend_gtt_mappings(dev_priv);
828c7908 1589
af6dc742 1590 i915_save_state(dev_priv);
9e06dd39 1591
bc87229f 1592 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
6f9f4b7a 1593 intel_opregion_notify_adapter(dev_priv, opregion_target_state);
e5747e3a 1594
68f60946 1595 intel_uncore_suspend(dev_priv);
03d92e47 1596 intel_opregion_unregister(dev_priv);
8ee1c3db 1597
82e3b8c1 1598 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
3fa016a0 1599
62d5d69b
MK		 1600 dev_priv->suspend_count++;
1601
f74ed08d 1602 intel_csr_ucode_suspend(dev_priv);
f514c2d8 1603
1f814dac
ID		 1604out:
1605 enable_rpm_wakeref_asserts(dev_priv);
1606
1607 return error;
84b79f8d
RW		 1608}
1609
c49d13ee 1610static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
c3c09c95 1611{
c49d13ee 1612 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 1613 struct pci_dev *pdev = dev_priv->drm.pdev;
bc87229f 1614 bool fw_csr;
c3c09c95
ID		 1615 int ret;
1616
1f814dac
ID		 1617 disable_rpm_wakeref_asserts(dev_priv);
1618
4c494a57
ID		 1619 intel_display_set_init_power(dev_priv, false);
1620
dd9f31c7 1621 fw_csr = !IS_GEN9_LP(dev_priv) && !hibernation &&
a7c8125f 1622 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
bc87229f
ID		 1623 /*
1624 * In case of firmware assisted context save/restore don't manually
1625 * deinit the power domains. This also means the CSR/DMC firmware will
1626 * stay active, it will power down any HW resources as required and
1627 * also enable deeper system power states that would be blocked if the
1628 * firmware was inactive.
1629 */
1630 if (!fw_csr)
1631 intel_power_domains_suspend(dev_priv);
73dfc227 1632
507e126e 1633 ret = 0;
b9fd799e 1634 if (IS_GEN9_LP(dev_priv))
507e126e 1635 bxt_enable_dc9(dev_priv);
b8aea3d1 1636 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
507e126e
ID		 1637 hsw_enable_pc8(dev_priv);
1638 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1639 ret = vlv_suspend_complete(dev_priv);
c3c09c95
ID		 1640
1641 if (ret) {
1642 DRM_ERROR("Suspend complete failed: %d\n", ret);
bc87229f
ID		 1643 if (!fw_csr)
1644 intel_power_domains_init_hw(dev_priv, true);
c3c09c95 1645
1f814dac 1646 goto out;
c3c09c95
ID		 1647 }
1648
52a05c30 1649 pci_disable_device(pdev);
ab3be73f 1650 /*
54875571 1651 * During hibernation on some platforms the BIOS may try to access
ab3be73f
ID		 1652 * the device even though it's already in D3 and hang the machine. So
1653 * leave the device in D0 on those platforms and hope the BIOS will
54875571
ID		 1654 * power down the device properly. The issue was seen on multiple old
1655 * GENs with different BIOS vendors, so having an explicit blacklist
1656 * is inpractical; apply the workaround on everything pre GEN6. The
1657 * platforms where the issue was seen:
1658 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1659 * Fujitsu FSC S7110
1660 * Acer Aspire 1830T
ab3be73f 1661 */
514e1d64 1662 if (!(hibernation && INTEL_GEN(dev_priv) < 6))
52a05c30 1663 pci_set_power_state(pdev, PCI_D3hot);
c3c09c95 1664
bc87229f
ID		 1665 dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1666
1f814dac
ID		 1667out:
1668 enable_rpm_wakeref_asserts(dev_priv);
1669
1670 return ret;
c3c09c95
ID		 1671}
1672
a9a251c2 1673static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
84b79f8d
RW		 1674{
1675 int error;
1676
ded8b07d 1677 if (!dev) {
84b79f8d
RW		 1678 DRM_ERROR("dev: %p\n", dev);
1679 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1680 return -ENODEV;
1681 }
1682
0b14cbd2
ID		 1683 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1684 state.event != PM_EVENT_FREEZE))
1685 return -EINVAL;
5bcf719b
DA		 1686
1687 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1688 return 0;
6eecba33 1689
5e365c39 1690 error = i915_drm_suspend(dev);
84b79f8d
RW		 1691 if (error)
1692 return error;
1693
ab3be73f 1694 return i915_drm_suspend_late(dev, false);
ba8bbcf6
JB		 1695}
1696
5e365c39 1697static int i915_drm_resume(struct drm_device *dev)
76c4b250 1698{
fac5e23e 1699 struct drm_i915_private *dev_priv = to_i915(dev);
ac840ae5 1700 int ret;
9d49c0ef 1701
1f814dac 1702 disable_rpm_wakeref_asserts(dev_priv);
abc80abd 1703 intel_sanitize_gt_powersave(dev_priv);
1f814dac 1704
97d6d7ab 1705 ret = i915_ggtt_enable_hw(dev_priv);
ac840ae5
VS		 1706 if (ret)
1707 DRM_ERROR("failed to re-enable GGTT\n");
1708
f74ed08d
ID		 1709 intel_csr_ucode_resume(dev_priv);
1710
af6dc742 1711 i915_restore_state(dev_priv);
8090ba8c 1712 intel_pps_unlock_regs_wa(dev_priv);
6f9f4b7a 1713 intel_opregion_setup(dev_priv);
61caf87c 1714
c39055b0 1715 intel_init_pch_refclk(dev_priv);
1833b134 1716
364aece0
PA		 1717 /*
1718 * Interrupts have to be enabled before any batches are run. If not the
1719 * GPU will hang. i915_gem_init_hw() will initiate batches to
1720 * update/restore the context.
1721 *
908764f6
ID		 1722 * drm_mode_config_reset() needs AUX interrupts.
1723 *
364aece0
PA		 1724 * Modeset enabling in intel_modeset_init_hw() also needs working
1725 * interrupts.
1726 */
1727 intel_runtime_pm_enable_interrupts(dev_priv);
1728
908764f6
ID		 1729 drm_mode_config_reset(dev);
1730
37cd3300 1731 i915_gem_resume(dev_priv);
226485e9 1732
d5818938 1733 intel_modeset_init_hw(dev);
675f7ff3 1734 intel_init_clock_gating(dev_priv);
24576d23 1735
d5818938
DV		 1736 spin_lock_irq(&dev_priv->irq_lock);
1737 if (dev_priv->display.hpd_irq_setup)
91d14251 1738 dev_priv->display.hpd_irq_setup(dev_priv);
d5818938 1739 spin_unlock_irq(&dev_priv->irq_lock);
0e32b39c 1740
d5818938 1741 intel_dp_mst_resume(dev);
e7d6f7d7 1742
a16b7658
L		 1743 intel_display_resume(dev);
1744
e0b70061
L		 1745 drm_kms_helper_poll_enable(dev);
1746
d5818938
DV		 1747 /*
1748 * ... but also need to make sure that hotplug processing
1749 * doesn't cause havoc. Like in the driver load code we don't
1750 * bother with the tiny race here where we might loose hotplug
1751 * notifications.
1752 * */
1753 intel_hpd_init(dev_priv);
1daed3fb 1754
03d92e47 1755 intel_opregion_register(dev_priv);
44834a67 1756
82e3b8c1 1757 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
073f34d9 1758
b8efb17b
ZR		 1759 mutex_lock(&dev_priv->modeset_restore_lock);
1760 dev_priv->modeset_restore = MODESET_DONE;
1761 mutex_unlock(&dev_priv->modeset_restore_lock);
8a187455 1762
6f9f4b7a 1763 intel_opregion_notify_adapter(dev_priv, PCI_D0);
e5747e3a 1764
1f814dac
ID		 1765 enable_rpm_wakeref_asserts(dev_priv);
1766
074c6ada 1767 return 0;
84b79f8d
RW		 1768}
1769
5e365c39 1770static int i915_drm_resume_early(struct drm_device *dev)
84b79f8d 1771{
fac5e23e 1772 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 1773 struct pci_dev *pdev = dev_priv->drm.pdev;
44410cd0 1774 int ret;
36d61e67 1775
76c4b250
ID		 1776 /*
1777 * We have a resume ordering issue with the snd-hda driver also
1778 * requiring our device to be power up. Due to the lack of a
1779 * parent/child relationship we currently solve this with an early
1780 * resume hook.
1781 *
1782 * FIXME: This should be solved with a special hdmi sink device or
1783 * similar so that power domains can be employed.
1784 */
44410cd0
ID		 1785
1786 /*
1787 * Note that we need to set the power state explicitly, since we
1788 * powered off the device during freeze and the PCI core won't power
1789 * it back up for us during thaw. Powering off the device during
1790 * freeze is not a hard requirement though, and during the
1791 * suspend/resume phases the PCI core makes sure we get here with the
1792 * device powered on. So in case we change our freeze logic and keep
1793 * the device powered we can also remove the following set power state
1794 * call.
1795 */
52a05c30 1796 ret = pci_set_power_state(pdev, PCI_D0);
44410cd0
ID		 1797 if (ret) {
1798 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1799 goto out;
1800 }
1801
1802 /*
1803 * Note that pci_enable_device() first enables any parent bridge
1804 * device and only then sets the power state for this device. The
1805 * bridge enabling is a nop though, since bridge devices are resumed
1806 * first. The order of enabling power and enabling the device is
1807 * imposed by the PCI core as described above, so here we preserve the
1808 * same order for the freeze/thaw phases.
1809 *
1810 * TODO: eventually we should remove pci_disable_device() /
1811 * pci_enable_enable_device() from suspend/resume. Due to how they
1812 * depend on the device enable refcount we can't anyway depend on them
1813 * disabling/enabling the device.
1814 */
52a05c30 1815 if (pci_enable_device(pdev)) {
bc87229f
ID		 1816 ret = -EIO;
1817 goto out;
1818 }
84b79f8d 1819
52a05c30 1820 pci_set_master(pdev);
84b79f8d 1821
1f814dac
ID		 1822 disable_rpm_wakeref_asserts(dev_priv);
1823
666a4537 1824 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1a5df187 1825 ret = vlv_resume_prepare(dev_priv, false);
36d61e67 1826 if (ret)
ff0b187f
DL		 1827 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1828 ret);
36d61e67 1829
68f60946 1830 intel_uncore_resume_early(dev_priv);
efee833a 1831
b9fd799e 1832 if (IS_GEN9_LP(dev_priv)) {
da2f41d1
ID		 1833 if (!dev_priv->suspended_to_idle)
1834 gen9_sanitize_dc_state(dev_priv);
507e126e 1835 bxt_disable_dc9(dev_priv);
da2f41d1 1836 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
a9a6b73a 1837 hsw_disable_pc8(dev_priv);
da2f41d1 1838 }
efee833a 1839
dc97997a 1840 intel_uncore_sanitize(dev_priv);
bc87229f 1841
b9fd799e 1842 if (IS_GEN9_LP(dev_priv) ||
a7c8125f 1843 !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
bc87229f 1844 intel_power_domains_init_hw(dev_priv, true);
d13a8479
ML		 1845 else
1846 intel_display_set_init_power(dev_priv, true);
bc87229f 1847
24145517
CW		 1848 i915_gem_sanitize(dev_priv);
1849
6e35e8ab
ID		 1850 enable_rpm_wakeref_asserts(dev_priv);
1851
bc87229f
ID		 1852out:
1853 dev_priv->suspended_to_idle = false;
36d61e67
ID		 1854
1855 return ret;
76c4b250
ID		 1856}
1857
7f26cb88 1858static int i915_resume_switcheroo(struct drm_device *dev)
76c4b250 1859{
50a0072f 1860 int ret;
76c4b250 1861
097dd837
ID		 1862 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1863 return 0;
1864
5e365c39 1865 ret = i915_drm_resume_early(dev);
50a0072f
ID		 1866 if (ret)
1867 return ret;
1868
5a17514e
ID		 1869 return i915_drm_resume(dev);
1870}
1871
11ed50ec 1872/**
f3953dcb 1873 * i915_reset - reset chip after a hang
535275d3
CW		 1874 * @i915: #drm_i915_private to reset
1875 * @flags: Instructions
11ed50ec 1876 *
780f262a
CW		 1877 * Reset the chip. Useful if a hang is detected. Marks the device as wedged
1878 * on failure.
11ed50ec 1879 *
221fe799
CW		 1880 * Caller must hold the struct_mutex.
1881 *
11ed50ec
BG		 1882 * Procedure is fairly simple:
1883 * - reset the chip using the reset reg
1884 * - re-init context state
1885 * - re-init hardware status page
1886 * - re-init ring buffer
1887 * - re-init interrupt state
1888 * - re-init display
1889 */
535275d3 1890void i915_reset(struct drm_i915_private *i915, unsigned int flags)
11ed50ec 1891{
535275d3 1892 struct i915_gpu_error *error = &i915->gpu_error;
0573ed4a 1893 int ret;
f7096d40 1894 int i;
11ed50ec 1895
f7096d40 1896 might_sleep();
535275d3 1897 lockdep_assert_held(&i915->drm.struct_mutex);
8c185eca 1898 GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
221fe799 1899
8c185eca 1900 if (!test_bit(I915_RESET_HANDOFF, &error->flags))
780f262a 1901 return;
11ed50ec 1902
d98c52cf 1903 /* Clear any previous failed attempts at recovery. Time to try again. */
535275d3 1904 if (!i915_gem_unset_wedged(i915))
2e8f9d32
CW		 1905 goto wakeup;
1906
535275d3
CW		 1907 if (!(flags & I915_RESET_QUIET))
1908 dev_notice(i915->drm.dev, "Resetting chip after gpu hang\n");
8af29b0c 1909 error->reset_count++;
d98c52cf 1910
535275d3
CW		 1911 disable_irq(i915->drm.irq);
1912 ret = i915_gem_reset_prepare(i915);
0e178aef 1913 if (ret) {
107783d0 1914 dev_err(i915->drm.dev, "GPU recovery failed\n");
535275d3 1915 intel_gpu_reset(i915, ALL_ENGINES);
107783d0 1916 goto taint;
0e178aef 1917 }
9e60ab03 1918
f7096d40 1919 if (!intel_has_gpu_reset(i915)) {
3ef98f50
CW		 1920 if (i915_modparams.reset)
1921 dev_err(i915->drm.dev, "GPU reset not supported\n");
1922 else
1923 DRM_DEBUG_DRIVER("GPU reset disabled\n");
f7096d40
CW		 1924 goto error;
1925 }
1926
1927 for (i = 0; i < 3; i++) {
1928 ret = intel_gpu_reset(i915, ALL_ENGINES);
1929 if (ret == 0)
1930 break;
1931
1932 msleep(100);
1933 }
0573ed4a 1934 if (ret) {
f7096d40 1935 dev_err(i915->drm.dev, "Failed to reset chip\n");
107783d0 1936 goto taint;
11ed50ec
BG		 1937 }
1938
1939 /* Ok, now get things going again... */
1940
1941 /*
1942 * Everything depends on having the GTT running, so we need to start
0db8c961
CW		 1943 * there.
1944 */
1945 ret = i915_ggtt_enable_hw(i915);
1946 if (ret) {
1947 DRM_ERROR("Failed to re-enable GGTT following reset %d\n", ret);
1948 goto error;
1949 }
1950
a31d73c3
CW		 1951 i915_gem_reset(i915);
1952 intel_overlay_reset(i915);
1953
0db8c961 1954 /*
11ed50ec
BG		 1955 * Next we need to restore the context, but we don't use those
1956 * yet either...
1957 *
1958 * Ring buffer needs to be re-initialized in the KMS case, or if X
1959 * was running at the time of the reset (i.e. we weren't VT
1960 * switched away).
1961 */
535275d3 1962 ret = i915_gem_init_hw(i915);
33d30a9c
DV		 1963 if (ret) {
1964 DRM_ERROR("Failed hw init on reset %d\n", ret);
d98c52cf 1965 goto error;
11ed50ec
BG		 1966 }
1967
535275d3 1968 i915_queue_hangcheck(i915);
c2a126a4 1969
2e8f9d32 1970finish:
535275d3
CW		 1971 i915_gem_reset_finish(i915);
1972 enable_irq(i915->drm.irq);
8c185eca 1973
2e8f9d32 1974wakeup:
8c185eca
CW		 1975 clear_bit(I915_RESET_HANDOFF, &error->flags);
1976 wake_up_bit(&error->flags, I915_RESET_HANDOFF);
780f262a 1977 return;
d98c52cf 1978
107783d0
CW		 1979taint:
1980 /*
1981 * History tells us that if we cannot reset the GPU now, we
1982 * never will. This then impacts everything that is run
1983 * subsequently. On failing the reset, we mark the driver
1984 * as wedged, preventing further execution on the GPU.
1985 * We also want to go one step further and add a taint to the
1986 * kernel so that any subsequent faults can be traced back to
1987 * this failure. This is important for CI, where if the
1988 * GPU/driver fails we would like to reboot and restart testing
1989 * rather than continue on into oblivion. For everyone else,
1990 * the system should still plod along, but they have been warned!
1991 */
1992 add_taint(TAINT_WARN, LOCKDEP_STILL_OK);
d98c52cf 1993error:
535275d3
CW		 1994 i915_gem_set_wedged(i915);
1995 i915_gem_retire_requests(i915);
2e8f9d32 1996 goto finish;
11ed50ec
BG		 1997}
1998
6acbea89
MT		 1999static inline int intel_gt_reset_engine(struct drm_i915_private *dev_priv,
2000 struct intel_engine_cs *engine)
2001{
2002 return intel_gpu_reset(dev_priv, intel_engine_flag(engine));
2003}
2004
142bc7d9
MT		 2005/**
2006 * i915_reset_engine - reset GPU engine to recover from a hang
2007 * @engine: engine to reset
535275d3 2008 * @flags: options
142bc7d9
MT		 2009 *
2010 * Reset a specific GPU engine. Useful if a hang is detected.
2011 * Returns zero on successful reset or otherwise an error code.
a1ef70e1
MT		 2012 *
2013 * Procedure is:
2014 * - identifies the request that caused the hang and it is dropped
2015 * - reset engine (which will force the engine to idle)
2016 * - re-init/configure engine
142bc7d9 2017 */
535275d3 2018int i915_reset_engine(struct intel_engine_cs *engine, unsigned int flags)
142bc7d9 2019{
a1ef70e1
MT		 2020 struct i915_gpu_error *error = &engine->i915->gpu_error;
2021 struct drm_i915_gem_request *active_request;
2022 int ret;
2023
2024 GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));
2025
f6ba181a
CW		 2026 active_request = i915_gem_reset_prepare_engine(engine);
2027 if (IS_ERR_OR_NULL(active_request)) {
2028 /* Either the previous reset failed, or we pardon the reset. */
2029 ret = PTR_ERR(active_request);
2030 goto out;
2031 }
2032
535275d3
CW		 2033 if (!(flags & I915_RESET_QUIET)) {
2034 dev_notice(engine->i915->drm.dev,
2035 "Resetting %s after gpu hang\n", engine->name);
2036 }
7367612f 2037 error->reset_engine_count[engine->id]++;
a1ef70e1 2038
6acbea89
MT		 2039 if (!engine->i915->guc.execbuf_client)
2040 ret = intel_gt_reset_engine(engine->i915, engine);
2041 else
2042 ret = intel_guc_reset_engine(&engine->i915->guc, engine);
0364cd19
CW		 2043 if (ret) {
2044 /* If we fail here, we expect to fallback to a global reset */
6acbea89
MT		 2045 DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n",
2046 engine->i915->guc.execbuf_client ? "GuC " : "",
0364cd19
CW		 2047 engine->name, ret);
2048 goto out;
2049 }
b4f3e163 2050
a1ef70e1
MT		 2051 /*
2052 * The request that caused the hang is stuck on elsp, we know the
2053 * active request and can drop it, adjust head to skip the offending
2054 * request to resume executing remaining requests in the queue.
2055 */
2056 i915_gem_reset_engine(engine, active_request);
2057
a1ef70e1
MT		 2058 /*
2059 * The engine and its registers (and workarounds in case of render)
2060 * have been reset to their default values. Follow the init_ring
2061 * process to program RING_MODE, HWSP and re-enable submission.
2062 */
2063 ret = engine->init_hw(engine);
702c8f8e
MT		 2064 if (ret)
2065 goto out;
a1ef70e1
MT		 2066
2067out:
0364cd19 2068 i915_gem_reset_finish_engine(engine);
a1ef70e1 2069 return ret;
142bc7d9
MT		 2070}
2071
c49d13ee 2072static int i915_pm_suspend(struct device *kdev)
112b715e 2073{
c49d13ee
DW		 2074 struct pci_dev *pdev = to_pci_dev(kdev);
2075 struct drm_device *dev = pci_get_drvdata(pdev);
112b715e 2076
c49d13ee
DW		 2077 if (!dev) {
2078 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
84b79f8d
RW		 2079 return -ENODEV;
2080 }
112b715e 2081
c49d13ee 2082 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
5bcf719b
DA		 2083 return 0;
2084
c49d13ee 2085 return i915_drm_suspend(dev);
76c4b250
ID		 2086}
2087
c49d13ee 2088static int i915_pm_suspend_late(struct device *kdev)
76c4b250 2089{
c49d13ee 2090 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
76c4b250
ID		 2091
2092 /*
c965d995 2093 * We have a suspend ordering issue with the snd-hda driver also
76c4b250
ID		 2094 * requiring our device to be power up. Due to the lack of a
2095 * parent/child relationship we currently solve this with an late
2096 * suspend hook.
2097 *
2098 * FIXME: This should be solved with a special hdmi sink device or
2099 * similar so that power domains can be employed.
2100 */
c49d13ee 2101 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
76c4b250 2102 return 0;
112b715e 2103
c49d13ee 2104 return i915_drm_suspend_late(dev, false);
ab3be73f
ID		 2105}
2106
c49d13ee 2107static int i915_pm_poweroff_late(struct device *kdev)
ab3be73f 2108{
c49d13ee 2109 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
ab3be73f 2110
c49d13ee 2111 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
ab3be73f
ID		 2112 return 0;
2113
c49d13ee 2114 return i915_drm_suspend_late(dev, true);
cbda12d7
ZW		 2115}
2116
c49d13ee 2117static int i915_pm_resume_early(struct device *kdev)
76c4b250 2118{
c49d13ee 2119 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
76c4b250 2120
c49d13ee 2121 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
097dd837
ID		 2122 return 0;
2123
c49d13ee 2124 return i915_drm_resume_early(dev);
76c4b250
ID		 2125}
2126
c49d13ee 2127static int i915_pm_resume(struct device *kdev)
cbda12d7 2128{
c49d13ee 2129 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
84b79f8d 2130
c49d13ee 2131 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
097dd837
ID		 2132 return 0;
2133
c49d13ee 2134 return i915_drm_resume(dev);
cbda12d7
ZW		 2135}
2136
1f19ac2a 2137/* freeze: before creating the hibernation_image */
c49d13ee 2138static int i915_pm_freeze(struct device *kdev)
1f19ac2a 2139{
dd9f31c7 2140 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
6a800eab
CW		 2141 int ret;
2142
dd9f31c7
ID		 2143 if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2144 ret = i915_drm_suspend(dev);
2145 if (ret)
2146 return ret;
2147 }
6a800eab
CW		 2148
2149 ret = i915_gem_freeze(kdev_to_i915(kdev));
2150 if (ret)
2151 return ret;
2152
2153 return 0;
1f19ac2a
CW		 2154}
2155
c49d13ee 2156static int i915_pm_freeze_late(struct device *kdev)
1f19ac2a 2157{
dd9f31c7 2158 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
461fb99c
CW		 2159 int ret;
2160
dd9f31c7
ID		 2161 if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2162 ret = i915_drm_suspend_late(dev, true);
2163 if (ret)
2164 return ret;
2165 }
461fb99c 2166
c49d13ee 2167 ret = i915_gem_freeze_late(kdev_to_i915(kdev));
461fb99c
CW		 2168 if (ret)
2169 return ret;
2170
2171 return 0;
1f19ac2a
CW		 2172}
2173
2174/* thaw: called after creating the hibernation image, but before turning off. */
c49d13ee 2175static int i915_pm_thaw_early(struct device *kdev)
1f19ac2a 2176{
c49d13ee 2177 return i915_pm_resume_early(kdev);
1f19ac2a
CW		 2178}
2179
c49d13ee 2180static int i915_pm_thaw(struct device *kdev)
1f19ac2a 2181{
c49d13ee 2182 return i915_pm_resume(kdev);
1f19ac2a
CW		 2183}
2184
2185/* restore: called after loading the hibernation image. */
c49d13ee 2186static int i915_pm_restore_early(struct device *kdev)
1f19ac2a 2187{
c49d13ee 2188 return i915_pm_resume_early(kdev);
1f19ac2a
CW		 2189}
2190
c49d13ee 2191static int i915_pm_restore(struct device *kdev)
1f19ac2a 2192{
c49d13ee 2193 return i915_pm_resume(kdev);
1f19ac2a
CW		 2194}
2195
ddeea5b0
ID		 2196/*
2197 * Save all Gunit registers that may be lost after a D3 and a subsequent
2198 * S0i[R123] transition. The list of registers needing a save/restore is
2199 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2200 * registers in the following way:
2201 * - Driver: saved/restored by the driver
2202 * - Punit : saved/restored by the Punit firmware
2203 * - No, w/o marking: no need to save/restore, since the register is R/O or
2204 * used internally by the HW in a way that doesn't depend
2205 * keeping the content across a suspend/resume.
2206 * - Debug : used for debugging
2207 *
2208 * We save/restore all registers marked with 'Driver', with the following
2209 * exceptions:
2210 * - Registers out of use, including also registers marked with 'Debug'.
2211 * These have no effect on the driver's operation, so we don't save/restore
2212 * them to reduce the overhead.
2213 * - Registers that are fully setup by an initialization function called from
2214 * the resume path. For example many clock gating and RPS/RC6 registers.
2215 * - Registers that provide the right functionality with their reset defaults.
2216 *
2217 * TODO: Except for registers that based on the above 3 criteria can be safely
2218 * ignored, we save/restore all others, practically treating the HW context as
2219 * a black-box for the driver. Further investigation is needed to reduce the
2220 * saved/restored registers even further, by following the same 3 criteria.
2221 */
2222static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2223{
2224 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2225 int i;
2226
2227 /* GAM 0x4000-0x4770 */
2228 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
2229 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
2230 s->arb_mode = I915_READ(ARB_MODE);
2231 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
2232 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
2233
2234 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
22dfe79f 2235 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
ddeea5b0
ID		 2236
2237 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
b5f1c97f 2238 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
ddeea5b0
ID		 2239
2240 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
2241 s->ecochk = I915_READ(GAM_ECOCHK);
2242 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
2243 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
2244
2245 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
2246
2247 /* MBC 0x9024-0x91D0, 0x8500 */
2248 s->g3dctl = I915_READ(VLV_G3DCTL);
2249 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
2250 s->mbctl = I915_READ(GEN6_MBCTL);
2251
2252 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2253 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
2254 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
2255 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
2256 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
2257 s->rstctl = I915_READ(GEN6_RSTCTL);
2258 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
2259
2260 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2261 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
2262 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
2263 s->rpdeuc = I915_READ(GEN6_RPDEUC);
2264 s->ecobus = I915_READ(ECOBUS);
2265 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
2266 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2267 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
2268 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
2269 s->rcedata = I915_READ(VLV_RCEDATA);
2270 s->spare2gh = I915_READ(VLV_SPAREG2H);
2271
2272 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2273 s->gt_imr = I915_READ(GTIMR);
2274 s->gt_ier = I915_READ(GTIER);
2275 s->pm_imr = I915_READ(GEN6_PMIMR);
2276 s->pm_ier = I915_READ(GEN6_PMIER);
2277
2278 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
22dfe79f 2279 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
ddeea5b0
ID		 2280
2281 /* GT SA CZ domain, 0x100000-0x138124 */
2282 s->tilectl = I915_READ(TILECTL);
2283 s->gt_fifoctl = I915_READ(GTFIFOCTL);
2284 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
2285 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2286 s->pmwgicz = I915_READ(VLV_PMWGICZ);
2287
2288 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2289 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
2290 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
9c25210f 2291 s->pcbr = I915_READ(VLV_PCBR);
ddeea5b0
ID		 2292 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2293
2294 /*
2295 * Not saving any of:
2296 * DFT, 0x9800-0x9EC0
2297 * SARB, 0xB000-0xB1FC
2298 * GAC, 0x5208-0x524C, 0x14000-0x14C000
2299 * PCI CFG
2300 */
2301}
2302
2303static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2304{
2305 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2306 u32 val;
2307 int i;
2308
2309 /* GAM 0x4000-0x4770 */
2310 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
2311 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
2312 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
2313 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
2314 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
2315
2316 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
22dfe79f 2317 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
ddeea5b0
ID		 2318
2319 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
b5f1c97f 2320 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
ddeea5b0
ID		 2321
2322 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2323 I915_WRITE(GAM_ECOCHK, s->ecochk);
2324 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
2325 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
2326
2327 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
2328
2329 /* MBC 0x9024-0x91D0, 0x8500 */
2330 I915_WRITE(VLV_G3DCTL, s->g3dctl);
2331 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
2332 I915_WRITE(GEN6_MBCTL, s->mbctl);
2333
2334 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2335 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
2336 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
2337 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
2338 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
2339 I915_WRITE(GEN6_RSTCTL, s->rstctl);
2340 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
2341
2342 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2343 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
2344 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
2345 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
2346 I915_WRITE(ECOBUS, s->ecobus);
2347 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
2348 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2349 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
2350 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
2351 I915_WRITE(VLV_RCEDATA, s->rcedata);
2352 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
2353
2354 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2355 I915_WRITE(GTIMR, s->gt_imr);
2356 I915_WRITE(GTIER, s->gt_ier);
2357 I915_WRITE(GEN6_PMIMR, s->pm_imr);
2358 I915_WRITE(GEN6_PMIER, s->pm_ier);
2359
2360 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
22dfe79f 2361 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
ddeea5b0
ID		 2362
2363 /* GT SA CZ domain, 0x100000-0x138124 */
2364 I915_WRITE(TILECTL, s->tilectl);
2365 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
2366 /*
2367 * Preserve the GT allow wake and GFX force clock bit, they are not
2368 * be restored, as they are used to control the s0ix suspend/resume
2369 * sequence by the caller.
2370 */
2371 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2372 val &= VLV_GTLC_ALLOWWAKEREQ;
2373 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2374 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2375
2376 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2377 val &= VLV_GFX_CLK_FORCE_ON_BIT;
2378 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2379 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2380
2381 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
2382
2383 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2384 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
2385 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
9c25210f 2386 I915_WRITE(VLV_PCBR, s->pcbr);
ddeea5b0
ID		 2387 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
2388}
2389
3dd14c04
CW		 2390static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2391 u32 mask, u32 val)
2392{
2393 /* The HW does not like us polling for PW_STATUS frequently, so
2394 * use the sleeping loop rather than risk the busy spin within
2395 * intel_wait_for_register().
2396 *
2397 * Transitioning between RC6 states should be at most 2ms (see
2398 * valleyview_enable_rps) so use a 3ms timeout.
2399 */
2400 return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val,
2401 3);
2402}
2403
650ad970
ID		 2404int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2405{
2406 u32 val;
2407 int err;
2408
650ad970
ID		 2409 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2410 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2411 if (force_on)
2412 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2413 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2414
2415 if (!force_on)
2416 return 0;
2417
c6ddc5f3
CW		 2418 err = intel_wait_for_register(dev_priv,
2419 VLV_GTLC_SURVIVABILITY_REG,
2420 VLV_GFX_CLK_STATUS_BIT,
2421 VLV_GFX_CLK_STATUS_BIT,
2422 20);
650ad970
ID		 2423 if (err)
2424 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2425 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2426
2427 return err;
650ad970
ID		 2428}
2429
ddeea5b0
ID		 2430static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2431{
3dd14c04 2432 u32 mask;
ddeea5b0 2433 u32 val;
3dd14c04 2434 int err;
ddeea5b0
ID		 2435
2436 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2437 val &= ~VLV_GTLC_ALLOWWAKEREQ;
2438 if (allow)
2439 val |= VLV_GTLC_ALLOWWAKEREQ;
2440 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2441 POSTING_READ(VLV_GTLC_WAKE_CTRL);
2442
3dd14c04
CW		 2443 mask = VLV_GTLC_ALLOWWAKEACK;
2444 val = allow ? mask : 0;
2445
2446 err = vlv_wait_for_pw_status(dev_priv, mask, val);
ddeea5b0
ID		 2447 if (err)
2448 DRM_ERROR("timeout disabling GT waking\n");
b2736695 2449
ddeea5b0 2450 return err;
ddeea5b0
ID		 2451}
2452
3dd14c04
CW		 2453static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2454 bool wait_for_on)
ddeea5b0
ID		 2455{
2456 u32 mask;
2457 u32 val;
ddeea5b0
ID		 2458
2459 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2460 val = wait_for_on ? mask : 0;
ddeea5b0
ID		 2461
2462 /*
2463 * RC6 transitioning can be delayed up to 2 msec (see
2464 * valleyview_enable_rps), use 3 msec for safety.
2465 */
3dd14c04 2466 if (vlv_wait_for_pw_status(dev_priv, mask, val))
ddeea5b0 2467 DRM_ERROR("timeout waiting for GT wells to go %s\n",
87ad3212 2468 onoff(wait_for_on));
ddeea5b0
ID		 2469}
2470
2471static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2472{
2473 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2474 return;
2475
6fa283b0 2476 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
ddeea5b0
ID		 2477 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2478}
2479
ebc32824 2480static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
ddeea5b0
ID		 2481{
2482 u32 mask;
2483 int err;
2484
2485 /*
2486 * Bspec defines the following GT well on flags as debug only, so
2487 * don't treat them as hard failures.
2488 */
3dd14c04 2489 vlv_wait_for_gt_wells(dev_priv, false);
ddeea5b0
ID		 2490
2491 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2492 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2493
2494 vlv_check_no_gt_access(dev_priv);
2495
2496 err = vlv_force_gfx_clock(dev_priv, true);
2497 if (err)
2498 goto err1;
2499
2500 err = vlv_allow_gt_wake(dev_priv, false);
2501 if (err)
2502 goto err2;
98711167 2503
2d1fe073 2504 if (!IS_CHERRYVIEW(dev_priv))
98711167 2505 vlv_save_gunit_s0ix_state(dev_priv);
ddeea5b0
ID		 2506
2507 err = vlv_force_gfx_clock(dev_priv, false);
2508 if (err)
2509 goto err2;
2510
2511 return 0;
2512
2513err2:
2514 /* For safety always re-enable waking and disable gfx clock forcing */
2515 vlv_allow_gt_wake(dev_priv, true);
2516err1:
2517 vlv_force_gfx_clock(dev_priv, false);
2518
2519 return err;
2520}
2521
016970be
SK		 2522static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2523 bool rpm_resume)
ddeea5b0 2524{
ddeea5b0
ID		 2525 int err;
2526 int ret;
2527
2528 /*
2529 * If any of the steps fail just try to continue, that's the best we
2530 * can do at this point. Return the first error code (which will also
2531 * leave RPM permanently disabled).
2532 */
2533 ret = vlv_force_gfx_clock(dev_priv, true);
2534
2d1fe073 2535 if (!IS_CHERRYVIEW(dev_priv))
98711167 2536 vlv_restore_gunit_s0ix_state(dev_priv);
ddeea5b0
ID		 2537
2538 err = vlv_allow_gt_wake(dev_priv, true);
2539 if (!ret)
2540 ret = err;
2541
2542 err = vlv_force_gfx_clock(dev_priv, false);
2543 if (!ret)
2544 ret = err;
2545
2546 vlv_check_no_gt_access(dev_priv);
2547
7c108fd8 2548 if (rpm_resume)
46f16e63 2549 intel_init_clock_gating(dev_priv);
ddeea5b0
ID		 2550
2551 return ret;
2552}
2553
c49d13ee 2554static int intel_runtime_suspend(struct device *kdev)
8a187455 2555{
c49d13ee 2556 struct pci_dev *pdev = to_pci_dev(kdev);
8a187455 2557 struct drm_device *dev = pci_get_drvdata(pdev);
fac5e23e 2558 struct drm_i915_private *dev_priv = to_i915(dev);
0ab9cfeb 2559 int ret;
8a187455 2560
fb6db0f5 2561 if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv))))
c6df39b5
ID		 2562 return -ENODEV;
2563
6772ffe0 2564 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
604effb7
ID		 2565 return -ENODEV;
2566
8a187455
PZ		 2567 DRM_DEBUG_KMS("Suspending device\n");
2568
1f814dac
ID		 2569 disable_rpm_wakeref_asserts(dev_priv);
2570
d6102977
ID		 2571 /*
2572 * We are safe here against re-faults, since the fault handler takes
2573 * an RPM reference.
2574 */
7c108fd8 2575 i915_gem_runtime_suspend(dev_priv);
d6102977 2576
bf9e8429 2577 intel_guc_suspend(dev_priv);
a1c41994 2578
2eb5252e 2579 intel_runtime_pm_disable_interrupts(dev_priv);
b5478bcd 2580
01c799c9
HG		 2581 intel_uncore_suspend(dev_priv);
2582
507e126e 2583 ret = 0;
b9fd799e 2584 if (IS_GEN9_LP(dev_priv)) {
507e126e
ID		 2585 bxt_display_core_uninit(dev_priv);
2586 bxt_enable_dc9(dev_priv);
2587 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2588 hsw_enable_pc8(dev_priv);
2589 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2590 ret = vlv_suspend_complete(dev_priv);
2591 }
2592
0ab9cfeb
ID		 2593 if (ret) {
2594 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
01c799c9
HG		 2595 intel_uncore_runtime_resume(dev_priv);
2596
b963291c 2597 intel_runtime_pm_enable_interrupts(dev_priv);
0ab9cfeb 2598
1f814dac
ID		 2599 enable_rpm_wakeref_asserts(dev_priv);
2600
0ab9cfeb
ID		 2601 return ret;
2602 }
a8a8bd54 2603
1f814dac 2604 enable_rpm_wakeref_asserts(dev_priv);
ad1443f0 2605 WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
55ec45c2 2606
bc3b9346 2607 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
55ec45c2
MK		 2608 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2609
ad1443f0 2610 dev_priv->runtime_pm.suspended = true;
1fb2362b
KCA		 2611
2612 /*
c8a0bd42
PZ		 2613 * FIXME: We really should find a document that references the arguments
2614 * used below!
1fb2362b 2615 */
6f9f4b7a 2616 if (IS_BROADWELL(dev_priv)) {
d37ae19a
PZ		 2617 /*
2618 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2619 * being detected, and the call we do at intel_runtime_resume()
2620 * won't be able to restore them. Since PCI_D3hot matches the
2621 * actual specification and appears to be working, use it.
2622 */
6f9f4b7a 2623 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
d37ae19a 2624 } else {
c8a0bd42
PZ		 2625 /*
2626 * current versions of firmware which depend on this opregion
2627 * notification have repurposed the D1 definition to mean
2628 * "runtime suspended" vs. what you would normally expect (D3)
2629 * to distinguish it from notifications that might be sent via
2630 * the suspend path.
2631 */
6f9f4b7a 2632 intel_opregion_notify_adapter(dev_priv, PCI_D1);
c8a0bd42 2633 }
8a187455 2634
59bad947 2635 assert_forcewakes_inactive(dev_priv);
dc9fb09c 2636
21d6e0bd 2637 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
19625e85
L		 2638 intel_hpd_poll_init(dev_priv);
2639
a8a8bd54 2640 DRM_DEBUG_KMS("Device suspended\n");
8a187455
PZ		 2641 return 0;
2642}
2643
c49d13ee 2644static int intel_runtime_resume(struct device *kdev)
8a187455 2645{
c49d13ee 2646 struct pci_dev *pdev = to_pci_dev(kdev);
8a187455 2647 struct drm_device *dev = pci_get_drvdata(pdev);
fac5e23e 2648 struct drm_i915_private *dev_priv = to_i915(dev);
1a5df187 2649 int ret = 0;
8a187455 2650
6772ffe0 2651 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
604effb7 2652 return -ENODEV;
8a187455
PZ		 2653
2654 DRM_DEBUG_KMS("Resuming device\n");
2655
ad1443f0 2656 WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
1f814dac
ID		 2657 disable_rpm_wakeref_asserts(dev_priv);
2658
6f9f4b7a 2659 intel_opregion_notify_adapter(dev_priv, PCI_D0);
ad1443f0 2660 dev_priv->runtime_pm.suspended = false;
55ec45c2
MK		 2661 if (intel_uncore_unclaimed_mmio(dev_priv))
2662 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
8a187455 2663
bf9e8429 2664 intel_guc_resume(dev_priv);
a1c41994 2665
b9fd799e 2666 if (IS_GEN9_LP(dev_priv)) {
507e126e
ID		 2667 bxt_disable_dc9(dev_priv);
2668 bxt_display_core_init(dev_priv, true);
f62c79b3
ID		 2669 if (dev_priv->csr.dmc_payload &&
2670 (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2671 gen9_enable_dc5(dev_priv);
507e126e 2672 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1a5df187 2673 hsw_disable_pc8(dev_priv);
507e126e 2674 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1a5df187 2675 ret = vlv_resume_prepare(dev_priv, true);
507e126e 2676 }
1a5df187 2677
bedf4d79
HG		 2678 intel_uncore_runtime_resume(dev_priv);
2679
0ab9cfeb
ID		 2680 /*
2681 * No point of rolling back things in case of an error, as the best
2682 * we can do is to hope that things will still work (and disable RPM).
2683 */
c6be607a 2684 i915_gem_init_swizzling(dev_priv);
83bf6d55 2685 i915_gem_restore_fences(dev_priv);
92b806d3 2686
b963291c 2687 intel_runtime_pm_enable_interrupts(dev_priv);
08d8a232
VS		 2688
2689 /*
2690 * On VLV/CHV display interrupts are part of the display
2691 * power well, so hpd is reinitialized from there. For
2692 * everyone else do it here.
2693 */
666a4537 2694 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
08d8a232
VS		 2695 intel_hpd_init(dev_priv);
2696
2503a0fe
KM		 2697 intel_enable_ipc(dev_priv);
2698
1f814dac
ID		 2699 enable_rpm_wakeref_asserts(dev_priv);
2700
0ab9cfeb
ID		 2701 if (ret)
2702 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2703 else
2704 DRM_DEBUG_KMS("Device resumed\n");
2705
2706 return ret;
8a187455
PZ		 2707}
2708
42f5551d 2709const struct dev_pm_ops i915_pm_ops = {
5545dbbf
ID		 2710 /*
2711 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2712 * PMSG_RESUME]
2713 */
0206e353 2714 .suspend = i915_pm_suspend,
76c4b250
ID		 2715 .suspend_late = i915_pm_suspend_late,
2716 .resume_early = i915_pm_resume_early,
0206e353 2717 .resume = i915_pm_resume,
5545dbbf
ID		 2718
2719 /*
2720 * S4 event handlers
2721 * @freeze, @freeze_late : called (1) before creating the
2722 * hibernation image [PMSG_FREEZE] and
2723 * (2) after rebooting, before restoring
2724 * the image [PMSG_QUIESCE]
2725 * @thaw, @thaw_early : called (1) after creating the hibernation
2726 * image, before writing it [PMSG_THAW]
2727 * and (2) after failing to create or
2728 * restore the image [PMSG_RECOVER]
2729 * @poweroff, @poweroff_late: called after writing the hibernation
2730 * image, before rebooting [PMSG_HIBERNATE]
2731 * @restore, @restore_early : called after rebooting and restoring the
2732 * hibernation image [PMSG_RESTORE]
2733 */
1f19ac2a
CW		 2734 .freeze = i915_pm_freeze,
2735 .freeze_late = i915_pm_freeze_late,
2736 .thaw_early = i915_pm_thaw_early,
2737 .thaw = i915_pm_thaw,
36d61e67 2738 .poweroff = i915_pm_suspend,
ab3be73f 2739 .poweroff_late = i915_pm_poweroff_late,
1f19ac2a
CW		 2740 .restore_early = i915_pm_restore_early,
2741 .restore = i915_pm_restore,
5545dbbf
ID		 2742
2743 /* S0ix (via runtime suspend) event handlers */
97bea207
PZ		 2744 .runtime_suspend = intel_runtime_suspend,
2745 .runtime_resume = intel_runtime_resume,
cbda12d7
ZW		 2746};
2747
78b68556 2748static const struct vm_operations_struct i915_gem_vm_ops = {
de151cf6 2749 .fault = i915_gem_fault,
ab00b3e5
JB		 2750 .open = drm_gem_vm_open,
2751 .close = drm_gem_vm_close,
de151cf6
JB		 2752};
2753
e08e96de
AV		 2754static const struct file_operations i915_driver_fops = {
2755 .owner = THIS_MODULE,
2756 .open = drm_open,
2757 .release = drm_release,
2758 .unlocked_ioctl = drm_ioctl,
2759 .mmap = drm_gem_mmap,
2760 .poll = drm_poll,
e08e96de 2761 .read = drm_read,
e08e96de 2762 .compat_ioctl = i915_compat_ioctl,
e08e96de
AV		 2763 .llseek = noop_llseek,
2764};
2765
0673ad47
CW		 2766static int
2767i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2768 struct drm_file *file)
2769{
2770 return -ENODEV;
2771}
2772
2773static const struct drm_ioctl_desc i915_ioctls[] = {
2774 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2775 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2776 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2777 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2778 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2779 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2780 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2781 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2782 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2783 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2784 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2785 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2786 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2787 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2788 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
2789 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2790 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2791 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2792 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
fec0445c 2793 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
0673ad47
CW		 2794 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2795 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2796 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2797 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2798 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2799 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2800 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2801 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2802 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2803 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2804 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2805 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2806 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2807 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2808 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
111dbcab
CW		 2809 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2810 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
0673ad47
CW		 2811 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2812 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2813 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2814 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2815 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2816 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2817 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2818 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2819 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2820 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2821 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2822 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2823 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2824 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2825 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
eec688e1 2826 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
f89823c2
LL		 2827 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2828 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
0673ad47
CW		 2829};
2830
1da177e4 2831static struct drm_driver driver = {
0c54781b
MW		 2832 /* Don't use MTRRs here; the Xserver or userspace app should
2833 * deal with them for Intel hardware.
792d2b9a 2834 */
673a394b 2835 .driver_features =
10ba5012 2836 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
cf6e7bac 2837 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
cad3688f 2838 .release = i915_driver_release,
673a394b 2839 .open = i915_driver_open,
22eae947 2840 .lastclose = i915_driver_lastclose,
673a394b 2841 .postclose = i915_driver_postclose,
d8e29209 2842
b1f788c6 2843 .gem_close_object = i915_gem_close_object,
f0cd5182 2844 .gem_free_object_unlocked = i915_gem_free_object,
de151cf6 2845 .gem_vm_ops = &i915_gem_vm_ops,
1286ff73
DV		 2846
2847 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2848 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2849 .gem_prime_export = i915_gem_prime_export,
2850 .gem_prime_import = i915_gem_prime_import,
2851
ff72145b 2852 .dumb_create = i915_gem_dumb_create,
da6b51d0 2853 .dumb_map_offset = i915_gem_mmap_gtt,
1da177e4 2854 .ioctls = i915_ioctls,
0673ad47 2855 .num_ioctls = ARRAY_SIZE(i915_ioctls),
e08e96de 2856 .fops = &i915_driver_fops,
22eae947
DA		 2857 .name = DRIVER_NAME,
2858 .desc = DRIVER_DESC,
2859 .date = DRIVER_DATE,
2860 .major = DRIVER_MAJOR,
2861 .minor = DRIVER_MINOR,
2862 .patchlevel = DRIVER_PATCHLEVEL,
1da177e4 2863};
66d9cb5d
CW		 2864
2865#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2866#include "selftests/mock_drm.c"
2867#endif
Linux 6.x block layer and io_uring tree(s)