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1da177e4 LT |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 | 29 | |
e5747e3a | 30 | #include <linux/acpi.h> |
0673ad47 CW |
31 | #include <linux/device.h> |
32 | #include <linux/oom.h> | |
e0cd3608 | 33 | #include <linux/module.h> |
0673ad47 CW |
34 | #include <linux/pci.h> |
35 | #include <linux/pm.h> | |
d6102977 | 36 | #include <linux/pm_runtime.h> |
0673ad47 CW |
37 | #include <linux/pnp.h> |
38 | #include <linux/slab.h> | |
39 | #include <linux/vgaarb.h> | |
704ab614 | 40 | #include <linux/vga_switcheroo.h> |
0673ad47 CW |
41 | #include <linux/vt.h> |
42 | #include <acpi/video.h> | |
43 | ||
a667fb40 | 44 | #include <drm/drm_atomic_helper.h> |
d0e93599 SR |
45 | #include <drm/drm_ioctl.h> |
46 | #include <drm/drm_irq.h> | |
47 | #include <drm/drm_probe_helper.h> | |
0673ad47 CW |
48 | #include <drm/i915_drm.h> |
49 | ||
df0566a6 JN |
50 | #include "display/intel_acpi.h" |
51 | #include "display/intel_audio.h" | |
52 | #include "display/intel_bw.h" | |
53 | #include "display/intel_cdclk.h" | |
379bc100 | 54 | #include "display/intel_dp.h" |
df0566a6 | 55 | #include "display/intel_fbdev.h" |
379bc100 | 56 | #include "display/intel_gmbus.h" |
df0566a6 JN |
57 | #include "display/intel_hotplug.h" |
58 | #include "display/intel_overlay.h" | |
59 | #include "display/intel_pipe_crc.h" | |
60 | #include "display/intel_sprite.h" | |
379bc100 | 61 | |
10be98a7 | 62 | #include "gem/i915_gem_context.h" |
afa13085 | 63 | #include "gem/i915_gem_ioctls.h" |
24635c51 | 64 | #include "gt/intel_gt.h" |
79ffac85 | 65 | #include "gt/intel_gt_pm.h" |
112ed2d3 | 66 | #include "gt/intel_reset.h" |
79ffac85 | 67 | #include "gt/intel_workarounds.h" |
0f261b24 | 68 | #include "gt/uc/intel_uc.h" |
112ed2d3 | 69 | |
2126d3e9 | 70 | #include "i915_debugfs.h" |
0673ad47 | 71 | #include "i915_drv.h" |
440e2b3d | 72 | #include "i915_irq.h" |
b46a33e2 | 73 | #include "i915_pmu.h" |
a446ae2c | 74 | #include "i915_query.h" |
331c201a | 75 | #include "i915_trace.h" |
0673ad47 | 76 | #include "i915_vgpu.h" |
174594db | 77 | #include "intel_csr.h" |
0673ad47 | 78 | #include "intel_drv.h" |
696173b0 | 79 | #include "intel_pm.h" |
79e53945 | 80 | |
112b715e KH |
81 | static struct drm_driver driver; |
82 | ||
fae919f0 | 83 | #if IS_ENABLED(CONFIG_DRM_I915_DEBUG) |
f2db53f1 | 84 | static unsigned int i915_probe_fail_count; |
0673ad47 | 85 | |
f2db53f1 | 86 | bool __i915_inject_probe_failure(const char *func, int line) |
0673ad47 | 87 | { |
f2db53f1 | 88 | if (i915_probe_fail_count >= i915_modparams.inject_load_failure) |
0673ad47 CW |
89 | return false; |
90 | ||
f2db53f1 | 91 | if (++i915_probe_fail_count == i915_modparams.inject_load_failure) { |
0673ad47 | 92 | DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n", |
4f044a88 | 93 | i915_modparams.inject_load_failure, func, line); |
cf68f0c3 | 94 | i915_modparams.inject_load_failure = 0; |
0673ad47 CW |
95 | return true; |
96 | } | |
97 | ||
98 | return false; | |
99 | } | |
51c18bf7 CW |
100 | |
101 | bool i915_error_injected(void) | |
102 | { | |
f2db53f1 | 103 | return i915_probe_fail_count && !i915_modparams.inject_load_failure; |
51c18bf7 CW |
104 | } |
105 | ||
fae919f0 | 106 | #endif |
0673ad47 CW |
107 | |
108 | #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI" | |
109 | #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \ | |
110 | "providing the dmesg log by booting with drm.debug=0xf" | |
111 | ||
112 | void | |
113 | __i915_printk(struct drm_i915_private *dev_priv, const char *level, | |
114 | const char *fmt, ...) | |
115 | { | |
116 | static bool shown_bug_once; | |
c49d13ee | 117 | struct device *kdev = dev_priv->drm.dev; |
0673ad47 CW |
118 | bool is_error = level[1] <= KERN_ERR[1]; |
119 | bool is_debug = level[1] == KERN_DEBUG[1]; | |
120 | struct va_format vaf; | |
121 | va_list args; | |
122 | ||
123 | if (is_debug && !(drm_debug & DRM_UT_DRIVER)) | |
124 | return; | |
125 | ||
126 | va_start(args, fmt); | |
127 | ||
128 | vaf.fmt = fmt; | |
129 | vaf.va = &args; | |
130 | ||
8cff1f4a CW |
131 | if (is_error) |
132 | dev_printk(level, kdev, "%pV", &vaf); | |
133 | else | |
134 | dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV", | |
135 | __builtin_return_address(0), &vaf); | |
136 | ||
137 | va_end(args); | |
0673ad47 CW |
138 | |
139 | if (is_error && !shown_bug_once) { | |
4e8507ba CW |
140 | /* |
141 | * Ask the user to file a bug report for the error, except | |
142 | * if they may have caused the bug by fiddling with unsafe | |
143 | * module parameters. | |
144 | */ | |
145 | if (!test_taint(TAINT_USER)) | |
146 | dev_notice(kdev, "%s", FDO_BUG_MSG); | |
0673ad47 CW |
147 | shown_bug_once = true; |
148 | } | |
0673ad47 CW |
149 | } |
150 | ||
da6c10c2 JN |
151 | /* Map PCH device id to PCH type, or PCH_NONE if unknown. */ |
152 | static enum intel_pch | |
153 | intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) | |
154 | { | |
155 | switch (id) { | |
156 | case INTEL_PCH_IBX_DEVICE_ID_TYPE: | |
157 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); | |
cf819eff | 158 | WARN_ON(!IS_GEN(dev_priv, 5)); |
da6c10c2 JN |
159 | return PCH_IBX; |
160 | case INTEL_PCH_CPT_DEVICE_ID_TYPE: | |
161 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); | |
cf819eff | 162 | WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv)); |
da6c10c2 JN |
163 | return PCH_CPT; |
164 | case INTEL_PCH_PPT_DEVICE_ID_TYPE: | |
165 | DRM_DEBUG_KMS("Found PantherPoint PCH\n"); | |
cf819eff | 166 | WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv)); |
da6c10c2 JN |
167 | /* PantherPoint is CPT compatible */ |
168 | return PCH_CPT; | |
169 | case INTEL_PCH_LPT_DEVICE_ID_TYPE: | |
170 | DRM_DEBUG_KMS("Found LynxPoint PCH\n"); | |
171 | WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); | |
172 | WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)); | |
173 | return PCH_LPT; | |
174 | case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE: | |
175 | DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); | |
176 | WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); | |
177 | WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv)); | |
178 | return PCH_LPT; | |
179 | case INTEL_PCH_WPT_DEVICE_ID_TYPE: | |
180 | DRM_DEBUG_KMS("Found WildcatPoint PCH\n"); | |
181 | WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); | |
182 | WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)); | |
183 | /* WildcatPoint is LPT compatible */ | |
184 | return PCH_LPT; | |
185 | case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE: | |
186 | DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n"); | |
187 | WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); | |
188 | WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv)); | |
189 | /* WildcatPoint is LPT compatible */ | |
190 | return PCH_LPT; | |
191 | case INTEL_PCH_SPT_DEVICE_ID_TYPE: | |
192 | DRM_DEBUG_KMS("Found SunrisePoint PCH\n"); | |
193 | WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv)); | |
194 | return PCH_SPT; | |
195 | case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE: | |
196 | DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n"); | |
197 | WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv)); | |
198 | return PCH_SPT; | |
199 | case INTEL_PCH_KBP_DEVICE_ID_TYPE: | |
200 | DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n"); | |
201 | WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) && | |
202 | !IS_COFFEELAKE(dev_priv)); | |
9ab91a30 VS |
203 | /* KBP is SPT compatible */ |
204 | return PCH_SPT; | |
da6c10c2 JN |
205 | case INTEL_PCH_CNP_DEVICE_ID_TYPE: |
206 | DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n"); | |
207 | WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv)); | |
208 | return PCH_CNP; | |
209 | case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE: | |
210 | DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n"); | |
211 | WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv)); | |
212 | return PCH_CNP; | |
729ae330 AS |
213 | case INTEL_PCH_CMP_DEVICE_ID_TYPE: |
214 | DRM_DEBUG_KMS("Found Comet Lake PCH (CMP)\n"); | |
215 | WARN_ON(!IS_COFFEELAKE(dev_priv)); | |
216 | /* CometPoint is CNP Compatible */ | |
217 | return PCH_CNP; | |
da6c10c2 JN |
218 | case INTEL_PCH_ICP_DEVICE_ID_TYPE: |
219 | DRM_DEBUG_KMS("Found Ice Lake PCH\n"); | |
220 | WARN_ON(!IS_ICELAKE(dev_priv)); | |
221 | return PCH_ICP; | |
c6f7acb8 | 222 | case INTEL_PCH_MCC_DEVICE_ID_TYPE: |
fc25441c | 223 | case INTEL_PCH_MCC2_DEVICE_ID_TYPE: |
c6f7acb8 MR |
224 | DRM_DEBUG_KMS("Found Mule Creek Canyon PCH\n"); |
225 | WARN_ON(!IS_ELKHARTLAKE(dev_priv)); | |
226 | return PCH_MCC; | |
7f028892 RS |
227 | case INTEL_PCH_TGP_DEVICE_ID_TYPE: |
228 | DRM_DEBUG_KMS("Found Tiger Lake LP PCH\n"); | |
229 | WARN_ON(!IS_TIGERLAKE(dev_priv)); | |
230 | return PCH_TGP; | |
da6c10c2 JN |
231 | default: |
232 | return PCH_NONE; | |
233 | } | |
234 | } | |
0673ad47 | 235 | |
435ad2c0 JN |
236 | static bool intel_is_virt_pch(unsigned short id, |
237 | unsigned short svendor, unsigned short sdevice) | |
238 | { | |
239 | return (id == INTEL_PCH_P2X_DEVICE_ID_TYPE || | |
240 | id == INTEL_PCH_P3X_DEVICE_ID_TYPE || | |
241 | (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE && | |
242 | svendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET && | |
243 | sdevice == PCI_SUBDEVICE_ID_QEMU)); | |
244 | } | |
245 | ||
40ace64b JN |
246 | static unsigned short |
247 | intel_virt_detect_pch(const struct drm_i915_private *dev_priv) | |
0673ad47 | 248 | { |
40ace64b | 249 | unsigned short id = 0; |
0673ad47 CW |
250 | |
251 | /* | |
252 | * In a virtualized passthrough environment we can be in a | |
253 | * setup where the ISA bridge is not able to be passed through. | |
254 | * In this case, a south bridge can be emulated and we have to | |
255 | * make an educated guess as to which PCH is really there. | |
256 | */ | |
257 | ||
d8df6bec MK |
258 | if (IS_TIGERLAKE(dev_priv)) |
259 | id = INTEL_PCH_TGP_DEVICE_ID_TYPE; | |
260 | else if (IS_ELKHARTLAKE(dev_priv)) | |
c6f7acb8 MR |
261 | id = INTEL_PCH_MCC_DEVICE_ID_TYPE; |
262 | else if (IS_ICELAKE(dev_priv)) | |
993298af RV |
263 | id = INTEL_PCH_ICP_DEVICE_ID_TYPE; |
264 | else if (IS_CANNONLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) | |
265 | id = INTEL_PCH_CNP_DEVICE_ID_TYPE; | |
266 | else if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv)) | |
267 | id = INTEL_PCH_SPT_DEVICE_ID_TYPE; | |
40ace64b JN |
268 | else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) |
269 | id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE; | |
270 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
271 | id = INTEL_PCH_LPT_DEVICE_ID_TYPE; | |
993298af RV |
272 | else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) |
273 | id = INTEL_PCH_CPT_DEVICE_ID_TYPE; | |
274 | else if (IS_GEN(dev_priv, 5)) | |
275 | id = INTEL_PCH_IBX_DEVICE_ID_TYPE; | |
40ace64b JN |
276 | |
277 | if (id) | |
278 | DRM_DEBUG_KMS("Assuming PCH ID %04x\n", id); | |
279 | else | |
280 | DRM_DEBUG_KMS("Assuming no PCH\n"); | |
281 | ||
282 | return id; | |
0673ad47 CW |
283 | } |
284 | ||
da5f53bf | 285 | static void intel_detect_pch(struct drm_i915_private *dev_priv) |
0673ad47 | 286 | { |
0673ad47 CW |
287 | struct pci_dev *pch = NULL; |
288 | ||
0673ad47 CW |
289 | /* |
290 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to | |
291 | * make graphics device passthrough work easy for VMM, that only | |
292 | * need to expose ISA bridge to let driver know the real hardware | |
293 | * underneath. This is a requirement from virtualization team. | |
294 | * | |
295 | * In some virtualized environments (e.g. XEN), there is irrelevant | |
296 | * ISA bridge in the system. To work reliably, we should scan trhough | |
297 | * all the ISA bridge devices and check for the first match, instead | |
298 | * of only checking the first one. | |
299 | */ | |
300 | while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) { | |
d67c0ac1 | 301 | unsigned short id; |
da6c10c2 | 302 | enum intel_pch pch_type; |
d67c0ac1 JN |
303 | |
304 | if (pch->vendor != PCI_VENDOR_ID_INTEL) | |
305 | continue; | |
306 | ||
307 | id = pch->device & INTEL_PCH_DEVICE_ID_MASK; | |
308 | ||
da6c10c2 JN |
309 | pch_type = intel_pch_type(dev_priv, id); |
310 | if (pch_type != PCH_NONE) { | |
311 | dev_priv->pch_type = pch_type; | |
40ace64b JN |
312 | dev_priv->pch_id = id; |
313 | break; | |
435ad2c0 | 314 | } else if (intel_is_virt_pch(id, pch->subsystem_vendor, |
40ace64b JN |
315 | pch->subsystem_device)) { |
316 | id = intel_virt_detect_pch(dev_priv); | |
85b17e6e JN |
317 | pch_type = intel_pch_type(dev_priv, id); |
318 | ||
319 | /* Sanity check virtual PCH id */ | |
320 | if (WARN_ON(id && pch_type == PCH_NONE)) | |
321 | id = 0; | |
322 | ||
40ace64b JN |
323 | dev_priv->pch_type = pch_type; |
324 | dev_priv->pch_id = id; | |
325 | break; | |
0673ad47 CW |
326 | } |
327 | } | |
07ba0a82 JN |
328 | |
329 | /* | |
330 | * Use PCH_NOP (PCH but no South Display) for PCH platforms without | |
331 | * display. | |
332 | */ | |
e1bf094b | 333 | if (pch && !HAS_DISPLAY(dev_priv)) { |
07ba0a82 JN |
334 | DRM_DEBUG_KMS("Display disabled, reverting to NOP PCH\n"); |
335 | dev_priv->pch_type = PCH_NOP; | |
336 | dev_priv->pch_id = 0; | |
337 | } | |
338 | ||
0673ad47 CW |
339 | if (!pch) |
340 | DRM_DEBUG_KMS("No PCH found.\n"); | |
341 | ||
342 | pci_dev_put(pch); | |
343 | } | |
344 | ||
6a20fe7b VS |
345 | static int i915_getparam_ioctl(struct drm_device *dev, void *data, |
346 | struct drm_file *file_priv) | |
0673ad47 | 347 | { |
fac5e23e | 348 | struct drm_i915_private *dev_priv = to_i915(dev); |
52a05c30 | 349 | struct pci_dev *pdev = dev_priv->drm.pdev; |
bd41ca49 | 350 | const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; |
0673ad47 | 351 | drm_i915_getparam_t *param = data; |
a10f361d | 352 | int value; |
0673ad47 CW |
353 | |
354 | switch (param->param) { | |
355 | case I915_PARAM_IRQ_ACTIVE: | |
356 | case I915_PARAM_ALLOW_BATCHBUFFER: | |
357 | case I915_PARAM_LAST_DISPATCH: | |
ef0f411f | 358 | case I915_PARAM_HAS_EXEC_CONSTANTS: |
0673ad47 CW |
359 | /* Reject all old ums/dri params. */ |
360 | return -ENODEV; | |
361 | case I915_PARAM_CHIPSET_ID: | |
52a05c30 | 362 | value = pdev->device; |
0673ad47 CW |
363 | break; |
364 | case I915_PARAM_REVISION: | |
52a05c30 | 365 | value = pdev->revision; |
0673ad47 | 366 | break; |
0673ad47 | 367 | case I915_PARAM_NUM_FENCES_AVAIL: |
0cf289bd | 368 | value = dev_priv->ggtt.num_fences; |
0673ad47 CW |
369 | break; |
370 | case I915_PARAM_HAS_OVERLAY: | |
371 | value = dev_priv->overlay ? 1 : 0; | |
372 | break; | |
0673ad47 | 373 | case I915_PARAM_HAS_BSD: |
8a68d464 | 374 | value = !!dev_priv->engine[VCS0]; |
0673ad47 CW |
375 | break; |
376 | case I915_PARAM_HAS_BLT: | |
8a68d464 | 377 | value = !!dev_priv->engine[BCS0]; |
0673ad47 CW |
378 | break; |
379 | case I915_PARAM_HAS_VEBOX: | |
8a68d464 | 380 | value = !!dev_priv->engine[VECS0]; |
0673ad47 CW |
381 | break; |
382 | case I915_PARAM_HAS_BSD2: | |
8a68d464 | 383 | value = !!dev_priv->engine[VCS1]; |
0673ad47 | 384 | break; |
0673ad47 | 385 | case I915_PARAM_HAS_LLC: |
16162470 | 386 | value = HAS_LLC(dev_priv); |
0673ad47 CW |
387 | break; |
388 | case I915_PARAM_HAS_WT: | |
16162470 | 389 | value = HAS_WT(dev_priv); |
0673ad47 CW |
390 | break; |
391 | case I915_PARAM_HAS_ALIASING_PPGTT: | |
51d623b6 | 392 | value = INTEL_PPGTT(dev_priv); |
0673ad47 CW |
393 | break; |
394 | case I915_PARAM_HAS_SEMAPHORES: | |
e8861964 | 395 | value = !!(dev_priv->caps.scheduler & I915_SCHEDULER_CAP_SEMAPHORES); |
0673ad47 | 396 | break; |
0673ad47 CW |
397 | case I915_PARAM_HAS_SECURE_BATCHES: |
398 | value = capable(CAP_SYS_ADMIN); | |
399 | break; | |
0673ad47 CW |
400 | case I915_PARAM_CMD_PARSER_VERSION: |
401 | value = i915_cmd_parser_get_version(dev_priv); | |
402 | break; | |
0673ad47 | 403 | case I915_PARAM_SUBSLICE_TOTAL: |
0040fd19 | 404 | value = intel_sseu_subslice_total(sseu); |
0673ad47 CW |
405 | if (!value) |
406 | return -ENODEV; | |
407 | break; | |
408 | case I915_PARAM_EU_TOTAL: | |
bd41ca49 | 409 | value = sseu->eu_total; |
0673ad47 CW |
410 | if (!value) |
411 | return -ENODEV; | |
412 | break; | |
413 | case I915_PARAM_HAS_GPU_RESET: | |
4f044a88 MW |
414 | value = i915_modparams.enable_hangcheck && |
415 | intel_has_gpu_reset(dev_priv); | |
142bc7d9 MT |
416 | if (value && intel_has_reset_engine(dev_priv)) |
417 | value = 2; | |
0673ad47 CW |
418 | break; |
419 | case I915_PARAM_HAS_RESOURCE_STREAMER: | |
08e3e21a | 420 | value = 0; |
0673ad47 | 421 | break; |
37f501af | 422 | case I915_PARAM_HAS_POOLED_EU: |
16162470 | 423 | value = HAS_POOLED_EU(dev_priv); |
37f501af | 424 | break; |
425 | case I915_PARAM_MIN_EU_IN_POOL: | |
bd41ca49 | 426 | value = sseu->min_eu_in_pool; |
37f501af | 427 | break; |
5464cd65 | 428 | case I915_PARAM_HUC_STATUS: |
8b5689d7 | 429 | value = intel_huc_check_status(&dev_priv->gt.uc.huc); |
fa265275 MW |
430 | if (value < 0) |
431 | return value; | |
5464cd65 | 432 | break; |
4cc69075 CW |
433 | case I915_PARAM_MMAP_GTT_VERSION: |
434 | /* Though we've started our numbering from 1, and so class all | |
435 | * earlier versions as 0, in effect their value is undefined as | |
436 | * the ioctl will report EINVAL for the unknown param! | |
437 | */ | |
438 | value = i915_gem_mmap_gtt_version(); | |
439 | break; | |
0de9136d | 440 | case I915_PARAM_HAS_SCHEDULER: |
3fed1808 | 441 | value = dev_priv->caps.scheduler; |
0de9136d | 442 | break; |
beecec90 | 443 | |
16162470 DW |
444 | case I915_PARAM_MMAP_VERSION: |
445 | /* Remember to bump this if the version changes! */ | |
446 | case I915_PARAM_HAS_GEM: | |
447 | case I915_PARAM_HAS_PAGEFLIPPING: | |
448 | case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */ | |
449 | case I915_PARAM_HAS_RELAXED_FENCING: | |
450 | case I915_PARAM_HAS_COHERENT_RINGS: | |
451 | case I915_PARAM_HAS_RELAXED_DELTA: | |
452 | case I915_PARAM_HAS_GEN7_SOL_RESET: | |
453 | case I915_PARAM_HAS_WAIT_TIMEOUT: | |
454 | case I915_PARAM_HAS_PRIME_VMAP_FLUSH: | |
455 | case I915_PARAM_HAS_PINNED_BATCHES: | |
456 | case I915_PARAM_HAS_EXEC_NO_RELOC: | |
457 | case I915_PARAM_HAS_EXEC_HANDLE_LUT: | |
458 | case I915_PARAM_HAS_COHERENT_PHYS_GTT: | |
459 | case I915_PARAM_HAS_EXEC_SOFTPIN: | |
77ae9957 | 460 | case I915_PARAM_HAS_EXEC_ASYNC: |
fec0445c | 461 | case I915_PARAM_HAS_EXEC_FENCE: |
b0fd47ad | 462 | case I915_PARAM_HAS_EXEC_CAPTURE: |
1a71cf2f | 463 | case I915_PARAM_HAS_EXEC_BATCH_FIRST: |
cf6e7bac | 464 | case I915_PARAM_HAS_EXEC_FENCE_ARRAY: |
a88b6e4c | 465 | case I915_PARAM_HAS_EXEC_SUBMIT_FENCE: |
16162470 DW |
466 | /* For the time being all of these are always true; |
467 | * if some supported hardware does not have one of these | |
468 | * features this value needs to be provided from | |
469 | * INTEL_INFO(), a feature macro, or similar. | |
470 | */ | |
471 | value = 1; | |
472 | break; | |
d2b4b979 CW |
473 | case I915_PARAM_HAS_CONTEXT_ISOLATION: |
474 | value = intel_engines_has_context_isolation(dev_priv); | |
475 | break; | |
7fed555c | 476 | case I915_PARAM_SLICE_MASK: |
bd41ca49 | 477 | value = sseu->slice_mask; |
7fed555c RB |
478 | if (!value) |
479 | return -ENODEV; | |
480 | break; | |
f5320233 | 481 | case I915_PARAM_SUBSLICE_MASK: |
a10f361d | 482 | value = sseu->subslice_mask[0]; |
f5320233 RB |
483 | if (!value) |
484 | return -ENODEV; | |
485 | break; | |
dab91783 | 486 | case I915_PARAM_CS_TIMESTAMP_FREQUENCY: |
0258404f | 487 | value = 1000 * RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz; |
dab91783 | 488 | break; |
900ccf30 CW |
489 | case I915_PARAM_MMAP_GTT_COHERENT: |
490 | value = INTEL_INFO(dev_priv)->has_coherent_ggtt; | |
491 | break; | |
0673ad47 CW |
492 | default: |
493 | DRM_DEBUG("Unknown parameter %d\n", param->param); | |
494 | return -EINVAL; | |
495 | } | |
496 | ||
dda33009 | 497 | if (put_user(value, param->value)) |
0673ad47 | 498 | return -EFAULT; |
0673ad47 CW |
499 | |
500 | return 0; | |
501 | } | |
502 | ||
da5f53bf | 503 | static int i915_get_bridge_dev(struct drm_i915_private *dev_priv) |
0673ad47 | 504 | { |
57b29646 SK |
505 | int domain = pci_domain_nr(dev_priv->drm.pdev->bus); |
506 | ||
507 | dev_priv->bridge_dev = | |
508 | pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0)); | |
0673ad47 CW |
509 | if (!dev_priv->bridge_dev) { |
510 | DRM_ERROR("bridge device not found\n"); | |
511 | return -1; | |
512 | } | |
513 | return 0; | |
514 | } | |
515 | ||
516 | /* Allocate space for the MCH regs if needed, return nonzero on error */ | |
517 | static int | |
da5f53bf | 518 | intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv) |
0673ad47 | 519 | { |
514e1d64 | 520 | int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
0673ad47 CW |
521 | u32 temp_lo, temp_hi = 0; |
522 | u64 mchbar_addr; | |
523 | int ret; | |
524 | ||
514e1d64 | 525 | if (INTEL_GEN(dev_priv) >= 4) |
0673ad47 CW |
526 | pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); |
527 | pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); | |
528 | mchbar_addr = ((u64)temp_hi << 32) | temp_lo; | |
529 | ||
530 | /* If ACPI doesn't have it, assume we need to allocate it ourselves */ | |
531 | #ifdef CONFIG_PNP | |
532 | if (mchbar_addr && | |
533 | pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) | |
534 | return 0; | |
535 | #endif | |
536 | ||
537 | /* Get some space for it */ | |
538 | dev_priv->mch_res.name = "i915 MCHBAR"; | |
539 | dev_priv->mch_res.flags = IORESOURCE_MEM; | |
540 | ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, | |
541 | &dev_priv->mch_res, | |
542 | MCHBAR_SIZE, MCHBAR_SIZE, | |
543 | PCIBIOS_MIN_MEM, | |
544 | 0, pcibios_align_resource, | |
545 | dev_priv->bridge_dev); | |
546 | if (ret) { | |
547 | DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret); | |
548 | dev_priv->mch_res.start = 0; | |
549 | return ret; | |
550 | } | |
551 | ||
514e1d64 | 552 | if (INTEL_GEN(dev_priv) >= 4) |
0673ad47 CW |
553 | pci_write_config_dword(dev_priv->bridge_dev, reg + 4, |
554 | upper_32_bits(dev_priv->mch_res.start)); | |
555 | ||
556 | pci_write_config_dword(dev_priv->bridge_dev, reg, | |
557 | lower_32_bits(dev_priv->mch_res.start)); | |
558 | return 0; | |
559 | } | |
560 | ||
561 | /* Setup MCHBAR if possible, return true if we should disable it again */ | |
562 | static void | |
da5f53bf | 563 | intel_setup_mchbar(struct drm_i915_private *dev_priv) |
0673ad47 | 564 | { |
514e1d64 | 565 | int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
0673ad47 CW |
566 | u32 temp; |
567 | bool enabled; | |
568 | ||
920a14b2 | 569 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
0673ad47 CW |
570 | return; |
571 | ||
572 | dev_priv->mchbar_need_disable = false; | |
573 | ||
50a0bc90 | 574 | if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { |
0673ad47 CW |
575 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp); |
576 | enabled = !!(temp & DEVEN_MCHBAR_EN); | |
577 | } else { | |
578 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
579 | enabled = temp & 1; | |
580 | } | |
581 | ||
582 | /* If it's already enabled, don't have to do anything */ | |
583 | if (enabled) | |
584 | return; | |
585 | ||
da5f53bf | 586 | if (intel_alloc_mchbar_resource(dev_priv)) |
0673ad47 CW |
587 | return; |
588 | ||
589 | dev_priv->mchbar_need_disable = true; | |
590 | ||
591 | /* Space is allocated or reserved, so enable it. */ | |
50a0bc90 | 592 | if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { |
0673ad47 CW |
593 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN, |
594 | temp | DEVEN_MCHBAR_EN); | |
595 | } else { | |
596 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
597 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); | |
598 | } | |
599 | } | |
600 | ||
601 | static void | |
da5f53bf | 602 | intel_teardown_mchbar(struct drm_i915_private *dev_priv) |
0673ad47 | 603 | { |
514e1d64 | 604 | int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
0673ad47 CW |
605 | |
606 | if (dev_priv->mchbar_need_disable) { | |
50a0bc90 | 607 | if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { |
0673ad47 CW |
608 | u32 deven_val; |
609 | ||
610 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN, | |
611 | &deven_val); | |
612 | deven_val &= ~DEVEN_MCHBAR_EN; | |
613 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN, | |
614 | deven_val); | |
615 | } else { | |
616 | u32 mchbar_val; | |
617 | ||
618 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, | |
619 | &mchbar_val); | |
620 | mchbar_val &= ~1; | |
621 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, | |
622 | mchbar_val); | |
623 | } | |
624 | } | |
625 | ||
626 | if (dev_priv->mch_res.start) | |
627 | release_resource(&dev_priv->mch_res); | |
628 | } | |
629 | ||
630 | /* true = enable decode, false = disable decoder */ | |
631 | static unsigned int i915_vga_set_decode(void *cookie, bool state) | |
632 | { | |
da5f53bf | 633 | struct drm_i915_private *dev_priv = cookie; |
0673ad47 | 634 | |
da5f53bf | 635 | intel_modeset_vga_set_state(dev_priv, state); |
0673ad47 CW |
636 | if (state) |
637 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
638 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
639 | else | |
640 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
641 | } | |
642 | ||
7f26cb88 TU |
643 | static int i915_resume_switcheroo(struct drm_device *dev); |
644 | static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state); | |
645 | ||
0673ad47 CW |
646 | static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) |
647 | { | |
648 | struct drm_device *dev = pci_get_drvdata(pdev); | |
649 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; | |
650 | ||
651 | if (state == VGA_SWITCHEROO_ON) { | |
652 | pr_info("switched on\n"); | |
653 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
654 | /* i915 resume handler doesn't set to D0 */ | |
52a05c30 | 655 | pci_set_power_state(pdev, PCI_D0); |
0673ad47 CW |
656 | i915_resume_switcheroo(dev); |
657 | dev->switch_power_state = DRM_SWITCH_POWER_ON; | |
658 | } else { | |
659 | pr_info("switched off\n"); | |
660 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
661 | i915_suspend_switcheroo(dev, pmm); | |
662 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; | |
663 | } | |
664 | } | |
665 | ||
666 | static bool i915_switcheroo_can_switch(struct pci_dev *pdev) | |
667 | { | |
668 | struct drm_device *dev = pci_get_drvdata(pdev); | |
669 | ||
670 | /* | |
671 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
672 | * locking inversion with the driver load path. And the access here is | |
673 | * completely racy anyway. So don't bother with locking for now. | |
674 | */ | |
675 | return dev->open_count == 0; | |
676 | } | |
677 | ||
678 | static const struct vga_switcheroo_client_ops i915_switcheroo_ops = { | |
679 | .set_gpu_state = i915_switcheroo_set_state, | |
680 | .reprobe = NULL, | |
681 | .can_switch = i915_switcheroo_can_switch, | |
682 | }; | |
683 | ||
0b61b8b0 | 684 | static int i915_driver_modeset_probe(struct drm_device *dev) |
0673ad47 | 685 | { |
fac5e23e | 686 | struct drm_i915_private *dev_priv = to_i915(dev); |
52a05c30 | 687 | struct pci_dev *pdev = dev_priv->drm.pdev; |
0673ad47 CW |
688 | int ret; |
689 | ||
f2db53f1 | 690 | if (i915_inject_probe_failure()) |
0673ad47 CW |
691 | return -ENODEV; |
692 | ||
e1bf094b | 693 | if (HAS_DISPLAY(dev_priv)) { |
8d3bf1a3 JRS |
694 | ret = drm_vblank_init(&dev_priv->drm, |
695 | INTEL_INFO(dev_priv)->num_pipes); | |
696 | if (ret) | |
697 | goto out; | |
698 | } | |
699 | ||
66578857 | 700 | intel_bios_init(dev_priv); |
0673ad47 CW |
701 | |
702 | /* If we have > 1 VGA cards, then we need to arbitrate access | |
703 | * to the common VGA resources. | |
704 | * | |
705 | * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA), | |
706 | * then we do not take part in VGA arbitration and the | |
707 | * vga_client_register() fails with -ENODEV. | |
708 | */ | |
da5f53bf | 709 | ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode); |
0673ad47 CW |
710 | if (ret && ret != -ENODEV) |
711 | goto out; | |
712 | ||
713 | intel_register_dsm_handler(); | |
714 | ||
52a05c30 | 715 | ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false); |
0673ad47 CW |
716 | if (ret) |
717 | goto cleanup_vga_client; | |
718 | ||
719 | /* must happen before intel_power_domains_init_hw() on VLV/CHV */ | |
720 | intel_update_rawclk(dev_priv); | |
721 | ||
722 | intel_power_domains_init_hw(dev_priv, false); | |
723 | ||
724 | intel_csr_ucode_init(dev_priv); | |
725 | ||
726 | ret = intel_irq_install(dev_priv); | |
727 | if (ret) | |
728 | goto cleanup_csr; | |
729 | ||
3ce2ea65 | 730 | intel_gmbus_setup(dev_priv); |
0673ad47 CW |
731 | |
732 | /* Important: The output setup functions called by modeset_init need | |
733 | * working irqs for e.g. gmbus and dp aux transfers. */ | |
b079bd17 VS |
734 | ret = intel_modeset_init(dev); |
735 | if (ret) | |
736 | goto cleanup_irq; | |
0673ad47 | 737 | |
bf9e8429 | 738 | ret = i915_gem_init(dev_priv); |
0673ad47 | 739 | if (ret) |
73bad7ca | 740 | goto cleanup_modeset; |
0673ad47 | 741 | |
58db08a7 | 742 | intel_overlay_setup(dev_priv); |
0673ad47 | 743 | |
e1bf094b | 744 | if (!HAS_DISPLAY(dev_priv)) |
0673ad47 CW |
745 | return 0; |
746 | ||
747 | ret = intel_fbdev_init(dev); | |
748 | if (ret) | |
749 | goto cleanup_gem; | |
750 | ||
751 | /* Only enable hotplug handling once the fbdev is fully set up. */ | |
752 | intel_hpd_init(dev_priv); | |
753 | ||
a8147d0c JRS |
754 | intel_init_ipc(dev_priv); |
755 | ||
0673ad47 CW |
756 | return 0; |
757 | ||
758 | cleanup_gem: | |
5861b013 | 759 | i915_gem_suspend(dev_priv); |
78dae1ac | 760 | i915_gem_driver_remove(dev_priv); |
3b58a945 | 761 | i915_gem_driver_release(dev_priv); |
73bad7ca | 762 | cleanup_modeset: |
78dae1ac | 763 | intel_modeset_driver_remove(dev); |
0673ad47 | 764 | cleanup_irq: |
b318b824 | 765 | intel_irq_uninstall(dev_priv); |
3ce2ea65 | 766 | intel_gmbus_teardown(dev_priv); |
0673ad47 CW |
767 | cleanup_csr: |
768 | intel_csr_ucode_fini(dev_priv); | |
78dae1ac | 769 | intel_power_domains_driver_remove(dev_priv); |
52a05c30 | 770 | vga_switcheroo_unregister_client(pdev); |
0673ad47 | 771 | cleanup_vga_client: |
52a05c30 | 772 | vga_client_register(pdev, NULL, NULL, NULL); |
0673ad47 CW |
773 | out: |
774 | return ret; | |
775 | } | |
776 | ||
0673ad47 CW |
777 | static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) |
778 | { | |
779 | struct apertures_struct *ap; | |
91c8a326 | 780 | struct pci_dev *pdev = dev_priv->drm.pdev; |
0673ad47 CW |
781 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
782 | bool primary; | |
783 | int ret; | |
784 | ||
785 | ap = alloc_apertures(1); | |
786 | if (!ap) | |
787 | return -ENOMEM; | |
788 | ||
73ebd503 | 789 | ap->ranges[0].base = ggtt->gmadr.start; |
0673ad47 CW |
790 | ap->ranges[0].size = ggtt->mappable_end; |
791 | ||
792 | primary = | |
793 | pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; | |
794 | ||
44adece5 | 795 | ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary); |
0673ad47 CW |
796 | |
797 | kfree(ap); | |
798 | ||
799 | return ret; | |
800 | } | |
0673ad47 | 801 | |
0673ad47 CW |
802 | static void intel_init_dpio(struct drm_i915_private *dev_priv) |
803 | { | |
804 | /* | |
805 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
806 | * CHV x1 PHY (DP/HDMI D) | |
807 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
808 | */ | |
809 | if (IS_CHERRYVIEW(dev_priv)) { | |
810 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
811 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
812 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
813 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; | |
814 | } | |
815 | } | |
816 | ||
817 | static int i915_workqueues_init(struct drm_i915_private *dev_priv) | |
818 | { | |
819 | /* | |
820 | * The i915 workqueue is primarily used for batched retirement of | |
821 | * requests (and thus managing bo) once the task has been completed | |
e61e0f51 | 822 | * by the GPU. i915_retire_requests() is called directly when we |
0673ad47 CW |
823 | * need high-priority retirement, such as waiting for an explicit |
824 | * bo. | |
825 | * | |
826 | * It is also used for periodic low-priority events, such as | |
827 | * idle-timers and recording error state. | |
828 | * | |
829 | * All tasks on the workqueue are expected to acquire the dev mutex | |
830 | * so there is no point in running more than one instance of the | |
831 | * workqueue at any time. Use an ordered one. | |
832 | */ | |
833 | dev_priv->wq = alloc_ordered_workqueue("i915", 0); | |
834 | if (dev_priv->wq == NULL) | |
835 | goto out_err; | |
836 | ||
837 | dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0); | |
838 | if (dev_priv->hotplug.dp_wq == NULL) | |
839 | goto out_free_wq; | |
840 | ||
0673ad47 CW |
841 | return 0; |
842 | ||
0673ad47 CW |
843 | out_free_wq: |
844 | destroy_workqueue(dev_priv->wq); | |
845 | out_err: | |
846 | DRM_ERROR("Failed to allocate workqueues.\n"); | |
847 | ||
848 | return -ENOMEM; | |
849 | } | |
850 | ||
851 | static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv) | |
852 | { | |
0673ad47 CW |
853 | destroy_workqueue(dev_priv->hotplug.dp_wq); |
854 | destroy_workqueue(dev_priv->wq); | |
855 | } | |
856 | ||
4fc7e845 PZ |
857 | /* |
858 | * We don't keep the workarounds for pre-production hardware, so we expect our | |
859 | * driver to fail on these machines in one way or another. A little warning on | |
860 | * dmesg may help both the user and the bug triagers. | |
6a7a6a98 CW |
861 | * |
862 | * Our policy for removing pre-production workarounds is to keep the | |
863 | * current gen workarounds as a guide to the bring-up of the next gen | |
864 | * (workarounds have a habit of persisting!). Anything older than that | |
865 | * should be removed along with the complications they introduce. | |
4fc7e845 PZ |
866 | */ |
867 | static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv) | |
868 | { | |
248a124d CW |
869 | bool pre = false; |
870 | ||
871 | pre |= IS_HSW_EARLY_SDV(dev_priv); | |
872 | pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0); | |
0102ba1f | 873 | pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST); |
1aca96cc | 874 | pre |= IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0); |
248a124d | 875 | |
7c5ff4a2 | 876 | if (pre) { |
4fc7e845 PZ |
877 | DRM_ERROR("This is a pre-production stepping. " |
878 | "It may not be fully functional.\n"); | |
7c5ff4a2 CW |
879 | add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK); |
880 | } | |
4fc7e845 PZ |
881 | } |
882 | ||
0673ad47 | 883 | /** |
0b61b8b0 | 884 | * i915_driver_early_probe - setup state not requiring device access |
0673ad47 CW |
885 | * @dev_priv: device private |
886 | * | |
887 | * Initialize everything that is a "SW-only" state, that is state not | |
888 | * requiring accessing the device or exposing the driver via kernel internal | |
889 | * or userspace interfaces. Example steps belonging here: lock initialization, | |
890 | * system memory allocation, setting up device specific attributes and | |
891 | * function hooks not requiring accessing the device. | |
892 | */ | |
0b61b8b0 | 893 | static int i915_driver_early_probe(struct drm_i915_private *dev_priv) |
0673ad47 | 894 | { |
0673ad47 CW |
895 | int ret = 0; |
896 | ||
f2db53f1 | 897 | if (i915_inject_probe_failure()) |
0673ad47 CW |
898 | return -ENODEV; |
899 | ||
805446c8 TU |
900 | intel_device_info_subplatform_init(dev_priv); |
901 | ||
01385758 | 902 | intel_uncore_init_early(&dev_priv->uncore, dev_priv); |
6cbe8830 | 903 | |
0673ad47 CW |
904 | spin_lock_init(&dev_priv->irq_lock); |
905 | spin_lock_init(&dev_priv->gpu_error.lock); | |
906 | mutex_init(&dev_priv->backlight_lock); | |
317eaa95 | 907 | |
0673ad47 | 908 | mutex_init(&dev_priv->sb_lock); |
a75d035f CW |
909 | pm_qos_add_request(&dev_priv->sb_qos, |
910 | PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); | |
911 | ||
0673ad47 CW |
912 | mutex_init(&dev_priv->av_mutex); |
913 | mutex_init(&dev_priv->wm.wm_mutex); | |
914 | mutex_init(&dev_priv->pps_mutex); | |
9055aac7 | 915 | mutex_init(&dev_priv->hdcp_comp_mutex); |
0673ad47 | 916 | |
0b1de5d5 | 917 | i915_memcpy_init_early(dev_priv); |
69c66355 | 918 | intel_runtime_pm_init_early(&dev_priv->runtime_pm); |
0b1de5d5 | 919 | |
0673ad47 CW |
920 | ret = i915_workqueues_init(dev_priv); |
921 | if (ret < 0) | |
f3bcb0cc | 922 | return ret; |
0673ad47 | 923 | |
724e9564 | 924 | intel_gt_init_early(&dev_priv->gt, dev_priv); |
24635c51 | 925 | |
a0de908d MW |
926 | ret = i915_gem_init_early(dev_priv); |
927 | if (ret < 0) | |
928 | goto err_workqueues; | |
929 | ||
0673ad47 | 930 | /* This must be called before any calls to HAS_PCH_* */ |
da5f53bf | 931 | intel_detect_pch(dev_priv); |
0673ad47 | 932 | |
a0de908d | 933 | intel_wopcm_init_early(&dev_priv->wopcm); |
ca7b2c1b | 934 | intel_uc_init_early(&dev_priv->gt.uc); |
192aa181 | 935 | intel_pm_setup(dev_priv); |
0673ad47 | 936 | intel_init_dpio(dev_priv); |
f28ec6f4 ID |
937 | ret = intel_power_domains_init(dev_priv); |
938 | if (ret < 0) | |
939 | goto err_uc; | |
0673ad47 CW |
940 | intel_irq_init(dev_priv); |
941 | intel_init_display_hooks(dev_priv); | |
942 | intel_init_clock_gating_hooks(dev_priv); | |
943 | intel_init_audio_hooks(dev_priv); | |
36cdd013 | 944 | intel_display_crc_init(dev_priv); |
0673ad47 | 945 | |
4fc7e845 | 946 | intel_detect_preproduction_hw(dev_priv); |
0673ad47 CW |
947 | |
948 | return 0; | |
949 | ||
f28ec6f4 | 950 | err_uc: |
ca7b2c1b | 951 | intel_uc_cleanup_early(&dev_priv->gt.uc); |
f28ec6f4 | 952 | i915_gem_cleanup_early(dev_priv); |
a0de908d | 953 | err_workqueues: |
6cf72db6 | 954 | intel_gt_driver_late_release(&dev_priv->gt); |
0673ad47 CW |
955 | i915_workqueues_cleanup(dev_priv); |
956 | return ret; | |
957 | } | |
958 | ||
959 | /** | |
3b58a945 | 960 | * i915_driver_late_release - cleanup the setup done in |
0b61b8b0 | 961 | * i915_driver_early_probe() |
0673ad47 CW |
962 | * @dev_priv: device private |
963 | */ | |
3b58a945 | 964 | static void i915_driver_late_release(struct drm_i915_private *dev_priv) |
0673ad47 | 965 | { |
cefcff8f | 966 | intel_irq_fini(dev_priv); |
f28ec6f4 | 967 | intel_power_domains_cleanup(dev_priv); |
ca7b2c1b | 968 | intel_uc_cleanup_early(&dev_priv->gt.uc); |
a0de908d | 969 | i915_gem_cleanup_early(dev_priv); |
6cf72db6 | 970 | intel_gt_driver_late_release(&dev_priv->gt); |
0673ad47 | 971 | i915_workqueues_cleanup(dev_priv); |
a75d035f CW |
972 | |
973 | pm_qos_remove_request(&dev_priv->sb_qos); | |
974 | mutex_destroy(&dev_priv->sb_lock); | |
0673ad47 CW |
975 | } |
976 | ||
0673ad47 | 977 | /** |
0b61b8b0 | 978 | * i915_driver_mmio_probe - setup device MMIO |
0673ad47 CW |
979 | * @dev_priv: device private |
980 | * | |
981 | * Setup minimal device state necessary for MMIO accesses later in the | |
982 | * initialization sequence. The setup here should avoid any other device-wide | |
983 | * side effects or exposing the driver via kernel internal or user space | |
984 | * interfaces. | |
985 | */ | |
0b61b8b0 | 986 | static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) |
0673ad47 | 987 | { |
0673ad47 CW |
988 | int ret; |
989 | ||
f2db53f1 | 990 | if (i915_inject_probe_failure()) |
0673ad47 CW |
991 | return -ENODEV; |
992 | ||
da5f53bf | 993 | if (i915_get_bridge_dev(dev_priv)) |
0673ad47 CW |
994 | return -EIO; |
995 | ||
3de6f852 | 996 | ret = intel_uncore_init_mmio(&dev_priv->uncore); |
0673ad47 | 997 | if (ret < 0) |
63ffbcda | 998 | goto err_bridge; |
0673ad47 | 999 | |
25286aac DCS |
1000 | /* Try to make sure MCHBAR is enabled before poking at it */ |
1001 | intel_setup_mchbar(dev_priv); | |
63ffbcda | 1002 | |
26376a7e OM |
1003 | intel_device_info_init_mmio(dev_priv); |
1004 | ||
3de6f852 | 1005 | intel_uncore_prune_mmio_domains(&dev_priv->uncore); |
26376a7e | 1006 | |
ca7b2c1b | 1007 | intel_uc_init_mmio(&dev_priv->gt.uc); |
1fc556fa | 1008 | |
63ffbcda JL |
1009 | ret = intel_engines_init_mmio(dev_priv); |
1010 | if (ret) | |
1011 | goto err_uncore; | |
1012 | ||
24145517 | 1013 | i915_gem_init_mmio(dev_priv); |
0673ad47 CW |
1014 | |
1015 | return 0; | |
1016 | ||
63ffbcda | 1017 | err_uncore: |
25286aac | 1018 | intel_teardown_mchbar(dev_priv); |
3de6f852 | 1019 | intel_uncore_fini_mmio(&dev_priv->uncore); |
63ffbcda | 1020 | err_bridge: |
0673ad47 CW |
1021 | pci_dev_put(dev_priv->bridge_dev); |
1022 | ||
1023 | return ret; | |
1024 | } | |
1025 | ||
1026 | /** | |
0b61b8b0 | 1027 | * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe() |
0673ad47 CW |
1028 | * @dev_priv: device private |
1029 | */ | |
3b58a945 | 1030 | static void i915_driver_mmio_release(struct drm_i915_private *dev_priv) |
0673ad47 | 1031 | { |
f3bcb0cc | 1032 | intel_engines_cleanup(dev_priv); |
25286aac | 1033 | intel_teardown_mchbar(dev_priv); |
3de6f852 | 1034 | intel_uncore_fini_mmio(&dev_priv->uncore); |
0673ad47 CW |
1035 | pci_dev_put(dev_priv->bridge_dev); |
1036 | } | |
1037 | ||
94b4f3ba CW |
1038 | static void intel_sanitize_options(struct drm_i915_private *dev_priv) |
1039 | { | |
67b7f33e | 1040 | intel_gvt_sanitize_options(dev_priv); |
94b4f3ba CW |
1041 | } |
1042 | ||
b185a352 VS |
1043 | #define DRAM_TYPE_STR(type) [INTEL_DRAM_ ## type] = #type |
1044 | ||
1045 | static const char *intel_dram_type_str(enum intel_dram_type type) | |
1046 | { | |
1047 | static const char * const str[] = { | |
1048 | DRAM_TYPE_STR(UNKNOWN), | |
1049 | DRAM_TYPE_STR(DDR3), | |
1050 | DRAM_TYPE_STR(DDR4), | |
1051 | DRAM_TYPE_STR(LPDDR3), | |
1052 | DRAM_TYPE_STR(LPDDR4), | |
1053 | }; | |
1054 | ||
1055 | if (type >= ARRAY_SIZE(str)) | |
1056 | type = INTEL_DRAM_UNKNOWN; | |
1057 | ||
1058 | return str[type]; | |
1059 | } | |
1060 | ||
1061 | #undef DRAM_TYPE_STR | |
1062 | ||
54561b23 VS |
1063 | static int intel_dimm_num_devices(const struct dram_dimm_info *dimm) |
1064 | { | |
1065 | return dimm->ranks * 64 / (dimm->width ?: 1); | |
1066 | } | |
1067 | ||
ea411e6b VS |
1068 | /* Returns total GB for the whole DIMM */ |
1069 | static int skl_get_dimm_size(u16 val) | |
5771caf8 | 1070 | { |
ea411e6b VS |
1071 | return val & SKL_DRAM_SIZE_MASK; |
1072 | } | |
1073 | ||
1074 | static int skl_get_dimm_width(u16 val) | |
1075 | { | |
1076 | if (skl_get_dimm_size(val) == 0) | |
80373fb6 | 1077 | return 0; |
5771caf8 | 1078 | |
ea411e6b VS |
1079 | switch (val & SKL_DRAM_WIDTH_MASK) { |
1080 | case SKL_DRAM_WIDTH_X8: | |
1081 | case SKL_DRAM_WIDTH_X16: | |
1082 | case SKL_DRAM_WIDTH_X32: | |
1083 | val = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT; | |
1084 | return 8 << val; | |
1085 | default: | |
1086 | MISSING_CASE(val); | |
1087 | return 0; | |
1088 | } | |
1089 | } | |
1090 | ||
1091 | static int skl_get_dimm_ranks(u16 val) | |
1092 | { | |
1093 | if (skl_get_dimm_size(val) == 0) | |
1094 | return 0; | |
1095 | ||
1096 | val = (val & SKL_DRAM_RANK_MASK) >> SKL_DRAM_RANK_SHIFT; | |
1097 | ||
1098 | return val + 1; | |
5771caf8 MK |
1099 | } |
1100 | ||
6d9c1e92 VS |
1101 | /* Returns total GB for the whole DIMM */ |
1102 | static int cnl_get_dimm_size(u16 val) | |
1103 | { | |
1104 | return (val & CNL_DRAM_SIZE_MASK) / 2; | |
1105 | } | |
1106 | ||
1107 | static int cnl_get_dimm_width(u16 val) | |
1108 | { | |
1109 | if (cnl_get_dimm_size(val) == 0) | |
1110 | return 0; | |
1111 | ||
1112 | switch (val & CNL_DRAM_WIDTH_MASK) { | |
1113 | case CNL_DRAM_WIDTH_X8: | |
1114 | case CNL_DRAM_WIDTH_X16: | |
1115 | case CNL_DRAM_WIDTH_X32: | |
1116 | val = (val & CNL_DRAM_WIDTH_MASK) >> CNL_DRAM_WIDTH_SHIFT; | |
1117 | return 8 << val; | |
1118 | default: | |
1119 | MISSING_CASE(val); | |
1120 | return 0; | |
1121 | } | |
1122 | } | |
1123 | ||
1124 | static int cnl_get_dimm_ranks(u16 val) | |
1125 | { | |
1126 | if (cnl_get_dimm_size(val) == 0) | |
1127 | return 0; | |
1128 | ||
1129 | val = (val & CNL_DRAM_RANK_MASK) >> CNL_DRAM_RANK_SHIFT; | |
1130 | ||
1131 | return val + 1; | |
1132 | } | |
1133 | ||
86b59287 | 1134 | static bool |
54561b23 | 1135 | skl_is_16gb_dimm(const struct dram_dimm_info *dimm) |
86b59287 | 1136 | { |
54561b23 VS |
1137 | /* Convert total GB to Gb per DRAM device */ |
1138 | return 8 * dimm->size / (intel_dimm_num_devices(dimm) ?: 1) == 16; | |
86b59287 MK |
1139 | } |
1140 | ||
198b8dd9 | 1141 | static void |
6d9c1e92 VS |
1142 | skl_dram_get_dimm_info(struct drm_i915_private *dev_priv, |
1143 | struct dram_dimm_info *dimm, | |
198b8dd9 | 1144 | int channel, char dimm_name, u16 val) |
5771caf8 | 1145 | { |
6d9c1e92 VS |
1146 | if (INTEL_GEN(dev_priv) >= 10) { |
1147 | dimm->size = cnl_get_dimm_size(val); | |
1148 | dimm->width = cnl_get_dimm_width(val); | |
1149 | dimm->ranks = cnl_get_dimm_ranks(val); | |
1150 | } else { | |
1151 | dimm->size = skl_get_dimm_size(val); | |
1152 | dimm->width = skl_get_dimm_width(val); | |
1153 | dimm->ranks = skl_get_dimm_ranks(val); | |
1154 | } | |
5771caf8 | 1155 | |
198b8dd9 VS |
1156 | DRM_DEBUG_KMS("CH%u DIMM %c size: %u GB, width: X%u, ranks: %u, 16Gb DIMMs: %s\n", |
1157 | channel, dimm_name, dimm->size, dimm->width, dimm->ranks, | |
1158 | yesno(skl_is_16gb_dimm(dimm))); | |
1159 | } | |
5771caf8 | 1160 | |
198b8dd9 | 1161 | static int |
6d9c1e92 VS |
1162 | skl_dram_get_channel_info(struct drm_i915_private *dev_priv, |
1163 | struct dram_channel_info *ch, | |
198b8dd9 VS |
1164 | int channel, u32 val) |
1165 | { | |
6d9c1e92 VS |
1166 | skl_dram_get_dimm_info(dev_priv, &ch->dimm_l, |
1167 | channel, 'L', val & 0xffff); | |
1168 | skl_dram_get_dimm_info(dev_priv, &ch->dimm_s, | |
1169 | channel, 'S', val >> 16); | |
5771caf8 | 1170 | |
1d55967d | 1171 | if (ch->dimm_l.size == 0 && ch->dimm_s.size == 0) { |
198b8dd9 | 1172 | DRM_DEBUG_KMS("CH%u not populated\n", channel); |
5771caf8 | 1173 | return -EINVAL; |
198b8dd9 | 1174 | } |
80373fb6 | 1175 | |
1d55967d | 1176 | if (ch->dimm_l.ranks == 2 || ch->dimm_s.ranks == 2) |
80373fb6 | 1177 | ch->ranks = 2; |
1d55967d | 1178 | else if (ch->dimm_l.ranks == 1 && ch->dimm_s.ranks == 1) |
80373fb6 | 1179 | ch->ranks = 2; |
5771caf8 | 1180 | else |
80373fb6 | 1181 | ch->ranks = 1; |
5771caf8 | 1182 | |
54561b23 | 1183 | ch->is_16gb_dimm = |
1d55967d VS |
1184 | skl_is_16gb_dimm(&ch->dimm_l) || |
1185 | skl_is_16gb_dimm(&ch->dimm_s); | |
86b59287 | 1186 | |
198b8dd9 VS |
1187 | DRM_DEBUG_KMS("CH%u ranks: %u, 16Gb DIMMs: %s\n", |
1188 | channel, ch->ranks, yesno(ch->is_16gb_dimm)); | |
5771caf8 MK |
1189 | |
1190 | return 0; | |
1191 | } | |
1192 | ||
8a6c5447 | 1193 | static bool |
d75434bc VS |
1194 | intel_is_dram_symmetric(const struct dram_channel_info *ch0, |
1195 | const struct dram_channel_info *ch1) | |
8a6c5447 | 1196 | { |
d75434bc | 1197 | return !memcmp(ch0, ch1, sizeof(*ch0)) && |
1d55967d VS |
1198 | (ch0->dimm_s.size == 0 || |
1199 | !memcmp(&ch0->dimm_l, &ch0->dimm_s, sizeof(ch0->dimm_l))); | |
8a6c5447 MK |
1200 | } |
1201 | ||
5771caf8 MK |
1202 | static int |
1203 | skl_dram_get_channels_info(struct drm_i915_private *dev_priv) | |
1204 | { | |
1205 | struct dram_info *dram_info = &dev_priv->dram_info; | |
198b8dd9 | 1206 | struct dram_channel_info ch0 = {}, ch1 = {}; |
d75434bc | 1207 | u32 val; |
5771caf8 MK |
1208 | int ret; |
1209 | ||
d75434bc | 1210 | val = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN); |
6d9c1e92 | 1211 | ret = skl_dram_get_channel_info(dev_priv, &ch0, 0, val); |
5771caf8 MK |
1212 | if (ret == 0) |
1213 | dram_info->num_channels++; | |
1214 | ||
d75434bc | 1215 | val = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN); |
6d9c1e92 | 1216 | ret = skl_dram_get_channel_info(dev_priv, &ch1, 1, val); |
5771caf8 MK |
1217 | if (ret == 0) |
1218 | dram_info->num_channels++; | |
1219 | ||
1220 | if (dram_info->num_channels == 0) { | |
1221 | DRM_INFO("Number of memory channels is zero\n"); | |
1222 | return -EINVAL; | |
1223 | } | |
1224 | ||
1225 | /* | |
1226 | * If any of the channel is single rank channel, worst case output | |
1227 | * will be same as if single rank memory, so consider single rank | |
1228 | * memory. | |
1229 | */ | |
80373fb6 VS |
1230 | if (ch0.ranks == 1 || ch1.ranks == 1) |
1231 | dram_info->ranks = 1; | |
5771caf8 | 1232 | else |
80373fb6 | 1233 | dram_info->ranks = max(ch0.ranks, ch1.ranks); |
5771caf8 | 1234 | |
80373fb6 | 1235 | if (dram_info->ranks == 0) { |
5771caf8 MK |
1236 | DRM_INFO("couldn't get memory rank information\n"); |
1237 | return -EINVAL; | |
1238 | } | |
86b59287 | 1239 | |
5d6f36b2 | 1240 | dram_info->is_16gb_dimm = ch0.is_16gb_dimm || ch1.is_16gb_dimm; |
86b59287 | 1241 | |
d75434bc | 1242 | dram_info->symmetric_memory = intel_is_dram_symmetric(&ch0, &ch1); |
8a6c5447 | 1243 | |
d75434bc VS |
1244 | DRM_DEBUG_KMS("Memory configuration is symmetric? %s\n", |
1245 | yesno(dram_info->symmetric_memory)); | |
5771caf8 MK |
1246 | return 0; |
1247 | } | |
1248 | ||
b185a352 VS |
1249 | static enum intel_dram_type |
1250 | skl_get_dram_type(struct drm_i915_private *dev_priv) | |
1251 | { | |
1252 | u32 val; | |
1253 | ||
1254 | val = I915_READ(SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN); | |
1255 | ||
1256 | switch (val & SKL_DRAM_DDR_TYPE_MASK) { | |
1257 | case SKL_DRAM_DDR_TYPE_DDR3: | |
1258 | return INTEL_DRAM_DDR3; | |
1259 | case SKL_DRAM_DDR_TYPE_DDR4: | |
1260 | return INTEL_DRAM_DDR4; | |
1261 | case SKL_DRAM_DDR_TYPE_LPDDR3: | |
1262 | return INTEL_DRAM_LPDDR3; | |
1263 | case SKL_DRAM_DDR_TYPE_LPDDR4: | |
1264 | return INTEL_DRAM_LPDDR4; | |
1265 | default: | |
1266 | MISSING_CASE(val); | |
1267 | return INTEL_DRAM_UNKNOWN; | |
1268 | } | |
1269 | } | |
1270 | ||
5771caf8 MK |
1271 | static int |
1272 | skl_get_dram_info(struct drm_i915_private *dev_priv) | |
1273 | { | |
1274 | struct dram_info *dram_info = &dev_priv->dram_info; | |
1275 | u32 mem_freq_khz, val; | |
1276 | int ret; | |
1277 | ||
b185a352 VS |
1278 | dram_info->type = skl_get_dram_type(dev_priv); |
1279 | DRM_DEBUG_KMS("DRAM type: %s\n", intel_dram_type_str(dram_info->type)); | |
1280 | ||
5771caf8 MK |
1281 | ret = skl_dram_get_channels_info(dev_priv); |
1282 | if (ret) | |
1283 | return ret; | |
1284 | ||
1285 | val = I915_READ(SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU); | |
1286 | mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) * | |
1287 | SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000); | |
1288 | ||
1289 | dram_info->bandwidth_kbps = dram_info->num_channels * | |
1290 | mem_freq_khz * 8; | |
1291 | ||
1292 | if (dram_info->bandwidth_kbps == 0) { | |
1293 | DRM_INFO("Couldn't get system memory bandwidth\n"); | |
1294 | return -EINVAL; | |
1295 | } | |
1296 | ||
1297 | dram_info->valid = true; | |
1298 | return 0; | |
1299 | } | |
1300 | ||
a62819a3 VS |
1301 | /* Returns Gb per DRAM device */ |
1302 | static int bxt_get_dimm_size(u32 val) | |
1303 | { | |
1304 | switch (val & BXT_DRAM_SIZE_MASK) { | |
8860343c | 1305 | case BXT_DRAM_SIZE_4GBIT: |
a62819a3 | 1306 | return 4; |
8860343c | 1307 | case BXT_DRAM_SIZE_6GBIT: |
a62819a3 | 1308 | return 6; |
8860343c | 1309 | case BXT_DRAM_SIZE_8GBIT: |
a62819a3 | 1310 | return 8; |
8860343c | 1311 | case BXT_DRAM_SIZE_12GBIT: |
a62819a3 | 1312 | return 12; |
8860343c | 1313 | case BXT_DRAM_SIZE_16GBIT: |
a62819a3 VS |
1314 | return 16; |
1315 | default: | |
1316 | MISSING_CASE(val); | |
1317 | return 0; | |
1318 | } | |
1319 | } | |
1320 | ||
1321 | static int bxt_get_dimm_width(u32 val) | |
1322 | { | |
1323 | if (!bxt_get_dimm_size(val)) | |
1324 | return 0; | |
1325 | ||
1326 | val = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT; | |
1327 | ||
1328 | return 8 << val; | |
1329 | } | |
1330 | ||
1331 | static int bxt_get_dimm_ranks(u32 val) | |
1332 | { | |
1333 | if (!bxt_get_dimm_size(val)) | |
1334 | return 0; | |
1335 | ||
1336 | switch (val & BXT_DRAM_RANK_MASK) { | |
1337 | case BXT_DRAM_RANK_SINGLE: | |
1338 | return 1; | |
1339 | case BXT_DRAM_RANK_DUAL: | |
1340 | return 2; | |
1341 | default: | |
1342 | MISSING_CASE(val); | |
1343 | return 0; | |
1344 | } | |
1345 | } | |
1346 | ||
b185a352 VS |
1347 | static enum intel_dram_type bxt_get_dimm_type(u32 val) |
1348 | { | |
1349 | if (!bxt_get_dimm_size(val)) | |
1350 | return INTEL_DRAM_UNKNOWN; | |
1351 | ||
1352 | switch (val & BXT_DRAM_TYPE_MASK) { | |
1353 | case BXT_DRAM_TYPE_DDR3: | |
1354 | return INTEL_DRAM_DDR3; | |
1355 | case BXT_DRAM_TYPE_LPDDR3: | |
1356 | return INTEL_DRAM_LPDDR3; | |
1357 | case BXT_DRAM_TYPE_DDR4: | |
1358 | return INTEL_DRAM_DDR4; | |
1359 | case BXT_DRAM_TYPE_LPDDR4: | |
1360 | return INTEL_DRAM_LPDDR4; | |
1361 | default: | |
1362 | MISSING_CASE(val); | |
1363 | return INTEL_DRAM_UNKNOWN; | |
1364 | } | |
1365 | } | |
1366 | ||
a62819a3 VS |
1367 | static void bxt_get_dimm_info(struct dram_dimm_info *dimm, |
1368 | u32 val) | |
1369 | { | |
a62819a3 VS |
1370 | dimm->width = bxt_get_dimm_width(val); |
1371 | dimm->ranks = bxt_get_dimm_ranks(val); | |
8860343c VS |
1372 | |
1373 | /* | |
1374 | * Size in register is Gb per DRAM device. Convert to total | |
1375 | * GB to match the way we report this for non-LP platforms. | |
1376 | */ | |
1377 | dimm->size = bxt_get_dimm_size(val) * intel_dimm_num_devices(dimm) / 8; | |
a62819a3 VS |
1378 | } |
1379 | ||
cbfa59d4 MK |
1380 | static int |
1381 | bxt_get_dram_info(struct drm_i915_private *dev_priv) | |
1382 | { | |
1383 | struct dram_info *dram_info = &dev_priv->dram_info; | |
1384 | u32 dram_channels; | |
1385 | u32 mem_freq_khz, val; | |
1386 | u8 num_active_channels; | |
1387 | int i; | |
1388 | ||
1389 | val = I915_READ(BXT_P_CR_MC_BIOS_REQ_0_0_0); | |
1390 | mem_freq_khz = DIV_ROUND_UP((val & BXT_REQ_DATA_MASK) * | |
1391 | BXT_MEMORY_FREQ_MULTIPLIER_HZ, 1000); | |
1392 | ||
1393 | dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK; | |
1394 | num_active_channels = hweight32(dram_channels); | |
1395 | ||
1396 | /* Each active bit represents 4-byte channel */ | |
1397 | dram_info->bandwidth_kbps = (mem_freq_khz * num_active_channels * 4); | |
1398 | ||
1399 | if (dram_info->bandwidth_kbps == 0) { | |
1400 | DRM_INFO("Couldn't get system memory bandwidth\n"); | |
1401 | return -EINVAL; | |
1402 | } | |
1403 | ||
1404 | /* | |
1405 | * Now read each DUNIT8/9/10/11 to check the rank of each dimms. | |
1406 | */ | |
1407 | for (i = BXT_D_CR_DRP0_DUNIT_START; i <= BXT_D_CR_DRP0_DUNIT_END; i++) { | |
a62819a3 | 1408 | struct dram_dimm_info dimm; |
b185a352 | 1409 | enum intel_dram_type type; |
cbfa59d4 MK |
1410 | |
1411 | val = I915_READ(BXT_D_CR_DRP0_DUNIT(i)); | |
1412 | if (val == 0xFFFFFFFF) | |
1413 | continue; | |
1414 | ||
1415 | dram_info->num_channels++; | |
a62819a3 VS |
1416 | |
1417 | bxt_get_dimm_info(&dimm, val); | |
b185a352 VS |
1418 | type = bxt_get_dimm_type(val); |
1419 | ||
1420 | WARN_ON(type != INTEL_DRAM_UNKNOWN && | |
1421 | dram_info->type != INTEL_DRAM_UNKNOWN && | |
1422 | dram_info->type != type); | |
a62819a3 | 1423 | |
b185a352 | 1424 | DRM_DEBUG_KMS("CH%u DIMM size: %u GB, width: X%u, ranks: %u, type: %s\n", |
a62819a3 | 1425 | i - BXT_D_CR_DRP0_DUNIT_START, |
b185a352 VS |
1426 | dimm.size, dimm.width, dimm.ranks, |
1427 | intel_dram_type_str(type)); | |
cbfa59d4 MK |
1428 | |
1429 | /* | |
1430 | * If any of the channel is single rank channel, | |
1431 | * worst case output will be same as if single rank | |
1432 | * memory, so consider single rank memory. | |
1433 | */ | |
80373fb6 | 1434 | if (dram_info->ranks == 0) |
a62819a3 VS |
1435 | dram_info->ranks = dimm.ranks; |
1436 | else if (dimm.ranks == 1) | |
80373fb6 | 1437 | dram_info->ranks = 1; |
b185a352 VS |
1438 | |
1439 | if (type != INTEL_DRAM_UNKNOWN) | |
1440 | dram_info->type = type; | |
cbfa59d4 MK |
1441 | } |
1442 | ||
b185a352 VS |
1443 | if (dram_info->type == INTEL_DRAM_UNKNOWN || |
1444 | dram_info->ranks == 0) { | |
1445 | DRM_INFO("couldn't get memory information\n"); | |
cbfa59d4 MK |
1446 | return -EINVAL; |
1447 | } | |
1448 | ||
1449 | dram_info->valid = true; | |
1450 | return 0; | |
1451 | } | |
1452 | ||
1453 | static void | |
1454 | intel_get_dram_info(struct drm_i915_private *dev_priv) | |
1455 | { | |
1456 | struct dram_info *dram_info = &dev_priv->dram_info; | |
1457 | int ret; | |
1458 | ||
5d6f36b2 VS |
1459 | /* |
1460 | * Assume 16Gb DIMMs are present until proven otherwise. | |
1461 | * This is only used for the level 0 watermark latency | |
1462 | * w/a which does not apply to bxt/glk. | |
1463 | */ | |
1464 | dram_info->is_16gb_dimm = !IS_GEN9_LP(dev_priv); | |
1465 | ||
331ecded | 1466 | if (INTEL_GEN(dev_priv) < 9) |
cbfa59d4 MK |
1467 | return; |
1468 | ||
331ecded | 1469 | if (IS_GEN9_LP(dev_priv)) |
5771caf8 | 1470 | ret = bxt_get_dram_info(dev_priv); |
5771caf8 | 1471 | else |
6d9c1e92 | 1472 | ret = skl_get_dram_info(dev_priv); |
cbfa59d4 MK |
1473 | if (ret) |
1474 | return; | |
1475 | ||
30a533e5 VS |
1476 | DRM_DEBUG_KMS("DRAM bandwidth: %u kBps, channels: %u\n", |
1477 | dram_info->bandwidth_kbps, | |
1478 | dram_info->num_channels); | |
1479 | ||
54561b23 | 1480 | DRM_DEBUG_KMS("DRAM ranks: %u, 16Gb DIMMs: %s\n", |
80373fb6 | 1481 | dram_info->ranks, yesno(dram_info->is_16gb_dimm)); |
cbfa59d4 MK |
1482 | } |
1483 | ||
f6ac993f DCS |
1484 | static u32 gen9_edram_size_mb(struct drm_i915_private *dev_priv, u32 cap) |
1485 | { | |
1486 | const unsigned int ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 }; | |
1487 | const unsigned int sets[4] = { 1, 1, 2, 2 }; | |
1488 | ||
1489 | return EDRAM_NUM_BANKS(cap) * | |
1490 | ways[EDRAM_WAYS_IDX(cap)] * | |
1491 | sets[EDRAM_SETS_IDX(cap)]; | |
1492 | } | |
1493 | ||
1494 | static void edram_detect(struct drm_i915_private *dev_priv) | |
1495 | { | |
1496 | u32 edram_cap = 0; | |
1497 | ||
1498 | if (!(IS_HASWELL(dev_priv) || | |
1499 | IS_BROADWELL(dev_priv) || | |
1500 | INTEL_GEN(dev_priv) >= 9)) | |
1501 | return; | |
1502 | ||
1503 | edram_cap = __raw_uncore_read32(&dev_priv->uncore, HSW_EDRAM_CAP); | |
1504 | ||
1505 | /* NB: We can't write IDICR yet because we don't have gt funcs set up */ | |
1506 | ||
1507 | if (!(edram_cap & EDRAM_ENABLED)) | |
1508 | return; | |
1509 | ||
1510 | /* | |
1511 | * The needed capability bits for size calculation are not there with | |
1512 | * pre gen9 so return 128MB always. | |
1513 | */ | |
1514 | if (INTEL_GEN(dev_priv) < 9) | |
1515 | dev_priv->edram_size_mb = 128; | |
1516 | else | |
1517 | dev_priv->edram_size_mb = | |
1518 | gen9_edram_size_mb(dev_priv, edram_cap); | |
1519 | ||
1520 | DRM_INFO("Found %uMB of eDRAM\n", dev_priv->edram_size_mb); | |
1521 | } | |
1522 | ||
0673ad47 | 1523 | /** |
0b61b8b0 | 1524 | * i915_driver_hw_probe - setup state requiring device access |
0673ad47 CW |
1525 | * @dev_priv: device private |
1526 | * | |
1527 | * Setup state that requires accessing the device, but doesn't require | |
1528 | * exposing the driver via kernel internal or userspace interfaces. | |
1529 | */ | |
0b61b8b0 | 1530 | static int i915_driver_hw_probe(struct drm_i915_private *dev_priv) |
0673ad47 | 1531 | { |
52a05c30 | 1532 | struct pci_dev *pdev = dev_priv->drm.pdev; |
0673ad47 CW |
1533 | int ret; |
1534 | ||
f2db53f1 | 1535 | if (i915_inject_probe_failure()) |
0673ad47 CW |
1536 | return -ENODEV; |
1537 | ||
1400cc7e | 1538 | intel_device_info_runtime_init(dev_priv); |
94b4f3ba | 1539 | |
4bdafb9d CW |
1540 | if (HAS_PPGTT(dev_priv)) { |
1541 | if (intel_vgpu_active(dev_priv) && | |
ca6ac684 | 1542 | !intel_vgpu_has_full_ppgtt(dev_priv)) { |
4bdafb9d CW |
1543 | i915_report_error(dev_priv, |
1544 | "incompatible vGPU found, support for isolated ppGTT required\n"); | |
1545 | return -ENXIO; | |
1546 | } | |
1547 | } | |
1548 | ||
46592892 CW |
1549 | if (HAS_EXECLISTS(dev_priv)) { |
1550 | /* | |
1551 | * Older GVT emulation depends upon intercepting CSB mmio, | |
1552 | * which we no longer use, preferring to use the HWSP cache | |
1553 | * instead. | |
1554 | */ | |
1555 | if (intel_vgpu_active(dev_priv) && | |
1556 | !intel_vgpu_has_hwsp_emulation(dev_priv)) { | |
1557 | i915_report_error(dev_priv, | |
1558 | "old vGPU host found, support for HWSP emulation required\n"); | |
1559 | return -ENXIO; | |
1560 | } | |
1561 | } | |
1562 | ||
94b4f3ba | 1563 | intel_sanitize_options(dev_priv); |
0673ad47 | 1564 | |
f6ac993f DCS |
1565 | /* needs to be done before ggtt probe */ |
1566 | edram_detect(dev_priv); | |
1567 | ||
9f9b2792 LL |
1568 | i915_perf_init(dev_priv); |
1569 | ||
97d6d7ab | 1570 | ret = i915_ggtt_probe_hw(dev_priv); |
0673ad47 | 1571 | if (ret) |
9f172f6f | 1572 | goto err_perf; |
0673ad47 | 1573 | |
9f172f6f CW |
1574 | /* |
1575 | * WARNING: Apparently we must kick fbdev drivers before vgacon, | |
1576 | * otherwise the vga fbdev driver falls over. | |
1577 | */ | |
0673ad47 CW |
1578 | ret = i915_kick_out_firmware_fb(dev_priv); |
1579 | if (ret) { | |
1580 | DRM_ERROR("failed to remove conflicting framebuffer drivers\n"); | |
9f172f6f | 1581 | goto err_ggtt; |
0673ad47 CW |
1582 | } |
1583 | ||
c6b38fbb | 1584 | ret = vga_remove_vgacon(pdev); |
0673ad47 CW |
1585 | if (ret) { |
1586 | DRM_ERROR("failed to remove conflicting VGA console\n"); | |
9f172f6f | 1587 | goto err_ggtt; |
0673ad47 CW |
1588 | } |
1589 | ||
97d6d7ab | 1590 | ret = i915_ggtt_init_hw(dev_priv); |
0088e522 | 1591 | if (ret) |
9f172f6f | 1592 | goto err_ggtt; |
0088e522 | 1593 | |
d8a44248 TU |
1594 | intel_gt_init_hw(dev_priv); |
1595 | ||
97d6d7ab | 1596 | ret = i915_ggtt_enable_hw(dev_priv); |
0088e522 CW |
1597 | if (ret) { |
1598 | DRM_ERROR("failed to enable GGTT\n"); | |
9f172f6f | 1599 | goto err_ggtt; |
0088e522 CW |
1600 | } |
1601 | ||
52a05c30 | 1602 | pci_set_master(pdev); |
0673ad47 CW |
1603 | |
1604 | /* overlay on gen2 is broken and can't address above 1G */ | |
cf819eff | 1605 | if (IS_GEN(dev_priv, 2)) { |
52a05c30 | 1606 | ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30)); |
0673ad47 CW |
1607 | if (ret) { |
1608 | DRM_ERROR("failed to set DMA mask\n"); | |
1609 | ||
9f172f6f | 1610 | goto err_ggtt; |
0673ad47 CW |
1611 | } |
1612 | } | |
1613 | ||
0673ad47 CW |
1614 | /* 965GM sometimes incorrectly writes to hardware status page (HWS) |
1615 | * using 32bit addressing, overwriting memory if HWS is located | |
1616 | * above 4GB. | |
1617 | * | |
1618 | * The documentation also mentions an issue with undefined | |
1619 | * behaviour if any general state is accessed within a page above 4GB, | |
1620 | * which also needs to be handled carefully. | |
1621 | */ | |
c0f86832 | 1622 | if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) { |
52a05c30 | 1623 | ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); |
0673ad47 CW |
1624 | |
1625 | if (ret) { | |
1626 | DRM_ERROR("failed to set DMA mask\n"); | |
1627 | ||
9f172f6f | 1628 | goto err_ggtt; |
0673ad47 CW |
1629 | } |
1630 | } | |
1631 | ||
0673ad47 CW |
1632 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, |
1633 | PM_QOS_DEFAULT_VALUE); | |
1634 | ||
19e0a8d4 DCS |
1635 | /* BIOS often leaves RC6 enabled, but disable it for hw init */ |
1636 | intel_sanitize_gt_powersave(dev_priv); | |
0673ad47 | 1637 | |
25d140fa | 1638 | intel_gt_init_workarounds(dev_priv); |
0673ad47 CW |
1639 | |
1640 | /* On the 945G/GM, the chipset reports the MSI capability on the | |
1641 | * integrated graphics even though the support isn't actually there | |
1642 | * according to the published specs. It doesn't appear to function | |
1643 | * correctly in testing on 945G. | |
1644 | * This may be a side effect of MSI having been made available for PEG | |
1645 | * and the registers being closely associated. | |
1646 | * | |
1647 | * According to chipset errata, on the 965GM, MSI interrupts may | |
e38c2da0 VS |
1648 | * be lost or delayed, and was defeatured. MSI interrupts seem to |
1649 | * get lost on g4x as well, and interrupt delivery seems to stay | |
1650 | * properly dead afterwards. So we'll just disable them for all | |
1651 | * pre-gen5 chipsets. | |
8a29c778 LDM |
1652 | * |
1653 | * dp aux and gmbus irq on gen4 seems to be able to generate legacy | |
1654 | * interrupts even when in MSI mode. This results in spurious | |
1655 | * interrupt warnings if the legacy irq no. is shared with another | |
1656 | * device. The kernel then disables that interrupt source and so | |
1657 | * prevents the other device from working properly. | |
0673ad47 | 1658 | */ |
e38c2da0 | 1659 | if (INTEL_GEN(dev_priv) >= 5) { |
52a05c30 | 1660 | if (pci_enable_msi(pdev) < 0) |
0673ad47 CW |
1661 | DRM_DEBUG_DRIVER("can't enable MSI"); |
1662 | } | |
1663 | ||
26f837e8 ZW |
1664 | ret = intel_gvt_init(dev_priv); |
1665 | if (ret) | |
7ab87ede CW |
1666 | goto err_msi; |
1667 | ||
1668 | intel_opregion_setup(dev_priv); | |
cbfa59d4 MK |
1669 | /* |
1670 | * Fill the dram structure to get the system raw bandwidth and | |
1671 | * dram info. This will be used for memory latency calculation. | |
1672 | */ | |
1673 | intel_get_dram_info(dev_priv); | |
1674 | ||
c457d9cf | 1675 | intel_bw_init_hw(dev_priv); |
26f837e8 | 1676 | |
0673ad47 CW |
1677 | return 0; |
1678 | ||
7ab87ede CW |
1679 | err_msi: |
1680 | if (pdev->msi_enabled) | |
1681 | pci_disable_msi(pdev); | |
1682 | pm_qos_remove_request(&dev_priv->pm_qos); | |
9f172f6f | 1683 | err_ggtt: |
3b58a945 | 1684 | i915_ggtt_driver_release(dev_priv); |
9f172f6f CW |
1685 | err_perf: |
1686 | i915_perf_fini(dev_priv); | |
0673ad47 CW |
1687 | return ret; |
1688 | } | |
1689 | ||
1690 | /** | |
78dae1ac | 1691 | * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe() |
0673ad47 CW |
1692 | * @dev_priv: device private |
1693 | */ | |
78dae1ac | 1694 | static void i915_driver_hw_remove(struct drm_i915_private *dev_priv) |
0673ad47 | 1695 | { |
52a05c30 | 1696 | struct pci_dev *pdev = dev_priv->drm.pdev; |
0673ad47 | 1697 | |
9f9b2792 LL |
1698 | i915_perf_fini(dev_priv); |
1699 | ||
52a05c30 DW |
1700 | if (pdev->msi_enabled) |
1701 | pci_disable_msi(pdev); | |
0673ad47 CW |
1702 | |
1703 | pm_qos_remove_request(&dev_priv->pm_qos); | |
0673ad47 CW |
1704 | } |
1705 | ||
1706 | /** | |
1707 | * i915_driver_register - register the driver with the rest of the system | |
1708 | * @dev_priv: device private | |
1709 | * | |
1710 | * Perform any steps necessary to make the driver available via kernel | |
1711 | * internal or userspace interfaces. | |
1712 | */ | |
1713 | static void i915_driver_register(struct drm_i915_private *dev_priv) | |
1714 | { | |
91c8a326 | 1715 | struct drm_device *dev = &dev_priv->drm; |
0673ad47 | 1716 | |
848b365d | 1717 | i915_gem_shrinker_register(dev_priv); |
b46a33e2 | 1718 | i915_pmu_register(dev_priv); |
0673ad47 CW |
1719 | |
1720 | /* | |
1721 | * Notify a valid surface after modesetting, | |
1722 | * when running inside a VM. | |
1723 | */ | |
1724 | if (intel_vgpu_active(dev_priv)) | |
1725 | I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY); | |
1726 | ||
1727 | /* Reveal our presence to userspace */ | |
1728 | if (drm_dev_register(dev, 0) == 0) { | |
1729 | i915_debugfs_register(dev_priv); | |
694c2828 | 1730 | i915_setup_sysfs(dev_priv); |
442b8c06 RB |
1731 | |
1732 | /* Depends on sysfs having been initialized */ | |
1733 | i915_perf_register(dev_priv); | |
0673ad47 CW |
1734 | } else |
1735 | DRM_ERROR("Failed to register driver for userspace access!\n"); | |
1736 | ||
e1bf094b | 1737 | if (HAS_DISPLAY(dev_priv)) { |
0673ad47 CW |
1738 | /* Must be done after probing outputs */ |
1739 | intel_opregion_register(dev_priv); | |
1740 | acpi_video_register(); | |
1741 | } | |
1742 | ||
cf819eff | 1743 | if (IS_GEN(dev_priv, 5)) |
0673ad47 CW |
1744 | intel_gpu_ips_init(dev_priv); |
1745 | ||
eef57324 | 1746 | intel_audio_init(dev_priv); |
0673ad47 CW |
1747 | |
1748 | /* | |
1749 | * Some ports require correctly set-up hpd registers for detection to | |
1750 | * work properly (leading to ghost connected connector status), e.g. VGA | |
1751 | * on gm45. Hence we can only set up the initial fbdev config after hpd | |
1752 | * irqs are fully enabled. We do it last so that the async config | |
1753 | * cannot run before the connectors are registered. | |
1754 | */ | |
1755 | intel_fbdev_initial_config_async(dev); | |
448aa911 CW |
1756 | |
1757 | /* | |
1758 | * We need to coordinate the hotplugs with the asynchronous fbdev | |
1759 | * configuration, for which we use the fbdev->async_cookie. | |
1760 | */ | |
e1bf094b | 1761 | if (HAS_DISPLAY(dev_priv)) |
448aa911 | 1762 | drm_kms_helper_poll_init(dev); |
07d80572 | 1763 | |
2cd9a689 | 1764 | intel_power_domains_enable(dev_priv); |
69c66355 | 1765 | intel_runtime_pm_enable(&dev_priv->runtime_pm); |
0673ad47 CW |
1766 | } |
1767 | ||
1768 | /** | |
1769 | * i915_driver_unregister - cleanup the registration done in i915_driver_regiser() | |
1770 | * @dev_priv: device private | |
1771 | */ | |
1772 | static void i915_driver_unregister(struct drm_i915_private *dev_priv) | |
1773 | { | |
69c66355 | 1774 | intel_runtime_pm_disable(&dev_priv->runtime_pm); |
2cd9a689 | 1775 | intel_power_domains_disable(dev_priv); |
07d80572 | 1776 | |
4f256d82 | 1777 | intel_fbdev_unregister(dev_priv); |
eef57324 | 1778 | intel_audio_deinit(dev_priv); |
0673ad47 | 1779 | |
448aa911 CW |
1780 | /* |
1781 | * After flushing the fbdev (incl. a late async config which will | |
1782 | * have delayed queuing of a hotplug event), then flush the hotplug | |
1783 | * events. | |
1784 | */ | |
1785 | drm_kms_helper_poll_fini(&dev_priv->drm); | |
1786 | ||
0673ad47 CW |
1787 | intel_gpu_ips_teardown(); |
1788 | acpi_video_unregister(); | |
1789 | intel_opregion_unregister(dev_priv); | |
1790 | ||
442b8c06 | 1791 | i915_perf_unregister(dev_priv); |
b46a33e2 | 1792 | i915_pmu_unregister(dev_priv); |
442b8c06 | 1793 | |
694c2828 | 1794 | i915_teardown_sysfs(dev_priv); |
d69990e0 | 1795 | drm_dev_unplug(&dev_priv->drm); |
0673ad47 | 1796 | |
848b365d | 1797 | i915_gem_shrinker_unregister(dev_priv); |
0673ad47 CW |
1798 | } |
1799 | ||
27d558a1 MW |
1800 | static void i915_welcome_messages(struct drm_i915_private *dev_priv) |
1801 | { | |
1802 | if (drm_debug & DRM_UT_DRIVER) { | |
1803 | struct drm_printer p = drm_debug_printer("i915 device info:"); | |
1804 | ||
805446c8 | 1805 | drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n", |
1787a984 JN |
1806 | INTEL_DEVID(dev_priv), |
1807 | INTEL_REVID(dev_priv), | |
1808 | intel_platform_name(INTEL_INFO(dev_priv)->platform), | |
805446c8 TU |
1809 | intel_subplatform(RUNTIME_INFO(dev_priv), |
1810 | INTEL_INFO(dev_priv)->platform), | |
1787a984 JN |
1811 | INTEL_GEN(dev_priv)); |
1812 | ||
1813 | intel_device_info_dump_flags(INTEL_INFO(dev_priv), &p); | |
0258404f | 1814 | intel_device_info_dump_runtime(RUNTIME_INFO(dev_priv), &p); |
27d558a1 MW |
1815 | } |
1816 | ||
1817 | if (IS_ENABLED(CONFIG_DRM_I915_DEBUG)) | |
1818 | DRM_INFO("DRM_I915_DEBUG enabled\n"); | |
1819 | if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) | |
1820 | DRM_INFO("DRM_I915_DEBUG_GEM enabled\n"); | |
6dfc4a8f ID |
1821 | if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) |
1822 | DRM_INFO("DRM_I915_DEBUG_RUNTIME_PM enabled\n"); | |
27d558a1 MW |
1823 | } |
1824 | ||
55ac5a16 CW |
1825 | static struct drm_i915_private * |
1826 | i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent) | |
1827 | { | |
1828 | const struct intel_device_info *match_info = | |
1829 | (struct intel_device_info *)ent->driver_data; | |
1830 | struct intel_device_info *device_info; | |
1831 | struct drm_i915_private *i915; | |
2ddcc982 | 1832 | int err; |
55ac5a16 CW |
1833 | |
1834 | i915 = kzalloc(sizeof(*i915), GFP_KERNEL); | |
1835 | if (!i915) | |
2ddcc982 | 1836 | return ERR_PTR(-ENOMEM); |
55ac5a16 | 1837 | |
2ddcc982 AS |
1838 | err = drm_dev_init(&i915->drm, &driver, &pdev->dev); |
1839 | if (err) { | |
55ac5a16 | 1840 | kfree(i915); |
2ddcc982 | 1841 | return ERR_PTR(err); |
55ac5a16 CW |
1842 | } |
1843 | ||
1844 | i915->drm.pdev = pdev; | |
1845 | i915->drm.dev_private = i915; | |
1846 | pci_set_drvdata(pdev, &i915->drm); | |
1847 | ||
1848 | /* Setup the write-once "constant" device info */ | |
1849 | device_info = mkwrite_device_info(i915); | |
1850 | memcpy(device_info, match_info, sizeof(*device_info)); | |
0258404f | 1851 | RUNTIME_INFO(i915)->device_id = pdev->device; |
55ac5a16 | 1852 | |
74f6e183 | 1853 | BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask)); |
55ac5a16 CW |
1854 | |
1855 | return i915; | |
1856 | } | |
1857 | ||
31962ca6 CW |
1858 | static void i915_driver_destroy(struct drm_i915_private *i915) |
1859 | { | |
1860 | struct pci_dev *pdev = i915->drm.pdev; | |
1861 | ||
1862 | drm_dev_fini(&i915->drm); | |
1863 | kfree(i915); | |
1864 | ||
1865 | /* And make sure we never chase our dangling pointer from pci_dev */ | |
1866 | pci_set_drvdata(pdev, NULL); | |
1867 | } | |
1868 | ||
0673ad47 | 1869 | /** |
b01558e5 | 1870 | * i915_driver_probe - setup chip and create an initial config |
d2ad3ae4 JL |
1871 | * @pdev: PCI device |
1872 | * @ent: matching PCI ID entry | |
0673ad47 | 1873 | * |
b01558e5 | 1874 | * The driver probe routine has to do several things: |
0673ad47 CW |
1875 | * - drive output discovery via intel_modeset_init() |
1876 | * - initialize the memory manager | |
1877 | * - allocate initial config memory | |
1878 | * - setup the DRM framebuffer with the allocated memory | |
1879 | */ | |
b01558e5 | 1880 | int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
0673ad47 | 1881 | { |
8d2b47dd ML |
1882 | const struct intel_device_info *match_info = |
1883 | (struct intel_device_info *)ent->driver_data; | |
0673ad47 CW |
1884 | struct drm_i915_private *dev_priv; |
1885 | int ret; | |
7d87a7f7 | 1886 | |
55ac5a16 | 1887 | dev_priv = i915_driver_create(pdev, ent); |
2ddcc982 AS |
1888 | if (IS_ERR(dev_priv)) |
1889 | return PTR_ERR(dev_priv); | |
719388e1 | 1890 | |
1feb64c4 VS |
1891 | /* Disable nuclear pageflip by default on pre-ILK */ |
1892 | if (!i915_modparams.nuclear_pageflip && match_info->gen < 5) | |
1893 | dev_priv->drm.driver_features &= ~DRIVER_ATOMIC; | |
1894 | ||
0673ad47 CW |
1895 | ret = pci_enable_device(pdev); |
1896 | if (ret) | |
cad3688f | 1897 | goto out_fini; |
1347f5b4 | 1898 | |
0b61b8b0 | 1899 | ret = i915_driver_early_probe(dev_priv); |
0673ad47 CW |
1900 | if (ret < 0) |
1901 | goto out_pci_disable; | |
ef11bdb3 | 1902 | |
9102650f | 1903 | disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); |
1da177e4 | 1904 | |
9e138ea1 DCS |
1905 | i915_detect_vgpu(dev_priv); |
1906 | ||
0b61b8b0 | 1907 | ret = i915_driver_mmio_probe(dev_priv); |
0673ad47 CW |
1908 | if (ret < 0) |
1909 | goto out_runtime_pm_put; | |
79e53945 | 1910 | |
0b61b8b0 | 1911 | ret = i915_driver_hw_probe(dev_priv); |
0673ad47 CW |
1912 | if (ret < 0) |
1913 | goto out_cleanup_mmio; | |
30c964a6 | 1914 | |
0b61b8b0 | 1915 | ret = i915_driver_modeset_probe(&dev_priv->drm); |
0673ad47 | 1916 | if (ret < 0) |
baf54385 | 1917 | goto out_cleanup_hw; |
0673ad47 CW |
1918 | |
1919 | i915_driver_register(dev_priv); | |
1920 | ||
9102650f | 1921 | enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); |
0673ad47 | 1922 | |
27d558a1 MW |
1923 | i915_welcome_messages(dev_priv); |
1924 | ||
0673ad47 CW |
1925 | return 0; |
1926 | ||
0673ad47 | 1927 | out_cleanup_hw: |
78dae1ac | 1928 | i915_driver_hw_remove(dev_priv); |
3b58a945 | 1929 | i915_ggtt_driver_release(dev_priv); |
19e0a8d4 DCS |
1930 | |
1931 | /* Paranoia: make sure we have disabled everything before we exit. */ | |
1932 | intel_sanitize_gt_powersave(dev_priv); | |
0673ad47 | 1933 | out_cleanup_mmio: |
3b58a945 | 1934 | i915_driver_mmio_release(dev_priv); |
0673ad47 | 1935 | out_runtime_pm_put: |
9102650f | 1936 | enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); |
3b58a945 | 1937 | i915_driver_late_release(dev_priv); |
0673ad47 CW |
1938 | out_pci_disable: |
1939 | pci_disable_device(pdev); | |
cad3688f | 1940 | out_fini: |
f2db53f1 | 1941 | i915_probe_error(dev_priv, "Device initialization failed (%d)\n", ret); |
31962ca6 | 1942 | i915_driver_destroy(dev_priv); |
30c964a6 RB |
1943 | return ret; |
1944 | } | |
1945 | ||
b01558e5 | 1946 | void i915_driver_remove(struct drm_device *dev) |
3bad0781 | 1947 | { |
fac5e23e | 1948 | struct drm_i915_private *dev_priv = to_i915(dev); |
52a05c30 | 1949 | struct pci_dev *pdev = dev_priv->drm.pdev; |
3bad0781 | 1950 | |
9102650f | 1951 | disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); |
07d80572 | 1952 | |
99c539be DV |
1953 | i915_driver_unregister(dev_priv); |
1954 | ||
141f3767 JK |
1955 | /* |
1956 | * After unregistering the device to prevent any new users, cancel | |
1957 | * all in-flight requests so that we can quickly unbind the active | |
1958 | * resources. | |
1959 | */ | |
cb823ed9 | 1960 | intel_gt_set_wedged(&dev_priv->gt); |
141f3767 | 1961 | |
4a8ab5ea CW |
1962 | /* Flush any external code that still may be under the RCU lock */ |
1963 | synchronize_rcu(); | |
1964 | ||
5861b013 | 1965 | i915_gem_suspend(dev_priv); |
ce1bb329 | 1966 | |
18dddadc | 1967 | drm_atomic_helper_shutdown(dev); |
a667fb40 | 1968 | |
78dae1ac | 1969 | intel_gvt_driver_remove(dev_priv); |
26f837e8 | 1970 | |
78dae1ac | 1971 | intel_modeset_driver_remove(dev); |
0673ad47 | 1972 | |
78dae1ac | 1973 | intel_bios_driver_remove(dev_priv); |
3bad0781 | 1974 | |
52a05c30 DW |
1975 | vga_switcheroo_unregister_client(pdev); |
1976 | vga_client_register(pdev, NULL, NULL, NULL); | |
bcdb72ac | 1977 | |
0673ad47 | 1978 | intel_csr_ucode_fini(dev_priv); |
bcdb72ac | 1979 | |
0673ad47 | 1980 | /* Free error state after interrupts are fully disabled. */ |
cb823ed9 | 1981 | cancel_delayed_work_sync(&dev_priv->gt.hangcheck.work); |
5a4c6f1b | 1982 | i915_reset_error_state(dev_priv); |
0673ad47 | 1983 | |
78dae1ac | 1984 | i915_gem_driver_remove(dev_priv); |
0673ad47 | 1985 | |
78dae1ac | 1986 | intel_power_domains_driver_remove(dev_priv); |
0673ad47 | 1987 | |
78dae1ac | 1988 | i915_driver_hw_remove(dev_priv); |
0673ad47 | 1989 | |
9102650f | 1990 | enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); |
cad3688f CW |
1991 | } |
1992 | ||
1993 | static void i915_driver_release(struct drm_device *dev) | |
1994 | { | |
1995 | struct drm_i915_private *dev_priv = to_i915(dev); | |
69c66355 | 1996 | struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; |
0673ad47 | 1997 | |
69c66355 | 1998 | disable_rpm_wakeref_asserts(rpm); |
47bc28d7 | 1999 | |
3b58a945 | 2000 | i915_gem_driver_release(dev_priv); |
47bc28d7 | 2001 | |
3b58a945 | 2002 | i915_ggtt_driver_release(dev_priv); |
19e0a8d4 DCS |
2003 | |
2004 | /* Paranoia: make sure we have disabled everything before we exit. */ | |
2005 | intel_sanitize_gt_powersave(dev_priv); | |
2006 | ||
3b58a945 | 2007 | i915_driver_mmio_release(dev_priv); |
47bc28d7 | 2008 | |
69c66355 | 2009 | enable_rpm_wakeref_asserts(rpm); |
3b58a945 | 2010 | intel_runtime_pm_driver_release(rpm); |
47bc28d7 | 2011 | |
3b58a945 | 2012 | i915_driver_late_release(dev_priv); |
31962ca6 | 2013 | i915_driver_destroy(dev_priv); |
3bad0781 ZW |
2014 | } |
2015 | ||
0673ad47 | 2016 | static int i915_driver_open(struct drm_device *dev, struct drm_file *file) |
2911a35b | 2017 | { |
829a0af2 | 2018 | struct drm_i915_private *i915 = to_i915(dev); |
0673ad47 | 2019 | int ret; |
2911a35b | 2020 | |
829a0af2 | 2021 | ret = i915_gem_open(i915, file); |
0673ad47 CW |
2022 | if (ret) |
2023 | return ret; | |
2911a35b | 2024 | |
0673ad47 CW |
2025 | return 0; |
2026 | } | |
71386ef9 | 2027 | |
0673ad47 CW |
2028 | /** |
2029 | * i915_driver_lastclose - clean up after all DRM clients have exited | |
2030 | * @dev: DRM device | |
2031 | * | |
2032 | * Take care of cleaning up after all DRM clients have exited. In the | |
2033 | * mode setting case, we want to restore the kernel's initial mode (just | |
2034 | * in case the last client left us in a bad state). | |
2035 | * | |
2036 | * Additionally, in the non-mode setting case, we'll tear down the GTT | |
2037 | * and DMA structures, since the kernel won't be using them, and clea | |
2038 | * up any GEM state. | |
2039 | */ | |
2040 | static void i915_driver_lastclose(struct drm_device *dev) | |
2041 | { | |
2042 | intel_fbdev_restore_mode(dev); | |
2043 | vga_switcheroo_process_delayed_switch(); | |
2044 | } | |
2911a35b | 2045 | |
7d2ec881 | 2046 | static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) |
0673ad47 | 2047 | { |
7d2ec881 DV |
2048 | struct drm_i915_file_private *file_priv = file->driver_priv; |
2049 | ||
0673ad47 | 2050 | mutex_lock(&dev->struct_mutex); |
829a0af2 | 2051 | i915_gem_context_close(file); |
0673ad47 CW |
2052 | i915_gem_release(dev, file); |
2053 | mutex_unlock(&dev->struct_mutex); | |
0673ad47 CW |
2054 | |
2055 | kfree(file_priv); | |
2911a35b BW |
2056 | } |
2057 | ||
07f9cd0b ID |
2058 | static void intel_suspend_encoders(struct drm_i915_private *dev_priv) |
2059 | { | |
91c8a326 | 2060 | struct drm_device *dev = &dev_priv->drm; |
19c8054c | 2061 | struct intel_encoder *encoder; |
07f9cd0b ID |
2062 | |
2063 | drm_modeset_lock_all(dev); | |
19c8054c JN |
2064 | for_each_intel_encoder(dev, encoder) |
2065 | if (encoder->suspend) | |
2066 | encoder->suspend(encoder); | |
07f9cd0b ID |
2067 | drm_modeset_unlock_all(dev); |
2068 | } | |
2069 | ||
1a5df187 PZ |
2070 | static int vlv_resume_prepare(struct drm_i915_private *dev_priv, |
2071 | bool rpm_resume); | |
507e126e | 2072 | static int vlv_suspend_complete(struct drm_i915_private *dev_priv); |
f75a1985 | 2073 | |
bc87229f ID |
2074 | static bool suspend_to_idle(struct drm_i915_private *dev_priv) |
2075 | { | |
2076 | #if IS_ENABLED(CONFIG_ACPI_SLEEP) | |
2077 | if (acpi_target_system_state() < ACPI_STATE_S3) | |
2078 | return true; | |
2079 | #endif | |
2080 | return false; | |
2081 | } | |
ebc32824 | 2082 | |
73b66f87 CW |
2083 | static int i915_drm_prepare(struct drm_device *dev) |
2084 | { | |
2085 | struct drm_i915_private *i915 = to_i915(dev); | |
73b66f87 CW |
2086 | |
2087 | /* | |
2088 | * NB intel_display_suspend() may issue new requests after we've | |
2089 | * ostensibly marked the GPU as ready-to-sleep here. We need to | |
2090 | * split out that work and pull it forward so that after point, | |
2091 | * the GPU is not woken again. | |
2092 | */ | |
5861b013 | 2093 | i915_gem_suspend(i915); |
73b66f87 | 2094 | |
5861b013 | 2095 | return 0; |
73b66f87 CW |
2096 | } |
2097 | ||
5e365c39 | 2098 | static int i915_drm_suspend(struct drm_device *dev) |
ba8bbcf6 | 2099 | { |
fac5e23e | 2100 | struct drm_i915_private *dev_priv = to_i915(dev); |
52a05c30 | 2101 | struct pci_dev *pdev = dev_priv->drm.pdev; |
e5747e3a | 2102 | pci_power_t opregion_target_state; |
61caf87c | 2103 | |
9102650f | 2104 | disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); |
1f814dac | 2105 | |
c67a470b PZ |
2106 | /* We do a lot of poking in a lot of registers, make sure they work |
2107 | * properly. */ | |
2cd9a689 | 2108 | intel_power_domains_disable(dev_priv); |
cb10799c | 2109 | |
5bcf719b DA |
2110 | drm_kms_helper_poll_disable(dev); |
2111 | ||
52a05c30 | 2112 | pci_save_state(pdev); |
ba8bbcf6 | 2113 | |
6b72d486 | 2114 | intel_display_suspend(dev); |
2eb5252e | 2115 | |
1a4313d1 | 2116 | intel_dp_mst_suspend(dev_priv); |
7d708ee4 | 2117 | |
d5818938 DV |
2118 | intel_runtime_pm_disable_interrupts(dev_priv); |
2119 | intel_hpd_cancel_work(dev_priv); | |
09b64267 | 2120 | |
d5818938 | 2121 | intel_suspend_encoders(dev_priv); |
0e32b39c | 2122 | |
712bf364 | 2123 | intel_suspend_hw(dev_priv); |
5669fcac | 2124 | |
275a991c | 2125 | i915_gem_suspend_gtt_mappings(dev_priv); |
828c7908 | 2126 | |
af6dc742 | 2127 | i915_save_state(dev_priv); |
9e06dd39 | 2128 | |
bc87229f | 2129 | opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold; |
a950adc6 | 2130 | intel_opregion_suspend(dev_priv, opregion_target_state); |
8ee1c3db | 2131 | |
82e3b8c1 | 2132 | intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true); |
3fa016a0 | 2133 | |
62d5d69b MK |
2134 | dev_priv->suspend_count++; |
2135 | ||
f74ed08d | 2136 | intel_csr_ucode_suspend(dev_priv); |
f514c2d8 | 2137 | |
9102650f | 2138 | enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); |
1f814dac | 2139 | |
73b66f87 | 2140 | return 0; |
84b79f8d RW |
2141 | } |
2142 | ||
2cd9a689 ID |
2143 | static enum i915_drm_suspend_mode |
2144 | get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate) | |
2145 | { | |
2146 | if (hibernate) | |
2147 | return I915_DRM_SUSPEND_HIBERNATE; | |
2148 | ||
2149 | if (suspend_to_idle(dev_priv)) | |
2150 | return I915_DRM_SUSPEND_IDLE; | |
2151 | ||
2152 | return I915_DRM_SUSPEND_MEM; | |
2153 | } | |
2154 | ||
c49d13ee | 2155 | static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) |
c3c09c95 | 2156 | { |
c49d13ee | 2157 | struct drm_i915_private *dev_priv = to_i915(dev); |
52a05c30 | 2158 | struct pci_dev *pdev = dev_priv->drm.pdev; |
69c66355 | 2159 | struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; |
c3c09c95 ID |
2160 | int ret; |
2161 | ||
69c66355 | 2162 | disable_rpm_wakeref_asserts(rpm); |
1f814dac | 2163 | |
ec92ad00 CW |
2164 | i915_gem_suspend_late(dev_priv); |
2165 | ||
f7de5027 | 2166 | intel_uncore_suspend(&dev_priv->uncore); |
4c494a57 | 2167 | |
2cd9a689 ID |
2168 | intel_power_domains_suspend(dev_priv, |
2169 | get_suspend_mode(dev_priv, hibernation)); | |
73dfc227 | 2170 | |
507e126e | 2171 | ret = 0; |
3b6ac43b | 2172 | if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) |
507e126e | 2173 | bxt_enable_dc9(dev_priv); |
b8aea3d1 | 2174 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
507e126e ID |
2175 | hsw_enable_pc8(dev_priv); |
2176 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
2177 | ret = vlv_suspend_complete(dev_priv); | |
c3c09c95 ID |
2178 | |
2179 | if (ret) { | |
2180 | DRM_ERROR("Suspend complete failed: %d\n", ret); | |
2cd9a689 | 2181 | intel_power_domains_resume(dev_priv); |
c3c09c95 | 2182 | |
1f814dac | 2183 | goto out; |
c3c09c95 ID |
2184 | } |
2185 | ||
52a05c30 | 2186 | pci_disable_device(pdev); |
ab3be73f | 2187 | /* |
54875571 | 2188 | * During hibernation on some platforms the BIOS may try to access |
ab3be73f ID |
2189 | * the device even though it's already in D3 and hang the machine. So |
2190 | * leave the device in D0 on those platforms and hope the BIOS will | |
54875571 ID |
2191 | * power down the device properly. The issue was seen on multiple old |
2192 | * GENs with different BIOS vendors, so having an explicit blacklist | |
2193 | * is inpractical; apply the workaround on everything pre GEN6. The | |
2194 | * platforms where the issue was seen: | |
2195 | * Lenovo Thinkpad X301, X61s, X60, T60, X41 | |
2196 | * Fujitsu FSC S7110 | |
2197 | * Acer Aspire 1830T | |
ab3be73f | 2198 | */ |
514e1d64 | 2199 | if (!(hibernation && INTEL_GEN(dev_priv) < 6)) |
52a05c30 | 2200 | pci_set_power_state(pdev, PCI_D3hot); |
c3c09c95 | 2201 | |
1f814dac | 2202 | out: |
69c66355 | 2203 | enable_rpm_wakeref_asserts(rpm); |
bd780f37 | 2204 | if (!dev_priv->uncore.user_forcewake.count) |
3b58a945 | 2205 | intel_runtime_pm_driver_release(rpm); |
1f814dac ID |
2206 | |
2207 | return ret; | |
c3c09c95 ID |
2208 | } |
2209 | ||
a9a251c2 | 2210 | static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state) |
84b79f8d RW |
2211 | { |
2212 | int error; | |
2213 | ||
ded8b07d | 2214 | if (!dev) { |
84b79f8d RW |
2215 | DRM_ERROR("dev: %p\n", dev); |
2216 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); | |
2217 | return -ENODEV; | |
2218 | } | |
2219 | ||
0b14cbd2 ID |
2220 | if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND && |
2221 | state.event != PM_EVENT_FREEZE)) | |
2222 | return -EINVAL; | |
5bcf719b DA |
2223 | |
2224 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
2225 | return 0; | |
6eecba33 | 2226 | |
5e365c39 | 2227 | error = i915_drm_suspend(dev); |
84b79f8d RW |
2228 | if (error) |
2229 | return error; | |
2230 | ||
ab3be73f | 2231 | return i915_drm_suspend_late(dev, false); |
ba8bbcf6 JB |
2232 | } |
2233 | ||
5e365c39 | 2234 | static int i915_drm_resume(struct drm_device *dev) |
76c4b250 | 2235 | { |
fac5e23e | 2236 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac840ae5 | 2237 | int ret; |
9d49c0ef | 2238 | |
9102650f | 2239 | disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); |
abc80abd | 2240 | intel_sanitize_gt_powersave(dev_priv); |
1f814dac | 2241 | |
1288786b CW |
2242 | i915_gem_sanitize(dev_priv); |
2243 | ||
97d6d7ab | 2244 | ret = i915_ggtt_enable_hw(dev_priv); |
ac840ae5 VS |
2245 | if (ret) |
2246 | DRM_ERROR("failed to re-enable GGTT\n"); | |
2247 | ||
f74ed08d ID |
2248 | intel_csr_ucode_resume(dev_priv); |
2249 | ||
af6dc742 | 2250 | i915_restore_state(dev_priv); |
8090ba8c | 2251 | intel_pps_unlock_regs_wa(dev_priv); |
61caf87c | 2252 | |
c39055b0 | 2253 | intel_init_pch_refclk(dev_priv); |
1833b134 | 2254 | |
364aece0 PA |
2255 | /* |
2256 | * Interrupts have to be enabled before any batches are run. If not the | |
2257 | * GPU will hang. i915_gem_init_hw() will initiate batches to | |
2258 | * update/restore the context. | |
2259 | * | |
908764f6 ID |
2260 | * drm_mode_config_reset() needs AUX interrupts. |
2261 | * | |
364aece0 PA |
2262 | * Modeset enabling in intel_modeset_init_hw() also needs working |
2263 | * interrupts. | |
2264 | */ | |
2265 | intel_runtime_pm_enable_interrupts(dev_priv); | |
2266 | ||
908764f6 ID |
2267 | drm_mode_config_reset(dev); |
2268 | ||
37cd3300 | 2269 | i915_gem_resume(dev_priv); |
226485e9 | 2270 | |
d5818938 | 2271 | intel_modeset_init_hw(dev); |
675f7ff3 | 2272 | intel_init_clock_gating(dev_priv); |
24576d23 | 2273 | |
d5818938 DV |
2274 | spin_lock_irq(&dev_priv->irq_lock); |
2275 | if (dev_priv->display.hpd_irq_setup) | |
91d14251 | 2276 | dev_priv->display.hpd_irq_setup(dev_priv); |
d5818938 | 2277 | spin_unlock_irq(&dev_priv->irq_lock); |
0e32b39c | 2278 | |
1a4313d1 | 2279 | intel_dp_mst_resume(dev_priv); |
e7d6f7d7 | 2280 | |
a16b7658 L |
2281 | intel_display_resume(dev); |
2282 | ||
e0b70061 L |
2283 | drm_kms_helper_poll_enable(dev); |
2284 | ||
d5818938 DV |
2285 | /* |
2286 | * ... but also need to make sure that hotplug processing | |
2287 | * doesn't cause havoc. Like in the driver load code we don't | |
c444ad79 | 2288 | * bother with the tiny race here where we might lose hotplug |
d5818938 DV |
2289 | * notifications. |
2290 | * */ | |
2291 | intel_hpd_init(dev_priv); | |
1daed3fb | 2292 | |
a950adc6 | 2293 | intel_opregion_resume(dev_priv); |
44834a67 | 2294 | |
82e3b8c1 | 2295 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false); |
073f34d9 | 2296 | |
2cd9a689 ID |
2297 | intel_power_domains_enable(dev_priv); |
2298 | ||
9102650f | 2299 | enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); |
1f814dac | 2300 | |
074c6ada | 2301 | return 0; |
84b79f8d RW |
2302 | } |
2303 | ||
5e365c39 | 2304 | static int i915_drm_resume_early(struct drm_device *dev) |
84b79f8d | 2305 | { |
fac5e23e | 2306 | struct drm_i915_private *dev_priv = to_i915(dev); |
52a05c30 | 2307 | struct pci_dev *pdev = dev_priv->drm.pdev; |
44410cd0 | 2308 | int ret; |
36d61e67 | 2309 | |
76c4b250 ID |
2310 | /* |
2311 | * We have a resume ordering issue with the snd-hda driver also | |
2312 | * requiring our device to be power up. Due to the lack of a | |
2313 | * parent/child relationship we currently solve this with an early | |
2314 | * resume hook. | |
2315 | * | |
2316 | * FIXME: This should be solved with a special hdmi sink device or | |
2317 | * similar so that power domains can be employed. | |
2318 | */ | |
44410cd0 ID |
2319 | |
2320 | /* | |
2321 | * Note that we need to set the power state explicitly, since we | |
2322 | * powered off the device during freeze and the PCI core won't power | |
2323 | * it back up for us during thaw. Powering off the device during | |
2324 | * freeze is not a hard requirement though, and during the | |
2325 | * suspend/resume phases the PCI core makes sure we get here with the | |
2326 | * device powered on. So in case we change our freeze logic and keep | |
2327 | * the device powered we can also remove the following set power state | |
2328 | * call. | |
2329 | */ | |
52a05c30 | 2330 | ret = pci_set_power_state(pdev, PCI_D0); |
44410cd0 ID |
2331 | if (ret) { |
2332 | DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret); | |
2cd9a689 | 2333 | return ret; |
44410cd0 ID |
2334 | } |
2335 | ||
2336 | /* | |
2337 | * Note that pci_enable_device() first enables any parent bridge | |
2338 | * device and only then sets the power state for this device. The | |
2339 | * bridge enabling is a nop though, since bridge devices are resumed | |
2340 | * first. The order of enabling power and enabling the device is | |
2341 | * imposed by the PCI core as described above, so here we preserve the | |
2342 | * same order for the freeze/thaw phases. | |
2343 | * | |
2344 | * TODO: eventually we should remove pci_disable_device() / | |
2345 | * pci_enable_enable_device() from suspend/resume. Due to how they | |
2346 | * depend on the device enable refcount we can't anyway depend on them | |
2347 | * disabling/enabling the device. | |
2348 | */ | |
2cd9a689 ID |
2349 | if (pci_enable_device(pdev)) |
2350 | return -EIO; | |
84b79f8d | 2351 | |
52a05c30 | 2352 | pci_set_master(pdev); |
84b79f8d | 2353 | |
9102650f | 2354 | disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); |
1f814dac | 2355 | |
666a4537 | 2356 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
1a5df187 | 2357 | ret = vlv_resume_prepare(dev_priv, false); |
36d61e67 | 2358 | if (ret) |
ff0b187f DL |
2359 | DRM_ERROR("Resume prepare failed: %d, continuing anyway\n", |
2360 | ret); | |
36d61e67 | 2361 | |
f7de5027 DCS |
2362 | intel_uncore_resume_early(&dev_priv->uncore); |
2363 | ||
eaf522f6 | 2364 | intel_gt_check_and_clear_faults(&dev_priv->gt); |
efee833a | 2365 | |
3e68928b | 2366 | if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) { |
0f90603c | 2367 | gen9_sanitize_dc_state(dev_priv); |
507e126e | 2368 | bxt_disable_dc9(dev_priv); |
da2f41d1 | 2369 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
a9a6b73a | 2370 | hsw_disable_pc8(dev_priv); |
da2f41d1 | 2371 | } |
efee833a | 2372 | |
19e0a8d4 | 2373 | intel_sanitize_gt_powersave(dev_priv); |
bc87229f | 2374 | |
2cd9a689 | 2375 | intel_power_domains_resume(dev_priv); |
bc87229f | 2376 | |
0c91621c | 2377 | intel_gt_sanitize(&dev_priv->gt, true); |
4fdd5b4e | 2378 | |
9102650f | 2379 | enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); |
6e35e8ab | 2380 | |
36d61e67 | 2381 | return ret; |
76c4b250 ID |
2382 | } |
2383 | ||
7f26cb88 | 2384 | static int i915_resume_switcheroo(struct drm_device *dev) |
76c4b250 | 2385 | { |
50a0072f | 2386 | int ret; |
76c4b250 | 2387 | |
097dd837 ID |
2388 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
2389 | return 0; | |
2390 | ||
5e365c39 | 2391 | ret = i915_drm_resume_early(dev); |
50a0072f ID |
2392 | if (ret) |
2393 | return ret; | |
2394 | ||
5a17514e ID |
2395 | return i915_drm_resume(dev); |
2396 | } | |
2397 | ||
73b66f87 CW |
2398 | static int i915_pm_prepare(struct device *kdev) |
2399 | { | |
906339a9 | 2400 | struct drm_device *dev = dev_get_drvdata(kdev); |
73b66f87 CW |
2401 | |
2402 | if (!dev) { | |
2403 | dev_err(kdev, "DRM not initialized, aborting suspend.\n"); | |
2404 | return -ENODEV; | |
2405 | } | |
2406 | ||
2407 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
2408 | return 0; | |
2409 | ||
2410 | return i915_drm_prepare(dev); | |
2411 | } | |
2412 | ||
c49d13ee | 2413 | static int i915_pm_suspend(struct device *kdev) |
112b715e | 2414 | { |
906339a9 | 2415 | struct drm_device *dev = dev_get_drvdata(kdev); |
112b715e | 2416 | |
c49d13ee DW |
2417 | if (!dev) { |
2418 | dev_err(kdev, "DRM not initialized, aborting suspend.\n"); | |
84b79f8d RW |
2419 | return -ENODEV; |
2420 | } | |
112b715e | 2421 | |
c49d13ee | 2422 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
5bcf719b DA |
2423 | return 0; |
2424 | ||
c49d13ee | 2425 | return i915_drm_suspend(dev); |
76c4b250 ID |
2426 | } |
2427 | ||
c49d13ee | 2428 | static int i915_pm_suspend_late(struct device *kdev) |
76c4b250 | 2429 | { |
c49d13ee | 2430 | struct drm_device *dev = &kdev_to_i915(kdev)->drm; |
76c4b250 ID |
2431 | |
2432 | /* | |
c965d995 | 2433 | * We have a suspend ordering issue with the snd-hda driver also |
76c4b250 ID |
2434 | * requiring our device to be power up. Due to the lack of a |
2435 | * parent/child relationship we currently solve this with an late | |
2436 | * suspend hook. | |
2437 | * | |
2438 | * FIXME: This should be solved with a special hdmi sink device or | |
2439 | * similar so that power domains can be employed. | |
2440 | */ | |
c49d13ee | 2441 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
76c4b250 | 2442 | return 0; |
112b715e | 2443 | |
c49d13ee | 2444 | return i915_drm_suspend_late(dev, false); |
ab3be73f ID |
2445 | } |
2446 | ||
c49d13ee | 2447 | static int i915_pm_poweroff_late(struct device *kdev) |
ab3be73f | 2448 | { |
c49d13ee | 2449 | struct drm_device *dev = &kdev_to_i915(kdev)->drm; |
ab3be73f | 2450 | |
c49d13ee | 2451 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
ab3be73f ID |
2452 | return 0; |
2453 | ||
c49d13ee | 2454 | return i915_drm_suspend_late(dev, true); |
cbda12d7 ZW |
2455 | } |
2456 | ||
c49d13ee | 2457 | static int i915_pm_resume_early(struct device *kdev) |
76c4b250 | 2458 | { |
c49d13ee | 2459 | struct drm_device *dev = &kdev_to_i915(kdev)->drm; |
76c4b250 | 2460 | |
c49d13ee | 2461 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
097dd837 ID |
2462 | return 0; |
2463 | ||
c49d13ee | 2464 | return i915_drm_resume_early(dev); |
76c4b250 ID |
2465 | } |
2466 | ||
c49d13ee | 2467 | static int i915_pm_resume(struct device *kdev) |
cbda12d7 | 2468 | { |
c49d13ee | 2469 | struct drm_device *dev = &kdev_to_i915(kdev)->drm; |
84b79f8d | 2470 | |
c49d13ee | 2471 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
097dd837 ID |
2472 | return 0; |
2473 | ||
c49d13ee | 2474 | return i915_drm_resume(dev); |
cbda12d7 ZW |
2475 | } |
2476 | ||
1f19ac2a | 2477 | /* freeze: before creating the hibernation_image */ |
c49d13ee | 2478 | static int i915_pm_freeze(struct device *kdev) |
1f19ac2a | 2479 | { |
dd9f31c7 | 2480 | struct drm_device *dev = &kdev_to_i915(kdev)->drm; |
6a800eab CW |
2481 | int ret; |
2482 | ||
dd9f31c7 ID |
2483 | if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) { |
2484 | ret = i915_drm_suspend(dev); | |
2485 | if (ret) | |
2486 | return ret; | |
2487 | } | |
6a800eab CW |
2488 | |
2489 | ret = i915_gem_freeze(kdev_to_i915(kdev)); | |
2490 | if (ret) | |
2491 | return ret; | |
2492 | ||
2493 | return 0; | |
1f19ac2a CW |
2494 | } |
2495 | ||
c49d13ee | 2496 | static int i915_pm_freeze_late(struct device *kdev) |
1f19ac2a | 2497 | { |
dd9f31c7 | 2498 | struct drm_device *dev = &kdev_to_i915(kdev)->drm; |
461fb99c CW |
2499 | int ret; |
2500 | ||
dd9f31c7 ID |
2501 | if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) { |
2502 | ret = i915_drm_suspend_late(dev, true); | |
2503 | if (ret) | |
2504 | return ret; | |
2505 | } | |
461fb99c | 2506 | |
c49d13ee | 2507 | ret = i915_gem_freeze_late(kdev_to_i915(kdev)); |
461fb99c CW |
2508 | if (ret) |
2509 | return ret; | |
2510 | ||
2511 | return 0; | |
1f19ac2a CW |
2512 | } |
2513 | ||
2514 | /* thaw: called after creating the hibernation image, but before turning off. */ | |
c49d13ee | 2515 | static int i915_pm_thaw_early(struct device *kdev) |
1f19ac2a | 2516 | { |
c49d13ee | 2517 | return i915_pm_resume_early(kdev); |
1f19ac2a CW |
2518 | } |
2519 | ||
c49d13ee | 2520 | static int i915_pm_thaw(struct device *kdev) |
1f19ac2a | 2521 | { |
c49d13ee | 2522 | return i915_pm_resume(kdev); |
1f19ac2a CW |
2523 | } |
2524 | ||
2525 | /* restore: called after loading the hibernation image. */ | |
c49d13ee | 2526 | static int i915_pm_restore_early(struct device *kdev) |
1f19ac2a | 2527 | { |
c49d13ee | 2528 | return i915_pm_resume_early(kdev); |
1f19ac2a CW |
2529 | } |
2530 | ||
c49d13ee | 2531 | static int i915_pm_restore(struct device *kdev) |
1f19ac2a | 2532 | { |
c49d13ee | 2533 | return i915_pm_resume(kdev); |
1f19ac2a CW |
2534 | } |
2535 | ||
ddeea5b0 ID |
2536 | /* |
2537 | * Save all Gunit registers that may be lost after a D3 and a subsequent | |
2538 | * S0i[R123] transition. The list of registers needing a save/restore is | |
2539 | * defined in the VLV2_S0IXRegs document. This documents marks all Gunit | |
2540 | * registers in the following way: | |
2541 | * - Driver: saved/restored by the driver | |
2542 | * - Punit : saved/restored by the Punit firmware | |
2543 | * - No, w/o marking: no need to save/restore, since the register is R/O or | |
2544 | * used internally by the HW in a way that doesn't depend | |
2545 | * keeping the content across a suspend/resume. | |
2546 | * - Debug : used for debugging | |
2547 | * | |
2548 | * We save/restore all registers marked with 'Driver', with the following | |
2549 | * exceptions: | |
2550 | * - Registers out of use, including also registers marked with 'Debug'. | |
2551 | * These have no effect on the driver's operation, so we don't save/restore | |
2552 | * them to reduce the overhead. | |
2553 | * - Registers that are fully setup by an initialization function called from | |
2554 | * the resume path. For example many clock gating and RPS/RC6 registers. | |
2555 | * - Registers that provide the right functionality with their reset defaults. | |
2556 | * | |
2557 | * TODO: Except for registers that based on the above 3 criteria can be safely | |
2558 | * ignored, we save/restore all others, practically treating the HW context as | |
2559 | * a black-box for the driver. Further investigation is needed to reduce the | |
2560 | * saved/restored registers even further, by following the same 3 criteria. | |
2561 | */ | |
2562 | static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv) | |
2563 | { | |
2564 | struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; | |
2565 | int i; | |
2566 | ||
2567 | /* GAM 0x4000-0x4770 */ | |
2568 | s->wr_watermark = I915_READ(GEN7_WR_WATERMARK); | |
2569 | s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL); | |
2570 | s->arb_mode = I915_READ(ARB_MODE); | |
2571 | s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0); | |
2572 | s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1); | |
2573 | ||
2574 | for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) | |
22dfe79f | 2575 | s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i)); |
ddeea5b0 ID |
2576 | |
2577 | s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); | |
b5f1c97f | 2578 | s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT); |
ddeea5b0 ID |
2579 | |
2580 | s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7); | |
2581 | s->ecochk = I915_READ(GAM_ECOCHK); | |
2582 | s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7); | |
2583 | s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7); | |
2584 | ||
2585 | s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR); | |
2586 | ||
2587 | /* MBC 0x9024-0x91D0, 0x8500 */ | |
2588 | s->g3dctl = I915_READ(VLV_G3DCTL); | |
2589 | s->gsckgctl = I915_READ(VLV_GSCKGCTL); | |
2590 | s->mbctl = I915_READ(GEN6_MBCTL); | |
2591 | ||
2592 | /* GCP 0x9400-0x9424, 0x8100-0x810C */ | |
2593 | s->ucgctl1 = I915_READ(GEN6_UCGCTL1); | |
2594 | s->ucgctl3 = I915_READ(GEN6_UCGCTL3); | |
2595 | s->rcgctl1 = I915_READ(GEN6_RCGCTL1); | |
2596 | s->rcgctl2 = I915_READ(GEN6_RCGCTL2); | |
2597 | s->rstctl = I915_READ(GEN6_RSTCTL); | |
2598 | s->misccpctl = I915_READ(GEN7_MISCCPCTL); | |
2599 | ||
2600 | /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ | |
2601 | s->gfxpause = I915_READ(GEN6_GFXPAUSE); | |
2602 | s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC); | |
2603 | s->rpdeuc = I915_READ(GEN6_RPDEUC); | |
2604 | s->ecobus = I915_READ(ECOBUS); | |
2605 | s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL); | |
2606 | s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT); | |
2607 | s->rp_deucsw = I915_READ(GEN6_RPDEUCSW); | |
2608 | s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR); | |
2609 | s->rcedata = I915_READ(VLV_RCEDATA); | |
2610 | s->spare2gh = I915_READ(VLV_SPAREG2H); | |
2611 | ||
2612 | /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ | |
2613 | s->gt_imr = I915_READ(GTIMR); | |
2614 | s->gt_ier = I915_READ(GTIER); | |
2615 | s->pm_imr = I915_READ(GEN6_PMIMR); | |
2616 | s->pm_ier = I915_READ(GEN6_PMIER); | |
2617 | ||
2618 | for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) | |
22dfe79f | 2619 | s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i)); |
ddeea5b0 ID |
2620 | |
2621 | /* GT SA CZ domain, 0x100000-0x138124 */ | |
2622 | s->tilectl = I915_READ(TILECTL); | |
2623 | s->gt_fifoctl = I915_READ(GTFIFOCTL); | |
2624 | s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL); | |
2625 | s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
2626 | s->pmwgicz = I915_READ(VLV_PMWGICZ); | |
2627 | ||
2628 | /* Gunit-Display CZ domain, 0x182028-0x1821CF */ | |
2629 | s->gu_ctl0 = I915_READ(VLV_GU_CTL0); | |
2630 | s->gu_ctl1 = I915_READ(VLV_GU_CTL1); | |
9c25210f | 2631 | s->pcbr = I915_READ(VLV_PCBR); |
ddeea5b0 ID |
2632 | s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2); |
2633 | ||
2634 | /* | |
2635 | * Not saving any of: | |
2636 | * DFT, 0x9800-0x9EC0 | |
2637 | * SARB, 0xB000-0xB1FC | |
2638 | * GAC, 0x5208-0x524C, 0x14000-0x14C000 | |
2639 | * PCI CFG | |
2640 | */ | |
2641 | } | |
2642 | ||
2643 | static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv) | |
2644 | { | |
2645 | struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; | |
2646 | u32 val; | |
2647 | int i; | |
2648 | ||
2649 | /* GAM 0x4000-0x4770 */ | |
2650 | I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark); | |
2651 | I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl); | |
2652 | I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16)); | |
2653 | I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0); | |
2654 | I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1); | |
2655 | ||
2656 | for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) | |
22dfe79f | 2657 | I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]); |
ddeea5b0 ID |
2658 | |
2659 | I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count); | |
b5f1c97f | 2660 | I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count); |
ddeea5b0 ID |
2661 | |
2662 | I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp); | |
2663 | I915_WRITE(GAM_ECOCHK, s->ecochk); | |
2664 | I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp); | |
2665 | I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp); | |
2666 | ||
2667 | I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr); | |
2668 | ||
2669 | /* MBC 0x9024-0x91D0, 0x8500 */ | |
2670 | I915_WRITE(VLV_G3DCTL, s->g3dctl); | |
2671 | I915_WRITE(VLV_GSCKGCTL, s->gsckgctl); | |
2672 | I915_WRITE(GEN6_MBCTL, s->mbctl); | |
2673 | ||
2674 | /* GCP 0x9400-0x9424, 0x8100-0x810C */ | |
2675 | I915_WRITE(GEN6_UCGCTL1, s->ucgctl1); | |
2676 | I915_WRITE(GEN6_UCGCTL3, s->ucgctl3); | |
2677 | I915_WRITE(GEN6_RCGCTL1, s->rcgctl1); | |
2678 | I915_WRITE(GEN6_RCGCTL2, s->rcgctl2); | |
2679 | I915_WRITE(GEN6_RSTCTL, s->rstctl); | |
2680 | I915_WRITE(GEN7_MISCCPCTL, s->misccpctl); | |
2681 | ||
2682 | /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ | |
2683 | I915_WRITE(GEN6_GFXPAUSE, s->gfxpause); | |
2684 | I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc); | |
2685 | I915_WRITE(GEN6_RPDEUC, s->rpdeuc); | |
2686 | I915_WRITE(ECOBUS, s->ecobus); | |
2687 | I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl); | |
2688 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout); | |
2689 | I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw); | |
2690 | I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr); | |
2691 | I915_WRITE(VLV_RCEDATA, s->rcedata); | |
2692 | I915_WRITE(VLV_SPAREG2H, s->spare2gh); | |
2693 | ||
2694 | /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ | |
2695 | I915_WRITE(GTIMR, s->gt_imr); | |
2696 | I915_WRITE(GTIER, s->gt_ier); | |
2697 | I915_WRITE(GEN6_PMIMR, s->pm_imr); | |
2698 | I915_WRITE(GEN6_PMIER, s->pm_ier); | |
2699 | ||
2700 | for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) | |
22dfe79f | 2701 | I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]); |
ddeea5b0 ID |
2702 | |
2703 | /* GT SA CZ domain, 0x100000-0x138124 */ | |
2704 | I915_WRITE(TILECTL, s->tilectl); | |
2705 | I915_WRITE(GTFIFOCTL, s->gt_fifoctl); | |
2706 | /* | |
2707 | * Preserve the GT allow wake and GFX force clock bit, they are not | |
2708 | * be restored, as they are used to control the s0ix suspend/resume | |
2709 | * sequence by the caller. | |
2710 | */ | |
2711 | val = I915_READ(VLV_GTLC_WAKE_CTRL); | |
2712 | val &= VLV_GTLC_ALLOWWAKEREQ; | |
2713 | val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ; | |
2714 | I915_WRITE(VLV_GTLC_WAKE_CTRL, val); | |
2715 | ||
2716 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
2717 | val &= VLV_GFX_CLK_FORCE_ON_BIT; | |
2718 | val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT; | |
2719 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); | |
2720 | ||
2721 | I915_WRITE(VLV_PMWGICZ, s->pmwgicz); | |
2722 | ||
2723 | /* Gunit-Display CZ domain, 0x182028-0x1821CF */ | |
2724 | I915_WRITE(VLV_GU_CTL0, s->gu_ctl0); | |
2725 | I915_WRITE(VLV_GU_CTL1, s->gu_ctl1); | |
9c25210f | 2726 | I915_WRITE(VLV_PCBR, s->pcbr); |
ddeea5b0 ID |
2727 | I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2); |
2728 | } | |
2729 | ||
5a31d30b | 2730 | static int vlv_wait_for_pw_status(struct drm_i915_private *i915, |
3dd14c04 CW |
2731 | u32 mask, u32 val) |
2732 | { | |
39806c3f VS |
2733 | i915_reg_t reg = VLV_GTLC_PW_STATUS; |
2734 | u32 reg_value; | |
2735 | int ret; | |
2736 | ||
3dd14c04 CW |
2737 | /* The HW does not like us polling for PW_STATUS frequently, so |
2738 | * use the sleeping loop rather than risk the busy spin within | |
2739 | * intel_wait_for_register(). | |
2740 | * | |
2741 | * Transitioning between RC6 states should be at most 2ms (see | |
2742 | * valleyview_enable_rps) so use a 3ms timeout. | |
2743 | */ | |
5a31d30b TU |
2744 | ret = wait_for(((reg_value = |
2745 | intel_uncore_read_notrace(&i915->uncore, reg)) & mask) | |
2746 | == val, 3); | |
39806c3f VS |
2747 | |
2748 | /* just trace the final value */ | |
2749 | trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true); | |
2750 | ||
2751 | return ret; | |
3dd14c04 CW |
2752 | } |
2753 | ||
650ad970 ID |
2754 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on) |
2755 | { | |
2756 | u32 val; | |
2757 | int err; | |
2758 | ||
650ad970 ID |
2759 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); |
2760 | val &= ~VLV_GFX_CLK_FORCE_ON_BIT; | |
2761 | if (force_on) | |
2762 | val |= VLV_GFX_CLK_FORCE_ON_BIT; | |
2763 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); | |
2764 | ||
2765 | if (!force_on) | |
2766 | return 0; | |
2767 | ||
97a04e0d | 2768 | err = intel_wait_for_register(&dev_priv->uncore, |
c6ddc5f3 CW |
2769 | VLV_GTLC_SURVIVABILITY_REG, |
2770 | VLV_GFX_CLK_STATUS_BIT, | |
2771 | VLV_GFX_CLK_STATUS_BIT, | |
2772 | 20); | |
650ad970 ID |
2773 | if (err) |
2774 | DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n", | |
2775 | I915_READ(VLV_GTLC_SURVIVABILITY_REG)); | |
2776 | ||
2777 | return err; | |
650ad970 ID |
2778 | } |
2779 | ||
ddeea5b0 ID |
2780 | static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow) |
2781 | { | |
3dd14c04 | 2782 | u32 mask; |
ddeea5b0 | 2783 | u32 val; |
3dd14c04 | 2784 | int err; |
ddeea5b0 ID |
2785 | |
2786 | val = I915_READ(VLV_GTLC_WAKE_CTRL); | |
2787 | val &= ~VLV_GTLC_ALLOWWAKEREQ; | |
2788 | if (allow) | |
2789 | val |= VLV_GTLC_ALLOWWAKEREQ; | |
2790 | I915_WRITE(VLV_GTLC_WAKE_CTRL, val); | |
2791 | POSTING_READ(VLV_GTLC_WAKE_CTRL); | |
2792 | ||
3dd14c04 CW |
2793 | mask = VLV_GTLC_ALLOWWAKEACK; |
2794 | val = allow ? mask : 0; | |
2795 | ||
2796 | err = vlv_wait_for_pw_status(dev_priv, mask, val); | |
ddeea5b0 ID |
2797 | if (err) |
2798 | DRM_ERROR("timeout disabling GT waking\n"); | |
b2736695 | 2799 | |
ddeea5b0 | 2800 | return err; |
ddeea5b0 ID |
2801 | } |
2802 | ||
3dd14c04 CW |
2803 | static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv, |
2804 | bool wait_for_on) | |
ddeea5b0 ID |
2805 | { |
2806 | u32 mask; | |
2807 | u32 val; | |
ddeea5b0 ID |
2808 | |
2809 | mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK; | |
2810 | val = wait_for_on ? mask : 0; | |
ddeea5b0 ID |
2811 | |
2812 | /* | |
2813 | * RC6 transitioning can be delayed up to 2 msec (see | |
2814 | * valleyview_enable_rps), use 3 msec for safety. | |
e01569ab CW |
2815 | * |
2816 | * This can fail to turn off the rc6 if the GPU is stuck after a failed | |
2817 | * reset and we are trying to force the machine to sleep. | |
ddeea5b0 | 2818 | */ |
3dd14c04 | 2819 | if (vlv_wait_for_pw_status(dev_priv, mask, val)) |
e01569ab CW |
2820 | DRM_DEBUG_DRIVER("timeout waiting for GT wells to go %s\n", |
2821 | onoff(wait_for_on)); | |
ddeea5b0 ID |
2822 | } |
2823 | ||
2824 | static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv) | |
2825 | { | |
2826 | if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR)) | |
2827 | return; | |
2828 | ||
6fa283b0 | 2829 | DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n"); |
ddeea5b0 ID |
2830 | I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR); |
2831 | } | |
2832 | ||
ebc32824 | 2833 | static int vlv_suspend_complete(struct drm_i915_private *dev_priv) |
ddeea5b0 ID |
2834 | { |
2835 | u32 mask; | |
2836 | int err; | |
2837 | ||
2838 | /* | |
2839 | * Bspec defines the following GT well on flags as debug only, so | |
2840 | * don't treat them as hard failures. | |
2841 | */ | |
3dd14c04 | 2842 | vlv_wait_for_gt_wells(dev_priv, false); |
ddeea5b0 ID |
2843 | |
2844 | mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS; | |
2845 | WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask); | |
2846 | ||
2847 | vlv_check_no_gt_access(dev_priv); | |
2848 | ||
2849 | err = vlv_force_gfx_clock(dev_priv, true); | |
2850 | if (err) | |
2851 | goto err1; | |
2852 | ||
2853 | err = vlv_allow_gt_wake(dev_priv, false); | |
2854 | if (err) | |
2855 | goto err2; | |
98711167 | 2856 | |
2d1fe073 | 2857 | if (!IS_CHERRYVIEW(dev_priv)) |
98711167 | 2858 | vlv_save_gunit_s0ix_state(dev_priv); |
ddeea5b0 ID |
2859 | |
2860 | err = vlv_force_gfx_clock(dev_priv, false); | |
2861 | if (err) | |
2862 | goto err2; | |
2863 | ||
2864 | return 0; | |
2865 | ||
2866 | err2: | |
2867 | /* For safety always re-enable waking and disable gfx clock forcing */ | |
2868 | vlv_allow_gt_wake(dev_priv, true); | |
2869 | err1: | |
2870 | vlv_force_gfx_clock(dev_priv, false); | |
2871 | ||
2872 | return err; | |
2873 | } | |
2874 | ||
016970be SK |
2875 | static int vlv_resume_prepare(struct drm_i915_private *dev_priv, |
2876 | bool rpm_resume) | |
ddeea5b0 | 2877 | { |
ddeea5b0 ID |
2878 | int err; |
2879 | int ret; | |
2880 | ||
2881 | /* | |
2882 | * If any of the steps fail just try to continue, that's the best we | |
2883 | * can do at this point. Return the first error code (which will also | |
2884 | * leave RPM permanently disabled). | |
2885 | */ | |
2886 | ret = vlv_force_gfx_clock(dev_priv, true); | |
2887 | ||
2d1fe073 | 2888 | if (!IS_CHERRYVIEW(dev_priv)) |
98711167 | 2889 | vlv_restore_gunit_s0ix_state(dev_priv); |
ddeea5b0 ID |
2890 | |
2891 | err = vlv_allow_gt_wake(dev_priv, true); | |
2892 | if (!ret) | |
2893 | ret = err; | |
2894 | ||
2895 | err = vlv_force_gfx_clock(dev_priv, false); | |
2896 | if (!ret) | |
2897 | ret = err; | |
2898 | ||
2899 | vlv_check_no_gt_access(dev_priv); | |
2900 | ||
7c108fd8 | 2901 | if (rpm_resume) |
46f16e63 | 2902 | intel_init_clock_gating(dev_priv); |
ddeea5b0 ID |
2903 | |
2904 | return ret; | |
2905 | } | |
2906 | ||
c49d13ee | 2907 | static int intel_runtime_suspend(struct device *kdev) |
8a187455 | 2908 | { |
906339a9 | 2909 | struct drm_device *dev = dev_get_drvdata(kdev); |
fac5e23e | 2910 | struct drm_i915_private *dev_priv = to_i915(dev); |
1bf676cc | 2911 | struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; |
0ab9cfeb | 2912 | int ret; |
8a187455 | 2913 | |
fb6db0f5 | 2914 | if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv)))) |
c6df39b5 ID |
2915 | return -ENODEV; |
2916 | ||
6772ffe0 | 2917 | if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv))) |
604effb7 ID |
2918 | return -ENODEV; |
2919 | ||
8a187455 PZ |
2920 | DRM_DEBUG_KMS("Suspending device\n"); |
2921 | ||
9102650f | 2922 | disable_rpm_wakeref_asserts(rpm); |
1f814dac | 2923 | |
d6102977 ID |
2924 | /* |
2925 | * We are safe here against re-faults, since the fault handler takes | |
2926 | * an RPM reference. | |
2927 | */ | |
7c108fd8 | 2928 | i915_gem_runtime_suspend(dev_priv); |
d6102977 | 2929 | |
ca7b2c1b | 2930 | intel_uc_runtime_suspend(&dev_priv->gt.uc); |
a1c41994 | 2931 | |
2eb5252e | 2932 | intel_runtime_pm_disable_interrupts(dev_priv); |
b5478bcd | 2933 | |
f7de5027 | 2934 | intel_uncore_suspend(&dev_priv->uncore); |
01c799c9 | 2935 | |
507e126e | 2936 | ret = 0; |
3e68928b AM |
2937 | if (INTEL_GEN(dev_priv) >= 11) { |
2938 | icl_display_core_uninit(dev_priv); | |
2939 | bxt_enable_dc9(dev_priv); | |
2940 | } else if (IS_GEN9_LP(dev_priv)) { | |
507e126e ID |
2941 | bxt_display_core_uninit(dev_priv); |
2942 | bxt_enable_dc9(dev_priv); | |
2943 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { | |
2944 | hsw_enable_pc8(dev_priv); | |
2945 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
2946 | ret = vlv_suspend_complete(dev_priv); | |
2947 | } | |
2948 | ||
0ab9cfeb ID |
2949 | if (ret) { |
2950 | DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret); | |
f7de5027 | 2951 | intel_uncore_runtime_resume(&dev_priv->uncore); |
01c799c9 | 2952 | |
b963291c | 2953 | intel_runtime_pm_enable_interrupts(dev_priv); |
0ab9cfeb | 2954 | |
602776f9 | 2955 | intel_uc_runtime_resume(&dev_priv->gt.uc); |
1ed21cb4 | 2956 | |
500bfa38 | 2957 | intel_gt_init_swizzling(&dev_priv->gt); |
1ed21cb4 SAK |
2958 | i915_gem_restore_fences(dev_priv); |
2959 | ||
9102650f | 2960 | enable_rpm_wakeref_asserts(rpm); |
1f814dac | 2961 | |
0ab9cfeb ID |
2962 | return ret; |
2963 | } | |
a8a8bd54 | 2964 | |
9102650f | 2965 | enable_rpm_wakeref_asserts(rpm); |
3b58a945 | 2966 | intel_runtime_pm_driver_release(rpm); |
55ec45c2 | 2967 | |
2cf7bf6f | 2968 | if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore)) |
55ec45c2 MK |
2969 | DRM_ERROR("Unclaimed access detected prior to suspending\n"); |
2970 | ||
9102650f | 2971 | rpm->suspended = true; |
1fb2362b KCA |
2972 | |
2973 | /* | |
c8a0bd42 PZ |
2974 | * FIXME: We really should find a document that references the arguments |
2975 | * used below! | |
1fb2362b | 2976 | */ |
6f9f4b7a | 2977 | if (IS_BROADWELL(dev_priv)) { |
d37ae19a PZ |
2978 | /* |
2979 | * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop | |
2980 | * being detected, and the call we do at intel_runtime_resume() | |
2981 | * won't be able to restore them. Since PCI_D3hot matches the | |
2982 | * actual specification and appears to be working, use it. | |
2983 | */ | |
6f9f4b7a | 2984 | intel_opregion_notify_adapter(dev_priv, PCI_D3hot); |
d37ae19a | 2985 | } else { |
c8a0bd42 PZ |
2986 | /* |
2987 | * current versions of firmware which depend on this opregion | |
2988 | * notification have repurposed the D1 definition to mean | |
2989 | * "runtime suspended" vs. what you would normally expect (D3) | |
2990 | * to distinguish it from notifications that might be sent via | |
2991 | * the suspend path. | |
2992 | */ | |
6f9f4b7a | 2993 | intel_opregion_notify_adapter(dev_priv, PCI_D1); |
c8a0bd42 | 2994 | } |
8a187455 | 2995 | |
f568eeee | 2996 | assert_forcewakes_inactive(&dev_priv->uncore); |
dc9fb09c | 2997 | |
21d6e0bd | 2998 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) |
19625e85 L |
2999 | intel_hpd_poll_init(dev_priv); |
3000 | ||
a8a8bd54 | 3001 | DRM_DEBUG_KMS("Device suspended\n"); |
8a187455 PZ |
3002 | return 0; |
3003 | } | |
3004 | ||
c49d13ee | 3005 | static int intel_runtime_resume(struct device *kdev) |
8a187455 | 3006 | { |
906339a9 | 3007 | struct drm_device *dev = dev_get_drvdata(kdev); |
fac5e23e | 3008 | struct drm_i915_private *dev_priv = to_i915(dev); |
1bf676cc | 3009 | struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; |
1a5df187 | 3010 | int ret = 0; |
8a187455 | 3011 | |
6772ffe0 | 3012 | if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv))) |
604effb7 | 3013 | return -ENODEV; |
8a187455 PZ |
3014 | |
3015 | DRM_DEBUG_KMS("Resuming device\n"); | |
3016 | ||
9102650f DCS |
3017 | WARN_ON_ONCE(atomic_read(&rpm->wakeref_count)); |
3018 | disable_rpm_wakeref_asserts(rpm); | |
1f814dac | 3019 | |
6f9f4b7a | 3020 | intel_opregion_notify_adapter(dev_priv, PCI_D0); |
9102650f | 3021 | rpm->suspended = false; |
2cf7bf6f | 3022 | if (intel_uncore_unclaimed_mmio(&dev_priv->uncore)) |
55ec45c2 | 3023 | DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n"); |
8a187455 | 3024 | |
3e68928b AM |
3025 | if (INTEL_GEN(dev_priv) >= 11) { |
3026 | bxt_disable_dc9(dev_priv); | |
3027 | icl_display_core_init(dev_priv, true); | |
3028 | if (dev_priv->csr.dmc_payload) { | |
3029 | if (dev_priv->csr.allowed_dc_mask & | |
3030 | DC_STATE_EN_UPTO_DC6) | |
3031 | skl_enable_dc6(dev_priv); | |
3032 | else if (dev_priv->csr.allowed_dc_mask & | |
3033 | DC_STATE_EN_UPTO_DC5) | |
3034 | gen9_enable_dc5(dev_priv); | |
3035 | } | |
3036 | } else if (IS_GEN9_LP(dev_priv)) { | |
507e126e ID |
3037 | bxt_disable_dc9(dev_priv); |
3038 | bxt_display_core_init(dev_priv, true); | |
f62c79b3 ID |
3039 | if (dev_priv->csr.dmc_payload && |
3040 | (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)) | |
3041 | gen9_enable_dc5(dev_priv); | |
507e126e | 3042 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
1a5df187 | 3043 | hsw_disable_pc8(dev_priv); |
507e126e | 3044 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
1a5df187 | 3045 | ret = vlv_resume_prepare(dev_priv, true); |
507e126e | 3046 | } |
1a5df187 | 3047 | |
f7de5027 | 3048 | intel_uncore_runtime_resume(&dev_priv->uncore); |
bedf4d79 | 3049 | |
1ed21cb4 SAK |
3050 | intel_runtime_pm_enable_interrupts(dev_priv); |
3051 | ||
602776f9 | 3052 | intel_uc_runtime_resume(&dev_priv->gt.uc); |
1ed21cb4 | 3053 | |
0ab9cfeb ID |
3054 | /* |
3055 | * No point of rolling back things in case of an error, as the best | |
3056 | * we can do is to hope that things will still work (and disable RPM). | |
3057 | */ | |
500bfa38 | 3058 | intel_gt_init_swizzling(&dev_priv->gt); |
83bf6d55 | 3059 | i915_gem_restore_fences(dev_priv); |
92b806d3 | 3060 | |
08d8a232 VS |
3061 | /* |
3062 | * On VLV/CHV display interrupts are part of the display | |
3063 | * power well, so hpd is reinitialized from there. For | |
3064 | * everyone else do it here. | |
3065 | */ | |
666a4537 | 3066 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) |
08d8a232 VS |
3067 | intel_hpd_init(dev_priv); |
3068 | ||
2503a0fe KM |
3069 | intel_enable_ipc(dev_priv); |
3070 | ||
9102650f | 3071 | enable_rpm_wakeref_asserts(rpm); |
1f814dac | 3072 | |
0ab9cfeb ID |
3073 | if (ret) |
3074 | DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret); | |
3075 | else | |
3076 | DRM_DEBUG_KMS("Device resumed\n"); | |
3077 | ||
3078 | return ret; | |
8a187455 PZ |
3079 | } |
3080 | ||
42f5551d | 3081 | const struct dev_pm_ops i915_pm_ops = { |
5545dbbf ID |
3082 | /* |
3083 | * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, | |
3084 | * PMSG_RESUME] | |
3085 | */ | |
73b66f87 | 3086 | .prepare = i915_pm_prepare, |
0206e353 | 3087 | .suspend = i915_pm_suspend, |
76c4b250 ID |
3088 | .suspend_late = i915_pm_suspend_late, |
3089 | .resume_early = i915_pm_resume_early, | |
0206e353 | 3090 | .resume = i915_pm_resume, |
5545dbbf ID |
3091 | |
3092 | /* | |
3093 | * S4 event handlers | |
3094 | * @freeze, @freeze_late : called (1) before creating the | |
3095 | * hibernation image [PMSG_FREEZE] and | |
3096 | * (2) after rebooting, before restoring | |
3097 | * the image [PMSG_QUIESCE] | |
3098 | * @thaw, @thaw_early : called (1) after creating the hibernation | |
3099 | * image, before writing it [PMSG_THAW] | |
3100 | * and (2) after failing to create or | |
3101 | * restore the image [PMSG_RECOVER] | |
3102 | * @poweroff, @poweroff_late: called after writing the hibernation | |
3103 | * image, before rebooting [PMSG_HIBERNATE] | |
3104 | * @restore, @restore_early : called after rebooting and restoring the | |
3105 | * hibernation image [PMSG_RESTORE] | |
3106 | */ | |
1f19ac2a CW |
3107 | .freeze = i915_pm_freeze, |
3108 | .freeze_late = i915_pm_freeze_late, | |
3109 | .thaw_early = i915_pm_thaw_early, | |
3110 | .thaw = i915_pm_thaw, | |
36d61e67 | 3111 | .poweroff = i915_pm_suspend, |
ab3be73f | 3112 | .poweroff_late = i915_pm_poweroff_late, |
1f19ac2a CW |
3113 | .restore_early = i915_pm_restore_early, |
3114 | .restore = i915_pm_restore, | |
5545dbbf ID |
3115 | |
3116 | /* S0ix (via runtime suspend) event handlers */ | |
97bea207 PZ |
3117 | .runtime_suspend = intel_runtime_suspend, |
3118 | .runtime_resume = intel_runtime_resume, | |
cbda12d7 ZW |
3119 | }; |
3120 | ||
78b68556 | 3121 | static const struct vm_operations_struct i915_gem_vm_ops = { |
de151cf6 | 3122 | .fault = i915_gem_fault, |
ab00b3e5 JB |
3123 | .open = drm_gem_vm_open, |
3124 | .close = drm_gem_vm_close, | |
de151cf6 JB |
3125 | }; |
3126 | ||
e08e96de AV |
3127 | static const struct file_operations i915_driver_fops = { |
3128 | .owner = THIS_MODULE, | |
3129 | .open = drm_open, | |
3130 | .release = drm_release, | |
3131 | .unlocked_ioctl = drm_ioctl, | |
3132 | .mmap = drm_gem_mmap, | |
3133 | .poll = drm_poll, | |
e08e96de | 3134 | .read = drm_read, |
e08e96de | 3135 | .compat_ioctl = i915_compat_ioctl, |
e08e96de AV |
3136 | .llseek = noop_llseek, |
3137 | }; | |
3138 | ||
0673ad47 CW |
3139 | static int |
3140 | i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data, | |
3141 | struct drm_file *file) | |
3142 | { | |
3143 | return -ENODEV; | |
3144 | } | |
3145 | ||
3146 | static const struct drm_ioctl_desc i915_ioctls[] = { | |
3147 | DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
3148 | DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH), | |
3149 | DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH), | |
3150 | DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH), | |
3151 | DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH), | |
3152 | DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH), | |
b972fffa | 3153 | DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW), |
0673ad47 CW |
3154 | DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
3155 | DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), | |
3156 | DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), | |
3157 | DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
3158 | DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH), | |
3159 | DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
3160 | DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
3161 | DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH), | |
3162 | DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH), | |
3163 | DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
3164 | DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
6a20fe7b | 3165 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH), |
b972fffa | 3166 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW), |
0673ad47 CW |
3167 | DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), |
3168 | DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), | |
b972fffa | 3169 | DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW), |
0673ad47 CW |
3170 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW), |
3171 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW), | |
b972fffa | 3172 | DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW), |
0673ad47 CW |
3173 | DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
3174 | DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
3175 | DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW), | |
3176 | DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW), | |
3177 | DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW), | |
3178 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW), | |
3179 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW), | |
3180 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW), | |
3181 | DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW), | |
111dbcab CW |
3182 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW), |
3183 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW), | |
0673ad47 | 3184 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW), |
6a20fe7b | 3185 | DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0), |
0673ad47 | 3186 | DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW), |
0cd54b03 DV |
3187 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER), |
3188 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER), | |
3189 | DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER), | |
3190 | DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER), | |
b972fffa | 3191 | DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW), |
b9171541 | 3192 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW), |
0673ad47 CW |
3193 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW), |
3194 | DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW), | |
3195 | DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW), | |
3196 | DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW), | |
3197 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW), | |
3198 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW), | |
eec688e1 | 3199 | DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW), |
f89823c2 LL |
3200 | DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
3201 | DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
a446ae2c | 3202 | DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
7f3f317a CW |
3203 | DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW), |
3204 | DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW), | |
0673ad47 CW |
3205 | }; |
3206 | ||
1da177e4 | 3207 | static struct drm_driver driver = { |
0c54781b MW |
3208 | /* Don't use MTRRs here; the Xserver or userspace app should |
3209 | * deal with them for Intel hardware. | |
792d2b9a | 3210 | */ |
673a394b | 3211 | .driver_features = |
1ff49481 | 3212 | DRIVER_GEM | DRIVER_PRIME | |
cf6e7bac | 3213 | DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ, |
cad3688f | 3214 | .release = i915_driver_release, |
673a394b | 3215 | .open = i915_driver_open, |
22eae947 | 3216 | .lastclose = i915_driver_lastclose, |
673a394b | 3217 | .postclose = i915_driver_postclose, |
d8e29209 | 3218 | |
b1f788c6 | 3219 | .gem_close_object = i915_gem_close_object, |
f0cd5182 | 3220 | .gem_free_object_unlocked = i915_gem_free_object, |
de151cf6 | 3221 | .gem_vm_ops = &i915_gem_vm_ops, |
1286ff73 DV |
3222 | |
3223 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
3224 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
3225 | .gem_prime_export = i915_gem_prime_export, | |
3226 | .gem_prime_import = i915_gem_prime_import, | |
3227 | ||
7d23e593 VS |
3228 | .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos, |
3229 | .get_scanout_position = i915_get_crtc_scanoutpos, | |
3230 | ||
ff72145b | 3231 | .dumb_create = i915_gem_dumb_create, |
da6b51d0 | 3232 | .dumb_map_offset = i915_gem_mmap_gtt, |
1da177e4 | 3233 | .ioctls = i915_ioctls, |
0673ad47 | 3234 | .num_ioctls = ARRAY_SIZE(i915_ioctls), |
e08e96de | 3235 | .fops = &i915_driver_fops, |
22eae947 DA |
3236 | .name = DRIVER_NAME, |
3237 | .desc = DRIVER_DESC, | |
3238 | .date = DRIVER_DATE, | |
3239 | .major = DRIVER_MAJOR, | |
3240 | .minor = DRIVER_MINOR, | |
3241 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 | 3242 | }; |
66d9cb5d CW |
3243 | |
3244 | #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) | |
3245 | #include "selftests/mock_drm.c" | |
3246 | #endif |