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drm/i915: Fix fbdev unload sequence
[linux-2.6-block.git] / drivers / gpu / drm / i915 / i915_drv.c
CommitLineData
1da177e4
LT		 1/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
0d6aa60b 3/*
bc54fd1a 4 *
1da177e4
LT		 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
bc54fd1a
DA		 7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
0d6aa60b 28 */
1da177e4 29
e5747e3a 30#include <linux/acpi.h>
0673ad47
CW		 31#include <linux/device.h>
32#include <linux/oom.h>
e0cd3608 33#include <linux/module.h>
0673ad47
CW		 34#include <linux/pci.h>
35#include <linux/pm.h>
d6102977 36#include <linux/pm_runtime.h>
0673ad47
CW		 37#include <linux/pnp.h>
38#include <linux/slab.h>
39#include <linux/vgaarb.h>
704ab614 40#include <linux/vga_switcheroo.h>
0673ad47
CW		 41#include <linux/vt.h>
42#include <acpi/video.h>
43
44#include <drm/drmP.h>
760285e7 45#include <drm/drm_crtc_helper.h>
a667fb40 46#include <drm/drm_atomic_helper.h>
0673ad47
CW		 47#include <drm/i915_drm.h>
48
49#include "i915_drv.h"
50#include "i915_trace.h"
51#include "i915_vgpu.h"
52#include "intel_drv.h"
5464cd65 53#include "intel_uc.h"
79e53945 54
112b715e
KH		 55static struct drm_driver driver;
56
0673ad47
CW		 57static unsigned int i915_load_fail_count;
58
59bool __i915_inject_load_failure(const char *func, int line)
60{
61 if (i915_load_fail_count >= i915.inject_load_failure)
62 return false;
63
64 if (++i915_load_fail_count == i915.inject_load_failure) {
65 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
66 i915.inject_load_failure, func, line);
67 return true;
68 }
69
70 return false;
71}
72
73#define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
74#define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
75 "providing the dmesg log by booting with drm.debug=0xf"
76
77void
78__i915_printk(struct drm_i915_private *dev_priv, const char *level,
79 const char *fmt, ...)
80{
81 static bool shown_bug_once;
c49d13ee 82 struct device *kdev = dev_priv->drm.dev;
0673ad47
CW		 83 bool is_error = level[1] <= KERN_ERR[1];
84 bool is_debug = level[1] == KERN_DEBUG[1];
85 struct va_format vaf;
86 va_list args;
87
88 if (is_debug && !(drm_debug & DRM_UT_DRIVER))
89 return;
90
91 va_start(args, fmt);
92
93 vaf.fmt = fmt;
94 vaf.va = &args;
95
c49d13ee 96 dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
0673ad47
CW		 97 __builtin_return_address(0), &vaf);
98
99 if (is_error && !shown_bug_once) {
c49d13ee 100 dev_notice(kdev, "%s", FDO_BUG_MSG);
0673ad47
CW		 101 shown_bug_once = true;
102 }
103
104 va_end(args);
105}
106
107static bool i915_error_injected(struct drm_i915_private *dev_priv)
108{
109 return i915.inject_load_failure &&
110 i915_load_fail_count == i915.inject_load_failure;
111}
112
113#define i915_load_error(dev_priv, fmt, ...) \
114 __i915_printk(dev_priv, \
115 i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
116 fmt, ##__VA_ARGS__)
117
118
fd6b8f43 119static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
0673ad47
CW		 120{
121 enum intel_pch ret = PCH_NOP;
122
123 /*
124 * In a virtualized passthrough environment we can be in a
125 * setup where the ISA bridge is not able to be passed through.
126 * In this case, a south bridge can be emulated and we have to
127 * make an educated guess as to which PCH is really there.
128 */
129
fd6b8f43 130 if (IS_GEN5(dev_priv)) {
0673ad47
CW		 131 ret = PCH_IBX;
132 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
fd6b8f43 133 } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
0673ad47 134 ret = PCH_CPT;
aa032130 135 DRM_DEBUG_KMS("Assuming CougarPoint PCH\n");
fd6b8f43 136 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
0673ad47 137 ret = PCH_LPT;
817aef5d
XZ		 138 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
139 dev_priv->pch_id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
140 else
141 dev_priv->pch_id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
0673ad47 142 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
fd6b8f43 143 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
0673ad47
CW		 144 ret = PCH_SPT;
145 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
80937819 146 } else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
acf1dba6 147 ret = PCH_CNP;
80937819 148 DRM_DEBUG_KMS("Assuming CannonPoint PCH\n");
0673ad47
CW		 149 }
150
151 return ret;
152}
153
da5f53bf 154static void intel_detect_pch(struct drm_i915_private *dev_priv)
0673ad47 155{
0673ad47
CW		 156 struct pci_dev *pch = NULL;
157
158 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
159 * (which really amounts to a PCH but no South Display).
160 */
b7f05d4a 161 if (INTEL_INFO(dev_priv)->num_pipes == 0) {
0673ad47
CW		 162 dev_priv->pch_type = PCH_NOP;
163 return;
164 }
165
166 /*
167 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
168 * make graphics device passthrough work easy for VMM, that only
169 * need to expose ISA bridge to let driver know the real hardware
170 * underneath. This is a requirement from virtualization team.
171 *
172 * In some virtualized environments (e.g. XEN), there is irrelevant
173 * ISA bridge in the system. To work reliably, we should scan trhough
174 * all the ISA bridge devices and check for the first match, instead
175 * of only checking the first one.
176 */
177 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
178 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
179 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
c5e855d0
VS		 180
181 dev_priv->pch_id = id;
ec7e0bb3 182
0673ad47
CW		 183 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
184 dev_priv->pch_type = PCH_IBX;
185 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
5db94019 186 WARN_ON(!IS_GEN5(dev_priv));
0673ad47
CW		 187 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
188 dev_priv->pch_type = PCH_CPT;
189 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
d4cdbf03
VS		 190 WARN_ON(!IS_GEN6(dev_priv) &&
191 !IS_IVYBRIDGE(dev_priv));
0673ad47
CW		 192 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
193 /* PantherPoint is CPT compatible */
194 dev_priv->pch_type = PCH_CPT;
195 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
d4cdbf03
VS		 196 WARN_ON(!IS_GEN6(dev_priv) &&
197 !IS_IVYBRIDGE(dev_priv));
0673ad47
CW		 198 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
199 dev_priv->pch_type = PCH_LPT;
200 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
8652744b
TU		 201 WARN_ON(!IS_HASWELL(dev_priv) &&
202 !IS_BROADWELL(dev_priv));
50a0bc90
TU		 203 WARN_ON(IS_HSW_ULT(dev_priv) ||
204 IS_BDW_ULT(dev_priv));
0673ad47
CW		 205 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
206 dev_priv->pch_type = PCH_LPT;
207 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
8652744b
TU		 208 WARN_ON(!IS_HASWELL(dev_priv) &&
209 !IS_BROADWELL(dev_priv));
50a0bc90
TU		 210 WARN_ON(!IS_HSW_ULT(dev_priv) &&
211 !IS_BDW_ULT(dev_priv));
c5e855d0
VS		 212 } else if (id == INTEL_PCH_WPT_DEVICE_ID_TYPE) {
213 /* WildcatPoint is LPT compatible */
214 dev_priv->pch_type = PCH_LPT;
215 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
216 WARN_ON(!IS_HASWELL(dev_priv) &&
217 !IS_BROADWELL(dev_priv));
218 WARN_ON(IS_HSW_ULT(dev_priv) ||
219 IS_BDW_ULT(dev_priv));
220 } else if (id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE) {
221 /* WildcatPoint is LPT compatible */
222 dev_priv->pch_type = PCH_LPT;
223 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
224 WARN_ON(!IS_HASWELL(dev_priv) &&
225 !IS_BROADWELL(dev_priv));
226 WARN_ON(!IS_HSW_ULT(dev_priv) &&
227 !IS_BDW_ULT(dev_priv));
0673ad47
CW		 228 } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
229 dev_priv->pch_type = PCH_SPT;
230 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
0853723b
TU		 231 WARN_ON(!IS_SKYLAKE(dev_priv) &&
232 !IS_KABYLAKE(dev_priv));
c5e855d0 233 } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
0673ad47
CW		 234 dev_priv->pch_type = PCH_SPT;
235 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
0853723b
TU		 236 WARN_ON(!IS_SKYLAKE(dev_priv) &&
237 !IS_KABYLAKE(dev_priv));
22dea0be
RV		 238 } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
239 dev_priv->pch_type = PCH_KBP;
240 DRM_DEBUG_KMS("Found KabyPoint PCH\n");
85327748
JN		 241 WARN_ON(!IS_SKYLAKE(dev_priv) &&
242 !IS_KABYLAKE(dev_priv));
7b22b8c4
RV		 243 } else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
244 dev_priv->pch_type = PCH_CNP;
245 DRM_DEBUG_KMS("Found CannonPoint PCH\n");
80937819
RV		 246 WARN_ON(!IS_CANNONLAKE(dev_priv) &&
247 !IS_COFFEELAKE(dev_priv));
c5e855d0 248 } else if (id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
ec7e0bb3
DP		 249 dev_priv->pch_type = PCH_CNP;
250 DRM_DEBUG_KMS("Found CannonPoint LP PCH\n");
80937819
RV		 251 WARN_ON(!IS_CANNONLAKE(dev_priv) &&
252 !IS_COFFEELAKE(dev_priv));
d4cdbf03
VS		 253 } else if (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
254 id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
255 (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
0673ad47
CW		 256 pch->subsystem_vendor ==
257 PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
258 pch->subsystem_device ==
259 PCI_SUBDEVICE_ID_QEMU)) {
fd6b8f43
TU		 260 dev_priv->pch_type =
261 intel_virt_detect_pch(dev_priv);
0673ad47
CW		 262 } else
263 continue;
264
265 break;
266 }
267 }
268 if (!pch)
269 DRM_DEBUG_KMS("No PCH found.\n");
270
271 pci_dev_put(pch);
272}
273
0673ad47
CW		 274static int i915_getparam(struct drm_device *dev, void *data,
275 struct drm_file *file_priv)
276{
fac5e23e 277 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 278 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 279 drm_i915_getparam_t *param = data;
280 int value;
281
282 switch (param->param) {
283 case I915_PARAM_IRQ_ACTIVE:
284 case I915_PARAM_ALLOW_BATCHBUFFER:
285 case I915_PARAM_LAST_DISPATCH:
ef0f411f 286 case I915_PARAM_HAS_EXEC_CONSTANTS:
0673ad47
CW		 287 /* Reject all old ums/dri params. */
288 return -ENODEV;
289 case I915_PARAM_CHIPSET_ID:
52a05c30 290 value = pdev->device;
0673ad47
CW		 291 break;
292 case I915_PARAM_REVISION:
52a05c30 293 value = pdev->revision;
0673ad47 294 break;
0673ad47
CW		 295 case I915_PARAM_NUM_FENCES_AVAIL:
296 value = dev_priv->num_fence_regs;
297 break;
298 case I915_PARAM_HAS_OVERLAY:
299 value = dev_priv->overlay ? 1 : 0;
300 break;
0673ad47 301 case I915_PARAM_HAS_BSD:
3b3f1650 302 value = !!dev_priv->engine[VCS];
0673ad47
CW		 303 break;
304 case I915_PARAM_HAS_BLT:
3b3f1650 305 value = !!dev_priv->engine[BCS];
0673ad47
CW		 306 break;
307 case I915_PARAM_HAS_VEBOX:
3b3f1650 308 value = !!dev_priv->engine[VECS];
0673ad47
CW		 309 break;
310 case I915_PARAM_HAS_BSD2:
3b3f1650 311 value = !!dev_priv->engine[VCS2];
0673ad47 312 break;
0673ad47 313 case I915_PARAM_HAS_LLC:
16162470 314 value = HAS_LLC(dev_priv);
0673ad47
CW		 315 break;
316 case I915_PARAM_HAS_WT:
16162470 317 value = HAS_WT(dev_priv);
0673ad47
CW		 318 break;
319 case I915_PARAM_HAS_ALIASING_PPGTT:
16162470 320 value = USES_PPGTT(dev_priv);
0673ad47
CW		 321 break;
322 case I915_PARAM_HAS_SEMAPHORES:
39df9190 323 value = i915.semaphores;
0673ad47 324 break;
0673ad47
CW		 325 case I915_PARAM_HAS_SECURE_BATCHES:
326 value = capable(CAP_SYS_ADMIN);
327 break;
0673ad47
CW		 328 case I915_PARAM_CMD_PARSER_VERSION:
329 value = i915_cmd_parser_get_version(dev_priv);
330 break;
0673ad47 331 case I915_PARAM_SUBSLICE_TOTAL:
57ec171e 332 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
0673ad47
CW		 333 if (!value)
334 return -ENODEV;
335 break;
336 case I915_PARAM_EU_TOTAL:
43b67998 337 value = INTEL_INFO(dev_priv)->sseu.eu_total;
0673ad47
CW		 338 if (!value)
339 return -ENODEV;
340 break;
341 case I915_PARAM_HAS_GPU_RESET:
342 value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
142bc7d9
MT		 343 if (value && intel_has_reset_engine(dev_priv))
344 value = 2;
0673ad47
CW		 345 break;
346 case I915_PARAM_HAS_RESOURCE_STREAMER:
16162470 347 value = HAS_RESOURCE_STREAMER(dev_priv);
0673ad47 348 break;
37f501af 349 case I915_PARAM_HAS_POOLED_EU:
16162470 350 value = HAS_POOLED_EU(dev_priv);
37f501af 351 break;
352 case I915_PARAM_MIN_EU_IN_POOL:
43b67998 353 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
37f501af 354 break;
5464cd65 355 case I915_PARAM_HUC_STATUS:
3582ad13 356 intel_runtime_pm_get(dev_priv);
5464cd65 357 value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
3582ad13 358 intel_runtime_pm_put(dev_priv);
5464cd65 359 break;
4cc69075
CW		 360 case I915_PARAM_MMAP_GTT_VERSION:
361 /* Though we've started our numbering from 1, and so class all
362 * earlier versions as 0, in effect their value is undefined as
363 * the ioctl will report EINVAL for the unknown param!
364 */
365 value = i915_gem_mmap_gtt_version();
366 break;
0de9136d
CW		 367 case I915_PARAM_HAS_SCHEDULER:
368 value = dev_priv->engine[RCS] &&
369 dev_priv->engine[RCS]->schedule;
370 break;
16162470
DW		 371 case I915_PARAM_MMAP_VERSION:
372 /* Remember to bump this if the version changes! */
373 case I915_PARAM_HAS_GEM:
374 case I915_PARAM_HAS_PAGEFLIPPING:
375 case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
376 case I915_PARAM_HAS_RELAXED_FENCING:
377 case I915_PARAM_HAS_COHERENT_RINGS:
378 case I915_PARAM_HAS_RELAXED_DELTA:
379 case I915_PARAM_HAS_GEN7_SOL_RESET:
380 case I915_PARAM_HAS_WAIT_TIMEOUT:
381 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
382 case I915_PARAM_HAS_PINNED_BATCHES:
383 case I915_PARAM_HAS_EXEC_NO_RELOC:
384 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
385 case I915_PARAM_HAS_COHERENT_PHYS_GTT:
386 case I915_PARAM_HAS_EXEC_SOFTPIN:
77ae9957 387 case I915_PARAM_HAS_EXEC_ASYNC:
fec0445c 388 case I915_PARAM_HAS_EXEC_FENCE:
b0fd47ad 389 case I915_PARAM_HAS_EXEC_CAPTURE:
1a71cf2f 390 case I915_PARAM_HAS_EXEC_BATCH_FIRST:
16162470
DW		 391 /* For the time being all of these are always true;
392 * if some supported hardware does not have one of these
393 * features this value needs to be provided from
394 * INTEL_INFO(), a feature macro, or similar.
395 */
396 value = 1;
397 break;
7fed555c
RB		 398 case I915_PARAM_SLICE_MASK:
399 value = INTEL_INFO(dev_priv)->sseu.slice_mask;
400 if (!value)
401 return -ENODEV;
402 break;
f5320233
RB		 403 case I915_PARAM_SUBSLICE_MASK:
404 value = INTEL_INFO(dev_priv)->sseu.subslice_mask;
405 if (!value)
406 return -ENODEV;
407 break;
0673ad47
CW		 408 default:
409 DRM_DEBUG("Unknown parameter %d\n", param->param);
410 return -EINVAL;
411 }
412
dda33009 413 if (put_user(value, param->value))
0673ad47 414 return -EFAULT;
0673ad47
CW		 415
416 return 0;
417}
418
da5f53bf 419static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
0673ad47 420{
0673ad47
CW		 421 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
422 if (!dev_priv->bridge_dev) {
423 DRM_ERROR("bridge device not found\n");
424 return -1;
425 }
426 return 0;
427}
428
429/* Allocate space for the MCH regs if needed, return nonzero on error */
430static int
da5f53bf 431intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
0673ad47 432{
514e1d64 433 int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
0673ad47
CW		 434 u32 temp_lo, temp_hi = 0;
435 u64 mchbar_addr;
436 int ret;
437
514e1d64 438 if (INTEL_GEN(dev_priv) >= 4)
0673ad47
CW		 439 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
440 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
441 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
442
443 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
444#ifdef CONFIG_PNP
445 if (mchbar_addr &&
446 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
447 return 0;
448#endif
449
450 /* Get some space for it */
451 dev_priv->mch_res.name = "i915 MCHBAR";
452 dev_priv->mch_res.flags = IORESOURCE_MEM;
453 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
454 &dev_priv->mch_res,
455 MCHBAR_SIZE, MCHBAR_SIZE,
456 PCIBIOS_MIN_MEM,
457 0, pcibios_align_resource,
458 dev_priv->bridge_dev);
459 if (ret) {
460 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
461 dev_priv->mch_res.start = 0;
462 return ret;
463 }
464
514e1d64 465 if (INTEL_GEN(dev_priv) >= 4)
0673ad47
CW		 466 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
467 upper_32_bits(dev_priv->mch_res.start));
468
469 pci_write_config_dword(dev_priv->bridge_dev, reg,
470 lower_32_bits(dev_priv->mch_res.start));
471 return 0;
472}
473
474/* Setup MCHBAR if possible, return true if we should disable it again */
475static void
da5f53bf 476intel_setup_mchbar(struct drm_i915_private *dev_priv)
0673ad47 477{
514e1d64 478 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
0673ad47
CW		 479 u32 temp;
480 bool enabled;
481
920a14b2 482 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
0673ad47
CW		 483 return;
484
485 dev_priv->mchbar_need_disable = false;
486
50a0bc90 487 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
0673ad47
CW		 488 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
489 enabled = !!(temp & DEVEN_MCHBAR_EN);
490 } else {
491 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
492 enabled = temp & 1;
493 }
494
495 /* If it's already enabled, don't have to do anything */
496 if (enabled)
497 return;
498
da5f53bf 499 if (intel_alloc_mchbar_resource(dev_priv))
0673ad47
CW		 500 return;
501
502 dev_priv->mchbar_need_disable = true;
503
504 /* Space is allocated or reserved, so enable it. */
50a0bc90 505 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
0673ad47
CW		 506 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
507 temp | DEVEN_MCHBAR_EN);
508 } else {
509 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
510 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
511 }
512}
513
514static void
da5f53bf 515intel_teardown_mchbar(struct drm_i915_private *dev_priv)
0673ad47 516{
514e1d64 517 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
0673ad47
CW		 518
519 if (dev_priv->mchbar_need_disable) {
50a0bc90 520 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
0673ad47
CW		 521 u32 deven_val;
522
523 pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
524 &deven_val);
525 deven_val &= ~DEVEN_MCHBAR_EN;
526 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
527 deven_val);
528 } else {
529 u32 mchbar_val;
530
531 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
532 &mchbar_val);
533 mchbar_val &= ~1;
534 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
535 mchbar_val);
536 }
537 }
538
539 if (dev_priv->mch_res.start)
540 release_resource(&dev_priv->mch_res);
541}
542
543/* true = enable decode, false = disable decoder */
544static unsigned int i915_vga_set_decode(void *cookie, bool state)
545{
da5f53bf 546 struct drm_i915_private *dev_priv = cookie;
0673ad47 547
da5f53bf 548 intel_modeset_vga_set_state(dev_priv, state);
0673ad47
CW		 549 if (state)
550 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
551 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
552 else
553 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
554}
555
7f26cb88
TU		 556static int i915_resume_switcheroo(struct drm_device *dev);
557static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
558
0673ad47
CW		 559static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
560{
561 struct drm_device *dev = pci_get_drvdata(pdev);
562 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
563
564 if (state == VGA_SWITCHEROO_ON) {
565 pr_info("switched on\n");
566 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
567 /* i915 resume handler doesn't set to D0 */
52a05c30 568 pci_set_power_state(pdev, PCI_D0);
0673ad47
CW		 569 i915_resume_switcheroo(dev);
570 dev->switch_power_state = DRM_SWITCH_POWER_ON;
571 } else {
572 pr_info("switched off\n");
573 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
574 i915_suspend_switcheroo(dev, pmm);
575 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
576 }
577}
578
579static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
580{
581 struct drm_device *dev = pci_get_drvdata(pdev);
582
583 /*
584 * FIXME: open_count is protected by drm_global_mutex but that would lead to
585 * locking inversion with the driver load path. And the access here is
586 * completely racy anyway. So don't bother with locking for now.
587 */
588 return dev->open_count == 0;
589}
590
591static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
592 .set_gpu_state = i915_switcheroo_set_state,
593 .reprobe = NULL,
594 .can_switch = i915_switcheroo_can_switch,
595};
596
fbbd37b3 597static void i915_gem_fini(struct drm_i915_private *dev_priv)
0673ad47 598{
3b19f16a
CW		 599 /* Flush any outstanding unpin_work. */
600 i915_gem_drain_workqueue(dev_priv);
5f09a9c8 601
fbbd37b3 602 mutex_lock(&dev_priv->drm.struct_mutex);
b8991403 603 intel_uc_fini_hw(dev_priv);
cb15d9f8 604 i915_gem_cleanup_engines(dev_priv);
829a0af2 605 i915_gem_contexts_fini(dev_priv);
8a2421bd 606 i915_gem_cleanup_userptr(dev_priv);
fbbd37b3 607 mutex_unlock(&dev_priv->drm.struct_mutex);
0673ad47 608
bdeb9785 609 i915_gem_drain_freed_objects(dev_priv);
fbbd37b3 610
829a0af2 611 WARN_ON(!list_empty(&dev_priv->contexts.list));
0673ad47
CW		 612}
613
614static int i915_load_modeset_init(struct drm_device *dev)
615{
fac5e23e 616 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 617 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 618 int ret;
619
620 if (i915_inject_load_failure())
621 return -ENODEV;
622
66578857 623 intel_bios_init(dev_priv);
0673ad47
CW		 624
625 /* If we have > 1 VGA cards, then we need to arbitrate access
626 * to the common VGA resources.
627 *
628 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
629 * then we do not take part in VGA arbitration and the
630 * vga_client_register() fails with -ENODEV.
631 */
da5f53bf 632 ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
0673ad47
CW		 633 if (ret && ret != -ENODEV)
634 goto out;
635
636 intel_register_dsm_handler();
637
52a05c30 638 ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
0673ad47
CW		 639 if (ret)
640 goto cleanup_vga_client;
641
642 /* must happen before intel_power_domains_init_hw() on VLV/CHV */
643 intel_update_rawclk(dev_priv);
644
645 intel_power_domains_init_hw(dev_priv, false);
646
647 intel_csr_ucode_init(dev_priv);
648
649 ret = intel_irq_install(dev_priv);
650 if (ret)
651 goto cleanup_csr;
652
40196446 653 intel_setup_gmbus(dev_priv);
0673ad47
CW		 654
655 /* Important: The output setup functions called by modeset_init need
656 * working irqs for e.g. gmbus and dp aux transfers. */
b079bd17
VS		 657 ret = intel_modeset_init(dev);
658 if (ret)
659 goto cleanup_irq;
0673ad47 660
29ad6a30 661 intel_uc_init_fw(dev_priv);
0673ad47 662
bf9e8429 663 ret = i915_gem_init(dev_priv);
0673ad47 664 if (ret)
3950bf3d 665 goto cleanup_uc;
0673ad47
CW		 666
667 intel_modeset_gem_init(dev);
668
b7f05d4a 669 if (INTEL_INFO(dev_priv)->num_pipes == 0)
0673ad47
CW		 670 return 0;
671
672 ret = intel_fbdev_init(dev);
673 if (ret)
674 goto cleanup_gem;
675
676 /* Only enable hotplug handling once the fbdev is fully set up. */
677 intel_hpd_init(dev_priv);
678
679 drm_kms_helper_poll_init(dev);
680
681 return 0;
682
683cleanup_gem:
bf9e8429 684 if (i915_gem_suspend(dev_priv))
1c777c5d 685 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
fbbd37b3 686 i915_gem_fini(dev_priv);
3950bf3d
OM		 687cleanup_uc:
688 intel_uc_fini_fw(dev_priv);
0673ad47 689cleanup_irq:
0673ad47 690 drm_irq_uninstall(dev);
40196446 691 intel_teardown_gmbus(dev_priv);
0673ad47
CW		 692cleanup_csr:
693 intel_csr_ucode_fini(dev_priv);
694 intel_power_domains_fini(dev_priv);
52a05c30 695 vga_switcheroo_unregister_client(pdev);
0673ad47 696cleanup_vga_client:
52a05c30 697 vga_client_register(pdev, NULL, NULL, NULL);
0673ad47
CW		 698out:
699 return ret;
700}
701
0673ad47
CW		 702static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
703{
704 struct apertures_struct *ap;
91c8a326 705 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 706 struct i915_ggtt *ggtt = &dev_priv->ggtt;
707 bool primary;
708 int ret;
709
710 ap = alloc_apertures(1);
711 if (!ap)
712 return -ENOMEM;
713
714 ap->ranges[0].base = ggtt->mappable_base;
715 ap->ranges[0].size = ggtt->mappable_end;
716
717 primary =
718 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
719
44adece5 720 ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
0673ad47
CW		 721
722 kfree(ap);
723
724 return ret;
725}
0673ad47
CW		 726
727#if !defined(CONFIG_VGA_CONSOLE)
728static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
729{
730 return 0;
731}
732#elif !defined(CONFIG_DUMMY_CONSOLE)
733static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
734{
735 return -ENODEV;
736}
737#else
738static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
739{
740 int ret = 0;
741
742 DRM_INFO("Replacing VGA console driver\n");
743
744 console_lock();
745 if (con_is_bound(&vga_con))
746 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
747 if (ret == 0) {
748 ret = do_unregister_con_driver(&vga_con);
749
750 /* Ignore "already unregistered". */
751 if (ret == -ENODEV)
752 ret = 0;
753 }
754 console_unlock();
755
756 return ret;
757}
758#endif
759
0673ad47
CW		 760static void intel_init_dpio(struct drm_i915_private *dev_priv)
761{
762 /*
763 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
764 * CHV x1 PHY (DP/HDMI D)
765 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
766 */
767 if (IS_CHERRYVIEW(dev_priv)) {
768 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
769 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
770 } else if (IS_VALLEYVIEW(dev_priv)) {
771 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
772 }
773}
774
775static int i915_workqueues_init(struct drm_i915_private *dev_priv)
776{
777 /*
778 * The i915 workqueue is primarily used for batched retirement of
779 * requests (and thus managing bo) once the task has been completed
780 * by the GPU. i915_gem_retire_requests() is called directly when we
781 * need high-priority retirement, such as waiting for an explicit
782 * bo.
783 *
784 * It is also used for periodic low-priority events, such as
785 * idle-timers and recording error state.
786 *
787 * All tasks on the workqueue are expected to acquire the dev mutex
788 * so there is no point in running more than one instance of the
789 * workqueue at any time. Use an ordered one.
790 */
791 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
792 if (dev_priv->wq == NULL)
793 goto out_err;
794
795 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
796 if (dev_priv->hotplug.dp_wq == NULL)
797 goto out_free_wq;
798
0673ad47
CW		 799 return 0;
800
0673ad47
CW		 801out_free_wq:
802 destroy_workqueue(dev_priv->wq);
803out_err:
804 DRM_ERROR("Failed to allocate workqueues.\n");
805
806 return -ENOMEM;
807}
808
bb8f0f5a
CW		 809static void i915_engines_cleanup(struct drm_i915_private *i915)
810{
811 struct intel_engine_cs *engine;
812 enum intel_engine_id id;
813
814 for_each_engine(engine, i915, id)
815 kfree(engine);
816}
817
0673ad47
CW		 818static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
819{
0673ad47
CW		 820 destroy_workqueue(dev_priv->hotplug.dp_wq);
821 destroy_workqueue(dev_priv->wq);
822}
823
4fc7e845
PZ		 824/*
825 * We don't keep the workarounds for pre-production hardware, so we expect our
826 * driver to fail on these machines in one way or another. A little warning on
827 * dmesg may help both the user and the bug triagers.
828 */
829static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
830{
248a124d
CW		 831 bool pre = false;
832
833 pre |= IS_HSW_EARLY_SDV(dev_priv);
834 pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
0102ba1f 835 pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
248a124d 836
7c5ff4a2 837 if (pre) {
4fc7e845
PZ		 838 DRM_ERROR("This is a pre-production stepping. "
839 "It may not be fully functional.\n");
7c5ff4a2
CW		 840 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
841 }
4fc7e845
PZ		 842}
843
0673ad47
CW		 844/**
845 * i915_driver_init_early - setup state not requiring device access
846 * @dev_priv: device private
847 *
848 * Initialize everything that is a "SW-only" state, that is state not
849 * requiring accessing the device or exposing the driver via kernel internal
850 * or userspace interfaces. Example steps belonging here: lock initialization,
851 * system memory allocation, setting up device specific attributes and
852 * function hooks not requiring accessing the device.
853 */
854static int i915_driver_init_early(struct drm_i915_private *dev_priv,
855 const struct pci_device_id *ent)
856{
857 const struct intel_device_info *match_info =
858 (struct intel_device_info *)ent->driver_data;
859 struct intel_device_info *device_info;
860 int ret = 0;
861
862 if (i915_inject_load_failure())
863 return -ENODEV;
864
865 /* Setup the write-once "constant" device info */
94b4f3ba 866 device_info = mkwrite_device_info(dev_priv);
0673ad47
CW		 867 memcpy(device_info, match_info, sizeof(*device_info));
868 device_info->device_id = dev_priv->drm.pdev->device;
869
870 BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
871 device_info->gen_mask = BIT(device_info->gen - 1);
872
873 spin_lock_init(&dev_priv->irq_lock);
874 spin_lock_init(&dev_priv->gpu_error.lock);
875 mutex_init(&dev_priv->backlight_lock);
876 spin_lock_init(&dev_priv->uncore.lock);
317eaa95 877
0673ad47
CW		 878 spin_lock_init(&dev_priv->mm.object_stat_lock);
879 spin_lock_init(&dev_priv->mmio_flip_lock);
880 mutex_init(&dev_priv->sb_lock);
881 mutex_init(&dev_priv->modeset_restore_lock);
882 mutex_init(&dev_priv->av_mutex);
883 mutex_init(&dev_priv->wm.wm_mutex);
884 mutex_init(&dev_priv->pps_mutex);
885
413e8fdb 886 intel_uc_init_early(dev_priv);
0b1de5d5
CW		 887 i915_memcpy_init_early(dev_priv);
888
0673ad47
CW		 889 ret = i915_workqueues_init(dev_priv);
890 if (ret < 0)
bb8f0f5a 891 goto err_engines;
0673ad47 892
0673ad47 893 /* This must be called before any calls to HAS_PCH_* */
da5f53bf 894 intel_detect_pch(dev_priv);
0673ad47 895
192aa181 896 intel_pm_setup(dev_priv);
0673ad47
CW		 897 intel_init_dpio(dev_priv);
898 intel_power_domains_init(dev_priv);
899 intel_irq_init(dev_priv);
3ac168a7 900 intel_hangcheck_init(dev_priv);
0673ad47
CW		 901 intel_init_display_hooks(dev_priv);
902 intel_init_clock_gating_hooks(dev_priv);
903 intel_init_audio_hooks(dev_priv);
cb15d9f8 904 ret = i915_gem_load_init(dev_priv);
73cb9701 905 if (ret < 0)
cefcff8f 906 goto err_irq;
0673ad47 907
36cdd013 908 intel_display_crc_init(dev_priv);
0673ad47 909
94b4f3ba 910 intel_device_info_dump(dev_priv);
0673ad47 911
4fc7e845 912 intel_detect_preproduction_hw(dev_priv);
0673ad47 913
eec688e1
RB		 914 i915_perf_init(dev_priv);
915
0673ad47
CW		 916 return 0;
917
cefcff8f
JL		 918err_irq:
919 intel_irq_fini(dev_priv);
0673ad47 920 i915_workqueues_cleanup(dev_priv);
bb8f0f5a
CW		 921err_engines:
922 i915_engines_cleanup(dev_priv);
0673ad47
CW		 923 return ret;
924}
925
926/**
927 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
928 * @dev_priv: device private
929 */
930static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
931{
eec688e1 932 i915_perf_fini(dev_priv);
cb15d9f8 933 i915_gem_load_cleanup(dev_priv);
cefcff8f 934 intel_irq_fini(dev_priv);
0673ad47 935 i915_workqueues_cleanup(dev_priv);
bb8f0f5a 936 i915_engines_cleanup(dev_priv);
0673ad47
CW		 937}
938
da5f53bf 939static int i915_mmio_setup(struct drm_i915_private *dev_priv)
0673ad47 940{
52a05c30 941 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 942 int mmio_bar;
943 int mmio_size;
944
5db94019 945 mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
0673ad47
CW		 946 /*
947 * Before gen4, the registers and the GTT are behind different BARs.
948 * However, from gen4 onwards, the registers and the GTT are shared
949 * in the same BAR, so we want to restrict this ioremap from
950 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
951 * the register BAR remains the same size for all the earlier
952 * generations up to Ironlake.
953 */
514e1d64 954 if (INTEL_GEN(dev_priv) < 5)
0673ad47
CW		 955 mmio_size = 512 * 1024;
956 else
957 mmio_size = 2 * 1024 * 1024;
52a05c30 958 dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
0673ad47
CW		 959 if (dev_priv->regs == NULL) {
960 DRM_ERROR("failed to map registers\n");
961
962 return -EIO;
963 }
964
965 /* Try to make sure MCHBAR is enabled before poking at it */
da5f53bf 966 intel_setup_mchbar(dev_priv);
0673ad47
CW		 967
968 return 0;
969}
970
da5f53bf 971static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
0673ad47 972{
52a05c30 973 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47 974
da5f53bf 975 intel_teardown_mchbar(dev_priv);
52a05c30 976 pci_iounmap(pdev, dev_priv->regs);
0673ad47
CW		 977}
978
979/**
980 * i915_driver_init_mmio - setup device MMIO
981 * @dev_priv: device private
982 *
983 * Setup minimal device state necessary for MMIO accesses later in the
984 * initialization sequence. The setup here should avoid any other device-wide
985 * side effects or exposing the driver via kernel internal or user space
986 * interfaces.
987 */
988static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
989{
0673ad47
CW		 990 int ret;
991
992 if (i915_inject_load_failure())
993 return -ENODEV;
994
da5f53bf 995 if (i915_get_bridge_dev(dev_priv))
0673ad47
CW		 996 return -EIO;
997
da5f53bf 998 ret = i915_mmio_setup(dev_priv);
0673ad47 999 if (ret < 0)
63ffbcda 1000 goto err_bridge;
0673ad47
CW		 1001
1002 intel_uncore_init(dev_priv);
63ffbcda
JL		 1003
1004 ret = intel_engines_init_mmio(dev_priv);
1005 if (ret)
1006 goto err_uncore;
1007
24145517 1008 i915_gem_init_mmio(dev_priv);
0673ad47
CW		 1009
1010 return 0;
1011
63ffbcda
JL		 1012err_uncore:
1013 intel_uncore_fini(dev_priv);
1014err_bridge:
0673ad47
CW		 1015 pci_dev_put(dev_priv->bridge_dev);
1016
1017 return ret;
1018}
1019
1020/**
1021 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1022 * @dev_priv: device private
1023 */
1024static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1025{
0673ad47 1026 intel_uncore_fini(dev_priv);
da5f53bf 1027 i915_mmio_cleanup(dev_priv);
0673ad47
CW		 1028 pci_dev_put(dev_priv->bridge_dev);
1029}
1030
94b4f3ba
CW		 1031static void intel_sanitize_options(struct drm_i915_private *dev_priv)
1032{
1033 i915.enable_execlists =
1034 intel_sanitize_enable_execlists(dev_priv,
1035 i915.enable_execlists);
1036
1037 /*
1038 * i915.enable_ppgtt is read-only, so do an early pass to validate the
1039 * user's requested state against the hardware/driver capabilities. We
1040 * do this now so that we can print out any log messages once rather
1041 * than every time we check intel_enable_ppgtt().
1042 */
1043 i915.enable_ppgtt =
1044 intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
1045 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
39df9190
CW		 1046
1047 i915.semaphores = intel_sanitize_semaphores(dev_priv, i915.semaphores);
784f2f1a 1048 DRM_DEBUG_DRIVER("use GPU semaphores? %s\n", yesno(i915.semaphores));
d2be9f2f
AH		 1049
1050 intel_uc_sanitize_options(dev_priv);
67b7f33e
CD		 1051
1052 intel_gvt_sanitize_options(dev_priv);
94b4f3ba
CW		 1053}
1054
0673ad47
CW		 1055/**
1056 * i915_driver_init_hw - setup state requiring device access
1057 * @dev_priv: device private
1058 *
1059 * Setup state that requires accessing the device, but doesn't require
1060 * exposing the driver via kernel internal or userspace interfaces.
1061 */
1062static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1063{
52a05c30 1064 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 1065 int ret;
1066
1067 if (i915_inject_load_failure())
1068 return -ENODEV;
1069
94b4f3ba
CW		 1070 intel_device_info_runtime_init(dev_priv);
1071
1072 intel_sanitize_options(dev_priv);
0673ad47 1073
97d6d7ab 1074 ret = i915_ggtt_probe_hw(dev_priv);
0673ad47
CW		 1075 if (ret)
1076 return ret;
1077
0673ad47
CW		 1078 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1079 * otherwise the vga fbdev driver falls over. */
1080 ret = i915_kick_out_firmware_fb(dev_priv);
1081 if (ret) {
1082 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1083 goto out_ggtt;
1084 }
1085
1086 ret = i915_kick_out_vgacon(dev_priv);
1087 if (ret) {
1088 DRM_ERROR("failed to remove conflicting VGA console\n");
1089 goto out_ggtt;
1090 }
1091
97d6d7ab 1092 ret = i915_ggtt_init_hw(dev_priv);
0088e522
CW		 1093 if (ret)
1094 return ret;
1095
97d6d7ab 1096 ret = i915_ggtt_enable_hw(dev_priv);
0088e522
CW		 1097 if (ret) {
1098 DRM_ERROR("failed to enable GGTT\n");
1099 goto out_ggtt;
1100 }
1101
52a05c30 1102 pci_set_master(pdev);
0673ad47
CW		 1103
1104 /* overlay on gen2 is broken and can't address above 1G */
5db94019 1105 if (IS_GEN2(dev_priv)) {
52a05c30 1106 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
0673ad47
CW		 1107 if (ret) {
1108 DRM_ERROR("failed to set DMA mask\n");
1109
1110 goto out_ggtt;
1111 }
1112 }
1113
0673ad47
CW		 1114 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1115 * using 32bit addressing, overwriting memory if HWS is located
1116 * above 4GB.
1117 *
1118 * The documentation also mentions an issue with undefined
1119 * behaviour if any general state is accessed within a page above 4GB,
1120 * which also needs to be handled carefully.
1121 */
c0f86832 1122 if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
52a05c30 1123 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
0673ad47
CW		 1124
1125 if (ret) {
1126 DRM_ERROR("failed to set DMA mask\n");
1127
1128 goto out_ggtt;
1129 }
1130 }
1131
0673ad47
CW		 1132 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1133 PM_QOS_DEFAULT_VALUE);
1134
1135 intel_uncore_sanitize(dev_priv);
1136
1137 intel_opregion_setup(dev_priv);
1138
1139 i915_gem_load_init_fences(dev_priv);
1140
1141 /* On the 945G/GM, the chipset reports the MSI capability on the
1142 * integrated graphics even though the support isn't actually there
1143 * according to the published specs. It doesn't appear to function
1144 * correctly in testing on 945G.
1145 * This may be a side effect of MSI having been made available for PEG
1146 * and the registers being closely associated.
1147 *
1148 * According to chipset errata, on the 965GM, MSI interrupts may
e38c2da0
VS		 1149 * be lost or delayed, and was defeatured. MSI interrupts seem to
1150 * get lost on g4x as well, and interrupt delivery seems to stay
1151 * properly dead afterwards. So we'll just disable them for all
1152 * pre-gen5 chipsets.
0673ad47 1153 */
e38c2da0 1154 if (INTEL_GEN(dev_priv) >= 5) {
52a05c30 1155 if (pci_enable_msi(pdev) < 0)
0673ad47
CW		 1156 DRM_DEBUG_DRIVER("can't enable MSI");
1157 }
1158
26f837e8
ZW		 1159 ret = intel_gvt_init(dev_priv);
1160 if (ret)
1161 goto out_ggtt;
1162
0673ad47
CW		 1163 return 0;
1164
1165out_ggtt:
97d6d7ab 1166 i915_ggtt_cleanup_hw(dev_priv);
0673ad47
CW		 1167
1168 return ret;
1169}
1170
1171/**
1172 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1173 * @dev_priv: device private
1174 */
1175static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1176{
52a05c30 1177 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47 1178
52a05c30
DW		 1179 if (pdev->msi_enabled)
1180 pci_disable_msi(pdev);
0673ad47
CW		 1181
1182 pm_qos_remove_request(&dev_priv->pm_qos);
97d6d7ab 1183 i915_ggtt_cleanup_hw(dev_priv);
0673ad47
CW		 1184}
1185
1186/**
1187 * i915_driver_register - register the driver with the rest of the system
1188 * @dev_priv: device private
1189 *
1190 * Perform any steps necessary to make the driver available via kernel
1191 * internal or userspace interfaces.
1192 */
1193static void i915_driver_register(struct drm_i915_private *dev_priv)
1194{
91c8a326 1195 struct drm_device *dev = &dev_priv->drm;
0673ad47
CW		 1196
1197 i915_gem_shrinker_init(dev_priv);
1198
1199 /*
1200 * Notify a valid surface after modesetting,
1201 * when running inside a VM.
1202 */
1203 if (intel_vgpu_active(dev_priv))
1204 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1205
1206 /* Reveal our presence to userspace */
1207 if (drm_dev_register(dev, 0) == 0) {
1208 i915_debugfs_register(dev_priv);
f9cda048 1209 i915_guc_log_register(dev_priv);
694c2828 1210 i915_setup_sysfs(dev_priv);
442b8c06
RB		 1211
1212 /* Depends on sysfs having been initialized */
1213 i915_perf_register(dev_priv);
0673ad47
CW		 1214 } else
1215 DRM_ERROR("Failed to register driver for userspace access!\n");
1216
1217 if (INTEL_INFO(dev_priv)->num_pipes) {
1218 /* Must be done after probing outputs */
1219 intel_opregion_register(dev_priv);
1220 acpi_video_register();
1221 }
1222
1223 if (IS_GEN5(dev_priv))
1224 intel_gpu_ips_init(dev_priv);
1225
eef57324 1226 intel_audio_init(dev_priv);
0673ad47
CW		 1227
1228 /*
1229 * Some ports require correctly set-up hpd registers for detection to
1230 * work properly (leading to ghost connected connector status), e.g. VGA
1231 * on gm45. Hence we can only set up the initial fbdev config after hpd
1232 * irqs are fully enabled. We do it last so that the async config
1233 * cannot run before the connectors are registered.
1234 */
1235 intel_fbdev_initial_config_async(dev);
1236}
1237
1238/**
1239 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1240 * @dev_priv: device private
1241 */
1242static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1243{
4f256d82 1244 intel_fbdev_unregister(dev_priv);
eef57324 1245 intel_audio_deinit(dev_priv);
0673ad47
CW		 1246
1247 intel_gpu_ips_teardown();
1248 acpi_video_unregister();
1249 intel_opregion_unregister(dev_priv);
1250
442b8c06
RB		 1251 i915_perf_unregister(dev_priv);
1252
694c2828 1253 i915_teardown_sysfs(dev_priv);
f9cda048 1254 i915_guc_log_unregister(dev_priv);
91c8a326 1255 drm_dev_unregister(&dev_priv->drm);
0673ad47
CW		 1256
1257 i915_gem_shrinker_cleanup(dev_priv);
1258}
1259
1260/**
1261 * i915_driver_load - setup chip and create an initial config
d2ad3ae4
JL		 1262 * @pdev: PCI device
1263 * @ent: matching PCI ID entry
0673ad47
CW		 1264 *
1265 * The driver load routine has to do several things:
1266 * - drive output discovery via intel_modeset_init()
1267 * - initialize the memory manager
1268 * - allocate initial config memory
1269 * - setup the DRM framebuffer with the allocated memory
1270 */
42f5551d 1271int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
0673ad47 1272{
8d2b47dd
ML		 1273 const struct intel_device_info *match_info =
1274 (struct intel_device_info *)ent->driver_data;
0673ad47
CW		 1275 struct drm_i915_private *dev_priv;
1276 int ret;
7d87a7f7 1277
ff4c3b76
VS		 1278 /* Enable nuclear pageflip on ILK+ */
1279 if (!i915.nuclear_pageflip && match_info->gen < 5)
8d2b47dd 1280 driver.driver_features &= ~DRIVER_ATOMIC;
a09d0ba1 1281
0673ad47
CW		 1282 ret = -ENOMEM;
1283 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1284 if (dev_priv)
1285 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1286 if (ret) {
87a6752c 1287 DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
cad3688f 1288 goto out_free;
0673ad47 1289 }
72bbf0af 1290
0673ad47
CW		 1291 dev_priv->drm.pdev = pdev;
1292 dev_priv->drm.dev_private = dev_priv;
719388e1 1293
0673ad47
CW		 1294 ret = pci_enable_device(pdev);
1295 if (ret)
cad3688f 1296 goto out_fini;
1347f5b4 1297
0673ad47 1298 pci_set_drvdata(pdev, &dev_priv->drm);
adfdf85d
ID		 1299 /*
1300 * Disable the system suspend direct complete optimization, which can
1301 * leave the device suspended skipping the driver's suspend handlers
1302 * if the device was already runtime suspended. This is needed due to
1303 * the difference in our runtime and system suspend sequence and
1304 * becaue the HDA driver may require us to enable the audio power
1305 * domain during system suspend.
1306 */
1307 pdev->dev_flags |= PCI_DEV_FLAGS_NEEDS_RESUME;
ef11bdb3 1308
0673ad47
CW		 1309 ret = i915_driver_init_early(dev_priv, ent);
1310 if (ret < 0)
1311 goto out_pci_disable;
ef11bdb3 1312
0673ad47 1313 intel_runtime_pm_get(dev_priv);
1da177e4 1314
0673ad47
CW		 1315 ret = i915_driver_init_mmio(dev_priv);
1316 if (ret < 0)
1317 goto out_runtime_pm_put;
79e53945 1318
0673ad47
CW		 1319 ret = i915_driver_init_hw(dev_priv);
1320 if (ret < 0)
1321 goto out_cleanup_mmio;
30c964a6
RB		 1322
1323 /*
0673ad47
CW		 1324 * TODO: move the vblank init and parts of modeset init steps into one
1325 * of the i915_driver_init_/i915_driver_register functions according
1326 * to the role/effect of the given init step.
30c964a6 1327 */
0673ad47 1328 if (INTEL_INFO(dev_priv)->num_pipes) {
91c8a326 1329 ret = drm_vblank_init(&dev_priv->drm,
0673ad47
CW		 1330 INTEL_INFO(dev_priv)->num_pipes);
1331 if (ret)
1332 goto out_cleanup_hw;
30c964a6
RB		 1333 }
1334
91c8a326 1335 ret = i915_load_modeset_init(&dev_priv->drm);
0673ad47
CW		 1336 if (ret < 0)
1337 goto out_cleanup_vblank;
1338
1339 i915_driver_register(dev_priv);
1340
1341 intel_runtime_pm_enable(dev_priv);
1342
a3a8986c
MK		 1343 dev_priv->ipc_enabled = false;
1344
0525a062
CW		 1345 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1346 DRM_INFO("DRM_I915_DEBUG enabled\n");
1347 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1348 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
bc5ca47c 1349
0673ad47
CW		 1350 intel_runtime_pm_put(dev_priv);
1351
1352 return 0;
1353
1354out_cleanup_vblank:
91c8a326 1355 drm_vblank_cleanup(&dev_priv->drm);
0673ad47
CW		 1356out_cleanup_hw:
1357 i915_driver_cleanup_hw(dev_priv);
1358out_cleanup_mmio:
1359 i915_driver_cleanup_mmio(dev_priv);
1360out_runtime_pm_put:
1361 intel_runtime_pm_put(dev_priv);
1362 i915_driver_cleanup_early(dev_priv);
1363out_pci_disable:
1364 pci_disable_device(pdev);
cad3688f 1365out_fini:
0673ad47 1366 i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
cad3688f
CW		 1367 drm_dev_fini(&dev_priv->drm);
1368out_free:
1369 kfree(dev_priv);
30c964a6
RB		 1370 return ret;
1371}
1372
42f5551d 1373void i915_driver_unload(struct drm_device *dev)
3bad0781 1374{
fac5e23e 1375 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 1376 struct pci_dev *pdev = dev_priv->drm.pdev;
3bad0781 1377
bf9e8429 1378 if (i915_gem_suspend(dev_priv))
42f5551d 1379 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
ce1bb329 1380
0673ad47
CW		 1381 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1382
18dddadc 1383 drm_atomic_helper_shutdown(dev);
a667fb40 1384
26f837e8
ZW		 1385 intel_gvt_cleanup(dev_priv);
1386
0673ad47
CW		 1387 i915_driver_unregister(dev_priv);
1388
1389 drm_vblank_cleanup(dev);
1390
1391 intel_modeset_cleanup(dev);
1392
3bad0781 1393 /*
0673ad47
CW		 1394 * free the memory space allocated for the child device
1395 * config parsed from VBT
3bad0781 1396 */
0673ad47
CW		 1397 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1398 kfree(dev_priv->vbt.child_dev);
1399 dev_priv->vbt.child_dev = NULL;
1400 dev_priv->vbt.child_dev_num = 0;
1401 }
1402 kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1403 dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1404 kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1405 dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
3bad0781 1406
52a05c30
DW		 1407 vga_switcheroo_unregister_client(pdev);
1408 vga_client_register(pdev, NULL, NULL, NULL);
bcdb72ac 1409
0673ad47 1410 intel_csr_ucode_fini(dev_priv);
bcdb72ac 1411
0673ad47
CW		 1412 /* Free error state after interrupts are fully disabled. */
1413 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
5a4c6f1b 1414 i915_reset_error_state(dev_priv);
0673ad47 1415
fbbd37b3 1416 i915_gem_fini(dev_priv);
3950bf3d 1417 intel_uc_fini_fw(dev_priv);
0673ad47
CW		 1418 intel_fbc_cleanup_cfb(dev_priv);
1419
1420 intel_power_domains_fini(dev_priv);
1421
1422 i915_driver_cleanup_hw(dev_priv);
1423 i915_driver_cleanup_mmio(dev_priv);
1424
1425 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
cad3688f
CW		 1426}
1427
1428static void i915_driver_release(struct drm_device *dev)
1429{
1430 struct drm_i915_private *dev_priv = to_i915(dev);
0673ad47
CW		 1431
1432 i915_driver_cleanup_early(dev_priv);
cad3688f
CW		 1433 drm_dev_fini(&dev_priv->drm);
1434
1435 kfree(dev_priv);
3bad0781
ZW		 1436}
1437
0673ad47 1438static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
2911a35b 1439{
829a0af2 1440 struct drm_i915_private *i915 = to_i915(dev);
0673ad47 1441 int ret;
2911a35b 1442
829a0af2 1443 ret = i915_gem_open(i915, file);
0673ad47
CW		 1444 if (ret)
1445 return ret;
2911a35b 1446
0673ad47
CW		 1447 return 0;
1448}
71386ef9 1449
0673ad47
CW		 1450/**
1451 * i915_driver_lastclose - clean up after all DRM clients have exited
1452 * @dev: DRM device
1453 *
1454 * Take care of cleaning up after all DRM clients have exited. In the
1455 * mode setting case, we want to restore the kernel's initial mode (just
1456 * in case the last client left us in a bad state).
1457 *
1458 * Additionally, in the non-mode setting case, we'll tear down the GTT
1459 * and DMA structures, since the kernel won't be using them, and clea
1460 * up any GEM state.
1461 */
1462static void i915_driver_lastclose(struct drm_device *dev)
1463{
1464 intel_fbdev_restore_mode(dev);
1465 vga_switcheroo_process_delayed_switch();
1466}
2911a35b 1467
7d2ec881 1468static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
0673ad47 1469{
7d2ec881
DV		 1470 struct drm_i915_file_private *file_priv = file->driver_priv;
1471
0673ad47 1472 mutex_lock(&dev->struct_mutex);
829a0af2 1473 i915_gem_context_close(file);
0673ad47
CW		 1474 i915_gem_release(dev, file);
1475 mutex_unlock(&dev->struct_mutex);
0673ad47
CW		 1476
1477 kfree(file_priv);
2911a35b
BW		 1478}
1479
07f9cd0b
ID		 1480static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1481{
91c8a326 1482 struct drm_device *dev = &dev_priv->drm;
19c8054c 1483 struct intel_encoder *encoder;
07f9cd0b
ID		 1484
1485 drm_modeset_lock_all(dev);
19c8054c
JN		 1486 for_each_intel_encoder(dev, encoder)
1487 if (encoder->suspend)
1488 encoder->suspend(encoder);
07f9cd0b
ID		 1489 drm_modeset_unlock_all(dev);
1490}
1491
1a5df187
PZ		 1492static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1493 bool rpm_resume);
507e126e 1494static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
f75a1985 1495
bc87229f
ID		 1496static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1497{
1498#if IS_ENABLED(CONFIG_ACPI_SLEEP)
1499 if (acpi_target_system_state() < ACPI_STATE_S3)
1500 return true;
1501#endif
1502 return false;
1503}
ebc32824 1504
5e365c39 1505static int i915_drm_suspend(struct drm_device *dev)
ba8bbcf6 1506{
fac5e23e 1507 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 1508 struct pci_dev *pdev = dev_priv->drm.pdev;
e5747e3a 1509 pci_power_t opregion_target_state;
d5818938 1510 int error;
61caf87c 1511
b8efb17b
ZR		 1512 /* ignore lid events during suspend */
1513 mutex_lock(&dev_priv->modeset_restore_lock);
1514 dev_priv->modeset_restore = MODESET_SUSPENDED;
1515 mutex_unlock(&dev_priv->modeset_restore_lock);
1516
1f814dac
ID		 1517 disable_rpm_wakeref_asserts(dev_priv);
1518
c67a470b
PZ		 1519 /* We do a lot of poking in a lot of registers, make sure they work
1520 * properly. */
da7e29bd 1521 intel_display_set_init_power(dev_priv, true);
cb10799c 1522
5bcf719b
DA		 1523 drm_kms_helper_poll_disable(dev);
1524
52a05c30 1525 pci_save_state(pdev);
ba8bbcf6 1526
bf9e8429 1527 error = i915_gem_suspend(dev_priv);
d5818938 1528 if (error) {
52a05c30 1529 dev_err(&pdev->dev,
d5818938 1530 "GEM idle failed, resume might fail\n");
1f814dac 1531 goto out;
d5818938 1532 }
db1b76ca 1533
6b72d486 1534 intel_display_suspend(dev);
2eb5252e 1535
d5818938 1536 intel_dp_mst_suspend(dev);
7d708ee4 1537
d5818938
DV		 1538 intel_runtime_pm_disable_interrupts(dev_priv);
1539 intel_hpd_cancel_work(dev_priv);
09b64267 1540
d5818938 1541 intel_suspend_encoders(dev_priv);
0e32b39c 1542
712bf364 1543 intel_suspend_hw(dev_priv);
5669fcac 1544
275a991c 1545 i915_gem_suspend_gtt_mappings(dev_priv);
828c7908 1546
af6dc742 1547 i915_save_state(dev_priv);
9e06dd39 1548
bc87229f 1549 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
6f9f4b7a 1550 intel_opregion_notify_adapter(dev_priv, opregion_target_state);
e5747e3a 1551
68f60946 1552 intel_uncore_suspend(dev_priv);
03d92e47 1553 intel_opregion_unregister(dev_priv);
8ee1c3db 1554
82e3b8c1 1555 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
3fa016a0 1556
62d5d69b
MK		 1557 dev_priv->suspend_count++;
1558
f74ed08d 1559 intel_csr_ucode_suspend(dev_priv);
f514c2d8 1560
1f814dac
ID		 1561out:
1562 enable_rpm_wakeref_asserts(dev_priv);
1563
1564 return error;
84b79f8d
RW		 1565}
1566
c49d13ee 1567static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
c3c09c95 1568{
c49d13ee 1569 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 1570 struct pci_dev *pdev = dev_priv->drm.pdev;
bc87229f 1571 bool fw_csr;
c3c09c95
ID		 1572 int ret;
1573
1f814dac
ID		 1574 disable_rpm_wakeref_asserts(dev_priv);
1575
4c494a57
ID		 1576 intel_display_set_init_power(dev_priv, false);
1577
b9fd799e 1578 fw_csr = !IS_GEN9_LP(dev_priv) &&
a7c8125f 1579 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
bc87229f
ID		 1580 /*
1581 * In case of firmware assisted context save/restore don't manually
1582 * deinit the power domains. This also means the CSR/DMC firmware will
1583 * stay active, it will power down any HW resources as required and
1584 * also enable deeper system power states that would be blocked if the
1585 * firmware was inactive.
1586 */
1587 if (!fw_csr)
1588 intel_power_domains_suspend(dev_priv);
73dfc227 1589
507e126e 1590 ret = 0;
b9fd799e 1591 if (IS_GEN9_LP(dev_priv))
507e126e 1592 bxt_enable_dc9(dev_priv);
b8aea3d1 1593 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
507e126e
ID		 1594 hsw_enable_pc8(dev_priv);
1595 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1596 ret = vlv_suspend_complete(dev_priv);
c3c09c95
ID		 1597
1598 if (ret) {
1599 DRM_ERROR("Suspend complete failed: %d\n", ret);
bc87229f
ID		 1600 if (!fw_csr)
1601 intel_power_domains_init_hw(dev_priv, true);
c3c09c95 1602
1f814dac 1603 goto out;
c3c09c95
ID		 1604 }
1605
52a05c30 1606 pci_disable_device(pdev);
ab3be73f 1607 /*
54875571 1608 * During hibernation on some platforms the BIOS may try to access
ab3be73f
ID		 1609 * the device even though it's already in D3 and hang the machine. So
1610 * leave the device in D0 on those platforms and hope the BIOS will
54875571
ID		 1611 * power down the device properly. The issue was seen on multiple old
1612 * GENs with different BIOS vendors, so having an explicit blacklist
1613 * is inpractical; apply the workaround on everything pre GEN6. The
1614 * platforms where the issue was seen:
1615 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1616 * Fujitsu FSC S7110
1617 * Acer Aspire 1830T
ab3be73f 1618 */
514e1d64 1619 if (!(hibernation && INTEL_GEN(dev_priv) < 6))
52a05c30 1620 pci_set_power_state(pdev, PCI_D3hot);
c3c09c95 1621
bc87229f
ID		 1622 dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1623
1f814dac
ID		 1624out:
1625 enable_rpm_wakeref_asserts(dev_priv);
1626
1627 return ret;
c3c09c95
ID		 1628}
1629
a9a251c2 1630static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
84b79f8d
RW		 1631{
1632 int error;
1633
ded8b07d 1634 if (!dev) {
84b79f8d
RW		 1635 DRM_ERROR("dev: %p\n", dev);
1636 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1637 return -ENODEV;
1638 }
1639
0b14cbd2
ID		 1640 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1641 state.event != PM_EVENT_FREEZE))
1642 return -EINVAL;
5bcf719b
DA		 1643
1644 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1645 return 0;
6eecba33 1646
5e365c39 1647 error = i915_drm_suspend(dev);
84b79f8d
RW		 1648 if (error)
1649 return error;
1650
ab3be73f 1651 return i915_drm_suspend_late(dev, false);
ba8bbcf6
JB		 1652}
1653
5e365c39 1654static int i915_drm_resume(struct drm_device *dev)
76c4b250 1655{
fac5e23e 1656 struct drm_i915_private *dev_priv = to_i915(dev);
ac840ae5 1657 int ret;
9d49c0ef 1658
1f814dac 1659 disable_rpm_wakeref_asserts(dev_priv);
abc80abd 1660 intel_sanitize_gt_powersave(dev_priv);
1f814dac 1661
97d6d7ab 1662 ret = i915_ggtt_enable_hw(dev_priv);
ac840ae5
VS		 1663 if (ret)
1664 DRM_ERROR("failed to re-enable GGTT\n");
1665
f74ed08d
ID		 1666 intel_csr_ucode_resume(dev_priv);
1667
bf9e8429 1668 i915_gem_resume(dev_priv);
9d49c0ef 1669
af6dc742 1670 i915_restore_state(dev_priv);
8090ba8c 1671 intel_pps_unlock_regs_wa(dev_priv);
6f9f4b7a 1672 intel_opregion_setup(dev_priv);
61caf87c 1673
c39055b0 1674 intel_init_pch_refclk(dev_priv);
1833b134 1675
364aece0
PA		 1676 /*
1677 * Interrupts have to be enabled before any batches are run. If not the
1678 * GPU will hang. i915_gem_init_hw() will initiate batches to
1679 * update/restore the context.
1680 *
908764f6
ID		 1681 * drm_mode_config_reset() needs AUX interrupts.
1682 *
364aece0
PA		 1683 * Modeset enabling in intel_modeset_init_hw() also needs working
1684 * interrupts.
1685 */
1686 intel_runtime_pm_enable_interrupts(dev_priv);
1687
908764f6
ID		 1688 drm_mode_config_reset(dev);
1689
d5818938 1690 mutex_lock(&dev->struct_mutex);
bf9e8429 1691 if (i915_gem_init_hw(dev_priv)) {
d5818938 1692 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
821ed7df 1693 i915_gem_set_wedged(dev_priv);
d5818938
DV		 1694 }
1695 mutex_unlock(&dev->struct_mutex);
226485e9 1696
bf9e8429 1697 intel_guc_resume(dev_priv);
a1c41994 1698
d5818938 1699 intel_modeset_init_hw(dev);
24576d23 1700
d5818938
DV		 1701 spin_lock_irq(&dev_priv->irq_lock);
1702 if (dev_priv->display.hpd_irq_setup)
91d14251 1703 dev_priv->display.hpd_irq_setup(dev_priv);
d5818938 1704 spin_unlock_irq(&dev_priv->irq_lock);
0e32b39c 1705
d5818938 1706 intel_dp_mst_resume(dev);
e7d6f7d7 1707
a16b7658
L		 1708 intel_display_resume(dev);
1709
e0b70061
L		 1710 drm_kms_helper_poll_enable(dev);
1711
d5818938
DV		 1712 /*
1713 * ... but also need to make sure that hotplug processing
1714 * doesn't cause havoc. Like in the driver load code we don't
1715 * bother with the tiny race here where we might loose hotplug
1716 * notifications.
1717 * */
1718 intel_hpd_init(dev_priv);
1daed3fb 1719
03d92e47 1720 intel_opregion_register(dev_priv);
44834a67 1721
82e3b8c1 1722 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
073f34d9 1723
b8efb17b
ZR		 1724 mutex_lock(&dev_priv->modeset_restore_lock);
1725 dev_priv->modeset_restore = MODESET_DONE;
1726 mutex_unlock(&dev_priv->modeset_restore_lock);
8a187455 1727
6f9f4b7a 1728 intel_opregion_notify_adapter(dev_priv, PCI_D0);
e5747e3a 1729
54b4f68f 1730 intel_autoenable_gt_powersave(dev_priv);
ee6f280e 1731
1f814dac
ID		 1732 enable_rpm_wakeref_asserts(dev_priv);
1733
074c6ada 1734 return 0;
84b79f8d
RW		 1735}
1736
5e365c39 1737static int i915_drm_resume_early(struct drm_device *dev)
84b79f8d 1738{
fac5e23e 1739 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 1740 struct pci_dev *pdev = dev_priv->drm.pdev;
44410cd0 1741 int ret;
36d61e67 1742
76c4b250
ID		 1743 /*
1744 * We have a resume ordering issue with the snd-hda driver also
1745 * requiring our device to be power up. Due to the lack of a
1746 * parent/child relationship we currently solve this with an early
1747 * resume hook.
1748 *
1749 * FIXME: This should be solved with a special hdmi sink device or
1750 * similar so that power domains can be employed.
1751 */
44410cd0
ID		 1752
1753 /*
1754 * Note that we need to set the power state explicitly, since we
1755 * powered off the device during freeze and the PCI core won't power
1756 * it back up for us during thaw. Powering off the device during
1757 * freeze is not a hard requirement though, and during the
1758 * suspend/resume phases the PCI core makes sure we get here with the
1759 * device powered on. So in case we change our freeze logic and keep
1760 * the device powered we can also remove the following set power state
1761 * call.
1762 */
52a05c30 1763 ret = pci_set_power_state(pdev, PCI_D0);
44410cd0
ID		 1764 if (ret) {
1765 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1766 goto out;
1767 }
1768
1769 /*
1770 * Note that pci_enable_device() first enables any parent bridge
1771 * device and only then sets the power state for this device. The
1772 * bridge enabling is a nop though, since bridge devices are resumed
1773 * first. The order of enabling power and enabling the device is
1774 * imposed by the PCI core as described above, so here we preserve the
1775 * same order for the freeze/thaw phases.
1776 *
1777 * TODO: eventually we should remove pci_disable_device() /
1778 * pci_enable_enable_device() from suspend/resume. Due to how they
1779 * depend on the device enable refcount we can't anyway depend on them
1780 * disabling/enabling the device.
1781 */
52a05c30 1782 if (pci_enable_device(pdev)) {
bc87229f
ID		 1783 ret = -EIO;
1784 goto out;
1785 }
84b79f8d 1786
52a05c30 1787 pci_set_master(pdev);
84b79f8d 1788
1f814dac
ID		 1789 disable_rpm_wakeref_asserts(dev_priv);
1790
666a4537 1791 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1a5df187 1792 ret = vlv_resume_prepare(dev_priv, false);
36d61e67 1793 if (ret)
ff0b187f
DL		 1794 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1795 ret);
36d61e67 1796
68f60946 1797 intel_uncore_resume_early(dev_priv);
efee833a 1798
b9fd799e 1799 if (IS_GEN9_LP(dev_priv)) {
da2f41d1
ID		 1800 if (!dev_priv->suspended_to_idle)
1801 gen9_sanitize_dc_state(dev_priv);
507e126e 1802 bxt_disable_dc9(dev_priv);
da2f41d1 1803 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
a9a6b73a 1804 hsw_disable_pc8(dev_priv);
da2f41d1 1805 }
efee833a 1806
dc97997a 1807 intel_uncore_sanitize(dev_priv);
bc87229f 1808
b9fd799e 1809 if (IS_GEN9_LP(dev_priv) ||
a7c8125f 1810 !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
bc87229f
ID		 1811 intel_power_domains_init_hw(dev_priv, true);
1812
24145517
CW		 1813 i915_gem_sanitize(dev_priv);
1814
6e35e8ab
ID		 1815 enable_rpm_wakeref_asserts(dev_priv);
1816
bc87229f
ID		 1817out:
1818 dev_priv->suspended_to_idle = false;
36d61e67
ID		 1819
1820 return ret;
76c4b250
ID		 1821}
1822
7f26cb88 1823static int i915_resume_switcheroo(struct drm_device *dev)
76c4b250 1824{
50a0072f 1825 int ret;
76c4b250 1826
097dd837
ID		 1827 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1828 return 0;
1829
5e365c39 1830 ret = i915_drm_resume_early(dev);
50a0072f
ID		 1831 if (ret)
1832 return ret;
1833
5a17514e
ID		 1834 return i915_drm_resume(dev);
1835}
1836
11ed50ec 1837/**
f3953dcb 1838 * i915_reset - reset chip after a hang
df210574 1839 * @dev_priv: device private to reset
11ed50ec 1840 *
780f262a
CW		 1841 * Reset the chip. Useful if a hang is detected. Marks the device as wedged
1842 * on failure.
11ed50ec 1843 *
221fe799
CW		 1844 * Caller must hold the struct_mutex.
1845 *
11ed50ec
BG		 1846 * Procedure is fairly simple:
1847 * - reset the chip using the reset reg
1848 * - re-init context state
1849 * - re-init hardware status page
1850 * - re-init ring buffer
1851 * - re-init interrupt state
1852 * - re-init display
1853 */
780f262a 1854void i915_reset(struct drm_i915_private *dev_priv)
11ed50ec 1855{
d98c52cf 1856 struct i915_gpu_error *error = &dev_priv->gpu_error;
0573ed4a 1857 int ret;
11ed50ec 1858
bf9e8429 1859 lockdep_assert_held(&dev_priv->drm.struct_mutex);
8c185eca 1860 GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
221fe799 1861
8c185eca 1862 if (!test_bit(I915_RESET_HANDOFF, &error->flags))
780f262a 1863 return;
11ed50ec 1864
d98c52cf 1865 /* Clear any previous failed attempts at recovery. Time to try again. */
2e8f9d32
CW		 1866 if (!i915_gem_unset_wedged(dev_priv))
1867 goto wakeup;
1868
8af29b0c 1869 error->reset_count++;
d98c52cf 1870
7b4d3a16 1871 pr_notice("drm/i915: Resetting chip after gpu hang\n");
4c965543 1872 disable_irq(dev_priv->drm.irq);
0e178aef
CW		 1873 ret = i915_gem_reset_prepare(dev_priv);
1874 if (ret) {
1875 DRM_ERROR("GPU recovery failed\n");
1876 intel_gpu_reset(dev_priv, ALL_ENGINES);
1877 goto error;
1878 }
9e60ab03 1879
dc97997a 1880 ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
0573ed4a 1881 if (ret) {
804e59a8
CW		 1882 if (ret != -ENODEV)
1883 DRM_ERROR("Failed to reset chip: %i\n", ret);
1884 else
1885 DRM_DEBUG_DRIVER("GPU reset disabled\n");
d98c52cf 1886 goto error;
11ed50ec
BG		 1887 }
1888
d8027093 1889 i915_gem_reset(dev_priv);
1362b776
VS		 1890 intel_overlay_reset(dev_priv);
1891
11ed50ec
BG		 1892 /* Ok, now get things going again... */
1893
1894 /*
1895 * Everything depends on having the GTT running, so we need to start
1896 * there. Fortunately we don't need to do this unless we reset the
1897 * chip at a PCI level.
1898 *
1899 * Next we need to restore the context, but we don't use those
1900 * yet either...
1901 *
1902 * Ring buffer needs to be re-initialized in the KMS case, or if X
1903 * was running at the time of the reset (i.e. we weren't VT
1904 * switched away).
1905 */
bf9e8429 1906 ret = i915_gem_init_hw(dev_priv);
33d30a9c
DV		 1907 if (ret) {
1908 DRM_ERROR("Failed hw init on reset %d\n", ret);
d98c52cf 1909 goto error;
11ed50ec
BG		 1910 }
1911
c2a126a4
CW		 1912 i915_queue_hangcheck(dev_priv);
1913
2e8f9d32 1914finish:
8d613c53 1915 i915_gem_reset_finish(dev_priv);
4c965543 1916 enable_irq(dev_priv->drm.irq);
8c185eca 1917
2e8f9d32 1918wakeup:
8c185eca
CW		 1919 clear_bit(I915_RESET_HANDOFF, &error->flags);
1920 wake_up_bit(&error->flags, I915_RESET_HANDOFF);
780f262a 1921 return;
d98c52cf
CW		 1922
1923error:
821ed7df 1924 i915_gem_set_wedged(dev_priv);
36703e79 1925 i915_gem_retire_requests(dev_priv);
2e8f9d32 1926 goto finish;
11ed50ec
BG		 1927}
1928
142bc7d9
MT		 1929/**
1930 * i915_reset_engine - reset GPU engine to recover from a hang
1931 * @engine: engine to reset
1932 *
1933 * Reset a specific GPU engine. Useful if a hang is detected.
1934 * Returns zero on successful reset or otherwise an error code.
a1ef70e1
MT		 1935 *
1936 * Procedure is:
1937 * - identifies the request that caused the hang and it is dropped
1938 * - reset engine (which will force the engine to idle)
1939 * - re-init/configure engine
142bc7d9
MT		 1940 */
1941int i915_reset_engine(struct intel_engine_cs *engine)
1942{
a1ef70e1
MT		 1943 struct i915_gpu_error *error = &engine->i915->gpu_error;
1944 struct drm_i915_gem_request *active_request;
1945 int ret;
1946
1947 GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));
1948
1949 DRM_DEBUG_DRIVER("resetting %s\n", engine->name);
1950
1951 active_request = i915_gem_reset_prepare_engine(engine);
1952 if (IS_ERR(active_request)) {
1953 DRM_DEBUG_DRIVER("Previous reset failed, promote to full reset\n");
1954 ret = PTR_ERR(active_request);
1955 goto out;
1956 }
1957
1958 /*
1959 * The request that caused the hang is stuck on elsp, we know the
1960 * active request and can drop it, adjust head to skip the offending
1961 * request to resume executing remaining requests in the queue.
1962 */
1963 i915_gem_reset_engine(engine, active_request);
1964
1965 /* Finally, reset just this engine. */
1966 ret = intel_gpu_reset(engine->i915, intel_engine_flag(engine));
1967
1968 i915_gem_reset_finish_engine(engine);
1969
1970 if (ret) {
1971 /* If we fail here, we expect to fallback to a global reset */
1972 DRM_DEBUG_DRIVER("Failed to reset %s, ret=%d\n",
1973 engine->name, ret);
1974 goto out;
1975 }
1976
1977 /*
1978 * The engine and its registers (and workarounds in case of render)
1979 * have been reset to their default values. Follow the init_ring
1980 * process to program RING_MODE, HWSP and re-enable submission.
1981 */
1982 ret = engine->init_hw(engine);
702c8f8e
MT		 1983 if (ret)
1984 goto out;
a1ef70e1 1985
702c8f8e 1986 error->reset_engine_count[engine->id]++;
a1ef70e1
MT		 1987out:
1988 return ret;
142bc7d9
MT		 1989}
1990
c49d13ee 1991static int i915_pm_suspend(struct device *kdev)
112b715e 1992{
c49d13ee
DW		 1993 struct pci_dev *pdev = to_pci_dev(kdev);
1994 struct drm_device *dev = pci_get_drvdata(pdev);
112b715e 1995
c49d13ee
DW		 1996 if (!dev) {
1997 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
84b79f8d
RW		 1998 return -ENODEV;
1999 }
112b715e 2000
c49d13ee 2001 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
5bcf719b
DA		 2002 return 0;
2003
c49d13ee 2004 return i915_drm_suspend(dev);
76c4b250
ID		 2005}
2006
c49d13ee 2007static int i915_pm_suspend_late(struct device *kdev)
76c4b250 2008{
c49d13ee 2009 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
76c4b250
ID		 2010
2011 /*
c965d995 2012 * We have a suspend ordering issue with the snd-hda driver also
76c4b250
ID		 2013 * requiring our device to be power up. Due to the lack of a
2014 * parent/child relationship we currently solve this with an late
2015 * suspend hook.
2016 *
2017 * FIXME: This should be solved with a special hdmi sink device or
2018 * similar so that power domains can be employed.
2019 */
c49d13ee 2020 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
76c4b250 2021 return 0;
112b715e 2022
c49d13ee 2023 return i915_drm_suspend_late(dev, false);
ab3be73f
ID		 2024}
2025
c49d13ee 2026static int i915_pm_poweroff_late(struct device *kdev)
ab3be73f 2027{
c49d13ee 2028 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
ab3be73f 2029
c49d13ee 2030 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
ab3be73f
ID		 2031 return 0;
2032
c49d13ee 2033 return i915_drm_suspend_late(dev, true);
cbda12d7
ZW		 2034}
2035
c49d13ee 2036static int i915_pm_resume_early(struct device *kdev)
76c4b250 2037{
c49d13ee 2038 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
76c4b250 2039
c49d13ee 2040 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
097dd837
ID		 2041 return 0;
2042
c49d13ee 2043 return i915_drm_resume_early(dev);
76c4b250
ID		 2044}
2045
c49d13ee 2046static int i915_pm_resume(struct device *kdev)
cbda12d7 2047{
c49d13ee 2048 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
84b79f8d 2049
c49d13ee 2050 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
097dd837
ID		 2051 return 0;
2052
c49d13ee 2053 return i915_drm_resume(dev);
cbda12d7
ZW		 2054}
2055
1f19ac2a 2056/* freeze: before creating the hibernation_image */
c49d13ee 2057static int i915_pm_freeze(struct device *kdev)
1f19ac2a 2058{
6a800eab
CW		 2059 int ret;
2060
2061 ret = i915_pm_suspend(kdev);
2062 if (ret)
2063 return ret;
2064
2065 ret = i915_gem_freeze(kdev_to_i915(kdev));
2066 if (ret)
2067 return ret;
2068
2069 return 0;
1f19ac2a
CW		 2070}
2071
c49d13ee 2072static int i915_pm_freeze_late(struct device *kdev)
1f19ac2a 2073{
461fb99c
CW		 2074 int ret;
2075
c49d13ee 2076 ret = i915_pm_suspend_late(kdev);
461fb99c
CW		 2077 if (ret)
2078 return ret;
2079
c49d13ee 2080 ret = i915_gem_freeze_late(kdev_to_i915(kdev));
461fb99c
CW		 2081 if (ret)
2082 return ret;
2083
2084 return 0;
1f19ac2a
CW		 2085}
2086
2087/* thaw: called after creating the hibernation image, but before turning off. */
c49d13ee 2088static int i915_pm_thaw_early(struct device *kdev)
1f19ac2a 2089{
c49d13ee 2090 return i915_pm_resume_early(kdev);
1f19ac2a
CW		 2091}
2092
c49d13ee 2093static int i915_pm_thaw(struct device *kdev)
1f19ac2a 2094{
c49d13ee 2095 return i915_pm_resume(kdev);
1f19ac2a
CW		 2096}
2097
2098/* restore: called after loading the hibernation image. */
c49d13ee 2099static int i915_pm_restore_early(struct device *kdev)
1f19ac2a 2100{
c49d13ee 2101 return i915_pm_resume_early(kdev);
1f19ac2a
CW		 2102}
2103
c49d13ee 2104static int i915_pm_restore(struct device *kdev)
1f19ac2a 2105{
c49d13ee 2106 return i915_pm_resume(kdev);
1f19ac2a
CW		 2107}
2108
ddeea5b0
ID		 2109/*
2110 * Save all Gunit registers that may be lost after a D3 and a subsequent
2111 * S0i[R123] transition. The list of registers needing a save/restore is
2112 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2113 * registers in the following way:
2114 * - Driver: saved/restored by the driver
2115 * - Punit : saved/restored by the Punit firmware
2116 * - No, w/o marking: no need to save/restore, since the register is R/O or
2117 * used internally by the HW in a way that doesn't depend
2118 * keeping the content across a suspend/resume.
2119 * - Debug : used for debugging
2120 *
2121 * We save/restore all registers marked with 'Driver', with the following
2122 * exceptions:
2123 * - Registers out of use, including also registers marked with 'Debug'.
2124 * These have no effect on the driver's operation, so we don't save/restore
2125 * them to reduce the overhead.
2126 * - Registers that are fully setup by an initialization function called from
2127 * the resume path. For example many clock gating and RPS/RC6 registers.
2128 * - Registers that provide the right functionality with their reset defaults.
2129 *
2130 * TODO: Except for registers that based on the above 3 criteria can be safely
2131 * ignored, we save/restore all others, practically treating the HW context as
2132 * a black-box for the driver. Further investigation is needed to reduce the
2133 * saved/restored registers even further, by following the same 3 criteria.
2134 */
2135static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2136{
2137 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2138 int i;
2139
2140 /* GAM 0x4000-0x4770 */
2141 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
2142 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
2143 s->arb_mode = I915_READ(ARB_MODE);
2144 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
2145 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
2146
2147 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
22dfe79f 2148 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
ddeea5b0
ID		 2149
2150 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
b5f1c97f 2151 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
ddeea5b0
ID		 2152
2153 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
2154 s->ecochk = I915_READ(GAM_ECOCHK);
2155 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
2156 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
2157
2158 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
2159
2160 /* MBC 0x9024-0x91D0, 0x8500 */
2161 s->g3dctl = I915_READ(VLV_G3DCTL);
2162 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
2163 s->mbctl = I915_READ(GEN6_MBCTL);
2164
2165 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2166 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
2167 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
2168 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
2169 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
2170 s->rstctl = I915_READ(GEN6_RSTCTL);
2171 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
2172
2173 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2174 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
2175 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
2176 s->rpdeuc = I915_READ(GEN6_RPDEUC);
2177 s->ecobus = I915_READ(ECOBUS);
2178 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
2179 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2180 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
2181 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
2182 s->rcedata = I915_READ(VLV_RCEDATA);
2183 s->spare2gh = I915_READ(VLV_SPAREG2H);
2184
2185 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2186 s->gt_imr = I915_READ(GTIMR);
2187 s->gt_ier = I915_READ(GTIER);
2188 s->pm_imr = I915_READ(GEN6_PMIMR);
2189 s->pm_ier = I915_READ(GEN6_PMIER);
2190
2191 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
22dfe79f 2192 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
ddeea5b0
ID		 2193
2194 /* GT SA CZ domain, 0x100000-0x138124 */
2195 s->tilectl = I915_READ(TILECTL);
2196 s->gt_fifoctl = I915_READ(GTFIFOCTL);
2197 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
2198 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2199 s->pmwgicz = I915_READ(VLV_PMWGICZ);
2200
2201 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2202 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
2203 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
9c25210f 2204 s->pcbr = I915_READ(VLV_PCBR);
ddeea5b0
ID		 2205 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2206
2207 /*
2208 * Not saving any of:
2209 * DFT, 0x9800-0x9EC0
2210 * SARB, 0xB000-0xB1FC
2211 * GAC, 0x5208-0x524C, 0x14000-0x14C000
2212 * PCI CFG
2213 */
2214}
2215
2216static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2217{
2218 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2219 u32 val;
2220 int i;
2221
2222 /* GAM 0x4000-0x4770 */
2223 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
2224 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
2225 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
2226 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
2227 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
2228
2229 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
22dfe79f 2230 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
ddeea5b0
ID		 2231
2232 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
b5f1c97f 2233 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
ddeea5b0
ID		 2234
2235 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2236 I915_WRITE(GAM_ECOCHK, s->ecochk);
2237 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
2238 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
2239
2240 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
2241
2242 /* MBC 0x9024-0x91D0, 0x8500 */
2243 I915_WRITE(VLV_G3DCTL, s->g3dctl);
2244 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
2245 I915_WRITE(GEN6_MBCTL, s->mbctl);
2246
2247 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2248 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
2249 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
2250 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
2251 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
2252 I915_WRITE(GEN6_RSTCTL, s->rstctl);
2253 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
2254
2255 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2256 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
2257 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
2258 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
2259 I915_WRITE(ECOBUS, s->ecobus);
2260 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
2261 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2262 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
2263 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
2264 I915_WRITE(VLV_RCEDATA, s->rcedata);
2265 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
2266
2267 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2268 I915_WRITE(GTIMR, s->gt_imr);
2269 I915_WRITE(GTIER, s->gt_ier);
2270 I915_WRITE(GEN6_PMIMR, s->pm_imr);
2271 I915_WRITE(GEN6_PMIER, s->pm_ier);
2272
2273 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
22dfe79f 2274 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
ddeea5b0
ID		 2275
2276 /* GT SA CZ domain, 0x100000-0x138124 */
2277 I915_WRITE(TILECTL, s->tilectl);
2278 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
2279 /*
2280 * Preserve the GT allow wake and GFX force clock bit, they are not
2281 * be restored, as they are used to control the s0ix suspend/resume
2282 * sequence by the caller.
2283 */
2284 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2285 val &= VLV_GTLC_ALLOWWAKEREQ;
2286 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2287 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2288
2289 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2290 val &= VLV_GFX_CLK_FORCE_ON_BIT;
2291 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2292 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2293
2294 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
2295
2296 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2297 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
2298 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
9c25210f 2299 I915_WRITE(VLV_PCBR, s->pcbr);
ddeea5b0
ID		 2300 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
2301}
2302
3dd14c04
CW		 2303static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2304 u32 mask, u32 val)
2305{
2306 /* The HW does not like us polling for PW_STATUS frequently, so
2307 * use the sleeping loop rather than risk the busy spin within
2308 * intel_wait_for_register().
2309 *
2310 * Transitioning between RC6 states should be at most 2ms (see
2311 * valleyview_enable_rps) so use a 3ms timeout.
2312 */
2313 return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val,
2314 3);
2315}
2316
650ad970
ID		 2317int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2318{
2319 u32 val;
2320 int err;
2321
650ad970
ID		 2322 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2323 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2324 if (force_on)
2325 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2326 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2327
2328 if (!force_on)
2329 return 0;
2330
c6ddc5f3
CW		 2331 err = intel_wait_for_register(dev_priv,
2332 VLV_GTLC_SURVIVABILITY_REG,
2333 VLV_GFX_CLK_STATUS_BIT,
2334 VLV_GFX_CLK_STATUS_BIT,
2335 20);
650ad970
ID		 2336 if (err)
2337 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2338 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2339
2340 return err;
650ad970
ID		 2341}
2342
ddeea5b0
ID		 2343static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2344{
3dd14c04 2345 u32 mask;
ddeea5b0 2346 u32 val;
3dd14c04 2347 int err;
ddeea5b0
ID		 2348
2349 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2350 val &= ~VLV_GTLC_ALLOWWAKEREQ;
2351 if (allow)
2352 val |= VLV_GTLC_ALLOWWAKEREQ;
2353 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2354 POSTING_READ(VLV_GTLC_WAKE_CTRL);
2355
3dd14c04
CW		 2356 mask = VLV_GTLC_ALLOWWAKEACK;
2357 val = allow ? mask : 0;
2358
2359 err = vlv_wait_for_pw_status(dev_priv, mask, val);
ddeea5b0
ID		 2360 if (err)
2361 DRM_ERROR("timeout disabling GT waking\n");
b2736695 2362
ddeea5b0 2363 return err;
ddeea5b0
ID		 2364}
2365
3dd14c04
CW		 2366static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2367 bool wait_for_on)
ddeea5b0
ID		 2368{
2369 u32 mask;
2370 u32 val;
ddeea5b0
ID		 2371
2372 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2373 val = wait_for_on ? mask : 0;
ddeea5b0
ID		 2374
2375 /*
2376 * RC6 transitioning can be delayed up to 2 msec (see
2377 * valleyview_enable_rps), use 3 msec for safety.
2378 */
3dd14c04 2379 if (vlv_wait_for_pw_status(dev_priv, mask, val))
ddeea5b0 2380 DRM_ERROR("timeout waiting for GT wells to go %s\n",
87ad3212 2381 onoff(wait_for_on));
ddeea5b0
ID		 2382}
2383
2384static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2385{
2386 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2387 return;
2388
6fa283b0 2389 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
ddeea5b0
ID		 2390 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2391}
2392
ebc32824 2393static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
ddeea5b0
ID		 2394{
2395 u32 mask;
2396 int err;
2397
2398 /*
2399 * Bspec defines the following GT well on flags as debug only, so
2400 * don't treat them as hard failures.
2401 */
3dd14c04 2402 vlv_wait_for_gt_wells(dev_priv, false);
ddeea5b0
ID		 2403
2404 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2405 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2406
2407 vlv_check_no_gt_access(dev_priv);
2408
2409 err = vlv_force_gfx_clock(dev_priv, true);
2410 if (err)
2411 goto err1;
2412
2413 err = vlv_allow_gt_wake(dev_priv, false);
2414 if (err)
2415 goto err2;
98711167 2416
2d1fe073 2417 if (!IS_CHERRYVIEW(dev_priv))
98711167 2418 vlv_save_gunit_s0ix_state(dev_priv);
ddeea5b0
ID		 2419
2420 err = vlv_force_gfx_clock(dev_priv, false);
2421 if (err)
2422 goto err2;
2423
2424 return 0;
2425
2426err2:
2427 /* For safety always re-enable waking and disable gfx clock forcing */
2428 vlv_allow_gt_wake(dev_priv, true);
2429err1:
2430 vlv_force_gfx_clock(dev_priv, false);
2431
2432 return err;
2433}
2434
016970be
SK		 2435static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2436 bool rpm_resume)
ddeea5b0 2437{
ddeea5b0
ID		 2438 int err;
2439 int ret;
2440
2441 /*
2442 * If any of the steps fail just try to continue, that's the best we
2443 * can do at this point. Return the first error code (which will also
2444 * leave RPM permanently disabled).
2445 */
2446 ret = vlv_force_gfx_clock(dev_priv, true);
2447
2d1fe073 2448 if (!IS_CHERRYVIEW(dev_priv))
98711167 2449 vlv_restore_gunit_s0ix_state(dev_priv);
ddeea5b0
ID		 2450
2451 err = vlv_allow_gt_wake(dev_priv, true);
2452 if (!ret)
2453 ret = err;
2454
2455 err = vlv_force_gfx_clock(dev_priv, false);
2456 if (!ret)
2457 ret = err;
2458
2459 vlv_check_no_gt_access(dev_priv);
2460
7c108fd8 2461 if (rpm_resume)
46f16e63 2462 intel_init_clock_gating(dev_priv);
ddeea5b0
ID		 2463
2464 return ret;
2465}
2466
c49d13ee 2467static int intel_runtime_suspend(struct device *kdev)
8a187455 2468{
c49d13ee 2469 struct pci_dev *pdev = to_pci_dev(kdev);
8a187455 2470 struct drm_device *dev = pci_get_drvdata(pdev);
fac5e23e 2471 struct drm_i915_private *dev_priv = to_i915(dev);
0ab9cfeb 2472 int ret;
8a187455 2473
dc97997a 2474 if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
c6df39b5
ID		 2475 return -ENODEV;
2476
6772ffe0 2477 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
604effb7
ID		 2478 return -ENODEV;
2479
8a187455
PZ		 2480 DRM_DEBUG_KMS("Suspending device\n");
2481
1f814dac
ID		 2482 disable_rpm_wakeref_asserts(dev_priv);
2483
d6102977
ID		 2484 /*
2485 * We are safe here against re-faults, since the fault handler takes
2486 * an RPM reference.
2487 */
7c108fd8 2488 i915_gem_runtime_suspend(dev_priv);
d6102977 2489
bf9e8429 2490 intel_guc_suspend(dev_priv);
a1c41994 2491
2eb5252e 2492 intel_runtime_pm_disable_interrupts(dev_priv);
b5478bcd 2493
507e126e 2494 ret = 0;
b9fd799e 2495 if (IS_GEN9_LP(dev_priv)) {
507e126e
ID		 2496 bxt_display_core_uninit(dev_priv);
2497 bxt_enable_dc9(dev_priv);
2498 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2499 hsw_enable_pc8(dev_priv);
2500 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2501 ret = vlv_suspend_complete(dev_priv);
2502 }
2503
0ab9cfeb
ID		 2504 if (ret) {
2505 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
b963291c 2506 intel_runtime_pm_enable_interrupts(dev_priv);
0ab9cfeb 2507
1f814dac
ID		 2508 enable_rpm_wakeref_asserts(dev_priv);
2509
0ab9cfeb
ID		 2510 return ret;
2511 }
a8a8bd54 2512
68f60946 2513 intel_uncore_suspend(dev_priv);
1f814dac
ID		 2514
2515 enable_rpm_wakeref_asserts(dev_priv);
2516 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
55ec45c2 2517
bc3b9346 2518 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
55ec45c2
MK		 2519 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2520
8a187455 2521 dev_priv->pm.suspended = true;
1fb2362b
KCA		 2522
2523 /*
c8a0bd42
PZ		 2524 * FIXME: We really should find a document that references the arguments
2525 * used below!
1fb2362b 2526 */
6f9f4b7a 2527 if (IS_BROADWELL(dev_priv)) {
d37ae19a
PZ		 2528 /*
2529 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2530 * being detected, and the call we do at intel_runtime_resume()
2531 * won't be able to restore them. Since PCI_D3hot matches the
2532 * actual specification and appears to be working, use it.
2533 */
6f9f4b7a 2534 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
d37ae19a 2535 } else {
c8a0bd42
PZ		 2536 /*
2537 * current versions of firmware which depend on this opregion
2538 * notification have repurposed the D1 definition to mean
2539 * "runtime suspended" vs. what you would normally expect (D3)
2540 * to distinguish it from notifications that might be sent via
2541 * the suspend path.
2542 */
6f9f4b7a 2543 intel_opregion_notify_adapter(dev_priv, PCI_D1);
c8a0bd42 2544 }
8a187455 2545
59bad947 2546 assert_forcewakes_inactive(dev_priv);
dc9fb09c 2547
21d6e0bd 2548 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
19625e85
L		 2549 intel_hpd_poll_init(dev_priv);
2550
a8a8bd54 2551 DRM_DEBUG_KMS("Device suspended\n");
8a187455
PZ		 2552 return 0;
2553}
2554
c49d13ee 2555static int intel_runtime_resume(struct device *kdev)
8a187455 2556{
c49d13ee 2557 struct pci_dev *pdev = to_pci_dev(kdev);
8a187455 2558 struct drm_device *dev = pci_get_drvdata(pdev);
fac5e23e 2559 struct drm_i915_private *dev_priv = to_i915(dev);
1a5df187 2560 int ret = 0;
8a187455 2561
6772ffe0 2562 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
604effb7 2563 return -ENODEV;
8a187455
PZ		 2564
2565 DRM_DEBUG_KMS("Resuming device\n");
2566
1f814dac
ID		 2567 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2568 disable_rpm_wakeref_asserts(dev_priv);
2569
6f9f4b7a 2570 intel_opregion_notify_adapter(dev_priv, PCI_D0);
8a187455 2571 dev_priv->pm.suspended = false;
55ec45c2
MK		 2572 if (intel_uncore_unclaimed_mmio(dev_priv))
2573 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
8a187455 2574
bf9e8429 2575 intel_guc_resume(dev_priv);
a1c41994 2576
b9fd799e 2577 if (IS_GEN9_LP(dev_priv)) {
507e126e
ID		 2578 bxt_disable_dc9(dev_priv);
2579 bxt_display_core_init(dev_priv, true);
f62c79b3
ID		 2580 if (dev_priv->csr.dmc_payload &&
2581 (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2582 gen9_enable_dc5(dev_priv);
507e126e 2583 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1a5df187 2584 hsw_disable_pc8(dev_priv);
507e126e 2585 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1a5df187 2586 ret = vlv_resume_prepare(dev_priv, true);
507e126e 2587 }
1a5df187 2588
0ab9cfeb
ID		 2589 /*
2590 * No point of rolling back things in case of an error, as the best
2591 * we can do is to hope that things will still work (and disable RPM).
2592 */
c6be607a 2593 i915_gem_init_swizzling(dev_priv);
83bf6d55 2594 i915_gem_restore_fences(dev_priv);
92b806d3 2595
b963291c 2596 intel_runtime_pm_enable_interrupts(dev_priv);
08d8a232
VS		 2597
2598 /*
2599 * On VLV/CHV display interrupts are part of the display
2600 * power well, so hpd is reinitialized from there. For
2601 * everyone else do it here.
2602 */
666a4537 2603 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
08d8a232
VS		 2604 intel_hpd_init(dev_priv);
2605
1f814dac
ID		 2606 enable_rpm_wakeref_asserts(dev_priv);
2607
0ab9cfeb
ID		 2608 if (ret)
2609 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2610 else
2611 DRM_DEBUG_KMS("Device resumed\n");
2612
2613 return ret;
8a187455
PZ		 2614}
2615
42f5551d 2616const struct dev_pm_ops i915_pm_ops = {
5545dbbf
ID		 2617 /*
2618 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2619 * PMSG_RESUME]
2620 */
0206e353 2621 .suspend = i915_pm_suspend,
76c4b250
ID		 2622 .suspend_late = i915_pm_suspend_late,
2623 .resume_early = i915_pm_resume_early,
0206e353 2624 .resume = i915_pm_resume,
5545dbbf
ID		 2625
2626 /*
2627 * S4 event handlers
2628 * @freeze, @freeze_late : called (1) before creating the
2629 * hibernation image [PMSG_FREEZE] and
2630 * (2) after rebooting, before restoring
2631 * the image [PMSG_QUIESCE]
2632 * @thaw, @thaw_early : called (1) after creating the hibernation
2633 * image, before writing it [PMSG_THAW]
2634 * and (2) after failing to create or
2635 * restore the image [PMSG_RECOVER]
2636 * @poweroff, @poweroff_late: called after writing the hibernation
2637 * image, before rebooting [PMSG_HIBERNATE]
2638 * @restore, @restore_early : called after rebooting and restoring the
2639 * hibernation image [PMSG_RESTORE]
2640 */
1f19ac2a
CW		 2641 .freeze = i915_pm_freeze,
2642 .freeze_late = i915_pm_freeze_late,
2643 .thaw_early = i915_pm_thaw_early,
2644 .thaw = i915_pm_thaw,
36d61e67 2645 .poweroff = i915_pm_suspend,
ab3be73f 2646 .poweroff_late = i915_pm_poweroff_late,
1f19ac2a
CW		 2647 .restore_early = i915_pm_restore_early,
2648 .restore = i915_pm_restore,
5545dbbf
ID		 2649
2650 /* S0ix (via runtime suspend) event handlers */
97bea207
PZ		 2651 .runtime_suspend = intel_runtime_suspend,
2652 .runtime_resume = intel_runtime_resume,
cbda12d7
ZW		 2653};
2654
78b68556 2655static const struct vm_operations_struct i915_gem_vm_ops = {
de151cf6 2656 .fault = i915_gem_fault,
ab00b3e5
JB		 2657 .open = drm_gem_vm_open,
2658 .close = drm_gem_vm_close,
de151cf6
JB		 2659};
2660
e08e96de
AV		 2661static const struct file_operations i915_driver_fops = {
2662 .owner = THIS_MODULE,
2663 .open = drm_open,
2664 .release = drm_release,
2665 .unlocked_ioctl = drm_ioctl,
2666 .mmap = drm_gem_mmap,
2667 .poll = drm_poll,
e08e96de 2668 .read = drm_read,
e08e96de 2669 .compat_ioctl = i915_compat_ioctl,
e08e96de
AV		 2670 .llseek = noop_llseek,
2671};
2672
0673ad47
CW		 2673static int
2674i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2675 struct drm_file *file)
2676{
2677 return -ENODEV;
2678}
2679
2680static const struct drm_ioctl_desc i915_ioctls[] = {
2681 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2682 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2683 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2684 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2685 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2686 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2687 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2688 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2689 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2690 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2691 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2692 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2693 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2694 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2695 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
2696 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2697 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2698 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2699 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
fec0445c 2700 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
0673ad47
CW		 2701 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2702 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2703 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2704 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2705 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2706 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2707 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2708 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2709 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2710 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2711 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2712 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2713 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2714 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2715 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
111dbcab
CW		 2716 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2717 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
0673ad47
CW		 2718 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2719 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2720 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2721 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2722 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2723 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2724 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2725 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2726 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2727 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2728 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2729 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2730 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2731 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2732 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
eec688e1 2733 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
0673ad47
CW		 2734};
2735
1da177e4 2736static struct drm_driver driver = {
0c54781b
MW		 2737 /* Don't use MTRRs here; the Xserver or userspace app should
2738 * deal with them for Intel hardware.
792d2b9a 2739 */
673a394b 2740 .driver_features =
10ba5012 2741 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
8d2b47dd 2742 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC,
cad3688f 2743 .release = i915_driver_release,
673a394b 2744 .open = i915_driver_open,
22eae947 2745 .lastclose = i915_driver_lastclose,
673a394b 2746 .postclose = i915_driver_postclose,
915b4d11 2747 .set_busid = drm_pci_set_busid,
d8e29209 2748
b1f788c6 2749 .gem_close_object = i915_gem_close_object,
f0cd5182 2750 .gem_free_object_unlocked = i915_gem_free_object,
de151cf6 2751 .gem_vm_ops = &i915_gem_vm_ops,
1286ff73
DV		 2752
2753 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2754 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2755 .gem_prime_export = i915_gem_prime_export,
2756 .gem_prime_import = i915_gem_prime_import,
2757
ff72145b 2758 .dumb_create = i915_gem_dumb_create,
da6b51d0 2759 .dumb_map_offset = i915_gem_mmap_gtt,
43387b37 2760 .dumb_destroy = drm_gem_dumb_destroy,
1da177e4 2761 .ioctls = i915_ioctls,
0673ad47 2762 .num_ioctls = ARRAY_SIZE(i915_ioctls),
e08e96de 2763 .fops = &i915_driver_fops,
22eae947
DA		 2764 .name = DRIVER_NAME,
2765 .desc = DRIVER_DESC,
2766 .date = DRIVER_DATE,
2767 .major = DRIVER_MAJOR,
2768 .minor = DRIVER_MINOR,
2769 .patchlevel = DRIVER_PATCHLEVEL,
1da177e4 2770};
66d9cb5d
CW		 2771
2772#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2773#include "selftests/mock_drm.c"
2774#endif
Linux 6.x block layer and io_uring tree(s)