projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: fix PIPE_DDI_PORT_MASK
[linux-2.6-block.git] / drivers / gpu / drm / i915 / i915_drv.c
CommitLineData
1da177e4
LT		 1/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
0d6aa60b 3/*
bc54fd1a 4 *
1da177e4
LT		 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
bc54fd1a
DA		 7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
0d6aa60b 28 */
1da177e4 29
5669fcac 30#include <linux/device.h>
1da177e4
LT		 31#include "drmP.h"
32#include "drm.h"
33#include "i915_drm.h"
34#include "i915_drv.h"
990bbdad 35#include "i915_trace.h"
f49f0586 36#include "intel_drv.h"
1da177e4 37
79e53945 38#include <linux/console.h>
e0cd3608 39#include <linux/module.h>
354ff967 40#include "drm_crtc_helper.h"
79e53945 41
a35d9d3c 42static int i915_modeset __read_mostly = -1;
79e53945 43module_param_named(modeset, i915_modeset, int, 0400);
6e96e775
BW		 44MODULE_PARM_DESC(modeset,
45 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
46 "1=on, -1=force vga console preference [default])");
79e53945 47
a35d9d3c 48unsigned int i915_fbpercrtc __always_unused = 0;
79e53945 49module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
1da177e4 50
a35d9d3c 51int i915_panel_ignore_lid __read_mostly = 0;
fca87409 52module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
6e96e775
BW		 53MODULE_PARM_DESC(panel_ignore_lid,
54 "Override lid status (0=autodetect [default], 1=lid open, "
55 "-1=lid closed)");
fca87409 56
a35d9d3c 57unsigned int i915_powersave __read_mostly = 1;
0aa99277 58module_param_named(powersave, i915_powersave, int, 0600);
6e96e775
BW		 59MODULE_PARM_DESC(powersave,
60 "Enable powersavings, fbc, downclocking, etc. (default: true)");
652c393a 61
f45b5557 62int i915_semaphores __read_mostly = -1;
a1656b90 63module_param_named(semaphores, i915_semaphores, int, 0600);
6e96e775 64MODULE_PARM_DESC(semaphores,
f45b5557 65 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
a1656b90 66
c0f372b3 67int i915_enable_rc6 __read_mostly = -1;
f57f9c16 68module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
6e96e775 69MODULE_PARM_DESC(i915_enable_rc6,
83b7f9ac
ED		 70 "Enable power-saving render C-state 6. "
71 "Different stages can be selected via bitmask values "
72 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
73 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
74 "default: -1 (use per-chip default)");
ac668088 75
4415e63b 76int i915_enable_fbc __read_mostly = -1;
c1a9f047 77module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
6e96e775
BW		 78MODULE_PARM_DESC(i915_enable_fbc,
79 "Enable frame buffer compression for power savings "
cd0de039 80 "(default: -1 (use per-chip default))");
c1a9f047 81
a35d9d3c 82unsigned int i915_lvds_downclock __read_mostly = 0;
33814341 83module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
6e96e775
BW		 84MODULE_PARM_DESC(lvds_downclock,
85 "Use panel (LVDS/eDP) downclocking for power savings "
86 "(default: false)");
33814341 87
121d527a
TI		 88int i915_lvds_channel_mode __read_mostly;
89module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
90MODULE_PARM_DESC(lvds_channel_mode,
91 "Specify LVDS channel mode "
92 "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
93
4415e63b 94int i915_panel_use_ssc __read_mostly = -1;
a7615030 95module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
6e96e775
BW		 96MODULE_PARM_DESC(lvds_use_ssc,
97 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
72bbe58c 98 "(default: auto from VBT)");
a7615030 99
a35d9d3c 100int i915_vbt_sdvo_panel_type __read_mostly = -1;
5a1e5b6c 101module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
6e96e775 102MODULE_PARM_DESC(vbt_sdvo_panel_type,
c10e408a
MF		 103 "Override/Ignore selection of SDVO panel mode in the VBT "
104 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
5a1e5b6c 105
a35d9d3c 106static bool i915_try_reset __read_mostly = true;
d78cb50b 107module_param_named(reset, i915_try_reset, bool, 0600);
6e96e775 108MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
d78cb50b 109
a35d9d3c 110bool i915_enable_hangcheck __read_mostly = true;
3e0dc6b0 111module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
6e96e775
BW		 112MODULE_PARM_DESC(enable_hangcheck,
113 "Periodically check GPU activity for detecting hangs. "
114 "WARNING: Disabling this can cause system wide hangs. "
115 "(default: true)");
3e0dc6b0 116
650dc07e
DV		 117int i915_enable_ppgtt __read_mostly = -1;
118module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
e21af88d
DV		 119MODULE_PARM_DESC(i915_enable_ppgtt,
120 "Enable PPGTT (default: true)");
121
112b715e 122static struct drm_driver driver;
1f7a6e37 123extern int intel_agp_enabled;
112b715e 124
cfdf1fa2 125#define INTEL_VGA_DEVICE(id, info) { \
80a2901d 126 .class = PCI_BASE_CLASS_DISPLAY << 16, \
934f992c 127 .class_mask = 0xff0000, \
49ae35f2
KH		 128 .vendor = 0x8086, \
129 .device = id, \
130 .subvendor = PCI_ANY_ID, \
131 .subdevice = PCI_ANY_ID, \
cfdf1fa2
KH		 132 .driver_data = (unsigned long) info }
133
9a7e8492 134static const struct intel_device_info intel_i830_info = {
a6c45cf0 135 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
31578148 136 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2
KH		 137};
138
9a7e8492 139static const struct intel_device_info intel_845g_info = {
a6c45cf0 140 .gen = 2,
31578148 141 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2
KH		 142};
143
9a7e8492 144static const struct intel_device_info intel_i85x_info = {
a6c45cf0 145 .gen = 2, .is_i85x = 1, .is_mobile = 1,
5ce8ba7c 146 .cursor_needs_physical = 1,
31578148 147 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2
KH		 148};
149
9a7e8492 150static const struct intel_device_info intel_i865g_info = {
a6c45cf0 151 .gen = 2,
31578148 152 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2
KH		 153};
154
9a7e8492 155static const struct intel_device_info intel_i915g_info = {
a6c45cf0 156 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
31578148 157 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2 158};
9a7e8492 159static const struct intel_device_info intel_i915gm_info = {
a6c45cf0 160 .gen = 3, .is_mobile = 1,
b295d1b6 161 .cursor_needs_physical = 1,
31578148 162 .has_overlay = 1, .overlay_needs_physical = 1,
a6c45cf0 163 .supports_tv = 1,
cfdf1fa2 164};
9a7e8492 165static const struct intel_device_info intel_i945g_info = {
a6c45cf0 166 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
31578148 167 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2 168};
9a7e8492 169static const struct intel_device_info intel_i945gm_info = {
a6c45cf0 170 .gen = 3, .is_i945gm = 1, .is_mobile = 1,
b295d1b6 171 .has_hotplug = 1, .cursor_needs_physical = 1,
31578148 172 .has_overlay = 1, .overlay_needs_physical = 1,
a6c45cf0 173 .supports_tv = 1,
cfdf1fa2
KH		 174};
175
9a7e8492 176static const struct intel_device_info intel_i965g_info = {
a6c45cf0 177 .gen = 4, .is_broadwater = 1,
c96c3a8c 178 .has_hotplug = 1,
31578148 179 .has_overlay = 1,
cfdf1fa2
KH		 180};
181
9a7e8492 182static const struct intel_device_info intel_i965gm_info = {
a6c45cf0 183 .gen = 4, .is_crestline = 1,
e3c4e5dd 184 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
31578148 185 .has_overlay = 1,
a6c45cf0 186 .supports_tv = 1,
cfdf1fa2
KH		 187};
188
9a7e8492 189static const struct intel_device_info intel_g33_info = {
a6c45cf0 190 .gen = 3, .is_g33 = 1,
c96c3a8c 191 .need_gfx_hws = 1, .has_hotplug = 1,
31578148 192 .has_overlay = 1,
cfdf1fa2
KH		 193};
194
9a7e8492 195static const struct intel_device_info intel_g45_info = {
a6c45cf0 196 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
c96c3a8c 197 .has_pipe_cxsr = 1, .has_hotplug = 1,
92f49d9c 198 .has_bsd_ring = 1,
cfdf1fa2
KH		 199};
200
9a7e8492 201static const struct intel_device_info intel_gm45_info = {
a6c45cf0 202 .gen = 4, .is_g4x = 1,
e3c4e5dd 203 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
c96c3a8c 204 .has_pipe_cxsr = 1, .has_hotplug = 1,
a6c45cf0 205 .supports_tv = 1,
92f49d9c 206 .has_bsd_ring = 1,
cfdf1fa2
KH		 207};
208
9a7e8492 209static const struct intel_device_info intel_pineview_info = {
a6c45cf0 210 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
c96c3a8c 211 .need_gfx_hws = 1, .has_hotplug = 1,
31578148 212 .has_overlay = 1,
cfdf1fa2
KH		 213};
214
9a7e8492 215static const struct intel_device_info intel_ironlake_d_info = {
f00a3ddf 216 .gen = 5,
5a117db7 217 .need_gfx_hws = 1, .has_hotplug = 1,
92f49d9c 218 .has_bsd_ring = 1,
cfdf1fa2
KH		 219};
220
9a7e8492 221static const struct intel_device_info intel_ironlake_m_info = {
f00a3ddf 222 .gen = 5, .is_mobile = 1,
e3c4e5dd 223 .need_gfx_hws = 1, .has_hotplug = 1,
c1a9f047 224 .has_fbc = 1,
92f49d9c 225 .has_bsd_ring = 1,
cfdf1fa2
KH		 226};
227
9a7e8492 228static const struct intel_device_info intel_sandybridge_d_info = {
a6c45cf0 229 .gen = 6,
c96c3a8c 230 .need_gfx_hws = 1, .has_hotplug = 1,
881f47b6 231 .has_bsd_ring = 1,
549f7365 232 .has_blt_ring = 1,
3d29b842 233 .has_llc = 1,
b7884eb4 234 .has_force_wake = 1,
f6e450a6
EA		 235};
236
9a7e8492 237static const struct intel_device_info intel_sandybridge_m_info = {
a6c45cf0 238 .gen = 6, .is_mobile = 1,
c96c3a8c 239 .need_gfx_hws = 1, .has_hotplug = 1,
9c04f015 240 .has_fbc = 1,
881f47b6 241 .has_bsd_ring = 1,
549f7365 242 .has_blt_ring = 1,
3d29b842 243 .has_llc = 1,
b7884eb4 244 .has_force_wake = 1,
a13e4093
EA		 245};
246
c76b615c
JB		 247static const struct intel_device_info intel_ivybridge_d_info = {
248 .is_ivybridge = 1, .gen = 7,
249 .need_gfx_hws = 1, .has_hotplug = 1,
250 .has_bsd_ring = 1,
251 .has_blt_ring = 1,
3d29b842 252 .has_llc = 1,
b7884eb4 253 .has_force_wake = 1,
c76b615c
JB		 254};
255
256static const struct intel_device_info intel_ivybridge_m_info = {
257 .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
258 .need_gfx_hws = 1, .has_hotplug = 1,
259 .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */
260 .has_bsd_ring = 1,
261 .has_blt_ring = 1,
3d29b842 262 .has_llc = 1,
b7884eb4 263 .has_force_wake = 1,
c76b615c
JB		 264};
265
70a3eb7a
JB		 266static const struct intel_device_info intel_valleyview_m_info = {
267 .gen = 7, .is_mobile = 1,
268 .need_gfx_hws = 1, .has_hotplug = 1,
269 .has_fbc = 0,
270 .has_bsd_ring = 1,
271 .has_blt_ring = 1,
272 .is_valleyview = 1,
273};
274
275static const struct intel_device_info intel_valleyview_d_info = {
276 .gen = 7,
277 .need_gfx_hws = 1, .has_hotplug = 1,
278 .has_fbc = 0,
279 .has_bsd_ring = 1,
280 .has_blt_ring = 1,
281 .is_valleyview = 1,
282};
283
4cae9ae0
ED		 284static const struct intel_device_info intel_haswell_d_info = {
285 .is_haswell = 1, .gen = 7,
286 .need_gfx_hws = 1, .has_hotplug = 1,
287 .has_bsd_ring = 1,
288 .has_blt_ring = 1,
289 .has_llc = 1,
b7884eb4 290 .has_force_wake = 1,
4cae9ae0
ED		 291};
292
293static const struct intel_device_info intel_haswell_m_info = {
294 .is_haswell = 1, .gen = 7, .is_mobile = 1,
295 .need_gfx_hws = 1, .has_hotplug = 1,
296 .has_bsd_ring = 1,
297 .has_blt_ring = 1,
298 .has_llc = 1,
b7884eb4 299 .has_force_wake = 1,
c76b615c
JB		 300};
301
6103da0d
CW		 302static const struct pci_device_id pciidlist[] = { /* aka */
303 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
304 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
305 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
5ce8ba7c 306 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
6103da0d
CW		 307 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
308 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
309 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
310 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
311 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
312 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
313 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
314 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
315 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
316 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
317 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
318 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
319 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
320 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
321 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
322 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
323 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
324 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
325 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
326 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
327 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
328 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
41a51428 329 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
cfdf1fa2
KH		 330 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
331 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
332 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
333 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
f6e450a6 334 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
85540480
ZW		 335 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
336 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
a13e4093 337 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
85540480 338 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
4fefe435 339 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
85540480 340 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
c76b615c
JB		 341 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
342 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
343 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
344 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
345 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
cc22a938 346 INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
c14f5286
ED		 347 INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
348 INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
349 INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
350 INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
351 INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
352 INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
353 INTEL_VGA_DEVICE(0x0c16, &intel_haswell_d_info), /* SDV */
ff049b6c
JB		 354 INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
355 INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
356 INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
49ae35f2 357 {0, 0, 0}
1da177e4
LT		 358};
359
79e53945
JB		 360#if defined(CONFIG_DRM_I915_KMS)
361MODULE_DEVICE_TABLE(pci, pciidlist);
362#endif
363
3bad0781 364#define INTEL_PCH_DEVICE_ID_MASK 0xff00
90711d50 365#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
3bad0781 366#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
c792513b 367#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
eb877ebf 368#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
3bad0781 369
0206e353 370void intel_detect_pch(struct drm_device *dev)
3bad0781
ZW		 371{
372 struct drm_i915_private *dev_priv = dev->dev_private;
373 struct pci_dev *pch;
374
375 /*
376 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
377 * make graphics device passthrough work easy for VMM, that only
378 * need to expose ISA bridge to let driver know the real hardware
379 * underneath. This is a requirement from virtualization team.
380 */
381 pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
382 if (pch) {
383 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
384 int id;
385 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
386
90711d50
JB		 387 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
388 dev_priv->pch_type = PCH_IBX;
ee7b9f93 389 dev_priv->num_pch_pll = 2;
90711d50
JB		 390 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
391 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
3bad0781 392 dev_priv->pch_type = PCH_CPT;
ee7b9f93 393 dev_priv->num_pch_pll = 2;
3bad0781 394 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
c792513b
JB		 395 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
396 /* PantherPoint is CPT compatible */
397 dev_priv->pch_type = PCH_CPT;
ee7b9f93 398 dev_priv->num_pch_pll = 2;
c792513b 399 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
eb877ebf
ED		 400 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
401 dev_priv->pch_type = PCH_LPT;
ee7b9f93 402 dev_priv->num_pch_pll = 0;
eb877ebf 403 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
3bad0781 404 }
ee7b9f93 405 BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
3bad0781
ZW		 406 }
407 pci_dev_put(pch);
408 }
409}
410
2911a35b
BW		 411bool i915_semaphore_is_enabled(struct drm_device *dev)
412{
413 if (INTEL_INFO(dev)->gen < 6)
414 return 0;
415
416 if (i915_semaphores >= 0)
417 return i915_semaphores;
418
59de3295 419#ifdef CONFIG_INTEL_IOMMU
2911a35b 420 /* Enable semaphores on SNB when IO remapping is off */
59de3295
DV		 421 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
422 return false;
423#endif
2911a35b
BW		 424
425 return 1;
426}
427
84b79f8d 428static int i915_drm_freeze(struct drm_device *dev)
ba8bbcf6 429{
61caf87c
RW		 430 struct drm_i915_private *dev_priv = dev->dev_private;
431
5bcf719b
DA		 432 drm_kms_helper_poll_disable(dev);
433
ba8bbcf6 434 pci_save_state(dev->pdev);
ba8bbcf6 435
5669fcac 436 /* If KMS is active, we do the leavevt stuff here */
226485e9 437 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
84b79f8d
RW		 438 int error = i915_gem_idle(dev);
439 if (error) {
226485e9 440 dev_err(&dev->pdev->dev,
84b79f8d
RW		 441 "GEM idle failed, resume might fail\n");
442 return error;
443 }
226485e9 444 drm_irq_uninstall(dev);
5669fcac
JB		 445 }
446
9e06dd39
JB		 447 i915_save_state(dev);
448
44834a67 449 intel_opregion_fini(dev);
8ee1c3db 450
84b79f8d
RW		 451 /* Modeset on resume, not lid events */
452 dev_priv->modeset_on_lid = 0;
61caf87c 453
3fa016a0
DA		 454 console_lock();
455 intel_fbdev_set_suspend(dev, 1);
456 console_unlock();
457
61caf87c 458 return 0;
84b79f8d
RW		 459}
460
6a9ee8af 461int i915_suspend(struct drm_device *dev, pm_message_t state)
84b79f8d
RW		 462{
463 int error;
464
465 if (!dev || !dev->dev_private) {
466 DRM_ERROR("dev: %p\n", dev);
467 DRM_ERROR("DRM not initialized, aborting suspend.\n");
468 return -ENODEV;
469 }
470
471 if (state.event == PM_EVENT_PRETHAW)
472 return 0;
473
5bcf719b
DA		 474
475 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
476 return 0;
6eecba33 477
84b79f8d
RW		 478 error = i915_drm_freeze(dev);
479 if (error)
480 return error;
481
b932ccb5
DA		 482 if (state.event == PM_EVENT_SUSPEND) {
483 /* Shut down the device */
484 pci_disable_device(dev->pdev);
485 pci_set_power_state(dev->pdev, PCI_D3hot);
486 }
ba8bbcf6
JB		 487
488 return 0;
489}
490
84b79f8d 491static int i915_drm_thaw(struct drm_device *dev)
ba8bbcf6 492{
5669fcac 493 struct drm_i915_private *dev_priv = dev->dev_private;
84b79f8d 494 int error = 0;
8ee1c3db 495
d1c3b177
CW		 496 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
497 mutex_lock(&dev->struct_mutex);
498 i915_gem_restore_gtt_mappings(dev);
499 mutex_unlock(&dev->struct_mutex);
500 }
501
61caf87c 502 i915_restore_state(dev);
44834a67 503 intel_opregion_setup(dev);
61caf87c 504
5669fcac
JB		 505 /* KMS EnterVT equivalent */
506 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
40579abe 507 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
1833b134
CW		 508 ironlake_init_pch_refclk(dev);
509
5669fcac
JB		 510 mutex_lock(&dev->struct_mutex);
511 dev_priv->mm.suspended = 0;
512
f691e2f4 513 error = i915_gem_init_hw(dev);
5669fcac 514 mutex_unlock(&dev->struct_mutex);
226485e9 515
1833b134 516 intel_modeset_init_hw(dev);
500f7147 517 drm_mode_config_reset(dev);
226485e9 518 drm_irq_install(dev);
84b79f8d 519
354ff967 520 /* Resume the modeset for every activated CRTC */
927a2f11 521 mutex_lock(&dev->mode_config.mutex);
354ff967 522 drm_helper_resume_force_mode(dev);
927a2f11 523 mutex_unlock(&dev->mode_config.mutex);
d5bb081b 524 }
1daed3fb 525
44834a67
CW		 526 intel_opregion_init(dev);
527
c9354c85 528 dev_priv->modeset_on_lid = 0;
06891e27 529
3fa016a0
DA		 530 console_lock();
531 intel_fbdev_set_suspend(dev, 0);
532 console_unlock();
84b79f8d
RW		 533 return error;
534}
535
6a9ee8af 536int i915_resume(struct drm_device *dev)
84b79f8d 537{
6eecba33
CW		 538 int ret;
539
5bcf719b
DA		 540 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
541 return 0;
542
84b79f8d
RW		 543 if (pci_enable_device(dev->pdev))
544 return -EIO;
545
546 pci_set_master(dev->pdev);
547
6eecba33
CW		 548 ret = i915_drm_thaw(dev);
549 if (ret)
550 return ret;
551
552 drm_kms_helper_poll_enable(dev);
553 return 0;
ba8bbcf6
JB		 554}
555
d4b8bb2a 556static int i8xx_do_reset(struct drm_device *dev)
dc96e9b8
CW		 557{
558 struct drm_i915_private *dev_priv = dev->dev_private;
559
560 if (IS_I85X(dev))
561 return -ENODEV;
562
563 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
564 POSTING_READ(D_STATE);
565
566 if (IS_I830(dev) || IS_845G(dev)) {
567 I915_WRITE(DEBUG_RESET_I830,
568 DEBUG_RESET_DISPLAY |
569 DEBUG_RESET_RENDER |
570 DEBUG_RESET_FULL);
571 POSTING_READ(DEBUG_RESET_I830);
572 msleep(1);
573
574 I915_WRITE(DEBUG_RESET_I830, 0);
575 POSTING_READ(DEBUG_RESET_I830);
576 }
577
578 msleep(1);
579
580 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
581 POSTING_READ(D_STATE);
582
583 return 0;
584}
585
f49f0586
KG		 586static int i965_reset_complete(struct drm_device *dev)
587{
588 u8 gdrst;
eeccdcac 589 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
5fe9fe8c 590 return (gdrst & GRDOM_RESET_ENABLE) == 0;
f49f0586
KG		 591}
592
d4b8bb2a 593static int i965_do_reset(struct drm_device *dev)
0573ed4a 594{
5ccce180 595 int ret;
0573ed4a
KG		 596 u8 gdrst;
597
ae681d96
CW		 598 /*
599 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
600 * well as the reset bit (GR/bit 0). Setting the GR bit
601 * triggers the reset; when done, the hardware will clear it.
602 */
0573ed4a 603 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
d4b8bb2a 604 pci_write_config_byte(dev->pdev, I965_GDRST,
5ccce180
DV		 605 gdrst | GRDOM_RENDER |
606 GRDOM_RESET_ENABLE);
607 ret = wait_for(i965_reset_complete(dev), 500);
608 if (ret)
609 return ret;
610
611 /* We can't reset render&media without also resetting display ... */
612 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
613 pci_write_config_byte(dev->pdev, I965_GDRST,
614 gdrst | GRDOM_MEDIA |
615 GRDOM_RESET_ENABLE);
0573ed4a
KG		 616
617 return wait_for(i965_reset_complete(dev), 500);
618}
619
d4b8bb2a 620static int ironlake_do_reset(struct drm_device *dev)
0573ed4a
KG		 621{
622 struct drm_i915_private *dev_priv = dev->dev_private;
5ccce180
DV		 623 u32 gdrst;
624 int ret;
625
626 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
627 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
628 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
629 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
630 if (ret)
631 return ret;
632
633 /* We can't reset render&media without also resetting display ... */
634 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
d4b8bb2a 635 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
5ccce180 636 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
0573ed4a 637 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
ba8bbcf6
JB		 638}
639
d4b8bb2a 640static int gen6_do_reset(struct drm_device *dev)
cff458c2
EA		 641{
642 struct drm_i915_private *dev_priv = dev->dev_private;
b6e45f86
KP		 643 int ret;
644 unsigned long irqflags;
cff458c2 645
286fed41
KP		 646 /* Hold gt_lock across reset to prevent any register access
647 * with forcewake not set correctly
648 */
b6e45f86 649 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
286fed41
KP		 650
651 /* Reset the chip */
652
653 /* GEN6_GDRST is not in the gt power well, no need to check
654 * for fifo space for the write or forcewake the chip for
655 * the read
656 */
657 I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
658
659 /* Spin waiting for the device to ack the reset request */
660 ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
661
662 /* If reset with a user forcewake, try to restore, otherwise turn it off */
b6e45f86 663 if (dev_priv->forcewake_count)
990bbdad 664 dev_priv->gt.force_wake_get(dev_priv);
286fed41 665 else
990bbdad 666 dev_priv->gt.force_wake_put(dev_priv);
286fed41
KP		 667
668 /* Restore fifo count */
669 dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
670
b6e45f86
KP		 671 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
672 return ret;
cff458c2
EA		 673}
674
8e96d9c4 675int intel_gpu_reset(struct drm_device *dev)
350d2706 676{
2b9dc9a2 677 struct drm_i915_private *dev_priv = dev->dev_private;
350d2706
DV		 678 int ret = -ENODEV;
679
680 switch (INTEL_INFO(dev)->gen) {
681 case 7:
682 case 6:
d4b8bb2a 683 ret = gen6_do_reset(dev);
350d2706
DV		 684 break;
685 case 5:
d4b8bb2a 686 ret = ironlake_do_reset(dev);
350d2706
DV		 687 break;
688 case 4:
d4b8bb2a 689 ret = i965_do_reset(dev);
350d2706
DV		 690 break;
691 case 2:
d4b8bb2a 692 ret = i8xx_do_reset(dev);
350d2706
DV		 693 break;
694 }
695
2b9dc9a2
DV		 696 /* Also reset the gpu hangman. */
697 if (dev_priv->stop_rings) {
698 DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n");
699 dev_priv->stop_rings = 0;
700 if (ret == -ENODEV) {
701 DRM_ERROR("Reset not implemented, but ignoring "
702 "error for simulated gpu hangs\n");
703 ret = 0;
704 }
705 }
706
350d2706
DV		 707 return ret;
708}
709
11ed50ec 710/**
f3953dcb 711 * i915_reset - reset chip after a hang
11ed50ec 712 * @dev: drm device to reset
11ed50ec
BG		 713 *
714 * Reset the chip. Useful if a hang is detected. Returns zero on successful
715 * reset or otherwise an error code.
716 *
717 * Procedure is fairly simple:
718 * - reset the chip using the reset reg
719 * - re-init context state
720 * - re-init hardware status page
721 * - re-init ring buffer
722 * - re-init interrupt state
723 * - re-init display
724 */
d4b8bb2a 725int i915_reset(struct drm_device *dev)
11ed50ec
BG		 726{
727 drm_i915_private_t *dev_priv = dev->dev_private;
0573ed4a 728 int ret;
11ed50ec 729
d78cb50b
CW		 730 if (!i915_try_reset)
731 return 0;
732
340479aa
CW		 733 if (!mutex_trylock(&dev->struct_mutex))
734 return -EBUSY;
11ed50ec 735
069efc1d 736 i915_gem_reset(dev);
77f01230 737
f803aa55 738 ret = -ENODEV;
350d2706 739 if (get_seconds() - dev_priv->last_gpu_reset < 5)
ae681d96 740 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
350d2706 741 else
d4b8bb2a 742 ret = intel_gpu_reset(dev);
350d2706 743
ae681d96 744 dev_priv->last_gpu_reset = get_seconds();
0573ed4a 745 if (ret) {
f803aa55 746 DRM_ERROR("Failed to reset chip.\n");
f953c935 747 mutex_unlock(&dev->struct_mutex);
f803aa55 748 return ret;
11ed50ec
BG		 749 }
750
751 /* Ok, now get things going again... */
752
753 /*
754 * Everything depends on having the GTT running, so we need to start
755 * there. Fortunately we don't need to do this unless we reset the
756 * chip at a PCI level.
757 *
758 * Next we need to restore the context, but we don't use those
759 * yet either...
760 *
761 * Ring buffer needs to be re-initialized in the KMS case, or if X
762 * was running at the time of the reset (i.e. we weren't VT
763 * switched away).
764 */
765 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
8187a2b7 766 !dev_priv->mm.suspended) {
b4519513
CW		 767 struct intel_ring_buffer *ring;
768 int i;
769
11ed50ec 770 dev_priv->mm.suspended = 0;
75a6898f 771
f691e2f4
DV		 772 i915_gem_init_swizzling(dev);
773
b4519513
CW		 774 for_each_ring(ring, dev_priv, i)
775 ring->init(ring);
75a6898f 776
254f965c 777 i915_gem_context_init(dev);
e21af88d
DV		 778 i915_gem_init_ppgtt(dev);
779
8e88a2bd
DV		 780 /*
781 * It would make sense to re-init all the other hw state, at
782 * least the rps/rc6/emon init done within modeset_init_hw. For
783 * some unknown reason, this blows up my ilk, so don't.
784 */
f817586c 785
8e88a2bd 786 mutex_unlock(&dev->struct_mutex);
f817586c 787
11ed50ec
BG		 788 drm_irq_uninstall(dev);
789 drm_irq_install(dev);
bcbc324a
DV		 790 } else {
791 mutex_unlock(&dev->struct_mutex);
11ed50ec
BG		 792 }
793
11ed50ec
BG		 794 return 0;
795}
796
112b715e
KH		 797static int __devinit
798i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
799{
01a06850
DV		 800 struct intel_device_info *intel_info =
801 (struct intel_device_info *) ent->driver_data;
802
5fe49d86
CW		 803 /* Only bind to function 0 of the device. Early generations
804 * used function 1 as a placeholder for multi-head. This causes
805 * us confusion instead, especially on the systems where both
806 * functions have the same PCI-ID!
807 */
808 if (PCI_FUNC(pdev->devfn))
809 return -ENODEV;
810
01a06850
DV		 811 /* We've managed to ship a kms-enabled ddx that shipped with an XvMC
812 * implementation for gen3 (and only gen3) that used legacy drm maps
813 * (gasp!) to share buffers between X and the client. Hence we need to
814 * keep around the fake agp stuff for gen3, even when kms is enabled. */
815 if (intel_info->gen != 3) {
816 driver.driver_features &=
817 ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
818 } else if (!intel_agp_enabled) {
819 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
820 return -ENODEV;
821 }
822
dcdb1674 823 return drm_get_pci_dev(pdev, ent, &driver);
112b715e
KH		 824}
825
826static void
827i915_pci_remove(struct pci_dev *pdev)
828{
829 struct drm_device *dev = pci_get_drvdata(pdev);
830
831 drm_put_dev(dev);
832}
833
84b79f8d 834static int i915_pm_suspend(struct device *dev)
112b715e 835{
84b79f8d
RW		 836 struct pci_dev *pdev = to_pci_dev(dev);
837 struct drm_device *drm_dev = pci_get_drvdata(pdev);
838 int error;
112b715e 839
84b79f8d
RW		 840 if (!drm_dev || !drm_dev->dev_private) {
841 dev_err(dev, "DRM not initialized, aborting suspend.\n");
842 return -ENODEV;
843 }
112b715e 844
5bcf719b
DA		 845 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
846 return 0;
847
84b79f8d
RW		 848 error = i915_drm_freeze(drm_dev);
849 if (error)
850 return error;
112b715e 851
84b79f8d
RW		 852 pci_disable_device(pdev);
853 pci_set_power_state(pdev, PCI_D3hot);
cbda12d7 854
84b79f8d 855 return 0;
cbda12d7
ZW		 856}
857
84b79f8d 858static int i915_pm_resume(struct device *dev)
cbda12d7 859{
84b79f8d
RW		 860 struct pci_dev *pdev = to_pci_dev(dev);
861 struct drm_device *drm_dev = pci_get_drvdata(pdev);
862
863 return i915_resume(drm_dev);
cbda12d7
ZW		 864}
865
84b79f8d 866static int i915_pm_freeze(struct device *dev)
cbda12d7 867{
84b79f8d
RW		 868 struct pci_dev *pdev = to_pci_dev(dev);
869 struct drm_device *drm_dev = pci_get_drvdata(pdev);
870
871 if (!drm_dev || !drm_dev->dev_private) {
872 dev_err(dev, "DRM not initialized, aborting suspend.\n");
873 return -ENODEV;
874 }
875
876 return i915_drm_freeze(drm_dev);
cbda12d7
ZW		 877}
878
84b79f8d 879static int i915_pm_thaw(struct device *dev)
cbda12d7 880{
84b79f8d
RW		 881 struct pci_dev *pdev = to_pci_dev(dev);
882 struct drm_device *drm_dev = pci_get_drvdata(pdev);
883
884 return i915_drm_thaw(drm_dev);
cbda12d7
ZW		 885}
886
84b79f8d 887static int i915_pm_poweroff(struct device *dev)
cbda12d7 888{
84b79f8d
RW		 889 struct pci_dev *pdev = to_pci_dev(dev);
890 struct drm_device *drm_dev = pci_get_drvdata(pdev);
84b79f8d 891
61caf87c 892 return i915_drm_freeze(drm_dev);
cbda12d7
ZW		 893}
894
b4b78d12 895static const struct dev_pm_ops i915_pm_ops = {
0206e353
AJ		 896 .suspend = i915_pm_suspend,
897 .resume = i915_pm_resume,
898 .freeze = i915_pm_freeze,
899 .thaw = i915_pm_thaw,
900 .poweroff = i915_pm_poweroff,
901 .restore = i915_pm_resume,
cbda12d7
ZW		 902};
903
78b68556 904static const struct vm_operations_struct i915_gem_vm_ops = {
de151cf6 905 .fault = i915_gem_fault,
ab00b3e5
JB		 906 .open = drm_gem_vm_open,
907 .close = drm_gem_vm_close,
de151cf6
JB		 908};
909
e08e96de
AV		 910static const struct file_operations i915_driver_fops = {
911 .owner = THIS_MODULE,
912 .open = drm_open,
913 .release = drm_release,
914 .unlocked_ioctl = drm_ioctl,
915 .mmap = drm_gem_mmap,
916 .poll = drm_poll,
917 .fasync = drm_fasync,
918 .read = drm_read,
919#ifdef CONFIG_COMPAT
920 .compat_ioctl = i915_compat_ioctl,
921#endif
922 .llseek = noop_llseek,
923};
924
1da177e4 925static struct drm_driver driver = {
0c54781b
MW		 926 /* Don't use MTRRs here; the Xserver or userspace app should
927 * deal with them for Intel hardware.
792d2b9a 928 */
673a394b
EA		 929 .driver_features =
930 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
1286ff73 931 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME,
22eae947 932 .load = i915_driver_load,
ba8bbcf6 933 .unload = i915_driver_unload,
673a394b 934 .open = i915_driver_open,
22eae947
DA		 935 .lastclose = i915_driver_lastclose,
936 .preclose = i915_driver_preclose,
673a394b 937 .postclose = i915_driver_postclose,
d8e29209
RW		 938
939 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
940 .suspend = i915_suspend,
941 .resume = i915_resume,
942
cda17380 943 .device_is_agp = i915_driver_device_is_agp,
1da177e4 944 .reclaim_buffers = drm_core_reclaim_buffers,
7c1c2871
DA		 945 .master_create = i915_master_create,
946 .master_destroy = i915_master_destroy,
955b12de 947#if defined(CONFIG_DEBUG_FS)
27c202ad
BG		 948 .debugfs_init = i915_debugfs_init,
949 .debugfs_cleanup = i915_debugfs_cleanup,
955b12de 950#endif
673a394b
EA		 951 .gem_init_object = i915_gem_init_object,
952 .gem_free_object = i915_gem_free_object,
de151cf6 953 .gem_vm_ops = &i915_gem_vm_ops,
1286ff73
DV		 954
955 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
956 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
957 .gem_prime_export = i915_gem_prime_export,
958 .gem_prime_import = i915_gem_prime_import,
959
ff72145b
DA		 960 .dumb_create = i915_gem_dumb_create,
961 .dumb_map_offset = i915_gem_mmap_gtt,
962 .dumb_destroy = i915_gem_dumb_destroy,
1da177e4 963 .ioctls = i915_ioctls,
e08e96de 964 .fops = &i915_driver_fops,
22eae947
DA		 965 .name = DRIVER_NAME,
966 .desc = DRIVER_DESC,
967 .date = DRIVER_DATE,
968 .major = DRIVER_MAJOR,
969 .minor = DRIVER_MINOR,
970 .patchlevel = DRIVER_PATCHLEVEL,
1da177e4
LT		 971};
972
8410ea3b
DA		 973static struct pci_driver i915_pci_driver = {
974 .name = DRIVER_NAME,
975 .id_table = pciidlist,
976 .probe = i915_pci_probe,
977 .remove = i915_pci_remove,
978 .driver.pm = &i915_pm_ops,
979};
980
1da177e4
LT		 981static int __init i915_init(void)
982{
983 driver.num_ioctls = i915_max_ioctl;
79e53945
JB		 984
985 /*
986 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
987 * explicitly disabled with the module pararmeter.
988 *
989 * Otherwise, just follow the parameter (defaulting to off).
990 *
991 * Allow optional vga_text_mode_force boot option to override
992 * the default behavior.
993 */
994#if defined(CONFIG_DRM_I915_KMS)
995 if (i915_modeset != 0)
996 driver.driver_features |= DRIVER_MODESET;
997#endif
998 if (i915_modeset == 1)
999 driver.driver_features |= DRIVER_MODESET;
1000
1001#ifdef CONFIG_VGA_CONSOLE
1002 if (vgacon_text_force() && i915_modeset == -1)
1003 driver.driver_features &= ~DRIVER_MODESET;
1004#endif
1005
3885c6bb
CW		 1006 if (!(driver.driver_features & DRIVER_MODESET))
1007 driver.get_vblank_timestamp = NULL;
1008
8410ea3b 1009 return drm_pci_init(&driver, &i915_pci_driver);
1da177e4
LT		 1010}
1011
1012static void __exit i915_exit(void)
1013{
8410ea3b 1014 drm_pci_exit(&driver, &i915_pci_driver);
1da177e4
LT		 1015}
1016
1017module_init(i915_init);
1018module_exit(i915_exit);
1019
b5e89ed5
DA		 1020MODULE_AUTHOR(DRIVER_AUTHOR);
1021MODULE_DESCRIPTION(DRIVER_DESC);
1da177e4 1022MODULE_LICENSE("GPL and additional rights");
f7000883 1023
b7d84096
JB		 1024/* We give fast paths for the really cool registers */
1025#define NEEDS_FORCE_WAKE(dev_priv, reg) \
b7884eb4
DV		 1026 ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
1027 ((reg) < 0x40000) && \
1028 ((reg) != FORCEWAKE))
b7d84096 1029
f7dff0c9
JB		 1030static bool IS_DISPLAYREG(u32 reg)
1031{
1032 /*
1033 * This should make it easier to transition modules over to the
1034 * new register block scheme, since we can do it incrementally.
1035 */
1036 if (reg >= 0x180000)
1037 return false;
1038
1039 if (reg >= RENDER_RING_BASE &&
1040 reg < RENDER_RING_BASE + 0xff)
1041 return false;
1042 if (reg >= GEN6_BSD_RING_BASE &&
1043 reg < GEN6_BSD_RING_BASE + 0xff)
1044 return false;
1045 if (reg >= BLT_RING_BASE &&
1046 reg < BLT_RING_BASE + 0xff)
1047 return false;
1048
1049 if (reg == PGTBL_ER)
1050 return false;
1051
1052 if (reg >= IPEIR_I965 &&
1053 reg < HWSTAM)
1054 return false;
1055
1056 if (reg == MI_MODE)
1057 return false;
1058
1059 if (reg == GFX_MODE_GEN7)
1060 return false;
1061
1062 if (reg == RENDER_HWS_PGA_GEN7 ||
1063 reg == BSD_HWS_PGA_GEN7 ||
1064 reg == BLT_HWS_PGA_GEN7)
1065 return false;
1066
1067 if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL ||
1068 reg == GEN6_BSD_RNCID)
1069 return false;
1070
1071 if (reg == GEN6_BLITTER_ECOSKPD)
1072 return false;
1073
1074 if (reg >= 0x4000c &&
1075 reg <= 0x4002c)
1076 return false;
1077
1078 if (reg >= 0x4f000 &&
1079 reg <= 0x4f08f)
1080 return false;
1081
1082 if (reg >= 0x4f100 &&
1083 reg <= 0x4f11f)
1084 return false;
1085
1086 if (reg >= VLV_MASTER_IER &&
1087 reg <= GEN6_PMIER)
1088 return false;
1089
1090 if (reg >= FENCE_REG_SANDYBRIDGE_0 &&
1091 reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8)))
1092 return false;
1093
1094 if (reg >= VLV_IIR_RW &&
1095 reg <= VLV_ISR)
1096 return false;
1097
1098 if (reg == FORCEWAKE_VLV ||
1099 reg == FORCEWAKE_ACK_VLV)
1100 return false;
1101
1102 if (reg == GEN6_GDRST)
1103 return false;
1104
1105 return true;
1106}
1107
f7000883
AK		 1108#define __i915_read(x, y) \
1109u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1110 u##x val = 0; \
1111 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
c937504e
KP		 1112 unsigned long irqflags; \
1113 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1114 if (dev_priv->forcewake_count == 0) \
990bbdad 1115 dev_priv->gt.force_wake_get(dev_priv); \
f7000883 1116 val = read##y(dev_priv->regs + reg); \
c937504e 1117 if (dev_priv->forcewake_count == 0) \
990bbdad 1118 dev_priv->gt.force_wake_put(dev_priv); \
c937504e 1119 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
f7dff0c9
JB		 1120 } else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
1121 val = read##y(dev_priv->regs + reg + 0x180000); \
f7000883
AK		 1122 } else { \
1123 val = read##y(dev_priv->regs + reg); \
1124 } \
1125 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1126 return val; \
1127}
1128
1129__i915_read(8, b)
1130__i915_read(16, w)
1131__i915_read(32, l)
1132__i915_read(64, q)
1133#undef __i915_read
1134
1135#define __i915_write(x, y) \
1136void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
67a3744f 1137 u32 __fifo_ret = 0; \
f7000883
AK		 1138 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1139 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
67a3744f 1140 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
f7000883 1141 } \
f7dff0c9
JB		 1142 if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
1143 write##y(val, dev_priv->regs + reg + 0x180000); \
1144 } else { \
1145 write##y(val, dev_priv->regs + reg); \
1146 } \
67a3744f
BW		 1147 if (unlikely(__fifo_ret)) { \
1148 gen6_gt_check_fifodbg(dev_priv); \
1149 } \
f7000883
AK		 1150}
1151__i915_write(8, b)
1152__i915_write(16, w)
1153__i915_write(32, l)
1154__i915_write(64, q)
1155#undef __i915_write
Linux 6.x block layer and io_uring tree(s)