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drm/i915: extract gt interrupt handler
[linux-2.6-block.git] / drivers / gpu / drm / i915 / i915_dma.c
CommitLineData
1da177e4
LT		 1/* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
1da177e4
LT		 31#include "drmP.h"
32#include "drm.h"
79e53945 33#include "drm_crtc_helper.h"
785b93ef 34#include "drm_fb_helper.h"
79e53945 35#include "intel_drv.h"
1da177e4
LT		 36#include "i915_drm.h"
37#include "i915_drv.h"
1c5d22f7 38#include "i915_trace.h"
63ee41d7 39#include "../../../platform/x86/intel_ips.h"
dcdb1674 40#include <linux/pci.h>
28d52043 41#include <linux/vgaarb.h>
c4804411
ZW		 42#include <linux/acpi.h>
43#include <linux/pnp.h>
6a9ee8af 44#include <linux/vga_switcheroo.h>
5a0e3ad6 45#include <linux/slab.h>
e0cd3608 46#include <linux/module.h>
44834a67 47#include <acpi/video.h>
9e984bc1 48#include <asm/pat.h>
1da177e4 49
4cbf74cc
CW		 50static void i915_write_hws_pga(struct drm_device *dev)
51{
52 drm_i915_private_t *dev_priv = dev->dev_private;
53 u32 addr;
54
55 addr = dev_priv->status_page_dmah->busaddr;
56 if (INTEL_INFO(dev)->gen >= 4)
57 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
58 I915_WRITE(HWS_PGA, addr);
59}
60
398c9cb2
KP		 61/**
62 * Sets up the hardware status page for devices that need a physical address
63 * in the register.
64 */
3043c60c 65static int i915_init_phys_hws(struct drm_device *dev)
398c9cb2
KP		 66{
67 drm_i915_private_t *dev_priv = dev->dev_private;
1ec14ad3 68
398c9cb2
KP		 69 /* Program Hardware Status Page */
70 dev_priv->status_page_dmah =
e6be8d9d 71 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
398c9cb2
KP		 72
73 if (!dev_priv->status_page_dmah) {
74 DRM_ERROR("Can not allocate hardware status page\n");
75 return -ENOMEM;
76 }
398c9cb2 77
f3234706
KP		 78 memset_io((void __force __iomem *)dev_priv->status_page_dmah->vaddr,
79 0, PAGE_SIZE);
398c9cb2 80
4cbf74cc 81 i915_write_hws_pga(dev);
9b974cc1 82
8a4c47f3 83 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
398c9cb2
KP		 84 return 0;
85}
86
87/**
88 * Frees the hardware status page, whether it's a physical address or a virtual
89 * address set up by the X Server.
90 */
3043c60c 91static void i915_free_hws(struct drm_device *dev)
398c9cb2
KP		 92{
93 drm_i915_private_t *dev_priv = dev->dev_private;
1ec14ad3
CW		 94 struct intel_ring_buffer *ring = LP_RING(dev_priv);
95
398c9cb2
KP		 96 if (dev_priv->status_page_dmah) {
97 drm_pci_free(dev, dev_priv->status_page_dmah);
98 dev_priv->status_page_dmah = NULL;
99 }
100
1ec14ad3
CW		 101 if (ring->status_page.gfx_addr) {
102 ring->status_page.gfx_addr = 0;
398c9cb2
KP		 103 drm_core_ioremapfree(&dev_priv->hws_map, dev);
104 }
105
106 /* Need to rewrite hardware status page */
107 I915_WRITE(HWS_PGA, 0x1ffff000);
108}
109
84b1fd10 110void i915_kernel_lost_context(struct drm_device * dev)
1da177e4
LT		 111{
112 drm_i915_private_t *dev_priv = dev->dev_private;
7c1c2871 113 struct drm_i915_master_private *master_priv;
1ec14ad3 114 struct intel_ring_buffer *ring = LP_RING(dev_priv);
1da177e4 115
79e53945
JB		 116 /*
117 * We should never lose context on the ring with modesetting
118 * as we don't expose it to userspace
119 */
120 if (drm_core_check_feature(dev, DRIVER_MODESET))
121 return;
122
8168bd48
CW		 123 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
124 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
1da177e4
LT		 125 ring->space = ring->head - (ring->tail + 8);
126 if (ring->space < 0)
8187a2b7 127 ring->space += ring->size;
1da177e4 128
7c1c2871
DA		 129 if (!dev->primary->master)
130 return;
131
132 master_priv = dev->primary->master->driver_priv;
133 if (ring->head == ring->tail && master_priv->sarea_priv)
134 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
1da177e4
LT		 135}
136
84b1fd10 137static int i915_dma_cleanup(struct drm_device * dev)
1da177e4 138{
ba8bbcf6 139 drm_i915_private_t *dev_priv = dev->dev_private;
1ec14ad3
CW		 140 int i;
141
1da177e4
LT		 142 /* Make sure interrupts are disabled here because the uninstall ioctl
143 * may not have been called from userspace and after dev_private
144 * is freed, it's too late.
145 */
ed4cb414 146 if (dev->irq_enabled)
b5e89ed5 147 drm_irq_uninstall(dev);
1da177e4 148
ee0c6bfb 149 mutex_lock(&dev->struct_mutex);
1ec14ad3
CW		 150 for (i = 0; i < I915_NUM_RINGS; i++)
151 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
ee0c6bfb 152 mutex_unlock(&dev->struct_mutex);
dc7a9319 153
398c9cb2
KP		 154 /* Clear the HWS virtual address at teardown */
155 if (I915_NEED_GFX_HWS(dev))
156 i915_free_hws(dev);
1da177e4
LT		 157
158 return 0;
159}
160
ba8bbcf6 161static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
1da177e4 162{
ba8bbcf6 163 drm_i915_private_t *dev_priv = dev->dev_private;
7c1c2871 164 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
e8616b6c 165 int ret;
1da177e4 166
3a03ac1a
DA		 167 master_priv->sarea = drm_getsarea(dev);
168 if (master_priv->sarea) {
169 master_priv->sarea_priv = (drm_i915_sarea_t *)
170 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
171 } else {
8a4c47f3 172 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
3a03ac1a
DA		 173 }
174
673a394b 175 if (init->ring_size != 0) {
e8616b6c 176 if (LP_RING(dev_priv)->obj != NULL) {
673a394b
EA		 177 i915_dma_cleanup(dev);
178 DRM_ERROR("Client tried to initialize ringbuffer in "
179 "GEM mode\n");
180 return -EINVAL;
181 }
1da177e4 182
e8616b6c
CW		 183 ret = intel_render_ring_init_dri(dev,
184 init->ring_start,
185 init->ring_size);
186 if (ret) {
673a394b 187 i915_dma_cleanup(dev);
e8616b6c 188 return ret;
673a394b 189 }
1da177e4
LT		 190 }
191
a6b54f3f 192 dev_priv->cpp = init->cpp;
1da177e4
LT		 193 dev_priv->back_offset = init->back_offset;
194 dev_priv->front_offset = init->front_offset;
195 dev_priv->current_page = 0;
7c1c2871
DA		 196 if (master_priv->sarea_priv)
197 master_priv->sarea_priv->pf_current_page = 0;
1da177e4 198
1da177e4
LT		 199 /* Allow hardware batchbuffers unless told otherwise.
200 */
201 dev_priv->allow_batchbuffer = 1;
202
1da177e4
LT		 203 return 0;
204}
205
84b1fd10 206static int i915_dma_resume(struct drm_device * dev)
1da177e4
LT		 207{
208 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1ec14ad3 209 struct intel_ring_buffer *ring = LP_RING(dev_priv);
1da177e4 210
8a4c47f3 211 DRM_DEBUG_DRIVER("%s\n", __func__);
1da177e4 212
8187a2b7 213 if (ring->map.handle == NULL) {
1da177e4
LT		 214 DRM_ERROR("can not ioremap virtual address for"
215 " ring buffer\n");
20caafa6 216 return -ENOMEM;
1da177e4
LT		 217 }
218
219 /* Program Hardware Status Page */
8187a2b7 220 if (!ring->status_page.page_addr) {
1da177e4 221 DRM_ERROR("Can not find hardware status page\n");
20caafa6 222 return -EINVAL;
1da177e4 223 }
8a4c47f3 224 DRM_DEBUG_DRIVER("hw status page @ %p\n",
8187a2b7
ZN		 225 ring->status_page.page_addr);
226 if (ring->status_page.gfx_addr != 0)
78501eac 227 intel_ring_setup_status_page(ring);
dc7a9319 228 else
4cbf74cc 229 i915_write_hws_pga(dev);
8187a2b7 230
8a4c47f3 231 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
1da177e4
LT		 232
233 return 0;
234}
235
c153f45f
EA		 236static int i915_dma_init(struct drm_device *dev, void *data,
237 struct drm_file *file_priv)
1da177e4 238{
c153f45f 239 drm_i915_init_t *init = data;
1da177e4
LT		 240 int retcode = 0;
241
c153f45f 242 switch (init->func) {
1da177e4 243 case I915_INIT_DMA:
ba8bbcf6 244 retcode = i915_initialize(dev, init);
1da177e4
LT		 245 break;
246 case I915_CLEANUP_DMA:
247 retcode = i915_dma_cleanup(dev);
248 break;
249 case I915_RESUME_DMA:
0d6aa60b 250 retcode = i915_dma_resume(dev);
1da177e4
LT		 251 break;
252 default:
20caafa6 253 retcode = -EINVAL;
1da177e4
LT		 254 break;
255 }
256
257 return retcode;
258}
259
260/* Implement basically the same security restrictions as hardware does
261 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
262 *
263 * Most of the calculations below involve calculating the size of a
264 * particular instruction. It's important to get the size right as
265 * that tells us where the next instruction to check is. Any illegal
266 * instruction detected will be given a size of zero, which is a
267 * signal to abort the rest of the buffer.
268 */
e1f99ce6 269static int validate_cmd(int cmd)
1da177e4
LT		 270{
271 switch (((cmd >> 29) & 0x7)) {
272 case 0x0:
273 switch ((cmd >> 23) & 0x3f) {
274 case 0x0:
275 return 1; /* MI_NOOP */
276 case 0x4:
277 return 1; /* MI_FLUSH */
278 default:
279 return 0; /* disallow everything else */
280 }
281 break;
282 case 0x1:
283 return 0; /* reserved */
284 case 0x2:
285 return (cmd & 0xff) + 2; /* 2d commands */
286 case 0x3:
287 if (((cmd >> 24) & 0x1f) <= 0x18)
288 return 1;
289
290 switch ((cmd >> 24) & 0x1f) {
291 case 0x1c:
292 return 1;
293 case 0x1d:
b5e89ed5 294 switch ((cmd >> 16) & 0xff) {
1da177e4
LT		 295 case 0x3:
296 return (cmd & 0x1f) + 2;
297 case 0x4:
298 return (cmd & 0xf) + 2;
299 default:
300 return (cmd & 0xffff) + 2;
301 }
302 case 0x1e:
303 if (cmd & (1 << 23))
304 return (cmd & 0xffff) + 1;
305 else
306 return 1;
307 case 0x1f:
308 if ((cmd & (1 << 23)) == 0) /* inline vertices */
309 return (cmd & 0x1ffff) + 2;
310 else if (cmd & (1 << 17)) /* indirect random */
311 if ((cmd & 0xffff) == 0)
312 return 0; /* unknown length, too hard */
313 else
314 return (((cmd & 0xffff) + 1) / 2) + 1;
315 else
316 return 2; /* indirect sequential */
317 default:
318 return 0;
319 }
320 default:
321 return 0;
322 }
323
324 return 0;
325}
326
201361a5 327static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
1da177e4
LT		 328{
329 drm_i915_private_t *dev_priv = dev->dev_private;
e1f99ce6 330 int i, ret;
1da177e4 331
1ec14ad3 332 if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
20caafa6 333 return -EINVAL;
de227f5f 334
1da177e4 335 for (i = 0; i < dwords;) {
e1f99ce6
CW		 336 int sz = validate_cmd(buffer[i]);
337 if (sz == 0 || i + sz > dwords)
20caafa6 338 return -EINVAL;
e1f99ce6 339 i += sz;
1da177e4
LT		 340 }
341
e1f99ce6
CW		 342 ret = BEGIN_LP_RING((dwords+1)&~1);
343 if (ret)
344 return ret;
345
346 for (i = 0; i < dwords; i++)
347 OUT_RING(buffer[i]);
de227f5f
DA		 348 if (dwords & 1)
349 OUT_RING(0);
350
351 ADVANCE_LP_RING();
352
1da177e4
LT		 353 return 0;
354}
355
673a394b
EA		 356int
357i915_emit_box(struct drm_device *dev,
c4e7a414
CW		 358 struct drm_clip_rect *box,
359 int DR1, int DR4)
1da177e4 360{
e1f99ce6 361 struct drm_i915_private *dev_priv = dev->dev_private;
e1f99ce6 362 int ret;
1da177e4 363
c4e7a414
CW		 364 if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
365 box->y2 <= 0 || box->x2 <= 0) {
1da177e4 366 DRM_ERROR("Bad box %d,%d..%d,%d\n",
c4e7a414 367 box->x1, box->y1, box->x2, box->y2);
20caafa6 368 return -EINVAL;
1da177e4
LT		 369 }
370
a6c45cf0 371 if (INTEL_INFO(dev)->gen >= 4) {
e1f99ce6
CW		 372 ret = BEGIN_LP_RING(4);
373 if (ret)
374 return ret;
375
c29b669c 376 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
c4e7a414
CW		 377 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
378 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
c29b669c 379 OUT_RING(DR4);
c29b669c 380 } else {
e1f99ce6
CW		 381 ret = BEGIN_LP_RING(6);
382 if (ret)
383 return ret;
384
c29b669c
AH		 385 OUT_RING(GFX_OP_DRAWRECT_INFO);
386 OUT_RING(DR1);
c4e7a414
CW		 387 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
388 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
c29b669c
AH		 389 OUT_RING(DR4);
390 OUT_RING(0);
c29b669c 391 }
e1f99ce6 392 ADVANCE_LP_RING();
1da177e4
LT		 393
394 return 0;
395}
396
c29b669c
AH		 397/* XXX: Emitting the counter should really be moved to part of the IRQ
398 * emit. For now, do it in both places:
399 */
400
84b1fd10 401static void i915_emit_breadcrumb(struct drm_device *dev)
de227f5f
DA		 402{
403 drm_i915_private_t *dev_priv = dev->dev_private;
7c1c2871 404 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
de227f5f 405
c99b058f 406 dev_priv->counter++;
af6061af 407 if (dev_priv->counter > 0x7FFFFFFFUL)
c99b058f 408 dev_priv->counter = 0;
7c1c2871
DA		 409 if (master_priv->sarea_priv)
410 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
de227f5f 411
e1f99ce6
CW		 412 if (BEGIN_LP_RING(4) == 0) {
413 OUT_RING(MI_STORE_DWORD_INDEX);
414 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
415 OUT_RING(dev_priv->counter);
416 OUT_RING(0);
417 ADVANCE_LP_RING();
418 }
de227f5f
DA		 419}
420
84b1fd10 421static int i915_dispatch_cmdbuffer(struct drm_device * dev,
201361a5
EA		 422 drm_i915_cmdbuffer_t *cmd,
423 struct drm_clip_rect *cliprects,
424 void *cmdbuf)
1da177e4
LT		 425{
426 int nbox = cmd->num_cliprects;
427 int i = 0, count, ret;
428
429 if (cmd->sz & 0x3) {
430 DRM_ERROR("alignment");
20caafa6 431 return -EINVAL;
1da177e4
LT		 432 }
433
434 i915_kernel_lost_context(dev);
435
436 count = nbox ? nbox : 1;
437
438 for (i = 0; i < count; i++) {
439 if (i < nbox) {
c4e7a414 440 ret = i915_emit_box(dev, &cliprects[i],
1da177e4
LT		 441 cmd->DR1, cmd->DR4);
442 if (ret)
443 return ret;
444 }
445
201361a5 446 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
1da177e4
LT		 447 if (ret)
448 return ret;
449 }
450
de227f5f 451 i915_emit_breadcrumb(dev);
1da177e4
LT		 452 return 0;
453}
454
84b1fd10 455static int i915_dispatch_batchbuffer(struct drm_device * dev,
201361a5
EA		 456 drm_i915_batchbuffer_t * batch,
457 struct drm_clip_rect *cliprects)
1da177e4 458{
e1f99ce6 459 struct drm_i915_private *dev_priv = dev->dev_private;
1da177e4 460 int nbox = batch->num_cliprects;
e1f99ce6 461 int i, count, ret;
1da177e4
LT		 462
463 if ((batch->start | batch->used) & 0x7) {
464 DRM_ERROR("alignment");
20caafa6 465 return -EINVAL;
1da177e4
LT		 466 }
467
468 i915_kernel_lost_context(dev);
469
470 count = nbox ? nbox : 1;
1da177e4
LT		 471 for (i = 0; i < count; i++) {
472 if (i < nbox) {
c4e7a414 473 ret = i915_emit_box(dev, &cliprects[i],
e1f99ce6 474 batch->DR1, batch->DR4);
1da177e4
LT		 475 if (ret)
476 return ret;
477 }
478
0790d5e1 479 if (!IS_I830(dev) && !IS_845G(dev)) {
e1f99ce6
CW		 480 ret = BEGIN_LP_RING(2);
481 if (ret)
482 return ret;
483
a6c45cf0 484 if (INTEL_INFO(dev)->gen >= 4) {
21f16289
DA		 485 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
486 OUT_RING(batch->start);
487 } else {
488 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
489 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
490 }
1da177e4 491 } else {
e1f99ce6
CW		 492 ret = BEGIN_LP_RING(4);
493 if (ret)
494 return ret;
495
1da177e4
LT		 496 OUT_RING(MI_BATCH_BUFFER);
497 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
498 OUT_RING(batch->start + batch->used - 4);
499 OUT_RING(0);
1da177e4 500 }
e1f99ce6 501 ADVANCE_LP_RING();
1da177e4
LT		 502 }
503
1cafd347 504
f00a3ddf 505 if (IS_G4X(dev) || IS_GEN5(dev)) {
e1f99ce6
CW		 506 if (BEGIN_LP_RING(2) == 0) {
507 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
508 OUT_RING(MI_NOOP);
509 ADVANCE_LP_RING();
510 }
1cafd347 511 }
1da177e4 512
e1f99ce6 513 i915_emit_breadcrumb(dev);
1da177e4
LT		 514 return 0;
515}
516
af6061af 517static int i915_dispatch_flip(struct drm_device * dev)
1da177e4
LT		 518{
519 drm_i915_private_t *dev_priv = dev->dev_private;
7c1c2871
DA		 520 struct drm_i915_master_private *master_priv =
521 dev->primary->master->driver_priv;
e1f99ce6 522 int ret;
1da177e4 523
7c1c2871 524 if (!master_priv->sarea_priv)
c99b058f
KH		 525 return -EINVAL;
526
8a4c47f3 527 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
be25ed9c 528 __func__,
529 dev_priv->current_page,
530 master_priv->sarea_priv->pf_current_page);
1da177e4 531
af6061af
DA		 532 i915_kernel_lost_context(dev);
533
e1f99ce6
CW		 534 ret = BEGIN_LP_RING(10);
535 if (ret)
536 return ret;
537
585fb111 538 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
af6061af 539 OUT_RING(0);
1da177e4 540
af6061af
DA		 541 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
542 OUT_RING(0);
543 if (dev_priv->current_page == 0) {
544 OUT_RING(dev_priv->back_offset);
545 dev_priv->current_page = 1;
1da177e4 546 } else {
af6061af
DA		 547 OUT_RING(dev_priv->front_offset);
548 dev_priv->current_page = 0;
1da177e4 549 }
af6061af 550 OUT_RING(0);
1da177e4 551
af6061af
DA		 552 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
553 OUT_RING(0);
e1f99ce6 554
af6061af 555 ADVANCE_LP_RING();
1da177e4 556
7c1c2871 557 master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
1da177e4 558
e1f99ce6
CW		 559 if (BEGIN_LP_RING(4) == 0) {
560 OUT_RING(MI_STORE_DWORD_INDEX);
561 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
562 OUT_RING(dev_priv->counter);
563 OUT_RING(0);
564 ADVANCE_LP_RING();
565 }
1da177e4 566
7c1c2871 567 master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
af6061af 568 return 0;
1da177e4
LT		 569}
570
1ec14ad3 571static int i915_quiescent(struct drm_device *dev)
1da177e4 572{
1ec14ad3 573 struct intel_ring_buffer *ring = LP_RING(dev->dev_private);
1da177e4
LT		 574
575 i915_kernel_lost_context(dev);
96f298aa 576 return intel_wait_ring_idle(ring);
1da177e4
LT		 577}
578
c153f45f
EA		 579static int i915_flush_ioctl(struct drm_device *dev, void *data,
580 struct drm_file *file_priv)
1da177e4 581{
546b0974
EA		 582 int ret;
583
584 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 585
546b0974
EA		 586 mutex_lock(&dev->struct_mutex);
587 ret = i915_quiescent(dev);
588 mutex_unlock(&dev->struct_mutex);
589
590 return ret;
1da177e4
LT		 591}
592
c153f45f
EA		 593static int i915_batchbuffer(struct drm_device *dev, void *data,
594 struct drm_file *file_priv)
1da177e4 595{
1da177e4 596 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7c1c2871 597 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1da177e4 598 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
7c1c2871 599 master_priv->sarea_priv;
c153f45f 600 drm_i915_batchbuffer_t *batch = data;
1da177e4 601 int ret;
201361a5 602 struct drm_clip_rect *cliprects = NULL;
1da177e4
LT		 603
604 if (!dev_priv->allow_batchbuffer) {
605 DRM_ERROR("Batchbuffer ioctl disabled\n");
20caafa6 606 return -EINVAL;
1da177e4
LT		 607 }
608
8a4c47f3 609 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
be25ed9c 610 batch->start, batch->used, batch->num_cliprects);
1da177e4 611
546b0974 612 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 613
201361a5
EA		 614 if (batch->num_cliprects < 0)
615 return -EINVAL;
616
617 if (batch->num_cliprects) {
9a298b2a
EA		 618 cliprects = kcalloc(batch->num_cliprects,
619 sizeof(struct drm_clip_rect),
620 GFP_KERNEL);
201361a5
EA		 621 if (cliprects == NULL)
622 return -ENOMEM;
623
624 ret = copy_from_user(cliprects, batch->cliprects,
625 batch->num_cliprects *
626 sizeof(struct drm_clip_rect));
9927a403
DC		 627 if (ret != 0) {
628 ret = -EFAULT;
201361a5 629 goto fail_free;
9927a403 630 }
201361a5 631 }
1da177e4 632
546b0974 633 mutex_lock(&dev->struct_mutex);
201361a5 634 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
546b0974 635 mutex_unlock(&dev->struct_mutex);
1da177e4 636
c99b058f 637 if (sarea_priv)
0baf823a 638 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
201361a5
EA		 639
640fail_free:
9a298b2a 641 kfree(cliprects);
201361a5 642
1da177e4
LT		 643 return ret;
644}
645
c153f45f
EA		 646static int i915_cmdbuffer(struct drm_device *dev, void *data,
647 struct drm_file *file_priv)
1da177e4 648{
1da177e4 649 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7c1c2871 650 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1da177e4 651 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
7c1c2871 652 master_priv->sarea_priv;
c153f45f 653 drm_i915_cmdbuffer_t *cmdbuf = data;
201361a5
EA		 654 struct drm_clip_rect *cliprects = NULL;
655 void *batch_data;
1da177e4
LT		 656 int ret;
657
8a4c47f3 658 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
be25ed9c 659 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
1da177e4 660
546b0974 661 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 662
201361a5
EA		 663 if (cmdbuf->num_cliprects < 0)
664 return -EINVAL;
665
9a298b2a 666 batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
201361a5
EA		 667 if (batch_data == NULL)
668 return -ENOMEM;
669
670 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
9927a403
DC		 671 if (ret != 0) {
672 ret = -EFAULT;
201361a5 673 goto fail_batch_free;
9927a403 674 }
201361a5
EA		 675
676 if (cmdbuf->num_cliprects) {
9a298b2a
EA		 677 cliprects = kcalloc(cmdbuf->num_cliprects,
678 sizeof(struct drm_clip_rect), GFP_KERNEL);
a40e8d31
OA		 679 if (cliprects == NULL) {
680 ret = -ENOMEM;
201361a5 681 goto fail_batch_free;
a40e8d31 682 }
201361a5
EA		 683
684 ret = copy_from_user(cliprects, cmdbuf->cliprects,
685 cmdbuf->num_cliprects *
686 sizeof(struct drm_clip_rect));
9927a403
DC		 687 if (ret != 0) {
688 ret = -EFAULT;
201361a5 689 goto fail_clip_free;
9927a403 690 }
1da177e4
LT		 691 }
692
546b0974 693 mutex_lock(&dev->struct_mutex);
201361a5 694 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
546b0974 695 mutex_unlock(&dev->struct_mutex);
1da177e4
LT		 696 if (ret) {
697 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
355d7f37 698 goto fail_clip_free;
1da177e4
LT		 699 }
700
c99b058f 701 if (sarea_priv)
0baf823a 702 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
201361a5 703
201361a5 704fail_clip_free:
9a298b2a 705 kfree(cliprects);
355d7f37 706fail_batch_free:
9a298b2a 707 kfree(batch_data);
201361a5
EA		 708
709 return ret;
1da177e4
LT		 710}
711
c153f45f
EA		 712static int i915_flip_bufs(struct drm_device *dev, void *data,
713 struct drm_file *file_priv)
1da177e4 714{
546b0974
EA		 715 int ret;
716
8a4c47f3 717 DRM_DEBUG_DRIVER("%s\n", __func__);
1da177e4 718
546b0974 719 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 720
546b0974
EA		 721 mutex_lock(&dev->struct_mutex);
722 ret = i915_dispatch_flip(dev);
723 mutex_unlock(&dev->struct_mutex);
724
725 return ret;
1da177e4
LT		 726}
727
c153f45f
EA		 728static int i915_getparam(struct drm_device *dev, void *data,
729 struct drm_file *file_priv)
1da177e4 730{
1da177e4 731 drm_i915_private_t *dev_priv = dev->dev_private;
c153f45f 732 drm_i915_getparam_t *param = data;
1da177e4
LT		 733 int value;
734
735 if (!dev_priv) {
3e684eae 736 DRM_ERROR("called with no initialization\n");
20caafa6 737 return -EINVAL;
1da177e4
LT		 738 }
739
c153f45f 740 switch (param->param) {
1da177e4 741 case I915_PARAM_IRQ_ACTIVE:
0a3e67a4 742 value = dev->pdev->irq ? 1 : 0;
1da177e4
LT		 743 break;
744 case I915_PARAM_ALLOW_BATCHBUFFER:
745 value = dev_priv->allow_batchbuffer ? 1 : 0;
746 break;
0d6aa60b
DA		 747 case I915_PARAM_LAST_DISPATCH:
748 value = READ_BREADCRUMB(dev_priv);
749 break;
ed4c9c4a
KH		 750 case I915_PARAM_CHIPSET_ID:
751 value = dev->pci_device;
752 break;
673a394b 753 case I915_PARAM_HAS_GEM:
ac5c4e76 754 value = dev_priv->has_gem;
673a394b 755 break;
0f973f27
JB		 756 case I915_PARAM_NUM_FENCES_AVAIL:
757 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
758 break;
02e792fb
DV		 759 case I915_PARAM_HAS_OVERLAY:
760 value = dev_priv->overlay ? 1 : 0;
761 break;
e9560f7c
JB		 762 case I915_PARAM_HAS_PAGEFLIPPING:
763 value = 1;
764 break;
76446cac
JB		 765 case I915_PARAM_HAS_EXECBUF2:
766 /* depends on GEM */
767 value = dev_priv->has_gem;
768 break;
e3a815fc
ZN		 769 case I915_PARAM_HAS_BSD:
770 value = HAS_BSD(dev);
771 break;
549f7365
CW		 772 case I915_PARAM_HAS_BLT:
773 value = HAS_BLT(dev);
774 break;
a00b10c3
CW		 775 case I915_PARAM_HAS_RELAXED_FENCING:
776 value = 1;
777 break;
bbf0c6b3
DV		 778 case I915_PARAM_HAS_COHERENT_RINGS:
779 value = 1;
780 break;
72bfa19c
CW		 781 case I915_PARAM_HAS_EXEC_CONSTANTS:
782 value = INTEL_INFO(dev)->gen >= 4;
783 break;
271d81b8
CW		 784 case I915_PARAM_HAS_RELAXED_DELTA:
785 value = 1;
786 break;
ae662d31
EA		 787 case I915_PARAM_HAS_GEN7_SOL_RESET:
788 value = 1;
789 break;
3d29b842
ED		 790 case I915_PARAM_HAS_LLC:
791 value = HAS_LLC(dev);
792 break;
777ee96f
DV		 793 case I915_PARAM_HAS_ALIASING_PPGTT:
794 value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
795 break;
1da177e4 796 default:
8a4c47f3 797 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
76446cac 798 param->param);
20caafa6 799 return -EINVAL;
1da177e4
LT		 800 }
801
c153f45f 802 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
1da177e4 803 DRM_ERROR("DRM_COPY_TO_USER failed\n");
20caafa6 804 return -EFAULT;
1da177e4
LT		 805 }
806
807 return 0;
808}
809
c153f45f
EA		 810static int i915_setparam(struct drm_device *dev, void *data,
811 struct drm_file *file_priv)
1da177e4 812{
1da177e4 813 drm_i915_private_t *dev_priv = dev->dev_private;
c153f45f 814 drm_i915_setparam_t *param = data;
1da177e4
LT		 815
816 if (!dev_priv) {
3e684eae 817 DRM_ERROR("called with no initialization\n");
20caafa6 818 return -EINVAL;
1da177e4
LT		 819 }
820
c153f45f 821 switch (param->param) {
1da177e4 822 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1da177e4
LT		 823 break;
824 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
c153f45f 825 dev_priv->tex_lru_log_granularity = param->value;
1da177e4
LT		 826 break;
827 case I915_SETPARAM_ALLOW_BATCHBUFFER:
c153f45f 828 dev_priv->allow_batchbuffer = param->value;
1da177e4 829 break;
0f973f27
JB		 830 case I915_SETPARAM_NUM_USED_FENCES:
831 if (param->value > dev_priv->num_fence_regs ||
832 param->value < 0)
833 return -EINVAL;
834 /* Userspace can use first N regs */
835 dev_priv->fence_reg_start = param->value;
836 break;
1da177e4 837 default:
8a4c47f3 838 DRM_DEBUG_DRIVER("unknown parameter %d\n",
be25ed9c 839 param->param);
20caafa6 840 return -EINVAL;
1da177e4
LT		 841 }
842
843 return 0;
844}
845
c153f45f
EA		 846static int i915_set_status_page(struct drm_device *dev, void *data,
847 struct drm_file *file_priv)
dc7a9319 848{
dc7a9319 849 drm_i915_private_t *dev_priv = dev->dev_private;
c153f45f 850 drm_i915_hws_addr_t *hws = data;
1ec14ad3 851 struct intel_ring_buffer *ring = LP_RING(dev_priv);
b39d50e5
ZW		 852
853 if (!I915_NEED_GFX_HWS(dev))
854 return -EINVAL;
dc7a9319
WZ		 855
856 if (!dev_priv) {
3e684eae 857 DRM_ERROR("called with no initialization\n");
20caafa6 858 return -EINVAL;
dc7a9319 859 }
dc7a9319 860
79e53945
JB		 861 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
862 WARN(1, "tried to set status page when mode setting active\n");
863 return 0;
864 }
865
8a4c47f3 866 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
c153f45f 867
8187a2b7 868 ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
dc7a9319 869
8b409580 870 dev_priv->hws_map.offset = dev->agp->base + hws->addr;
dc7a9319
WZ		 871 dev_priv->hws_map.size = 4*1024;
872 dev_priv->hws_map.type = 0;
873 dev_priv->hws_map.flags = 0;
874 dev_priv->hws_map.mtrr = 0;
875
dd0910b3 876 drm_core_ioremap_wc(&dev_priv->hws_map, dev);
dc7a9319 877 if (dev_priv->hws_map.handle == NULL) {
dc7a9319 878 i915_dma_cleanup(dev);
e20f9c64 879 ring->status_page.gfx_addr = 0;
dc7a9319
WZ		 880 DRM_ERROR("can not ioremap virtual address for"
881 " G33 hw status page\n");
20caafa6 882 return -ENOMEM;
dc7a9319 883 }
311bd68e
CW		 884 ring->status_page.page_addr =
885 (void __force __iomem *)dev_priv->hws_map.handle;
886 memset_io(ring->status_page.page_addr, 0, PAGE_SIZE);
8187a2b7 887 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
dc7a9319 888
8a4c47f3 889 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
e20f9c64 890 ring->status_page.gfx_addr);
8a4c47f3 891 DRM_DEBUG_DRIVER("load hws at %p\n",
e20f9c64 892 ring->status_page.page_addr);
dc7a9319
WZ		 893 return 0;
894}
895
ec2a4c3f
DA		 896static int i915_get_bridge_dev(struct drm_device *dev)
897{
898 struct drm_i915_private *dev_priv = dev->dev_private;
899
0206e353 900 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
ec2a4c3f
DA		 901 if (!dev_priv->bridge_dev) {
902 DRM_ERROR("bridge device not found\n");
903 return -1;
904 }
905 return 0;
906}
907
c4804411
ZW		 908#define MCHBAR_I915 0x44
909#define MCHBAR_I965 0x48
910#define MCHBAR_SIZE (4*4096)
911
912#define DEVEN_REG 0x54
913#define DEVEN_MCHBAR_EN (1 << 28)
914
915/* Allocate space for the MCH regs if needed, return nonzero on error */
916static int
917intel_alloc_mchbar_resource(struct drm_device *dev)
918{
919 drm_i915_private_t *dev_priv = dev->dev_private;
a6c45cf0 920 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
c4804411
ZW		 921 u32 temp_lo, temp_hi = 0;
922 u64 mchbar_addr;
a25c25c2 923 int ret;
c4804411 924
a6c45cf0 925 if (INTEL_INFO(dev)->gen >= 4)
c4804411
ZW		 926 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
927 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
928 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
929
930 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
931#ifdef CONFIG_PNP
932 if (mchbar_addr &&
a25c25c2
CW		 933 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
934 return 0;
c4804411
ZW		 935#endif
936
937 /* Get some space for it */
a25c25c2
CW		 938 dev_priv->mch_res.name = "i915 MCHBAR";
939 dev_priv->mch_res.flags = IORESOURCE_MEM;
940 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
941 &dev_priv->mch_res,
c4804411
ZW		 942 MCHBAR_SIZE, MCHBAR_SIZE,
943 PCIBIOS_MIN_MEM,
a25c25c2 944 0, pcibios_align_resource,
c4804411
ZW		 945 dev_priv->bridge_dev);
946 if (ret) {
947 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
948 dev_priv->mch_res.start = 0;
a25c25c2 949 return ret;
c4804411
ZW		 950 }
951
a6c45cf0 952 if (INTEL_INFO(dev)->gen >= 4)
c4804411
ZW		 953 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
954 upper_32_bits(dev_priv->mch_res.start));
955
956 pci_write_config_dword(dev_priv->bridge_dev, reg,
957 lower_32_bits(dev_priv->mch_res.start));
a25c25c2 958 return 0;
c4804411
ZW		 959}
960
961/* Setup MCHBAR if possible, return true if we should disable it again */
962static void
963intel_setup_mchbar(struct drm_device *dev)
964{
965 drm_i915_private_t *dev_priv = dev->dev_private;
a6c45cf0 966 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
c4804411
ZW		 967 u32 temp;
968 bool enabled;
969
970 dev_priv->mchbar_need_disable = false;
971
972 if (IS_I915G(dev) || IS_I915GM(dev)) {
973 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
974 enabled = !!(temp & DEVEN_MCHBAR_EN);
975 } else {
976 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
977 enabled = temp & 1;
978 }
979
980 /* If it's already enabled, don't have to do anything */
981 if (enabled)
982 return;
983
984 if (intel_alloc_mchbar_resource(dev))
985 return;
986
987 dev_priv->mchbar_need_disable = true;
988
989 /* Space is allocated or reserved, so enable it. */
990 if (IS_I915G(dev) || IS_I915GM(dev)) {
991 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
992 temp | DEVEN_MCHBAR_EN);
993 } else {
994 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
995 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
996 }
997}
998
999static void
1000intel_teardown_mchbar(struct drm_device *dev)
1001{
1002 drm_i915_private_t *dev_priv = dev->dev_private;
a6c45cf0 1003 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
c4804411
ZW		 1004 u32 temp;
1005
1006 if (dev_priv->mchbar_need_disable) {
1007 if (IS_I915G(dev) || IS_I915GM(dev)) {
1008 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1009 temp &= ~DEVEN_MCHBAR_EN;
1010 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1011 } else {
1012 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1013 temp &= ~1;
1014 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1015 }
1016 }
1017
1018 if (dev_priv->mch_res.start)
1019 release_resource(&dev_priv->mch_res);
1020}
1021
80824003
JB		 1022#define PTE_ADDRESS_MASK 0xfffff000
1023#define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */
1024#define PTE_MAPPING_TYPE_UNCACHED (0 << 1)
1025#define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */
1026#define PTE_MAPPING_TYPE_CACHED (3 << 1)
1027#define PTE_MAPPING_TYPE_MASK (3 << 1)
1028#define PTE_VALID (1 << 0)
1029
1030/**
fe669bf8
CW		 1031 * i915_stolen_to_phys - take an offset into stolen memory and turn it into
1032 * a physical one
80824003 1033 * @dev: drm device
fe669bf8 1034 * @offset: address to translate
80824003 1035 *
fe669bf8
CW		 1036 * Some chip functions require allocations from stolen space and need the
1037 * physical address of the memory in question.
80824003 1038 */
fe669bf8 1039static unsigned long i915_stolen_to_phys(struct drm_device *dev, u32 offset)
80824003 1040{
fe669bf8
CW		 1041 struct drm_i915_private *dev_priv = dev->dev_private;
1042 struct pci_dev *pdev = dev_priv->bridge_dev;
1043 u32 base;
1044
1045#if 0
1046 /* On the machines I have tested the Graphics Base of Stolen Memory
1047 * is unreliable, so compute the base by subtracting the stolen memory
1048 * from the Top of Low Usable DRAM which is where the BIOS places
1049 * the graphics stolen memory.
1050 */
1051 if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) {
1052 /* top 32bits are reserved = 0 */
1053 pci_read_config_dword(pdev, 0xA4, &base);
80824003 1054 } else {
fe669bf8
CW		 1055 /* XXX presume 8xx is the same as i915 */
1056 pci_bus_read_config_dword(pdev->bus, 2, 0x5C, &base);
1057 }
1058#else
1059 if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) {
1060 u16 val;
1061 pci_read_config_word(pdev, 0xb0, &val);
1062 base = val >> 4 << 20;
1063 } else {
1064 u8 val;
1065 pci_read_config_byte(pdev, 0x9c, &val);
1066 base = val >> 3 << 27;
80824003 1067 }
c64f7ba5 1068 base -= dev_priv->mm.gtt->stolen_size;
fe669bf8 1069#endif
80824003 1070
fe669bf8 1071 return base + offset;
80824003
JB		 1072}
1073
1074static void i915_warn_stolen(struct drm_device *dev)
1075{
1076 DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1077 DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1078}
1079
1080static void i915_setup_compression(struct drm_device *dev, int size)
1081{
1082 struct drm_i915_private *dev_priv = dev->dev_private;
132b6aab 1083 struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb);
29bd0ae2
AM		 1084 unsigned long cfb_base;
1085 unsigned long ll_base = 0;
80824003 1086
43a9539f
CW		 1087 /* Just in case the BIOS is doing something questionable. */
1088 intel_disable_fbc(dev);
1089
fe669bf8
CW		 1090 compressed_fb = drm_mm_search_free(&dev_priv->mm.stolen, size, 4096, 0);
1091 if (compressed_fb)
1092 compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1093 if (!compressed_fb)
1094 goto err;
80824003 1095
fe669bf8
CW		 1096 cfb_base = i915_stolen_to_phys(dev, compressed_fb->start);
1097 if (!cfb_base)
1098 goto err_fb;
80824003 1099
9c04f015 1100 if (!(IS_GM45(dev) || HAS_PCH_SPLIT(dev))) {
fe669bf8
CW		 1101 compressed_llb = drm_mm_search_free(&dev_priv->mm.stolen,
1102 4096, 4096, 0);
1103 if (compressed_llb)
1104 compressed_llb = drm_mm_get_block(compressed_llb,
1105 4096, 4096);
1106 if (!compressed_llb)
1107 goto err_fb;
74dff282 1108
fe669bf8
CW		 1109 ll_base = i915_stolen_to_phys(dev, compressed_llb->start);
1110 if (!ll_base)
1111 goto err_llb;
80824003
JB		 1112 }
1113
1114 dev_priv->cfb_size = size;
1115
20bf377e 1116 dev_priv->compressed_fb = compressed_fb;
9c04f015 1117 if (HAS_PCH_SPLIT(dev))
b52eb4dc
ZY		 1118 I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start);
1119 else if (IS_GM45(dev)) {
74dff282
JB		 1120 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1121 } else {
74dff282
JB		 1122 I915_WRITE(FBC_CFB_BASE, cfb_base);
1123 I915_WRITE(FBC_LL_BASE, ll_base);
20bf377e 1124 dev_priv->compressed_llb = compressed_llb;
80824003
JB		 1125 }
1126
fe669bf8
CW		 1127 DRM_DEBUG_KMS("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n",
1128 cfb_base, ll_base, size >> 20);
1129 return;
1130
1131err_llb:
1132 drm_mm_put_block(compressed_llb);
1133err_fb:
1134 drm_mm_put_block(compressed_fb);
1135err:
1136 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1137 i915_warn_stolen(dev);
80824003
JB		 1138}
1139
20bf377e
JB		 1140static void i915_cleanup_compression(struct drm_device *dev)
1141{
1142 struct drm_i915_private *dev_priv = dev->dev_private;
1143
1144 drm_mm_put_block(dev_priv->compressed_fb);
aebf0daf 1145 if (dev_priv->compressed_llb)
20bf377e
JB		 1146 drm_mm_put_block(dev_priv->compressed_llb);
1147}
1148
28d52043
DA		 1149/* true = enable decode, false = disable decoder */
1150static unsigned int i915_vga_set_decode(void *cookie, bool state)
1151{
1152 struct drm_device *dev = cookie;
1153
1154 intel_modeset_vga_set_state(dev, state);
1155 if (state)
1156 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1157 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1158 else
1159 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1160}
1161
6a9ee8af
DA		 1162static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1163{
1164 struct drm_device *dev = pci_get_drvdata(pdev);
1165 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1166 if (state == VGA_SWITCHEROO_ON) {
a70491cc 1167 pr_info("switched on\n");
5bcf719b 1168 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
6a9ee8af
DA		 1169 /* i915 resume handler doesn't set to D0 */
1170 pci_set_power_state(dev->pdev, PCI_D0);
1171 i915_resume(dev);
5bcf719b 1172 dev->switch_power_state = DRM_SWITCH_POWER_ON;
6a9ee8af 1173 } else {
a70491cc 1174 pr_err("switched off\n");
5bcf719b 1175 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
6a9ee8af 1176 i915_suspend(dev, pmm);
5bcf719b 1177 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
6a9ee8af
DA		 1178 }
1179}
1180
1181static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1182{
1183 struct drm_device *dev = pci_get_drvdata(pdev);
1184 bool can_switch;
1185
1186 spin_lock(&dev->count_lock);
1187 can_switch = (dev->open_count == 0);
1188 spin_unlock(&dev->count_lock);
1189 return can_switch;
1190}
1191
2c7111db 1192static int i915_load_gem_init(struct drm_device *dev)
79e53945
JB		 1193{
1194 struct drm_i915_private *dev_priv = dev->dev_private;
53984635 1195 unsigned long prealloc_size, gtt_size, mappable_size;
2c7111db 1196 int ret;
79e53945 1197
c64f7ba5 1198 prealloc_size = dev_priv->mm.gtt->stolen_size;
53984635
DV		 1199 gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
1200 mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
53984635 1201
fe669bf8
CW		 1202 /* Basic memrange allocator for stolen space */
1203 drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size);
79e53945 1204
d3ae0810 1205 mutex_lock(&dev->struct_mutex);
e21af88d 1206 if (i915_enable_ppgtt && HAS_ALIASING_PPGTT(dev)) {
1d2a314c
DV		 1207 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
1208 * aperture accordingly when using aliasing ppgtt. */
1209 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
1d2a314c 1210
644ec02b 1211 i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size);
1d2a314c
DV		 1212
1213 ret = i915_gem_init_aliasing_ppgtt(dev);
1214 if (ret)
1215 return ret;
1216 } else {
1217 /* Let GEM Manage all of the aperture.
1218 *
1219 * However, leave one page at the end still bound to the scratch
1220 * page. There are a number of places where the hardware
1221 * apparently prefetches past the end of the object, and we've
1222 * seen multiple hangs with the GPU head pointer stuck in a
1223 * batchbuffer bound at the last page of the aperture. One page
1224 * should be enough to keep any prefetching inside of the
1225 * aperture.
1226 */
644ec02b 1227 i915_gem_init_global_gtt(dev, 0, mappable_size,
d1dd20a9 1228 gtt_size);
1d2a314c 1229 }
79e53945 1230
f691e2f4 1231 ret = i915_gem_init_hw(dev);
11ed50ec 1232 mutex_unlock(&dev->struct_mutex);
1d2a314c
DV		 1233 if (ret) {
1234 i915_gem_cleanup_aliasing_ppgtt(dev);
2c7111db 1235 return ret;
1d2a314c 1236 }
79e53945 1237
80824003 1238 /* Try to set up FBC with a reasonable compressed buffer size */
9216d44d 1239 if (I915_HAS_FBC(dev) && i915_powersave) {
80824003
JB		 1240 int cfb_size;
1241
fe669bf8
CW		 1242 /* Leave 1M for line length buffer & misc. */
1243
1244 /* Try to get a 32M buffer... */
1245 if (prealloc_size > (36*1024*1024))
1246 cfb_size = 32*1024*1024;
80824003
JB		 1247 else /* fall back to 7/8 of the stolen space */
1248 cfb_size = prealloc_size * 7 / 8;
1249 i915_setup_compression(dev, cfb_size);
1250 }
1251
fe669bf8 1252 /* Allow hardware batchbuffers unless told otherwise. */
79e53945 1253 dev_priv->allow_batchbuffer = 1;
2c7111db
CW		 1254 return 0;
1255}
1256
1257static int i915_load_modeset_init(struct drm_device *dev)
1258{
1259 struct drm_i915_private *dev_priv = dev->dev_private;
1260 int ret;
79e53945 1261
6d139a87 1262 ret = intel_parse_bios(dev);
79e53945
JB		 1263 if (ret)
1264 DRM_INFO("failed to find VBIOS tables\n");
1265
934f992c
CW		 1266 /* If we have > 1 VGA cards, then we need to arbitrate access
1267 * to the common VGA resources.
1268 *
1269 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1270 * then we do not take part in VGA arbitration and the
1271 * vga_client_register() fails with -ENODEV.
1272 */
28d52043 1273 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
934f992c 1274 if (ret && ret != -ENODEV)
2c7111db 1275 goto out;
28d52043 1276
723bfd70
JB		 1277 intel_register_dsm_handler();
1278
6a9ee8af
DA		 1279 ret = vga_switcheroo_register_client(dev->pdev,
1280 i915_switcheroo_set_state,
8d608aa6 1281 NULL,
6a9ee8af
DA		 1282 i915_switcheroo_can_switch);
1283 if (ret)
5a79395b 1284 goto cleanup_vga_client;
6a9ee8af 1285
1afe3e9d
JB		 1286 /* IIR "flip pending" bit means done if this bit is set */
1287 if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
1288 dev_priv->flip_pending_is_done = true;
1289
b01f2c3a
JB		 1290 intel_modeset_init(dev);
1291
2c7111db 1292 ret = i915_load_gem_init(dev);
79e53945 1293 if (ret)
5a79395b 1294 goto cleanup_vga_switcheroo;
79e53945 1295
2c7111db
CW		 1296 intel_modeset_gem_init(dev);
1297
1298 ret = drm_irq_install(dev);
1299 if (ret)
1300 goto cleanup_gem;
1301
79e53945
JB		 1302 /* Always safe in the mode setting case. */
1303 /* FIXME: do pre/post-mode set stuff in core KMS code */
1304 dev->vblank_disable_allowed = 1;
1305
5a79395b
CW		 1306 ret = intel_fbdev_init(dev);
1307 if (ret)
1308 goto cleanup_irq;
1309
eb1f8e4f 1310 drm_kms_helper_poll_init(dev);
87acb0a5
CW		 1311
1312 /* We're off and running w/KMS */
1313 dev_priv->mm.suspended = 0;
1314
79e53945
JB		 1315 return 0;
1316
5a79395b
CW		 1317cleanup_irq:
1318 drm_irq_uninstall(dev);
2c7111db
CW		 1319cleanup_gem:
1320 mutex_lock(&dev->struct_mutex);
1321 i915_gem_cleanup_ringbuffer(dev);
1322 mutex_unlock(&dev->struct_mutex);
1d2a314c 1323 i915_gem_cleanup_aliasing_ppgtt(dev);
5a79395b
CW		 1324cleanup_vga_switcheroo:
1325 vga_switcheroo_unregister_client(dev->pdev);
1326cleanup_vga_client:
1327 vga_client_register(dev->pdev, NULL, NULL, NULL);
79e53945
JB		 1328out:
1329 return ret;
1330}
1331
7c1c2871
DA		 1332int i915_master_create(struct drm_device *dev, struct drm_master *master)
1333{
1334 struct drm_i915_master_private *master_priv;
1335
9a298b2a 1336 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
7c1c2871
DA		 1337 if (!master_priv)
1338 return -ENOMEM;
1339
1340 master->driver_priv = master_priv;
1341 return 0;
1342}
1343
1344void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1345{
1346 struct drm_i915_master_private *master_priv = master->driver_priv;
1347
1348 if (!master_priv)
1349 return;
1350
9a298b2a 1351 kfree(master_priv);
7c1c2871
DA		 1352
1353 master->driver_priv = NULL;
1354}
1355
7648fa99 1356static void i915_pineview_get_mem_freq(struct drm_device *dev)
7662c8bd
SL		 1357{
1358 drm_i915_private_t *dev_priv = dev->dev_private;
1359 u32 tmp;
1360
7662c8bd
SL		 1361 tmp = I915_READ(CLKCFG);
1362
1363 switch (tmp & CLKCFG_FSB_MASK) {
1364 case CLKCFG_FSB_533:
1365 dev_priv->fsb_freq = 533; /* 133*4 */
1366 break;
1367 case CLKCFG_FSB_800:
1368 dev_priv->fsb_freq = 800; /* 200*4 */
1369 break;
1370 case CLKCFG_FSB_667:
1371 dev_priv->fsb_freq = 667; /* 167*4 */
1372 break;
1373 case CLKCFG_FSB_400:
1374 dev_priv->fsb_freq = 400; /* 100*4 */
1375 break;
1376 }
1377
1378 switch (tmp & CLKCFG_MEM_MASK) {
1379 case CLKCFG_MEM_533:
1380 dev_priv->mem_freq = 533;
1381 break;
1382 case CLKCFG_MEM_667:
1383 dev_priv->mem_freq = 667;
1384 break;
1385 case CLKCFG_MEM_800:
1386 dev_priv->mem_freq = 800;
1387 break;
1388 }
95534263
LP		 1389
1390 /* detect pineview DDR3 setting */
1391 tmp = I915_READ(CSHRDDR3CTL);
1392 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
7662c8bd
SL		 1393}
1394
7648fa99
JB		 1395static void i915_ironlake_get_mem_freq(struct drm_device *dev)
1396{
1397 drm_i915_private_t *dev_priv = dev->dev_private;
1398 u16 ddrpll, csipll;
1399
1400 ddrpll = I915_READ16(DDRMPLL1);
1401 csipll = I915_READ16(CSIPLL0);
1402
1403 switch (ddrpll & 0xff) {
1404 case 0xc:
1405 dev_priv->mem_freq = 800;
1406 break;
1407 case 0x10:
1408 dev_priv->mem_freq = 1066;
1409 break;
1410 case 0x14:
1411 dev_priv->mem_freq = 1333;
1412 break;
1413 case 0x18:
1414 dev_priv->mem_freq = 1600;
1415 break;
1416 default:
1417 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
1418 ddrpll & 0xff);
1419 dev_priv->mem_freq = 0;
1420 break;
1421 }
1422
1423 dev_priv->r_t = dev_priv->mem_freq;
1424
1425 switch (csipll & 0x3ff) {
1426 case 0x00c:
1427 dev_priv->fsb_freq = 3200;
1428 break;
1429 case 0x00e:
1430 dev_priv->fsb_freq = 3733;
1431 break;
1432 case 0x010:
1433 dev_priv->fsb_freq = 4266;
1434 break;
1435 case 0x012:
1436 dev_priv->fsb_freq = 4800;
1437 break;
1438 case 0x014:
1439 dev_priv->fsb_freq = 5333;
1440 break;
1441 case 0x016:
1442 dev_priv->fsb_freq = 5866;
1443 break;
1444 case 0x018:
1445 dev_priv->fsb_freq = 6400;
1446 break;
1447 default:
1448 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
1449 csipll & 0x3ff);
1450 dev_priv->fsb_freq = 0;
1451 break;
1452 }
1453
1454 if (dev_priv->fsb_freq == 3200) {
1455 dev_priv->c_m = 0;
1456 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1457 dev_priv->c_m = 1;
1458 } else {
1459 dev_priv->c_m = 2;
1460 }
1461}
1462
faa60c41
CW		 1463static const struct cparams {
1464 u16 i;
1465 u16 t;
1466 u16 m;
1467 u16 c;
1468} cparams[] = {
7648fa99
JB		 1469 { 1, 1333, 301, 28664 },
1470 { 1, 1066, 294, 24460 },
1471 { 1, 800, 294, 25192 },
1472 { 0, 1333, 276, 27605 },
1473 { 0, 1066, 276, 27605 },
1474 { 0, 800, 231, 23784 },
1475};
1476
1477unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
1478{
1479 u64 total_count, diff, ret;
1480 u32 count1, count2, count3, m = 0, c = 0;
1481 unsigned long now = jiffies_to_msecs(jiffies), diff1;
1482 int i;
1483
1484 diff1 = now - dev_priv->last_time1;
1485
4ed0b577
ED		 1486 /* Prevent division-by-zero if we are asking too fast.
1487 * Also, we don't get interesting results if we are polling
1488 * faster than once in 10ms, so just return the saved value
1489 * in such cases.
1490 */
1491 if (diff1 <= 10)
1492 return dev_priv->chipset_power;
1493
7648fa99
JB		 1494 count1 = I915_READ(DMIEC);
1495 count2 = I915_READ(DDREC);
1496 count3 = I915_READ(CSIEC);
1497
1498 total_count = count1 + count2 + count3;
1499
1500 /* FIXME: handle per-counter overflow */
1501 if (total_count < dev_priv->last_count1) {
1502 diff = ~0UL - dev_priv->last_count1;
1503 diff += total_count;
1504 } else {
1505 diff = total_count - dev_priv->last_count1;
1506 }
1507
1508 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
1509 if (cparams[i].i == dev_priv->c_m &&
1510 cparams[i].t == dev_priv->r_t) {
1511 m = cparams[i].m;
1512 c = cparams[i].c;
1513 break;
1514 }
1515 }
1516
d270ae34 1517 diff = div_u64(diff, diff1);
7648fa99 1518 ret = ((m * diff) + c);
d270ae34 1519 ret = div_u64(ret, 10);
7648fa99
JB		 1520
1521 dev_priv->last_count1 = total_count;
1522 dev_priv->last_time1 = now;
1523
4ed0b577
ED		 1524 dev_priv->chipset_power = ret;
1525
7648fa99
JB		 1526 return ret;
1527}
1528
1529unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
1530{
1531 unsigned long m, x, b;
1532 u32 tsfs;
1533
1534 tsfs = I915_READ(TSFS);
1535
1536 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
1537 x = I915_READ8(TR1);
1538
1539 b = tsfs & TSFS_INTR_MASK;
1540
1541 return ((m * x) / 127) - b;
1542}
1543
faa60c41 1544static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
7648fa99 1545{
faa60c41
CW		 1546 static const struct v_table {
1547 u16 vd; /* in .1 mil */
1548 u16 vm; /* in .1 mil */
1549 } v_table[] = {
1550 { 0, 0, },
1551 { 375, 0, },
1552 { 500, 0, },
1553 { 625, 0, },
1554 { 750, 0, },
1555 { 875, 0, },
1556 { 1000, 0, },
1557 { 1125, 0, },
1558 { 4125, 3000, },
1559 { 4125, 3000, },
1560 { 4125, 3000, },
1561 { 4125, 3000, },
1562 { 4125, 3000, },
1563 { 4125, 3000, },
1564 { 4125, 3000, },
1565 { 4125, 3000, },
1566 { 4125, 3000, },
1567 { 4125, 3000, },
1568 { 4125, 3000, },
1569 { 4125, 3000, },
1570 { 4125, 3000, },
1571 { 4125, 3000, },
1572 { 4125, 3000, },
1573 { 4125, 3000, },
1574 { 4125, 3000, },
1575 { 4125, 3000, },
1576 { 4125, 3000, },
1577 { 4125, 3000, },
1578 { 4125, 3000, },
1579 { 4125, 3000, },
1580 { 4125, 3000, },
1581 { 4125, 3000, },
1582 { 4250, 3125, },
1583 { 4375, 3250, },
1584 { 4500, 3375, },
1585 { 4625, 3500, },
1586 { 4750, 3625, },
1587 { 4875, 3750, },
1588 { 5000, 3875, },
1589 { 5125, 4000, },
1590 { 5250, 4125, },
1591 { 5375, 4250, },
1592 { 5500, 4375, },
1593 { 5625, 4500, },
1594 { 5750, 4625, },
1595 { 5875, 4750, },
1596 { 6000, 4875, },
1597 { 6125, 5000, },
1598 { 6250, 5125, },
1599 { 6375, 5250, },
1600 { 6500, 5375, },
1601 { 6625, 5500, },
1602 { 6750, 5625, },
1603 { 6875, 5750, },
1604 { 7000, 5875, },
1605 { 7125, 6000, },
1606 { 7250, 6125, },
1607 { 7375, 6250, },
1608 { 7500, 6375, },
1609 { 7625, 6500, },
1610 { 7750, 6625, },
1611 { 7875, 6750, },
1612 { 8000, 6875, },
1613 { 8125, 7000, },
1614 { 8250, 7125, },
1615 { 8375, 7250, },
1616 { 8500, 7375, },
1617 { 8625, 7500, },
1618 { 8750, 7625, },
1619 { 8875, 7750, },
1620 { 9000, 7875, },
1621 { 9125, 8000, },
1622 { 9250, 8125, },
1623 { 9375, 8250, },
1624 { 9500, 8375, },
1625 { 9625, 8500, },
1626 { 9750, 8625, },
1627 { 9875, 8750, },
1628 { 10000, 8875, },
1629 { 10125, 9000, },
1630 { 10250, 9125, },
1631 { 10375, 9250, },
1632 { 10500, 9375, },
1633 { 10625, 9500, },
1634 { 10750, 9625, },
1635 { 10875, 9750, },
1636 { 11000, 9875, },
1637 { 11125, 10000, },
1638 { 11250, 10125, },
1639 { 11375, 10250, },
1640 { 11500, 10375, },
1641 { 11625, 10500, },
1642 { 11750, 10625, },
1643 { 11875, 10750, },
1644 { 12000, 10875, },
1645 { 12125, 11000, },
1646 { 12250, 11125, },
1647 { 12375, 11250, },
1648 { 12500, 11375, },
1649 { 12625, 11500, },
1650 { 12750, 11625, },
1651 { 12875, 11750, },
1652 { 13000, 11875, },
1653 { 13125, 12000, },
1654 { 13250, 12125, },
1655 { 13375, 12250, },
1656 { 13500, 12375, },
1657 { 13625, 12500, },
1658 { 13750, 12625, },
1659 { 13875, 12750, },
1660 { 14000, 12875, },
1661 { 14125, 13000, },
1662 { 14250, 13125, },
1663 { 14375, 13250, },
1664 { 14500, 13375, },
1665 { 14625, 13500, },
1666 { 14750, 13625, },
1667 { 14875, 13750, },
1668 { 15000, 13875, },
1669 { 15125, 14000, },
1670 { 15250, 14125, },
1671 { 15375, 14250, },
1672 { 15500, 14375, },
1673 { 15625, 14500, },
1674 { 15750, 14625, },
1675 { 15875, 14750, },
1676 { 16000, 14875, },
1677 { 16125, 15000, },
1678 };
1679 if (dev_priv->info->is_mobile)
1680 return v_table[pxvid].vm;
1681 else
1682 return v_table[pxvid].vd;
7648fa99
JB		 1683}
1684
1685void i915_update_gfx_val(struct drm_i915_private *dev_priv)
1686{
1687 struct timespec now, diff1;
1688 u64 diff;
1689 unsigned long diffms;
1690 u32 count;
1691
1692 getrawmonotonic(&now);
1693 diff1 = timespec_sub(now, dev_priv->last_time2);
1694
1695 /* Don't divide by 0 */
1696 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
1697 if (!diffms)
1698 return;
1699
1700 count = I915_READ(GFXEC);
1701
1702 if (count < dev_priv->last_count2) {
1703 diff = ~0UL - dev_priv->last_count2;
1704 diff += count;
1705 } else {
1706 diff = count - dev_priv->last_count2;
1707 }
1708
1709 dev_priv->last_count2 = count;
1710 dev_priv->last_time2 = now;
1711
1712 /* More magic constants... */
1713 diff = diff * 1181;
d270ae34 1714 diff = div_u64(diff, diffms * 10);
7648fa99
JB		 1715 dev_priv->gfx_power = diff;
1716}
1717
1718unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
1719{
1720 unsigned long t, corr, state1, corr2, state2;
1721 u32 pxvid, ext_v;
1722
1723 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
1724 pxvid = (pxvid >> 24) & 0x7f;
1725 ext_v = pvid_to_extvid(dev_priv, pxvid);
1726
1727 state1 = ext_v;
1728
1729 t = i915_mch_val(dev_priv);
1730
1731 /* Revel in the empirically derived constants */
1732
1733 /* Correction factor in 1/100000 units */
1734 if (t > 80)
1735 corr = ((t * 2349) + 135940);
1736 else if (t >= 50)
1737 corr = ((t * 964) + 29317);
1738 else /* < 50 */
1739 corr = ((t * 301) + 1004);
1740
1741 corr = corr * ((150142 * state1) / 10000 - 78642);
1742 corr /= 100000;
1743 corr2 = (corr * dev_priv->corr);
1744
1745 state2 = (corr2 * state1) / 10000;
1746 state2 /= 100; /* convert to mW */
1747
1748 i915_update_gfx_val(dev_priv);
1749
1750 return dev_priv->gfx_power + state2;
1751}
1752
1753/* Global for IPS driver to get at the current i915 device */
1754static struct drm_i915_private *i915_mch_dev;
1755/*
1756 * Lock protecting IPS related data structures
1757 * - i915_mch_dev
1758 * - dev_priv->max_delay
1759 * - dev_priv->min_delay
1760 * - dev_priv->fmax
1761 * - dev_priv->gpu_busy
1762 */
995b6762 1763static DEFINE_SPINLOCK(mchdev_lock);
7648fa99
JB		 1764
1765/**
1766 * i915_read_mch_val - return value for IPS use
1767 *
1768 * Calculate and return a value for the IPS driver to use when deciding whether
1769 * we have thermal and power headroom to increase CPU or GPU power budget.
1770 */
1771unsigned long i915_read_mch_val(void)
1772{
0206e353 1773 struct drm_i915_private *dev_priv;
7648fa99
JB		 1774 unsigned long chipset_val, graphics_val, ret = 0;
1775
0206e353 1776 spin_lock(&mchdev_lock);
7648fa99
JB		 1777 if (!i915_mch_dev)
1778 goto out_unlock;
1779 dev_priv = i915_mch_dev;
1780
1781 chipset_val = i915_chipset_val(dev_priv);
1782 graphics_val = i915_gfx_val(dev_priv);
1783
1784 ret = chipset_val + graphics_val;
1785
1786out_unlock:
0206e353 1787 spin_unlock(&mchdev_lock);
7648fa99 1788
0206e353 1789 return ret;
7648fa99
JB		 1790}
1791EXPORT_SYMBOL_GPL(i915_read_mch_val);
1792
1793/**
1794 * i915_gpu_raise - raise GPU frequency limit
1795 *
1796 * Raise the limit; IPS indicates we have thermal headroom.
1797 */
1798bool i915_gpu_raise(void)
1799{
0206e353 1800 struct drm_i915_private *dev_priv;
7648fa99
JB		 1801 bool ret = true;
1802
0206e353 1803 spin_lock(&mchdev_lock);
7648fa99
JB		 1804 if (!i915_mch_dev) {
1805 ret = false;
1806 goto out_unlock;
1807 }
1808 dev_priv = i915_mch_dev;
1809
1810 if (dev_priv->max_delay > dev_priv->fmax)
1811 dev_priv->max_delay--;
1812
1813out_unlock:
0206e353 1814 spin_unlock(&mchdev_lock);
7648fa99 1815
0206e353 1816 return ret;
7648fa99
JB		 1817}
1818EXPORT_SYMBOL_GPL(i915_gpu_raise);
1819
1820/**
1821 * i915_gpu_lower - lower GPU frequency limit
1822 *
1823 * IPS indicates we're close to a thermal limit, so throttle back the GPU
1824 * frequency maximum.
1825 */
1826bool i915_gpu_lower(void)
1827{
0206e353 1828 struct drm_i915_private *dev_priv;
7648fa99
JB		 1829 bool ret = true;
1830
0206e353 1831 spin_lock(&mchdev_lock);
7648fa99
JB		 1832 if (!i915_mch_dev) {
1833 ret = false;
1834 goto out_unlock;
1835 }
1836 dev_priv = i915_mch_dev;
1837
1838 if (dev_priv->max_delay < dev_priv->min_delay)
1839 dev_priv->max_delay++;
1840
1841out_unlock:
0206e353 1842 spin_unlock(&mchdev_lock);
7648fa99 1843
0206e353 1844 return ret;
7648fa99
JB		 1845}
1846EXPORT_SYMBOL_GPL(i915_gpu_lower);
1847
1848/**
1849 * i915_gpu_busy - indicate GPU business to IPS
1850 *
1851 * Tell the IPS driver whether or not the GPU is busy.
1852 */
1853bool i915_gpu_busy(void)
1854{
0206e353 1855 struct drm_i915_private *dev_priv;
7648fa99
JB		 1856 bool ret = false;
1857
0206e353 1858 spin_lock(&mchdev_lock);
7648fa99
JB		 1859 if (!i915_mch_dev)
1860 goto out_unlock;
1861 dev_priv = i915_mch_dev;
1862
1863 ret = dev_priv->busy;
1864
1865out_unlock:
0206e353 1866 spin_unlock(&mchdev_lock);
7648fa99 1867
0206e353 1868 return ret;
7648fa99
JB		 1869}
1870EXPORT_SYMBOL_GPL(i915_gpu_busy);
1871
1872/**
1873 * i915_gpu_turbo_disable - disable graphics turbo
1874 *
1875 * Disable graphics turbo by resetting the max frequency and setting the
1876 * current frequency to the default.
1877 */
1878bool i915_gpu_turbo_disable(void)
1879{
0206e353 1880 struct drm_i915_private *dev_priv;
7648fa99
JB		 1881 bool ret = true;
1882
0206e353 1883 spin_lock(&mchdev_lock);
7648fa99
JB		 1884 if (!i915_mch_dev) {
1885 ret = false;
1886 goto out_unlock;
1887 }
1888 dev_priv = i915_mch_dev;
1889
1890 dev_priv->max_delay = dev_priv->fstart;
1891
1892 if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
1893 ret = false;
1894
1895out_unlock:
0206e353 1896 spin_unlock(&mchdev_lock);
7648fa99 1897
0206e353 1898 return ret;
7648fa99
JB		 1899}
1900EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
1901
63ee41d7
EA		 1902/**
1903 * Tells the intel_ips driver that the i915 driver is now loaded, if
1904 * IPS got loaded first.
1905 *
1906 * This awkward dance is so that neither module has to depend on the
1907 * other in order for IPS to do the appropriate communication of
1908 * GPU turbo limits to i915.
1909 */
1910static void
1911ips_ping_for_i915_load(void)
1912{
1913 void (*link)(void);
1914
1915 link = symbol_get(ips_link_to_i915_driver);
1916 if (link) {
1917 link();
1918 symbol_put(ips_link_to_i915_driver);
1919 }
1920}
1921
e2b665c4
AJ		 1922static void
1923i915_mtrr_setup(struct drm_i915_private *dev_priv, unsigned long base,
1924 unsigned long size)
1925{
23f54bea
CW		 1926 dev_priv->mm.gtt_mtrr = -1;
1927
9e984bc1
AJ		 1928#if defined(CONFIG_X86_PAT)
1929 if (cpu_has_pat)
1930 return;
1931#endif
1932
e2b665c4
AJ		 1933 /* Set up a WC MTRR for non-PAT systems. This is more common than
1934 * one would think, because the kernel disables PAT on first
1935 * generation Core chips because WC PAT gets overridden by a UC
1936 * MTRR if present. Even if a UC MTRR isn't present.
1937 */
1938 dev_priv->mm.gtt_mtrr = mtrr_add(base, size, MTRR_TYPE_WRCOMB, 1);
1939 if (dev_priv->mm.gtt_mtrr < 0) {
1940 DRM_INFO("MTRR allocation failed. Graphics "
1941 "performance may suffer.\n");
1942 }
1943}
1944
79e53945
JB		 1945/**
1946 * i915_driver_load - setup chip and create an initial config
1947 * @dev: DRM device
1948 * @flags: startup flags
1949 *
1950 * The driver load routine has to do several things:
1951 * - drive output discovery via intel_modeset_init()
1952 * - initialize the memory manager
1953 * - allocate initial config memory
1954 * - setup the DRM framebuffer with the allocated memory
1955 */
84b1fd10 1956int i915_driver_load(struct drm_device *dev, unsigned long flags)
22eae947 1957{
ea059a1e 1958 struct drm_i915_private *dev_priv;
cfdf1fa2 1959 int ret = 0, mmio_bar;
9021f284 1960 uint32_t aperture_size;
fe669bf8 1961
22eae947
DA		 1962 /* i915 has 4 more counters */
1963 dev->counters += 4;
1964 dev->types[6] = _DRM_STAT_IRQ;
1965 dev->types[7] = _DRM_STAT_PRIMARY;
1966 dev->types[8] = _DRM_STAT_SECONDARY;
1967 dev->types[9] = _DRM_STAT_DMA;
1968
9a298b2a 1969 dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
ba8bbcf6
JB		 1970 if (dev_priv == NULL)
1971 return -ENOMEM;
1972
ba8bbcf6 1973 dev->dev_private = (void *)dev_priv;
673a394b 1974 dev_priv->dev = dev;
cfdf1fa2 1975 dev_priv->info = (struct intel_device_info *) flags;
ba8bbcf6 1976
ec2a4c3f
DA		 1977 if (i915_get_bridge_dev(dev)) {
1978 ret = -EIO;
1979 goto free_priv;
1980 }
1981
466e69b8
DA		 1982 pci_set_master(dev->pdev);
1983
9f82d238
DV		 1984 /* overlay on gen2 is broken and can't address above 1G */
1985 if (IS_GEN2(dev))
1986 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1987
6927faf3
JN		 1988 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1989 * using 32bit addressing, overwriting memory if HWS is located
1990 * above 4GB.
1991 *
1992 * The documentation also mentions an issue with undefined
1993 * behaviour if any general state is accessed within a page above 4GB,
1994 * which also needs to be handled carefully.
1995 */
1996 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1997 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1998
b4ce0f85
CW		 1999 mmio_bar = IS_GEN2(dev) ? 1 : 0;
2000 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, 0);
2001 if (!dev_priv->regs) {
2002 DRM_ERROR("failed to map registers\n");
2003 ret = -EIO;
2004 goto put_bridge;
2005 }
2006
71e9339c
CW		 2007 dev_priv->mm.gtt = intel_gtt_get();
2008 if (!dev_priv->mm.gtt) {
2009 DRM_ERROR("Failed to initialize GTT\n");
2010 ret = -ENODEV;
a7b85d2a 2011 goto out_rmmap;
71e9339c
CW		 2012 }
2013
9021f284 2014 aperture_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
71e9339c 2015
0206e353 2016 dev_priv->mm.gtt_mapping =
9021f284 2017 io_mapping_create_wc(dev->agp->base, aperture_size);
6644107d
VP		 2018 if (dev_priv->mm.gtt_mapping == NULL) {
2019 ret = -EIO;
2020 goto out_rmmap;
2021 }
2022
9021f284 2023 i915_mtrr_setup(dev_priv, dev->agp->base, aperture_size);
19966754 2024
e642abbf
CW		 2025 /* The i915 workqueue is primarily used for batched retirement of
2026 * requests (and thus managing bo) once the task has been completed
2027 * by the GPU. i915_gem_retire_requests() is called directly when we
2028 * need high-priority retirement, such as waiting for an explicit
2029 * bo.
2030 *
2031 * It is also used for periodic low-priority events, such as
df9c2042 2032 * idle-timers and recording error state.
e642abbf
CW		 2033 *
2034 * All tasks on the workqueue are expected to acquire the dev mutex
2035 * so there is no point in running more than one instance of the
2036 * workqueue at any time: max_active = 1 and NON_REENTRANT.
2037 */
2038 dev_priv->wq = alloc_workqueue("i915",
2039 WQ_UNBOUND | WQ_NON_REENTRANT,
2040 1);
9c9fe1f8
EA		 2041 if (dev_priv->wq == NULL) {
2042 DRM_ERROR("Failed to create our workqueue.\n");
2043 ret = -ENOMEM;
a7b85d2a 2044 goto out_mtrrfree;
9c9fe1f8
EA		 2045 }
2046
ac5c4e76
DA		 2047 /* enable GEM by default */
2048 dev_priv->has_gem = 1;
ac5c4e76 2049
f71d4af4 2050 intel_irq_init(dev);
9880b7a5 2051
c4804411
ZW		 2052 /* Try to make sure MCHBAR is enabled before poking at it */
2053 intel_setup_mchbar(dev);
f899fc64 2054 intel_setup_gmbus(dev);
44834a67 2055 intel_opregion_setup(dev);
c4804411 2056
6d139a87
BF		 2057 /* Make sure the bios did its job and set up vital registers */
2058 intel_setup_bios(dev);
2059
673a394b
EA		 2060 i915_gem_load(dev);
2061
398c9cb2
KP		 2062 /* Init HWS */
2063 if (!I915_NEED_GFX_HWS(dev)) {
2064 ret = i915_init_phys_hws(dev);
56e2ea34
CW		 2065 if (ret)
2066 goto out_gem_unload;
398c9cb2 2067 }
ed4cb414 2068
7648fa99
JB		 2069 if (IS_PINEVIEW(dev))
2070 i915_pineview_get_mem_freq(dev);
f00a3ddf 2071 else if (IS_GEN5(dev))
7648fa99 2072 i915_ironlake_get_mem_freq(dev);
7662c8bd 2073
ed4cb414
EA		 2074 /* On the 945G/GM, the chipset reports the MSI capability on the
2075 * integrated graphics even though the support isn't actually there
2076 * according to the published specs. It doesn't appear to function
2077 * correctly in testing on 945G.
2078 * This may be a side effect of MSI having been made available for PEG
2079 * and the registers being closely associated.
d1ed629f
KP		 2080 *
2081 * According to chipset errata, on the 965GM, MSI interrupts may
b60678a7
KP		 2082 * be lost or delayed, but we use them anyways to avoid
2083 * stuck interrupts on some machines.
ed4cb414 2084 */
b60678a7 2085 if (!IS_I945G(dev) && !IS_I945GM(dev))
d3e74d02 2086 pci_enable_msi(dev->pdev);
ed4cb414 2087
9f1f46a4 2088 spin_lock_init(&dev_priv->gt_lock);
1ec14ad3 2089 spin_lock_init(&dev_priv->irq_lock);
63eeaf38 2090 spin_lock_init(&dev_priv->error_lock);
4912d041 2091 spin_lock_init(&dev_priv->rps_lock);
ed4cb414 2092
27f8227b
JB		 2093 if (IS_IVYBRIDGE(dev))
2094 dev_priv->num_pipe = 3;
2095 else if (IS_MOBILE(dev) || !IS_GEN2(dev))
9db4a9c7
JB		 2096 dev_priv->num_pipe = 2;
2097 else
2098 dev_priv->num_pipe = 1;
2099
2100 ret = drm_vblank_init(dev, dev_priv->num_pipe);
56e2ea34
CW		 2101 if (ret)
2102 goto out_gem_unload;
52440211 2103
11ed50ec
BG		 2104 /* Start out suspended */
2105 dev_priv->mm.suspended = 1;
2106
3bad0781
ZW		 2107 intel_detect_pch(dev);
2108
79e53945 2109 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
53984635 2110 ret = i915_load_modeset_init(dev);
79e53945
JB		 2111 if (ret < 0) {
2112 DRM_ERROR("failed to init modeset\n");
56e2ea34 2113 goto out_gem_unload;
79e53945
JB		 2114 }
2115 }
2116
74a365b3 2117 /* Must be done after probing outputs */
44834a67
CW		 2118 intel_opregion_init(dev);
2119 acpi_video_register();
74a365b3 2120
f65d9421
BG		 2121 setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
2122 (unsigned long) dev);
7648fa99
JB		 2123
2124 spin_lock(&mchdev_lock);
2125 i915_mch_dev = dev_priv;
2126 dev_priv->mchdev_lock = &mchdev_lock;
2127 spin_unlock(&mchdev_lock);
2128
63ee41d7
EA		 2129 ips_ping_for_i915_load();
2130
79e53945
JB		 2131 return 0;
2132
56e2ea34 2133out_gem_unload:
a7b85d2a
KP		 2134 if (dev_priv->mm.inactive_shrinker.shrink)
2135 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
2136
56e2ea34
CW		 2137 if (dev->pdev->msi_enabled)
2138 pci_disable_msi(dev->pdev);
2139
2140 intel_teardown_gmbus(dev);
2141 intel_teardown_mchbar(dev);
9c9fe1f8 2142 destroy_workqueue(dev_priv->wq);
a7b85d2a
KP		 2143out_mtrrfree:
2144 if (dev_priv->mm.gtt_mtrr >= 0) {
2145 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2146 dev->agp->agp_info.aper_size * 1024 * 1024);
2147 dev_priv->mm.gtt_mtrr = -1;
2148 }
6644107d 2149 io_mapping_free(dev_priv->mm.gtt_mapping);
79e53945 2150out_rmmap:
6dda569f 2151 pci_iounmap(dev->pdev, dev_priv->regs);
ec2a4c3f
DA		 2152put_bridge:
2153 pci_dev_put(dev_priv->bridge_dev);
79e53945 2154free_priv:
9a298b2a 2155 kfree(dev_priv);
ba8bbcf6
JB		 2156 return ret;
2157}
2158
2159int i915_driver_unload(struct drm_device *dev)
2160{
2161 struct drm_i915_private *dev_priv = dev->dev_private;
c911fc1c 2162 int ret;
ba8bbcf6 2163
7648fa99
JB		 2164 spin_lock(&mchdev_lock);
2165 i915_mch_dev = NULL;
2166 spin_unlock(&mchdev_lock);
2167
17250b71
CW		 2168 if (dev_priv->mm.inactive_shrinker.shrink)
2169 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
2170
c911fc1c 2171 mutex_lock(&dev->struct_mutex);
b93f9cf1 2172 ret = i915_gpu_idle(dev, true);
c911fc1c
DV		 2173 if (ret)
2174 DRM_ERROR("failed to idle hardware: %d\n", ret);
2175 mutex_unlock(&dev->struct_mutex);
2176
75ef9da2
DV		 2177 /* Cancel the retire work handler, which should be idle now. */
2178 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2179
ab657db1
EA		 2180 io_mapping_free(dev_priv->mm.gtt_mapping);
2181 if (dev_priv->mm.gtt_mtrr >= 0) {
2182 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2183 dev->agp->agp_info.aper_size * 1024 * 1024);
2184 dev_priv->mm.gtt_mtrr = -1;
2185 }
2186
44834a67
CW		 2187 acpi_video_unregister();
2188
79e53945 2189 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
7b4f3990 2190 intel_fbdev_fini(dev);
3d8620cc
JB		 2191 intel_modeset_cleanup(dev);
2192
6363ee6f
ZY		 2193 /*
2194 * free the memory space allocated for the child device
2195 * config parsed from VBT
2196 */
2197 if (dev_priv->child_dev && dev_priv->child_dev_num) {
2198 kfree(dev_priv->child_dev);
2199 dev_priv->child_dev = NULL;
2200 dev_priv->child_dev_num = 0;
2201 }
6c0d9350 2202
6a9ee8af 2203 vga_switcheroo_unregister_client(dev->pdev);
28d52043 2204 vga_client_register(dev->pdev, NULL, NULL, NULL);
79e53945
JB		 2205 }
2206
a8b4899e 2207 /* Free error state after interrupts are fully disabled. */
bc0c7f14
DV		 2208 del_timer_sync(&dev_priv->hangcheck_timer);
2209 cancel_work_sync(&dev_priv->error_work);
a8b4899e 2210 i915_destroy_error_state(dev);
bc0c7f14 2211
ed4cb414
EA		 2212 if (dev->pdev->msi_enabled)
2213 pci_disable_msi(dev->pdev);
2214
44834a67 2215 intel_opregion_fini(dev);
8ee1c3db 2216
79e53945 2217 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
67e77c5a
DV		 2218 /* Flush any outstanding unpin_work. */
2219 flush_workqueue(dev_priv->wq);
2220
79e53945 2221 mutex_lock(&dev->struct_mutex);
ecbec53b 2222 i915_gem_free_all_phys_object(dev);
79e53945
JB		 2223 i915_gem_cleanup_ringbuffer(dev);
2224 mutex_unlock(&dev->struct_mutex);
1d2a314c 2225 i915_gem_cleanup_aliasing_ppgtt(dev);
20bf377e
JB		 2226 if (I915_HAS_FBC(dev) && i915_powersave)
2227 i915_cleanup_compression(dev);
fe669bf8 2228 drm_mm_takedown(&dev_priv->mm.stolen);
02e792fb
DV		 2229
2230 intel_cleanup_overlay(dev);
c2873e96
KP		 2231
2232 if (!I915_NEED_GFX_HWS(dev))
2233 i915_free_hws(dev);
79e53945
JB		 2234 }
2235
701394cc 2236 if (dev_priv->regs != NULL)
6dda569f 2237 pci_iounmap(dev->pdev, dev_priv->regs);
701394cc 2238
f899fc64 2239 intel_teardown_gmbus(dev);
c4804411
ZW		 2240 intel_teardown_mchbar(dev);
2241
bc0c7f14
DV		 2242 destroy_workqueue(dev_priv->wq);
2243
ec2a4c3f 2244 pci_dev_put(dev_priv->bridge_dev);
9a298b2a 2245 kfree(dev->dev_private);
ba8bbcf6 2246
22eae947
DA		 2247 return 0;
2248}
2249
f787a5f5 2250int i915_driver_open(struct drm_device *dev, struct drm_file *file)
673a394b 2251{
f787a5f5 2252 struct drm_i915_file_private *file_priv;
673a394b 2253
8a4c47f3 2254 DRM_DEBUG_DRIVER("\n");
f787a5f5
CW		 2255 file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL);
2256 if (!file_priv)
673a394b
EA		 2257 return -ENOMEM;
2258
f787a5f5 2259 file->driver_priv = file_priv;
673a394b 2260
1c25595f 2261 spin_lock_init(&file_priv->mm.lock);
f787a5f5 2262 INIT_LIST_HEAD(&file_priv->mm.request_list);
673a394b
EA		 2263
2264 return 0;
2265}
2266
79e53945
JB		 2267/**
2268 * i915_driver_lastclose - clean up after all DRM clients have exited
2269 * @dev: DRM device
2270 *
2271 * Take care of cleaning up after all DRM clients have exited. In the
2272 * mode setting case, we want to restore the kernel's initial mode (just
2273 * in case the last client left us in a bad state).
2274 *
9021f284 2275 * Additionally, in the non-mode setting case, we'll tear down the GTT
79e53945
JB		 2276 * and DMA structures, since the kernel won't be using them, and clea
2277 * up any GEM state.
2278 */
84b1fd10 2279void i915_driver_lastclose(struct drm_device * dev)
1da177e4 2280{
ba8bbcf6
JB		 2281 drm_i915_private_t *dev_priv = dev->dev_private;
2282
79e53945 2283 if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
e8e7a2b8 2284 intel_fb_restore_mode(dev);
6a9ee8af 2285 vga_switcheroo_process_delayed_switch();
144a75fa 2286 return;
79e53945 2287 }
144a75fa 2288
673a394b
EA		 2289 i915_gem_lastclose(dev);
2290
b5e89ed5 2291 i915_dma_cleanup(dev);
1da177e4
LT		 2292}
2293
6c340eac 2294void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1da177e4 2295{
b962442e 2296 i915_gem_release(dev, file_priv);
1da177e4
LT		 2297}
2298
f787a5f5 2299void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
673a394b 2300{
f787a5f5 2301 struct drm_i915_file_private *file_priv = file->driver_priv;
673a394b 2302
f787a5f5 2303 kfree(file_priv);
673a394b
EA		 2304}
2305
c153f45f 2306struct drm_ioctl_desc i915_ioctls[] = {
1b2f1489
DA		 2307 DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2308 DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2309 DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
2310 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2311 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2312 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2313 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
2314 DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
b2c606fe
DV		 2315 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2316 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2317 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1b2f1489 2318 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
b2c606fe 2319 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1b2f1489
DA		 2320 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2321 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH),
2322 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2323 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2324 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2325 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2326 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
2327 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2328 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2329 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
2330 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
2331 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2332 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2333 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
2334 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
2335 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
2336 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
2337 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
2338 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
2339 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
2340 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
2341 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
2342 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
2343 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2344 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
2345 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2346 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
8ea30864
JB		 2347 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2348 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
c94f7029
DA		 2349};
2350
2351int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
cda17380 2352
9021f284
DV		 2353/*
2354 * This is really ugly: Because old userspace abused the linux agp interface to
2355 * manage the gtt, we need to claim that all intel devices are agp. For
2356 * otherwise the drm core refuses to initialize the agp support code.
cda17380 2357 */
84b1fd10 2358int i915_driver_device_is_agp(struct drm_device * dev)
cda17380
DA		 2359{
2360 return 1;
2361}
Linux 6.x block layer and io_uring tree(s)