Commit | Line | Data |
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1da177e4 LT |
1 | /* i915_dma.c -- DMA support for the I915 -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 LT |
28 | |
29 | #include "drmP.h" | |
30 | #include "drm.h" | |
79e53945 | 31 | #include "drm_crtc_helper.h" |
785b93ef | 32 | #include "drm_fb_helper.h" |
79e53945 | 33 | #include "intel_drv.h" |
1da177e4 LT |
34 | #include "i915_drm.h" |
35 | #include "i915_drv.h" | |
1c5d22f7 | 36 | #include "i915_trace.h" |
28d52043 | 37 | #include <linux/vgaarb.h> |
1da177e4 | 38 | |
1da177e4 LT |
39 | /* Really want an OS-independent resettable timer. Would like to have |
40 | * this loop run for (eg) 3 sec, but have the timer reset every time | |
41 | * the head pointer changes, so that EBUSY only happens if the ring | |
42 | * actually stalls for (eg) 3 seconds. | |
43 | */ | |
84b1fd10 | 44 | int i915_wait_ring(struct drm_device * dev, int n, const char *caller) |
1da177e4 LT |
45 | { |
46 | drm_i915_private_t *dev_priv = dev->dev_private; | |
47 | drm_i915_ring_buffer_t *ring = &(dev_priv->ring); | |
d3a6d446 KP |
48 | u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD; |
49 | u32 last_acthd = I915_READ(acthd_reg); | |
50 | u32 acthd; | |
585fb111 | 51 | u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
1da177e4 LT |
52 | int i; |
53 | ||
1c5d22f7 CW |
54 | trace_i915_ring_wait_begin (dev); |
55 | ||
d3a6d446 | 56 | for (i = 0; i < 100000; i++) { |
585fb111 | 57 | ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
d3a6d446 | 58 | acthd = I915_READ(acthd_reg); |
1da177e4 LT |
59 | ring->space = ring->head - (ring->tail + 8); |
60 | if (ring->space < 0) | |
61 | ring->space += ring->Size; | |
1c5d22f7 CW |
62 | if (ring->space >= n) { |
63 | trace_i915_ring_wait_end (dev); | |
1da177e4 | 64 | return 0; |
1c5d22f7 | 65 | } |
1da177e4 | 66 | |
98787c05 CW |
67 | if (dev->primary->master) { |
68 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; | |
69 | if (master_priv->sarea_priv) | |
70 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
71 | } | |
72 | ||
1da177e4 LT |
73 | |
74 | if (ring->head != last_head) | |
75 | i = 0; | |
d3a6d446 KP |
76 | if (acthd != last_acthd) |
77 | i = 0; | |
1da177e4 LT |
78 | |
79 | last_head = ring->head; | |
d3a6d446 KP |
80 | last_acthd = acthd; |
81 | msleep_interruptible(10); | |
82 | ||
1da177e4 LT |
83 | } |
84 | ||
1c5d22f7 | 85 | trace_i915_ring_wait_end (dev); |
20caafa6 | 86 | return -EBUSY; |
1da177e4 LT |
87 | } |
88 | ||
0ef82af7 CW |
89 | /* As a ringbuffer is only allowed to wrap between instructions, fill |
90 | * the tail with NOOPs. | |
91 | */ | |
92 | int i915_wrap_ring(struct drm_device *dev) | |
93 | { | |
94 | drm_i915_private_t *dev_priv = dev->dev_private; | |
95 | volatile unsigned int *virt; | |
96 | int rem; | |
97 | ||
98 | rem = dev_priv->ring.Size - dev_priv->ring.tail; | |
99 | if (dev_priv->ring.space < rem) { | |
100 | int ret = i915_wait_ring(dev, rem, __func__); | |
101 | if (ret) | |
102 | return ret; | |
103 | } | |
104 | dev_priv->ring.space -= rem; | |
105 | ||
106 | virt = (unsigned int *) | |
107 | (dev_priv->ring.virtual_start + dev_priv->ring.tail); | |
108 | rem /= 4; | |
109 | while (rem--) | |
110 | *virt++ = MI_NOOP; | |
111 | ||
112 | dev_priv->ring.tail = 0; | |
113 | ||
114 | return 0; | |
115 | } | |
116 | ||
398c9cb2 KP |
117 | /** |
118 | * Sets up the hardware status page for devices that need a physical address | |
119 | * in the register. | |
120 | */ | |
3043c60c | 121 | static int i915_init_phys_hws(struct drm_device *dev) |
398c9cb2 KP |
122 | { |
123 | drm_i915_private_t *dev_priv = dev->dev_private; | |
124 | /* Program Hardware Status Page */ | |
125 | dev_priv->status_page_dmah = | |
e6be8d9d | 126 | drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE); |
398c9cb2 KP |
127 | |
128 | if (!dev_priv->status_page_dmah) { | |
129 | DRM_ERROR("Can not allocate hardware status page\n"); | |
130 | return -ENOMEM; | |
131 | } | |
132 | dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr; | |
133 | dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr; | |
134 | ||
135 | memset(dev_priv->hw_status_page, 0, PAGE_SIZE); | |
136 | ||
9b974cc1 ZW |
137 | if (IS_I965G(dev)) |
138 | dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) & | |
139 | 0xf0; | |
140 | ||
398c9cb2 | 141 | I915_WRITE(HWS_PGA, dev_priv->dma_status_page); |
8a4c47f3 | 142 | DRM_DEBUG_DRIVER("Enabled hardware status page\n"); |
398c9cb2 KP |
143 | return 0; |
144 | } | |
145 | ||
146 | /** | |
147 | * Frees the hardware status page, whether it's a physical address or a virtual | |
148 | * address set up by the X Server. | |
149 | */ | |
3043c60c | 150 | static void i915_free_hws(struct drm_device *dev) |
398c9cb2 KP |
151 | { |
152 | drm_i915_private_t *dev_priv = dev->dev_private; | |
153 | if (dev_priv->status_page_dmah) { | |
154 | drm_pci_free(dev, dev_priv->status_page_dmah); | |
155 | dev_priv->status_page_dmah = NULL; | |
156 | } | |
157 | ||
158 | if (dev_priv->status_gfx_addr) { | |
159 | dev_priv->status_gfx_addr = 0; | |
160 | drm_core_ioremapfree(&dev_priv->hws_map, dev); | |
161 | } | |
162 | ||
163 | /* Need to rewrite hardware status page */ | |
164 | I915_WRITE(HWS_PGA, 0x1ffff000); | |
165 | } | |
166 | ||
84b1fd10 | 167 | void i915_kernel_lost_context(struct drm_device * dev) |
1da177e4 LT |
168 | { |
169 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 170 | struct drm_i915_master_private *master_priv; |
1da177e4 LT |
171 | drm_i915_ring_buffer_t *ring = &(dev_priv->ring); |
172 | ||
79e53945 JB |
173 | /* |
174 | * We should never lose context on the ring with modesetting | |
175 | * as we don't expose it to userspace | |
176 | */ | |
177 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
178 | return; | |
179 | ||
585fb111 JB |
180 | ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
181 | ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR; | |
1da177e4 LT |
182 | ring->space = ring->head - (ring->tail + 8); |
183 | if (ring->space < 0) | |
184 | ring->space += ring->Size; | |
185 | ||
7c1c2871 DA |
186 | if (!dev->primary->master) |
187 | return; | |
188 | ||
189 | master_priv = dev->primary->master->driver_priv; | |
190 | if (ring->head == ring->tail && master_priv->sarea_priv) | |
191 | master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY; | |
1da177e4 LT |
192 | } |
193 | ||
84b1fd10 | 194 | static int i915_dma_cleanup(struct drm_device * dev) |
1da177e4 | 195 | { |
ba8bbcf6 | 196 | drm_i915_private_t *dev_priv = dev->dev_private; |
1da177e4 LT |
197 | /* Make sure interrupts are disabled here because the uninstall ioctl |
198 | * may not have been called from userspace and after dev_private | |
199 | * is freed, it's too late. | |
200 | */ | |
ed4cb414 | 201 | if (dev->irq_enabled) |
b5e89ed5 | 202 | drm_irq_uninstall(dev); |
1da177e4 | 203 | |
ba8bbcf6 JB |
204 | if (dev_priv->ring.virtual_start) { |
205 | drm_core_ioremapfree(&dev_priv->ring.map, dev); | |
3043c60c EA |
206 | dev_priv->ring.virtual_start = NULL; |
207 | dev_priv->ring.map.handle = NULL; | |
ba8bbcf6 JB |
208 | dev_priv->ring.map.size = 0; |
209 | } | |
dc7a9319 | 210 | |
398c9cb2 KP |
211 | /* Clear the HWS virtual address at teardown */ |
212 | if (I915_NEED_GFX_HWS(dev)) | |
213 | i915_free_hws(dev); | |
1da177e4 LT |
214 | |
215 | return 0; | |
216 | } | |
217 | ||
ba8bbcf6 | 218 | static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) |
1da177e4 | 219 | { |
ba8bbcf6 | 220 | drm_i915_private_t *dev_priv = dev->dev_private; |
7c1c2871 | 221 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 222 | |
3a03ac1a DA |
223 | master_priv->sarea = drm_getsarea(dev); |
224 | if (master_priv->sarea) { | |
225 | master_priv->sarea_priv = (drm_i915_sarea_t *) | |
226 | ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset); | |
227 | } else { | |
8a4c47f3 | 228 | DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n"); |
3a03ac1a DA |
229 | } |
230 | ||
673a394b EA |
231 | if (init->ring_size != 0) { |
232 | if (dev_priv->ring.ring_obj != NULL) { | |
233 | i915_dma_cleanup(dev); | |
234 | DRM_ERROR("Client tried to initialize ringbuffer in " | |
235 | "GEM mode\n"); | |
236 | return -EINVAL; | |
237 | } | |
1da177e4 | 238 | |
673a394b | 239 | dev_priv->ring.Size = init->ring_size; |
1da177e4 | 240 | |
673a394b EA |
241 | dev_priv->ring.map.offset = init->ring_start; |
242 | dev_priv->ring.map.size = init->ring_size; | |
243 | dev_priv->ring.map.type = 0; | |
244 | dev_priv->ring.map.flags = 0; | |
245 | dev_priv->ring.map.mtrr = 0; | |
1da177e4 | 246 | |
6fb88588 | 247 | drm_core_ioremap_wc(&dev_priv->ring.map, dev); |
673a394b EA |
248 | |
249 | if (dev_priv->ring.map.handle == NULL) { | |
250 | i915_dma_cleanup(dev); | |
251 | DRM_ERROR("can not ioremap virtual address for" | |
252 | " ring buffer\n"); | |
253 | return -ENOMEM; | |
254 | } | |
1da177e4 LT |
255 | } |
256 | ||
257 | dev_priv->ring.virtual_start = dev_priv->ring.map.handle; | |
258 | ||
a6b54f3f | 259 | dev_priv->cpp = init->cpp; |
1da177e4 LT |
260 | dev_priv->back_offset = init->back_offset; |
261 | dev_priv->front_offset = init->front_offset; | |
262 | dev_priv->current_page = 0; | |
7c1c2871 DA |
263 | if (master_priv->sarea_priv) |
264 | master_priv->sarea_priv->pf_current_page = 0; | |
1da177e4 | 265 | |
1da177e4 LT |
266 | /* Allow hardware batchbuffers unless told otherwise. |
267 | */ | |
268 | dev_priv->allow_batchbuffer = 1; | |
269 | ||
1da177e4 LT |
270 | return 0; |
271 | } | |
272 | ||
84b1fd10 | 273 | static int i915_dma_resume(struct drm_device * dev) |
1da177e4 LT |
274 | { |
275 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
276 | ||
8a4c47f3 | 277 | DRM_DEBUG_DRIVER("%s\n", __func__); |
1da177e4 | 278 | |
1da177e4 LT |
279 | if (dev_priv->ring.map.handle == NULL) { |
280 | DRM_ERROR("can not ioremap virtual address for" | |
281 | " ring buffer\n"); | |
20caafa6 | 282 | return -ENOMEM; |
1da177e4 LT |
283 | } |
284 | ||
285 | /* Program Hardware Status Page */ | |
286 | if (!dev_priv->hw_status_page) { | |
287 | DRM_ERROR("Can not find hardware status page\n"); | |
20caafa6 | 288 | return -EINVAL; |
1da177e4 | 289 | } |
8a4c47f3 | 290 | DRM_DEBUG_DRIVER("hw status page @ %p\n", |
be25ed9c | 291 | dev_priv->hw_status_page); |
1da177e4 | 292 | |
dc7a9319 | 293 | if (dev_priv->status_gfx_addr != 0) |
585fb111 | 294 | I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); |
dc7a9319 | 295 | else |
585fb111 | 296 | I915_WRITE(HWS_PGA, dev_priv->dma_status_page); |
8a4c47f3 | 297 | DRM_DEBUG_DRIVER("Enabled hardware status page\n"); |
1da177e4 LT |
298 | |
299 | return 0; | |
300 | } | |
301 | ||
c153f45f EA |
302 | static int i915_dma_init(struct drm_device *dev, void *data, |
303 | struct drm_file *file_priv) | |
1da177e4 | 304 | { |
c153f45f | 305 | drm_i915_init_t *init = data; |
1da177e4 LT |
306 | int retcode = 0; |
307 | ||
c153f45f | 308 | switch (init->func) { |
1da177e4 | 309 | case I915_INIT_DMA: |
ba8bbcf6 | 310 | retcode = i915_initialize(dev, init); |
1da177e4 LT |
311 | break; |
312 | case I915_CLEANUP_DMA: | |
313 | retcode = i915_dma_cleanup(dev); | |
314 | break; | |
315 | case I915_RESUME_DMA: | |
0d6aa60b | 316 | retcode = i915_dma_resume(dev); |
1da177e4 LT |
317 | break; |
318 | default: | |
20caafa6 | 319 | retcode = -EINVAL; |
1da177e4 LT |
320 | break; |
321 | } | |
322 | ||
323 | return retcode; | |
324 | } | |
325 | ||
326 | /* Implement basically the same security restrictions as hardware does | |
327 | * for MI_BATCH_NON_SECURE. These can be made stricter at any time. | |
328 | * | |
329 | * Most of the calculations below involve calculating the size of a | |
330 | * particular instruction. It's important to get the size right as | |
331 | * that tells us where the next instruction to check is. Any illegal | |
332 | * instruction detected will be given a size of zero, which is a | |
333 | * signal to abort the rest of the buffer. | |
334 | */ | |
335 | static int do_validate_cmd(int cmd) | |
336 | { | |
337 | switch (((cmd >> 29) & 0x7)) { | |
338 | case 0x0: | |
339 | switch ((cmd >> 23) & 0x3f) { | |
340 | case 0x0: | |
341 | return 1; /* MI_NOOP */ | |
342 | case 0x4: | |
343 | return 1; /* MI_FLUSH */ | |
344 | default: | |
345 | return 0; /* disallow everything else */ | |
346 | } | |
347 | break; | |
348 | case 0x1: | |
349 | return 0; /* reserved */ | |
350 | case 0x2: | |
351 | return (cmd & 0xff) + 2; /* 2d commands */ | |
352 | case 0x3: | |
353 | if (((cmd >> 24) & 0x1f) <= 0x18) | |
354 | return 1; | |
355 | ||
356 | switch ((cmd >> 24) & 0x1f) { | |
357 | case 0x1c: | |
358 | return 1; | |
359 | case 0x1d: | |
b5e89ed5 | 360 | switch ((cmd >> 16) & 0xff) { |
1da177e4 LT |
361 | case 0x3: |
362 | return (cmd & 0x1f) + 2; | |
363 | case 0x4: | |
364 | return (cmd & 0xf) + 2; | |
365 | default: | |
366 | return (cmd & 0xffff) + 2; | |
367 | } | |
368 | case 0x1e: | |
369 | if (cmd & (1 << 23)) | |
370 | return (cmd & 0xffff) + 1; | |
371 | else | |
372 | return 1; | |
373 | case 0x1f: | |
374 | if ((cmd & (1 << 23)) == 0) /* inline vertices */ | |
375 | return (cmd & 0x1ffff) + 2; | |
376 | else if (cmd & (1 << 17)) /* indirect random */ | |
377 | if ((cmd & 0xffff) == 0) | |
378 | return 0; /* unknown length, too hard */ | |
379 | else | |
380 | return (((cmd & 0xffff) + 1) / 2) + 1; | |
381 | else | |
382 | return 2; /* indirect sequential */ | |
383 | default: | |
384 | return 0; | |
385 | } | |
386 | default: | |
387 | return 0; | |
388 | } | |
389 | ||
390 | return 0; | |
391 | } | |
392 | ||
393 | static int validate_cmd(int cmd) | |
394 | { | |
395 | int ret = do_validate_cmd(cmd); | |
396 | ||
bc5f4523 | 397 | /* printk("validate_cmd( %x ): %d\n", cmd, ret); */ |
1da177e4 LT |
398 | |
399 | return ret; | |
400 | } | |
401 | ||
201361a5 | 402 | static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords) |
1da177e4 LT |
403 | { |
404 | drm_i915_private_t *dev_priv = dev->dev_private; | |
405 | int i; | |
406 | RING_LOCALS; | |
407 | ||
de227f5f | 408 | if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8) |
20caafa6 | 409 | return -EINVAL; |
de227f5f | 410 | |
c29b669c | 411 | BEGIN_LP_RING((dwords+1)&~1); |
de227f5f | 412 | |
1da177e4 LT |
413 | for (i = 0; i < dwords;) { |
414 | int cmd, sz; | |
415 | ||
201361a5 | 416 | cmd = buffer[i]; |
1da177e4 | 417 | |
1da177e4 | 418 | if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords) |
20caafa6 | 419 | return -EINVAL; |
1da177e4 | 420 | |
1da177e4 LT |
421 | OUT_RING(cmd); |
422 | ||
423 | while (++i, --sz) { | |
201361a5 | 424 | OUT_RING(buffer[i]); |
1da177e4 | 425 | } |
1da177e4 LT |
426 | } |
427 | ||
de227f5f DA |
428 | if (dwords & 1) |
429 | OUT_RING(0); | |
430 | ||
431 | ADVANCE_LP_RING(); | |
432 | ||
1da177e4 LT |
433 | return 0; |
434 | } | |
435 | ||
673a394b EA |
436 | int |
437 | i915_emit_box(struct drm_device *dev, | |
201361a5 | 438 | struct drm_clip_rect *boxes, |
673a394b | 439 | int i, int DR1, int DR4) |
1da177e4 LT |
440 | { |
441 | drm_i915_private_t *dev_priv = dev->dev_private; | |
201361a5 | 442 | struct drm_clip_rect box = boxes[i]; |
1da177e4 LT |
443 | RING_LOCALS; |
444 | ||
1da177e4 LT |
445 | if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) { |
446 | DRM_ERROR("Bad box %d,%d..%d,%d\n", | |
447 | box.x1, box.y1, box.x2, box.y2); | |
20caafa6 | 448 | return -EINVAL; |
1da177e4 LT |
449 | } |
450 | ||
c29b669c AH |
451 | if (IS_I965G(dev)) { |
452 | BEGIN_LP_RING(4); | |
453 | OUT_RING(GFX_OP_DRAWRECT_INFO_I965); | |
454 | OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); | |
78eca43d | 455 | OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); |
c29b669c AH |
456 | OUT_RING(DR4); |
457 | ADVANCE_LP_RING(); | |
458 | } else { | |
459 | BEGIN_LP_RING(6); | |
460 | OUT_RING(GFX_OP_DRAWRECT_INFO); | |
461 | OUT_RING(DR1); | |
462 | OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); | |
463 | OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); | |
464 | OUT_RING(DR4); | |
465 | OUT_RING(0); | |
466 | ADVANCE_LP_RING(); | |
467 | } | |
1da177e4 LT |
468 | |
469 | return 0; | |
470 | } | |
471 | ||
c29b669c AH |
472 | /* XXX: Emitting the counter should really be moved to part of the IRQ |
473 | * emit. For now, do it in both places: | |
474 | */ | |
475 | ||
84b1fd10 | 476 | static void i915_emit_breadcrumb(struct drm_device *dev) |
de227f5f DA |
477 | { |
478 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 479 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
de227f5f DA |
480 | RING_LOCALS; |
481 | ||
c99b058f | 482 | dev_priv->counter++; |
af6061af | 483 | if (dev_priv->counter > 0x7FFFFFFFUL) |
c99b058f | 484 | dev_priv->counter = 0; |
7c1c2871 DA |
485 | if (master_priv->sarea_priv) |
486 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; | |
de227f5f DA |
487 | |
488 | BEGIN_LP_RING(4); | |
585fb111 | 489 | OUT_RING(MI_STORE_DWORD_INDEX); |
0baf823a | 490 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
de227f5f DA |
491 | OUT_RING(dev_priv->counter); |
492 | OUT_RING(0); | |
493 | ADVANCE_LP_RING(); | |
494 | } | |
495 | ||
84b1fd10 | 496 | static int i915_dispatch_cmdbuffer(struct drm_device * dev, |
201361a5 EA |
497 | drm_i915_cmdbuffer_t *cmd, |
498 | struct drm_clip_rect *cliprects, | |
499 | void *cmdbuf) | |
1da177e4 LT |
500 | { |
501 | int nbox = cmd->num_cliprects; | |
502 | int i = 0, count, ret; | |
503 | ||
504 | if (cmd->sz & 0x3) { | |
505 | DRM_ERROR("alignment"); | |
20caafa6 | 506 | return -EINVAL; |
1da177e4 LT |
507 | } |
508 | ||
509 | i915_kernel_lost_context(dev); | |
510 | ||
511 | count = nbox ? nbox : 1; | |
512 | ||
513 | for (i = 0; i < count; i++) { | |
514 | if (i < nbox) { | |
201361a5 | 515 | ret = i915_emit_box(dev, cliprects, i, |
1da177e4 LT |
516 | cmd->DR1, cmd->DR4); |
517 | if (ret) | |
518 | return ret; | |
519 | } | |
520 | ||
201361a5 | 521 | ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4); |
1da177e4 LT |
522 | if (ret) |
523 | return ret; | |
524 | } | |
525 | ||
de227f5f | 526 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
527 | return 0; |
528 | } | |
529 | ||
84b1fd10 | 530 | static int i915_dispatch_batchbuffer(struct drm_device * dev, |
201361a5 EA |
531 | drm_i915_batchbuffer_t * batch, |
532 | struct drm_clip_rect *cliprects) | |
1da177e4 LT |
533 | { |
534 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1da177e4 LT |
535 | int nbox = batch->num_cliprects; |
536 | int i = 0, count; | |
537 | RING_LOCALS; | |
538 | ||
539 | if ((batch->start | batch->used) & 0x7) { | |
540 | DRM_ERROR("alignment"); | |
20caafa6 | 541 | return -EINVAL; |
1da177e4 LT |
542 | } |
543 | ||
544 | i915_kernel_lost_context(dev); | |
545 | ||
546 | count = nbox ? nbox : 1; | |
547 | ||
548 | for (i = 0; i < count; i++) { | |
549 | if (i < nbox) { | |
201361a5 | 550 | int ret = i915_emit_box(dev, cliprects, i, |
1da177e4 LT |
551 | batch->DR1, batch->DR4); |
552 | if (ret) | |
553 | return ret; | |
554 | } | |
555 | ||
0790d5e1 | 556 | if (!IS_I830(dev) && !IS_845G(dev)) { |
1da177e4 | 557 | BEGIN_LP_RING(2); |
21f16289 DA |
558 | if (IS_I965G(dev)) { |
559 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965); | |
560 | OUT_RING(batch->start); | |
561 | } else { | |
562 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6)); | |
563 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
564 | } | |
1da177e4 LT |
565 | ADVANCE_LP_RING(); |
566 | } else { | |
567 | BEGIN_LP_RING(4); | |
568 | OUT_RING(MI_BATCH_BUFFER); | |
569 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
570 | OUT_RING(batch->start + batch->used - 4); | |
571 | OUT_RING(0); | |
572 | ADVANCE_LP_RING(); | |
573 | } | |
574 | } | |
575 | ||
de227f5f | 576 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
577 | |
578 | return 0; | |
579 | } | |
580 | ||
af6061af | 581 | static int i915_dispatch_flip(struct drm_device * dev) |
1da177e4 LT |
582 | { |
583 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 DA |
584 | struct drm_i915_master_private *master_priv = |
585 | dev->primary->master->driver_priv; | |
1da177e4 LT |
586 | RING_LOCALS; |
587 | ||
7c1c2871 | 588 | if (!master_priv->sarea_priv) |
c99b058f KH |
589 | return -EINVAL; |
590 | ||
8a4c47f3 | 591 | DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n", |
be25ed9c | 592 | __func__, |
593 | dev_priv->current_page, | |
594 | master_priv->sarea_priv->pf_current_page); | |
1da177e4 | 595 | |
af6061af DA |
596 | i915_kernel_lost_context(dev); |
597 | ||
598 | BEGIN_LP_RING(2); | |
585fb111 | 599 | OUT_RING(MI_FLUSH | MI_READ_FLUSH); |
af6061af DA |
600 | OUT_RING(0); |
601 | ADVANCE_LP_RING(); | |
1da177e4 | 602 | |
af6061af DA |
603 | BEGIN_LP_RING(6); |
604 | OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP); | |
605 | OUT_RING(0); | |
606 | if (dev_priv->current_page == 0) { | |
607 | OUT_RING(dev_priv->back_offset); | |
608 | dev_priv->current_page = 1; | |
1da177e4 | 609 | } else { |
af6061af DA |
610 | OUT_RING(dev_priv->front_offset); |
611 | dev_priv->current_page = 0; | |
1da177e4 | 612 | } |
af6061af DA |
613 | OUT_RING(0); |
614 | ADVANCE_LP_RING(); | |
1da177e4 | 615 | |
af6061af DA |
616 | BEGIN_LP_RING(2); |
617 | OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP); | |
618 | OUT_RING(0); | |
619 | ADVANCE_LP_RING(); | |
1da177e4 | 620 | |
7c1c2871 | 621 | master_priv->sarea_priv->last_enqueue = dev_priv->counter++; |
1da177e4 LT |
622 | |
623 | BEGIN_LP_RING(4); | |
585fb111 | 624 | OUT_RING(MI_STORE_DWORD_INDEX); |
0baf823a | 625 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
af6061af DA |
626 | OUT_RING(dev_priv->counter); |
627 | OUT_RING(0); | |
1da177e4 LT |
628 | ADVANCE_LP_RING(); |
629 | ||
7c1c2871 | 630 | master_priv->sarea_priv->pf_current_page = dev_priv->current_page; |
af6061af | 631 | return 0; |
1da177e4 LT |
632 | } |
633 | ||
84b1fd10 | 634 | static int i915_quiescent(struct drm_device * dev) |
1da177e4 LT |
635 | { |
636 | drm_i915_private_t *dev_priv = dev->dev_private; | |
637 | ||
638 | i915_kernel_lost_context(dev); | |
bf9d8929 | 639 | return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__); |
1da177e4 LT |
640 | } |
641 | ||
c153f45f EA |
642 | static int i915_flush_ioctl(struct drm_device *dev, void *data, |
643 | struct drm_file *file_priv) | |
1da177e4 | 644 | { |
546b0974 EA |
645 | int ret; |
646 | ||
647 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); | |
1da177e4 | 648 | |
546b0974 EA |
649 | mutex_lock(&dev->struct_mutex); |
650 | ret = i915_quiescent(dev); | |
651 | mutex_unlock(&dev->struct_mutex); | |
652 | ||
653 | return ret; | |
1da177e4 LT |
654 | } |
655 | ||
c153f45f EA |
656 | static int i915_batchbuffer(struct drm_device *dev, void *data, |
657 | struct drm_file *file_priv) | |
1da177e4 | 658 | { |
1da177e4 | 659 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 660 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 661 | drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) |
7c1c2871 | 662 | master_priv->sarea_priv; |
c153f45f | 663 | drm_i915_batchbuffer_t *batch = data; |
1da177e4 | 664 | int ret; |
201361a5 | 665 | struct drm_clip_rect *cliprects = NULL; |
1da177e4 LT |
666 | |
667 | if (!dev_priv->allow_batchbuffer) { | |
668 | DRM_ERROR("Batchbuffer ioctl disabled\n"); | |
20caafa6 | 669 | return -EINVAL; |
1da177e4 LT |
670 | } |
671 | ||
8a4c47f3 | 672 | DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n", |
be25ed9c | 673 | batch->start, batch->used, batch->num_cliprects); |
1da177e4 | 674 | |
546b0974 | 675 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 676 | |
201361a5 EA |
677 | if (batch->num_cliprects < 0) |
678 | return -EINVAL; | |
679 | ||
680 | if (batch->num_cliprects) { | |
9a298b2a EA |
681 | cliprects = kcalloc(batch->num_cliprects, |
682 | sizeof(struct drm_clip_rect), | |
683 | GFP_KERNEL); | |
201361a5 EA |
684 | if (cliprects == NULL) |
685 | return -ENOMEM; | |
686 | ||
687 | ret = copy_from_user(cliprects, batch->cliprects, | |
688 | batch->num_cliprects * | |
689 | sizeof(struct drm_clip_rect)); | |
690 | if (ret != 0) | |
691 | goto fail_free; | |
692 | } | |
1da177e4 | 693 | |
546b0974 | 694 | mutex_lock(&dev->struct_mutex); |
201361a5 | 695 | ret = i915_dispatch_batchbuffer(dev, batch, cliprects); |
546b0974 | 696 | mutex_unlock(&dev->struct_mutex); |
1da177e4 | 697 | |
c99b058f | 698 | if (sarea_priv) |
0baf823a | 699 | sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
201361a5 EA |
700 | |
701 | fail_free: | |
9a298b2a | 702 | kfree(cliprects); |
201361a5 | 703 | |
1da177e4 LT |
704 | return ret; |
705 | } | |
706 | ||
c153f45f EA |
707 | static int i915_cmdbuffer(struct drm_device *dev, void *data, |
708 | struct drm_file *file_priv) | |
1da177e4 | 709 | { |
1da177e4 | 710 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 711 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 712 | drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) |
7c1c2871 | 713 | master_priv->sarea_priv; |
c153f45f | 714 | drm_i915_cmdbuffer_t *cmdbuf = data; |
201361a5 EA |
715 | struct drm_clip_rect *cliprects = NULL; |
716 | void *batch_data; | |
1da177e4 LT |
717 | int ret; |
718 | ||
8a4c47f3 | 719 | DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n", |
be25ed9c | 720 | cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects); |
1da177e4 | 721 | |
546b0974 | 722 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 723 | |
201361a5 EA |
724 | if (cmdbuf->num_cliprects < 0) |
725 | return -EINVAL; | |
726 | ||
9a298b2a | 727 | batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL); |
201361a5 EA |
728 | if (batch_data == NULL) |
729 | return -ENOMEM; | |
730 | ||
731 | ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz); | |
732 | if (ret != 0) | |
733 | goto fail_batch_free; | |
734 | ||
735 | if (cmdbuf->num_cliprects) { | |
9a298b2a EA |
736 | cliprects = kcalloc(cmdbuf->num_cliprects, |
737 | sizeof(struct drm_clip_rect), GFP_KERNEL); | |
201361a5 EA |
738 | if (cliprects == NULL) |
739 | goto fail_batch_free; | |
740 | ||
741 | ret = copy_from_user(cliprects, cmdbuf->cliprects, | |
742 | cmdbuf->num_cliprects * | |
743 | sizeof(struct drm_clip_rect)); | |
744 | if (ret != 0) | |
745 | goto fail_clip_free; | |
1da177e4 LT |
746 | } |
747 | ||
546b0974 | 748 | mutex_lock(&dev->struct_mutex); |
201361a5 | 749 | ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data); |
546b0974 | 750 | mutex_unlock(&dev->struct_mutex); |
1da177e4 LT |
751 | if (ret) { |
752 | DRM_ERROR("i915_dispatch_cmdbuffer failed\n"); | |
355d7f37 | 753 | goto fail_clip_free; |
1da177e4 LT |
754 | } |
755 | ||
c99b058f | 756 | if (sarea_priv) |
0baf823a | 757 | sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
201361a5 | 758 | |
201361a5 | 759 | fail_clip_free: |
9a298b2a | 760 | kfree(cliprects); |
355d7f37 | 761 | fail_batch_free: |
9a298b2a | 762 | kfree(batch_data); |
201361a5 EA |
763 | |
764 | return ret; | |
1da177e4 LT |
765 | } |
766 | ||
c153f45f EA |
767 | static int i915_flip_bufs(struct drm_device *dev, void *data, |
768 | struct drm_file *file_priv) | |
1da177e4 | 769 | { |
546b0974 EA |
770 | int ret; |
771 | ||
8a4c47f3 | 772 | DRM_DEBUG_DRIVER("%s\n", __func__); |
1da177e4 | 773 | |
546b0974 | 774 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 775 | |
546b0974 EA |
776 | mutex_lock(&dev->struct_mutex); |
777 | ret = i915_dispatch_flip(dev); | |
778 | mutex_unlock(&dev->struct_mutex); | |
779 | ||
780 | return ret; | |
1da177e4 LT |
781 | } |
782 | ||
c153f45f EA |
783 | static int i915_getparam(struct drm_device *dev, void *data, |
784 | struct drm_file *file_priv) | |
1da177e4 | 785 | { |
1da177e4 | 786 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 787 | drm_i915_getparam_t *param = data; |
1da177e4 LT |
788 | int value; |
789 | ||
790 | if (!dev_priv) { | |
3e684eae | 791 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 792 | return -EINVAL; |
1da177e4 LT |
793 | } |
794 | ||
c153f45f | 795 | switch (param->param) { |
1da177e4 | 796 | case I915_PARAM_IRQ_ACTIVE: |
0a3e67a4 | 797 | value = dev->pdev->irq ? 1 : 0; |
1da177e4 LT |
798 | break; |
799 | case I915_PARAM_ALLOW_BATCHBUFFER: | |
800 | value = dev_priv->allow_batchbuffer ? 1 : 0; | |
801 | break; | |
0d6aa60b DA |
802 | case I915_PARAM_LAST_DISPATCH: |
803 | value = READ_BREADCRUMB(dev_priv); | |
804 | break; | |
ed4c9c4a KH |
805 | case I915_PARAM_CHIPSET_ID: |
806 | value = dev->pci_device; | |
807 | break; | |
673a394b | 808 | case I915_PARAM_HAS_GEM: |
ac5c4e76 | 809 | value = dev_priv->has_gem; |
673a394b | 810 | break; |
0f973f27 JB |
811 | case I915_PARAM_NUM_FENCES_AVAIL: |
812 | value = dev_priv->num_fence_regs - dev_priv->fence_reg_start; | |
813 | break; | |
02e792fb DV |
814 | case I915_PARAM_HAS_OVERLAY: |
815 | value = dev_priv->overlay ? 1 : 0; | |
816 | break; | |
e9560f7c JB |
817 | case I915_PARAM_HAS_PAGEFLIPPING: |
818 | value = 1; | |
819 | break; | |
76446cac JB |
820 | case I915_PARAM_HAS_EXECBUF2: |
821 | /* depends on GEM */ | |
822 | value = dev_priv->has_gem; | |
823 | break; | |
1da177e4 | 824 | default: |
8a4c47f3 | 825 | DRM_DEBUG_DRIVER("Unknown parameter %d\n", |
76446cac | 826 | param->param); |
20caafa6 | 827 | return -EINVAL; |
1da177e4 LT |
828 | } |
829 | ||
c153f45f | 830 | if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { |
1da177e4 | 831 | DRM_ERROR("DRM_COPY_TO_USER failed\n"); |
20caafa6 | 832 | return -EFAULT; |
1da177e4 LT |
833 | } |
834 | ||
835 | return 0; | |
836 | } | |
837 | ||
c153f45f EA |
838 | static int i915_setparam(struct drm_device *dev, void *data, |
839 | struct drm_file *file_priv) | |
1da177e4 | 840 | { |
1da177e4 | 841 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 842 | drm_i915_setparam_t *param = data; |
1da177e4 LT |
843 | |
844 | if (!dev_priv) { | |
3e684eae | 845 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 846 | return -EINVAL; |
1da177e4 LT |
847 | } |
848 | ||
c153f45f | 849 | switch (param->param) { |
1da177e4 | 850 | case I915_SETPARAM_USE_MI_BATCHBUFFER_START: |
1da177e4 LT |
851 | break; |
852 | case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY: | |
c153f45f | 853 | dev_priv->tex_lru_log_granularity = param->value; |
1da177e4 LT |
854 | break; |
855 | case I915_SETPARAM_ALLOW_BATCHBUFFER: | |
c153f45f | 856 | dev_priv->allow_batchbuffer = param->value; |
1da177e4 | 857 | break; |
0f973f27 JB |
858 | case I915_SETPARAM_NUM_USED_FENCES: |
859 | if (param->value > dev_priv->num_fence_regs || | |
860 | param->value < 0) | |
861 | return -EINVAL; | |
862 | /* Userspace can use first N regs */ | |
863 | dev_priv->fence_reg_start = param->value; | |
864 | break; | |
1da177e4 | 865 | default: |
8a4c47f3 | 866 | DRM_DEBUG_DRIVER("unknown parameter %d\n", |
be25ed9c | 867 | param->param); |
20caafa6 | 868 | return -EINVAL; |
1da177e4 LT |
869 | } |
870 | ||
871 | return 0; | |
872 | } | |
873 | ||
c153f45f EA |
874 | static int i915_set_status_page(struct drm_device *dev, void *data, |
875 | struct drm_file *file_priv) | |
dc7a9319 | 876 | { |
dc7a9319 | 877 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 878 | drm_i915_hws_addr_t *hws = data; |
b39d50e5 ZW |
879 | |
880 | if (!I915_NEED_GFX_HWS(dev)) | |
881 | return -EINVAL; | |
dc7a9319 WZ |
882 | |
883 | if (!dev_priv) { | |
3e684eae | 884 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 885 | return -EINVAL; |
dc7a9319 | 886 | } |
dc7a9319 | 887 | |
79e53945 JB |
888 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
889 | WARN(1, "tried to set status page when mode setting active\n"); | |
890 | return 0; | |
891 | } | |
892 | ||
8a4c47f3 | 893 | DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr); |
c153f45f EA |
894 | |
895 | dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12); | |
dc7a9319 | 896 | |
8b409580 | 897 | dev_priv->hws_map.offset = dev->agp->base + hws->addr; |
dc7a9319 WZ |
898 | dev_priv->hws_map.size = 4*1024; |
899 | dev_priv->hws_map.type = 0; | |
900 | dev_priv->hws_map.flags = 0; | |
901 | dev_priv->hws_map.mtrr = 0; | |
902 | ||
dd0910b3 | 903 | drm_core_ioremap_wc(&dev_priv->hws_map, dev); |
dc7a9319 | 904 | if (dev_priv->hws_map.handle == NULL) { |
dc7a9319 WZ |
905 | i915_dma_cleanup(dev); |
906 | dev_priv->status_gfx_addr = 0; | |
907 | DRM_ERROR("can not ioremap virtual address for" | |
908 | " G33 hw status page\n"); | |
20caafa6 | 909 | return -ENOMEM; |
dc7a9319 WZ |
910 | } |
911 | dev_priv->hw_status_page = dev_priv->hws_map.handle; | |
912 | ||
913 | memset(dev_priv->hw_status_page, 0, PAGE_SIZE); | |
585fb111 | 914 | I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); |
8a4c47f3 | 915 | DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n", |
be25ed9c | 916 | dev_priv->status_gfx_addr); |
8a4c47f3 | 917 | DRM_DEBUG_DRIVER("load hws at %p\n", |
be25ed9c | 918 | dev_priv->hw_status_page); |
dc7a9319 WZ |
919 | return 0; |
920 | } | |
921 | ||
ec2a4c3f DA |
922 | static int i915_get_bridge_dev(struct drm_device *dev) |
923 | { | |
924 | struct drm_i915_private *dev_priv = dev->dev_private; | |
925 | ||
926 | dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); | |
927 | if (!dev_priv->bridge_dev) { | |
928 | DRM_ERROR("bridge device not found\n"); | |
929 | return -1; | |
930 | } | |
931 | return 0; | |
932 | } | |
933 | ||
79e53945 JB |
934 | /** |
935 | * i915_probe_agp - get AGP bootup configuration | |
936 | * @pdev: PCI device | |
937 | * @aperture_size: returns AGP aperture configured size | |
938 | * @preallocated_size: returns size of BIOS preallocated AGP space | |
939 | * | |
940 | * Since Intel integrated graphics are UMA, the BIOS has to set aside | |
941 | * some RAM for the framebuffer at early boot. This code figures out | |
942 | * how much was set aside so we can use it for our own purposes. | |
943 | */ | |
2a34f5e6 | 944 | static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size, |
80824003 JB |
945 | uint32_t *preallocated_size, |
946 | uint32_t *start) | |
79e53945 | 947 | { |
ec2a4c3f | 948 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
949 | u16 tmp = 0; |
950 | unsigned long overhead; | |
241fa85b | 951 | unsigned long stolen; |
79e53945 | 952 | |
79e53945 | 953 | /* Get the fb aperture size and "stolen" memory amount. */ |
ec2a4c3f | 954 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp); |
79e53945 JB |
955 | |
956 | *aperture_size = 1024 * 1024; | |
957 | *preallocated_size = 1024 * 1024; | |
958 | ||
60fd99e3 | 959 | switch (dev->pdev->device) { |
79e53945 JB |
960 | case PCI_DEVICE_ID_INTEL_82830_CGC: |
961 | case PCI_DEVICE_ID_INTEL_82845G_IG: | |
962 | case PCI_DEVICE_ID_INTEL_82855GM_IG: | |
963 | case PCI_DEVICE_ID_INTEL_82865_IG: | |
964 | if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M) | |
965 | *aperture_size *= 64; | |
966 | else | |
967 | *aperture_size *= 128; | |
968 | break; | |
969 | default: | |
970 | /* 9xx supports large sizes, just look at the length */ | |
60fd99e3 | 971 | *aperture_size = pci_resource_len(dev->pdev, 2); |
79e53945 JB |
972 | break; |
973 | } | |
974 | ||
975 | /* | |
976 | * Some of the preallocated space is taken by the GTT | |
977 | * and popup. GTT is 1K per MB of aperture size, and popup is 4K. | |
978 | */ | |
f2b115e6 | 979 | if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev)) |
60fd99e3 EA |
980 | overhead = 4096; |
981 | else | |
982 | overhead = (*aperture_size / 1024) + 4096; | |
983 | ||
241fa85b EA |
984 | switch (tmp & INTEL_GMCH_GMS_MASK) { |
985 | case INTEL_855_GMCH_GMS_DISABLED: | |
986 | DRM_ERROR("video memory is disabled\n"); | |
987 | return -1; | |
79e53945 | 988 | case INTEL_855_GMCH_GMS_STOLEN_1M: |
241fa85b EA |
989 | stolen = 1 * 1024 * 1024; |
990 | break; | |
79e53945 | 991 | case INTEL_855_GMCH_GMS_STOLEN_4M: |
241fa85b | 992 | stolen = 4 * 1024 * 1024; |
79e53945 JB |
993 | break; |
994 | case INTEL_855_GMCH_GMS_STOLEN_8M: | |
241fa85b | 995 | stolen = 8 * 1024 * 1024; |
79e53945 JB |
996 | break; |
997 | case INTEL_855_GMCH_GMS_STOLEN_16M: | |
241fa85b | 998 | stolen = 16 * 1024 * 1024; |
79e53945 JB |
999 | break; |
1000 | case INTEL_855_GMCH_GMS_STOLEN_32M: | |
241fa85b | 1001 | stolen = 32 * 1024 * 1024; |
79e53945 JB |
1002 | break; |
1003 | case INTEL_915G_GMCH_GMS_STOLEN_48M: | |
241fa85b | 1004 | stolen = 48 * 1024 * 1024; |
79e53945 JB |
1005 | break; |
1006 | case INTEL_915G_GMCH_GMS_STOLEN_64M: | |
241fa85b EA |
1007 | stolen = 64 * 1024 * 1024; |
1008 | break; | |
1009 | case INTEL_GMCH_GMS_STOLEN_128M: | |
1010 | stolen = 128 * 1024 * 1024; | |
1011 | break; | |
1012 | case INTEL_GMCH_GMS_STOLEN_256M: | |
1013 | stolen = 256 * 1024 * 1024; | |
1014 | break; | |
1015 | case INTEL_GMCH_GMS_STOLEN_96M: | |
1016 | stolen = 96 * 1024 * 1024; | |
1017 | break; | |
1018 | case INTEL_GMCH_GMS_STOLEN_160M: | |
1019 | stolen = 160 * 1024 * 1024; | |
1020 | break; | |
1021 | case INTEL_GMCH_GMS_STOLEN_224M: | |
1022 | stolen = 224 * 1024 * 1024; | |
1023 | break; | |
1024 | case INTEL_GMCH_GMS_STOLEN_352M: | |
1025 | stolen = 352 * 1024 * 1024; | |
79e53945 | 1026 | break; |
79e53945 JB |
1027 | default: |
1028 | DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n", | |
241fa85b | 1029 | tmp & INTEL_GMCH_GMS_MASK); |
79e53945 JB |
1030 | return -1; |
1031 | } | |
241fa85b | 1032 | *preallocated_size = stolen - overhead; |
80824003 | 1033 | *start = overhead; |
79e53945 JB |
1034 | |
1035 | return 0; | |
1036 | } | |
1037 | ||
80824003 JB |
1038 | #define PTE_ADDRESS_MASK 0xfffff000 |
1039 | #define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */ | |
1040 | #define PTE_MAPPING_TYPE_UNCACHED (0 << 1) | |
1041 | #define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */ | |
1042 | #define PTE_MAPPING_TYPE_CACHED (3 << 1) | |
1043 | #define PTE_MAPPING_TYPE_MASK (3 << 1) | |
1044 | #define PTE_VALID (1 << 0) | |
1045 | ||
1046 | /** | |
1047 | * i915_gtt_to_phys - take a GTT address and turn it into a physical one | |
1048 | * @dev: drm device | |
1049 | * @gtt_addr: address to translate | |
1050 | * | |
1051 | * Some chip functions require allocations from stolen space but need the | |
1052 | * physical address of the memory in question. We use this routine | |
1053 | * to get a physical address suitable for register programming from a given | |
1054 | * GTT address. | |
1055 | */ | |
1056 | static unsigned long i915_gtt_to_phys(struct drm_device *dev, | |
1057 | unsigned long gtt_addr) | |
1058 | { | |
1059 | unsigned long *gtt; | |
1060 | unsigned long entry, phys; | |
1061 | int gtt_bar = IS_I9XX(dev) ? 0 : 1; | |
1062 | int gtt_offset, gtt_size; | |
1063 | ||
1064 | if (IS_I965G(dev)) { | |
f2b115e6 | 1065 | if (IS_G4X(dev) || IS_IRONLAKE(dev)) { |
80824003 JB |
1066 | gtt_offset = 2*1024*1024; |
1067 | gtt_size = 2*1024*1024; | |
1068 | } else { | |
1069 | gtt_offset = 512*1024; | |
1070 | gtt_size = 512*1024; | |
1071 | } | |
1072 | } else { | |
1073 | gtt_bar = 3; | |
1074 | gtt_offset = 0; | |
1075 | gtt_size = pci_resource_len(dev->pdev, gtt_bar); | |
1076 | } | |
1077 | ||
1078 | gtt = ioremap_wc(pci_resource_start(dev->pdev, gtt_bar) + gtt_offset, | |
1079 | gtt_size); | |
1080 | if (!gtt) { | |
1081 | DRM_ERROR("ioremap of GTT failed\n"); | |
1082 | return 0; | |
1083 | } | |
1084 | ||
1085 | entry = *(volatile u32 *)(gtt + (gtt_addr / 1024)); | |
1086 | ||
44d98a61 | 1087 | DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry); |
80824003 JB |
1088 | |
1089 | /* Mask out these reserved bits on this hardware. */ | |
1090 | if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) || | |
1091 | IS_I945G(dev) || IS_I945GM(dev)) { | |
1092 | entry &= ~PTE_ADDRESS_MASK_HIGH; | |
1093 | } | |
1094 | ||
1095 | /* If it's not a mapping type we know, then bail. */ | |
1096 | if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED && | |
1097 | (entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_CACHED) { | |
1098 | iounmap(gtt); | |
1099 | return 0; | |
1100 | } | |
1101 | ||
1102 | if (!(entry & PTE_VALID)) { | |
1103 | DRM_ERROR("bad GTT entry in stolen space\n"); | |
1104 | iounmap(gtt); | |
1105 | return 0; | |
1106 | } | |
1107 | ||
1108 | iounmap(gtt); | |
1109 | ||
1110 | phys =(entry & PTE_ADDRESS_MASK) | | |
1111 | ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4)); | |
1112 | ||
44d98a61 | 1113 | DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys); |
80824003 JB |
1114 | |
1115 | return phys; | |
1116 | } | |
1117 | ||
1118 | static void i915_warn_stolen(struct drm_device *dev) | |
1119 | { | |
1120 | DRM_ERROR("not enough stolen space for compressed buffer, disabling\n"); | |
1121 | DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n"); | |
1122 | } | |
1123 | ||
1124 | static void i915_setup_compression(struct drm_device *dev, int size) | |
1125 | { | |
1126 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1127 | struct drm_mm_node *compressed_fb, *compressed_llb; | |
29bd0ae2 AM |
1128 | unsigned long cfb_base; |
1129 | unsigned long ll_base = 0; | |
80824003 JB |
1130 | |
1131 | /* Leave 1M for line length buffer & misc. */ | |
1132 | compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0); | |
1133 | if (!compressed_fb) { | |
1134 | i915_warn_stolen(dev); | |
1135 | return; | |
1136 | } | |
1137 | ||
1138 | compressed_fb = drm_mm_get_block(compressed_fb, size, 4096); | |
1139 | if (!compressed_fb) { | |
1140 | i915_warn_stolen(dev); | |
1141 | return; | |
1142 | } | |
1143 | ||
74dff282 JB |
1144 | cfb_base = i915_gtt_to_phys(dev, compressed_fb->start); |
1145 | if (!cfb_base) { | |
1146 | DRM_ERROR("failed to get stolen phys addr, disabling FBC\n"); | |
1147 | drm_mm_put_block(compressed_fb); | |
80824003 JB |
1148 | } |
1149 | ||
74dff282 JB |
1150 | if (!IS_GM45(dev)) { |
1151 | compressed_llb = drm_mm_search_free(&dev_priv->vram, 4096, | |
1152 | 4096, 0); | |
1153 | if (!compressed_llb) { | |
1154 | i915_warn_stolen(dev); | |
1155 | return; | |
1156 | } | |
1157 | ||
1158 | compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096); | |
1159 | if (!compressed_llb) { | |
1160 | i915_warn_stolen(dev); | |
1161 | return; | |
1162 | } | |
1163 | ||
1164 | ll_base = i915_gtt_to_phys(dev, compressed_llb->start); | |
1165 | if (!ll_base) { | |
1166 | DRM_ERROR("failed to get stolen phys addr, disabling FBC\n"); | |
1167 | drm_mm_put_block(compressed_fb); | |
1168 | drm_mm_put_block(compressed_llb); | |
1169 | } | |
80824003 JB |
1170 | } |
1171 | ||
1172 | dev_priv->cfb_size = size; | |
1173 | ||
74dff282 JB |
1174 | if (IS_GM45(dev)) { |
1175 | g4x_disable_fbc(dev); | |
1176 | I915_WRITE(DPFC_CB_BASE, compressed_fb->start); | |
1177 | } else { | |
1178 | i8xx_disable_fbc(dev); | |
1179 | I915_WRITE(FBC_CFB_BASE, cfb_base); | |
1180 | I915_WRITE(FBC_LL_BASE, ll_base); | |
80824003 JB |
1181 | } |
1182 | ||
80824003 JB |
1183 | DRM_DEBUG("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base, |
1184 | ll_base, size >> 20); | |
80824003 JB |
1185 | } |
1186 | ||
28d52043 DA |
1187 | /* true = enable decode, false = disable decoder */ |
1188 | static unsigned int i915_vga_set_decode(void *cookie, bool state) | |
1189 | { | |
1190 | struct drm_device *dev = cookie; | |
1191 | ||
1192 | intel_modeset_vga_set_state(dev, state); | |
1193 | if (state) | |
1194 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
1195 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1196 | else | |
1197 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1198 | } | |
1199 | ||
2a34f5e6 | 1200 | static int i915_load_modeset_init(struct drm_device *dev, |
80824003 | 1201 | unsigned long prealloc_start, |
2a34f5e6 EA |
1202 | unsigned long prealloc_size, |
1203 | unsigned long agp_size) | |
79e53945 JB |
1204 | { |
1205 | struct drm_i915_private *dev_priv = dev->dev_private; | |
79e53945 JB |
1206 | int fb_bar = IS_I9XX(dev) ? 2 : 0; |
1207 | int ret = 0; | |
1208 | ||
1209 | dev->mode_config.fb_base = drm_get_resource_start(dev, fb_bar) & | |
1210 | 0xff000000; | |
1211 | ||
79e53945 JB |
1212 | /* Basic memrange allocator for stolen space (aka vram) */ |
1213 | drm_mm_init(&dev_priv->vram, 0, prealloc_size); | |
80824003 | 1214 | DRM_INFO("set up %ldM of stolen space\n", prealloc_size / (1024*1024)); |
79e53945 | 1215 | |
11ed50ec BG |
1216 | /* We're off and running w/KMS */ |
1217 | dev_priv->mm.suspended = 0; | |
79e53945 | 1218 | |
13f4c435 EA |
1219 | /* Let GEM Manage from end of prealloc space to end of aperture. |
1220 | * | |
1221 | * However, leave one page at the end still bound to the scratch page. | |
1222 | * There are a number of places where the hardware apparently | |
1223 | * prefetches past the end of the object, and we've seen multiple | |
1224 | * hangs with the GPU head pointer stuck in a batchbuffer bound | |
1225 | * at the last page of the aperture. One page should be enough to | |
1226 | * keep any prefetching inside of the aperture. | |
1227 | */ | |
1228 | i915_gem_do_init(dev, prealloc_size, agp_size - 4096); | |
79e53945 | 1229 | |
11ed50ec | 1230 | mutex_lock(&dev->struct_mutex); |
79e53945 | 1231 | ret = i915_gem_init_ringbuffer(dev); |
11ed50ec | 1232 | mutex_unlock(&dev->struct_mutex); |
79e53945 | 1233 | if (ret) |
b8da7de5 | 1234 | goto out; |
79e53945 | 1235 | |
80824003 | 1236 | /* Try to set up FBC with a reasonable compressed buffer size */ |
9216d44d | 1237 | if (I915_HAS_FBC(dev) && i915_powersave) { |
80824003 JB |
1238 | int cfb_size; |
1239 | ||
1240 | /* Try to get an 8M buffer... */ | |
1241 | if (prealloc_size > (9*1024*1024)) | |
1242 | cfb_size = 8*1024*1024; | |
1243 | else /* fall back to 7/8 of the stolen space */ | |
1244 | cfb_size = prealloc_size * 7 / 8; | |
1245 | i915_setup_compression(dev, cfb_size); | |
1246 | } | |
1247 | ||
79e53945 JB |
1248 | /* Allow hardware batchbuffers unless told otherwise. |
1249 | */ | |
1250 | dev_priv->allow_batchbuffer = 1; | |
1251 | ||
1252 | ret = intel_init_bios(dev); | |
1253 | if (ret) | |
1254 | DRM_INFO("failed to find VBIOS tables\n"); | |
1255 | ||
28d52043 DA |
1256 | /* if we have > 1 VGA cards, then disable the radeon VGA resources */ |
1257 | ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode); | |
1258 | if (ret) | |
1259 | goto destroy_ringbuffer; | |
1260 | ||
b01f2c3a JB |
1261 | intel_modeset_init(dev); |
1262 | ||
79e53945 JB |
1263 | ret = drm_irq_install(dev); |
1264 | if (ret) | |
1265 | goto destroy_ringbuffer; | |
1266 | ||
79e53945 JB |
1267 | /* Always safe in the mode setting case. */ |
1268 | /* FIXME: do pre/post-mode set stuff in core KMS code */ | |
1269 | dev->vblank_disable_allowed = 1; | |
1270 | ||
1271 | /* | |
1272 | * Initialize the hardware status page IRQ location. | |
1273 | */ | |
1274 | ||
1275 | I915_WRITE(INSTPM, (1 << 5) | (1 << 21)); | |
1276 | ||
7a1fb5d0 | 1277 | drm_helper_initial_config(dev); |
79e53945 | 1278 | |
79e53945 JB |
1279 | return 0; |
1280 | ||
79e53945 JB |
1281 | destroy_ringbuffer: |
1282 | i915_gem_cleanup_ringbuffer(dev); | |
1283 | out: | |
1284 | return ret; | |
1285 | } | |
1286 | ||
7c1c2871 DA |
1287 | int i915_master_create(struct drm_device *dev, struct drm_master *master) |
1288 | { | |
1289 | struct drm_i915_master_private *master_priv; | |
1290 | ||
9a298b2a | 1291 | master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL); |
7c1c2871 DA |
1292 | if (!master_priv) |
1293 | return -ENOMEM; | |
1294 | ||
1295 | master->driver_priv = master_priv; | |
1296 | return 0; | |
1297 | } | |
1298 | ||
1299 | void i915_master_destroy(struct drm_device *dev, struct drm_master *master) | |
1300 | { | |
1301 | struct drm_i915_master_private *master_priv = master->driver_priv; | |
1302 | ||
1303 | if (!master_priv) | |
1304 | return; | |
1305 | ||
9a298b2a | 1306 | kfree(master_priv); |
7c1c2871 DA |
1307 | |
1308 | master->driver_priv = NULL; | |
1309 | } | |
1310 | ||
7662c8bd SL |
1311 | static void i915_get_mem_freq(struct drm_device *dev) |
1312 | { | |
1313 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1314 | u32 tmp; | |
1315 | ||
f2b115e6 | 1316 | if (!IS_PINEVIEW(dev)) |
7662c8bd SL |
1317 | return; |
1318 | ||
1319 | tmp = I915_READ(CLKCFG); | |
1320 | ||
1321 | switch (tmp & CLKCFG_FSB_MASK) { | |
1322 | case CLKCFG_FSB_533: | |
1323 | dev_priv->fsb_freq = 533; /* 133*4 */ | |
1324 | break; | |
1325 | case CLKCFG_FSB_800: | |
1326 | dev_priv->fsb_freq = 800; /* 200*4 */ | |
1327 | break; | |
1328 | case CLKCFG_FSB_667: | |
1329 | dev_priv->fsb_freq = 667; /* 167*4 */ | |
1330 | break; | |
1331 | case CLKCFG_FSB_400: | |
1332 | dev_priv->fsb_freq = 400; /* 100*4 */ | |
1333 | break; | |
1334 | } | |
1335 | ||
1336 | switch (tmp & CLKCFG_MEM_MASK) { | |
1337 | case CLKCFG_MEM_533: | |
1338 | dev_priv->mem_freq = 533; | |
1339 | break; | |
1340 | case CLKCFG_MEM_667: | |
1341 | dev_priv->mem_freq = 667; | |
1342 | break; | |
1343 | case CLKCFG_MEM_800: | |
1344 | dev_priv->mem_freq = 800; | |
1345 | break; | |
1346 | } | |
1347 | } | |
1348 | ||
79e53945 JB |
1349 | /** |
1350 | * i915_driver_load - setup chip and create an initial config | |
1351 | * @dev: DRM device | |
1352 | * @flags: startup flags | |
1353 | * | |
1354 | * The driver load routine has to do several things: | |
1355 | * - drive output discovery via intel_modeset_init() | |
1356 | * - initialize the memory manager | |
1357 | * - allocate initial config memory | |
1358 | * - setup the DRM framebuffer with the allocated memory | |
1359 | */ | |
84b1fd10 | 1360 | int i915_driver_load(struct drm_device *dev, unsigned long flags) |
22eae947 | 1361 | { |
ba8bbcf6 | 1362 | struct drm_i915_private *dev_priv = dev->dev_private; |
d883f7f1 | 1363 | resource_size_t base, size; |
cfdf1fa2 | 1364 | int ret = 0, mmio_bar; |
80824003 | 1365 | uint32_t agp_size, prealloc_size, prealloc_start; |
ba8bbcf6 | 1366 | |
22eae947 DA |
1367 | /* i915 has 4 more counters */ |
1368 | dev->counters += 4; | |
1369 | dev->types[6] = _DRM_STAT_IRQ; | |
1370 | dev->types[7] = _DRM_STAT_PRIMARY; | |
1371 | dev->types[8] = _DRM_STAT_SECONDARY; | |
1372 | dev->types[9] = _DRM_STAT_DMA; | |
1373 | ||
9a298b2a | 1374 | dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL); |
ba8bbcf6 JB |
1375 | if (dev_priv == NULL) |
1376 | return -ENOMEM; | |
1377 | ||
ba8bbcf6 | 1378 | dev->dev_private = (void *)dev_priv; |
673a394b | 1379 | dev_priv->dev = dev; |
cfdf1fa2 | 1380 | dev_priv->info = (struct intel_device_info *) flags; |
ba8bbcf6 JB |
1381 | |
1382 | /* Add register map (needed for suspend/resume) */ | |
cfdf1fa2 | 1383 | mmio_bar = IS_I9XX(dev) ? 0 : 1; |
ba8bbcf6 JB |
1384 | base = drm_get_resource_start(dev, mmio_bar); |
1385 | size = drm_get_resource_len(dev, mmio_bar); | |
1386 | ||
ec2a4c3f DA |
1387 | if (i915_get_bridge_dev(dev)) { |
1388 | ret = -EIO; | |
1389 | goto free_priv; | |
1390 | } | |
1391 | ||
3043c60c | 1392 | dev_priv->regs = ioremap(base, size); |
79e53945 JB |
1393 | if (!dev_priv->regs) { |
1394 | DRM_ERROR("failed to map registers\n"); | |
1395 | ret = -EIO; | |
ec2a4c3f | 1396 | goto put_bridge; |
79e53945 | 1397 | } |
ed4cb414 | 1398 | |
ab657db1 EA |
1399 | dev_priv->mm.gtt_mapping = |
1400 | io_mapping_create_wc(dev->agp->base, | |
1401 | dev->agp->agp_info.aper_size * 1024*1024); | |
6644107d VP |
1402 | if (dev_priv->mm.gtt_mapping == NULL) { |
1403 | ret = -EIO; | |
1404 | goto out_rmmap; | |
1405 | } | |
1406 | ||
ab657db1 EA |
1407 | /* Set up a WC MTRR for non-PAT systems. This is more common than |
1408 | * one would think, because the kernel disables PAT on first | |
1409 | * generation Core chips because WC PAT gets overridden by a UC | |
1410 | * MTRR if present. Even if a UC MTRR isn't present. | |
1411 | */ | |
1412 | dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base, | |
1413 | dev->agp->agp_info.aper_size * | |
1414 | 1024 * 1024, | |
1415 | MTRR_TYPE_WRCOMB, 1); | |
1416 | if (dev_priv->mm.gtt_mtrr < 0) { | |
040aefa2 | 1417 | DRM_INFO("MTRR allocation failed. Graphics " |
ab657db1 EA |
1418 | "performance may suffer.\n"); |
1419 | } | |
1420 | ||
80824003 | 1421 | ret = i915_probe_agp(dev, &agp_size, &prealloc_size, &prealloc_start); |
2a34f5e6 EA |
1422 | if (ret) |
1423 | goto out_iomapfree; | |
1424 | ||
aed5f1dc | 1425 | dev_priv->wq = create_singlethread_workqueue("i915"); |
9c9fe1f8 EA |
1426 | if (dev_priv->wq == NULL) { |
1427 | DRM_ERROR("Failed to create our workqueue.\n"); | |
1428 | ret = -ENOMEM; | |
1429 | goto out_iomapfree; | |
1430 | } | |
1431 | ||
ac5c4e76 DA |
1432 | /* enable GEM by default */ |
1433 | dev_priv->has_gem = 1; | |
ac5c4e76 | 1434 | |
2a34f5e6 EA |
1435 | if (prealloc_size > agp_size * 3 / 4) { |
1436 | DRM_ERROR("Detected broken video BIOS with %d/%dkB of video " | |
1437 | "memory stolen.\n", | |
1438 | prealloc_size / 1024, agp_size / 1024); | |
1439 | DRM_ERROR("Disabling GEM. (try reducing stolen memory or " | |
1440 | "updating the BIOS to fix).\n"); | |
1441 | dev_priv->has_gem = 0; | |
1442 | } | |
1443 | ||
9880b7a5 | 1444 | dev->driver->get_vblank_counter = i915_get_vblank_counter; |
42c2798b | 1445 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ |
f2b115e6 | 1446 | if (IS_G4X(dev) || IS_IRONLAKE(dev)) { |
42c2798b | 1447 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
9880b7a5 | 1448 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; |
42c2798b | 1449 | } |
9880b7a5 | 1450 | |
673a394b EA |
1451 | i915_gem_load(dev); |
1452 | ||
398c9cb2 KP |
1453 | /* Init HWS */ |
1454 | if (!I915_NEED_GFX_HWS(dev)) { | |
1455 | ret = i915_init_phys_hws(dev); | |
1456 | if (ret != 0) | |
9c9fe1f8 | 1457 | goto out_workqueue_free; |
398c9cb2 | 1458 | } |
ed4cb414 | 1459 | |
7662c8bd SL |
1460 | i915_get_mem_freq(dev); |
1461 | ||
ed4cb414 EA |
1462 | /* On the 945G/GM, the chipset reports the MSI capability on the |
1463 | * integrated graphics even though the support isn't actually there | |
1464 | * according to the published specs. It doesn't appear to function | |
1465 | * correctly in testing on 945G. | |
1466 | * This may be a side effect of MSI having been made available for PEG | |
1467 | * and the registers being closely associated. | |
d1ed629f KP |
1468 | * |
1469 | * According to chipset errata, on the 965GM, MSI interrupts may | |
b60678a7 KP |
1470 | * be lost or delayed, but we use them anyways to avoid |
1471 | * stuck interrupts on some machines. | |
ed4cb414 | 1472 | */ |
b60678a7 | 1473 | if (!IS_I945G(dev) && !IS_I945GM(dev)) |
d3e74d02 | 1474 | pci_enable_msi(dev->pdev); |
ed4cb414 EA |
1475 | |
1476 | spin_lock_init(&dev_priv->user_irq_lock); | |
63eeaf38 | 1477 | spin_lock_init(&dev_priv->error_lock); |
79e53945 | 1478 | dev_priv->user_irq_refcount = 0; |
9d34e5db | 1479 | dev_priv->trace_irq_seqno = 0; |
ed4cb414 | 1480 | |
52440211 KP |
1481 | ret = drm_vblank_init(dev, I915_NUM_PIPE); |
1482 | ||
1483 | if (ret) { | |
1484 | (void) i915_driver_unload(dev); | |
1485 | return ret; | |
1486 | } | |
1487 | ||
11ed50ec BG |
1488 | /* Start out suspended */ |
1489 | dev_priv->mm.suspended = 1; | |
1490 | ||
79e53945 | 1491 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
80824003 JB |
1492 | ret = i915_load_modeset_init(dev, prealloc_start, |
1493 | prealloc_size, agp_size); | |
79e53945 JB |
1494 | if (ret < 0) { |
1495 | DRM_ERROR("failed to init modeset\n"); | |
9c9fe1f8 | 1496 | goto out_workqueue_free; |
79e53945 JB |
1497 | } |
1498 | } | |
1499 | ||
74a365b3 | 1500 | /* Must be done after probing outputs */ |
01c66889 | 1501 | intel_opregion_init(dev, 0); |
74a365b3 | 1502 | |
f65d9421 BG |
1503 | setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed, |
1504 | (unsigned long) dev); | |
79e53945 JB |
1505 | return 0; |
1506 | ||
9c9fe1f8 EA |
1507 | out_workqueue_free: |
1508 | destroy_workqueue(dev_priv->wq); | |
6644107d VP |
1509 | out_iomapfree: |
1510 | io_mapping_free(dev_priv->mm.gtt_mapping); | |
79e53945 JB |
1511 | out_rmmap: |
1512 | iounmap(dev_priv->regs); | |
ec2a4c3f DA |
1513 | put_bridge: |
1514 | pci_dev_put(dev_priv->bridge_dev); | |
79e53945 | 1515 | free_priv: |
9a298b2a | 1516 | kfree(dev_priv); |
ba8bbcf6 JB |
1517 | return ret; |
1518 | } | |
1519 | ||
1520 | int i915_driver_unload(struct drm_device *dev) | |
1521 | { | |
1522 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1523 | ||
9c9fe1f8 | 1524 | destroy_workqueue(dev_priv->wq); |
f65d9421 | 1525 | del_timer_sync(&dev_priv->hangcheck_timer); |
9c9fe1f8 | 1526 | |
ab657db1 EA |
1527 | io_mapping_free(dev_priv->mm.gtt_mapping); |
1528 | if (dev_priv->mm.gtt_mtrr >= 0) { | |
1529 | mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base, | |
1530 | dev->agp->agp_info.aper_size * 1024 * 1024); | |
1531 | dev_priv->mm.gtt_mtrr = -1; | |
1532 | } | |
1533 | ||
79e53945 | 1534 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
6363ee6f ZY |
1535 | /* |
1536 | * free the memory space allocated for the child device | |
1537 | * config parsed from VBT | |
1538 | */ | |
1539 | if (dev_priv->child_dev && dev_priv->child_dev_num) { | |
1540 | kfree(dev_priv->child_dev); | |
1541 | dev_priv->child_dev = NULL; | |
1542 | dev_priv->child_dev_num = 0; | |
1543 | } | |
79e53945 | 1544 | drm_irq_uninstall(dev); |
28d52043 | 1545 | vga_client_register(dev->pdev, NULL, NULL, NULL); |
79e53945 JB |
1546 | } |
1547 | ||
ed4cb414 EA |
1548 | if (dev->pdev->msi_enabled) |
1549 | pci_disable_msi(dev->pdev); | |
1550 | ||
3043c60c EA |
1551 | if (dev_priv->regs != NULL) |
1552 | iounmap(dev_priv->regs); | |
ba8bbcf6 | 1553 | |
01c66889 | 1554 | intel_opregion_free(dev, 0); |
8ee1c3db | 1555 | |
79e53945 JB |
1556 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
1557 | intel_modeset_cleanup(dev); | |
1558 | ||
71acb5eb DA |
1559 | i915_gem_free_all_phys_object(dev); |
1560 | ||
79e53945 JB |
1561 | mutex_lock(&dev->struct_mutex); |
1562 | i915_gem_cleanup_ringbuffer(dev); | |
1563 | mutex_unlock(&dev->struct_mutex); | |
1564 | drm_mm_takedown(&dev_priv->vram); | |
1565 | i915_gem_lastclose(dev); | |
02e792fb DV |
1566 | |
1567 | intel_cleanup_overlay(dev); | |
79e53945 JB |
1568 | } |
1569 | ||
ec2a4c3f | 1570 | pci_dev_put(dev_priv->bridge_dev); |
9a298b2a | 1571 | kfree(dev->dev_private); |
ba8bbcf6 | 1572 | |
22eae947 DA |
1573 | return 0; |
1574 | } | |
1575 | ||
673a394b EA |
1576 | int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv) |
1577 | { | |
1578 | struct drm_i915_file_private *i915_file_priv; | |
1579 | ||
8a4c47f3 | 1580 | DRM_DEBUG_DRIVER("\n"); |
673a394b | 1581 | i915_file_priv = (struct drm_i915_file_private *) |
9a298b2a | 1582 | kmalloc(sizeof(*i915_file_priv), GFP_KERNEL); |
673a394b EA |
1583 | |
1584 | if (!i915_file_priv) | |
1585 | return -ENOMEM; | |
1586 | ||
1587 | file_priv->driver_priv = i915_file_priv; | |
1588 | ||
b962442e | 1589 | INIT_LIST_HEAD(&i915_file_priv->mm.request_list); |
673a394b EA |
1590 | |
1591 | return 0; | |
1592 | } | |
1593 | ||
79e53945 JB |
1594 | /** |
1595 | * i915_driver_lastclose - clean up after all DRM clients have exited | |
1596 | * @dev: DRM device | |
1597 | * | |
1598 | * Take care of cleaning up after all DRM clients have exited. In the | |
1599 | * mode setting case, we want to restore the kernel's initial mode (just | |
1600 | * in case the last client left us in a bad state). | |
1601 | * | |
1602 | * Additionally, in the non-mode setting case, we'll tear down the AGP | |
1603 | * and DMA structures, since the kernel won't be using them, and clea | |
1604 | * up any GEM state. | |
1605 | */ | |
84b1fd10 | 1606 | void i915_driver_lastclose(struct drm_device * dev) |
1da177e4 | 1607 | { |
ba8bbcf6 JB |
1608 | drm_i915_private_t *dev_priv = dev->dev_private; |
1609 | ||
79e53945 | 1610 | if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) { |
785b93ef | 1611 | drm_fb_helper_restore(); |
144a75fa | 1612 | return; |
79e53945 | 1613 | } |
144a75fa | 1614 | |
673a394b EA |
1615 | i915_gem_lastclose(dev); |
1616 | ||
ba8bbcf6 | 1617 | if (dev_priv->agp_heap) |
b5e89ed5 | 1618 | i915_mem_takedown(&(dev_priv->agp_heap)); |
ba8bbcf6 | 1619 | |
b5e89ed5 | 1620 | i915_dma_cleanup(dev); |
1da177e4 LT |
1621 | } |
1622 | ||
6c340eac | 1623 | void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv) |
1da177e4 | 1624 | { |
ba8bbcf6 | 1625 | drm_i915_private_t *dev_priv = dev->dev_private; |
b962442e | 1626 | i915_gem_release(dev, file_priv); |
79e53945 JB |
1627 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
1628 | i915_mem_release(dev, file_priv, dev_priv->agp_heap); | |
1da177e4 LT |
1629 | } |
1630 | ||
673a394b EA |
1631 | void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv) |
1632 | { | |
1633 | struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; | |
1634 | ||
9a298b2a | 1635 | kfree(i915_file_priv); |
673a394b EA |
1636 | } |
1637 | ||
c153f45f EA |
1638 | struct drm_ioctl_desc i915_ioctls[] = { |
1639 | DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1640 | DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH), | |
1641 | DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH), | |
1642 | DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH), | |
1643 | DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH), | |
1644 | DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH), | |
1645 | DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH), | |
1646 | DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1647 | DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH), | |
1648 | DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH), | |
1649 | DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1650 | DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH), | |
1651 | DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ), | |
1652 | DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ), | |
1653 | DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ), | |
1654 | DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH), | |
4b408939 | 1655 | DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
2bdf00b2 | 1656 | DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
673a394b | 1657 | DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH), |
76446cac | 1658 | DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH), |
673a394b EA |
1659 | DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), |
1660 | DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), | |
1661 | DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH), | |
1662 | DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH), | |
2bdf00b2 DA |
1663 | DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1664 | DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
673a394b EA |
1665 | DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0), |
1666 | DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, 0), | |
1667 | DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, 0), | |
1668 | DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0), | |
de151cf6 | 1669 | DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, 0), |
673a394b EA |
1670 | DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, 0), |
1671 | DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0), | |
1672 | DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0), | |
1673 | DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0), | |
5a125c3c | 1674 | DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, 0), |
08d7b3d1 | 1675 | DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0), |
3ef94daa | 1676 | DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, 0), |
02e792fb DV |
1677 | DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW), |
1678 | DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW), | |
c94f7029 DA |
1679 | }; |
1680 | ||
1681 | int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); | |
cda17380 DA |
1682 | |
1683 | /** | |
1684 | * Determine if the device really is AGP or not. | |
1685 | * | |
1686 | * All Intel graphics chipsets are treated as AGP, even if they are really | |
1687 | * PCI-e. | |
1688 | * | |
1689 | * \param dev The device to be tested. | |
1690 | * | |
1691 | * \returns | |
1692 | * A value of 1 is always retured to indictate every i9x5 is AGP. | |
1693 | */ | |
84b1fd10 | 1694 | int i915_driver_device_is_agp(struct drm_device * dev) |
cda17380 DA |
1695 | { |
1696 | return 1; | |
1697 | } |