Commit | Line | Data |
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1da177e4 LT |
1 | /* i915_dma.c -- DMA support for the I915 -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
760285e7 DH |
31 | #include <drm/drmP.h> |
32 | #include <drm/drm_crtc_helper.h> | |
33 | #include <drm/drm_fb_helper.h> | |
4f03b1fc | 34 | #include <drm/drm_legacy.h> |
79e53945 | 35 | #include "intel_drv.h" |
760285e7 | 36 | #include <drm/i915_drm.h> |
1da177e4 | 37 | #include "i915_drv.h" |
e21fd552 | 38 | #include "i915_vgpu.h" |
1c5d22f7 | 39 | #include "i915_trace.h" |
dcdb1674 | 40 | #include <linux/pci.h> |
a4de0526 DV |
41 | #include <linux/console.h> |
42 | #include <linux/vt.h> | |
28d52043 | 43 | #include <linux/vgaarb.h> |
c4804411 ZW |
44 | #include <linux/acpi.h> |
45 | #include <linux/pnp.h> | |
6a9ee8af | 46 | #include <linux/vga_switcheroo.h> |
5a0e3ad6 | 47 | #include <linux/slab.h> |
44834a67 | 48 | #include <acpi/video.h> |
8a187455 PZ |
49 | #include <linux/pm.h> |
50 | #include <linux/pm_runtime.h> | |
4bdc7293 | 51 | #include <linux/oom.h> |
1da177e4 | 52 | |
4fec15d1 ID |
53 | static unsigned int i915_load_fail_count; |
54 | ||
55 | bool __i915_inject_load_failure(const char *func, int line) | |
56 | { | |
57 | if (i915_load_fail_count >= i915.inject_load_failure) | |
58 | return false; | |
59 | ||
60 | if (++i915_load_fail_count == i915.inject_load_failure) { | |
61 | DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n", | |
62 | i915.inject_load_failure, func, line); | |
63 | return true; | |
64 | } | |
65 | ||
66 | return false; | |
67 | } | |
1da177e4 | 68 | |
d15d7538 ID |
69 | #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI" |
70 | #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \ | |
71 | "providing the dmesg log by booting with drm.debug=0xf" | |
72 | ||
73 | void | |
74 | __i915_printk(struct drm_i915_private *dev_priv, const char *level, | |
75 | const char *fmt, ...) | |
76 | { | |
77 | static bool shown_bug_once; | |
78 | struct device *dev = dev_priv->dev->dev; | |
79 | bool is_error = level[1] <= KERN_ERR[1]; | |
ad45d839 | 80 | bool is_debug = level[1] == KERN_DEBUG[1]; |
d15d7538 ID |
81 | struct va_format vaf; |
82 | va_list args; | |
83 | ||
ad45d839 ID |
84 | if (is_debug && !(drm_debug & DRM_UT_DRIVER)) |
85 | return; | |
86 | ||
d15d7538 ID |
87 | va_start(args, fmt); |
88 | ||
89 | vaf.fmt = fmt; | |
90 | vaf.va = &args; | |
91 | ||
92 | dev_printk(level, dev, "[" DRM_NAME ":%ps] %pV", | |
93 | __builtin_return_address(0), &vaf); | |
94 | ||
95 | if (is_error && !shown_bug_once) { | |
96 | dev_notice(dev, "%s", FDO_BUG_MSG); | |
97 | shown_bug_once = true; | |
98 | } | |
99 | ||
100 | va_end(args); | |
101 | } | |
102 | ||
103 | static bool i915_error_injected(struct drm_i915_private *dev_priv) | |
104 | { | |
105 | return i915.inject_load_failure && | |
106 | i915_load_fail_count == i915.inject_load_failure; | |
107 | } | |
108 | ||
109 | #define i915_load_error(dev_priv, fmt, ...) \ | |
110 | __i915_printk(dev_priv, \ | |
111 | i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \ | |
112 | fmt, ##__VA_ARGS__) | |
113 | ||
c153f45f EA |
114 | static int i915_getparam(struct drm_device *dev, void *data, |
115 | struct drm_file *file_priv) | |
1da177e4 | 116 | { |
4c8a4be9 | 117 | struct drm_i915_private *dev_priv = dev->dev_private; |
c153f45f | 118 | drm_i915_getparam_t *param = data; |
1da177e4 LT |
119 | int value; |
120 | ||
c153f45f | 121 | switch (param->param) { |
1da177e4 | 122 | case I915_PARAM_IRQ_ACTIVE: |
1da177e4 | 123 | case I915_PARAM_ALLOW_BATCHBUFFER: |
0d6aa60b | 124 | case I915_PARAM_LAST_DISPATCH: |
ac883c84 | 125 | /* Reject all old ums/dri params. */ |
5c6c6003 | 126 | return -ENODEV; |
ed4c9c4a | 127 | case I915_PARAM_CHIPSET_ID: |
ffbab09b | 128 | value = dev->pdev->device; |
ed4c9c4a | 129 | break; |
27cd4461 NR |
130 | case I915_PARAM_REVISION: |
131 | value = dev->pdev->revision; | |
132 | break; | |
673a394b | 133 | case I915_PARAM_HAS_GEM: |
2e895b17 | 134 | value = 1; |
673a394b | 135 | break; |
0f973f27 | 136 | case I915_PARAM_NUM_FENCES_AVAIL: |
c668cde5 | 137 | value = dev_priv->num_fence_regs; |
0f973f27 | 138 | break; |
02e792fb DV |
139 | case I915_PARAM_HAS_OVERLAY: |
140 | value = dev_priv->overlay ? 1 : 0; | |
141 | break; | |
e9560f7c JB |
142 | case I915_PARAM_HAS_PAGEFLIPPING: |
143 | value = 1; | |
144 | break; | |
76446cac JB |
145 | case I915_PARAM_HAS_EXECBUF2: |
146 | /* depends on GEM */ | |
2e895b17 | 147 | value = 1; |
76446cac | 148 | break; |
e3a815fc | 149 | case I915_PARAM_HAS_BSD: |
117897f4 | 150 | value = intel_engine_initialized(&dev_priv->engine[VCS]); |
e3a815fc | 151 | break; |
549f7365 | 152 | case I915_PARAM_HAS_BLT: |
117897f4 | 153 | value = intel_engine_initialized(&dev_priv->engine[BCS]); |
549f7365 | 154 | break; |
a1f2cc73 | 155 | case I915_PARAM_HAS_VEBOX: |
117897f4 | 156 | value = intel_engine_initialized(&dev_priv->engine[VECS]); |
a1f2cc73 | 157 | break; |
08e16dc8 | 158 | case I915_PARAM_HAS_BSD2: |
117897f4 | 159 | value = intel_engine_initialized(&dev_priv->engine[VCS2]); |
08e16dc8 | 160 | break; |
a00b10c3 CW |
161 | case I915_PARAM_HAS_RELAXED_FENCING: |
162 | value = 1; | |
163 | break; | |
bbf0c6b3 DV |
164 | case I915_PARAM_HAS_COHERENT_RINGS: |
165 | value = 1; | |
166 | break; | |
72bfa19c CW |
167 | case I915_PARAM_HAS_EXEC_CONSTANTS: |
168 | value = INTEL_INFO(dev)->gen >= 4; | |
169 | break; | |
271d81b8 CW |
170 | case I915_PARAM_HAS_RELAXED_DELTA: |
171 | value = 1; | |
172 | break; | |
ae662d31 EA |
173 | case I915_PARAM_HAS_GEN7_SOL_RESET: |
174 | value = 1; | |
175 | break; | |
3d29b842 ED |
176 | case I915_PARAM_HAS_LLC: |
177 | value = HAS_LLC(dev); | |
178 | break; | |
651d794f CW |
179 | case I915_PARAM_HAS_WT: |
180 | value = HAS_WT(dev); | |
181 | break; | |
777ee96f | 182 | case I915_PARAM_HAS_ALIASING_PPGTT: |
896ab1a5 | 183 | value = USES_PPGTT(dev); |
777ee96f | 184 | break; |
172cf15d BW |
185 | case I915_PARAM_HAS_WAIT_TIMEOUT: |
186 | value = 1; | |
187 | break; | |
2fedbff9 | 188 | case I915_PARAM_HAS_SEMAPHORES: |
c033666a | 189 | value = i915_semaphore_is_enabled(dev_priv); |
2fedbff9 | 190 | break; |
ec6f1bb9 DA |
191 | case I915_PARAM_HAS_PRIME_VMAP_FLUSH: |
192 | value = 1; | |
193 | break; | |
d7d4eedd CW |
194 | case I915_PARAM_HAS_SECURE_BATCHES: |
195 | value = capable(CAP_SYS_ADMIN); | |
196 | break; | |
b45305fc DV |
197 | case I915_PARAM_HAS_PINNED_BATCHES: |
198 | value = 1; | |
199 | break; | |
ed5982e6 DV |
200 | case I915_PARAM_HAS_EXEC_NO_RELOC: |
201 | value = 1; | |
202 | break; | |
eef90ccb CW |
203 | case I915_PARAM_HAS_EXEC_HANDLE_LUT: |
204 | value = 1; | |
205 | break; | |
d728c8ef | 206 | case I915_PARAM_CMD_PARSER_VERSION: |
1ca3712c | 207 | value = i915_cmd_parser_get_version(dev_priv); |
d728c8ef | 208 | break; |
6a2c4232 CW |
209 | case I915_PARAM_HAS_COHERENT_PHYS_GTT: |
210 | value = 1; | |
1816f923 AG |
211 | break; |
212 | case I915_PARAM_MMAP_VERSION: | |
213 | value = 1; | |
6a2c4232 | 214 | break; |
a1559ffe JM |
215 | case I915_PARAM_SUBSLICE_TOTAL: |
216 | value = INTEL_INFO(dev)->subslice_total; | |
217 | if (!value) | |
218 | return -ENODEV; | |
219 | break; | |
220 | case I915_PARAM_EU_TOTAL: | |
221 | value = INTEL_INFO(dev)->eu_total; | |
222 | if (!value) | |
223 | return -ENODEV; | |
224 | break; | |
49e4d842 | 225 | case I915_PARAM_HAS_GPU_RESET: |
dc97997a | 226 | value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv); |
49e4d842 | 227 | break; |
a9ed33ca AJ |
228 | case I915_PARAM_HAS_RESOURCE_STREAMER: |
229 | value = HAS_RESOURCE_STREAMER(dev); | |
230 | break; | |
506a8e87 CW |
231 | case I915_PARAM_HAS_EXEC_SOFTPIN: |
232 | value = 1; | |
233 | break; | |
1da177e4 | 234 | default: |
e29c32da | 235 | DRM_DEBUG("Unknown parameter %d\n", param->param); |
20caafa6 | 236 | return -EINVAL; |
1da177e4 LT |
237 | } |
238 | ||
1d6ac185 DV |
239 | if (copy_to_user(param->value, &value, sizeof(int))) { |
240 | DRM_ERROR("copy_to_user failed\n"); | |
20caafa6 | 241 | return -EFAULT; |
1da177e4 LT |
242 | } |
243 | ||
244 | return 0; | |
245 | } | |
246 | ||
ec2a4c3f DA |
247 | static int i915_get_bridge_dev(struct drm_device *dev) |
248 | { | |
249 | struct drm_i915_private *dev_priv = dev->dev_private; | |
250 | ||
0206e353 | 251 | dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); |
ec2a4c3f DA |
252 | if (!dev_priv->bridge_dev) { |
253 | DRM_ERROR("bridge device not found\n"); | |
254 | return -1; | |
255 | } | |
256 | return 0; | |
257 | } | |
258 | ||
c4804411 ZW |
259 | /* Allocate space for the MCH regs if needed, return nonzero on error */ |
260 | static int | |
261 | intel_alloc_mchbar_resource(struct drm_device *dev) | |
262 | { | |
4c8a4be9 | 263 | struct drm_i915_private *dev_priv = dev->dev_private; |
a6c45cf0 | 264 | int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
265 | u32 temp_lo, temp_hi = 0; |
266 | u64 mchbar_addr; | |
a25c25c2 | 267 | int ret; |
c4804411 | 268 | |
a6c45cf0 | 269 | if (INTEL_INFO(dev)->gen >= 4) |
c4804411 ZW |
270 | pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); |
271 | pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); | |
272 | mchbar_addr = ((u64)temp_hi << 32) | temp_lo; | |
273 | ||
274 | /* If ACPI doesn't have it, assume we need to allocate it ourselves */ | |
275 | #ifdef CONFIG_PNP | |
276 | if (mchbar_addr && | |
a25c25c2 CW |
277 | pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) |
278 | return 0; | |
c4804411 ZW |
279 | #endif |
280 | ||
281 | /* Get some space for it */ | |
a25c25c2 CW |
282 | dev_priv->mch_res.name = "i915 MCHBAR"; |
283 | dev_priv->mch_res.flags = IORESOURCE_MEM; | |
284 | ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, | |
285 | &dev_priv->mch_res, | |
c4804411 ZW |
286 | MCHBAR_SIZE, MCHBAR_SIZE, |
287 | PCIBIOS_MIN_MEM, | |
a25c25c2 | 288 | 0, pcibios_align_resource, |
c4804411 ZW |
289 | dev_priv->bridge_dev); |
290 | if (ret) { | |
291 | DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret); | |
292 | dev_priv->mch_res.start = 0; | |
a25c25c2 | 293 | return ret; |
c4804411 ZW |
294 | } |
295 | ||
a6c45cf0 | 296 | if (INTEL_INFO(dev)->gen >= 4) |
c4804411 ZW |
297 | pci_write_config_dword(dev_priv->bridge_dev, reg + 4, |
298 | upper_32_bits(dev_priv->mch_res.start)); | |
299 | ||
300 | pci_write_config_dword(dev_priv->bridge_dev, reg, | |
301 | lower_32_bits(dev_priv->mch_res.start)); | |
a25c25c2 | 302 | return 0; |
c4804411 ZW |
303 | } |
304 | ||
305 | /* Setup MCHBAR if possible, return true if we should disable it again */ | |
306 | static void | |
307 | intel_setup_mchbar(struct drm_device *dev) | |
308 | { | |
4c8a4be9 | 309 | struct drm_i915_private *dev_priv = dev->dev_private; |
a6c45cf0 | 310 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
311 | u32 temp; |
312 | bool enabled; | |
313 | ||
666a4537 | 314 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
11ea8b7d JB |
315 | return; |
316 | ||
c4804411 ZW |
317 | dev_priv->mchbar_need_disable = false; |
318 | ||
319 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
e10fa551 | 320 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp); |
c4804411 ZW |
321 | enabled = !!(temp & DEVEN_MCHBAR_EN); |
322 | } else { | |
323 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
324 | enabled = temp & 1; | |
325 | } | |
326 | ||
327 | /* If it's already enabled, don't have to do anything */ | |
328 | if (enabled) | |
329 | return; | |
330 | ||
331 | if (intel_alloc_mchbar_resource(dev)) | |
332 | return; | |
333 | ||
334 | dev_priv->mchbar_need_disable = true; | |
335 | ||
336 | /* Space is allocated or reserved, so enable it. */ | |
337 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
e10fa551 | 338 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN, |
c4804411 ZW |
339 | temp | DEVEN_MCHBAR_EN); |
340 | } else { | |
341 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
342 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); | |
343 | } | |
344 | } | |
345 | ||
346 | static void | |
347 | intel_teardown_mchbar(struct drm_device *dev) | |
348 | { | |
4c8a4be9 | 349 | struct drm_i915_private *dev_priv = dev->dev_private; |
a6c45cf0 | 350 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
351 | |
352 | if (dev_priv->mchbar_need_disable) { | |
353 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
e10fa551 JL |
354 | u32 deven_val; |
355 | ||
356 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN, | |
357 | &deven_val); | |
358 | deven_val &= ~DEVEN_MCHBAR_EN; | |
359 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN, | |
360 | deven_val); | |
c4804411 | 361 | } else { |
e10fa551 JL |
362 | u32 mchbar_val; |
363 | ||
364 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, | |
365 | &mchbar_val); | |
366 | mchbar_val &= ~1; | |
367 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, | |
368 | mchbar_val); | |
c4804411 ZW |
369 | } |
370 | } | |
371 | ||
372 | if (dev_priv->mch_res.start) | |
373 | release_resource(&dev_priv->mch_res); | |
374 | } | |
375 | ||
28d52043 DA |
376 | /* true = enable decode, false = disable decoder */ |
377 | static unsigned int i915_vga_set_decode(void *cookie, bool state) | |
378 | { | |
379 | struct drm_device *dev = cookie; | |
380 | ||
381 | intel_modeset_vga_set_state(dev, state); | |
382 | if (state) | |
383 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
384 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
385 | else | |
386 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
387 | } | |
388 | ||
6a9ee8af DA |
389 | static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) |
390 | { | |
391 | struct drm_device *dev = pci_get_drvdata(pdev); | |
392 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; | |
1a5036bf | 393 | |
6a9ee8af | 394 | if (state == VGA_SWITCHEROO_ON) { |
a70491cc | 395 | pr_info("switched on\n"); |
5bcf719b | 396 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
6a9ee8af DA |
397 | /* i915 resume handler doesn't set to D0 */ |
398 | pci_set_power_state(dev->pdev, PCI_D0); | |
1751fcf9 | 399 | i915_resume_switcheroo(dev); |
5bcf719b | 400 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
6a9ee8af | 401 | } else { |
fa9d6078 | 402 | pr_info("switched off\n"); |
5bcf719b | 403 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
1751fcf9 | 404 | i915_suspend_switcheroo(dev, pmm); |
5bcf719b | 405 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
6a9ee8af DA |
406 | } |
407 | } | |
408 | ||
409 | static bool i915_switcheroo_can_switch(struct pci_dev *pdev) | |
410 | { | |
411 | struct drm_device *dev = pci_get_drvdata(pdev); | |
6a9ee8af | 412 | |
fc8fd40e DV |
413 | /* |
414 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
415 | * locking inversion with the driver load path. And the access here is | |
416 | * completely racy anyway. So don't bother with locking for now. | |
417 | */ | |
418 | return dev->open_count == 0; | |
6a9ee8af DA |
419 | } |
420 | ||
26ec685f TI |
421 | static const struct vga_switcheroo_client_ops i915_switcheroo_ops = { |
422 | .set_gpu_state = i915_switcheroo_set_state, | |
423 | .reprobe = NULL, | |
424 | .can_switch = i915_switcheroo_can_switch, | |
425 | }; | |
426 | ||
e7ae86ba CW |
427 | static void i915_gem_fini(struct drm_device *dev) |
428 | { | |
dc97997a CW |
429 | struct drm_i915_private *dev_priv = to_i915(dev); |
430 | ||
e7ae86ba CW |
431 | /* |
432 | * Neither the BIOS, ourselves or any other kernel | |
433 | * expects the system to be in execlists mode on startup, | |
434 | * so we need to reset the GPU back to legacy mode. And the only | |
435 | * known way to disable logical contexts is through a GPU reset. | |
436 | * | |
437 | * So in order to leave the system in a known default configuration, | |
438 | * always reset the GPU upon unload. Afterwards we then clean up the | |
439 | * GEM state tracking, flushing off the requests and leaving the | |
440 | * system in a known idle state. | |
441 | * | |
442 | * Note that is of the upmost importance that the GPU is idle and | |
443 | * all stray writes are flushed *before* we dismantle the backing | |
444 | * storage for the pinned objects. | |
445 | * | |
446 | * However, since we are uncertain that reseting the GPU on older | |
447 | * machines is a good idea, we don't - just in case it leaves the | |
448 | * machine in an unusable condition. | |
449 | */ | |
450 | if (HAS_HW_CONTEXTS(dev)) { | |
dc97997a | 451 | int reset = intel_gpu_reset(dev_priv, ALL_ENGINES); |
e7ae86ba CW |
452 | WARN_ON(reset && reset != -ENODEV); |
453 | } | |
454 | ||
455 | mutex_lock(&dev->struct_mutex); | |
456 | i915_gem_reset(dev); | |
457 | i915_gem_cleanup_engines(dev); | |
458 | i915_gem_context_fini(dev); | |
459 | mutex_unlock(&dev->struct_mutex); | |
460 | ||
461 | WARN_ON(!list_empty(&to_i915(dev)->context_list)); | |
462 | } | |
463 | ||
2c7111db CW |
464 | static int i915_load_modeset_init(struct drm_device *dev) |
465 | { | |
466 | struct drm_i915_private *dev_priv = dev->dev_private; | |
467 | int ret; | |
79e53945 | 468 | |
4fec15d1 ID |
469 | if (i915_inject_load_failure()) |
470 | return -ENODEV; | |
471 | ||
98f3a1dc | 472 | ret = intel_bios_init(dev_priv); |
79e53945 JB |
473 | if (ret) |
474 | DRM_INFO("failed to find VBIOS tables\n"); | |
475 | ||
934f992c CW |
476 | /* If we have > 1 VGA cards, then we need to arbitrate access |
477 | * to the common VGA resources. | |
478 | * | |
479 | * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA), | |
480 | * then we do not take part in VGA arbitration and the | |
481 | * vga_client_register() fails with -ENODEV. | |
482 | */ | |
ebff5fa9 DA |
483 | ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode); |
484 | if (ret && ret != -ENODEV) | |
485 | goto out; | |
28d52043 | 486 | |
723bfd70 JB |
487 | intel_register_dsm_handler(); |
488 | ||
0d69704a | 489 | ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false); |
6a9ee8af | 490 | if (ret) |
5a79395b | 491 | goto cleanup_vga_client; |
6a9ee8af | 492 | |
19ab4ed3 VS |
493 | /* must happen before intel_power_domains_init_hw() on VLV/CHV */ |
494 | intel_update_rawclk(dev_priv); | |
495 | ||
73dfc227 | 496 | intel_power_domains_init_hw(dev_priv, false); |
e13192f6 | 497 | |
f4448375 | 498 | intel_csr_ucode_init(dev_priv); |
ebae38d0 | 499 | |
2aeb7d3a | 500 | ret = intel_irq_install(dev_priv); |
52d7eced | 501 | if (ret) |
89250fec | 502 | goto cleanup_csr; |
52d7eced | 503 | |
f5949141 DV |
504 | intel_setup_gmbus(dev); |
505 | ||
52d7eced DV |
506 | /* Important: The output setup functions called by modeset_init need |
507 | * working irqs for e.g. gmbus and dp aux transfers. */ | |
b01f2c3a JB |
508 | intel_modeset_init(dev); |
509 | ||
f09d675f | 510 | intel_guc_init(dev); |
33a732f4 | 511 | |
1070a42b | 512 | ret = i915_gem_init(dev); |
79e53945 | 513 | if (ret) |
713028b3 | 514 | goto cleanup_irq; |
2c7111db | 515 | |
52d7eced | 516 | intel_modeset_gem_init(dev); |
2c7111db | 517 | |
713028b3 | 518 | if (INTEL_INFO(dev)->num_pipes == 0) |
e3c74757 | 519 | return 0; |
79e53945 | 520 | |
5a79395b CW |
521 | ret = intel_fbdev_init(dev); |
522 | if (ret) | |
52d7eced DV |
523 | goto cleanup_gem; |
524 | ||
20afbda2 | 525 | /* Only enable hotplug handling once the fbdev is fully set up. */ |
b963291c | 526 | intel_hpd_init(dev_priv); |
20afbda2 | 527 | |
eb1f8e4f | 528 | drm_kms_helper_poll_init(dev); |
87acb0a5 | 529 | |
79e53945 JB |
530 | return 0; |
531 | ||
2c7111db | 532 | cleanup_gem: |
e7ae86ba | 533 | i915_gem_fini(dev); |
713028b3 | 534 | cleanup_irq: |
f09d675f | 535 | intel_guc_fini(dev); |
52d7eced | 536 | drm_irq_uninstall(dev); |
f5949141 | 537 | intel_teardown_gmbus(dev); |
89250fec ID |
538 | cleanup_csr: |
539 | intel_csr_ucode_fini(dev_priv); | |
65ff442f | 540 | intel_power_domains_fini(dev_priv); |
5a79395b CW |
541 | vga_switcheroo_unregister_client(dev->pdev); |
542 | cleanup_vga_client: | |
543 | vga_client_register(dev->pdev, NULL, NULL, NULL); | |
79e53945 JB |
544 | out: |
545 | return ret; | |
546 | } | |
547 | ||
243eaf38 | 548 | #if IS_ENABLED(CONFIG_FB) |
f96de58f | 549 | static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) |
e188719a DV |
550 | { |
551 | struct apertures_struct *ap; | |
552 | struct pci_dev *pdev = dev_priv->dev->pdev; | |
72e96d64 | 553 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
e188719a | 554 | bool primary; |
f96de58f | 555 | int ret; |
e188719a DV |
556 | |
557 | ap = alloc_apertures(1); | |
558 | if (!ap) | |
f96de58f | 559 | return -ENOMEM; |
e188719a | 560 | |
72e96d64 JL |
561 | ap->ranges[0].base = ggtt->mappable_base; |
562 | ap->ranges[0].size = ggtt->mappable_end; | |
93d18799 | 563 | |
e188719a DV |
564 | primary = |
565 | pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; | |
566 | ||
f96de58f | 567 | ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary); |
e188719a DV |
568 | |
569 | kfree(ap); | |
f96de58f CW |
570 | |
571 | return ret; | |
e188719a | 572 | } |
4520f53a | 573 | #else |
f96de58f | 574 | static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) |
4520f53a | 575 | { |
f96de58f | 576 | return 0; |
4520f53a DV |
577 | } |
578 | #endif | |
e188719a | 579 | |
a4de0526 DV |
580 | #if !defined(CONFIG_VGA_CONSOLE) |
581 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) | |
582 | { | |
583 | return 0; | |
584 | } | |
585 | #elif !defined(CONFIG_DUMMY_CONSOLE) | |
586 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) | |
587 | { | |
588 | return -ENODEV; | |
589 | } | |
590 | #else | |
591 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) | |
592 | { | |
1bb9e632 | 593 | int ret = 0; |
a4de0526 DV |
594 | |
595 | DRM_INFO("Replacing VGA console driver\n"); | |
596 | ||
597 | console_lock(); | |
1bb9e632 DV |
598 | if (con_is_bound(&vga_con)) |
599 | ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1); | |
a4de0526 DV |
600 | if (ret == 0) { |
601 | ret = do_unregister_con_driver(&vga_con); | |
602 | ||
603 | /* Ignore "already unregistered". */ | |
604 | if (ret == -ENODEV) | |
605 | ret = 0; | |
606 | } | |
607 | console_unlock(); | |
608 | ||
609 | return ret; | |
610 | } | |
611 | #endif | |
612 | ||
c96ea64e DV |
613 | static void i915_dump_device_info(struct drm_i915_private *dev_priv) |
614 | { | |
5c969aa7 | 615 | const struct intel_device_info *info = &dev_priv->info; |
c96ea64e | 616 | |
e2a5800a DL |
617 | #define PRINT_S(name) "%s" |
618 | #define SEP_EMPTY | |
79fc46df DL |
619 | #define PRINT_FLAG(name) info->name ? #name "," : "" |
620 | #define SEP_COMMA , | |
19c656a1 | 621 | DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags=" |
e2a5800a | 622 | DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY), |
c96ea64e DV |
623 | info->gen, |
624 | dev_priv->dev->pdev->device, | |
19c656a1 | 625 | dev_priv->dev->pdev->revision, |
79fc46df | 626 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA)); |
e2a5800a DL |
627 | #undef PRINT_S |
628 | #undef SEP_EMPTY | |
79fc46df DL |
629 | #undef PRINT_FLAG |
630 | #undef SEP_COMMA | |
c96ea64e DV |
631 | } |
632 | ||
9705ad8a JM |
633 | static void cherryview_sseu_info_init(struct drm_device *dev) |
634 | { | |
635 | struct drm_i915_private *dev_priv = dev->dev_private; | |
636 | struct intel_device_info *info; | |
637 | u32 fuse, eu_dis; | |
638 | ||
639 | info = (struct intel_device_info *)&dev_priv->info; | |
640 | fuse = I915_READ(CHV_FUSE_GT); | |
641 | ||
642 | info->slice_total = 1; | |
643 | ||
644 | if (!(fuse & CHV_FGT_DISABLE_SS0)) { | |
645 | info->subslice_per_slice++; | |
646 | eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK | | |
647 | CHV_FGT_EU_DIS_SS0_R1_MASK); | |
648 | info->eu_total += 8 - hweight32(eu_dis); | |
649 | } | |
650 | ||
651 | if (!(fuse & CHV_FGT_DISABLE_SS1)) { | |
652 | info->subslice_per_slice++; | |
653 | eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK | | |
654 | CHV_FGT_EU_DIS_SS1_R1_MASK); | |
655 | info->eu_total += 8 - hweight32(eu_dis); | |
656 | } | |
657 | ||
658 | info->subslice_total = info->subslice_per_slice; | |
659 | /* | |
660 | * CHV expected to always have a uniform distribution of EU | |
661 | * across subslices. | |
662 | */ | |
663 | info->eu_per_subslice = info->subslice_total ? | |
664 | info->eu_total / info->subslice_total : | |
665 | 0; | |
666 | /* | |
667 | * CHV supports subslice power gating on devices with more than | |
668 | * one subslice, and supports EU power gating on devices with | |
669 | * more than one EU pair per subslice. | |
670 | */ | |
671 | info->has_slice_pg = 0; | |
672 | info->has_subslice_pg = (info->subslice_total > 1); | |
673 | info->has_eu_pg = (info->eu_per_subslice > 2); | |
674 | } | |
675 | ||
676 | static void gen9_sseu_info_init(struct drm_device *dev) | |
677 | { | |
678 | struct drm_i915_private *dev_priv = dev->dev_private; | |
679 | struct intel_device_info *info; | |
dead16e2 | 680 | int s_max = 3, ss_max = 4, eu_max = 8; |
9705ad8a | 681 | int s, ss; |
dead16e2 JM |
682 | u32 fuse2, s_enable, ss_disable, eu_disable; |
683 | u8 eu_mask = 0xff; | |
684 | ||
9705ad8a JM |
685 | info = (struct intel_device_info *)&dev_priv->info; |
686 | fuse2 = I915_READ(GEN8_FUSE2); | |
687 | s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> | |
688 | GEN8_F2_S_ENA_SHIFT; | |
689 | ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >> | |
690 | GEN9_F2_SS_DIS_SHIFT; | |
691 | ||
9705ad8a JM |
692 | info->slice_total = hweight32(s_enable); |
693 | /* | |
694 | * The subslice disable field is global, i.e. it applies | |
695 | * to each of the enabled slices. | |
696 | */ | |
697 | info->subslice_per_slice = ss_max - hweight32(ss_disable); | |
698 | info->subslice_total = info->slice_total * | |
699 | info->subslice_per_slice; | |
700 | ||
701 | /* | |
702 | * Iterate through enabled slices and subslices to | |
703 | * count the total enabled EU. | |
704 | */ | |
705 | for (s = 0; s < s_max; s++) { | |
706 | if (!(s_enable & (0x1 << s))) | |
707 | /* skip disabled slice */ | |
708 | continue; | |
709 | ||
dead16e2 | 710 | eu_disable = I915_READ(GEN9_EU_DISABLE(s)); |
9705ad8a | 711 | for (ss = 0; ss < ss_max; ss++) { |
dead16e2 | 712 | int eu_per_ss; |
9705ad8a JM |
713 | |
714 | if (ss_disable & (0x1 << ss)) | |
715 | /* skip disabled subslice */ | |
716 | continue; | |
717 | ||
dead16e2 JM |
718 | eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) & |
719 | eu_mask); | |
9705ad8a JM |
720 | |
721 | /* | |
722 | * Record which subslice(s) has(have) 7 EUs. we | |
723 | * can tune the hash used to spread work among | |
724 | * subslices if they are unbalanced. | |
725 | */ | |
dead16e2 | 726 | if (eu_per_ss == 7) |
9705ad8a JM |
727 | info->subslice_7eu[s] |= 1 << ss; |
728 | ||
dead16e2 | 729 | info->eu_total += eu_per_ss; |
9705ad8a JM |
730 | } |
731 | } | |
732 | ||
733 | /* | |
734 | * SKL is expected to always have a uniform distribution | |
735 | * of EU across subslices with the exception that any one | |
736 | * EU in any one subslice may be fused off for die | |
dead16e2 JM |
737 | * recovery. BXT is expected to be perfectly uniform in EU |
738 | * distribution. | |
9705ad8a JM |
739 | */ |
740 | info->eu_per_subslice = info->subslice_total ? | |
741 | DIV_ROUND_UP(info->eu_total, | |
742 | info->subslice_total) : 0; | |
743 | /* | |
744 | * SKL supports slice power gating on devices with more than | |
745 | * one slice, and supports EU power gating on devices with | |
dead16e2 JM |
746 | * more than one EU pair per subslice. BXT supports subslice |
747 | * power gating on devices with more than one subslice, and | |
748 | * supports EU power gating on devices with more than one EU | |
749 | * pair per subslice. | |
9705ad8a | 750 | */ |
ef11bdb3 RV |
751 | info->has_slice_pg = ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && |
752 | (info->slice_total > 1)); | |
dead16e2 JM |
753 | info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1)); |
754 | info->has_eu_pg = (info->eu_per_subslice > 2); | |
33e141ed | 755 | |
756 | if (IS_BROXTON(dev)) { | |
757 | #define IS_SS_DISABLED(_ss_disable, ss) (_ss_disable & (0x1 << ss)) | |
e015dd69 | 758 | /* |
759 | * There is a HW issue in 2x6 fused down parts that requires | |
760 | * Pooled EU to be enabled as a WA. The pool configuration | |
761 | * changes depending upon which subslice is fused down. This | |
762 | * doesn't affect if the device has all 3 subslices enabled. | |
763 | */ | |
764 | /* WaEnablePooledEuFor2x6:bxt */ | |
765 | info->has_pooled_eu = ((info->subslice_per_slice == 3) || | |
766 | (info->subslice_per_slice == 2 && | |
767 | INTEL_REVID(dev) < BXT_REVID_C0)); | |
33e141ed | 768 | |
769 | info->min_eu_in_pool = 0; | |
770 | if (info->has_pooled_eu) { | |
771 | if (IS_SS_DISABLED(ss_disable, 0) || | |
772 | IS_SS_DISABLED(ss_disable, 2)) | |
773 | info->min_eu_in_pool = 3; | |
774 | else if (IS_SS_DISABLED(ss_disable, 1)) | |
775 | info->min_eu_in_pool = 6; | |
776 | else | |
777 | info->min_eu_in_pool = 9; | |
778 | } | |
779 | #undef IS_SS_DISABLED | |
780 | } | |
9705ad8a JM |
781 | } |
782 | ||
91bedd34 ŁD |
783 | static void broadwell_sseu_info_init(struct drm_device *dev) |
784 | { | |
785 | struct drm_i915_private *dev_priv = dev->dev_private; | |
786 | struct intel_device_info *info; | |
787 | const int s_max = 3, ss_max = 3, eu_max = 8; | |
788 | int s, ss; | |
789 | u32 fuse2, eu_disable[s_max], s_enable, ss_disable; | |
790 | ||
791 | fuse2 = I915_READ(GEN8_FUSE2); | |
792 | s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; | |
793 | ss_disable = (fuse2 & GEN8_F2_SS_DIS_MASK) >> GEN8_F2_SS_DIS_SHIFT; | |
794 | ||
795 | eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK; | |
796 | eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) | | |
797 | ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) << | |
798 | (32 - GEN8_EU_DIS0_S1_SHIFT)); | |
799 | eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) | | |
800 | ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) << | |
801 | (32 - GEN8_EU_DIS1_S2_SHIFT)); | |
802 | ||
803 | ||
804 | info = (struct intel_device_info *)&dev_priv->info; | |
805 | info->slice_total = hweight32(s_enable); | |
806 | ||
807 | /* | |
808 | * The subslice disable field is global, i.e. it applies | |
809 | * to each of the enabled slices. | |
810 | */ | |
811 | info->subslice_per_slice = ss_max - hweight32(ss_disable); | |
812 | info->subslice_total = info->slice_total * info->subslice_per_slice; | |
813 | ||
814 | /* | |
815 | * Iterate through enabled slices and subslices to | |
816 | * count the total enabled EU. | |
817 | */ | |
818 | for (s = 0; s < s_max; s++) { | |
819 | if (!(s_enable & (0x1 << s))) | |
820 | /* skip disabled slice */ | |
821 | continue; | |
822 | ||
823 | for (ss = 0; ss < ss_max; ss++) { | |
824 | u32 n_disabled; | |
825 | ||
826 | if (ss_disable & (0x1 << ss)) | |
827 | /* skip disabled subslice */ | |
828 | continue; | |
829 | ||
830 | n_disabled = hweight8(eu_disable[s] >> (ss * eu_max)); | |
831 | ||
832 | /* | |
833 | * Record which subslices have 7 EUs. | |
834 | */ | |
835 | if (eu_max - n_disabled == 7) | |
836 | info->subslice_7eu[s] |= 1 << ss; | |
837 | ||
838 | info->eu_total += eu_max - n_disabled; | |
839 | } | |
840 | } | |
841 | ||
842 | /* | |
843 | * BDW is expected to always have a uniform distribution of EU across | |
844 | * subslices with the exception that any one EU in any one subslice may | |
845 | * be fused off for die recovery. | |
846 | */ | |
847 | info->eu_per_subslice = info->subslice_total ? | |
848 | DIV_ROUND_UP(info->eu_total, info->subslice_total) : 0; | |
849 | ||
850 | /* | |
851 | * BDW supports slice power gating on devices with more than | |
852 | * one slice. | |
853 | */ | |
854 | info->has_slice_pg = (info->slice_total > 1); | |
855 | info->has_subslice_pg = 0; | |
856 | info->has_eu_pg = 0; | |
857 | } | |
858 | ||
22d3fd46 DL |
859 | /* |
860 | * Determine various intel_device_info fields at runtime. | |
861 | * | |
862 | * Use it when either: | |
863 | * - it's judged too laborious to fill n static structures with the limit | |
864 | * when a simple if statement does the job, | |
865 | * - run-time checks (eg read fuse/strap registers) are needed. | |
658ac4c6 DL |
866 | * |
867 | * This function needs to be called: | |
868 | * - after the MMIO has been setup as we are reading registers, | |
869 | * - after the PCH has been detected, | |
870 | * - before the first usage of the fields it can tweak. | |
22d3fd46 DL |
871 | */ |
872 | static void intel_device_info_runtime_init(struct drm_device *dev) | |
873 | { | |
658ac4c6 | 874 | struct drm_i915_private *dev_priv = dev->dev_private; |
22d3fd46 | 875 | struct intel_device_info *info; |
d615a166 | 876 | enum pipe pipe; |
22d3fd46 | 877 | |
658ac4c6 | 878 | info = (struct intel_device_info *)&dev_priv->info; |
22d3fd46 | 879 | |
edd43ed8 DL |
880 | /* |
881 | * Skylake and Broxton currently don't expose the topmost plane as its | |
882 | * use is exclusive with the legacy cursor and we only want to expose | |
883 | * one of those, not both. Until we can safely expose the topmost plane | |
884 | * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported, | |
885 | * we don't expose the topmost plane at all to prevent ABI breakage | |
886 | * down the line. | |
887 | */ | |
8fb9397d | 888 | if (IS_BROXTON(dev)) { |
edd43ed8 DL |
889 | info->num_sprites[PIPE_A] = 2; |
890 | info->num_sprites[PIPE_B] = 2; | |
891 | info->num_sprites[PIPE_C] = 1; | |
666a4537 | 892 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
055e393f | 893 | for_each_pipe(dev_priv, pipe) |
d615a166 DL |
894 | info->num_sprites[pipe] = 2; |
895 | else | |
055e393f | 896 | for_each_pipe(dev_priv, pipe) |
d615a166 | 897 | info->num_sprites[pipe] = 1; |
658ac4c6 | 898 | |
a0bae57f DL |
899 | if (i915.disable_display) { |
900 | DRM_INFO("Display disabled (module parameter)\n"); | |
901 | info->num_pipes = 0; | |
902 | } else if (info->num_pipes > 0 && | |
7e22dbbb | 903 | (IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) && |
a7e478c7 | 904 | HAS_PCH_SPLIT(dev)) { |
658ac4c6 DL |
905 | u32 fuse_strap = I915_READ(FUSE_STRAP); |
906 | u32 sfuse_strap = I915_READ(SFUSE_STRAP); | |
907 | ||
908 | /* | |
909 | * SFUSE_STRAP is supposed to have a bit signalling the display | |
910 | * is fused off. Unfortunately it seems that, at least in | |
911 | * certain cases, fused off display means that PCH display | |
912 | * reads don't land anywhere. In that case, we read 0s. | |
913 | * | |
914 | * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK | |
915 | * should be set when taking over after the firmware. | |
916 | */ | |
917 | if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || | |
918 | sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || | |
919 | (dev_priv->pch_type == PCH_CPT && | |
920 | !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { | |
921 | DRM_INFO("Display fused off, disabling\n"); | |
922 | info->num_pipes = 0; | |
8c448cad GF |
923 | } else if (fuse_strap & IVB_PIPE_C_DISABLE) { |
924 | DRM_INFO("PipeC fused off\n"); | |
925 | info->num_pipes -= 1; | |
658ac4c6 | 926 | } |
7e22dbbb | 927 | } else if (info->num_pipes > 0 && IS_GEN9(dev_priv)) { |
bf4f2fb0 PJ |
928 | u32 dfsm = I915_READ(SKL_DFSM); |
929 | u8 disabled_mask = 0; | |
930 | bool invalid; | |
931 | int num_bits; | |
932 | ||
933 | if (dfsm & SKL_DFSM_PIPE_A_DISABLE) | |
934 | disabled_mask |= BIT(PIPE_A); | |
935 | if (dfsm & SKL_DFSM_PIPE_B_DISABLE) | |
936 | disabled_mask |= BIT(PIPE_B); | |
937 | if (dfsm & SKL_DFSM_PIPE_C_DISABLE) | |
938 | disabled_mask |= BIT(PIPE_C); | |
939 | ||
940 | num_bits = hweight8(disabled_mask); | |
941 | ||
942 | switch (disabled_mask) { | |
943 | case BIT(PIPE_A): | |
944 | case BIT(PIPE_B): | |
945 | case BIT(PIPE_A) | BIT(PIPE_B): | |
946 | case BIT(PIPE_A) | BIT(PIPE_C): | |
947 | invalid = true; | |
948 | break; | |
949 | default: | |
950 | invalid = false; | |
951 | } | |
952 | ||
953 | if (num_bits > info->num_pipes || invalid) | |
954 | DRM_ERROR("invalid pipe fuse configuration: 0x%x\n", | |
955 | disabled_mask); | |
956 | else | |
957 | info->num_pipes -= num_bits; | |
658ac4c6 | 958 | } |
693d11c3 | 959 | |
3873218f | 960 | /* Initialize slice/subslice/EU info */ |
9705ad8a JM |
961 | if (IS_CHERRYVIEW(dev)) |
962 | cherryview_sseu_info_init(dev); | |
91bedd34 ŁD |
963 | else if (IS_BROADWELL(dev)) |
964 | broadwell_sseu_info_init(dev); | |
dead16e2 | 965 | else if (INTEL_INFO(dev)->gen >= 9) |
9705ad8a | 966 | gen9_sseu_info_init(dev); |
3873218f | 967 | |
ca377809 | 968 | info->has_snoop = !info->has_llc; |
e8fcdf1e JN |
969 | |
970 | /* Snooping is broken on BXT A stepping. */ | |
971 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) | |
972 | info->has_snoop = false; | |
ca377809 | 973 | |
3873218f JM |
974 | DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total); |
975 | DRM_DEBUG_DRIVER("subslice total: %u\n", info->subslice_total); | |
976 | DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice); | |
977 | DRM_DEBUG_DRIVER("EU total: %u\n", info->eu_total); | |
978 | DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->eu_per_subslice); | |
33e141ed | 979 | DRM_DEBUG_DRIVER("Has Pooled EU: %s\n", HAS_POOLED_EU(dev) ? "y" : "n"); |
980 | if (HAS_POOLED_EU(dev)) | |
981 | DRM_DEBUG_DRIVER("Min EU in pool: %u\n", info->min_eu_in_pool); | |
3873218f JM |
982 | DRM_DEBUG_DRIVER("has slice power gating: %s\n", |
983 | info->has_slice_pg ? "y" : "n"); | |
984 | DRM_DEBUG_DRIVER("has subslice power gating: %s\n", | |
985 | info->has_subslice_pg ? "y" : "n"); | |
986 | DRM_DEBUG_DRIVER("has EU power gating: %s\n", | |
987 | info->has_eu_pg ? "y" : "n"); | |
0e4ca100 CW |
988 | |
989 | i915.enable_execlists = | |
c033666a CW |
990 | intel_sanitize_enable_execlists(dev_priv, |
991 | i915.enable_execlists); | |
0e4ca100 CW |
992 | |
993 | /* | |
994 | * i915.enable_ppgtt is read-only, so do an early pass to validate the | |
995 | * user's requested state against the hardware/driver capabilities. We | |
996 | * do this now so that we can print out any log messages once rather | |
997 | * than every time we check intel_enable_ppgtt(). | |
998 | */ | |
999 | i915.enable_ppgtt = | |
c033666a | 1000 | intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt); |
0e4ca100 | 1001 | DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt); |
22d3fd46 DL |
1002 | } |
1003 | ||
e27f299e VS |
1004 | static void intel_init_dpio(struct drm_i915_private *dev_priv) |
1005 | { | |
e27f299e VS |
1006 | /* |
1007 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
1008 | * CHV x1 PHY (DP/HDMI D) | |
1009 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
1010 | */ | |
1011 | if (IS_CHERRYVIEW(dev_priv)) { | |
1012 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
1013 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
666a4537 | 1014 | } else if (IS_VALLEYVIEW(dev_priv)) { |
e27f299e VS |
1015 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; |
1016 | } | |
1017 | } | |
1018 | ||
399bb5b6 ID |
1019 | static int i915_workqueues_init(struct drm_i915_private *dev_priv) |
1020 | { | |
1021 | /* | |
1022 | * The i915 workqueue is primarily used for batched retirement of | |
1023 | * requests (and thus managing bo) once the task has been completed | |
1024 | * by the GPU. i915_gem_retire_requests() is called directly when we | |
1025 | * need high-priority retirement, such as waiting for an explicit | |
1026 | * bo. | |
1027 | * | |
1028 | * It is also used for periodic low-priority events, such as | |
1029 | * idle-timers and recording error state. | |
1030 | * | |
1031 | * All tasks on the workqueue are expected to acquire the dev mutex | |
1032 | * so there is no point in running more than one instance of the | |
1033 | * workqueue at any time. Use an ordered one. | |
1034 | */ | |
1035 | dev_priv->wq = alloc_ordered_workqueue("i915", 0); | |
1036 | if (dev_priv->wq == NULL) | |
1037 | goto out_err; | |
1038 | ||
1039 | dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0); | |
1040 | if (dev_priv->hotplug.dp_wq == NULL) | |
1041 | goto out_free_wq; | |
1042 | ||
1043 | dev_priv->gpu_error.hangcheck_wq = | |
1044 | alloc_ordered_workqueue("i915-hangcheck", 0); | |
1045 | if (dev_priv->gpu_error.hangcheck_wq == NULL) | |
1046 | goto out_free_dp_wq; | |
1047 | ||
1048 | return 0; | |
1049 | ||
1050 | out_free_dp_wq: | |
1051 | destroy_workqueue(dev_priv->hotplug.dp_wq); | |
1052 | out_free_wq: | |
1053 | destroy_workqueue(dev_priv->wq); | |
1054 | out_err: | |
1055 | DRM_ERROR("Failed to allocate workqueues.\n"); | |
1056 | ||
1057 | return -ENOMEM; | |
1058 | } | |
1059 | ||
1060 | static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv) | |
1061 | { | |
1062 | destroy_workqueue(dev_priv->gpu_error.hangcheck_wq); | |
1063 | destroy_workqueue(dev_priv->hotplug.dp_wq); | |
1064 | destroy_workqueue(dev_priv->wq); | |
1065 | } | |
1066 | ||
5d7a6eef ID |
1067 | /** |
1068 | * i915_driver_init_early - setup state not requiring device access | |
1069 | * @dev_priv: device private | |
1070 | * | |
1071 | * Initialize everything that is a "SW-only" state, that is state not | |
1072 | * requiring accessing the device or exposing the driver via kernel internal | |
1073 | * or userspace interfaces. Example steps belonging here: lock initialization, | |
1074 | * system memory allocation, setting up device specific attributes and | |
1075 | * function hooks not requiring accessing the device. | |
1076 | */ | |
1077 | static int i915_driver_init_early(struct drm_i915_private *dev_priv, | |
8f460e2c | 1078 | const struct pci_device_id *ent) |
5d7a6eef | 1079 | { |
8f460e2c CW |
1080 | const struct intel_device_info *match_info = |
1081 | (struct intel_device_info *)ent->driver_data; | |
5d7a6eef ID |
1082 | struct intel_device_info *device_info; |
1083 | int ret = 0; | |
1084 | ||
4fec15d1 ID |
1085 | if (i915_inject_load_failure()) |
1086 | return -ENODEV; | |
1087 | ||
5d7a6eef ID |
1088 | /* Setup the write-once "constant" device info */ |
1089 | device_info = (struct intel_device_info *)&dev_priv->info; | |
8f460e2c CW |
1090 | memcpy(device_info, match_info, sizeof(*device_info)); |
1091 | device_info->device_id = dev_priv->drm.pdev->device; | |
5d7a6eef | 1092 | |
ae5702d2 TU |
1093 | BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE); |
1094 | device_info->gen_mask = BIT(device_info->gen - 1); | |
1095 | ||
5d7a6eef ID |
1096 | spin_lock_init(&dev_priv->irq_lock); |
1097 | spin_lock_init(&dev_priv->gpu_error.lock); | |
1098 | mutex_init(&dev_priv->backlight_lock); | |
1099 | spin_lock_init(&dev_priv->uncore.lock); | |
1100 | spin_lock_init(&dev_priv->mm.object_stat_lock); | |
1101 | spin_lock_init(&dev_priv->mmio_flip_lock); | |
1102 | mutex_init(&dev_priv->sb_lock); | |
1103 | mutex_init(&dev_priv->modeset_restore_lock); | |
1104 | mutex_init(&dev_priv->av_mutex); | |
1105 | mutex_init(&dev_priv->wm.wm_mutex); | |
1106 | mutex_init(&dev_priv->pps_mutex); | |
1107 | ||
1108 | ret = i915_workqueues_init(dev_priv); | |
1109 | if (ret < 0) | |
1110 | return ret; | |
1111 | ||
0ad35fed ZW |
1112 | ret = intel_gvt_init(dev_priv); |
1113 | if (ret < 0) | |
1114 | goto err_workqueues; | |
1115 | ||
5d7a6eef | 1116 | /* This must be called before any calls to HAS_PCH_* */ |
8f460e2c | 1117 | intel_detect_pch(&dev_priv->drm); |
5d7a6eef | 1118 | |
8f460e2c | 1119 | intel_pm_setup(&dev_priv->drm); |
5d7a6eef ID |
1120 | intel_init_dpio(dev_priv); |
1121 | intel_power_domains_init(dev_priv); | |
1122 | intel_irq_init(dev_priv); | |
1123 | intel_init_display_hooks(dev_priv); | |
1124 | intel_init_clock_gating_hooks(dev_priv); | |
1125 | intel_init_audio_hooks(dev_priv); | |
8f460e2c | 1126 | i915_gem_load_init(&dev_priv->drm); |
5d7a6eef | 1127 | |
8f460e2c | 1128 | intel_display_crc_init(&dev_priv->drm); |
5d7a6eef ID |
1129 | |
1130 | i915_dump_device_info(dev_priv); | |
1131 | ||
1132 | /* Not all pre-production machines fall into this category, only the | |
1133 | * very first ones. Almost everything should work, except for maybe | |
1134 | * suspend/resume. And we don't implement workarounds that affect only | |
1135 | * pre-production machines. */ | |
8f460e2c | 1136 | if (IS_HSW_EARLY_SDV(dev_priv)) |
5d7a6eef ID |
1137 | DRM_INFO("This is an early pre-production Haswell machine. " |
1138 | "It may not be fully functional.\n"); | |
1139 | ||
1140 | return 0; | |
0ad35fed ZW |
1141 | |
1142 | err_workqueues: | |
1143 | i915_workqueues_cleanup(dev_priv); | |
1144 | return ret; | |
5d7a6eef ID |
1145 | } |
1146 | ||
1147 | /** | |
1148 | * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early() | |
1149 | * @dev_priv: device private | |
1150 | */ | |
1151 | static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv) | |
1152 | { | |
1153 | i915_gem_load_cleanup(dev_priv->dev); | |
1154 | i915_workqueues_cleanup(dev_priv); | |
1155 | } | |
1156 | ||
ad5c3d3f ID |
1157 | static int i915_mmio_setup(struct drm_device *dev) |
1158 | { | |
1159 | struct drm_i915_private *dev_priv = to_i915(dev); | |
1160 | int mmio_bar; | |
1161 | int mmio_size; | |
1162 | ||
1163 | mmio_bar = IS_GEN2(dev) ? 1 : 0; | |
1164 | /* | |
1165 | * Before gen4, the registers and the GTT are behind different BARs. | |
1166 | * However, from gen4 onwards, the registers and the GTT are shared | |
1167 | * in the same BAR, so we want to restrict this ioremap from | |
1168 | * clobbering the GTT which we want ioremap_wc instead. Fortunately, | |
1169 | * the register BAR remains the same size for all the earlier | |
1170 | * generations up to Ironlake. | |
1171 | */ | |
1172 | if (INTEL_INFO(dev)->gen < 5) | |
1173 | mmio_size = 512 * 1024; | |
1174 | else | |
1175 | mmio_size = 2 * 1024 * 1024; | |
1176 | dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size); | |
1177 | if (dev_priv->regs == NULL) { | |
1178 | DRM_ERROR("failed to map registers\n"); | |
1179 | ||
1180 | return -EIO; | |
1181 | } | |
1182 | ||
1183 | /* Try to make sure MCHBAR is enabled before poking at it */ | |
1184 | intel_setup_mchbar(dev); | |
1185 | ||
1186 | return 0; | |
1187 | } | |
1188 | ||
1189 | static void i915_mmio_cleanup(struct drm_device *dev) | |
1190 | { | |
1191 | struct drm_i915_private *dev_priv = to_i915(dev); | |
1192 | ||
1193 | intel_teardown_mchbar(dev); | |
1194 | pci_iounmap(dev->pdev, dev_priv->regs); | |
1195 | } | |
1196 | ||
f28cea45 ID |
1197 | /** |
1198 | * i915_driver_init_mmio - setup device MMIO | |
1199 | * @dev_priv: device private | |
1200 | * | |
1201 | * Setup minimal device state necessary for MMIO accesses later in the | |
1202 | * initialization sequence. The setup here should avoid any other device-wide | |
1203 | * side effects or exposing the driver via kernel internal or user space | |
1204 | * interfaces. | |
1205 | */ | |
1206 | static int i915_driver_init_mmio(struct drm_i915_private *dev_priv) | |
1207 | { | |
1208 | struct drm_device *dev = dev_priv->dev; | |
1209 | int ret; | |
1210 | ||
4fec15d1 ID |
1211 | if (i915_inject_load_failure()) |
1212 | return -ENODEV; | |
1213 | ||
f28cea45 ID |
1214 | if (i915_get_bridge_dev(dev)) |
1215 | return -EIO; | |
1216 | ||
1217 | ret = i915_mmio_setup(dev); | |
1218 | if (ret < 0) | |
1219 | goto put_bridge; | |
1220 | ||
dc97997a | 1221 | intel_uncore_init(dev_priv); |
f28cea45 ID |
1222 | |
1223 | return 0; | |
1224 | ||
1225 | put_bridge: | |
1226 | pci_dev_put(dev_priv->bridge_dev); | |
1227 | ||
1228 | return ret; | |
1229 | } | |
1230 | ||
1231 | /** | |
1232 | * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio() | |
1233 | * @dev_priv: device private | |
1234 | */ | |
1235 | static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv) | |
1236 | { | |
1237 | struct drm_device *dev = dev_priv->dev; | |
1238 | ||
dc97997a | 1239 | intel_uncore_fini(dev_priv); |
f28cea45 ID |
1240 | i915_mmio_cleanup(dev); |
1241 | pci_dev_put(dev_priv->bridge_dev); | |
1242 | } | |
1243 | ||
79e53945 | 1244 | /** |
09cfcb45 ID |
1245 | * i915_driver_init_hw - setup state requiring device access |
1246 | * @dev_priv: device private | |
79e53945 | 1247 | * |
09cfcb45 ID |
1248 | * Setup state that requires accessing the device, but doesn't require |
1249 | * exposing the driver via kernel internal or userspace interfaces. | |
79e53945 | 1250 | */ |
09cfcb45 | 1251 | static int i915_driver_init_hw(struct drm_i915_private *dev_priv) |
22eae947 | 1252 | { |
09cfcb45 | 1253 | struct drm_device *dev = dev_priv->dev; |
72e96d64 | 1254 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
9021f284 | 1255 | uint32_t aperture_size; |
09cfcb45 | 1256 | int ret; |
c3d685a7 | 1257 | |
4fec15d1 ID |
1258 | if (i915_inject_load_failure()) |
1259 | return -ENODEV; | |
1260 | ||
13c8f4c8 ID |
1261 | intel_device_info_runtime_init(dev); |
1262 | ||
d85489d3 | 1263 | ret = i915_ggtt_init_hw(dev); |
e76e9aeb | 1264 | if (ret) |
09cfcb45 | 1265 | return ret; |
e188719a | 1266 | |
ac840ae5 VS |
1267 | ret = i915_ggtt_enable_hw(dev); |
1268 | if (ret) { | |
1269 | DRM_ERROR("failed to enable GGTT\n"); | |
1270 | goto out_ggtt; | |
1271 | } | |
1272 | ||
17fa6463 DV |
1273 | /* WARNING: Apparently we must kick fbdev drivers before vgacon, |
1274 | * otherwise the vga fbdev driver falls over. */ | |
1275 | ret = i915_kick_out_firmware_fb(dev_priv); | |
1276 | if (ret) { | |
1277 | DRM_ERROR("failed to remove conflicting framebuffer drivers\n"); | |
d85489d3 | 1278 | goto out_ggtt; |
17fa6463 | 1279 | } |
a4de0526 | 1280 | |
17fa6463 DV |
1281 | ret = i915_kick_out_vgacon(dev_priv); |
1282 | if (ret) { | |
1283 | DRM_ERROR("failed to remove conflicting VGA console\n"); | |
d85489d3 | 1284 | goto out_ggtt; |
a4de0526 | 1285 | } |
e188719a | 1286 | |
466e69b8 DA |
1287 | pci_set_master(dev->pdev); |
1288 | ||
9f82d238 | 1289 | /* overlay on gen2 is broken and can't address above 1G */ |
7d7792e5 ID |
1290 | if (IS_GEN2(dev)) { |
1291 | ret = dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30)); | |
1292 | if (ret) { | |
1293 | DRM_ERROR("failed to set DMA mask\n"); | |
1294 | ||
1295 | goto out_ggtt; | |
1296 | } | |
1297 | } | |
1298 | ||
9f82d238 | 1299 | |
6927faf3 JN |
1300 | /* 965GM sometimes incorrectly writes to hardware status page (HWS) |
1301 | * using 32bit addressing, overwriting memory if HWS is located | |
1302 | * above 4GB. | |
1303 | * | |
1304 | * The documentation also mentions an issue with undefined | |
1305 | * behaviour if any general state is accessed within a page above 4GB, | |
1306 | * which also needs to be handled carefully. | |
1307 | */ | |
7d7792e5 ID |
1308 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) { |
1309 | ret = dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32)); | |
1310 | ||
1311 | if (ret) { | |
1312 | DRM_ERROR("failed to set DMA mask\n"); | |
1313 | ||
1314 | goto out_ggtt; | |
1315 | } | |
1316 | } | |
6927faf3 | 1317 | |
72e96d64 | 1318 | aperture_size = ggtt->mappable_end; |
71e9339c | 1319 | |
72e96d64 JL |
1320 | ggtt->mappable = |
1321 | io_mapping_create_wc(ggtt->mappable_base, | |
dd2757f8 | 1322 | aperture_size); |
72e96d64 | 1323 | if (!ggtt->mappable) { |
6644107d | 1324 | ret = -EIO; |
d85489d3 | 1325 | goto out_ggtt; |
6644107d VP |
1326 | } |
1327 | ||
72e96d64 | 1328 | ggtt->mtrr = arch_phys_wc_add(ggtt->mappable_base, |
911bdf0a | 1329 | aperture_size); |
19966754 | 1330 | |
bd39ec5d ID |
1331 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, |
1332 | PM_QOS_DEFAULT_VALUE); | |
1333 | ||
dc97997a | 1334 | intel_uncore_sanitize(dev_priv); |
9880b7a5 | 1335 | |
6f9f4b7a | 1336 | intel_opregion_setup(dev_priv); |
c4804411 | 1337 | |
40ae4e16 ID |
1338 | i915_gem_load_init_fences(dev_priv); |
1339 | ||
ed4cb414 EA |
1340 | /* On the 945G/GM, the chipset reports the MSI capability on the |
1341 | * integrated graphics even though the support isn't actually there | |
1342 | * according to the published specs. It doesn't appear to function | |
1343 | * correctly in testing on 945G. | |
1344 | * This may be a side effect of MSI having been made available for PEG | |
1345 | * and the registers being closely associated. | |
d1ed629f KP |
1346 | * |
1347 | * According to chipset errata, on the 965GM, MSI interrupts may | |
b60678a7 KP |
1348 | * be lost or delayed, but we use them anyways to avoid |
1349 | * stuck interrupts on some machines. | |
ed4cb414 | 1350 | */ |
b074eae1 ID |
1351 | if (!IS_I945G(dev) && !IS_I945GM(dev)) { |
1352 | if (pci_enable_msi(dev->pdev) < 0) | |
1353 | DRM_DEBUG_DRIVER("can't enable MSI"); | |
1354 | } | |
ed4cb414 | 1355 | |
09cfcb45 ID |
1356 | return 0; |
1357 | ||
d85489d3 JL |
1358 | out_ggtt: |
1359 | i915_ggtt_cleanup_hw(dev); | |
09cfcb45 ID |
1360 | |
1361 | return ret; | |
1362 | } | |
1363 | ||
1364 | /** | |
1365 | * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw() | |
1366 | * @dev_priv: device private | |
1367 | */ | |
1368 | static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv) | |
1369 | { | |
1370 | struct drm_device *dev = dev_priv->dev; | |
72e96d64 | 1371 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
09cfcb45 ID |
1372 | |
1373 | if (dev->pdev->msi_enabled) | |
1374 | pci_disable_msi(dev->pdev); | |
1375 | ||
1376 | pm_qos_remove_request(&dev_priv->pm_qos); | |
72e96d64 JL |
1377 | arch_phys_wc_del(ggtt->mtrr); |
1378 | io_mapping_free(ggtt->mappable); | |
d85489d3 | 1379 | i915_ggtt_cleanup_hw(dev); |
09cfcb45 ID |
1380 | } |
1381 | ||
432f856d ID |
1382 | /** |
1383 | * i915_driver_register - register the driver with the rest of the system | |
1384 | * @dev_priv: device private | |
1385 | * | |
1386 | * Perform any steps necessary to make the driver available via kernel | |
1387 | * internal or userspace interfaces. | |
1388 | */ | |
1389 | static void i915_driver_register(struct drm_i915_private *dev_priv) | |
1390 | { | |
1391 | struct drm_device *dev = dev_priv->dev; | |
1392 | ||
1393 | i915_gem_shrinker_init(dev_priv); | |
8f460e2c | 1394 | |
432f856d ID |
1395 | /* |
1396 | * Notify a valid surface after modesetting, | |
1397 | * when running inside a VM. | |
1398 | */ | |
c033666a | 1399 | if (intel_vgpu_active(dev_priv)) |
432f856d ID |
1400 | I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY); |
1401 | ||
8f460e2c CW |
1402 | /* Reveal our presence to userspace */ |
1403 | if (drm_dev_register(dev, 0) == 0) { | |
1404 | i915_debugfs_register(dev_priv); | |
1405 | i915_setup_sysfs(dev); | |
1406 | intel_modeset_register(dev_priv); | |
1407 | } else | |
1408 | DRM_ERROR("Failed to register driver for userspace access!\n"); | |
432f856d ID |
1409 | |
1410 | if (INTEL_INFO(dev_priv)->num_pipes) { | |
1411 | /* Must be done after probing outputs */ | |
03d92e47 | 1412 | intel_opregion_register(dev_priv); |
432f856d ID |
1413 | acpi_video_register(); |
1414 | } | |
1415 | ||
1416 | if (IS_GEN5(dev_priv)) | |
1417 | intel_gpu_ips_init(dev_priv); | |
1418 | ||
1419 | i915_audio_component_init(dev_priv); | |
d626f345 CW |
1420 | |
1421 | /* | |
1422 | * Some ports require correctly set-up hpd registers for detection to | |
1423 | * work properly (leading to ghost connected connector status), e.g. VGA | |
1424 | * on gm45. Hence we can only set up the initial fbdev config after hpd | |
1425 | * irqs are fully enabled. We do it last so that the async config | |
1426 | * cannot run before the connectors are registered. | |
1427 | */ | |
1428 | intel_fbdev_initial_config_async(dev); | |
432f856d ID |
1429 | } |
1430 | ||
1431 | /** | |
1432 | * i915_driver_unregister - cleanup the registration done in i915_driver_regiser() | |
1433 | * @dev_priv: device private | |
1434 | */ | |
1435 | static void i915_driver_unregister(struct drm_i915_private *dev_priv) | |
1436 | { | |
1437 | i915_audio_component_cleanup(dev_priv); | |
1438 | intel_gpu_ips_teardown(); | |
1439 | acpi_video_unregister(); | |
03d92e47 | 1440 | intel_opregion_unregister(dev_priv); |
843152b4 | 1441 | intel_modeset_unregister(dev_priv); |
432f856d | 1442 | i915_teardown_sysfs(dev_priv->dev); |
1dac891c | 1443 | i915_debugfs_unregister(dev_priv); |
432f856d ID |
1444 | i915_gem_shrinker_cleanup(dev_priv); |
1445 | } | |
1446 | ||
09cfcb45 ID |
1447 | /** |
1448 | * i915_driver_load - setup chip and create an initial config | |
1449 | * @dev: DRM device | |
1450 | * @flags: startup flags | |
1451 | * | |
1452 | * The driver load routine has to do several things: | |
1453 | * - drive output discovery via intel_modeset_init() | |
1454 | * - initialize the memory manager | |
1455 | * - allocate initial config memory | |
1456 | * - setup the DRM framebuffer with the allocated memory | |
1457 | */ | |
8f460e2c CW |
1458 | int i915_driver_load(struct pci_dev *pdev, |
1459 | const struct pci_device_id *ent, | |
1460 | struct drm_driver *driver) | |
09cfcb45 ID |
1461 | { |
1462 | struct drm_i915_private *dev_priv; | |
8f460e2c | 1463 | int ret; |
09cfcb45 | 1464 | |
8f460e2c | 1465 | ret = -ENOMEM; |
09cfcb45 | 1466 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); |
8f460e2c CW |
1467 | if (dev_priv) |
1468 | ret = drm_dev_init(&dev_priv->drm, driver, &pdev->dev); | |
1469 | if (ret) { | |
1470 | dev_printk(KERN_ERR, &pdev->dev, | |
1471 | "[" DRM_NAME ":%s] allocation failed\n", __func__); | |
1472 | kfree(dev_priv); | |
1473 | return ret; | |
1474 | } | |
09cfcb45 | 1475 | |
d15d7538 | 1476 | /* Must be set before calling __i915_printk */ |
8f460e2c CW |
1477 | dev_priv->drm.pdev = pdev; |
1478 | dev_priv->drm.dev_private = dev_priv; | |
1479 | dev_priv->dev = &dev_priv->drm; | |
09cfcb45 | 1480 | |
8f460e2c CW |
1481 | ret = pci_enable_device(pdev); |
1482 | if (ret) | |
1483 | goto out_free_priv; | |
1484 | ||
1485 | pci_set_drvdata(pdev, &dev_priv->drm); | |
09cfcb45 | 1486 | |
8f460e2c | 1487 | ret = i915_driver_init_early(dev_priv, ent); |
09cfcb45 | 1488 | if (ret < 0) |
8f460e2c | 1489 | goto out_pci_disable; |
09cfcb45 ID |
1490 | |
1491 | intel_runtime_pm_get(dev_priv); | |
1492 | ||
1493 | ret = i915_driver_init_mmio(dev_priv); | |
1494 | if (ret < 0) | |
1495 | goto out_runtime_pm_put; | |
1496 | ||
1497 | ret = i915_driver_init_hw(dev_priv); | |
1498 | if (ret < 0) | |
1499 | goto out_cleanup_mmio; | |
1500 | ||
432f856d ID |
1501 | /* |
1502 | * TODO: move the vblank init and parts of modeset init steps into one | |
1503 | * of the i915_driver_init_/i915_driver_register functions according | |
1504 | * to the role/effect of the given init step. | |
1505 | */ | |
8f460e2c CW |
1506 | if (INTEL_INFO(dev_priv)->num_pipes) { |
1507 | ret = drm_vblank_init(dev_priv->dev, | |
1508 | INTEL_INFO(dev_priv)->num_pipes); | |
e3c74757 | 1509 | if (ret) |
09cfcb45 | 1510 | goto out_cleanup_hw; |
e3c74757 | 1511 | } |
52440211 | 1512 | |
8f460e2c | 1513 | ret = i915_load_modeset_init(dev_priv->dev); |
d15d7538 | 1514 | if (ret < 0) |
65ff442f | 1515 | goto out_cleanup_vblank; |
79e53945 | 1516 | |
432f856d | 1517 | i915_driver_register(dev_priv); |
58fddc28 | 1518 | |
3487b66b ID |
1519 | intel_runtime_pm_enable(dev_priv); |
1520 | ||
1f814dac ID |
1521 | intel_runtime_pm_put(dev_priv); |
1522 | ||
79e53945 JB |
1523 | return 0; |
1524 | ||
65ff442f | 1525 | out_cleanup_vblank: |
8f460e2c | 1526 | drm_vblank_cleanup(dev_priv->dev); |
09cfcb45 ID |
1527 | out_cleanup_hw: |
1528 | i915_driver_cleanup_hw(dev_priv); | |
f28cea45 ID |
1529 | out_cleanup_mmio: |
1530 | i915_driver_cleanup_mmio(dev_priv); | |
02036cee | 1531 | out_runtime_pm_put: |
1f814dac | 1532 | intel_runtime_pm_put(dev_priv); |
5d7a6eef | 1533 | i915_driver_cleanup_early(dev_priv); |
8f460e2c CW |
1534 | out_pci_disable: |
1535 | pci_disable_device(pdev); | |
399bb5b6 | 1536 | out_free_priv: |
d15d7538 | 1537 | i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret); |
8f460e2c | 1538 | drm_dev_unref(&dev_priv->drm); |
ba8bbcf6 JB |
1539 | return ret; |
1540 | } | |
1541 | ||
1542 | int i915_driver_unload(struct drm_device *dev) | |
1543 | { | |
1544 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c911fc1c | 1545 | int ret; |
ba8bbcf6 | 1546 | |
2013bfc0 VS |
1547 | intel_fbdev_fini(dev); |
1548 | ||
0ad35fed ZW |
1549 | intel_gvt_cleanup(dev_priv); |
1550 | ||
ce58c32b CW |
1551 | ret = i915_gem_suspend(dev); |
1552 | if (ret) { | |
1553 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
1554 | return ret; | |
1555 | } | |
1556 | ||
250ad48e | 1557 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); |
8a187455 | 1558 | |
432f856d | 1559 | i915_driver_unregister(dev_priv); |
44834a67 | 1560 | |
2ebfaf5f PZ |
1561 | drm_vblank_cleanup(dev); |
1562 | ||
17fa6463 | 1563 | intel_modeset_cleanup(dev); |
6c0d9350 | 1564 | |
17fa6463 DV |
1565 | /* |
1566 | * free the memory space allocated for the child device | |
1567 | * config parsed from VBT | |
1568 | */ | |
1569 | if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) { | |
1570 | kfree(dev_priv->vbt.child_dev); | |
1571 | dev_priv->vbt.child_dev = NULL; | |
1572 | dev_priv->vbt.child_dev_num = 0; | |
79e53945 | 1573 | } |
9aa61142 MR |
1574 | kfree(dev_priv->vbt.sdvo_lvds_vbt_mode); |
1575 | dev_priv->vbt.sdvo_lvds_vbt_mode = NULL; | |
1576 | kfree(dev_priv->vbt.lfp_lvds_vbt_mode); | |
1577 | dev_priv->vbt.lfp_lvds_vbt_mode = NULL; | |
79e53945 | 1578 | |
17fa6463 DV |
1579 | vga_switcheroo_unregister_client(dev->pdev); |
1580 | vga_client_register(dev->pdev, NULL, NULL, NULL); | |
1581 | ||
89250fec ID |
1582 | intel_csr_ucode_fini(dev_priv); |
1583 | ||
a8b4899e | 1584 | /* Free error state after interrupts are fully disabled. */ |
737b1506 | 1585 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
a8b4899e | 1586 | i915_destroy_error_state(dev); |
bc0c7f14 | 1587 | |
17fa6463 DV |
1588 | /* Flush any outstanding unpin_work. */ |
1589 | flush_workqueue(dev_priv->wq); | |
67e77c5a | 1590 | |
f09d675f | 1591 | intel_guc_fini(dev); |
e7ae86ba | 1592 | i915_gem_fini(dev); |
7733b49b | 1593 | intel_fbc_cleanup_cfb(dev_priv); |
79e53945 | 1594 | |
250ad48e ID |
1595 | intel_power_domains_fini(dev_priv); |
1596 | ||
09cfcb45 | 1597 | i915_driver_cleanup_hw(dev_priv); |
f28cea45 | 1598 | i915_driver_cleanup_mmio(dev_priv); |
250ad48e ID |
1599 | |
1600 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); | |
1601 | ||
5d7a6eef | 1602 | i915_driver_cleanup_early(dev_priv); |
ba8bbcf6 | 1603 | |
22eae947 DA |
1604 | return 0; |
1605 | } | |
1606 | ||
f787a5f5 | 1607 | int i915_driver_open(struct drm_device *dev, struct drm_file *file) |
673a394b | 1608 | { |
b29c19b6 | 1609 | int ret; |
673a394b | 1610 | |
b29c19b6 CW |
1611 | ret = i915_gem_open(dev, file); |
1612 | if (ret) | |
1613 | return ret; | |
254f965c | 1614 | |
673a394b EA |
1615 | return 0; |
1616 | } | |
1617 | ||
79e53945 JB |
1618 | /** |
1619 | * i915_driver_lastclose - clean up after all DRM clients have exited | |
1620 | * @dev: DRM device | |
1621 | * | |
1622 | * Take care of cleaning up after all DRM clients have exited. In the | |
1623 | * mode setting case, we want to restore the kernel's initial mode (just | |
1624 | * in case the last client left us in a bad state). | |
1625 | * | |
9021f284 | 1626 | * Additionally, in the non-mode setting case, we'll tear down the GTT |
79e53945 JB |
1627 | * and DMA structures, since the kernel won't be using them, and clea |
1628 | * up any GEM state. | |
1629 | */ | |
1a5036bf | 1630 | void i915_driver_lastclose(struct drm_device *dev) |
1da177e4 | 1631 | { |
377e91b2 DV |
1632 | intel_fbdev_restore_mode(dev); |
1633 | vga_switcheroo_process_delayed_switch(); | |
1da177e4 LT |
1634 | } |
1635 | ||
2885f6ac | 1636 | void i915_driver_preclose(struct drm_device *dev, struct drm_file *file) |
1da177e4 | 1637 | { |
0d1430a3 | 1638 | mutex_lock(&dev->struct_mutex); |
2885f6ac JH |
1639 | i915_gem_context_close(dev, file); |
1640 | i915_gem_release(dev, file); | |
0d1430a3 | 1641 | mutex_unlock(&dev->struct_mutex); |
1da177e4 LT |
1642 | } |
1643 | ||
f787a5f5 | 1644 | void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) |
673a394b | 1645 | { |
f787a5f5 | 1646 | struct drm_i915_file_private *file_priv = file->driver_priv; |
673a394b | 1647 | |
f787a5f5 | 1648 | kfree(file_priv); |
673a394b EA |
1649 | } |
1650 | ||
4feb7659 DV |
1651 | static int |
1652 | i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data, | |
1653 | struct drm_file *file) | |
1654 | { | |
1655 | return -ENODEV; | |
1656 | } | |
1657 | ||
baa70943 | 1658 | const struct drm_ioctl_desc i915_ioctls[] = { |
77f31815 DV |
1659 | DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1660 | DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH), | |
1661 | DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH), | |
1662 | DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH), | |
1663 | DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH), | |
1664 | DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH), | |
10ba5012 | 1665 | DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW), |
c668cde5 | 1666 | DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
b2c606fe DV |
1667 | DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), |
1668 | DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), | |
1669 | DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
77f31815 | 1670 | DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH), |
b2c606fe | 1671 | DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
d1c1edbc | 1672 | DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
77f31815 DV |
1673 | DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH), |
1674 | DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH), | |
1675 | DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
f8c47144 DV |
1676 | DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1677 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH), | |
1678 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW), | |
1679 | DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), | |
1680 | DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), | |
1681 | DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
1682 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW), | |
1683 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW), | |
1684 | DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
1685 | DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1686 | DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1687 | DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW), | |
1688 | DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW), | |
1689 | DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW), | |
1690 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW), | |
1691 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW), | |
1692 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW), | |
1693 | DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW), | |
1694 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_RENDER_ALLOW), | |
1695 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_RENDER_ALLOW), | |
1696 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW), | |
1697 | DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0), | |
1698 | DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW), | |
1ee8da6d CW |
1699 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW), |
1700 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW), | |
f8c47144 DV |
1701 | DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW), |
1702 | DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW), | |
1703 | DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
1704 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW), | |
1705 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW), | |
1706 | DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW), | |
d538704b | 1707 | DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW), |
f8c47144 DV |
1708 | DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW), |
1709 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW), | |
1710 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW), | |
c94f7029 DA |
1711 | }; |
1712 | ||
f95aeb17 | 1713 | int i915_max_ioctl = ARRAY_SIZE(i915_ioctls); |