Commit | Line | Data |
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1da177e4 LT |
1 | /* i915_dma.c -- DMA support for the I915 -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 LT |
28 | |
29 | #include "drmP.h" | |
30 | #include "drm.h" | |
31 | #include "i915_drm.h" | |
32 | #include "i915_drv.h" | |
33 | ||
1da177e4 LT |
34 | /* Really want an OS-independent resettable timer. Would like to have |
35 | * this loop run for (eg) 3 sec, but have the timer reset every time | |
36 | * the head pointer changes, so that EBUSY only happens if the ring | |
37 | * actually stalls for (eg) 3 seconds. | |
38 | */ | |
84b1fd10 | 39 | int i915_wait_ring(struct drm_device * dev, int n, const char *caller) |
1da177e4 LT |
40 | { |
41 | drm_i915_private_t *dev_priv = dev->dev_private; | |
42 | drm_i915_ring_buffer_t *ring = &(dev_priv->ring); | |
d3a6d446 KP |
43 | u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD; |
44 | u32 last_acthd = I915_READ(acthd_reg); | |
45 | u32 acthd; | |
585fb111 | 46 | u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
1da177e4 LT |
47 | int i; |
48 | ||
d3a6d446 | 49 | for (i = 0; i < 100000; i++) { |
585fb111 | 50 | ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
d3a6d446 | 51 | acthd = I915_READ(acthd_reg); |
1da177e4 LT |
52 | ring->space = ring->head - (ring->tail + 8); |
53 | if (ring->space < 0) | |
54 | ring->space += ring->Size; | |
55 | if (ring->space >= n) | |
56 | return 0; | |
57 | ||
58 | dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
59 | ||
60 | if (ring->head != last_head) | |
61 | i = 0; | |
d3a6d446 KP |
62 | if (acthd != last_acthd) |
63 | i = 0; | |
1da177e4 LT |
64 | |
65 | last_head = ring->head; | |
d3a6d446 KP |
66 | last_acthd = acthd; |
67 | msleep_interruptible(10); | |
68 | ||
1da177e4 LT |
69 | } |
70 | ||
20caafa6 | 71 | return -EBUSY; |
1da177e4 LT |
72 | } |
73 | ||
398c9cb2 KP |
74 | /** |
75 | * Sets up the hardware status page for devices that need a physical address | |
76 | * in the register. | |
77 | */ | |
78 | int i915_init_phys_hws(struct drm_device *dev) | |
79 | { | |
80 | drm_i915_private_t *dev_priv = dev->dev_private; | |
81 | /* Program Hardware Status Page */ | |
82 | dev_priv->status_page_dmah = | |
83 | drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff); | |
84 | ||
85 | if (!dev_priv->status_page_dmah) { | |
86 | DRM_ERROR("Can not allocate hardware status page\n"); | |
87 | return -ENOMEM; | |
88 | } | |
89 | dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr; | |
90 | dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr; | |
91 | ||
92 | memset(dev_priv->hw_status_page, 0, PAGE_SIZE); | |
93 | ||
94 | I915_WRITE(HWS_PGA, dev_priv->dma_status_page); | |
95 | DRM_DEBUG("Enabled hardware status page\n"); | |
96 | return 0; | |
97 | } | |
98 | ||
99 | /** | |
100 | * Frees the hardware status page, whether it's a physical address or a virtual | |
101 | * address set up by the X Server. | |
102 | */ | |
103 | void i915_free_hws(struct drm_device *dev) | |
104 | { | |
105 | drm_i915_private_t *dev_priv = dev->dev_private; | |
106 | if (dev_priv->status_page_dmah) { | |
107 | drm_pci_free(dev, dev_priv->status_page_dmah); | |
108 | dev_priv->status_page_dmah = NULL; | |
109 | } | |
110 | ||
111 | if (dev_priv->status_gfx_addr) { | |
112 | dev_priv->status_gfx_addr = 0; | |
113 | drm_core_ioremapfree(&dev_priv->hws_map, dev); | |
114 | } | |
115 | ||
116 | /* Need to rewrite hardware status page */ | |
117 | I915_WRITE(HWS_PGA, 0x1ffff000); | |
118 | } | |
119 | ||
84b1fd10 | 120 | void i915_kernel_lost_context(struct drm_device * dev) |
1da177e4 LT |
121 | { |
122 | drm_i915_private_t *dev_priv = dev->dev_private; | |
123 | drm_i915_ring_buffer_t *ring = &(dev_priv->ring); | |
124 | ||
585fb111 JB |
125 | ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
126 | ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR; | |
1da177e4 LT |
127 | ring->space = ring->head - (ring->tail + 8); |
128 | if (ring->space < 0) | |
129 | ring->space += ring->Size; | |
130 | ||
131 | if (ring->head == ring->tail) | |
132 | dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY; | |
133 | } | |
134 | ||
84b1fd10 | 135 | static int i915_dma_cleanup(struct drm_device * dev) |
1da177e4 | 136 | { |
ba8bbcf6 | 137 | drm_i915_private_t *dev_priv = dev->dev_private; |
1da177e4 LT |
138 | /* Make sure interrupts are disabled here because the uninstall ioctl |
139 | * may not have been called from userspace and after dev_private | |
140 | * is freed, it's too late. | |
141 | */ | |
ed4cb414 | 142 | if (dev->irq_enabled) |
b5e89ed5 | 143 | drm_irq_uninstall(dev); |
1da177e4 | 144 | |
ba8bbcf6 JB |
145 | if (dev_priv->ring.virtual_start) { |
146 | drm_core_ioremapfree(&dev_priv->ring.map, dev); | |
147 | dev_priv->ring.virtual_start = 0; | |
148 | dev_priv->ring.map.handle = 0; | |
149 | dev_priv->ring.map.size = 0; | |
150 | } | |
dc7a9319 | 151 | |
398c9cb2 KP |
152 | /* Clear the HWS virtual address at teardown */ |
153 | if (I915_NEED_GFX_HWS(dev)) | |
154 | i915_free_hws(dev); | |
1da177e4 LT |
155 | |
156 | return 0; | |
157 | } | |
158 | ||
ba8bbcf6 | 159 | static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) |
1da177e4 | 160 | { |
ba8bbcf6 | 161 | drm_i915_private_t *dev_priv = dev->dev_private; |
1da177e4 | 162 | |
da509d7a | 163 | dev_priv->sarea = drm_getsarea(dev); |
1da177e4 LT |
164 | if (!dev_priv->sarea) { |
165 | DRM_ERROR("can not find sarea!\n"); | |
1da177e4 | 166 | i915_dma_cleanup(dev); |
20caafa6 | 167 | return -EINVAL; |
1da177e4 LT |
168 | } |
169 | ||
1da177e4 LT |
170 | dev_priv->sarea_priv = (drm_i915_sarea_t *) |
171 | ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset); | |
172 | ||
673a394b EA |
173 | if (init->ring_size != 0) { |
174 | if (dev_priv->ring.ring_obj != NULL) { | |
175 | i915_dma_cleanup(dev); | |
176 | DRM_ERROR("Client tried to initialize ringbuffer in " | |
177 | "GEM mode\n"); | |
178 | return -EINVAL; | |
179 | } | |
1da177e4 | 180 | |
673a394b EA |
181 | dev_priv->ring.Size = init->ring_size; |
182 | dev_priv->ring.tail_mask = dev_priv->ring.Size - 1; | |
1da177e4 | 183 | |
673a394b EA |
184 | dev_priv->ring.map.offset = init->ring_start; |
185 | dev_priv->ring.map.size = init->ring_size; | |
186 | dev_priv->ring.map.type = 0; | |
187 | dev_priv->ring.map.flags = 0; | |
188 | dev_priv->ring.map.mtrr = 0; | |
1da177e4 | 189 | |
673a394b EA |
190 | drm_core_ioremap(&dev_priv->ring.map, dev); |
191 | ||
192 | if (dev_priv->ring.map.handle == NULL) { | |
193 | i915_dma_cleanup(dev); | |
194 | DRM_ERROR("can not ioremap virtual address for" | |
195 | " ring buffer\n"); | |
196 | return -ENOMEM; | |
197 | } | |
1da177e4 LT |
198 | } |
199 | ||
200 | dev_priv->ring.virtual_start = dev_priv->ring.map.handle; | |
201 | ||
a6b54f3f | 202 | dev_priv->cpp = init->cpp; |
1da177e4 LT |
203 | dev_priv->back_offset = init->back_offset; |
204 | dev_priv->front_offset = init->front_offset; | |
205 | dev_priv->current_page = 0; | |
206 | dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; | |
207 | ||
1da177e4 LT |
208 | /* Allow hardware batchbuffers unless told otherwise. |
209 | */ | |
210 | dev_priv->allow_batchbuffer = 1; | |
211 | ||
1da177e4 LT |
212 | return 0; |
213 | } | |
214 | ||
84b1fd10 | 215 | static int i915_dma_resume(struct drm_device * dev) |
1da177e4 LT |
216 | { |
217 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
218 | ||
bf9d8929 | 219 | DRM_DEBUG("%s\n", __func__); |
1da177e4 LT |
220 | |
221 | if (!dev_priv->sarea) { | |
222 | DRM_ERROR("can not find sarea!\n"); | |
20caafa6 | 223 | return -EINVAL; |
1da177e4 LT |
224 | } |
225 | ||
1da177e4 LT |
226 | if (dev_priv->ring.map.handle == NULL) { |
227 | DRM_ERROR("can not ioremap virtual address for" | |
228 | " ring buffer\n"); | |
20caafa6 | 229 | return -ENOMEM; |
1da177e4 LT |
230 | } |
231 | ||
232 | /* Program Hardware Status Page */ | |
233 | if (!dev_priv->hw_status_page) { | |
234 | DRM_ERROR("Can not find hardware status page\n"); | |
20caafa6 | 235 | return -EINVAL; |
1da177e4 LT |
236 | } |
237 | DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page); | |
238 | ||
dc7a9319 | 239 | if (dev_priv->status_gfx_addr != 0) |
585fb111 | 240 | I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); |
dc7a9319 | 241 | else |
585fb111 | 242 | I915_WRITE(HWS_PGA, dev_priv->dma_status_page); |
1da177e4 LT |
243 | DRM_DEBUG("Enabled hardware status page\n"); |
244 | ||
245 | return 0; | |
246 | } | |
247 | ||
c153f45f EA |
248 | static int i915_dma_init(struct drm_device *dev, void *data, |
249 | struct drm_file *file_priv) | |
1da177e4 | 250 | { |
c153f45f | 251 | drm_i915_init_t *init = data; |
1da177e4 LT |
252 | int retcode = 0; |
253 | ||
c153f45f | 254 | switch (init->func) { |
1da177e4 | 255 | case I915_INIT_DMA: |
ba8bbcf6 | 256 | retcode = i915_initialize(dev, init); |
1da177e4 LT |
257 | break; |
258 | case I915_CLEANUP_DMA: | |
259 | retcode = i915_dma_cleanup(dev); | |
260 | break; | |
261 | case I915_RESUME_DMA: | |
0d6aa60b | 262 | retcode = i915_dma_resume(dev); |
1da177e4 LT |
263 | break; |
264 | default: | |
20caafa6 | 265 | retcode = -EINVAL; |
1da177e4 LT |
266 | break; |
267 | } | |
268 | ||
269 | return retcode; | |
270 | } | |
271 | ||
272 | /* Implement basically the same security restrictions as hardware does | |
273 | * for MI_BATCH_NON_SECURE. These can be made stricter at any time. | |
274 | * | |
275 | * Most of the calculations below involve calculating the size of a | |
276 | * particular instruction. It's important to get the size right as | |
277 | * that tells us where the next instruction to check is. Any illegal | |
278 | * instruction detected will be given a size of zero, which is a | |
279 | * signal to abort the rest of the buffer. | |
280 | */ | |
281 | static int do_validate_cmd(int cmd) | |
282 | { | |
283 | switch (((cmd >> 29) & 0x7)) { | |
284 | case 0x0: | |
285 | switch ((cmd >> 23) & 0x3f) { | |
286 | case 0x0: | |
287 | return 1; /* MI_NOOP */ | |
288 | case 0x4: | |
289 | return 1; /* MI_FLUSH */ | |
290 | default: | |
291 | return 0; /* disallow everything else */ | |
292 | } | |
293 | break; | |
294 | case 0x1: | |
295 | return 0; /* reserved */ | |
296 | case 0x2: | |
297 | return (cmd & 0xff) + 2; /* 2d commands */ | |
298 | case 0x3: | |
299 | if (((cmd >> 24) & 0x1f) <= 0x18) | |
300 | return 1; | |
301 | ||
302 | switch ((cmd >> 24) & 0x1f) { | |
303 | case 0x1c: | |
304 | return 1; | |
305 | case 0x1d: | |
b5e89ed5 | 306 | switch ((cmd >> 16) & 0xff) { |
1da177e4 LT |
307 | case 0x3: |
308 | return (cmd & 0x1f) + 2; | |
309 | case 0x4: | |
310 | return (cmd & 0xf) + 2; | |
311 | default: | |
312 | return (cmd & 0xffff) + 2; | |
313 | } | |
314 | case 0x1e: | |
315 | if (cmd & (1 << 23)) | |
316 | return (cmd & 0xffff) + 1; | |
317 | else | |
318 | return 1; | |
319 | case 0x1f: | |
320 | if ((cmd & (1 << 23)) == 0) /* inline vertices */ | |
321 | return (cmd & 0x1ffff) + 2; | |
322 | else if (cmd & (1 << 17)) /* indirect random */ | |
323 | if ((cmd & 0xffff) == 0) | |
324 | return 0; /* unknown length, too hard */ | |
325 | else | |
326 | return (((cmd & 0xffff) + 1) / 2) + 1; | |
327 | else | |
328 | return 2; /* indirect sequential */ | |
329 | default: | |
330 | return 0; | |
331 | } | |
332 | default: | |
333 | return 0; | |
334 | } | |
335 | ||
336 | return 0; | |
337 | } | |
338 | ||
339 | static int validate_cmd(int cmd) | |
340 | { | |
341 | int ret = do_validate_cmd(cmd); | |
342 | ||
bc5f4523 | 343 | /* printk("validate_cmd( %x ): %d\n", cmd, ret); */ |
1da177e4 LT |
344 | |
345 | return ret; | |
346 | } | |
347 | ||
84b1fd10 | 348 | static int i915_emit_cmds(struct drm_device * dev, int __user * buffer, int dwords) |
1da177e4 LT |
349 | { |
350 | drm_i915_private_t *dev_priv = dev->dev_private; | |
351 | int i; | |
352 | RING_LOCALS; | |
353 | ||
de227f5f | 354 | if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8) |
20caafa6 | 355 | return -EINVAL; |
de227f5f | 356 | |
c29b669c | 357 | BEGIN_LP_RING((dwords+1)&~1); |
de227f5f | 358 | |
1da177e4 LT |
359 | for (i = 0; i < dwords;) { |
360 | int cmd, sz; | |
361 | ||
362 | if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd))) | |
20caafa6 | 363 | return -EINVAL; |
1da177e4 | 364 | |
1da177e4 | 365 | if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords) |
20caafa6 | 366 | return -EINVAL; |
1da177e4 | 367 | |
1da177e4 LT |
368 | OUT_RING(cmd); |
369 | ||
370 | while (++i, --sz) { | |
371 | if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], | |
372 | sizeof(cmd))) { | |
20caafa6 | 373 | return -EINVAL; |
1da177e4 LT |
374 | } |
375 | OUT_RING(cmd); | |
376 | } | |
1da177e4 LT |
377 | } |
378 | ||
de227f5f DA |
379 | if (dwords & 1) |
380 | OUT_RING(0); | |
381 | ||
382 | ADVANCE_LP_RING(); | |
383 | ||
1da177e4 LT |
384 | return 0; |
385 | } | |
386 | ||
673a394b EA |
387 | int |
388 | i915_emit_box(struct drm_device *dev, | |
389 | struct drm_clip_rect __user *boxes, | |
390 | int i, int DR1, int DR4) | |
1da177e4 LT |
391 | { |
392 | drm_i915_private_t *dev_priv = dev->dev_private; | |
c60ce623 | 393 | struct drm_clip_rect box; |
1da177e4 LT |
394 | RING_LOCALS; |
395 | ||
396 | if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) { | |
20caafa6 | 397 | return -EFAULT; |
1da177e4 LT |
398 | } |
399 | ||
400 | if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) { | |
401 | DRM_ERROR("Bad box %d,%d..%d,%d\n", | |
402 | box.x1, box.y1, box.x2, box.y2); | |
20caafa6 | 403 | return -EINVAL; |
1da177e4 LT |
404 | } |
405 | ||
c29b669c AH |
406 | if (IS_I965G(dev)) { |
407 | BEGIN_LP_RING(4); | |
408 | OUT_RING(GFX_OP_DRAWRECT_INFO_I965); | |
409 | OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); | |
78eca43d | 410 | OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); |
c29b669c AH |
411 | OUT_RING(DR4); |
412 | ADVANCE_LP_RING(); | |
413 | } else { | |
414 | BEGIN_LP_RING(6); | |
415 | OUT_RING(GFX_OP_DRAWRECT_INFO); | |
416 | OUT_RING(DR1); | |
417 | OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); | |
418 | OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); | |
419 | OUT_RING(DR4); | |
420 | OUT_RING(0); | |
421 | ADVANCE_LP_RING(); | |
422 | } | |
1da177e4 LT |
423 | |
424 | return 0; | |
425 | } | |
426 | ||
c29b669c AH |
427 | /* XXX: Emitting the counter should really be moved to part of the IRQ |
428 | * emit. For now, do it in both places: | |
429 | */ | |
430 | ||
84b1fd10 | 431 | static void i915_emit_breadcrumb(struct drm_device *dev) |
de227f5f DA |
432 | { |
433 | drm_i915_private_t *dev_priv = dev->dev_private; | |
434 | RING_LOCALS; | |
435 | ||
af6061af | 436 | dev_priv->sarea_priv->last_enqueue = ++dev_priv->counter; |
c29b669c | 437 | |
af6061af DA |
438 | if (dev_priv->counter > 0x7FFFFFFFUL) |
439 | dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1; | |
de227f5f DA |
440 | |
441 | BEGIN_LP_RING(4); | |
585fb111 JB |
442 | OUT_RING(MI_STORE_DWORD_INDEX); |
443 | OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT); | |
de227f5f DA |
444 | OUT_RING(dev_priv->counter); |
445 | OUT_RING(0); | |
446 | ADVANCE_LP_RING(); | |
447 | } | |
448 | ||
84b1fd10 | 449 | static int i915_dispatch_cmdbuffer(struct drm_device * dev, |
1da177e4 LT |
450 | drm_i915_cmdbuffer_t * cmd) |
451 | { | |
452 | int nbox = cmd->num_cliprects; | |
453 | int i = 0, count, ret; | |
454 | ||
455 | if (cmd->sz & 0x3) { | |
456 | DRM_ERROR("alignment"); | |
20caafa6 | 457 | return -EINVAL; |
1da177e4 LT |
458 | } |
459 | ||
460 | i915_kernel_lost_context(dev); | |
461 | ||
462 | count = nbox ? nbox : 1; | |
463 | ||
464 | for (i = 0; i < count; i++) { | |
465 | if (i < nbox) { | |
466 | ret = i915_emit_box(dev, cmd->cliprects, i, | |
467 | cmd->DR1, cmd->DR4); | |
468 | if (ret) | |
469 | return ret; | |
470 | } | |
471 | ||
472 | ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4); | |
473 | if (ret) | |
474 | return ret; | |
475 | } | |
476 | ||
de227f5f | 477 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
478 | return 0; |
479 | } | |
480 | ||
84b1fd10 | 481 | static int i915_dispatch_batchbuffer(struct drm_device * dev, |
1da177e4 LT |
482 | drm_i915_batchbuffer_t * batch) |
483 | { | |
484 | drm_i915_private_t *dev_priv = dev->dev_private; | |
c60ce623 | 485 | struct drm_clip_rect __user *boxes = batch->cliprects; |
1da177e4 LT |
486 | int nbox = batch->num_cliprects; |
487 | int i = 0, count; | |
488 | RING_LOCALS; | |
489 | ||
490 | if ((batch->start | batch->used) & 0x7) { | |
491 | DRM_ERROR("alignment"); | |
20caafa6 | 492 | return -EINVAL; |
1da177e4 LT |
493 | } |
494 | ||
495 | i915_kernel_lost_context(dev); | |
496 | ||
497 | count = nbox ? nbox : 1; | |
498 | ||
499 | for (i = 0; i < count; i++) { | |
500 | if (i < nbox) { | |
501 | int ret = i915_emit_box(dev, boxes, i, | |
502 | batch->DR1, batch->DR4); | |
503 | if (ret) | |
504 | return ret; | |
505 | } | |
506 | ||
0790d5e1 | 507 | if (!IS_I830(dev) && !IS_845G(dev)) { |
1da177e4 | 508 | BEGIN_LP_RING(2); |
21f16289 DA |
509 | if (IS_I965G(dev)) { |
510 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965); | |
511 | OUT_RING(batch->start); | |
512 | } else { | |
513 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6)); | |
514 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
515 | } | |
1da177e4 LT |
516 | ADVANCE_LP_RING(); |
517 | } else { | |
518 | BEGIN_LP_RING(4); | |
519 | OUT_RING(MI_BATCH_BUFFER); | |
520 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
521 | OUT_RING(batch->start + batch->used - 4); | |
522 | OUT_RING(0); | |
523 | ADVANCE_LP_RING(); | |
524 | } | |
525 | } | |
526 | ||
de227f5f | 527 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
528 | |
529 | return 0; | |
530 | } | |
531 | ||
af6061af | 532 | static int i915_dispatch_flip(struct drm_device * dev) |
1da177e4 LT |
533 | { |
534 | drm_i915_private_t *dev_priv = dev->dev_private; | |
535 | RING_LOCALS; | |
536 | ||
af6061af | 537 | DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n", |
80a914dc | 538 | __func__, |
af6061af DA |
539 | dev_priv->current_page, |
540 | dev_priv->sarea_priv->pf_current_page); | |
1da177e4 | 541 | |
af6061af DA |
542 | i915_kernel_lost_context(dev); |
543 | ||
544 | BEGIN_LP_RING(2); | |
585fb111 | 545 | OUT_RING(MI_FLUSH | MI_READ_FLUSH); |
af6061af DA |
546 | OUT_RING(0); |
547 | ADVANCE_LP_RING(); | |
1da177e4 | 548 | |
af6061af DA |
549 | BEGIN_LP_RING(6); |
550 | OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP); | |
551 | OUT_RING(0); | |
552 | if (dev_priv->current_page == 0) { | |
553 | OUT_RING(dev_priv->back_offset); | |
554 | dev_priv->current_page = 1; | |
1da177e4 | 555 | } else { |
af6061af DA |
556 | OUT_RING(dev_priv->front_offset); |
557 | dev_priv->current_page = 0; | |
1da177e4 | 558 | } |
af6061af DA |
559 | OUT_RING(0); |
560 | ADVANCE_LP_RING(); | |
1da177e4 | 561 | |
af6061af DA |
562 | BEGIN_LP_RING(2); |
563 | OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP); | |
564 | OUT_RING(0); | |
565 | ADVANCE_LP_RING(); | |
1da177e4 | 566 | |
af6061af | 567 | dev_priv->sarea_priv->last_enqueue = dev_priv->counter++; |
1da177e4 LT |
568 | |
569 | BEGIN_LP_RING(4); | |
585fb111 JB |
570 | OUT_RING(MI_STORE_DWORD_INDEX); |
571 | OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT); | |
af6061af DA |
572 | OUT_RING(dev_priv->counter); |
573 | OUT_RING(0); | |
1da177e4 LT |
574 | ADVANCE_LP_RING(); |
575 | ||
af6061af DA |
576 | dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; |
577 | return 0; | |
1da177e4 LT |
578 | } |
579 | ||
84b1fd10 | 580 | static int i915_quiescent(struct drm_device * dev) |
1da177e4 LT |
581 | { |
582 | drm_i915_private_t *dev_priv = dev->dev_private; | |
583 | ||
584 | i915_kernel_lost_context(dev); | |
bf9d8929 | 585 | return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__); |
1da177e4 LT |
586 | } |
587 | ||
c153f45f EA |
588 | static int i915_flush_ioctl(struct drm_device *dev, void *data, |
589 | struct drm_file *file_priv) | |
1da177e4 | 590 | { |
546b0974 EA |
591 | int ret; |
592 | ||
593 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); | |
1da177e4 | 594 | |
546b0974 EA |
595 | mutex_lock(&dev->struct_mutex); |
596 | ret = i915_quiescent(dev); | |
597 | mutex_unlock(&dev->struct_mutex); | |
598 | ||
599 | return ret; | |
1da177e4 LT |
600 | } |
601 | ||
c153f45f EA |
602 | static int i915_batchbuffer(struct drm_device *dev, void *data, |
603 | struct drm_file *file_priv) | |
1da177e4 | 604 | { |
1da177e4 | 605 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
af6061af | 606 | u32 *hw_status = dev_priv->hw_status_page; |
1da177e4 LT |
607 | drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) |
608 | dev_priv->sarea_priv; | |
c153f45f | 609 | drm_i915_batchbuffer_t *batch = data; |
1da177e4 LT |
610 | int ret; |
611 | ||
612 | if (!dev_priv->allow_batchbuffer) { | |
613 | DRM_ERROR("Batchbuffer ioctl disabled\n"); | |
20caafa6 | 614 | return -EINVAL; |
1da177e4 LT |
615 | } |
616 | ||
1da177e4 | 617 | DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n", |
c153f45f | 618 | batch->start, batch->used, batch->num_cliprects); |
1da177e4 | 619 | |
546b0974 | 620 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 621 | |
c153f45f EA |
622 | if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects, |
623 | batch->num_cliprects * | |
c60ce623 | 624 | sizeof(struct drm_clip_rect))) |
20caafa6 | 625 | return -EFAULT; |
1da177e4 | 626 | |
546b0974 | 627 | mutex_lock(&dev->struct_mutex); |
c153f45f | 628 | ret = i915_dispatch_batchbuffer(dev, batch); |
546b0974 | 629 | mutex_unlock(&dev->struct_mutex); |
1da177e4 | 630 | |
af6061af | 631 | sarea_priv->last_dispatch = (int)hw_status[5]; |
1da177e4 LT |
632 | return ret; |
633 | } | |
634 | ||
c153f45f EA |
635 | static int i915_cmdbuffer(struct drm_device *dev, void *data, |
636 | struct drm_file *file_priv) | |
1da177e4 | 637 | { |
1da177e4 | 638 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
af6061af | 639 | u32 *hw_status = dev_priv->hw_status_page; |
1da177e4 LT |
640 | drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) |
641 | dev_priv->sarea_priv; | |
c153f45f | 642 | drm_i915_cmdbuffer_t *cmdbuf = data; |
1da177e4 LT |
643 | int ret; |
644 | ||
1da177e4 | 645 | DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n", |
c153f45f | 646 | cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects); |
1da177e4 | 647 | |
546b0974 | 648 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 649 | |
c153f45f EA |
650 | if (cmdbuf->num_cliprects && |
651 | DRM_VERIFYAREA_READ(cmdbuf->cliprects, | |
652 | cmdbuf->num_cliprects * | |
c60ce623 | 653 | sizeof(struct drm_clip_rect))) { |
1da177e4 | 654 | DRM_ERROR("Fault accessing cliprects\n"); |
20caafa6 | 655 | return -EFAULT; |
1da177e4 LT |
656 | } |
657 | ||
546b0974 | 658 | mutex_lock(&dev->struct_mutex); |
c153f45f | 659 | ret = i915_dispatch_cmdbuffer(dev, cmdbuf); |
546b0974 | 660 | mutex_unlock(&dev->struct_mutex); |
1da177e4 LT |
661 | if (ret) { |
662 | DRM_ERROR("i915_dispatch_cmdbuffer failed\n"); | |
663 | return ret; | |
664 | } | |
665 | ||
af6061af | 666 | sarea_priv->last_dispatch = (int)hw_status[5]; |
1da177e4 LT |
667 | return 0; |
668 | } | |
669 | ||
c153f45f EA |
670 | static int i915_flip_bufs(struct drm_device *dev, void *data, |
671 | struct drm_file *file_priv) | |
1da177e4 | 672 | { |
546b0974 EA |
673 | int ret; |
674 | ||
80a914dc | 675 | DRM_DEBUG("%s\n", __func__); |
1da177e4 | 676 | |
546b0974 | 677 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 678 | |
546b0974 EA |
679 | mutex_lock(&dev->struct_mutex); |
680 | ret = i915_dispatch_flip(dev); | |
681 | mutex_unlock(&dev->struct_mutex); | |
682 | ||
683 | return ret; | |
1da177e4 LT |
684 | } |
685 | ||
c153f45f EA |
686 | static int i915_getparam(struct drm_device *dev, void *data, |
687 | struct drm_file *file_priv) | |
1da177e4 | 688 | { |
1da177e4 | 689 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 690 | drm_i915_getparam_t *param = data; |
1da177e4 LT |
691 | int value; |
692 | ||
693 | if (!dev_priv) { | |
3e684eae | 694 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 695 | return -EINVAL; |
1da177e4 LT |
696 | } |
697 | ||
c153f45f | 698 | switch (param->param) { |
1da177e4 | 699 | case I915_PARAM_IRQ_ACTIVE: |
0a3e67a4 | 700 | value = dev->pdev->irq ? 1 : 0; |
1da177e4 LT |
701 | break; |
702 | case I915_PARAM_ALLOW_BATCHBUFFER: | |
703 | value = dev_priv->allow_batchbuffer ? 1 : 0; | |
704 | break; | |
0d6aa60b DA |
705 | case I915_PARAM_LAST_DISPATCH: |
706 | value = READ_BREADCRUMB(dev_priv); | |
707 | break; | |
ed4c9c4a KH |
708 | case I915_PARAM_CHIPSET_ID: |
709 | value = dev->pci_device; | |
710 | break; | |
673a394b EA |
711 | case I915_PARAM_HAS_GEM: |
712 | value = 1; | |
713 | break; | |
1da177e4 | 714 | default: |
c153f45f | 715 | DRM_ERROR("Unknown parameter %d\n", param->param); |
20caafa6 | 716 | return -EINVAL; |
1da177e4 LT |
717 | } |
718 | ||
c153f45f | 719 | if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { |
1da177e4 | 720 | DRM_ERROR("DRM_COPY_TO_USER failed\n"); |
20caafa6 | 721 | return -EFAULT; |
1da177e4 LT |
722 | } |
723 | ||
724 | return 0; | |
725 | } | |
726 | ||
c153f45f EA |
727 | static int i915_setparam(struct drm_device *dev, void *data, |
728 | struct drm_file *file_priv) | |
1da177e4 | 729 | { |
1da177e4 | 730 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 731 | drm_i915_setparam_t *param = data; |
1da177e4 LT |
732 | |
733 | if (!dev_priv) { | |
3e684eae | 734 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 735 | return -EINVAL; |
1da177e4 LT |
736 | } |
737 | ||
c153f45f | 738 | switch (param->param) { |
1da177e4 | 739 | case I915_SETPARAM_USE_MI_BATCHBUFFER_START: |
1da177e4 LT |
740 | break; |
741 | case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY: | |
c153f45f | 742 | dev_priv->tex_lru_log_granularity = param->value; |
1da177e4 LT |
743 | break; |
744 | case I915_SETPARAM_ALLOW_BATCHBUFFER: | |
c153f45f | 745 | dev_priv->allow_batchbuffer = param->value; |
1da177e4 LT |
746 | break; |
747 | default: | |
c153f45f | 748 | DRM_ERROR("unknown parameter %d\n", param->param); |
20caafa6 | 749 | return -EINVAL; |
1da177e4 LT |
750 | } |
751 | ||
752 | return 0; | |
753 | } | |
754 | ||
c153f45f EA |
755 | static int i915_set_status_page(struct drm_device *dev, void *data, |
756 | struct drm_file *file_priv) | |
dc7a9319 | 757 | { |
dc7a9319 | 758 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 759 | drm_i915_hws_addr_t *hws = data; |
b39d50e5 ZW |
760 | |
761 | if (!I915_NEED_GFX_HWS(dev)) | |
762 | return -EINVAL; | |
dc7a9319 WZ |
763 | |
764 | if (!dev_priv) { | |
3e684eae | 765 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 766 | return -EINVAL; |
dc7a9319 | 767 | } |
dc7a9319 | 768 | |
c153f45f EA |
769 | printk(KERN_DEBUG "set status page addr 0x%08x\n", (u32)hws->addr); |
770 | ||
771 | dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12); | |
dc7a9319 | 772 | |
8b409580 | 773 | dev_priv->hws_map.offset = dev->agp->base + hws->addr; |
dc7a9319 WZ |
774 | dev_priv->hws_map.size = 4*1024; |
775 | dev_priv->hws_map.type = 0; | |
776 | dev_priv->hws_map.flags = 0; | |
777 | dev_priv->hws_map.mtrr = 0; | |
778 | ||
779 | drm_core_ioremap(&dev_priv->hws_map, dev); | |
780 | if (dev_priv->hws_map.handle == NULL) { | |
dc7a9319 WZ |
781 | i915_dma_cleanup(dev); |
782 | dev_priv->status_gfx_addr = 0; | |
783 | DRM_ERROR("can not ioremap virtual address for" | |
784 | " G33 hw status page\n"); | |
20caafa6 | 785 | return -ENOMEM; |
dc7a9319 WZ |
786 | } |
787 | dev_priv->hw_status_page = dev_priv->hws_map.handle; | |
788 | ||
789 | memset(dev_priv->hw_status_page, 0, PAGE_SIZE); | |
585fb111 JB |
790 | I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); |
791 | DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n", | |
dc7a9319 WZ |
792 | dev_priv->status_gfx_addr); |
793 | DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page); | |
794 | return 0; | |
795 | } | |
796 | ||
84b1fd10 | 797 | int i915_driver_load(struct drm_device *dev, unsigned long flags) |
22eae947 | 798 | { |
ba8bbcf6 JB |
799 | struct drm_i915_private *dev_priv = dev->dev_private; |
800 | unsigned long base, size; | |
801 | int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1; | |
802 | ||
22eae947 DA |
803 | /* i915 has 4 more counters */ |
804 | dev->counters += 4; | |
805 | dev->types[6] = _DRM_STAT_IRQ; | |
806 | dev->types[7] = _DRM_STAT_PRIMARY; | |
807 | dev->types[8] = _DRM_STAT_SECONDARY; | |
808 | dev->types[9] = _DRM_STAT_DMA; | |
809 | ||
ba8bbcf6 JB |
810 | dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER); |
811 | if (dev_priv == NULL) | |
812 | return -ENOMEM; | |
813 | ||
814 | memset(dev_priv, 0, sizeof(drm_i915_private_t)); | |
815 | ||
816 | dev->dev_private = (void *)dev_priv; | |
673a394b | 817 | dev_priv->dev = dev; |
ba8bbcf6 JB |
818 | |
819 | /* Add register map (needed for suspend/resume) */ | |
820 | base = drm_get_resource_start(dev, mmio_bar); | |
821 | size = drm_get_resource_len(dev, mmio_bar); | |
822 | ||
e3236a11 DA |
823 | ret = drm_addmap(dev, base, size, _DRM_REGISTERS, |
824 | _DRM_KERNEL | _DRM_DRIVER, | |
ba8bbcf6 | 825 | &dev_priv->mmio_map); |
ed4cb414 | 826 | |
673a394b EA |
827 | i915_gem_load(dev); |
828 | ||
398c9cb2 KP |
829 | /* Init HWS */ |
830 | if (!I915_NEED_GFX_HWS(dev)) { | |
831 | ret = i915_init_phys_hws(dev); | |
832 | if (ret != 0) | |
833 | return ret; | |
834 | } | |
ed4cb414 EA |
835 | |
836 | /* On the 945G/GM, the chipset reports the MSI capability on the | |
837 | * integrated graphics even though the support isn't actually there | |
838 | * according to the published specs. It doesn't appear to function | |
839 | * correctly in testing on 945G. | |
840 | * This may be a side effect of MSI having been made available for PEG | |
841 | * and the registers being closely associated. | |
842 | */ | |
843 | if (!IS_I945G(dev) && !IS_I945GM(dev)) | |
0a3e67a4 JB |
844 | if (pci_enable_msi(dev->pdev)) |
845 | DRM_ERROR("failed to enable MSI\n"); | |
ed4cb414 | 846 | |
8ee1c3db MG |
847 | intel_opregion_init(dev); |
848 | ||
ed4cb414 EA |
849 | spin_lock_init(&dev_priv->user_irq_lock); |
850 | ||
ba8bbcf6 JB |
851 | return ret; |
852 | } | |
853 | ||
854 | int i915_driver_unload(struct drm_device *dev) | |
855 | { | |
856 | struct drm_i915_private *dev_priv = dev->dev_private; | |
857 | ||
ed4cb414 EA |
858 | if (dev->pdev->msi_enabled) |
859 | pci_disable_msi(dev->pdev); | |
860 | ||
398c9cb2 KP |
861 | i915_free_hws(dev); |
862 | ||
ba8bbcf6 JB |
863 | if (dev_priv->mmio_map) |
864 | drm_rmmap(dev, dev_priv->mmio_map); | |
865 | ||
8ee1c3db MG |
866 | intel_opregion_free(dev); |
867 | ||
ba8bbcf6 JB |
868 | drm_free(dev->dev_private, sizeof(drm_i915_private_t), |
869 | DRM_MEM_DRIVER); | |
870 | ||
22eae947 DA |
871 | return 0; |
872 | } | |
873 | ||
673a394b EA |
874 | int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv) |
875 | { | |
876 | struct drm_i915_file_private *i915_file_priv; | |
877 | ||
878 | DRM_DEBUG("\n"); | |
879 | i915_file_priv = (struct drm_i915_file_private *) | |
880 | drm_alloc(sizeof(*i915_file_priv), DRM_MEM_FILES); | |
881 | ||
882 | if (!i915_file_priv) | |
883 | return -ENOMEM; | |
884 | ||
885 | file_priv->driver_priv = i915_file_priv; | |
886 | ||
887 | i915_file_priv->mm.last_gem_seqno = 0; | |
888 | i915_file_priv->mm.last_gem_throttle_seqno = 0; | |
889 | ||
890 | return 0; | |
891 | } | |
892 | ||
84b1fd10 | 893 | void i915_driver_lastclose(struct drm_device * dev) |
1da177e4 | 894 | { |
ba8bbcf6 JB |
895 | drm_i915_private_t *dev_priv = dev->dev_private; |
896 | ||
144a75fa DA |
897 | if (!dev_priv) |
898 | return; | |
899 | ||
673a394b EA |
900 | i915_gem_lastclose(dev); |
901 | ||
ba8bbcf6 | 902 | if (dev_priv->agp_heap) |
b5e89ed5 | 903 | i915_mem_takedown(&(dev_priv->agp_heap)); |
ba8bbcf6 | 904 | |
b5e89ed5 | 905 | i915_dma_cleanup(dev); |
1da177e4 LT |
906 | } |
907 | ||
6c340eac | 908 | void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv) |
1da177e4 | 909 | { |
ba8bbcf6 JB |
910 | drm_i915_private_t *dev_priv = dev->dev_private; |
911 | i915_mem_release(dev, file_priv, dev_priv->agp_heap); | |
1da177e4 LT |
912 | } |
913 | ||
673a394b EA |
914 | void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv) |
915 | { | |
916 | struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; | |
917 | ||
918 | drm_free(i915_file_priv, sizeof(*i915_file_priv), DRM_MEM_FILES); | |
919 | } | |
920 | ||
c153f45f EA |
921 | struct drm_ioctl_desc i915_ioctls[] = { |
922 | DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
923 | DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH), | |
924 | DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH), | |
925 | DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH), | |
926 | DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH), | |
927 | DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH), | |
928 | DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH), | |
929 | DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
930 | DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH), | |
931 | DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH), | |
932 | DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
933 | DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH), | |
934 | DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ), | |
935 | DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ), | |
936 | DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ), | |
937 | DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH), | |
938 | DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH), | |
673a394b EA |
939 | DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH), |
940 | DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH), | |
941 | DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), | |
942 | DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), | |
943 | DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH), | |
944 | DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH), | |
945 | DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH), | |
946 | DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH), | |
947 | DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0), | |
948 | DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, 0), | |
949 | DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, 0), | |
950 | DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0), | |
951 | DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, 0), | |
952 | DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0), | |
953 | DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0), | |
954 | DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0), | |
c94f7029 DA |
955 | }; |
956 | ||
957 | int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); | |
cda17380 DA |
958 | |
959 | /** | |
960 | * Determine if the device really is AGP or not. | |
961 | * | |
962 | * All Intel graphics chipsets are treated as AGP, even if they are really | |
963 | * PCI-e. | |
964 | * | |
965 | * \param dev The device to be tested. | |
966 | * | |
967 | * \returns | |
968 | * A value of 1 is always retured to indictate every i9x5 is AGP. | |
969 | */ | |
84b1fd10 | 970 | int i915_driver_device_is_agp(struct drm_device * dev) |
cda17380 DA |
971 | { |
972 | return 1; | |
973 | } |