Commit | Line | Data |
---|---|---|
2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
b2c88f5b | 30 | #include <linux/circ_buf.h> |
926321d5 | 31 | #include <linux/ctype.h> |
f3cd474b | 32 | #include <linux/debugfs.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
2d1a8a48 | 34 | #include <linux/export.h> |
6d2b8885 | 35 | #include <linux/list_sort.h> |
ec013e7f | 36 | #include <asm/msr-index.h> |
760285e7 | 37 | #include <drm/drmP.h> |
4e5359cd | 38 | #include "intel_drv.h" |
e5c65260 | 39 | #include "intel_ringbuffer.h" |
760285e7 | 40 | #include <drm/i915_drm.h> |
2017263e BG |
41 | #include "i915_drv.h" |
42 | ||
f13d3f73 | 43 | enum { |
69dc4987 | 44 | ACTIVE_LIST, |
f13d3f73 | 45 | INACTIVE_LIST, |
d21d5975 | 46 | PINNED_LIST, |
f13d3f73 | 47 | }; |
2017263e | 48 | |
497666d8 DL |
49 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
50 | * allocated we need to hook into the minor for release. */ | |
51 | static int | |
52 | drm_add_fake_info_node(struct drm_minor *minor, | |
53 | struct dentry *ent, | |
54 | const void *key) | |
55 | { | |
56 | struct drm_info_node *node; | |
57 | ||
58 | node = kmalloc(sizeof(*node), GFP_KERNEL); | |
59 | if (node == NULL) { | |
60 | debugfs_remove(ent); | |
61 | return -ENOMEM; | |
62 | } | |
63 | ||
64 | node->minor = minor; | |
65 | node->dent = ent; | |
66 | node->info_ent = (void *) key; | |
67 | ||
68 | mutex_lock(&minor->debugfs_lock); | |
69 | list_add(&node->list, &minor->debugfs_list); | |
70 | mutex_unlock(&minor->debugfs_lock); | |
71 | ||
72 | return 0; | |
73 | } | |
74 | ||
70d39fe4 CW |
75 | static int i915_capabilities(struct seq_file *m, void *data) |
76 | { | |
9f25d007 | 77 | struct drm_info_node *node = m->private; |
70d39fe4 CW |
78 | struct drm_device *dev = node->minor->dev; |
79 | const struct intel_device_info *info = INTEL_INFO(dev); | |
80 | ||
81 | seq_printf(m, "gen: %d\n", info->gen); | |
03d00ac5 | 82 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
79fc46df DL |
83 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
84 | #define SEP_SEMICOLON ; | |
85 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); | |
86 | #undef PRINT_FLAG | |
87 | #undef SEP_SEMICOLON | |
70d39fe4 CW |
88 | |
89 | return 0; | |
90 | } | |
2017263e | 91 | |
a7363de7 | 92 | static char get_active_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 93 | { |
be12a86b | 94 | return obj->active ? '*' : ' '; |
a6172a80 CW |
95 | } |
96 | ||
a7363de7 | 97 | static char get_pin_flag(struct drm_i915_gem_object *obj) |
be12a86b TU |
98 | { |
99 | return obj->pin_display ? 'p' : ' '; | |
100 | } | |
101 | ||
a7363de7 | 102 | static char get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 103 | { |
0206e353 AJ |
104 | switch (obj->tiling_mode) { |
105 | default: | |
be12a86b TU |
106 | case I915_TILING_NONE: return ' '; |
107 | case I915_TILING_X: return 'X'; | |
108 | case I915_TILING_Y: return 'Y'; | |
0206e353 | 109 | } |
a6172a80 CW |
110 | } |
111 | ||
a7363de7 | 112 | static char get_global_flag(struct drm_i915_gem_object *obj) |
be12a86b TU |
113 | { |
114 | return i915_gem_obj_to_ggtt(obj) ? 'g' : ' '; | |
115 | } | |
116 | ||
a7363de7 | 117 | static char get_pin_mapped_flag(struct drm_i915_gem_object *obj) |
1d693bcc | 118 | { |
be12a86b | 119 | return obj->mapping ? 'M' : ' '; |
1d693bcc BW |
120 | } |
121 | ||
ca1543be TU |
122 | static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj) |
123 | { | |
124 | u64 size = 0; | |
125 | struct i915_vma *vma; | |
126 | ||
1c7f4bca | 127 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
596c5923 | 128 | if (vma->is_ggtt && drm_mm_node_allocated(&vma->node)) |
ca1543be TU |
129 | size += vma->node.size; |
130 | } | |
131 | ||
132 | return size; | |
133 | } | |
134 | ||
37811fcc CW |
135 | static void |
136 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
137 | { | |
b4716185 | 138 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e2f80391 | 139 | struct intel_engine_cs *engine; |
1d693bcc | 140 | struct i915_vma *vma; |
d7f46fc4 | 141 | int pin_count = 0; |
c3232b18 | 142 | enum intel_engine_id id; |
d7f46fc4 | 143 | |
188c1ab7 CW |
144 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
145 | ||
be12a86b | 146 | seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ", |
37811fcc | 147 | &obj->base, |
be12a86b | 148 | get_active_flag(obj), |
37811fcc CW |
149 | get_pin_flag(obj), |
150 | get_tiling_flag(obj), | |
1d693bcc | 151 | get_global_flag(obj), |
be12a86b | 152 | get_pin_mapped_flag(obj), |
a05a5862 | 153 | obj->base.size / 1024, |
37811fcc | 154 | obj->base.read_domains, |
b4716185 | 155 | obj->base.write_domain); |
c3232b18 | 156 | for_each_engine_id(engine, dev_priv, id) |
b4716185 | 157 | seq_printf(m, "%x ", |
c3232b18 | 158 | i915_gem_request_get_seqno(obj->last_read_req[id])); |
b4716185 | 159 | seq_printf(m, "] %x %x%s%s%s", |
97b2a6a1 JH |
160 | i915_gem_request_get_seqno(obj->last_write_req), |
161 | i915_gem_request_get_seqno(obj->last_fenced_req), | |
0a4cd7c8 | 162 | i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level), |
37811fcc CW |
163 | obj->dirty ? " dirty" : "", |
164 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
165 | if (obj->base.name) | |
166 | seq_printf(m, " (name: %d)", obj->base.name); | |
1c7f4bca | 167 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
d7f46fc4 BW |
168 | if (vma->pin_count > 0) |
169 | pin_count++; | |
ba0635ff DC |
170 | } |
171 | seq_printf(m, " (pinned x %d)", pin_count); | |
cc98b413 CW |
172 | if (obj->pin_display) |
173 | seq_printf(m, " (display)"); | |
37811fcc CW |
174 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
175 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
1c7f4bca | 176 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
8d2fdc3f | 177 | seq_printf(m, " (%sgtt offset: %08llx, size: %08llx", |
596c5923 | 178 | vma->is_ggtt ? "g" : "pp", |
8d2fdc3f | 179 | vma->node.start, vma->node.size); |
596c5923 CW |
180 | if (vma->is_ggtt) |
181 | seq_printf(m, ", type: %u", vma->ggtt_view.type); | |
182 | seq_puts(m, ")"); | |
1d693bcc | 183 | } |
c1ad11fc | 184 | if (obj->stolen) |
440fd528 | 185 | seq_printf(m, " (stolen: %08llx)", obj->stolen->start); |
30154650 | 186 | if (obj->pin_display || obj->fault_mappable) { |
6299f992 | 187 | char s[3], *t = s; |
30154650 | 188 | if (obj->pin_display) |
6299f992 CW |
189 | *t++ = 'p'; |
190 | if (obj->fault_mappable) | |
191 | *t++ = 'f'; | |
192 | *t = '\0'; | |
193 | seq_printf(m, " (%s mappable)", s); | |
194 | } | |
b4716185 | 195 | if (obj->last_write_req != NULL) |
41c52415 | 196 | seq_printf(m, " (%s)", |
666796da | 197 | i915_gem_request_get_engine(obj->last_write_req)->name); |
d5a81ef1 DV |
198 | if (obj->frontbuffer_bits) |
199 | seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits); | |
37811fcc CW |
200 | } |
201 | ||
273497e5 | 202 | static void describe_ctx(struct seq_file *m, struct intel_context *ctx) |
3ccfd19d | 203 | { |
ea0c76f8 | 204 | seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i'); |
3ccfd19d BW |
205 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); |
206 | seq_putc(m, ' '); | |
207 | } | |
208 | ||
433e12f7 | 209 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
2017263e | 210 | { |
9f25d007 | 211 | struct drm_info_node *node = m->private; |
433e12f7 BG |
212 | uintptr_t list = (uintptr_t) node->info_ent->data; |
213 | struct list_head *head; | |
2017263e | 214 | struct drm_device *dev = node->minor->dev; |
72e96d64 JL |
215 | struct drm_i915_private *dev_priv = to_i915(dev); |
216 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
ca191b13 | 217 | struct i915_vma *vma; |
c44ef60e | 218 | u64 total_obj_size, total_gtt_size; |
8f2480fb | 219 | int count, ret; |
de227ef0 CW |
220 | |
221 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
222 | if (ret) | |
223 | return ret; | |
2017263e | 224 | |
ca191b13 | 225 | /* FIXME: the user of this interface might want more than just GGTT */ |
433e12f7 BG |
226 | switch (list) { |
227 | case ACTIVE_LIST: | |
267f0c90 | 228 | seq_puts(m, "Active:\n"); |
72e96d64 | 229 | head = &ggtt->base.active_list; |
433e12f7 BG |
230 | break; |
231 | case INACTIVE_LIST: | |
267f0c90 | 232 | seq_puts(m, "Inactive:\n"); |
72e96d64 | 233 | head = &ggtt->base.inactive_list; |
433e12f7 | 234 | break; |
433e12f7 | 235 | default: |
de227ef0 CW |
236 | mutex_unlock(&dev->struct_mutex); |
237 | return -EINVAL; | |
2017263e | 238 | } |
2017263e | 239 | |
8f2480fb | 240 | total_obj_size = total_gtt_size = count = 0; |
1c7f4bca | 241 | list_for_each_entry(vma, head, vm_link) { |
ca191b13 BW |
242 | seq_printf(m, " "); |
243 | describe_obj(m, vma->obj); | |
244 | seq_printf(m, "\n"); | |
245 | total_obj_size += vma->obj->base.size; | |
246 | total_gtt_size += vma->node.size; | |
8f2480fb | 247 | count++; |
2017263e | 248 | } |
de227ef0 | 249 | mutex_unlock(&dev->struct_mutex); |
5e118f41 | 250 | |
c44ef60e | 251 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
8f2480fb | 252 | count, total_obj_size, total_gtt_size); |
2017263e BG |
253 | return 0; |
254 | } | |
255 | ||
6d2b8885 CW |
256 | static int obj_rank_by_stolen(void *priv, |
257 | struct list_head *A, struct list_head *B) | |
258 | { | |
259 | struct drm_i915_gem_object *a = | |
b25cb2f8 | 260 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 261 | struct drm_i915_gem_object *b = |
b25cb2f8 | 262 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 263 | |
2d05fa16 RV |
264 | if (a->stolen->start < b->stolen->start) |
265 | return -1; | |
266 | if (a->stolen->start > b->stolen->start) | |
267 | return 1; | |
268 | return 0; | |
6d2b8885 CW |
269 | } |
270 | ||
271 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
272 | { | |
9f25d007 | 273 | struct drm_info_node *node = m->private; |
6d2b8885 CW |
274 | struct drm_device *dev = node->minor->dev; |
275 | struct drm_i915_private *dev_priv = dev->dev_private; | |
276 | struct drm_i915_gem_object *obj; | |
c44ef60e | 277 | u64 total_obj_size, total_gtt_size; |
6d2b8885 CW |
278 | LIST_HEAD(stolen); |
279 | int count, ret; | |
280 | ||
281 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
282 | if (ret) | |
283 | return ret; | |
284 | ||
285 | total_obj_size = total_gtt_size = count = 0; | |
286 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
287 | if (obj->stolen == NULL) | |
288 | continue; | |
289 | ||
b25cb2f8 | 290 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
291 | |
292 | total_obj_size += obj->base.size; | |
ca1543be | 293 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
6d2b8885 CW |
294 | count++; |
295 | } | |
296 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
297 | if (obj->stolen == NULL) | |
298 | continue; | |
299 | ||
b25cb2f8 | 300 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
301 | |
302 | total_obj_size += obj->base.size; | |
303 | count++; | |
304 | } | |
305 | list_sort(NULL, &stolen, obj_rank_by_stolen); | |
306 | seq_puts(m, "Stolen:\n"); | |
307 | while (!list_empty(&stolen)) { | |
b25cb2f8 | 308 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
6d2b8885 CW |
309 | seq_puts(m, " "); |
310 | describe_obj(m, obj); | |
311 | seq_putc(m, '\n'); | |
b25cb2f8 | 312 | list_del_init(&obj->obj_exec_link); |
6d2b8885 CW |
313 | } |
314 | mutex_unlock(&dev->struct_mutex); | |
315 | ||
c44ef60e | 316 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
6d2b8885 CW |
317 | count, total_obj_size, total_gtt_size); |
318 | return 0; | |
319 | } | |
320 | ||
6299f992 CW |
321 | #define count_objects(list, member) do { \ |
322 | list_for_each_entry(obj, list, member) { \ | |
ca1543be | 323 | size += i915_gem_obj_total_ggtt_size(obj); \ |
6299f992 CW |
324 | ++count; \ |
325 | if (obj->map_and_fenceable) { \ | |
f343c5f6 | 326 | mappable_size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
327 | ++mappable_count; \ |
328 | } \ | |
329 | } \ | |
0206e353 | 330 | } while (0) |
6299f992 | 331 | |
2db8e9d6 | 332 | struct file_stats { |
6313c204 | 333 | struct drm_i915_file_private *file_priv; |
c44ef60e MK |
334 | unsigned long count; |
335 | u64 total, unbound; | |
336 | u64 global, shared; | |
337 | u64 active, inactive; | |
2db8e9d6 CW |
338 | }; |
339 | ||
340 | static int per_file_stats(int id, void *ptr, void *data) | |
341 | { | |
342 | struct drm_i915_gem_object *obj = ptr; | |
343 | struct file_stats *stats = data; | |
6313c204 | 344 | struct i915_vma *vma; |
2db8e9d6 CW |
345 | |
346 | stats->count++; | |
347 | stats->total += obj->base.size; | |
348 | ||
c67a17e9 CW |
349 | if (obj->base.name || obj->base.dma_buf) |
350 | stats->shared += obj->base.size; | |
351 | ||
6313c204 | 352 | if (USES_FULL_PPGTT(obj->base.dev)) { |
1c7f4bca | 353 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
6313c204 CW |
354 | struct i915_hw_ppgtt *ppgtt; |
355 | ||
356 | if (!drm_mm_node_allocated(&vma->node)) | |
357 | continue; | |
358 | ||
596c5923 | 359 | if (vma->is_ggtt) { |
6313c204 CW |
360 | stats->global += obj->base.size; |
361 | continue; | |
362 | } | |
363 | ||
364 | ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base); | |
4d884705 | 365 | if (ppgtt->file_priv != stats->file_priv) |
6313c204 CW |
366 | continue; |
367 | ||
41c52415 | 368 | if (obj->active) /* XXX per-vma statistic */ |
6313c204 CW |
369 | stats->active += obj->base.size; |
370 | else | |
371 | stats->inactive += obj->base.size; | |
372 | ||
373 | return 0; | |
374 | } | |
2db8e9d6 | 375 | } else { |
6313c204 CW |
376 | if (i915_gem_obj_ggtt_bound(obj)) { |
377 | stats->global += obj->base.size; | |
41c52415 | 378 | if (obj->active) |
6313c204 CW |
379 | stats->active += obj->base.size; |
380 | else | |
381 | stats->inactive += obj->base.size; | |
382 | return 0; | |
383 | } | |
2db8e9d6 CW |
384 | } |
385 | ||
6313c204 CW |
386 | if (!list_empty(&obj->global_list)) |
387 | stats->unbound += obj->base.size; | |
388 | ||
2db8e9d6 CW |
389 | return 0; |
390 | } | |
391 | ||
b0da1b79 CW |
392 | #define print_file_stats(m, name, stats) do { \ |
393 | if (stats.count) \ | |
c44ef60e | 394 | seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \ |
b0da1b79 CW |
395 | name, \ |
396 | stats.count, \ | |
397 | stats.total, \ | |
398 | stats.active, \ | |
399 | stats.inactive, \ | |
400 | stats.global, \ | |
401 | stats.shared, \ | |
402 | stats.unbound); \ | |
403 | } while (0) | |
493018dc BV |
404 | |
405 | static void print_batch_pool_stats(struct seq_file *m, | |
406 | struct drm_i915_private *dev_priv) | |
407 | { | |
408 | struct drm_i915_gem_object *obj; | |
409 | struct file_stats stats; | |
e2f80391 | 410 | struct intel_engine_cs *engine; |
b4ac5afc | 411 | int j; |
493018dc BV |
412 | |
413 | memset(&stats, 0, sizeof(stats)); | |
414 | ||
b4ac5afc | 415 | for_each_engine(engine, dev_priv) { |
e2f80391 | 416 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 | 417 | list_for_each_entry(obj, |
e2f80391 | 418 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
419 | batch_pool_link) |
420 | per_file_stats(0, obj, &stats); | |
421 | } | |
06fbca71 | 422 | } |
493018dc | 423 | |
b0da1b79 | 424 | print_file_stats(m, "[k]batch pool", stats); |
493018dc BV |
425 | } |
426 | ||
ca191b13 BW |
427 | #define count_vmas(list, member) do { \ |
428 | list_for_each_entry(vma, list, member) { \ | |
ca1543be | 429 | size += i915_gem_obj_total_ggtt_size(vma->obj); \ |
ca191b13 BW |
430 | ++count; \ |
431 | if (vma->obj->map_and_fenceable) { \ | |
432 | mappable_size += i915_gem_obj_ggtt_size(vma->obj); \ | |
433 | ++mappable_count; \ | |
434 | } \ | |
435 | } \ | |
436 | } while (0) | |
437 | ||
438 | static int i915_gem_object_info(struct seq_file *m, void* data) | |
73aa808f | 439 | { |
9f25d007 | 440 | struct drm_info_node *node = m->private; |
73aa808f | 441 | struct drm_device *dev = node->minor->dev; |
72e96d64 JL |
442 | struct drm_i915_private *dev_priv = to_i915(dev); |
443 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
b7abb714 | 444 | u32 count, mappable_count, purgeable_count; |
c44ef60e | 445 | u64 size, mappable_size, purgeable_size; |
be19b10d TU |
446 | unsigned long pin_mapped_count = 0, pin_mapped_purgeable_count = 0; |
447 | u64 pin_mapped_size = 0, pin_mapped_purgeable_size = 0; | |
6299f992 | 448 | struct drm_i915_gem_object *obj; |
2db8e9d6 | 449 | struct drm_file *file; |
ca191b13 | 450 | struct i915_vma *vma; |
73aa808f CW |
451 | int ret; |
452 | ||
453 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
454 | if (ret) | |
455 | return ret; | |
456 | ||
6299f992 CW |
457 | seq_printf(m, "%u objects, %zu bytes\n", |
458 | dev_priv->mm.object_count, | |
459 | dev_priv->mm.object_memory); | |
460 | ||
461 | size = count = mappable_size = mappable_count = 0; | |
35c20a60 | 462 | count_objects(&dev_priv->mm.bound_list, global_list); |
c44ef60e | 463 | seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n", |
6299f992 CW |
464 | count, mappable_count, size, mappable_size); |
465 | ||
466 | size = count = mappable_size = mappable_count = 0; | |
72e96d64 | 467 | count_vmas(&ggtt->base.active_list, vm_link); |
c44ef60e | 468 | seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n", |
6299f992 CW |
469 | count, mappable_count, size, mappable_size); |
470 | ||
6299f992 | 471 | size = count = mappable_size = mappable_count = 0; |
72e96d64 | 472 | count_vmas(&ggtt->base.inactive_list, vm_link); |
c44ef60e | 473 | seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n", |
6299f992 CW |
474 | count, mappable_count, size, mappable_size); |
475 | ||
b7abb714 | 476 | size = count = purgeable_size = purgeable_count = 0; |
35c20a60 | 477 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
6c085a72 | 478 | size += obj->base.size, ++count; |
b7abb714 CW |
479 | if (obj->madv == I915_MADV_DONTNEED) |
480 | purgeable_size += obj->base.size, ++purgeable_count; | |
be19b10d TU |
481 | if (obj->mapping) { |
482 | pin_mapped_count++; | |
483 | pin_mapped_size += obj->base.size; | |
484 | if (obj->pages_pin_count == 0) { | |
485 | pin_mapped_purgeable_count++; | |
486 | pin_mapped_purgeable_size += obj->base.size; | |
487 | } | |
488 | } | |
b7abb714 | 489 | } |
c44ef60e | 490 | seq_printf(m, "%u unbound objects, %llu bytes\n", count, size); |
6c085a72 | 491 | |
6299f992 | 492 | size = count = mappable_size = mappable_count = 0; |
35c20a60 | 493 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6299f992 | 494 | if (obj->fault_mappable) { |
f343c5f6 | 495 | size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
496 | ++count; |
497 | } | |
30154650 | 498 | if (obj->pin_display) { |
f343c5f6 | 499 | mappable_size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
500 | ++mappable_count; |
501 | } | |
b7abb714 CW |
502 | if (obj->madv == I915_MADV_DONTNEED) { |
503 | purgeable_size += obj->base.size; | |
504 | ++purgeable_count; | |
505 | } | |
be19b10d TU |
506 | if (obj->mapping) { |
507 | pin_mapped_count++; | |
508 | pin_mapped_size += obj->base.size; | |
509 | if (obj->pages_pin_count == 0) { | |
510 | pin_mapped_purgeable_count++; | |
511 | pin_mapped_purgeable_size += obj->base.size; | |
512 | } | |
513 | } | |
6299f992 | 514 | } |
c44ef60e | 515 | seq_printf(m, "%u purgeable objects, %llu bytes\n", |
b7abb714 | 516 | purgeable_count, purgeable_size); |
c44ef60e | 517 | seq_printf(m, "%u pinned mappable objects, %llu bytes\n", |
6299f992 | 518 | mappable_count, mappable_size); |
c44ef60e | 519 | seq_printf(m, "%u fault mappable objects, %llu bytes\n", |
6299f992 | 520 | count, size); |
be19b10d TU |
521 | seq_printf(m, |
522 | "%lu [%lu] pin mapped objects, %llu [%llu] bytes [purgeable]\n", | |
523 | pin_mapped_count, pin_mapped_purgeable_count, | |
524 | pin_mapped_size, pin_mapped_purgeable_size); | |
6299f992 | 525 | |
c44ef60e | 526 | seq_printf(m, "%llu [%llu] gtt total\n", |
72e96d64 | 527 | ggtt->base.total, ggtt->mappable_end - ggtt->base.start); |
73aa808f | 528 | |
493018dc BV |
529 | seq_putc(m, '\n'); |
530 | print_batch_pool_stats(m, dev_priv); | |
1d2ac403 DV |
531 | |
532 | mutex_unlock(&dev->struct_mutex); | |
533 | ||
534 | mutex_lock(&dev->filelist_mutex); | |
2db8e9d6 CW |
535 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
536 | struct file_stats stats; | |
3ec2f427 | 537 | struct task_struct *task; |
2db8e9d6 CW |
538 | |
539 | memset(&stats, 0, sizeof(stats)); | |
6313c204 | 540 | stats.file_priv = file->driver_priv; |
5b5ffff0 | 541 | spin_lock(&file->table_lock); |
2db8e9d6 | 542 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
5b5ffff0 | 543 | spin_unlock(&file->table_lock); |
3ec2f427 TH |
544 | /* |
545 | * Although we have a valid reference on file->pid, that does | |
546 | * not guarantee that the task_struct who called get_pid() is | |
547 | * still alive (e.g. get_pid(current) => fork() => exit()). | |
548 | * Therefore, we need to protect this ->comm access using RCU. | |
549 | */ | |
550 | rcu_read_lock(); | |
551 | task = pid_task(file->pid, PIDTYPE_PID); | |
493018dc | 552 | print_file_stats(m, task ? task->comm : "<unknown>", stats); |
3ec2f427 | 553 | rcu_read_unlock(); |
2db8e9d6 | 554 | } |
1d2ac403 | 555 | mutex_unlock(&dev->filelist_mutex); |
73aa808f CW |
556 | |
557 | return 0; | |
558 | } | |
559 | ||
aee56cff | 560 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 | 561 | { |
9f25d007 | 562 | struct drm_info_node *node = m->private; |
08c18323 | 563 | struct drm_device *dev = node->minor->dev; |
1b50247a | 564 | uintptr_t list = (uintptr_t) node->info_ent->data; |
08c18323 CW |
565 | struct drm_i915_private *dev_priv = dev->dev_private; |
566 | struct drm_i915_gem_object *obj; | |
c44ef60e | 567 | u64 total_obj_size, total_gtt_size; |
08c18323 CW |
568 | int count, ret; |
569 | ||
570 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
571 | if (ret) | |
572 | return ret; | |
573 | ||
574 | total_obj_size = total_gtt_size = count = 0; | |
35c20a60 | 575 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
d7f46fc4 | 576 | if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj)) |
1b50247a CW |
577 | continue; |
578 | ||
267f0c90 | 579 | seq_puts(m, " "); |
08c18323 | 580 | describe_obj(m, obj); |
267f0c90 | 581 | seq_putc(m, '\n'); |
08c18323 | 582 | total_obj_size += obj->base.size; |
ca1543be | 583 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
08c18323 CW |
584 | count++; |
585 | } | |
586 | ||
587 | mutex_unlock(&dev->struct_mutex); | |
588 | ||
c44ef60e | 589 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
08c18323 CW |
590 | count, total_obj_size, total_gtt_size); |
591 | ||
592 | return 0; | |
593 | } | |
594 | ||
6885843a ML |
595 | static void i915_dump_pageflip(struct seq_file *m, |
596 | struct drm_i915_private *dev_priv, | |
597 | struct intel_crtc *crtc, | |
598 | struct intel_flip_work *work) | |
599 | { | |
600 | const char pipe = pipe_name(crtc->pipe); | |
6885843a | 601 | u32 pending; |
143f73b3 | 602 | int i; |
6885843a ML |
603 | |
604 | pending = atomic_read(&work->pending); | |
605 | if (pending) { | |
606 | seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n", | |
143f73b3 | 607 | pipe, plane_name(crtc->plane)); |
6885843a ML |
608 | } else { |
609 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", | |
143f73b3 | 610 | pipe, plane_name(crtc->plane)); |
6885843a | 611 | } |
6885843a | 612 | |
143f73b3 ML |
613 | for (i = 0; i < work->num_planes; i++) { |
614 | struct intel_plane_state *old_plane_state = work->old_plane_state[i]; | |
615 | struct drm_plane *plane = old_plane_state->base.plane; | |
616 | struct drm_i915_gem_request *req = old_plane_state->wait_req; | |
617 | struct intel_engine_cs *engine; | |
618 | ||
619 | seq_printf(m, "[PLANE:%i] part of flip.\n", plane->base.id); | |
620 | ||
621 | if (!req) { | |
622 | seq_printf(m, "Plane not associated with any engine\n"); | |
623 | continue; | |
624 | } | |
625 | ||
626 | engine = i915_gem_request_get_engine(req); | |
627 | ||
628 | seq_printf(m, "Plane blocked on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n", | |
6885843a | 629 | engine->name, |
143f73b3 | 630 | i915_gem_request_get_seqno(req), |
6885843a ML |
631 | dev_priv->next_seqno, |
632 | engine->get_seqno(engine), | |
143f73b3 ML |
633 | i915_gem_request_completed(req, true)); |
634 | } | |
635 | ||
8dd634d9 ML |
636 | seq_printf(m, "Flip queued on frame %d, now %d\n", |
637 | pending ? work->flip_queued_vblank : -1, | |
6885843a | 638 | intel_crtc_get_vblank_counter(crtc)); |
6885843a ML |
639 | } |
640 | ||
4e5359cd SF |
641 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
642 | { | |
9f25d007 | 643 | struct drm_info_node *node = m->private; |
4e5359cd | 644 | struct drm_device *dev = node->minor->dev; |
d6bbafa1 | 645 | struct drm_i915_private *dev_priv = dev->dev_private; |
4e5359cd | 646 | struct intel_crtc *crtc; |
8a270ebf DV |
647 | int ret; |
648 | ||
649 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
650 | if (ret) | |
651 | return ret; | |
4e5359cd | 652 | |
d3fcc808 | 653 | for_each_intel_crtc(dev, crtc) { |
9db4a9c7 JB |
654 | const char pipe = pipe_name(crtc->pipe); |
655 | const char plane = plane_name(crtc->plane); | |
51cbaf01 | 656 | struct intel_flip_work *work; |
4e5359cd | 657 | |
5e2d7afc | 658 | spin_lock_irq(&dev->event_lock); |
6885843a | 659 | if (list_empty(&crtc->flip_work)) { |
9db4a9c7 | 660 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
661 | pipe, plane); |
662 | } else { | |
6885843a ML |
663 | list_for_each_entry(work, &crtc->flip_work, head) { |
664 | i915_dump_pageflip(m, dev_priv, crtc, work); | |
665 | seq_puts(m, "\n"); | |
4e5359cd SF |
666 | } |
667 | } | |
5e2d7afc | 668 | spin_unlock_irq(&dev->event_lock); |
4e5359cd SF |
669 | } |
670 | ||
8a270ebf DV |
671 | mutex_unlock(&dev->struct_mutex); |
672 | ||
4e5359cd SF |
673 | return 0; |
674 | } | |
675 | ||
493018dc BV |
676 | static int i915_gem_batch_pool_info(struct seq_file *m, void *data) |
677 | { | |
678 | struct drm_info_node *node = m->private; | |
679 | struct drm_device *dev = node->minor->dev; | |
680 | struct drm_i915_private *dev_priv = dev->dev_private; | |
681 | struct drm_i915_gem_object *obj; | |
e2f80391 | 682 | struct intel_engine_cs *engine; |
8d9d5744 | 683 | int total = 0; |
b4ac5afc | 684 | int ret, j; |
493018dc BV |
685 | |
686 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
687 | if (ret) | |
688 | return ret; | |
689 | ||
b4ac5afc | 690 | for_each_engine(engine, dev_priv) { |
e2f80391 | 691 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 CW |
692 | int count; |
693 | ||
694 | count = 0; | |
695 | list_for_each_entry(obj, | |
e2f80391 | 696 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
697 | batch_pool_link) |
698 | count++; | |
699 | seq_printf(m, "%s cache[%d]: %d objects\n", | |
e2f80391 | 700 | engine->name, j, count); |
8d9d5744 CW |
701 | |
702 | list_for_each_entry(obj, | |
e2f80391 | 703 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
704 | batch_pool_link) { |
705 | seq_puts(m, " "); | |
706 | describe_obj(m, obj); | |
707 | seq_putc(m, '\n'); | |
708 | } | |
709 | ||
710 | total += count; | |
06fbca71 | 711 | } |
493018dc BV |
712 | } |
713 | ||
8d9d5744 | 714 | seq_printf(m, "total: %d\n", total); |
493018dc BV |
715 | |
716 | mutex_unlock(&dev->struct_mutex); | |
717 | ||
718 | return 0; | |
719 | } | |
720 | ||
2017263e BG |
721 | static int i915_gem_request_info(struct seq_file *m, void *data) |
722 | { | |
9f25d007 | 723 | struct drm_info_node *node = m->private; |
2017263e | 724 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 725 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 726 | struct intel_engine_cs *engine; |
eed29a5b | 727 | struct drm_i915_gem_request *req; |
b4ac5afc | 728 | int ret, any; |
de227ef0 CW |
729 | |
730 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
731 | if (ret) | |
732 | return ret; | |
2017263e | 733 | |
2d1070b2 | 734 | any = 0; |
b4ac5afc | 735 | for_each_engine(engine, dev_priv) { |
2d1070b2 CW |
736 | int count; |
737 | ||
738 | count = 0; | |
e2f80391 | 739 | list_for_each_entry(req, &engine->request_list, list) |
2d1070b2 CW |
740 | count++; |
741 | if (count == 0) | |
a2c7f6fd CW |
742 | continue; |
743 | ||
e2f80391 TU |
744 | seq_printf(m, "%s requests: %d\n", engine->name, count); |
745 | list_for_each_entry(req, &engine->request_list, list) { | |
2d1070b2 CW |
746 | struct task_struct *task; |
747 | ||
748 | rcu_read_lock(); | |
749 | task = NULL; | |
eed29a5b DV |
750 | if (req->pid) |
751 | task = pid_task(req->pid, PIDTYPE_PID); | |
2d1070b2 | 752 | seq_printf(m, " %x @ %d: %s [%d]\n", |
eed29a5b DV |
753 | req->seqno, |
754 | (int) (jiffies - req->emitted_jiffies), | |
2d1070b2 CW |
755 | task ? task->comm : "<unknown>", |
756 | task ? task->pid : -1); | |
757 | rcu_read_unlock(); | |
c2c347a9 | 758 | } |
2d1070b2 CW |
759 | |
760 | any++; | |
2017263e | 761 | } |
de227ef0 CW |
762 | mutex_unlock(&dev->struct_mutex); |
763 | ||
2d1070b2 | 764 | if (any == 0) |
267f0c90 | 765 | seq_puts(m, "No requests\n"); |
c2c347a9 | 766 | |
2017263e BG |
767 | return 0; |
768 | } | |
769 | ||
b2223497 | 770 | static void i915_ring_seqno_info(struct seq_file *m, |
0bc40be8 | 771 | struct intel_engine_cs *engine) |
b2223497 | 772 | { |
12471ba8 CW |
773 | seq_printf(m, "Current sequence (%s): %x\n", |
774 | engine->name, engine->get_seqno(engine)); | |
775 | seq_printf(m, "Current user interrupts (%s): %x\n", | |
776 | engine->name, READ_ONCE(engine->user_interrupts)); | |
b2223497 CW |
777 | } |
778 | ||
2017263e BG |
779 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
780 | { | |
9f25d007 | 781 | struct drm_info_node *node = m->private; |
2017263e | 782 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 783 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 784 | struct intel_engine_cs *engine; |
b4ac5afc | 785 | int ret; |
de227ef0 CW |
786 | |
787 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
788 | if (ret) | |
789 | return ret; | |
c8c8fb33 | 790 | intel_runtime_pm_get(dev_priv); |
2017263e | 791 | |
b4ac5afc | 792 | for_each_engine(engine, dev_priv) |
e2f80391 | 793 | i915_ring_seqno_info(m, engine); |
de227ef0 | 794 | |
c8c8fb33 | 795 | intel_runtime_pm_put(dev_priv); |
de227ef0 CW |
796 | mutex_unlock(&dev->struct_mutex); |
797 | ||
2017263e BG |
798 | return 0; |
799 | } | |
800 | ||
801 | ||
802 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
803 | { | |
9f25d007 | 804 | struct drm_info_node *node = m->private; |
2017263e | 805 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 806 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 807 | struct intel_engine_cs *engine; |
9db4a9c7 | 808 | int ret, i, pipe; |
de227ef0 CW |
809 | |
810 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
811 | if (ret) | |
812 | return ret; | |
c8c8fb33 | 813 | intel_runtime_pm_get(dev_priv); |
2017263e | 814 | |
74e1ca8c | 815 | if (IS_CHERRYVIEW(dev)) { |
74e1ca8c VS |
816 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
817 | I915_READ(GEN8_MASTER_IRQ)); | |
818 | ||
819 | seq_printf(m, "Display IER:\t%08x\n", | |
820 | I915_READ(VLV_IER)); | |
821 | seq_printf(m, "Display IIR:\t%08x\n", | |
822 | I915_READ(VLV_IIR)); | |
823 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
824 | I915_READ(VLV_IIR_RW)); | |
825 | seq_printf(m, "Display IMR:\t%08x\n", | |
826 | I915_READ(VLV_IMR)); | |
055e393f | 827 | for_each_pipe(dev_priv, pipe) |
74e1ca8c VS |
828 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
829 | pipe_name(pipe), | |
830 | I915_READ(PIPESTAT(pipe))); | |
831 | ||
832 | seq_printf(m, "Port hotplug:\t%08x\n", | |
833 | I915_READ(PORT_HOTPLUG_EN)); | |
834 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
835 | I915_READ(VLV_DPFLIPSTAT)); | |
836 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
837 | I915_READ(DPINVGTT)); | |
838 | ||
839 | for (i = 0; i < 4; i++) { | |
840 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
841 | i, I915_READ(GEN8_GT_IMR(i))); | |
842 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
843 | i, I915_READ(GEN8_GT_IIR(i))); | |
844 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
845 | i, I915_READ(GEN8_GT_IER(i))); | |
846 | } | |
847 | ||
848 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
849 | I915_READ(GEN8_PCU_IMR)); | |
850 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
851 | I915_READ(GEN8_PCU_IIR)); | |
852 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
853 | I915_READ(GEN8_PCU_IER)); | |
854 | } else if (INTEL_INFO(dev)->gen >= 8) { | |
a123f157 BW |
855 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
856 | I915_READ(GEN8_MASTER_IRQ)); | |
857 | ||
858 | for (i = 0; i < 4; i++) { | |
859 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
860 | i, I915_READ(GEN8_GT_IMR(i))); | |
861 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
862 | i, I915_READ(GEN8_GT_IIR(i))); | |
863 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
864 | i, I915_READ(GEN8_GT_IER(i))); | |
865 | } | |
866 | ||
055e393f | 867 | for_each_pipe(dev_priv, pipe) { |
e129649b ID |
868 | enum intel_display_power_domain power_domain; |
869 | ||
870 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
871 | if (!intel_display_power_get_if_enabled(dev_priv, | |
872 | power_domain)) { | |
22c59960 PZ |
873 | seq_printf(m, "Pipe %c power disabled\n", |
874 | pipe_name(pipe)); | |
875 | continue; | |
876 | } | |
a123f157 | 877 | seq_printf(m, "Pipe %c IMR:\t%08x\n", |
07d27e20 DL |
878 | pipe_name(pipe), |
879 | I915_READ(GEN8_DE_PIPE_IMR(pipe))); | |
a123f157 | 880 | seq_printf(m, "Pipe %c IIR:\t%08x\n", |
07d27e20 DL |
881 | pipe_name(pipe), |
882 | I915_READ(GEN8_DE_PIPE_IIR(pipe))); | |
a123f157 | 883 | seq_printf(m, "Pipe %c IER:\t%08x\n", |
07d27e20 DL |
884 | pipe_name(pipe), |
885 | I915_READ(GEN8_DE_PIPE_IER(pipe))); | |
e129649b ID |
886 | |
887 | intel_display_power_put(dev_priv, power_domain); | |
a123f157 BW |
888 | } |
889 | ||
890 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", | |
891 | I915_READ(GEN8_DE_PORT_IMR)); | |
892 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", | |
893 | I915_READ(GEN8_DE_PORT_IIR)); | |
894 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", | |
895 | I915_READ(GEN8_DE_PORT_IER)); | |
896 | ||
897 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", | |
898 | I915_READ(GEN8_DE_MISC_IMR)); | |
899 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", | |
900 | I915_READ(GEN8_DE_MISC_IIR)); | |
901 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", | |
902 | I915_READ(GEN8_DE_MISC_IER)); | |
903 | ||
904 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
905 | I915_READ(GEN8_PCU_IMR)); | |
906 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
907 | I915_READ(GEN8_PCU_IIR)); | |
908 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
909 | I915_READ(GEN8_PCU_IER)); | |
910 | } else if (IS_VALLEYVIEW(dev)) { | |
7e231dbe JB |
911 | seq_printf(m, "Display IER:\t%08x\n", |
912 | I915_READ(VLV_IER)); | |
913 | seq_printf(m, "Display IIR:\t%08x\n", | |
914 | I915_READ(VLV_IIR)); | |
915 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
916 | I915_READ(VLV_IIR_RW)); | |
917 | seq_printf(m, "Display IMR:\t%08x\n", | |
918 | I915_READ(VLV_IMR)); | |
055e393f | 919 | for_each_pipe(dev_priv, pipe) |
7e231dbe JB |
920 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
921 | pipe_name(pipe), | |
922 | I915_READ(PIPESTAT(pipe))); | |
923 | ||
924 | seq_printf(m, "Master IER:\t%08x\n", | |
925 | I915_READ(VLV_MASTER_IER)); | |
926 | ||
927 | seq_printf(m, "Render IER:\t%08x\n", | |
928 | I915_READ(GTIER)); | |
929 | seq_printf(m, "Render IIR:\t%08x\n", | |
930 | I915_READ(GTIIR)); | |
931 | seq_printf(m, "Render IMR:\t%08x\n", | |
932 | I915_READ(GTIMR)); | |
933 | ||
934 | seq_printf(m, "PM IER:\t\t%08x\n", | |
935 | I915_READ(GEN6_PMIER)); | |
936 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
937 | I915_READ(GEN6_PMIIR)); | |
938 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
939 | I915_READ(GEN6_PMIMR)); | |
940 | ||
941 | seq_printf(m, "Port hotplug:\t%08x\n", | |
942 | I915_READ(PORT_HOTPLUG_EN)); | |
943 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
944 | I915_READ(VLV_DPFLIPSTAT)); | |
945 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
946 | I915_READ(DPINVGTT)); | |
947 | ||
948 | } else if (!HAS_PCH_SPLIT(dev)) { | |
5f6a1695 ZW |
949 | seq_printf(m, "Interrupt enable: %08x\n", |
950 | I915_READ(IER)); | |
951 | seq_printf(m, "Interrupt identity: %08x\n", | |
952 | I915_READ(IIR)); | |
953 | seq_printf(m, "Interrupt mask: %08x\n", | |
954 | I915_READ(IMR)); | |
055e393f | 955 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
956 | seq_printf(m, "Pipe %c stat: %08x\n", |
957 | pipe_name(pipe), | |
958 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
959 | } else { |
960 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
961 | I915_READ(DEIER)); | |
962 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
963 | I915_READ(DEIIR)); | |
964 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
965 | I915_READ(DEIMR)); | |
966 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
967 | I915_READ(SDEIER)); | |
968 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
969 | I915_READ(SDEIIR)); | |
970 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
971 | I915_READ(SDEIMR)); | |
972 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
973 | I915_READ(GTIER)); | |
974 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
975 | I915_READ(GTIIR)); | |
976 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
977 | I915_READ(GTIMR)); | |
978 | } | |
b4ac5afc | 979 | for_each_engine(engine, dev_priv) { |
a123f157 | 980 | if (INTEL_INFO(dev)->gen >= 6) { |
a2c7f6fd CW |
981 | seq_printf(m, |
982 | "Graphics Interrupt mask (%s): %08x\n", | |
e2f80391 | 983 | engine->name, I915_READ_IMR(engine)); |
9862e600 | 984 | } |
e2f80391 | 985 | i915_ring_seqno_info(m, engine); |
9862e600 | 986 | } |
c8c8fb33 | 987 | intel_runtime_pm_put(dev_priv); |
de227ef0 CW |
988 | mutex_unlock(&dev->struct_mutex); |
989 | ||
2017263e BG |
990 | return 0; |
991 | } | |
992 | ||
a6172a80 CW |
993 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
994 | { | |
9f25d007 | 995 | struct drm_info_node *node = m->private; |
a6172a80 | 996 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 997 | struct drm_i915_private *dev_priv = dev->dev_private; |
de227ef0 CW |
998 | int i, ret; |
999 | ||
1000 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1001 | if (ret) | |
1002 | return ret; | |
a6172a80 | 1003 | |
a6172a80 CW |
1004 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); |
1005 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 1006 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 1007 | |
6c085a72 CW |
1008 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
1009 | i, dev_priv->fence_regs[i].pin_count); | |
c2c347a9 | 1010 | if (obj == NULL) |
267f0c90 | 1011 | seq_puts(m, "unused"); |
c2c347a9 | 1012 | else |
05394f39 | 1013 | describe_obj(m, obj); |
267f0c90 | 1014 | seq_putc(m, '\n'); |
a6172a80 CW |
1015 | } |
1016 | ||
05394f39 | 1017 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
1018 | return 0; |
1019 | } | |
1020 | ||
2017263e BG |
1021 | static int i915_hws_info(struct seq_file *m, void *data) |
1022 | { | |
9f25d007 | 1023 | struct drm_info_node *node = m->private; |
2017263e | 1024 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1025 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 1026 | struct intel_engine_cs *engine; |
1a240d4d | 1027 | const u32 *hws; |
4066c0ae CW |
1028 | int i; |
1029 | ||
4a570db5 | 1030 | engine = &dev_priv->engine[(uintptr_t)node->info_ent->data]; |
e2f80391 | 1031 | hws = engine->status_page.page_addr; |
2017263e BG |
1032 | if (hws == NULL) |
1033 | return 0; | |
1034 | ||
1035 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
1036 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
1037 | i * 4, | |
1038 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
1039 | } | |
1040 | return 0; | |
1041 | } | |
1042 | ||
d5442303 DV |
1043 | static ssize_t |
1044 | i915_error_state_write(struct file *filp, | |
1045 | const char __user *ubuf, | |
1046 | size_t cnt, | |
1047 | loff_t *ppos) | |
1048 | { | |
edc3d884 | 1049 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
d5442303 | 1050 | struct drm_device *dev = error_priv->dev; |
22bcfc6a | 1051 | int ret; |
d5442303 DV |
1052 | |
1053 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
1054 | ||
22bcfc6a DV |
1055 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1056 | if (ret) | |
1057 | return ret; | |
1058 | ||
d5442303 DV |
1059 | i915_destroy_error_state(dev); |
1060 | mutex_unlock(&dev->struct_mutex); | |
1061 | ||
1062 | return cnt; | |
1063 | } | |
1064 | ||
1065 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
1066 | { | |
1067 | struct drm_device *dev = inode->i_private; | |
d5442303 | 1068 | struct i915_error_state_file_priv *error_priv; |
d5442303 DV |
1069 | |
1070 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
1071 | if (!error_priv) | |
1072 | return -ENOMEM; | |
1073 | ||
1074 | error_priv->dev = dev; | |
1075 | ||
95d5bfb3 | 1076 | i915_error_state_get(dev, error_priv); |
d5442303 | 1077 | |
edc3d884 MK |
1078 | file->private_data = error_priv; |
1079 | ||
1080 | return 0; | |
d5442303 DV |
1081 | } |
1082 | ||
1083 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
1084 | { | |
edc3d884 | 1085 | struct i915_error_state_file_priv *error_priv = file->private_data; |
d5442303 | 1086 | |
95d5bfb3 | 1087 | i915_error_state_put(error_priv); |
d5442303 DV |
1088 | kfree(error_priv); |
1089 | ||
edc3d884 MK |
1090 | return 0; |
1091 | } | |
1092 | ||
4dc955f7 MK |
1093 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
1094 | size_t count, loff_t *pos) | |
1095 | { | |
1096 | struct i915_error_state_file_priv *error_priv = file->private_data; | |
1097 | struct drm_i915_error_state_buf error_str; | |
1098 | loff_t tmp_pos = 0; | |
1099 | ssize_t ret_count = 0; | |
1100 | int ret; | |
1101 | ||
0a4cd7c8 | 1102 | ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos); |
4dc955f7 MK |
1103 | if (ret) |
1104 | return ret; | |
edc3d884 | 1105 | |
fc16b48b | 1106 | ret = i915_error_state_to_str(&error_str, error_priv); |
edc3d884 MK |
1107 | if (ret) |
1108 | goto out; | |
1109 | ||
edc3d884 MK |
1110 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
1111 | error_str.buf, | |
1112 | error_str.bytes); | |
1113 | ||
1114 | if (ret_count < 0) | |
1115 | ret = ret_count; | |
1116 | else | |
1117 | *pos = error_str.start + ret_count; | |
1118 | out: | |
4dc955f7 | 1119 | i915_error_state_buf_release(&error_str); |
edc3d884 | 1120 | return ret ?: ret_count; |
d5442303 DV |
1121 | } |
1122 | ||
1123 | static const struct file_operations i915_error_state_fops = { | |
1124 | .owner = THIS_MODULE, | |
1125 | .open = i915_error_state_open, | |
edc3d884 | 1126 | .read = i915_error_state_read, |
d5442303 DV |
1127 | .write = i915_error_state_write, |
1128 | .llseek = default_llseek, | |
1129 | .release = i915_error_state_release, | |
1130 | }; | |
1131 | ||
647416f9 KC |
1132 | static int |
1133 | i915_next_seqno_get(void *data, u64 *val) | |
40633219 | 1134 | { |
647416f9 | 1135 | struct drm_device *dev = data; |
e277a1f8 | 1136 | struct drm_i915_private *dev_priv = dev->dev_private; |
40633219 MK |
1137 | int ret; |
1138 | ||
1139 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1140 | if (ret) | |
1141 | return ret; | |
1142 | ||
647416f9 | 1143 | *val = dev_priv->next_seqno; |
40633219 MK |
1144 | mutex_unlock(&dev->struct_mutex); |
1145 | ||
647416f9 | 1146 | return 0; |
40633219 MK |
1147 | } |
1148 | ||
647416f9 KC |
1149 | static int |
1150 | i915_next_seqno_set(void *data, u64 val) | |
1151 | { | |
1152 | struct drm_device *dev = data; | |
40633219 MK |
1153 | int ret; |
1154 | ||
40633219 MK |
1155 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1156 | if (ret) | |
1157 | return ret; | |
1158 | ||
e94fbaa8 | 1159 | ret = i915_gem_set_seqno(dev, val); |
40633219 MK |
1160 | mutex_unlock(&dev->struct_mutex); |
1161 | ||
647416f9 | 1162 | return ret; |
40633219 MK |
1163 | } |
1164 | ||
647416f9 KC |
1165 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
1166 | i915_next_seqno_get, i915_next_seqno_set, | |
3a3b4f98 | 1167 | "0x%llx\n"); |
40633219 | 1168 | |
adb4bd12 | 1169 | static int i915_frequency_info(struct seq_file *m, void *unused) |
f97108d1 | 1170 | { |
9f25d007 | 1171 | struct drm_info_node *node = m->private; |
f97108d1 | 1172 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1173 | struct drm_i915_private *dev_priv = dev->dev_private; |
c8c8fb33 PZ |
1174 | int ret = 0; |
1175 | ||
1176 | intel_runtime_pm_get(dev_priv); | |
3b8d8d91 | 1177 | |
5c9669ce TR |
1178 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
1179 | ||
3b8d8d91 JB |
1180 | if (IS_GEN5(dev)) { |
1181 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
1182 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
1183 | ||
1184 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
1185 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
1186 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
1187 | MEMSTAT_VID_SHIFT); | |
1188 | seq_printf(m, "Current P-state: %d\n", | |
1189 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
666a4537 WB |
1190 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
1191 | u32 freq_sts; | |
1192 | ||
1193 | mutex_lock(&dev_priv->rps.hw_lock); | |
1194 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); | |
1195 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); | |
1196 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
1197 | ||
1198 | seq_printf(m, "actual GPU freq: %d MHz\n", | |
1199 | intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); | |
1200 | ||
1201 | seq_printf(m, "current GPU freq: %d MHz\n", | |
1202 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1203 | ||
1204 | seq_printf(m, "max GPU freq: %d MHz\n", | |
1205 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1206 | ||
1207 | seq_printf(m, "min GPU freq: %d MHz\n", | |
1208 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
1209 | ||
1210 | seq_printf(m, "idle GPU freq: %d MHz\n", | |
1211 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
1212 | ||
1213 | seq_printf(m, | |
1214 | "efficient (RPe) frequency: %d MHz\n", | |
1215 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
1216 | mutex_unlock(&dev_priv->rps.hw_lock); | |
1217 | } else if (INTEL_INFO(dev)->gen >= 6) { | |
35040562 BP |
1218 | u32 rp_state_limits; |
1219 | u32 gt_perf_status; | |
1220 | u32 rp_state_cap; | |
0d8f9491 | 1221 | u32 rpmodectl, rpinclimit, rpdeclimit; |
8e8c06cd | 1222 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
1223 | u32 rpupei, rpcurup, rpprevup; |
1224 | u32 rpdownei, rpcurdown, rpprevdown; | |
9dd3c605 | 1225 | u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; |
3b8d8d91 JB |
1226 | int max_freq; |
1227 | ||
35040562 BP |
1228 | rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); |
1229 | if (IS_BROXTON(dev)) { | |
1230 | rp_state_cap = I915_READ(BXT_RP_STATE_CAP); | |
1231 | gt_perf_status = I915_READ(BXT_GT_PERF_STATUS); | |
1232 | } else { | |
1233 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
1234 | gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); | |
1235 | } | |
1236 | ||
3b8d8d91 | 1237 | /* RPSTAT1 is in the GT power well */ |
d1ebd816 BW |
1238 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1239 | if (ret) | |
c8c8fb33 | 1240 | goto out; |
d1ebd816 | 1241 | |
59bad947 | 1242 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
3b8d8d91 | 1243 | |
8e8c06cd | 1244 | reqf = I915_READ(GEN6_RPNSWREQ); |
60260a5b AG |
1245 | if (IS_GEN9(dev)) |
1246 | reqf >>= 23; | |
1247 | else { | |
1248 | reqf &= ~GEN6_TURBO_DISABLE; | |
1249 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
1250 | reqf >>= 24; | |
1251 | else | |
1252 | reqf >>= 25; | |
1253 | } | |
7c59a9c1 | 1254 | reqf = intel_gpu_freq(dev_priv, reqf); |
8e8c06cd | 1255 | |
0d8f9491 CW |
1256 | rpmodectl = I915_READ(GEN6_RP_CONTROL); |
1257 | rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); | |
1258 | rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); | |
1259 | ||
ccab5c82 | 1260 | rpstat = I915_READ(GEN6_RPSTAT1); |
d6cda9c7 AG |
1261 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; |
1262 | rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; | |
1263 | rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; | |
1264 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK; | |
1265 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK; | |
1266 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK; | |
60260a5b AG |
1267 | if (IS_GEN9(dev)) |
1268 | cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; | |
1269 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
f82855d3 BW |
1270 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
1271 | else | |
1272 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
7c59a9c1 | 1273 | cagf = intel_gpu_freq(dev_priv, cagf); |
ccab5c82 | 1274 | |
59bad947 | 1275 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
d1ebd816 BW |
1276 | mutex_unlock(&dev->struct_mutex); |
1277 | ||
9dd3c605 PZ |
1278 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1279 | pm_ier = I915_READ(GEN6_PMIER); | |
1280 | pm_imr = I915_READ(GEN6_PMIMR); | |
1281 | pm_isr = I915_READ(GEN6_PMISR); | |
1282 | pm_iir = I915_READ(GEN6_PMIIR); | |
1283 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1284 | } else { | |
1285 | pm_ier = I915_READ(GEN8_GT_IER(2)); | |
1286 | pm_imr = I915_READ(GEN8_GT_IMR(2)); | |
1287 | pm_isr = I915_READ(GEN8_GT_ISR(2)); | |
1288 | pm_iir = I915_READ(GEN8_GT_IIR(2)); | |
1289 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1290 | } | |
0d8f9491 | 1291 | seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", |
9dd3c605 | 1292 | pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); |
3b8d8d91 | 1293 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
3b8d8d91 | 1294 | seq_printf(m, "Render p-state ratio: %d\n", |
60260a5b | 1295 | (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8); |
3b8d8d91 JB |
1296 | seq_printf(m, "Render p-state VID: %d\n", |
1297 | gt_perf_status & 0xff); | |
1298 | seq_printf(m, "Render p-state limit: %d\n", | |
1299 | rp_state_limits & 0xff); | |
0d8f9491 CW |
1300 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
1301 | seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); | |
1302 | seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); | |
1303 | seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); | |
8e8c06cd | 1304 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 1305 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
d6cda9c7 AG |
1306 | seq_printf(m, "RP CUR UP EI: %d (%dus)\n", |
1307 | rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei)); | |
1308 | seq_printf(m, "RP CUR UP: %d (%dus)\n", | |
1309 | rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup)); | |
1310 | seq_printf(m, "RP PREV UP: %d (%dus)\n", | |
1311 | rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup)); | |
d86ed34a CW |
1312 | seq_printf(m, "Up threshold: %d%%\n", |
1313 | dev_priv->rps.up_threshold); | |
1314 | ||
d6cda9c7 AG |
1315 | seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n", |
1316 | rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei)); | |
1317 | seq_printf(m, "RP CUR DOWN: %d (%dus)\n", | |
1318 | rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown)); | |
1319 | seq_printf(m, "RP PREV DOWN: %d (%dus)\n", | |
1320 | rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown)); | |
d86ed34a CW |
1321 | seq_printf(m, "Down threshold: %d%%\n", |
1322 | dev_priv->rps.down_threshold); | |
3b8d8d91 | 1323 | |
35040562 BP |
1324 | max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 : |
1325 | rp_state_cap >> 16) & 0xff; | |
ef11bdb3 RV |
1326 | max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? |
1327 | GEN9_FREQ_SCALER : 1); | |
3b8d8d91 | 1328 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", |
7c59a9c1 | 1329 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 JB |
1330 | |
1331 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
ef11bdb3 RV |
1332 | max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? |
1333 | GEN9_FREQ_SCALER : 1); | |
3b8d8d91 | 1334 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", |
7c59a9c1 | 1335 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 | 1336 | |
35040562 BP |
1337 | max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 : |
1338 | rp_state_cap >> 0) & 0xff; | |
ef11bdb3 RV |
1339 | max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? |
1340 | GEN9_FREQ_SCALER : 1); | |
3b8d8d91 | 1341 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", |
7c59a9c1 | 1342 | intel_gpu_freq(dev_priv, max_freq)); |
31c77388 | 1343 | seq_printf(m, "Max overclocked frequency: %dMHz\n", |
7c59a9c1 | 1344 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); |
aed242ff | 1345 | |
d86ed34a CW |
1346 | seq_printf(m, "Current freq: %d MHz\n", |
1347 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1348 | seq_printf(m, "Actual freq: %d MHz\n", cagf); | |
aed242ff CW |
1349 | seq_printf(m, "Idle freq: %d MHz\n", |
1350 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
d86ed34a CW |
1351 | seq_printf(m, "Min freq: %d MHz\n", |
1352 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
1353 | seq_printf(m, "Max freq: %d MHz\n", | |
1354 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1355 | seq_printf(m, | |
1356 | "efficient (RPe) frequency: %d MHz\n", | |
1357 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
3b8d8d91 | 1358 | } else { |
267f0c90 | 1359 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 1360 | } |
f97108d1 | 1361 | |
1170f28c MK |
1362 | seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq); |
1363 | seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq); | |
1364 | seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq); | |
1365 | ||
c8c8fb33 PZ |
1366 | out: |
1367 | intel_runtime_pm_put(dev_priv); | |
1368 | return ret; | |
f97108d1 JB |
1369 | } |
1370 | ||
f654449a CW |
1371 | static int i915_hangcheck_info(struct seq_file *m, void *unused) |
1372 | { | |
1373 | struct drm_info_node *node = m->private; | |
ebbc7546 MK |
1374 | struct drm_device *dev = node->minor->dev; |
1375 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2f80391 | 1376 | struct intel_engine_cs *engine; |
666796da TU |
1377 | u64 acthd[I915_NUM_ENGINES]; |
1378 | u32 seqno[I915_NUM_ENGINES]; | |
61642ff0 | 1379 | u32 instdone[I915_NUM_INSTDONE_REG]; |
c3232b18 DG |
1380 | enum intel_engine_id id; |
1381 | int j; | |
f654449a CW |
1382 | |
1383 | if (!i915.enable_hangcheck) { | |
1384 | seq_printf(m, "Hangcheck disabled\n"); | |
1385 | return 0; | |
1386 | } | |
1387 | ||
ebbc7546 MK |
1388 | intel_runtime_pm_get(dev_priv); |
1389 | ||
c3232b18 | 1390 | for_each_engine_id(engine, dev_priv, id) { |
c3232b18 | 1391 | acthd[id] = intel_ring_get_active_head(engine); |
c04e0f3b | 1392 | seqno[id] = engine->get_seqno(engine); |
ebbc7546 MK |
1393 | } |
1394 | ||
c033666a | 1395 | i915_get_extra_instdone(dev_priv, instdone); |
61642ff0 | 1396 | |
ebbc7546 MK |
1397 | intel_runtime_pm_put(dev_priv); |
1398 | ||
f654449a CW |
1399 | if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) { |
1400 | seq_printf(m, "Hangcheck active, fires in %dms\n", | |
1401 | jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires - | |
1402 | jiffies)); | |
1403 | } else | |
1404 | seq_printf(m, "Hangcheck inactive\n"); | |
1405 | ||
c3232b18 | 1406 | for_each_engine_id(engine, dev_priv, id) { |
e2f80391 | 1407 | seq_printf(m, "%s:\n", engine->name); |
14fd0d6d CW |
1408 | seq_printf(m, "\tseqno = %x [current %x, last %x]\n", |
1409 | engine->hangcheck.seqno, | |
1410 | seqno[id], | |
1411 | engine->last_submitted_seqno); | |
12471ba8 CW |
1412 | seq_printf(m, "\tuser interrupts = %x [current %x]\n", |
1413 | engine->hangcheck.user_interrupts, | |
1414 | READ_ONCE(engine->user_interrupts)); | |
f654449a | 1415 | seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n", |
e2f80391 | 1416 | (long long)engine->hangcheck.acthd, |
c3232b18 | 1417 | (long long)acthd[id]); |
e2f80391 TU |
1418 | seq_printf(m, "\tscore = %d\n", engine->hangcheck.score); |
1419 | seq_printf(m, "\taction = %d\n", engine->hangcheck.action); | |
61642ff0 | 1420 | |
e2f80391 | 1421 | if (engine->id == RCS) { |
61642ff0 MK |
1422 | seq_puts(m, "\tinstdone read ="); |
1423 | ||
1424 | for (j = 0; j < I915_NUM_INSTDONE_REG; j++) | |
1425 | seq_printf(m, " 0x%08x", instdone[j]); | |
1426 | ||
1427 | seq_puts(m, "\n\tinstdone accu ="); | |
1428 | ||
1429 | for (j = 0; j < I915_NUM_INSTDONE_REG; j++) | |
1430 | seq_printf(m, " 0x%08x", | |
e2f80391 | 1431 | engine->hangcheck.instdone[j]); |
61642ff0 MK |
1432 | |
1433 | seq_puts(m, "\n"); | |
1434 | } | |
f654449a CW |
1435 | } |
1436 | ||
1437 | return 0; | |
1438 | } | |
1439 | ||
4d85529d | 1440 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 | 1441 | { |
9f25d007 | 1442 | struct drm_info_node *node = m->private; |
f97108d1 | 1443 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1444 | struct drm_i915_private *dev_priv = dev->dev_private; |
616fdb5a BW |
1445 | u32 rgvmodectl, rstdbyctl; |
1446 | u16 crstandvid; | |
1447 | int ret; | |
1448 | ||
1449 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1450 | if (ret) | |
1451 | return ret; | |
c8c8fb33 | 1452 | intel_runtime_pm_get(dev_priv); |
616fdb5a BW |
1453 | |
1454 | rgvmodectl = I915_READ(MEMMODECTL); | |
1455 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1456 | crstandvid = I915_READ16(CRSTANDVID); | |
1457 | ||
c8c8fb33 | 1458 | intel_runtime_pm_put(dev_priv); |
616fdb5a | 1459 | mutex_unlock(&dev->struct_mutex); |
f97108d1 | 1460 | |
742f491d | 1461 | seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN)); |
f97108d1 JB |
1462 | seq_printf(m, "Boost freq: %d\n", |
1463 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1464 | MEMMODE_BOOST_FREQ_SHIFT); | |
1465 | seq_printf(m, "HW control enabled: %s\n", | |
742f491d | 1466 | yesno(rgvmodectl & MEMMODE_HWIDLE_EN)); |
f97108d1 | 1467 | seq_printf(m, "SW control enabled: %s\n", |
742f491d | 1468 | yesno(rgvmodectl & MEMMODE_SWMODE_EN)); |
f97108d1 | 1469 | seq_printf(m, "Gated voltage change: %s\n", |
742f491d | 1470 | yesno(rgvmodectl & MEMMODE_RCLK_GATE)); |
f97108d1 JB |
1471 | seq_printf(m, "Starting frequency: P%d\n", |
1472 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1473 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1474 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1475 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1476 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1477 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1478 | seq_printf(m, "Render standby enabled: %s\n", | |
742f491d | 1479 | yesno(!(rstdbyctl & RCX_SW_EXIT))); |
267f0c90 | 1480 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1481 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1482 | case RSX_STATUS_ON: | |
267f0c90 | 1483 | seq_puts(m, "on\n"); |
88271da3 JB |
1484 | break; |
1485 | case RSX_STATUS_RC1: | |
267f0c90 | 1486 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1487 | break; |
1488 | case RSX_STATUS_RC1E: | |
267f0c90 | 1489 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1490 | break; |
1491 | case RSX_STATUS_RS1: | |
267f0c90 | 1492 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1493 | break; |
1494 | case RSX_STATUS_RS2: | |
267f0c90 | 1495 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1496 | break; |
1497 | case RSX_STATUS_RS3: | |
267f0c90 | 1498 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1499 | break; |
1500 | default: | |
267f0c90 | 1501 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1502 | break; |
1503 | } | |
f97108d1 JB |
1504 | |
1505 | return 0; | |
1506 | } | |
1507 | ||
f65367b5 | 1508 | static int i915_forcewake_domains(struct seq_file *m, void *data) |
669ab5aa | 1509 | { |
b2cff0db CW |
1510 | struct drm_info_node *node = m->private; |
1511 | struct drm_device *dev = node->minor->dev; | |
1512 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1513 | struct intel_uncore_forcewake_domain *fw_domain; | |
b2cff0db CW |
1514 | |
1515 | spin_lock_irq(&dev_priv->uncore.lock); | |
33c582c1 | 1516 | for_each_fw_domain(fw_domain, dev_priv) { |
b2cff0db | 1517 | seq_printf(m, "%s.wake_count = %u\n", |
33c582c1 | 1518 | intel_uncore_forcewake_domain_to_str(fw_domain->id), |
b2cff0db CW |
1519 | fw_domain->wake_count); |
1520 | } | |
1521 | spin_unlock_irq(&dev_priv->uncore.lock); | |
669ab5aa | 1522 | |
b2cff0db CW |
1523 | return 0; |
1524 | } | |
1525 | ||
1526 | static int vlv_drpc_info(struct seq_file *m) | |
1527 | { | |
9f25d007 | 1528 | struct drm_info_node *node = m->private; |
669ab5aa D |
1529 | struct drm_device *dev = node->minor->dev; |
1530 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6b312cd3 | 1531 | u32 rpmodectl1, rcctl1, pw_status; |
669ab5aa | 1532 | |
d46c0517 ID |
1533 | intel_runtime_pm_get(dev_priv); |
1534 | ||
6b312cd3 | 1535 | pw_status = I915_READ(VLV_GTLC_PW_STATUS); |
669ab5aa D |
1536 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
1537 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1538 | ||
d46c0517 ID |
1539 | intel_runtime_pm_put(dev_priv); |
1540 | ||
669ab5aa D |
1541 | seq_printf(m, "Video Turbo Mode: %s\n", |
1542 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1543 | seq_printf(m, "Turbo enabled: %s\n", | |
1544 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1545 | seq_printf(m, "HW control enabled: %s\n", | |
1546 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1547 | seq_printf(m, "SW control enabled: %s\n", | |
1548 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1549 | GEN6_RP_MEDIA_SW_MODE)); | |
1550 | seq_printf(m, "RC6 Enabled: %s\n", | |
1551 | yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | | |
1552 | GEN6_RC_CTL_EI_MODE(1)))); | |
1553 | seq_printf(m, "Render Power Well: %s\n", | |
6b312cd3 | 1554 | (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1555 | seq_printf(m, "Media Power Well: %s\n", |
6b312cd3 | 1556 | (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1557 | |
9cc19be5 ID |
1558 | seq_printf(m, "Render RC6 residency since boot: %u\n", |
1559 | I915_READ(VLV_GT_RENDER_RC6)); | |
1560 | seq_printf(m, "Media RC6 residency since boot: %u\n", | |
1561 | I915_READ(VLV_GT_MEDIA_RC6)); | |
1562 | ||
f65367b5 | 1563 | return i915_forcewake_domains(m, NULL); |
669ab5aa D |
1564 | } |
1565 | ||
4d85529d BW |
1566 | static int gen6_drpc_info(struct seq_file *m) |
1567 | { | |
9f25d007 | 1568 | struct drm_info_node *node = m->private; |
4d85529d BW |
1569 | struct drm_device *dev = node->minor->dev; |
1570 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ecd8faea | 1571 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
93b525dc | 1572 | unsigned forcewake_count; |
aee56cff | 1573 | int count = 0, ret; |
4d85529d BW |
1574 | |
1575 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1576 | if (ret) | |
1577 | return ret; | |
c8c8fb33 | 1578 | intel_runtime_pm_get(dev_priv); |
4d85529d | 1579 | |
907b28c5 | 1580 | spin_lock_irq(&dev_priv->uncore.lock); |
b2cff0db | 1581 | forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count; |
907b28c5 | 1582 | spin_unlock_irq(&dev_priv->uncore.lock); |
93b525dc DV |
1583 | |
1584 | if (forcewake_count) { | |
267f0c90 DL |
1585 | seq_puts(m, "RC information inaccurate because somebody " |
1586 | "holds a forcewake reference \n"); | |
4d85529d BW |
1587 | } else { |
1588 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1589 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1590 | udelay(10); | |
1591 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1592 | } | |
1593 | ||
75aa3f63 | 1594 | gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS); |
ed71f1b4 | 1595 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1596 | |
1597 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1598 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1599 | mutex_unlock(&dev->struct_mutex); | |
44cbd338 BW |
1600 | mutex_lock(&dev_priv->rps.hw_lock); |
1601 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1602 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d | 1603 | |
c8c8fb33 PZ |
1604 | intel_runtime_pm_put(dev_priv); |
1605 | ||
4d85529d BW |
1606 | seq_printf(m, "Video Turbo Mode: %s\n", |
1607 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1608 | seq_printf(m, "HW control enabled: %s\n", | |
1609 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1610 | seq_printf(m, "SW control enabled: %s\n", | |
1611 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1612 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1613 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1614 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1615 | seq_printf(m, "RC6 Enabled: %s\n", | |
1616 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
1617 | seq_printf(m, "Deep RC6 Enabled: %s\n", | |
1618 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1619 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1620 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1621 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1622 | switch (gt_core_status & GEN6_RCn_MASK) { |
1623 | case GEN6_RC0: | |
1624 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1625 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1626 | else |
267f0c90 | 1627 | seq_puts(m, "on\n"); |
4d85529d BW |
1628 | break; |
1629 | case GEN6_RC3: | |
267f0c90 | 1630 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1631 | break; |
1632 | case GEN6_RC6: | |
267f0c90 | 1633 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1634 | break; |
1635 | case GEN6_RC7: | |
267f0c90 | 1636 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1637 | break; |
1638 | default: | |
267f0c90 | 1639 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1640 | break; |
1641 | } | |
1642 | ||
1643 | seq_printf(m, "Core Power Down: %s\n", | |
1644 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
cce66a28 BW |
1645 | |
1646 | /* Not exactly sure what this is */ | |
1647 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1648 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1649 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1650 | I915_READ(GEN6_GT_GFX_RC6)); | |
1651 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1652 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1653 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1654 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1655 | ||
ecd8faea BW |
1656 | seq_printf(m, "RC6 voltage: %dmV\n", |
1657 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1658 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1659 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1660 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1661 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
4d85529d BW |
1662 | return 0; |
1663 | } | |
1664 | ||
1665 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1666 | { | |
9f25d007 | 1667 | struct drm_info_node *node = m->private; |
4d85529d BW |
1668 | struct drm_device *dev = node->minor->dev; |
1669 | ||
666a4537 | 1670 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
669ab5aa | 1671 | return vlv_drpc_info(m); |
ac66cf4b | 1672 | else if (INTEL_INFO(dev)->gen >= 6) |
4d85529d BW |
1673 | return gen6_drpc_info(m); |
1674 | else | |
1675 | return ironlake_drpc_info(m); | |
1676 | } | |
1677 | ||
9a851789 DV |
1678 | static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) |
1679 | { | |
1680 | struct drm_info_node *node = m->private; | |
1681 | struct drm_device *dev = node->minor->dev; | |
1682 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1683 | ||
1684 | seq_printf(m, "FB tracking busy bits: 0x%08x\n", | |
1685 | dev_priv->fb_tracking.busy_bits); | |
1686 | ||
1687 | seq_printf(m, "FB tracking flip bits: 0x%08x\n", | |
1688 | dev_priv->fb_tracking.flip_bits); | |
1689 | ||
1690 | return 0; | |
1691 | } | |
1692 | ||
b5e50c3f JB |
1693 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1694 | { | |
9f25d007 | 1695 | struct drm_info_node *node = m->private; |
b5e50c3f | 1696 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1697 | struct drm_i915_private *dev_priv = dev->dev_private; |
b5e50c3f | 1698 | |
3a77c4c4 | 1699 | if (!HAS_FBC(dev)) { |
267f0c90 | 1700 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1701 | return 0; |
1702 | } | |
1703 | ||
36623ef8 | 1704 | intel_runtime_pm_get(dev_priv); |
25ad93fd | 1705 | mutex_lock(&dev_priv->fbc.lock); |
36623ef8 | 1706 | |
0e631adc | 1707 | if (intel_fbc_is_active(dev_priv)) |
267f0c90 | 1708 | seq_puts(m, "FBC enabled\n"); |
2e8144a5 PZ |
1709 | else |
1710 | seq_printf(m, "FBC disabled: %s\n", | |
bf6189c6 | 1711 | dev_priv->fbc.no_fbc_reason); |
36623ef8 | 1712 | |
31b9df10 PZ |
1713 | if (INTEL_INFO(dev_priv)->gen >= 7) |
1714 | seq_printf(m, "Compressing: %s\n", | |
1715 | yesno(I915_READ(FBC_STATUS2) & | |
1716 | FBC_COMPRESSION_MASK)); | |
1717 | ||
25ad93fd | 1718 | mutex_unlock(&dev_priv->fbc.lock); |
36623ef8 PZ |
1719 | intel_runtime_pm_put(dev_priv); |
1720 | ||
b5e50c3f JB |
1721 | return 0; |
1722 | } | |
1723 | ||
da46f936 RV |
1724 | static int i915_fbc_fc_get(void *data, u64 *val) |
1725 | { | |
1726 | struct drm_device *dev = data; | |
1727 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1728 | ||
1729 | if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) | |
1730 | return -ENODEV; | |
1731 | ||
da46f936 | 1732 | *val = dev_priv->fbc.false_color; |
da46f936 RV |
1733 | |
1734 | return 0; | |
1735 | } | |
1736 | ||
1737 | static int i915_fbc_fc_set(void *data, u64 val) | |
1738 | { | |
1739 | struct drm_device *dev = data; | |
1740 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1741 | u32 reg; | |
1742 | ||
1743 | if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) | |
1744 | return -ENODEV; | |
1745 | ||
25ad93fd | 1746 | mutex_lock(&dev_priv->fbc.lock); |
da46f936 RV |
1747 | |
1748 | reg = I915_READ(ILK_DPFC_CONTROL); | |
1749 | dev_priv->fbc.false_color = val; | |
1750 | ||
1751 | I915_WRITE(ILK_DPFC_CONTROL, val ? | |
1752 | (reg | FBC_CTL_FALSE_COLOR) : | |
1753 | (reg & ~FBC_CTL_FALSE_COLOR)); | |
1754 | ||
25ad93fd | 1755 | mutex_unlock(&dev_priv->fbc.lock); |
da46f936 RV |
1756 | return 0; |
1757 | } | |
1758 | ||
1759 | DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops, | |
1760 | i915_fbc_fc_get, i915_fbc_fc_set, | |
1761 | "%llu\n"); | |
1762 | ||
92d44621 PZ |
1763 | static int i915_ips_status(struct seq_file *m, void *unused) |
1764 | { | |
9f25d007 | 1765 | struct drm_info_node *node = m->private; |
92d44621 PZ |
1766 | struct drm_device *dev = node->minor->dev; |
1767 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1768 | ||
f5adf94e | 1769 | if (!HAS_IPS(dev)) { |
92d44621 PZ |
1770 | seq_puts(m, "not supported\n"); |
1771 | return 0; | |
1772 | } | |
1773 | ||
36623ef8 PZ |
1774 | intel_runtime_pm_get(dev_priv); |
1775 | ||
0eaa53f0 RV |
1776 | seq_printf(m, "Enabled by kernel parameter: %s\n", |
1777 | yesno(i915.enable_ips)); | |
1778 | ||
1779 | if (INTEL_INFO(dev)->gen >= 8) { | |
1780 | seq_puts(m, "Currently: unknown\n"); | |
1781 | } else { | |
1782 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1783 | seq_puts(m, "Currently: enabled\n"); | |
1784 | else | |
1785 | seq_puts(m, "Currently: disabled\n"); | |
1786 | } | |
92d44621 | 1787 | |
36623ef8 PZ |
1788 | intel_runtime_pm_put(dev_priv); |
1789 | ||
92d44621 PZ |
1790 | return 0; |
1791 | } | |
1792 | ||
4a9bef37 JB |
1793 | static int i915_sr_status(struct seq_file *m, void *unused) |
1794 | { | |
9f25d007 | 1795 | struct drm_info_node *node = m->private; |
4a9bef37 | 1796 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1797 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a9bef37 JB |
1798 | bool sr_enabled = false; |
1799 | ||
36623ef8 PZ |
1800 | intel_runtime_pm_get(dev_priv); |
1801 | ||
1398261a | 1802 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1803 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
77b64555 ACO |
1804 | else if (IS_CRESTLINE(dev) || IS_G4X(dev) || |
1805 | IS_I945G(dev) || IS_I945GM(dev)) | |
4a9bef37 JB |
1806 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1807 | else if (IS_I915GM(dev)) | |
1808 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1809 | else if (IS_PINEVIEW(dev)) | |
1810 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
666a4537 | 1811 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
77b64555 | 1812 | sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; |
4a9bef37 | 1813 | |
36623ef8 PZ |
1814 | intel_runtime_pm_put(dev_priv); |
1815 | ||
5ba2aaaa CW |
1816 | seq_printf(m, "self-refresh: %s\n", |
1817 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1818 | |
1819 | return 0; | |
1820 | } | |
1821 | ||
7648fa99 JB |
1822 | static int i915_emon_status(struct seq_file *m, void *unused) |
1823 | { | |
9f25d007 | 1824 | struct drm_info_node *node = m->private; |
7648fa99 | 1825 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1826 | struct drm_i915_private *dev_priv = dev->dev_private; |
7648fa99 | 1827 | unsigned long temp, chipset, gfx; |
de227ef0 CW |
1828 | int ret; |
1829 | ||
582be6b4 CW |
1830 | if (!IS_GEN5(dev)) |
1831 | return -ENODEV; | |
1832 | ||
de227ef0 CW |
1833 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1834 | if (ret) | |
1835 | return ret; | |
7648fa99 JB |
1836 | |
1837 | temp = i915_mch_val(dev_priv); | |
1838 | chipset = i915_chipset_val(dev_priv); | |
1839 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1840 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1841 | |
1842 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1843 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1844 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1845 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1846 | ||
1847 | return 0; | |
1848 | } | |
1849 | ||
23b2f8bb JB |
1850 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1851 | { | |
9f25d007 | 1852 | struct drm_info_node *node = m->private; |
23b2f8bb | 1853 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1854 | struct drm_i915_private *dev_priv = dev->dev_private; |
5bfa0199 | 1855 | int ret = 0; |
23b2f8bb | 1856 | int gpu_freq, ia_freq; |
f936ec34 | 1857 | unsigned int max_gpu_freq, min_gpu_freq; |
23b2f8bb | 1858 | |
97d3308a | 1859 | if (!HAS_CORE_RING_FREQ(dev)) { |
267f0c90 | 1860 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1861 | return 0; |
1862 | } | |
1863 | ||
5bfa0199 PZ |
1864 | intel_runtime_pm_get(dev_priv); |
1865 | ||
5c9669ce TR |
1866 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
1867 | ||
4fc688ce | 1868 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb | 1869 | if (ret) |
5bfa0199 | 1870 | goto out; |
23b2f8bb | 1871 | |
ef11bdb3 | 1872 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
f936ec34 AG |
1873 | /* Convert GT frequency to 50 HZ units */ |
1874 | min_gpu_freq = | |
1875 | dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER; | |
1876 | max_gpu_freq = | |
1877 | dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER; | |
1878 | } else { | |
1879 | min_gpu_freq = dev_priv->rps.min_freq_softlimit; | |
1880 | max_gpu_freq = dev_priv->rps.max_freq_softlimit; | |
1881 | } | |
1882 | ||
267f0c90 | 1883 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1884 | |
f936ec34 | 1885 | for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) { |
42c0526c BW |
1886 | ia_freq = gpu_freq; |
1887 | sandybridge_pcode_read(dev_priv, | |
1888 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1889 | &ia_freq); | |
3ebecd07 | 1890 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
f936ec34 | 1891 | intel_gpu_freq(dev_priv, (gpu_freq * |
ef11bdb3 RV |
1892 | (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? |
1893 | GEN9_FREQ_SCALER : 1))), | |
3ebecd07 CW |
1894 | ((ia_freq >> 0) & 0xff) * 100, |
1895 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1896 | } |
1897 | ||
4fc688ce | 1898 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb | 1899 | |
5bfa0199 PZ |
1900 | out: |
1901 | intel_runtime_pm_put(dev_priv); | |
1902 | return ret; | |
23b2f8bb JB |
1903 | } |
1904 | ||
44834a67 CW |
1905 | static int i915_opregion(struct seq_file *m, void *unused) |
1906 | { | |
9f25d007 | 1907 | struct drm_info_node *node = m->private; |
44834a67 | 1908 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1909 | struct drm_i915_private *dev_priv = dev->dev_private; |
44834a67 CW |
1910 | struct intel_opregion *opregion = &dev_priv->opregion; |
1911 | int ret; | |
1912 | ||
1913 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1914 | if (ret) | |
0d38f009 | 1915 | goto out; |
44834a67 | 1916 | |
2455a8e4 JN |
1917 | if (opregion->header) |
1918 | seq_write(m, opregion->header, OPREGION_SIZE); | |
44834a67 CW |
1919 | |
1920 | mutex_unlock(&dev->struct_mutex); | |
1921 | ||
0d38f009 | 1922 | out: |
44834a67 CW |
1923 | return 0; |
1924 | } | |
1925 | ||
ada8f955 JN |
1926 | static int i915_vbt(struct seq_file *m, void *unused) |
1927 | { | |
1928 | struct drm_info_node *node = m->private; | |
1929 | struct drm_device *dev = node->minor->dev; | |
1930 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1931 | struct intel_opregion *opregion = &dev_priv->opregion; | |
1932 | ||
1933 | if (opregion->vbt) | |
1934 | seq_write(m, opregion->vbt, opregion->vbt_size); | |
1935 | ||
1936 | return 0; | |
1937 | } | |
1938 | ||
37811fcc CW |
1939 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1940 | { | |
9f25d007 | 1941 | struct drm_info_node *node = m->private; |
37811fcc | 1942 | struct drm_device *dev = node->minor->dev; |
b13b8402 | 1943 | struct intel_framebuffer *fbdev_fb = NULL; |
3a58ee10 | 1944 | struct drm_framebuffer *drm_fb; |
188c1ab7 CW |
1945 | int ret; |
1946 | ||
1947 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1948 | if (ret) | |
1949 | return ret; | |
37811fcc | 1950 | |
0695726e | 1951 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
b13b8402 NS |
1952 | if (to_i915(dev)->fbdev) { |
1953 | fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb); | |
1954 | ||
1955 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", | |
1956 | fbdev_fb->base.width, | |
1957 | fbdev_fb->base.height, | |
1958 | fbdev_fb->base.depth, | |
1959 | fbdev_fb->base.bits_per_pixel, | |
1960 | fbdev_fb->base.modifier[0], | |
747a598f | 1961 | drm_framebuffer_read_refcount(&fbdev_fb->base)); |
b13b8402 NS |
1962 | describe_obj(m, fbdev_fb->obj); |
1963 | seq_putc(m, '\n'); | |
1964 | } | |
4520f53a | 1965 | #endif |
37811fcc | 1966 | |
4b096ac1 | 1967 | mutex_lock(&dev->mode_config.fb_lock); |
3a58ee10 | 1968 | drm_for_each_fb(drm_fb, dev) { |
b13b8402 NS |
1969 | struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); |
1970 | if (fb == fbdev_fb) | |
37811fcc CW |
1971 | continue; |
1972 | ||
c1ca506d | 1973 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", |
37811fcc CW |
1974 | fb->base.width, |
1975 | fb->base.height, | |
1976 | fb->base.depth, | |
623f9783 | 1977 | fb->base.bits_per_pixel, |
c1ca506d | 1978 | fb->base.modifier[0], |
747a598f | 1979 | drm_framebuffer_read_refcount(&fb->base)); |
05394f39 | 1980 | describe_obj(m, fb->obj); |
267f0c90 | 1981 | seq_putc(m, '\n'); |
37811fcc | 1982 | } |
4b096ac1 | 1983 | mutex_unlock(&dev->mode_config.fb_lock); |
188c1ab7 | 1984 | mutex_unlock(&dev->struct_mutex); |
37811fcc CW |
1985 | |
1986 | return 0; | |
1987 | } | |
1988 | ||
c9fe99bd OM |
1989 | static void describe_ctx_ringbuf(struct seq_file *m, |
1990 | struct intel_ringbuffer *ringbuf) | |
1991 | { | |
1992 | seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)", | |
1993 | ringbuf->space, ringbuf->head, ringbuf->tail, | |
1994 | ringbuf->last_retired_head); | |
1995 | } | |
1996 | ||
e76d3630 BW |
1997 | static int i915_context_status(struct seq_file *m, void *unused) |
1998 | { | |
9f25d007 | 1999 | struct drm_info_node *node = m->private; |
e76d3630 | 2000 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 2001 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 2002 | struct intel_engine_cs *engine; |
273497e5 | 2003 | struct intel_context *ctx; |
c3232b18 DG |
2004 | enum intel_engine_id id; |
2005 | int ret; | |
e76d3630 | 2006 | |
f3d28878 | 2007 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
e76d3630 BW |
2008 | if (ret) |
2009 | return ret; | |
2010 | ||
a33afea5 | 2011 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
c9fe99bd OM |
2012 | if (!i915.enable_execlists && |
2013 | ctx->legacy_hw_ctx.rcs_state == NULL) | |
b77f6997 CW |
2014 | continue; |
2015 | ||
5d1808ec | 2016 | seq_printf(m, "HW context %u ", ctx->hw_id); |
3ccfd19d | 2017 | describe_ctx(m, ctx); |
e28e404c DG |
2018 | if (ctx == dev_priv->kernel_context) |
2019 | seq_printf(m, "(kernel context) "); | |
c9fe99bd OM |
2020 | |
2021 | if (i915.enable_execlists) { | |
2022 | seq_putc(m, '\n'); | |
c3232b18 | 2023 | for_each_engine_id(engine, dev_priv, id) { |
c9fe99bd | 2024 | struct drm_i915_gem_object *ctx_obj = |
c3232b18 | 2025 | ctx->engine[id].state; |
c9fe99bd | 2026 | struct intel_ringbuffer *ringbuf = |
c3232b18 | 2027 | ctx->engine[id].ringbuf; |
c9fe99bd | 2028 | |
e2f80391 | 2029 | seq_printf(m, "%s: ", engine->name); |
c9fe99bd OM |
2030 | if (ctx_obj) |
2031 | describe_obj(m, ctx_obj); | |
2032 | if (ringbuf) | |
2033 | describe_ctx_ringbuf(m, ringbuf); | |
2034 | seq_putc(m, '\n'); | |
2035 | } | |
2036 | } else { | |
2037 | describe_obj(m, ctx->legacy_hw_ctx.rcs_state); | |
2038 | } | |
a33afea5 | 2039 | |
a33afea5 | 2040 | seq_putc(m, '\n'); |
a168c293 BW |
2041 | } |
2042 | ||
f3d28878 | 2043 | mutex_unlock(&dev->struct_mutex); |
e76d3630 BW |
2044 | |
2045 | return 0; | |
2046 | } | |
2047 | ||
064ca1d2 | 2048 | static void i915_dump_lrc_obj(struct seq_file *m, |
ca82580c | 2049 | struct intel_context *ctx, |
0bc40be8 | 2050 | struct intel_engine_cs *engine) |
064ca1d2 TD |
2051 | { |
2052 | struct page *page; | |
2053 | uint32_t *reg_state; | |
2054 | int j; | |
0bc40be8 | 2055 | struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state; |
064ca1d2 TD |
2056 | unsigned long ggtt_offset = 0; |
2057 | ||
7069b144 CW |
2058 | seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id); |
2059 | ||
064ca1d2 | 2060 | if (ctx_obj == NULL) { |
7069b144 | 2061 | seq_puts(m, "\tNot allocated\n"); |
064ca1d2 TD |
2062 | return; |
2063 | } | |
2064 | ||
064ca1d2 TD |
2065 | if (!i915_gem_obj_ggtt_bound(ctx_obj)) |
2066 | seq_puts(m, "\tNot bound in GGTT\n"); | |
2067 | else | |
2068 | ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj); | |
2069 | ||
2070 | if (i915_gem_object_get_pages(ctx_obj)) { | |
2071 | seq_puts(m, "\tFailed to get pages for context object\n"); | |
2072 | return; | |
2073 | } | |
2074 | ||
d1675198 | 2075 | page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN); |
064ca1d2 TD |
2076 | if (!WARN_ON(page == NULL)) { |
2077 | reg_state = kmap_atomic(page); | |
2078 | ||
2079 | for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) { | |
2080 | seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2081 | ggtt_offset + 4096 + (j * 4), | |
2082 | reg_state[j], reg_state[j + 1], | |
2083 | reg_state[j + 2], reg_state[j + 3]); | |
2084 | } | |
2085 | kunmap_atomic(reg_state); | |
2086 | } | |
2087 | ||
2088 | seq_putc(m, '\n'); | |
2089 | } | |
2090 | ||
c0ab1ae9 BW |
2091 | static int i915_dump_lrc(struct seq_file *m, void *unused) |
2092 | { | |
2093 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2094 | struct drm_device *dev = node->minor->dev; | |
2095 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2f80391 | 2096 | struct intel_engine_cs *engine; |
c0ab1ae9 | 2097 | struct intel_context *ctx; |
b4ac5afc | 2098 | int ret; |
c0ab1ae9 BW |
2099 | |
2100 | if (!i915.enable_execlists) { | |
2101 | seq_printf(m, "Logical Ring Contexts are disabled\n"); | |
2102 | return 0; | |
2103 | } | |
2104 | ||
2105 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2106 | if (ret) | |
2107 | return ret; | |
2108 | ||
e28e404c | 2109 | list_for_each_entry(ctx, &dev_priv->context_list, link) |
24f1d3cc CW |
2110 | for_each_engine(engine, dev_priv) |
2111 | i915_dump_lrc_obj(m, ctx, engine); | |
c0ab1ae9 BW |
2112 | |
2113 | mutex_unlock(&dev->struct_mutex); | |
2114 | ||
2115 | return 0; | |
2116 | } | |
2117 | ||
4ba70e44 OM |
2118 | static int i915_execlists(struct seq_file *m, void *data) |
2119 | { | |
2120 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
2121 | struct drm_device *dev = node->minor->dev; | |
2122 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2f80391 | 2123 | struct intel_engine_cs *engine; |
4ba70e44 OM |
2124 | u32 status_pointer; |
2125 | u8 read_pointer; | |
2126 | u8 write_pointer; | |
2127 | u32 status; | |
2128 | u32 ctx_id; | |
2129 | struct list_head *cursor; | |
b4ac5afc | 2130 | int i, ret; |
4ba70e44 OM |
2131 | |
2132 | if (!i915.enable_execlists) { | |
2133 | seq_puts(m, "Logical Ring Contexts are disabled\n"); | |
2134 | return 0; | |
2135 | } | |
2136 | ||
2137 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2138 | if (ret) | |
2139 | return ret; | |
2140 | ||
fc0412ec MT |
2141 | intel_runtime_pm_get(dev_priv); |
2142 | ||
b4ac5afc | 2143 | for_each_engine(engine, dev_priv) { |
6d3d8274 | 2144 | struct drm_i915_gem_request *head_req = NULL; |
4ba70e44 | 2145 | int count = 0; |
4ba70e44 | 2146 | |
e2f80391 | 2147 | seq_printf(m, "%s\n", engine->name); |
4ba70e44 | 2148 | |
e2f80391 TU |
2149 | status = I915_READ(RING_EXECLIST_STATUS_LO(engine)); |
2150 | ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine)); | |
4ba70e44 OM |
2151 | seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n", |
2152 | status, ctx_id); | |
2153 | ||
e2f80391 | 2154 | status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine)); |
4ba70e44 OM |
2155 | seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer); |
2156 | ||
e2f80391 | 2157 | read_pointer = engine->next_context_status_buffer; |
5590a5f0 | 2158 | write_pointer = GEN8_CSB_WRITE_PTR(status_pointer); |
4ba70e44 | 2159 | if (read_pointer > write_pointer) |
5590a5f0 | 2160 | write_pointer += GEN8_CSB_ENTRIES; |
4ba70e44 OM |
2161 | seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n", |
2162 | read_pointer, write_pointer); | |
2163 | ||
5590a5f0 | 2164 | for (i = 0; i < GEN8_CSB_ENTRIES; i++) { |
e2f80391 TU |
2165 | status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i)); |
2166 | ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i)); | |
4ba70e44 OM |
2167 | |
2168 | seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n", | |
2169 | i, status, ctx_id); | |
2170 | } | |
2171 | ||
27af5eea | 2172 | spin_lock_bh(&engine->execlist_lock); |
e2f80391 | 2173 | list_for_each(cursor, &engine->execlist_queue) |
4ba70e44 | 2174 | count++; |
e2f80391 TU |
2175 | head_req = list_first_entry_or_null(&engine->execlist_queue, |
2176 | struct drm_i915_gem_request, | |
2177 | execlist_link); | |
27af5eea | 2178 | spin_unlock_bh(&engine->execlist_lock); |
4ba70e44 OM |
2179 | |
2180 | seq_printf(m, "\t%d requests in queue\n", count); | |
2181 | if (head_req) { | |
7069b144 CW |
2182 | seq_printf(m, "\tHead request context: %u\n", |
2183 | head_req->ctx->hw_id); | |
4ba70e44 | 2184 | seq_printf(m, "\tHead request tail: %u\n", |
6d3d8274 | 2185 | head_req->tail); |
4ba70e44 OM |
2186 | } |
2187 | ||
2188 | seq_putc(m, '\n'); | |
2189 | } | |
2190 | ||
fc0412ec | 2191 | intel_runtime_pm_put(dev_priv); |
4ba70e44 OM |
2192 | mutex_unlock(&dev->struct_mutex); |
2193 | ||
2194 | return 0; | |
2195 | } | |
2196 | ||
ea16a3cd DV |
2197 | static const char *swizzle_string(unsigned swizzle) |
2198 | { | |
aee56cff | 2199 | switch (swizzle) { |
ea16a3cd DV |
2200 | case I915_BIT_6_SWIZZLE_NONE: |
2201 | return "none"; | |
2202 | case I915_BIT_6_SWIZZLE_9: | |
2203 | return "bit9"; | |
2204 | case I915_BIT_6_SWIZZLE_9_10: | |
2205 | return "bit9/bit10"; | |
2206 | case I915_BIT_6_SWIZZLE_9_11: | |
2207 | return "bit9/bit11"; | |
2208 | case I915_BIT_6_SWIZZLE_9_10_11: | |
2209 | return "bit9/bit10/bit11"; | |
2210 | case I915_BIT_6_SWIZZLE_9_17: | |
2211 | return "bit9/bit17"; | |
2212 | case I915_BIT_6_SWIZZLE_9_10_17: | |
2213 | return "bit9/bit10/bit17"; | |
2214 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 2215 | return "unknown"; |
ea16a3cd DV |
2216 | } |
2217 | ||
2218 | return "bug"; | |
2219 | } | |
2220 | ||
2221 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
2222 | { | |
9f25d007 | 2223 | struct drm_info_node *node = m->private; |
ea16a3cd DV |
2224 | struct drm_device *dev = node->minor->dev; |
2225 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22bcfc6a DV |
2226 | int ret; |
2227 | ||
2228 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2229 | if (ret) | |
2230 | return ret; | |
c8c8fb33 | 2231 | intel_runtime_pm_get(dev_priv); |
ea16a3cd | 2232 | |
ea16a3cd DV |
2233 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
2234 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
2235 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
2236 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
2237 | ||
2238 | if (IS_GEN3(dev) || IS_GEN4(dev)) { | |
2239 | seq_printf(m, "DDC = 0x%08x\n", | |
2240 | I915_READ(DCC)); | |
656bfa3a DV |
2241 | seq_printf(m, "DDC2 = 0x%08x\n", |
2242 | I915_READ(DCC2)); | |
ea16a3cd DV |
2243 | seq_printf(m, "C0DRB3 = 0x%04x\n", |
2244 | I915_READ16(C0DRB3)); | |
2245 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
2246 | I915_READ16(C1DRB3)); | |
9d3203e1 | 2247 | } else if (INTEL_INFO(dev)->gen >= 6) { |
3fa7d235 DV |
2248 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
2249 | I915_READ(MAD_DIMM_C0)); | |
2250 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
2251 | I915_READ(MAD_DIMM_C1)); | |
2252 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
2253 | I915_READ(MAD_DIMM_C2)); | |
2254 | seq_printf(m, "TILECTL = 0x%08x\n", | |
2255 | I915_READ(TILECTL)); | |
5907f5fb | 2256 | if (INTEL_INFO(dev)->gen >= 8) |
9d3203e1 BW |
2257 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", |
2258 | I915_READ(GAMTARBMODE)); | |
2259 | else | |
2260 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
2261 | I915_READ(ARB_MODE)); | |
3fa7d235 DV |
2262 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
2263 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd | 2264 | } |
656bfa3a DV |
2265 | |
2266 | if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2267 | seq_puts(m, "L-shaped memory detected\n"); | |
2268 | ||
c8c8fb33 | 2269 | intel_runtime_pm_put(dev_priv); |
ea16a3cd DV |
2270 | mutex_unlock(&dev->struct_mutex); |
2271 | ||
2272 | return 0; | |
2273 | } | |
2274 | ||
1c60fef5 BW |
2275 | static int per_file_ctx(int id, void *ptr, void *data) |
2276 | { | |
273497e5 | 2277 | struct intel_context *ctx = ptr; |
1c60fef5 | 2278 | struct seq_file *m = data; |
ae6c4806 DV |
2279 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
2280 | ||
2281 | if (!ppgtt) { | |
2282 | seq_printf(m, " no ppgtt for context %d\n", | |
2283 | ctx->user_handle); | |
2284 | return 0; | |
2285 | } | |
1c60fef5 | 2286 | |
f83d6518 OM |
2287 | if (i915_gem_context_is_default(ctx)) |
2288 | seq_puts(m, " default context:\n"); | |
2289 | else | |
821d66dd | 2290 | seq_printf(m, " context %d:\n", ctx->user_handle); |
1c60fef5 BW |
2291 | ppgtt->debug_dump(ppgtt, m); |
2292 | ||
2293 | return 0; | |
2294 | } | |
2295 | ||
77df6772 | 2296 | static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev) |
3cf17fc5 | 2297 | { |
3cf17fc5 | 2298 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 2299 | struct intel_engine_cs *engine; |
77df6772 | 2300 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
b4ac5afc | 2301 | int i; |
3cf17fc5 | 2302 | |
77df6772 BW |
2303 | if (!ppgtt) |
2304 | return; | |
2305 | ||
b4ac5afc | 2306 | for_each_engine(engine, dev_priv) { |
e2f80391 | 2307 | seq_printf(m, "%s\n", engine->name); |
77df6772 | 2308 | for (i = 0; i < 4; i++) { |
e2f80391 | 2309 | u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i)); |
77df6772 | 2310 | pdp <<= 32; |
e2f80391 | 2311 | pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i)); |
a2a5b15c | 2312 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); |
77df6772 BW |
2313 | } |
2314 | } | |
2315 | } | |
2316 | ||
2317 | static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev) | |
2318 | { | |
2319 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2f80391 | 2320 | struct intel_engine_cs *engine; |
3cf17fc5 | 2321 | |
7e22dbbb | 2322 | if (IS_GEN6(dev_priv)) |
3cf17fc5 DV |
2323 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); |
2324 | ||
b4ac5afc | 2325 | for_each_engine(engine, dev_priv) { |
e2f80391 | 2326 | seq_printf(m, "%s\n", engine->name); |
7e22dbbb | 2327 | if (IS_GEN7(dev_priv)) |
e2f80391 TU |
2328 | seq_printf(m, "GFX_MODE: 0x%08x\n", |
2329 | I915_READ(RING_MODE_GEN7(engine))); | |
2330 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", | |
2331 | I915_READ(RING_PP_DIR_BASE(engine))); | |
2332 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", | |
2333 | I915_READ(RING_PP_DIR_BASE_READ(engine))); | |
2334 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", | |
2335 | I915_READ(RING_PP_DIR_DCLV(engine))); | |
3cf17fc5 DV |
2336 | } |
2337 | if (dev_priv->mm.aliasing_ppgtt) { | |
2338 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2339 | ||
267f0c90 | 2340 | seq_puts(m, "aliasing PPGTT:\n"); |
44159ddb | 2341 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset); |
1c60fef5 | 2342 | |
87d60b63 | 2343 | ppgtt->debug_dump(ppgtt, m); |
ae6c4806 | 2344 | } |
1c60fef5 | 2345 | |
3cf17fc5 | 2346 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); |
77df6772 BW |
2347 | } |
2348 | ||
2349 | static int i915_ppgtt_info(struct seq_file *m, void *data) | |
2350 | { | |
9f25d007 | 2351 | struct drm_info_node *node = m->private; |
77df6772 | 2352 | struct drm_device *dev = node->minor->dev; |
c8c8fb33 | 2353 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea91e401 | 2354 | struct drm_file *file; |
77df6772 BW |
2355 | |
2356 | int ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2357 | if (ret) | |
2358 | return ret; | |
c8c8fb33 | 2359 | intel_runtime_pm_get(dev_priv); |
77df6772 BW |
2360 | |
2361 | if (INTEL_INFO(dev)->gen >= 8) | |
2362 | gen8_ppgtt_info(m, dev); | |
2363 | else if (INTEL_INFO(dev)->gen >= 6) | |
2364 | gen6_ppgtt_info(m, dev); | |
2365 | ||
1d2ac403 | 2366 | mutex_lock(&dev->filelist_mutex); |
ea91e401 MT |
2367 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2368 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
7cb5dff8 | 2369 | struct task_struct *task; |
ea91e401 | 2370 | |
7cb5dff8 | 2371 | task = get_pid_task(file->pid, PIDTYPE_PID); |
06812760 DC |
2372 | if (!task) { |
2373 | ret = -ESRCH; | |
2374 | goto out_put; | |
2375 | } | |
7cb5dff8 GT |
2376 | seq_printf(m, "\nproc: %s\n", task->comm); |
2377 | put_task_struct(task); | |
ea91e401 MT |
2378 | idr_for_each(&file_priv->context_idr, per_file_ctx, |
2379 | (void *)(unsigned long)m); | |
2380 | } | |
1d2ac403 | 2381 | mutex_unlock(&dev->filelist_mutex); |
ea91e401 | 2382 | |
06812760 | 2383 | out_put: |
c8c8fb33 | 2384 | intel_runtime_pm_put(dev_priv); |
3cf17fc5 DV |
2385 | mutex_unlock(&dev->struct_mutex); |
2386 | ||
06812760 | 2387 | return ret; |
3cf17fc5 DV |
2388 | } |
2389 | ||
f5a4c67d CW |
2390 | static int count_irq_waiters(struct drm_i915_private *i915) |
2391 | { | |
e2f80391 | 2392 | struct intel_engine_cs *engine; |
f5a4c67d | 2393 | int count = 0; |
f5a4c67d | 2394 | |
b4ac5afc | 2395 | for_each_engine(engine, i915) |
e2f80391 | 2396 | count += engine->irq_refcount; |
f5a4c67d CW |
2397 | |
2398 | return count; | |
2399 | } | |
2400 | ||
1854d5ca CW |
2401 | static int i915_rps_boost_info(struct seq_file *m, void *data) |
2402 | { | |
2403 | struct drm_info_node *node = m->private; | |
2404 | struct drm_device *dev = node->minor->dev; | |
2405 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2406 | struct drm_file *file; | |
1854d5ca | 2407 | |
f5a4c67d CW |
2408 | seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled); |
2409 | seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy); | |
2410 | seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv)); | |
2411 | seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n", | |
2412 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), | |
2413 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), | |
2414 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit), | |
2415 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit), | |
2416 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1d2ac403 DV |
2417 | |
2418 | mutex_lock(&dev->filelist_mutex); | |
8d3afd7d | 2419 | spin_lock(&dev_priv->rps.client_lock); |
1854d5ca CW |
2420 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2421 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2422 | struct task_struct *task; | |
2423 | ||
2424 | rcu_read_lock(); | |
2425 | task = pid_task(file->pid, PIDTYPE_PID); | |
2426 | seq_printf(m, "%s [%d]: %d boosts%s\n", | |
2427 | task ? task->comm : "<unknown>", | |
2428 | task ? task->pid : -1, | |
2e1b8730 CW |
2429 | file_priv->rps.boosts, |
2430 | list_empty(&file_priv->rps.link) ? "" : ", active"); | |
1854d5ca CW |
2431 | rcu_read_unlock(); |
2432 | } | |
2e1b8730 CW |
2433 | seq_printf(m, "Semaphore boosts: %d%s\n", |
2434 | dev_priv->rps.semaphores.boosts, | |
2435 | list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active"); | |
2436 | seq_printf(m, "MMIO flip boosts: %d%s\n", | |
2437 | dev_priv->rps.mmioflips.boosts, | |
2438 | list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active"); | |
1854d5ca | 2439 | seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts); |
8d3afd7d | 2440 | spin_unlock(&dev_priv->rps.client_lock); |
1d2ac403 | 2441 | mutex_unlock(&dev->filelist_mutex); |
1854d5ca | 2442 | |
8d3afd7d | 2443 | return 0; |
1854d5ca CW |
2444 | } |
2445 | ||
63573eb7 BW |
2446 | static int i915_llc(struct seq_file *m, void *data) |
2447 | { | |
9f25d007 | 2448 | struct drm_info_node *node = m->private; |
63573eb7 BW |
2449 | struct drm_device *dev = node->minor->dev; |
2450 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3accaf7e | 2451 | const bool edram = INTEL_GEN(dev_priv) > 8; |
63573eb7 | 2452 | |
63573eb7 | 2453 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); |
3accaf7e MK |
2454 | seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC", |
2455 | intel_uncore_edram_size(dev_priv)/1024/1024); | |
63573eb7 BW |
2456 | |
2457 | return 0; | |
2458 | } | |
2459 | ||
fdf5d357 AD |
2460 | static int i915_guc_load_status_info(struct seq_file *m, void *data) |
2461 | { | |
2462 | struct drm_info_node *node = m->private; | |
2463 | struct drm_i915_private *dev_priv = node->minor->dev->dev_private; | |
2464 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; | |
2465 | u32 tmp, i; | |
2466 | ||
2d1fe073 | 2467 | if (!HAS_GUC_UCODE(dev_priv)) |
fdf5d357 AD |
2468 | return 0; |
2469 | ||
2470 | seq_printf(m, "GuC firmware status:\n"); | |
2471 | seq_printf(m, "\tpath: %s\n", | |
2472 | guc_fw->guc_fw_path); | |
2473 | seq_printf(m, "\tfetch: %s\n", | |
2474 | intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status)); | |
2475 | seq_printf(m, "\tload: %s\n", | |
2476 | intel_guc_fw_status_repr(guc_fw->guc_fw_load_status)); | |
2477 | seq_printf(m, "\tversion wanted: %d.%d\n", | |
2478 | guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted); | |
2479 | seq_printf(m, "\tversion found: %d.%d\n", | |
2480 | guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found); | |
feda33ef AD |
2481 | seq_printf(m, "\theader: offset is %d; size = %d\n", |
2482 | guc_fw->header_offset, guc_fw->header_size); | |
2483 | seq_printf(m, "\tuCode: offset is %d; size = %d\n", | |
2484 | guc_fw->ucode_offset, guc_fw->ucode_size); | |
2485 | seq_printf(m, "\tRSA: offset is %d; size = %d\n", | |
2486 | guc_fw->rsa_offset, guc_fw->rsa_size); | |
fdf5d357 AD |
2487 | |
2488 | tmp = I915_READ(GUC_STATUS); | |
2489 | ||
2490 | seq_printf(m, "\nGuC status 0x%08x:\n", tmp); | |
2491 | seq_printf(m, "\tBootrom status = 0x%x\n", | |
2492 | (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT); | |
2493 | seq_printf(m, "\tuKernel status = 0x%x\n", | |
2494 | (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT); | |
2495 | seq_printf(m, "\tMIA Core status = 0x%x\n", | |
2496 | (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT); | |
2497 | seq_puts(m, "\nScratch registers:\n"); | |
2498 | for (i = 0; i < 16; i++) | |
2499 | seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i))); | |
2500 | ||
2501 | return 0; | |
2502 | } | |
2503 | ||
8b417c26 DG |
2504 | static void i915_guc_client_info(struct seq_file *m, |
2505 | struct drm_i915_private *dev_priv, | |
2506 | struct i915_guc_client *client) | |
2507 | { | |
e2f80391 | 2508 | struct intel_engine_cs *engine; |
8b417c26 | 2509 | uint64_t tot = 0; |
8b417c26 DG |
2510 | |
2511 | seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n", | |
2512 | client->priority, client->ctx_index, client->proc_desc_offset); | |
2513 | seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n", | |
2514 | client->doorbell_id, client->doorbell_offset, client->cookie); | |
2515 | seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n", | |
2516 | client->wq_size, client->wq_offset, client->wq_tail); | |
2517 | ||
2518 | seq_printf(m, "\tFailed to queue: %u\n", client->q_fail); | |
2519 | seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail); | |
2520 | seq_printf(m, "\tLast submission result: %d\n", client->retcode); | |
2521 | ||
b4ac5afc | 2522 | for_each_engine(engine, dev_priv) { |
8b417c26 | 2523 | seq_printf(m, "\tSubmissions: %llu %s\n", |
e2f80391 TU |
2524 | client->submissions[engine->guc_id], |
2525 | engine->name); | |
2526 | tot += client->submissions[engine->guc_id]; | |
8b417c26 DG |
2527 | } |
2528 | seq_printf(m, "\tTotal: %llu\n", tot); | |
2529 | } | |
2530 | ||
2531 | static int i915_guc_info(struct seq_file *m, void *data) | |
2532 | { | |
2533 | struct drm_info_node *node = m->private; | |
2534 | struct drm_device *dev = node->minor->dev; | |
2535 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2536 | struct intel_guc guc; | |
0a0b457f | 2537 | struct i915_guc_client client = {}; |
e2f80391 | 2538 | struct intel_engine_cs *engine; |
8b417c26 DG |
2539 | u64 total = 0; |
2540 | ||
2d1fe073 | 2541 | if (!HAS_GUC_SCHED(dev_priv)) |
8b417c26 DG |
2542 | return 0; |
2543 | ||
5a843307 AD |
2544 | if (mutex_lock_interruptible(&dev->struct_mutex)) |
2545 | return 0; | |
2546 | ||
8b417c26 | 2547 | /* Take a local copy of the GuC data, so we can dump it at leisure */ |
8b417c26 | 2548 | guc = dev_priv->guc; |
5a843307 | 2549 | if (guc.execbuf_client) |
8b417c26 | 2550 | client = *guc.execbuf_client; |
5a843307 AD |
2551 | |
2552 | mutex_unlock(&dev->struct_mutex); | |
8b417c26 DG |
2553 | |
2554 | seq_printf(m, "GuC total action count: %llu\n", guc.action_count); | |
2555 | seq_printf(m, "GuC action failure count: %u\n", guc.action_fail); | |
2556 | seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd); | |
2557 | seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status); | |
2558 | seq_printf(m, "GuC last action error code: %d\n", guc.action_err); | |
2559 | ||
2560 | seq_printf(m, "\nGuC submissions:\n"); | |
b4ac5afc | 2561 | for_each_engine(engine, dev_priv) { |
397097b0 | 2562 | seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n", |
e2f80391 TU |
2563 | engine->name, guc.submissions[engine->guc_id], |
2564 | guc.last_seqno[engine->guc_id]); | |
2565 | total += guc.submissions[engine->guc_id]; | |
8b417c26 DG |
2566 | } |
2567 | seq_printf(m, "\t%s: %llu\n", "Total", total); | |
2568 | ||
2569 | seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client); | |
2570 | i915_guc_client_info(m, dev_priv, &client); | |
2571 | ||
2572 | /* Add more as required ... */ | |
2573 | ||
2574 | return 0; | |
2575 | } | |
2576 | ||
4c7e77fc AD |
2577 | static int i915_guc_log_dump(struct seq_file *m, void *data) |
2578 | { | |
2579 | struct drm_info_node *node = m->private; | |
2580 | struct drm_device *dev = node->minor->dev; | |
2581 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2582 | struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj; | |
2583 | u32 *log; | |
2584 | int i = 0, pg; | |
2585 | ||
2586 | if (!log_obj) | |
2587 | return 0; | |
2588 | ||
2589 | for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) { | |
2590 | log = kmap_atomic(i915_gem_object_get_page(log_obj, pg)); | |
2591 | ||
2592 | for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4) | |
2593 | seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2594 | *(log + i), *(log + i + 1), | |
2595 | *(log + i + 2), *(log + i + 3)); | |
2596 | ||
2597 | kunmap_atomic(log); | |
2598 | } | |
2599 | ||
2600 | seq_putc(m, '\n'); | |
2601 | ||
2602 | return 0; | |
2603 | } | |
2604 | ||
e91fd8c6 RV |
2605 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
2606 | { | |
2607 | struct drm_info_node *node = m->private; | |
2608 | struct drm_device *dev = node->minor->dev; | |
2609 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a031d709 | 2610 | u32 psrperf = 0; |
a6cbdb8e RV |
2611 | u32 stat[3]; |
2612 | enum pipe pipe; | |
a031d709 | 2613 | bool enabled = false; |
e91fd8c6 | 2614 | |
3553a8ea DL |
2615 | if (!HAS_PSR(dev)) { |
2616 | seq_puts(m, "PSR not supported\n"); | |
2617 | return 0; | |
2618 | } | |
2619 | ||
c8c8fb33 PZ |
2620 | intel_runtime_pm_get(dev_priv); |
2621 | ||
fa128fa6 | 2622 | mutex_lock(&dev_priv->psr.lock); |
a031d709 RV |
2623 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
2624 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); | |
2807cf69 | 2625 | seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); |
5755c78f | 2626 | seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); |
fa128fa6 DV |
2627 | seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", |
2628 | dev_priv->psr.busy_frontbuffer_bits); | |
2629 | seq_printf(m, "Re-enable work scheduled: %s\n", | |
2630 | yesno(work_busy(&dev_priv->psr.work.work))); | |
e91fd8c6 | 2631 | |
3553a8ea | 2632 | if (HAS_DDI(dev)) |
443a389f | 2633 | enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; |
3553a8ea DL |
2634 | else { |
2635 | for_each_pipe(dev_priv, pipe) { | |
2636 | stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) & | |
2637 | VLV_EDP_PSR_CURR_STATE_MASK; | |
2638 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2639 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2640 | enabled = true; | |
a6cbdb8e RV |
2641 | } |
2642 | } | |
60e5ffe3 RV |
2643 | |
2644 | seq_printf(m, "Main link in standby mode: %s\n", | |
2645 | yesno(dev_priv->psr.link_standby)); | |
2646 | ||
a6cbdb8e RV |
2647 | seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled)); |
2648 | ||
2649 | if (!HAS_DDI(dev)) | |
2650 | for_each_pipe(dev_priv, pipe) { | |
2651 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2652 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2653 | seq_printf(m, " pipe %c", pipe_name(pipe)); | |
2654 | } | |
2655 | seq_puts(m, "\n"); | |
e91fd8c6 | 2656 | |
05eec3c2 RV |
2657 | /* |
2658 | * VLV/CHV PSR has no kind of performance counter | |
2659 | * SKL+ Perf counter is reset to 0 everytime DC state is entered | |
2660 | */ | |
2661 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
443a389f | 2662 | psrperf = I915_READ(EDP_PSR_PERF_CNT) & |
a031d709 | 2663 | EDP_PSR_PERF_CNT_MASK; |
a6cbdb8e RV |
2664 | |
2665 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
2666 | } | |
fa128fa6 | 2667 | mutex_unlock(&dev_priv->psr.lock); |
e91fd8c6 | 2668 | |
c8c8fb33 | 2669 | intel_runtime_pm_put(dev_priv); |
e91fd8c6 RV |
2670 | return 0; |
2671 | } | |
2672 | ||
d2e216d0 RV |
2673 | static int i915_sink_crc(struct seq_file *m, void *data) |
2674 | { | |
2675 | struct drm_info_node *node = m->private; | |
2676 | struct drm_device *dev = node->minor->dev; | |
2677 | struct intel_encoder *encoder; | |
2678 | struct intel_connector *connector; | |
2679 | struct intel_dp *intel_dp = NULL; | |
2680 | int ret; | |
2681 | u8 crc[6]; | |
2682 | ||
2683 | drm_modeset_lock_all(dev); | |
aca5e361 | 2684 | for_each_intel_connector(dev, connector) { |
d2e216d0 RV |
2685 | |
2686 | if (connector->base.dpms != DRM_MODE_DPMS_ON) | |
2687 | continue; | |
2688 | ||
b6ae3c7c PZ |
2689 | if (!connector->base.encoder) |
2690 | continue; | |
2691 | ||
d2e216d0 RV |
2692 | encoder = to_intel_encoder(connector->base.encoder); |
2693 | if (encoder->type != INTEL_OUTPUT_EDP) | |
2694 | continue; | |
2695 | ||
2696 | intel_dp = enc_to_intel_dp(&encoder->base); | |
2697 | ||
2698 | ret = intel_dp_sink_crc(intel_dp, crc); | |
2699 | if (ret) | |
2700 | goto out; | |
2701 | ||
2702 | seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", | |
2703 | crc[0], crc[1], crc[2], | |
2704 | crc[3], crc[4], crc[5]); | |
2705 | goto out; | |
2706 | } | |
2707 | ret = -ENODEV; | |
2708 | out: | |
2709 | drm_modeset_unlock_all(dev); | |
2710 | return ret; | |
2711 | } | |
2712 | ||
ec013e7f JB |
2713 | static int i915_energy_uJ(struct seq_file *m, void *data) |
2714 | { | |
2715 | struct drm_info_node *node = m->private; | |
2716 | struct drm_device *dev = node->minor->dev; | |
2717 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2718 | u64 power; | |
2719 | u32 units; | |
2720 | ||
2721 | if (INTEL_INFO(dev)->gen < 6) | |
2722 | return -ENODEV; | |
2723 | ||
36623ef8 PZ |
2724 | intel_runtime_pm_get(dev_priv); |
2725 | ||
ec013e7f JB |
2726 | rdmsrl(MSR_RAPL_POWER_UNIT, power); |
2727 | power = (power & 0x1f00) >> 8; | |
2728 | units = 1000000 / (1 << power); /* convert to uJ */ | |
2729 | power = I915_READ(MCH_SECP_NRG_STTS); | |
2730 | power *= units; | |
2731 | ||
36623ef8 PZ |
2732 | intel_runtime_pm_put(dev_priv); |
2733 | ||
ec013e7f | 2734 | seq_printf(m, "%llu", (long long unsigned)power); |
371db66a PZ |
2735 | |
2736 | return 0; | |
2737 | } | |
2738 | ||
6455c870 | 2739 | static int i915_runtime_pm_status(struct seq_file *m, void *unused) |
371db66a | 2740 | { |
9f25d007 | 2741 | struct drm_info_node *node = m->private; |
371db66a PZ |
2742 | struct drm_device *dev = node->minor->dev; |
2743 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2744 | ||
a156e64d CW |
2745 | if (!HAS_RUNTIME_PM(dev_priv)) |
2746 | seq_puts(m, "Runtime power management not supported\n"); | |
371db66a | 2747 | |
86c4ec0d | 2748 | seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy)); |
371db66a | 2749 | seq_printf(m, "IRQs disabled: %s\n", |
9df7575f | 2750 | yesno(!intel_irqs_enabled(dev_priv))); |
0d804184 | 2751 | #ifdef CONFIG_PM |
a6aaec8b DL |
2752 | seq_printf(m, "Usage count: %d\n", |
2753 | atomic_read(&dev->dev->power.usage_count)); | |
0d804184 CW |
2754 | #else |
2755 | seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); | |
2756 | #endif | |
a156e64d CW |
2757 | seq_printf(m, "PCI device power state: %s [%d]\n", |
2758 | pci_power_name(dev_priv->dev->pdev->current_state), | |
2759 | dev_priv->dev->pdev->current_state); | |
371db66a | 2760 | |
ec013e7f JB |
2761 | return 0; |
2762 | } | |
2763 | ||
1da51581 ID |
2764 | static int i915_power_domain_info(struct seq_file *m, void *unused) |
2765 | { | |
9f25d007 | 2766 | struct drm_info_node *node = m->private; |
1da51581 ID |
2767 | struct drm_device *dev = node->minor->dev; |
2768 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2769 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
2770 | int i; | |
2771 | ||
2772 | mutex_lock(&power_domains->lock); | |
2773 | ||
2774 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); | |
2775 | for (i = 0; i < power_domains->power_well_count; i++) { | |
2776 | struct i915_power_well *power_well; | |
2777 | enum intel_display_power_domain power_domain; | |
2778 | ||
2779 | power_well = &power_domains->power_wells[i]; | |
2780 | seq_printf(m, "%-25s %d\n", power_well->name, | |
2781 | power_well->count); | |
2782 | ||
2783 | for (power_domain = 0; power_domain < POWER_DOMAIN_NUM; | |
2784 | power_domain++) { | |
2785 | if (!(BIT(power_domain) & power_well->domains)) | |
2786 | continue; | |
2787 | ||
2788 | seq_printf(m, " %-23s %d\n", | |
9895ad03 | 2789 | intel_display_power_domain_str(power_domain), |
1da51581 ID |
2790 | power_domains->domain_use_count[power_domain]); |
2791 | } | |
2792 | } | |
2793 | ||
2794 | mutex_unlock(&power_domains->lock); | |
2795 | ||
2796 | return 0; | |
2797 | } | |
2798 | ||
b7cec66d DL |
2799 | static int i915_dmc_info(struct seq_file *m, void *unused) |
2800 | { | |
2801 | struct drm_info_node *node = m->private; | |
2802 | struct drm_device *dev = node->minor->dev; | |
2803 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2804 | struct intel_csr *csr; | |
2805 | ||
2806 | if (!HAS_CSR(dev)) { | |
2807 | seq_puts(m, "not supported\n"); | |
2808 | return 0; | |
2809 | } | |
2810 | ||
2811 | csr = &dev_priv->csr; | |
2812 | ||
6fb403de MK |
2813 | intel_runtime_pm_get(dev_priv); |
2814 | ||
b7cec66d DL |
2815 | seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL)); |
2816 | seq_printf(m, "path: %s\n", csr->fw_path); | |
2817 | ||
2818 | if (!csr->dmc_payload) | |
6fb403de | 2819 | goto out; |
b7cec66d DL |
2820 | |
2821 | seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), | |
2822 | CSR_VERSION_MINOR(csr->version)); | |
2823 | ||
8337206d DL |
2824 | if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) { |
2825 | seq_printf(m, "DC3 -> DC5 count: %d\n", | |
2826 | I915_READ(SKL_CSR_DC3_DC5_COUNT)); | |
2827 | seq_printf(m, "DC5 -> DC6 count: %d\n", | |
2828 | I915_READ(SKL_CSR_DC5_DC6_COUNT)); | |
16e11b99 MK |
2829 | } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) { |
2830 | seq_printf(m, "DC3 -> DC5 count: %d\n", | |
2831 | I915_READ(BXT_CSR_DC3_DC5_COUNT)); | |
8337206d DL |
2832 | } |
2833 | ||
6fb403de MK |
2834 | out: |
2835 | seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0))); | |
2836 | seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE)); | |
2837 | seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL)); | |
2838 | ||
8337206d DL |
2839 | intel_runtime_pm_put(dev_priv); |
2840 | ||
b7cec66d DL |
2841 | return 0; |
2842 | } | |
2843 | ||
53f5e3ca JB |
2844 | static void intel_seq_print_mode(struct seq_file *m, int tabs, |
2845 | struct drm_display_mode *mode) | |
2846 | { | |
2847 | int i; | |
2848 | ||
2849 | for (i = 0; i < tabs; i++) | |
2850 | seq_putc(m, '\t'); | |
2851 | ||
2852 | seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", | |
2853 | mode->base.id, mode->name, | |
2854 | mode->vrefresh, mode->clock, | |
2855 | mode->hdisplay, mode->hsync_start, | |
2856 | mode->hsync_end, mode->htotal, | |
2857 | mode->vdisplay, mode->vsync_start, | |
2858 | mode->vsync_end, mode->vtotal, | |
2859 | mode->type, mode->flags); | |
2860 | } | |
2861 | ||
2862 | static void intel_encoder_info(struct seq_file *m, | |
2863 | struct intel_crtc *intel_crtc, | |
2864 | struct intel_encoder *intel_encoder) | |
2865 | { | |
9f25d007 | 2866 | struct drm_info_node *node = m->private; |
53f5e3ca JB |
2867 | struct drm_device *dev = node->minor->dev; |
2868 | struct drm_crtc *crtc = &intel_crtc->base; | |
2869 | struct intel_connector *intel_connector; | |
2870 | struct drm_encoder *encoder; | |
2871 | ||
2872 | encoder = &intel_encoder->base; | |
2873 | seq_printf(m, "\tencoder %d: type: %s, connectors:\n", | |
8e329a03 | 2874 | encoder->base.id, encoder->name); |
53f5e3ca JB |
2875 | for_each_connector_on_encoder(dev, encoder, intel_connector) { |
2876 | struct drm_connector *connector = &intel_connector->base; | |
2877 | seq_printf(m, "\t\tconnector %d: type: %s, status: %s", | |
2878 | connector->base.id, | |
c23cc417 | 2879 | connector->name, |
53f5e3ca JB |
2880 | drm_get_connector_status_name(connector->status)); |
2881 | if (connector->status == connector_status_connected) { | |
2882 | struct drm_display_mode *mode = &crtc->mode; | |
2883 | seq_printf(m, ", mode:\n"); | |
2884 | intel_seq_print_mode(m, 2, mode); | |
2885 | } else { | |
2886 | seq_putc(m, '\n'); | |
2887 | } | |
2888 | } | |
2889 | } | |
2890 | ||
2891 | static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
2892 | { | |
9f25d007 | 2893 | struct drm_info_node *node = m->private; |
53f5e3ca JB |
2894 | struct drm_device *dev = node->minor->dev; |
2895 | struct drm_crtc *crtc = &intel_crtc->base; | |
2896 | struct intel_encoder *intel_encoder; | |
23a48d53 ML |
2897 | struct drm_plane_state *plane_state = crtc->primary->state; |
2898 | struct drm_framebuffer *fb = plane_state->fb; | |
53f5e3ca | 2899 | |
23a48d53 | 2900 | if (fb) |
5aa8a937 | 2901 | seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", |
23a48d53 ML |
2902 | fb->base.id, plane_state->src_x >> 16, |
2903 | plane_state->src_y >> 16, fb->width, fb->height); | |
5aa8a937 MR |
2904 | else |
2905 | seq_puts(m, "\tprimary plane disabled\n"); | |
53f5e3ca JB |
2906 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
2907 | intel_encoder_info(m, intel_crtc, intel_encoder); | |
2908 | } | |
2909 | ||
2910 | static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) | |
2911 | { | |
2912 | struct drm_display_mode *mode = panel->fixed_mode; | |
2913 | ||
2914 | seq_printf(m, "\tfixed mode:\n"); | |
2915 | intel_seq_print_mode(m, 2, mode); | |
2916 | } | |
2917 | ||
2918 | static void intel_dp_info(struct seq_file *m, | |
2919 | struct intel_connector *intel_connector) | |
2920 | { | |
2921 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2922 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
2923 | ||
2924 | seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); | |
742f491d | 2925 | seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio)); |
53f5e3ca JB |
2926 | if (intel_encoder->type == INTEL_OUTPUT_EDP) |
2927 | intel_panel_info(m, &intel_connector->panel); | |
2928 | } | |
2929 | ||
2930 | static void intel_hdmi_info(struct seq_file *m, | |
2931 | struct intel_connector *intel_connector) | |
2932 | { | |
2933 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2934 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); | |
2935 | ||
742f491d | 2936 | seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio)); |
53f5e3ca JB |
2937 | } |
2938 | ||
2939 | static void intel_lvds_info(struct seq_file *m, | |
2940 | struct intel_connector *intel_connector) | |
2941 | { | |
2942 | intel_panel_info(m, &intel_connector->panel); | |
2943 | } | |
2944 | ||
2945 | static void intel_connector_info(struct seq_file *m, | |
2946 | struct drm_connector *connector) | |
2947 | { | |
2948 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
2949 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
f103fc7d | 2950 | struct drm_display_mode *mode; |
53f5e3ca JB |
2951 | |
2952 | seq_printf(m, "connector %d: type %s, status: %s\n", | |
c23cc417 | 2953 | connector->base.id, connector->name, |
53f5e3ca JB |
2954 | drm_get_connector_status_name(connector->status)); |
2955 | if (connector->status == connector_status_connected) { | |
2956 | seq_printf(m, "\tname: %s\n", connector->display_info.name); | |
2957 | seq_printf(m, "\tphysical dimensions: %dx%dmm\n", | |
2958 | connector->display_info.width_mm, | |
2959 | connector->display_info.height_mm); | |
2960 | seq_printf(m, "\tsubpixel order: %s\n", | |
2961 | drm_get_subpixel_order_name(connector->display_info.subpixel_order)); | |
2962 | seq_printf(m, "\tCEA rev: %d\n", | |
2963 | connector->display_info.cea_rev); | |
2964 | } | |
36cd7444 DA |
2965 | if (intel_encoder) { |
2966 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || | |
2967 | intel_encoder->type == INTEL_OUTPUT_EDP) | |
2968 | intel_dp_info(m, intel_connector); | |
2969 | else if (intel_encoder->type == INTEL_OUTPUT_HDMI) | |
2970 | intel_hdmi_info(m, intel_connector); | |
2971 | else if (intel_encoder->type == INTEL_OUTPUT_LVDS) | |
2972 | intel_lvds_info(m, intel_connector); | |
2973 | } | |
53f5e3ca | 2974 | |
f103fc7d JB |
2975 | seq_printf(m, "\tmodes:\n"); |
2976 | list_for_each_entry(mode, &connector->modes, head) | |
2977 | intel_seq_print_mode(m, 2, mode); | |
53f5e3ca JB |
2978 | } |
2979 | ||
065f2ec2 CW |
2980 | static bool cursor_active(struct drm_device *dev, int pipe) |
2981 | { | |
2982 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2983 | u32 state; | |
2984 | ||
2985 | if (IS_845G(dev) || IS_I865G(dev)) | |
0b87c24e | 2986 | state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
065f2ec2 | 2987 | else |
5efb3e28 | 2988 | state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
065f2ec2 CW |
2989 | |
2990 | return state; | |
2991 | } | |
2992 | ||
2993 | static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y) | |
2994 | { | |
2995 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2996 | u32 pos; | |
2997 | ||
5efb3e28 | 2998 | pos = I915_READ(CURPOS(pipe)); |
065f2ec2 CW |
2999 | |
3000 | *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK; | |
3001 | if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT)) | |
3002 | *x = -*x; | |
3003 | ||
3004 | *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK; | |
3005 | if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT)) | |
3006 | *y = -*y; | |
3007 | ||
3008 | return cursor_active(dev, pipe); | |
3009 | } | |
3010 | ||
3abc4e09 RF |
3011 | static const char *plane_type(enum drm_plane_type type) |
3012 | { | |
3013 | switch (type) { | |
3014 | case DRM_PLANE_TYPE_OVERLAY: | |
3015 | return "OVL"; | |
3016 | case DRM_PLANE_TYPE_PRIMARY: | |
3017 | return "PRI"; | |
3018 | case DRM_PLANE_TYPE_CURSOR: | |
3019 | return "CUR"; | |
3020 | /* | |
3021 | * Deliberately omitting default: to generate compiler warnings | |
3022 | * when a new drm_plane_type gets added. | |
3023 | */ | |
3024 | } | |
3025 | ||
3026 | return "unknown"; | |
3027 | } | |
3028 | ||
3029 | static const char *plane_rotation(unsigned int rotation) | |
3030 | { | |
3031 | static char buf[48]; | |
3032 | /* | |
3033 | * According to doc only one DRM_ROTATE_ is allowed but this | |
3034 | * will print them all to visualize if the values are misused | |
3035 | */ | |
3036 | snprintf(buf, sizeof(buf), | |
3037 | "%s%s%s%s%s%s(0x%08x)", | |
3038 | (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "", | |
3039 | (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "", | |
3040 | (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "", | |
3041 | (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "", | |
3042 | (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "", | |
3043 | (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "", | |
3044 | rotation); | |
3045 | ||
3046 | return buf; | |
3047 | } | |
3048 | ||
3049 | static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3050 | { | |
3051 | struct drm_info_node *node = m->private; | |
3052 | struct drm_device *dev = node->minor->dev; | |
3053 | struct intel_plane *intel_plane; | |
3054 | ||
3055 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { | |
3056 | struct drm_plane_state *state; | |
3057 | struct drm_plane *plane = &intel_plane->base; | |
3058 | ||
3059 | if (!plane->state) { | |
3060 | seq_puts(m, "plane->state is NULL!\n"); | |
3061 | continue; | |
3062 | } | |
3063 | ||
3064 | state = plane->state; | |
3065 | ||
3066 | seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n", | |
3067 | plane->base.id, | |
3068 | plane_type(intel_plane->base.type), | |
3069 | state->crtc_x, state->crtc_y, | |
3070 | state->crtc_w, state->crtc_h, | |
3071 | (state->src_x >> 16), | |
3072 | ((state->src_x & 0xffff) * 15625) >> 10, | |
3073 | (state->src_y >> 16), | |
3074 | ((state->src_y & 0xffff) * 15625) >> 10, | |
3075 | (state->src_w >> 16), | |
3076 | ((state->src_w & 0xffff) * 15625) >> 10, | |
3077 | (state->src_h >> 16), | |
3078 | ((state->src_h & 0xffff) * 15625) >> 10, | |
3079 | state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A", | |
3080 | plane_rotation(state->rotation)); | |
3081 | } | |
3082 | } | |
3083 | ||
3084 | static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3085 | { | |
3086 | struct intel_crtc_state *pipe_config; | |
3087 | int num_scalers = intel_crtc->num_scalers; | |
3088 | int i; | |
3089 | ||
3090 | pipe_config = to_intel_crtc_state(intel_crtc->base.state); | |
3091 | ||
3092 | /* Not all platformas have a scaler */ | |
3093 | if (num_scalers) { | |
3094 | seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d", | |
3095 | num_scalers, | |
3096 | pipe_config->scaler_state.scaler_users, | |
3097 | pipe_config->scaler_state.scaler_id); | |
3098 | ||
3099 | for (i = 0; i < SKL_NUM_SCALERS; i++) { | |
3100 | struct intel_scaler *sc = | |
3101 | &pipe_config->scaler_state.scalers[i]; | |
3102 | ||
3103 | seq_printf(m, ", scalers[%d]: use=%s, mode=%x", | |
3104 | i, yesno(sc->in_use), sc->mode); | |
3105 | } | |
3106 | seq_puts(m, "\n"); | |
3107 | } else { | |
3108 | seq_puts(m, "\tNo scalers available on this platform\n"); | |
3109 | } | |
3110 | } | |
3111 | ||
53f5e3ca JB |
3112 | static int i915_display_info(struct seq_file *m, void *unused) |
3113 | { | |
9f25d007 | 3114 | struct drm_info_node *node = m->private; |
53f5e3ca | 3115 | struct drm_device *dev = node->minor->dev; |
b0e5ddf3 | 3116 | struct drm_i915_private *dev_priv = dev->dev_private; |
065f2ec2 | 3117 | struct intel_crtc *crtc; |
53f5e3ca JB |
3118 | struct drm_connector *connector; |
3119 | ||
b0e5ddf3 | 3120 | intel_runtime_pm_get(dev_priv); |
53f5e3ca JB |
3121 | drm_modeset_lock_all(dev); |
3122 | seq_printf(m, "CRTC info\n"); | |
3123 | seq_printf(m, "---------\n"); | |
d3fcc808 | 3124 | for_each_intel_crtc(dev, crtc) { |
065f2ec2 | 3125 | bool active; |
f77076c9 | 3126 | struct intel_crtc_state *pipe_config; |
065f2ec2 | 3127 | int x, y; |
53f5e3ca | 3128 | |
f77076c9 ML |
3129 | pipe_config = to_intel_crtc_state(crtc->base.state); |
3130 | ||
3abc4e09 | 3131 | seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n", |
065f2ec2 | 3132 | crtc->base.base.id, pipe_name(crtc->pipe), |
f77076c9 | 3133 | yesno(pipe_config->base.active), |
3abc4e09 RF |
3134 | pipe_config->pipe_src_w, pipe_config->pipe_src_h, |
3135 | yesno(pipe_config->dither), pipe_config->pipe_bpp); | |
3136 | ||
f77076c9 | 3137 | if (pipe_config->base.active) { |
065f2ec2 CW |
3138 | intel_crtc_info(m, crtc); |
3139 | ||
a23dc658 | 3140 | active = cursor_position(dev, crtc->pipe, &x, &y); |
57127efa | 3141 | seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n", |
4b0e333e | 3142 | yesno(crtc->cursor_base), |
3dd512fb MR |
3143 | x, y, crtc->base.cursor->state->crtc_w, |
3144 | crtc->base.cursor->state->crtc_h, | |
57127efa | 3145 | crtc->cursor_addr, yesno(active)); |
3abc4e09 RF |
3146 | intel_scaler_info(m, crtc); |
3147 | intel_plane_info(m, crtc); | |
a23dc658 | 3148 | } |
cace841c DV |
3149 | |
3150 | seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", | |
3151 | yesno(!crtc->cpu_fifo_underrun_disabled), | |
3152 | yesno(!crtc->pch_fifo_underrun_disabled)); | |
53f5e3ca JB |
3153 | } |
3154 | ||
3155 | seq_printf(m, "\n"); | |
3156 | seq_printf(m, "Connector info\n"); | |
3157 | seq_printf(m, "--------------\n"); | |
3158 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
3159 | intel_connector_info(m, connector); | |
3160 | } | |
3161 | drm_modeset_unlock_all(dev); | |
b0e5ddf3 | 3162 | intel_runtime_pm_put(dev_priv); |
53f5e3ca JB |
3163 | |
3164 | return 0; | |
3165 | } | |
3166 | ||
e04934cf BW |
3167 | static int i915_semaphore_status(struct seq_file *m, void *unused) |
3168 | { | |
3169 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
3170 | struct drm_device *dev = node->minor->dev; | |
3171 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2f80391 | 3172 | struct intel_engine_cs *engine; |
e04934cf | 3173 | int num_rings = hweight32(INTEL_INFO(dev)->ring_mask); |
c3232b18 DG |
3174 | enum intel_engine_id id; |
3175 | int j, ret; | |
e04934cf | 3176 | |
c033666a | 3177 | if (!i915_semaphore_is_enabled(dev_priv)) { |
e04934cf BW |
3178 | seq_puts(m, "Semaphores are disabled\n"); |
3179 | return 0; | |
3180 | } | |
3181 | ||
3182 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
3183 | if (ret) | |
3184 | return ret; | |
03872064 | 3185 | intel_runtime_pm_get(dev_priv); |
e04934cf BW |
3186 | |
3187 | if (IS_BROADWELL(dev)) { | |
3188 | struct page *page; | |
3189 | uint64_t *seqno; | |
3190 | ||
3191 | page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0); | |
3192 | ||
3193 | seqno = (uint64_t *)kmap_atomic(page); | |
c3232b18 | 3194 | for_each_engine_id(engine, dev_priv, id) { |
e04934cf BW |
3195 | uint64_t offset; |
3196 | ||
e2f80391 | 3197 | seq_printf(m, "%s\n", engine->name); |
e04934cf BW |
3198 | |
3199 | seq_puts(m, " Last signal:"); | |
3200 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3201 | offset = id * I915_NUM_ENGINES + j; |
e04934cf BW |
3202 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3203 | seqno[offset], offset * 8); | |
3204 | } | |
3205 | seq_putc(m, '\n'); | |
3206 | ||
3207 | seq_puts(m, " Last wait: "); | |
3208 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3209 | offset = id + (j * I915_NUM_ENGINES); |
e04934cf BW |
3210 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3211 | seqno[offset], offset * 8); | |
3212 | } | |
3213 | seq_putc(m, '\n'); | |
3214 | ||
3215 | } | |
3216 | kunmap_atomic(seqno); | |
3217 | } else { | |
3218 | seq_puts(m, " Last signal:"); | |
b4ac5afc | 3219 | for_each_engine(engine, dev_priv) |
e04934cf BW |
3220 | for (j = 0; j < num_rings; j++) |
3221 | seq_printf(m, "0x%08x\n", | |
e2f80391 | 3222 | I915_READ(engine->semaphore.mbox.signal[j])); |
e04934cf BW |
3223 | seq_putc(m, '\n'); |
3224 | } | |
3225 | ||
3226 | seq_puts(m, "\nSync seqno:\n"); | |
b4ac5afc DG |
3227 | for_each_engine(engine, dev_priv) { |
3228 | for (j = 0; j < num_rings; j++) | |
e2f80391 TU |
3229 | seq_printf(m, " 0x%08x ", |
3230 | engine->semaphore.sync_seqno[j]); | |
e04934cf BW |
3231 | seq_putc(m, '\n'); |
3232 | } | |
3233 | seq_putc(m, '\n'); | |
3234 | ||
03872064 | 3235 | intel_runtime_pm_put(dev_priv); |
e04934cf BW |
3236 | mutex_unlock(&dev->struct_mutex); |
3237 | return 0; | |
3238 | } | |
3239 | ||
728e29d7 DV |
3240 | static int i915_shared_dplls_info(struct seq_file *m, void *unused) |
3241 | { | |
3242 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
3243 | struct drm_device *dev = node->minor->dev; | |
3244 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3245 | int i; | |
3246 | ||
3247 | drm_modeset_lock_all(dev); | |
3248 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
3249 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
3250 | ||
3251 | seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); | |
2dd66ebd ML |
3252 | seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n", |
3253 | pll->config.crtc_mask, pll->active_mask, yesno(pll->on)); | |
728e29d7 | 3254 | seq_printf(m, " tracked hardware state:\n"); |
3e369b76 ACO |
3255 | seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll); |
3256 | seq_printf(m, " dpll_md: 0x%08x\n", | |
3257 | pll->config.hw_state.dpll_md); | |
3258 | seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0); | |
3259 | seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1); | |
3260 | seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll); | |
728e29d7 DV |
3261 | } |
3262 | drm_modeset_unlock_all(dev); | |
3263 | ||
3264 | return 0; | |
3265 | } | |
3266 | ||
1ed1ef9d | 3267 | static int i915_wa_registers(struct seq_file *m, void *unused) |
888b5995 AS |
3268 | { |
3269 | int i; | |
3270 | int ret; | |
e2f80391 | 3271 | struct intel_engine_cs *engine; |
888b5995 AS |
3272 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
3273 | struct drm_device *dev = node->minor->dev; | |
3274 | struct drm_i915_private *dev_priv = dev->dev_private; | |
33136b06 | 3275 | struct i915_workarounds *workarounds = &dev_priv->workarounds; |
c3232b18 | 3276 | enum intel_engine_id id; |
888b5995 | 3277 | |
888b5995 AS |
3278 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
3279 | if (ret) | |
3280 | return ret; | |
3281 | ||
3282 | intel_runtime_pm_get(dev_priv); | |
3283 | ||
33136b06 | 3284 | seq_printf(m, "Workarounds applied: %d\n", workarounds->count); |
c3232b18 | 3285 | for_each_engine_id(engine, dev_priv, id) |
33136b06 | 3286 | seq_printf(m, "HW whitelist count for %s: %d\n", |
c3232b18 | 3287 | engine->name, workarounds->hw_whitelist_count[id]); |
33136b06 | 3288 | for (i = 0; i < workarounds->count; ++i) { |
f0f59a00 VS |
3289 | i915_reg_t addr; |
3290 | u32 mask, value, read; | |
2fa60f6d | 3291 | bool ok; |
888b5995 | 3292 | |
33136b06 AS |
3293 | addr = workarounds->reg[i].addr; |
3294 | mask = workarounds->reg[i].mask; | |
3295 | value = workarounds->reg[i].value; | |
2fa60f6d MK |
3296 | read = I915_READ(addr); |
3297 | ok = (value & mask) == (read & mask); | |
3298 | seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n", | |
f0f59a00 | 3299 | i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL"); |
888b5995 AS |
3300 | } |
3301 | ||
3302 | intel_runtime_pm_put(dev_priv); | |
3303 | mutex_unlock(&dev->struct_mutex); | |
3304 | ||
3305 | return 0; | |
3306 | } | |
3307 | ||
c5511e44 DL |
3308 | static int i915_ddb_info(struct seq_file *m, void *unused) |
3309 | { | |
3310 | struct drm_info_node *node = m->private; | |
3311 | struct drm_device *dev = node->minor->dev; | |
3312 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3313 | struct skl_ddb_allocation *ddb; | |
3314 | struct skl_ddb_entry *entry; | |
3315 | enum pipe pipe; | |
3316 | int plane; | |
3317 | ||
2fcffe19 DL |
3318 | if (INTEL_INFO(dev)->gen < 9) |
3319 | return 0; | |
3320 | ||
c5511e44 DL |
3321 | drm_modeset_lock_all(dev); |
3322 | ||
3323 | ddb = &dev_priv->wm.skl_hw.ddb; | |
3324 | ||
3325 | seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); | |
3326 | ||
3327 | for_each_pipe(dev_priv, pipe) { | |
3328 | seq_printf(m, "Pipe %c\n", pipe_name(pipe)); | |
3329 | ||
dd740780 | 3330 | for_each_plane(dev_priv, pipe, plane) { |
c5511e44 DL |
3331 | entry = &ddb->plane[pipe][plane]; |
3332 | seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1, | |
3333 | entry->start, entry->end, | |
3334 | skl_ddb_entry_size(entry)); | |
3335 | } | |
3336 | ||
4969d33e | 3337 | entry = &ddb->plane[pipe][PLANE_CURSOR]; |
c5511e44 DL |
3338 | seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, |
3339 | entry->end, skl_ddb_entry_size(entry)); | |
3340 | } | |
3341 | ||
3342 | drm_modeset_unlock_all(dev); | |
3343 | ||
3344 | return 0; | |
3345 | } | |
3346 | ||
a54746e3 VK |
3347 | static void drrs_status_per_crtc(struct seq_file *m, |
3348 | struct drm_device *dev, struct intel_crtc *intel_crtc) | |
3349 | { | |
3350 | struct intel_encoder *intel_encoder; | |
3351 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3352 | struct i915_drrs *drrs = &dev_priv->drrs; | |
3353 | int vrefresh = 0; | |
3354 | ||
3355 | for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) { | |
3356 | /* Encoder connected on this CRTC */ | |
3357 | switch (intel_encoder->type) { | |
3358 | case INTEL_OUTPUT_EDP: | |
3359 | seq_puts(m, "eDP:\n"); | |
3360 | break; | |
3361 | case INTEL_OUTPUT_DSI: | |
3362 | seq_puts(m, "DSI:\n"); | |
3363 | break; | |
3364 | case INTEL_OUTPUT_HDMI: | |
3365 | seq_puts(m, "HDMI:\n"); | |
3366 | break; | |
3367 | case INTEL_OUTPUT_DISPLAYPORT: | |
3368 | seq_puts(m, "DP:\n"); | |
3369 | break; | |
3370 | default: | |
3371 | seq_printf(m, "Other encoder (id=%d).\n", | |
3372 | intel_encoder->type); | |
3373 | return; | |
3374 | } | |
3375 | } | |
3376 | ||
3377 | if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT) | |
3378 | seq_puts(m, "\tVBT: DRRS_type: Static"); | |
3379 | else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) | |
3380 | seq_puts(m, "\tVBT: DRRS_type: Seamless"); | |
3381 | else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) | |
3382 | seq_puts(m, "\tVBT: DRRS_type: None"); | |
3383 | else | |
3384 | seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value"); | |
3385 | ||
3386 | seq_puts(m, "\n\n"); | |
3387 | ||
f77076c9 | 3388 | if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) { |
a54746e3 VK |
3389 | struct intel_panel *panel; |
3390 | ||
3391 | mutex_lock(&drrs->mutex); | |
3392 | /* DRRS Supported */ | |
3393 | seq_puts(m, "\tDRRS Supported: Yes\n"); | |
3394 | ||
3395 | /* disable_drrs() will make drrs->dp NULL */ | |
3396 | if (!drrs->dp) { | |
3397 | seq_puts(m, "Idleness DRRS: Disabled"); | |
3398 | mutex_unlock(&drrs->mutex); | |
3399 | return; | |
3400 | } | |
3401 | ||
3402 | panel = &drrs->dp->attached_connector->panel; | |
3403 | seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X", | |
3404 | drrs->busy_frontbuffer_bits); | |
3405 | ||
3406 | seq_puts(m, "\n\t\t"); | |
3407 | if (drrs->refresh_rate_type == DRRS_HIGH_RR) { | |
3408 | seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n"); | |
3409 | vrefresh = panel->fixed_mode->vrefresh; | |
3410 | } else if (drrs->refresh_rate_type == DRRS_LOW_RR) { | |
3411 | seq_puts(m, "DRRS_State: DRRS_LOW_RR\n"); | |
3412 | vrefresh = panel->downclock_mode->vrefresh; | |
3413 | } else { | |
3414 | seq_printf(m, "DRRS_State: Unknown(%d)\n", | |
3415 | drrs->refresh_rate_type); | |
3416 | mutex_unlock(&drrs->mutex); | |
3417 | return; | |
3418 | } | |
3419 | seq_printf(m, "\t\tVrefresh: %d", vrefresh); | |
3420 | ||
3421 | seq_puts(m, "\n\t\t"); | |
3422 | mutex_unlock(&drrs->mutex); | |
3423 | } else { | |
3424 | /* DRRS not supported. Print the VBT parameter*/ | |
3425 | seq_puts(m, "\tDRRS Supported : No"); | |
3426 | } | |
3427 | seq_puts(m, "\n"); | |
3428 | } | |
3429 | ||
3430 | static int i915_drrs_status(struct seq_file *m, void *unused) | |
3431 | { | |
3432 | struct drm_info_node *node = m->private; | |
3433 | struct drm_device *dev = node->minor->dev; | |
3434 | struct intel_crtc *intel_crtc; | |
3435 | int active_crtc_cnt = 0; | |
3436 | ||
3437 | for_each_intel_crtc(dev, intel_crtc) { | |
3438 | drm_modeset_lock(&intel_crtc->base.mutex, NULL); | |
3439 | ||
f77076c9 | 3440 | if (intel_crtc->base.state->active) { |
a54746e3 VK |
3441 | active_crtc_cnt++; |
3442 | seq_printf(m, "\nCRTC %d: ", active_crtc_cnt); | |
3443 | ||
3444 | drrs_status_per_crtc(m, dev, intel_crtc); | |
3445 | } | |
3446 | ||
3447 | drm_modeset_unlock(&intel_crtc->base.mutex); | |
3448 | } | |
3449 | ||
3450 | if (!active_crtc_cnt) | |
3451 | seq_puts(m, "No active crtc found\n"); | |
3452 | ||
3453 | return 0; | |
3454 | } | |
3455 | ||
07144428 DL |
3456 | struct pipe_crc_info { |
3457 | const char *name; | |
3458 | struct drm_device *dev; | |
3459 | enum pipe pipe; | |
3460 | }; | |
3461 | ||
11bed958 DA |
3462 | static int i915_dp_mst_info(struct seq_file *m, void *unused) |
3463 | { | |
3464 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
3465 | struct drm_device *dev = node->minor->dev; | |
3466 | struct drm_encoder *encoder; | |
3467 | struct intel_encoder *intel_encoder; | |
3468 | struct intel_digital_port *intel_dig_port; | |
3469 | drm_modeset_lock_all(dev); | |
3470 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
3471 | intel_encoder = to_intel_encoder(encoder); | |
3472 | if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT) | |
3473 | continue; | |
3474 | intel_dig_port = enc_to_dig_port(encoder); | |
3475 | if (!intel_dig_port->dp.can_mst) | |
3476 | continue; | |
40ae80cc JB |
3477 | seq_printf(m, "MST Source Port %c\n", |
3478 | port_name(intel_dig_port->port)); | |
11bed958 DA |
3479 | drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); |
3480 | } | |
3481 | drm_modeset_unlock_all(dev); | |
3482 | return 0; | |
3483 | } | |
3484 | ||
07144428 DL |
3485 | static int i915_pipe_crc_open(struct inode *inode, struct file *filep) |
3486 | { | |
be5c7a90 DL |
3487 | struct pipe_crc_info *info = inode->i_private; |
3488 | struct drm_i915_private *dev_priv = info->dev->dev_private; | |
3489 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
3490 | ||
7eb1c496 DV |
3491 | if (info->pipe >= INTEL_INFO(info->dev)->num_pipes) |
3492 | return -ENODEV; | |
3493 | ||
d538bbdf DL |
3494 | spin_lock_irq(&pipe_crc->lock); |
3495 | ||
3496 | if (pipe_crc->opened) { | |
3497 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 DL |
3498 | return -EBUSY; /* already open */ |
3499 | } | |
3500 | ||
d538bbdf | 3501 | pipe_crc->opened = true; |
07144428 DL |
3502 | filep->private_data = inode->i_private; |
3503 | ||
d538bbdf DL |
3504 | spin_unlock_irq(&pipe_crc->lock); |
3505 | ||
07144428 DL |
3506 | return 0; |
3507 | } | |
3508 | ||
3509 | static int i915_pipe_crc_release(struct inode *inode, struct file *filep) | |
3510 | { | |
be5c7a90 DL |
3511 | struct pipe_crc_info *info = inode->i_private; |
3512 | struct drm_i915_private *dev_priv = info->dev->dev_private; | |
3513 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
3514 | ||
d538bbdf DL |
3515 | spin_lock_irq(&pipe_crc->lock); |
3516 | pipe_crc->opened = false; | |
3517 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 | 3518 | |
07144428 DL |
3519 | return 0; |
3520 | } | |
3521 | ||
3522 | /* (6 fields, 8 chars each, space separated (5) + '\n') */ | |
3523 | #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1) | |
3524 | /* account for \'0' */ | |
3525 | #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1) | |
3526 | ||
3527 | static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc) | |
8bf1e9f1 | 3528 | { |
d538bbdf DL |
3529 | assert_spin_locked(&pipe_crc->lock); |
3530 | return CIRC_CNT(pipe_crc->head, pipe_crc->tail, | |
3531 | INTEL_PIPE_CRC_ENTRIES_NR); | |
07144428 DL |
3532 | } |
3533 | ||
3534 | static ssize_t | |
3535 | i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count, | |
3536 | loff_t *pos) | |
3537 | { | |
3538 | struct pipe_crc_info *info = filep->private_data; | |
3539 | struct drm_device *dev = info->dev; | |
3540 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3541 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
3542 | char buf[PIPE_CRC_BUFFER_LEN]; | |
9ad6d99f | 3543 | int n_entries; |
07144428 DL |
3544 | ssize_t bytes_read; |
3545 | ||
3546 | /* | |
3547 | * Don't allow user space to provide buffers not big enough to hold | |
3548 | * a line of data. | |
3549 | */ | |
3550 | if (count < PIPE_CRC_LINE_LEN) | |
3551 | return -EINVAL; | |
3552 | ||
3553 | if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE) | |
8bf1e9f1 | 3554 | return 0; |
07144428 DL |
3555 | |
3556 | /* nothing to read */ | |
d538bbdf | 3557 | spin_lock_irq(&pipe_crc->lock); |
07144428 | 3558 | while (pipe_crc_data_count(pipe_crc) == 0) { |
d538bbdf DL |
3559 | int ret; |
3560 | ||
3561 | if (filep->f_flags & O_NONBLOCK) { | |
3562 | spin_unlock_irq(&pipe_crc->lock); | |
07144428 | 3563 | return -EAGAIN; |
d538bbdf | 3564 | } |
07144428 | 3565 | |
d538bbdf DL |
3566 | ret = wait_event_interruptible_lock_irq(pipe_crc->wq, |
3567 | pipe_crc_data_count(pipe_crc), pipe_crc->lock); | |
3568 | if (ret) { | |
3569 | spin_unlock_irq(&pipe_crc->lock); | |
3570 | return ret; | |
3571 | } | |
8bf1e9f1 SH |
3572 | } |
3573 | ||
07144428 | 3574 | /* We now have one or more entries to read */ |
9ad6d99f | 3575 | n_entries = count / PIPE_CRC_LINE_LEN; |
d538bbdf | 3576 | |
07144428 | 3577 | bytes_read = 0; |
9ad6d99f VS |
3578 | while (n_entries > 0) { |
3579 | struct intel_pipe_crc_entry *entry = | |
3580 | &pipe_crc->entries[pipe_crc->tail]; | |
07144428 | 3581 | int ret; |
8bf1e9f1 | 3582 | |
9ad6d99f VS |
3583 | if (CIRC_CNT(pipe_crc->head, pipe_crc->tail, |
3584 | INTEL_PIPE_CRC_ENTRIES_NR) < 1) | |
3585 | break; | |
3586 | ||
3587 | BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR); | |
3588 | pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
3589 | ||
07144428 DL |
3590 | bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN, |
3591 | "%8u %8x %8x %8x %8x %8x\n", | |
3592 | entry->frame, entry->crc[0], | |
3593 | entry->crc[1], entry->crc[2], | |
3594 | entry->crc[3], entry->crc[4]); | |
3595 | ||
9ad6d99f VS |
3596 | spin_unlock_irq(&pipe_crc->lock); |
3597 | ||
3598 | ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN); | |
07144428 DL |
3599 | if (ret == PIPE_CRC_LINE_LEN) |
3600 | return -EFAULT; | |
b2c88f5b | 3601 | |
9ad6d99f VS |
3602 | user_buf += PIPE_CRC_LINE_LEN; |
3603 | n_entries--; | |
3604 | ||
3605 | spin_lock_irq(&pipe_crc->lock); | |
3606 | } | |
8bf1e9f1 | 3607 | |
d538bbdf DL |
3608 | spin_unlock_irq(&pipe_crc->lock); |
3609 | ||
07144428 DL |
3610 | return bytes_read; |
3611 | } | |
3612 | ||
3613 | static const struct file_operations i915_pipe_crc_fops = { | |
3614 | .owner = THIS_MODULE, | |
3615 | .open = i915_pipe_crc_open, | |
3616 | .read = i915_pipe_crc_read, | |
3617 | .release = i915_pipe_crc_release, | |
3618 | }; | |
3619 | ||
3620 | static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = { | |
3621 | { | |
3622 | .name = "i915_pipe_A_crc", | |
3623 | .pipe = PIPE_A, | |
3624 | }, | |
3625 | { | |
3626 | .name = "i915_pipe_B_crc", | |
3627 | .pipe = PIPE_B, | |
3628 | }, | |
3629 | { | |
3630 | .name = "i915_pipe_C_crc", | |
3631 | .pipe = PIPE_C, | |
3632 | }, | |
3633 | }; | |
3634 | ||
3635 | static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor, | |
3636 | enum pipe pipe) | |
3637 | { | |
3638 | struct drm_device *dev = minor->dev; | |
3639 | struct dentry *ent; | |
3640 | struct pipe_crc_info *info = &i915_pipe_crc_data[pipe]; | |
3641 | ||
3642 | info->dev = dev; | |
3643 | ent = debugfs_create_file(info->name, S_IRUGO, root, info, | |
3644 | &i915_pipe_crc_fops); | |
f3c5fe97 WY |
3645 | if (!ent) |
3646 | return -ENOMEM; | |
07144428 DL |
3647 | |
3648 | return drm_add_fake_info_node(minor, ent, info); | |
8bf1e9f1 SH |
3649 | } |
3650 | ||
e8dfcf78 | 3651 | static const char * const pipe_crc_sources[] = { |
926321d5 DV |
3652 | "none", |
3653 | "plane1", | |
3654 | "plane2", | |
3655 | "pf", | |
5b3a856b | 3656 | "pipe", |
3d099a05 DV |
3657 | "TV", |
3658 | "DP-B", | |
3659 | "DP-C", | |
3660 | "DP-D", | |
46a19188 | 3661 | "auto", |
926321d5 DV |
3662 | }; |
3663 | ||
3664 | static const char *pipe_crc_source_name(enum intel_pipe_crc_source source) | |
3665 | { | |
3666 | BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX); | |
3667 | return pipe_crc_sources[source]; | |
3668 | } | |
3669 | ||
bd9db02f | 3670 | static int display_crc_ctl_show(struct seq_file *m, void *data) |
926321d5 DV |
3671 | { |
3672 | struct drm_device *dev = m->private; | |
3673 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3674 | int i; | |
3675 | ||
3676 | for (i = 0; i < I915_MAX_PIPES; i++) | |
3677 | seq_printf(m, "%c %s\n", pipe_name(i), | |
3678 | pipe_crc_source_name(dev_priv->pipe_crc[i].source)); | |
3679 | ||
3680 | return 0; | |
3681 | } | |
3682 | ||
bd9db02f | 3683 | static int display_crc_ctl_open(struct inode *inode, struct file *file) |
926321d5 DV |
3684 | { |
3685 | struct drm_device *dev = inode->i_private; | |
3686 | ||
bd9db02f | 3687 | return single_open(file, display_crc_ctl_show, dev); |
926321d5 DV |
3688 | } |
3689 | ||
46a19188 | 3690 | static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
52f843f6 DV |
3691 | uint32_t *val) |
3692 | { | |
46a19188 DV |
3693 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
3694 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3695 | ||
3696 | switch (*source) { | |
52f843f6 DV |
3697 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3698 | *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; | |
3699 | break; | |
3700 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
3701 | *val = 0; | |
3702 | break; | |
3703 | default: | |
3704 | return -EINVAL; | |
3705 | } | |
3706 | ||
3707 | return 0; | |
3708 | } | |
3709 | ||
46a19188 DV |
3710 | static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe, |
3711 | enum intel_pipe_crc_source *source) | |
3712 | { | |
3713 | struct intel_encoder *encoder; | |
3714 | struct intel_crtc *crtc; | |
26756809 | 3715 | struct intel_digital_port *dig_port; |
46a19188 DV |
3716 | int ret = 0; |
3717 | ||
3718 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3719 | ||
6e9f798d | 3720 | drm_modeset_lock_all(dev); |
b2784e15 | 3721 | for_each_intel_encoder(dev, encoder) { |
46a19188 DV |
3722 | if (!encoder->base.crtc) |
3723 | continue; | |
3724 | ||
3725 | crtc = to_intel_crtc(encoder->base.crtc); | |
3726 | ||
3727 | if (crtc->pipe != pipe) | |
3728 | continue; | |
3729 | ||
3730 | switch (encoder->type) { | |
3731 | case INTEL_OUTPUT_TVOUT: | |
3732 | *source = INTEL_PIPE_CRC_SOURCE_TV; | |
3733 | break; | |
3734 | case INTEL_OUTPUT_DISPLAYPORT: | |
3735 | case INTEL_OUTPUT_EDP: | |
26756809 DV |
3736 | dig_port = enc_to_dig_port(&encoder->base); |
3737 | switch (dig_port->port) { | |
3738 | case PORT_B: | |
3739 | *source = INTEL_PIPE_CRC_SOURCE_DP_B; | |
3740 | break; | |
3741 | case PORT_C: | |
3742 | *source = INTEL_PIPE_CRC_SOURCE_DP_C; | |
3743 | break; | |
3744 | case PORT_D: | |
3745 | *source = INTEL_PIPE_CRC_SOURCE_DP_D; | |
3746 | break; | |
3747 | default: | |
3748 | WARN(1, "nonexisting DP port %c\n", | |
3749 | port_name(dig_port->port)); | |
3750 | break; | |
3751 | } | |
46a19188 | 3752 | break; |
6847d71b PZ |
3753 | default: |
3754 | break; | |
46a19188 DV |
3755 | } |
3756 | } | |
6e9f798d | 3757 | drm_modeset_unlock_all(dev); |
46a19188 DV |
3758 | |
3759 | return ret; | |
3760 | } | |
3761 | ||
3762 | static int vlv_pipe_crc_ctl_reg(struct drm_device *dev, | |
3763 | enum pipe pipe, | |
3764 | enum intel_pipe_crc_source *source, | |
7ac0129b DV |
3765 | uint32_t *val) |
3766 | { | |
8d2f24ca DV |
3767 | struct drm_i915_private *dev_priv = dev->dev_private; |
3768 | bool need_stable_symbols = false; | |
3769 | ||
46a19188 DV |
3770 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
3771 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); | |
3772 | if (ret) | |
3773 | return ret; | |
3774 | } | |
3775 | ||
3776 | switch (*source) { | |
7ac0129b DV |
3777 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3778 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; | |
3779 | break; | |
3780 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
3781 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; | |
8d2f24ca | 3782 | need_stable_symbols = true; |
7ac0129b DV |
3783 | break; |
3784 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
3785 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; | |
8d2f24ca | 3786 | need_stable_symbols = true; |
7ac0129b | 3787 | break; |
2be57922 VS |
3788 | case INTEL_PIPE_CRC_SOURCE_DP_D: |
3789 | if (!IS_CHERRYVIEW(dev)) | |
3790 | return -EINVAL; | |
3791 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV; | |
3792 | need_stable_symbols = true; | |
3793 | break; | |
7ac0129b DV |
3794 | case INTEL_PIPE_CRC_SOURCE_NONE: |
3795 | *val = 0; | |
3796 | break; | |
3797 | default: | |
3798 | return -EINVAL; | |
3799 | } | |
3800 | ||
8d2f24ca DV |
3801 | /* |
3802 | * When the pipe CRC tap point is after the transcoders we need | |
3803 | * to tweak symbol-level features to produce a deterministic series of | |
3804 | * symbols for a given frame. We need to reset those features only once | |
3805 | * a frame (instead of every nth symbol): | |
3806 | * - DC-balance: used to ensure a better clock recovery from the data | |
3807 | * link (SDVO) | |
3808 | * - DisplayPort scrambling: used for EMI reduction | |
3809 | */ | |
3810 | if (need_stable_symbols) { | |
3811 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3812 | ||
8d2f24ca | 3813 | tmp |= DC_BALANCE_RESET_VLV; |
eb736679 VS |
3814 | switch (pipe) { |
3815 | case PIPE_A: | |
8d2f24ca | 3816 | tmp |= PIPE_A_SCRAMBLE_RESET; |
eb736679 VS |
3817 | break; |
3818 | case PIPE_B: | |
8d2f24ca | 3819 | tmp |= PIPE_B_SCRAMBLE_RESET; |
eb736679 VS |
3820 | break; |
3821 | case PIPE_C: | |
3822 | tmp |= PIPE_C_SCRAMBLE_RESET; | |
3823 | break; | |
3824 | default: | |
3825 | return -EINVAL; | |
3826 | } | |
8d2f24ca DV |
3827 | I915_WRITE(PORT_DFT2_G4X, tmp); |
3828 | } | |
3829 | ||
7ac0129b DV |
3830 | return 0; |
3831 | } | |
3832 | ||
4b79ebf7 | 3833 | static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev, |
46a19188 DV |
3834 | enum pipe pipe, |
3835 | enum intel_pipe_crc_source *source, | |
4b79ebf7 DV |
3836 | uint32_t *val) |
3837 | { | |
84093603 DV |
3838 | struct drm_i915_private *dev_priv = dev->dev_private; |
3839 | bool need_stable_symbols = false; | |
3840 | ||
46a19188 DV |
3841 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
3842 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); | |
3843 | if (ret) | |
3844 | return ret; | |
3845 | } | |
3846 | ||
3847 | switch (*source) { | |
4b79ebf7 DV |
3848 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3849 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; | |
3850 | break; | |
3851 | case INTEL_PIPE_CRC_SOURCE_TV: | |
3852 | if (!SUPPORTS_TV(dev)) | |
3853 | return -EINVAL; | |
3854 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; | |
3855 | break; | |
3856 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
3857 | if (!IS_G4X(dev)) | |
3858 | return -EINVAL; | |
3859 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X; | |
84093603 | 3860 | need_stable_symbols = true; |
4b79ebf7 DV |
3861 | break; |
3862 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
3863 | if (!IS_G4X(dev)) | |
3864 | return -EINVAL; | |
3865 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X; | |
84093603 | 3866 | need_stable_symbols = true; |
4b79ebf7 DV |
3867 | break; |
3868 | case INTEL_PIPE_CRC_SOURCE_DP_D: | |
3869 | if (!IS_G4X(dev)) | |
3870 | return -EINVAL; | |
3871 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X; | |
84093603 | 3872 | need_stable_symbols = true; |
4b79ebf7 DV |
3873 | break; |
3874 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
3875 | *val = 0; | |
3876 | break; | |
3877 | default: | |
3878 | return -EINVAL; | |
3879 | } | |
3880 | ||
84093603 DV |
3881 | /* |
3882 | * When the pipe CRC tap point is after the transcoders we need | |
3883 | * to tweak symbol-level features to produce a deterministic series of | |
3884 | * symbols for a given frame. We need to reset those features only once | |
3885 | * a frame (instead of every nth symbol): | |
3886 | * - DC-balance: used to ensure a better clock recovery from the data | |
3887 | * link (SDVO) | |
3888 | * - DisplayPort scrambling: used for EMI reduction | |
3889 | */ | |
3890 | if (need_stable_symbols) { | |
3891 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3892 | ||
3893 | WARN_ON(!IS_G4X(dev)); | |
3894 | ||
3895 | I915_WRITE(PORT_DFT_I9XX, | |
3896 | I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET); | |
3897 | ||
3898 | if (pipe == PIPE_A) | |
3899 | tmp |= PIPE_A_SCRAMBLE_RESET; | |
3900 | else | |
3901 | tmp |= PIPE_B_SCRAMBLE_RESET; | |
3902 | ||
3903 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
3904 | } | |
3905 | ||
4b79ebf7 DV |
3906 | return 0; |
3907 | } | |
3908 | ||
8d2f24ca DV |
3909 | static void vlv_undo_pipe_scramble_reset(struct drm_device *dev, |
3910 | enum pipe pipe) | |
3911 | { | |
3912 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3913 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3914 | ||
eb736679 VS |
3915 | switch (pipe) { |
3916 | case PIPE_A: | |
8d2f24ca | 3917 | tmp &= ~PIPE_A_SCRAMBLE_RESET; |
eb736679 VS |
3918 | break; |
3919 | case PIPE_B: | |
8d2f24ca | 3920 | tmp &= ~PIPE_B_SCRAMBLE_RESET; |
eb736679 VS |
3921 | break; |
3922 | case PIPE_C: | |
3923 | tmp &= ~PIPE_C_SCRAMBLE_RESET; | |
3924 | break; | |
3925 | default: | |
3926 | return; | |
3927 | } | |
8d2f24ca DV |
3928 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) |
3929 | tmp &= ~DC_BALANCE_RESET_VLV; | |
3930 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
3931 | ||
3932 | } | |
3933 | ||
84093603 DV |
3934 | static void g4x_undo_pipe_scramble_reset(struct drm_device *dev, |
3935 | enum pipe pipe) | |
3936 | { | |
3937 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3938 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3939 | ||
3940 | if (pipe == PIPE_A) | |
3941 | tmp &= ~PIPE_A_SCRAMBLE_RESET; | |
3942 | else | |
3943 | tmp &= ~PIPE_B_SCRAMBLE_RESET; | |
3944 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
3945 | ||
3946 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) { | |
3947 | I915_WRITE(PORT_DFT_I9XX, | |
3948 | I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET); | |
3949 | } | |
3950 | } | |
3951 | ||
46a19188 | 3952 | static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
5b3a856b DV |
3953 | uint32_t *val) |
3954 | { | |
46a19188 DV |
3955 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
3956 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3957 | ||
3958 | switch (*source) { | |
5b3a856b DV |
3959 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
3960 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; | |
3961 | break; | |
3962 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
3963 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; | |
3964 | break; | |
5b3a856b DV |
3965 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3966 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; | |
3967 | break; | |
3d099a05 | 3968 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
3969 | *val = 0; |
3970 | break; | |
3d099a05 DV |
3971 | default: |
3972 | return -EINVAL; | |
5b3a856b DV |
3973 | } |
3974 | ||
3975 | return 0; | |
3976 | } | |
3977 | ||
c4e2d043 | 3978 | static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable) |
fabf6e51 DV |
3979 | { |
3980 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3981 | struct intel_crtc *crtc = | |
3982 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]); | |
f77076c9 | 3983 | struct intel_crtc_state *pipe_config; |
c4e2d043 ML |
3984 | struct drm_atomic_state *state; |
3985 | int ret = 0; | |
fabf6e51 DV |
3986 | |
3987 | drm_modeset_lock_all(dev); | |
c4e2d043 ML |
3988 | state = drm_atomic_state_alloc(dev); |
3989 | if (!state) { | |
3990 | ret = -ENOMEM; | |
3991 | goto out; | |
fabf6e51 | 3992 | } |
fabf6e51 | 3993 | |
c4e2d043 ML |
3994 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base); |
3995 | pipe_config = intel_atomic_get_crtc_state(state, crtc); | |
3996 | if (IS_ERR(pipe_config)) { | |
3997 | ret = PTR_ERR(pipe_config); | |
3998 | goto out; | |
3999 | } | |
fabf6e51 | 4000 | |
c4e2d043 ML |
4001 | pipe_config->pch_pfit.force_thru = enable; |
4002 | if (pipe_config->cpu_transcoder == TRANSCODER_EDP && | |
4003 | pipe_config->pch_pfit.enabled != enable) | |
4004 | pipe_config->base.connectors_changed = true; | |
1b509259 | 4005 | |
c4e2d043 ML |
4006 | ret = drm_atomic_commit(state); |
4007 | out: | |
fabf6e51 | 4008 | drm_modeset_unlock_all(dev); |
c4e2d043 ML |
4009 | WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret); |
4010 | if (ret) | |
4011 | drm_atomic_state_free(state); | |
fabf6e51 DV |
4012 | } |
4013 | ||
4014 | static int ivb_pipe_crc_ctl_reg(struct drm_device *dev, | |
4015 | enum pipe pipe, | |
4016 | enum intel_pipe_crc_source *source, | |
5b3a856b DV |
4017 | uint32_t *val) |
4018 | { | |
46a19188 DV |
4019 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
4020 | *source = INTEL_PIPE_CRC_SOURCE_PF; | |
4021 | ||
4022 | switch (*source) { | |
5b3a856b DV |
4023 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
4024 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; | |
4025 | break; | |
4026 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
4027 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; | |
4028 | break; | |
4029 | case INTEL_PIPE_CRC_SOURCE_PF: | |
fabf6e51 | 4030 | if (IS_HASWELL(dev) && pipe == PIPE_A) |
c4e2d043 | 4031 | hsw_trans_edp_pipe_A_crc_wa(dev, true); |
fabf6e51 | 4032 | |
5b3a856b DV |
4033 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; |
4034 | break; | |
3d099a05 | 4035 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
4036 | *val = 0; |
4037 | break; | |
3d099a05 DV |
4038 | default: |
4039 | return -EINVAL; | |
5b3a856b DV |
4040 | } |
4041 | ||
4042 | return 0; | |
4043 | } | |
4044 | ||
926321d5 DV |
4045 | static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, |
4046 | enum intel_pipe_crc_source source) | |
4047 | { | |
4048 | struct drm_i915_private *dev_priv = dev->dev_private; | |
cc3da175 | 4049 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
8c740dce PZ |
4050 | struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, |
4051 | pipe)); | |
e129649b | 4052 | enum intel_display_power_domain power_domain; |
432f3342 | 4053 | u32 val = 0; /* shut up gcc */ |
5b3a856b | 4054 | int ret; |
926321d5 | 4055 | |
cc3da175 DL |
4056 | if (pipe_crc->source == source) |
4057 | return 0; | |
4058 | ||
ae676fcd DL |
4059 | /* forbid changing the source without going back to 'none' */ |
4060 | if (pipe_crc->source && source) | |
4061 | return -EINVAL; | |
4062 | ||
e129649b ID |
4063 | power_domain = POWER_DOMAIN_PIPE(pipe); |
4064 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
9d8b0588 DV |
4065 | DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n"); |
4066 | return -EIO; | |
4067 | } | |
4068 | ||
52f843f6 | 4069 | if (IS_GEN2(dev)) |
46a19188 | 4070 | ret = i8xx_pipe_crc_ctl_reg(&source, &val); |
52f843f6 | 4071 | else if (INTEL_INFO(dev)->gen < 5) |
46a19188 | 4072 | ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
666a4537 | 4073 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
fabf6e51 | 4074 | ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
4b79ebf7 | 4075 | else if (IS_GEN5(dev) || IS_GEN6(dev)) |
46a19188 | 4076 | ret = ilk_pipe_crc_ctl_reg(&source, &val); |
5b3a856b | 4077 | else |
fabf6e51 | 4078 | ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
5b3a856b DV |
4079 | |
4080 | if (ret != 0) | |
e129649b | 4081 | goto out; |
5b3a856b | 4082 | |
4b584369 DL |
4083 | /* none -> real source transition */ |
4084 | if (source) { | |
4252fbc3 VS |
4085 | struct intel_pipe_crc_entry *entries; |
4086 | ||
7cd6ccff DL |
4087 | DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n", |
4088 | pipe_name(pipe), pipe_crc_source_name(source)); | |
4089 | ||
3cf54b34 VS |
4090 | entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR, |
4091 | sizeof(pipe_crc->entries[0]), | |
4252fbc3 | 4092 | GFP_KERNEL); |
e129649b ID |
4093 | if (!entries) { |
4094 | ret = -ENOMEM; | |
4095 | goto out; | |
4096 | } | |
e5f75aca | 4097 | |
8c740dce PZ |
4098 | /* |
4099 | * When IPS gets enabled, the pipe CRC changes. Since IPS gets | |
4100 | * enabled and disabled dynamically based on package C states, | |
4101 | * user space can't make reliable use of the CRCs, so let's just | |
4102 | * completely disable it. | |
4103 | */ | |
4104 | hsw_disable_ips(crtc); | |
4105 | ||
d538bbdf | 4106 | spin_lock_irq(&pipe_crc->lock); |
64387b61 | 4107 | kfree(pipe_crc->entries); |
4252fbc3 | 4108 | pipe_crc->entries = entries; |
d538bbdf DL |
4109 | pipe_crc->head = 0; |
4110 | pipe_crc->tail = 0; | |
4111 | spin_unlock_irq(&pipe_crc->lock); | |
4b584369 DL |
4112 | } |
4113 | ||
cc3da175 | 4114 | pipe_crc->source = source; |
926321d5 | 4115 | |
926321d5 DV |
4116 | I915_WRITE(PIPE_CRC_CTL(pipe), val); |
4117 | POSTING_READ(PIPE_CRC_CTL(pipe)); | |
4118 | ||
e5f75aca DL |
4119 | /* real source -> none transition */ |
4120 | if (source == INTEL_PIPE_CRC_SOURCE_NONE) { | |
d538bbdf | 4121 | struct intel_pipe_crc_entry *entries; |
a33d7105 DV |
4122 | struct intel_crtc *crtc = |
4123 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
d538bbdf | 4124 | |
7cd6ccff DL |
4125 | DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n", |
4126 | pipe_name(pipe)); | |
4127 | ||
a33d7105 | 4128 | drm_modeset_lock(&crtc->base.mutex, NULL); |
f77076c9 | 4129 | if (crtc->base.state->active) |
a33d7105 DV |
4130 | intel_wait_for_vblank(dev, pipe); |
4131 | drm_modeset_unlock(&crtc->base.mutex); | |
bcf17ab2 | 4132 | |
d538bbdf DL |
4133 | spin_lock_irq(&pipe_crc->lock); |
4134 | entries = pipe_crc->entries; | |
e5f75aca | 4135 | pipe_crc->entries = NULL; |
9ad6d99f VS |
4136 | pipe_crc->head = 0; |
4137 | pipe_crc->tail = 0; | |
d538bbdf DL |
4138 | spin_unlock_irq(&pipe_crc->lock); |
4139 | ||
4140 | kfree(entries); | |
84093603 DV |
4141 | |
4142 | if (IS_G4X(dev)) | |
4143 | g4x_undo_pipe_scramble_reset(dev, pipe); | |
666a4537 | 4144 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
8d2f24ca | 4145 | vlv_undo_pipe_scramble_reset(dev, pipe); |
fabf6e51 | 4146 | else if (IS_HASWELL(dev) && pipe == PIPE_A) |
c4e2d043 | 4147 | hsw_trans_edp_pipe_A_crc_wa(dev, false); |
8c740dce PZ |
4148 | |
4149 | hsw_enable_ips(crtc); | |
e5f75aca DL |
4150 | } |
4151 | ||
e129649b ID |
4152 | ret = 0; |
4153 | ||
4154 | out: | |
4155 | intel_display_power_put(dev_priv, power_domain); | |
4156 | ||
4157 | return ret; | |
926321d5 DV |
4158 | } |
4159 | ||
4160 | /* | |
4161 | * Parse pipe CRC command strings: | |
b94dec87 DL |
4162 | * command: wsp* object wsp+ name wsp+ source wsp* |
4163 | * object: 'pipe' | |
4164 | * name: (A | B | C) | |
926321d5 DV |
4165 | * source: (none | plane1 | plane2 | pf) |
4166 | * wsp: (#0x20 | #0x9 | #0xA)+ | |
4167 | * | |
4168 | * eg.: | |
b94dec87 DL |
4169 | * "pipe A plane1" -> Start CRC computations on plane1 of pipe A |
4170 | * "pipe A none" -> Stop CRC | |
926321d5 | 4171 | */ |
bd9db02f | 4172 | static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words) |
926321d5 DV |
4173 | { |
4174 | int n_words = 0; | |
4175 | ||
4176 | while (*buf) { | |
4177 | char *end; | |
4178 | ||
4179 | /* skip leading white space */ | |
4180 | buf = skip_spaces(buf); | |
4181 | if (!*buf) | |
4182 | break; /* end of buffer */ | |
4183 | ||
4184 | /* find end of word */ | |
4185 | for (end = buf; *end && !isspace(*end); end++) | |
4186 | ; | |
4187 | ||
4188 | if (n_words == max_words) { | |
4189 | DRM_DEBUG_DRIVER("too many words, allowed <= %d\n", | |
4190 | max_words); | |
4191 | return -EINVAL; /* ran out of words[] before bytes */ | |
4192 | } | |
4193 | ||
4194 | if (*end) | |
4195 | *end++ = '\0'; | |
4196 | words[n_words++] = buf; | |
4197 | buf = end; | |
4198 | } | |
4199 | ||
4200 | return n_words; | |
4201 | } | |
4202 | ||
b94dec87 DL |
4203 | enum intel_pipe_crc_object { |
4204 | PIPE_CRC_OBJECT_PIPE, | |
4205 | }; | |
4206 | ||
e8dfcf78 | 4207 | static const char * const pipe_crc_objects[] = { |
b94dec87 DL |
4208 | "pipe", |
4209 | }; | |
4210 | ||
4211 | static int | |
bd9db02f | 4212 | display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o) |
b94dec87 DL |
4213 | { |
4214 | int i; | |
4215 | ||
4216 | for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++) | |
4217 | if (!strcmp(buf, pipe_crc_objects[i])) { | |
bd9db02f | 4218 | *o = i; |
b94dec87 DL |
4219 | return 0; |
4220 | } | |
4221 | ||
4222 | return -EINVAL; | |
4223 | } | |
4224 | ||
bd9db02f | 4225 | static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe) |
926321d5 DV |
4226 | { |
4227 | const char name = buf[0]; | |
4228 | ||
4229 | if (name < 'A' || name >= pipe_name(I915_MAX_PIPES)) | |
4230 | return -EINVAL; | |
4231 | ||
4232 | *pipe = name - 'A'; | |
4233 | ||
4234 | return 0; | |
4235 | } | |
4236 | ||
4237 | static int | |
bd9db02f | 4238 | display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) |
926321d5 DV |
4239 | { |
4240 | int i; | |
4241 | ||
4242 | for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++) | |
4243 | if (!strcmp(buf, pipe_crc_sources[i])) { | |
bd9db02f | 4244 | *s = i; |
926321d5 DV |
4245 | return 0; |
4246 | } | |
4247 | ||
4248 | return -EINVAL; | |
4249 | } | |
4250 | ||
bd9db02f | 4251 | static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len) |
926321d5 | 4252 | { |
b94dec87 | 4253 | #define N_WORDS 3 |
926321d5 | 4254 | int n_words; |
b94dec87 | 4255 | char *words[N_WORDS]; |
926321d5 | 4256 | enum pipe pipe; |
b94dec87 | 4257 | enum intel_pipe_crc_object object; |
926321d5 DV |
4258 | enum intel_pipe_crc_source source; |
4259 | ||
bd9db02f | 4260 | n_words = display_crc_ctl_tokenize(buf, words, N_WORDS); |
b94dec87 DL |
4261 | if (n_words != N_WORDS) { |
4262 | DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n", | |
4263 | N_WORDS); | |
4264 | return -EINVAL; | |
4265 | } | |
4266 | ||
bd9db02f | 4267 | if (display_crc_ctl_parse_object(words[0], &object) < 0) { |
b94dec87 | 4268 | DRM_DEBUG_DRIVER("unknown object %s\n", words[0]); |
926321d5 DV |
4269 | return -EINVAL; |
4270 | } | |
4271 | ||
bd9db02f | 4272 | if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) { |
b94dec87 | 4273 | DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]); |
926321d5 DV |
4274 | return -EINVAL; |
4275 | } | |
4276 | ||
bd9db02f | 4277 | if (display_crc_ctl_parse_source(words[2], &source) < 0) { |
b94dec87 | 4278 | DRM_DEBUG_DRIVER("unknown source %s\n", words[2]); |
926321d5 DV |
4279 | return -EINVAL; |
4280 | } | |
4281 | ||
4282 | return pipe_crc_set_source(dev, pipe, source); | |
4283 | } | |
4284 | ||
bd9db02f DL |
4285 | static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf, |
4286 | size_t len, loff_t *offp) | |
926321d5 DV |
4287 | { |
4288 | struct seq_file *m = file->private_data; | |
4289 | struct drm_device *dev = m->private; | |
4290 | char *tmpbuf; | |
4291 | int ret; | |
4292 | ||
4293 | if (len == 0) | |
4294 | return 0; | |
4295 | ||
4296 | if (len > PAGE_SIZE - 1) { | |
4297 | DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n", | |
4298 | PAGE_SIZE); | |
4299 | return -E2BIG; | |
4300 | } | |
4301 | ||
4302 | tmpbuf = kmalloc(len + 1, GFP_KERNEL); | |
4303 | if (!tmpbuf) | |
4304 | return -ENOMEM; | |
4305 | ||
4306 | if (copy_from_user(tmpbuf, ubuf, len)) { | |
4307 | ret = -EFAULT; | |
4308 | goto out; | |
4309 | } | |
4310 | tmpbuf[len] = '\0'; | |
4311 | ||
bd9db02f | 4312 | ret = display_crc_ctl_parse(dev, tmpbuf, len); |
926321d5 DV |
4313 | |
4314 | out: | |
4315 | kfree(tmpbuf); | |
4316 | if (ret < 0) | |
4317 | return ret; | |
4318 | ||
4319 | *offp += len; | |
4320 | return len; | |
4321 | } | |
4322 | ||
bd9db02f | 4323 | static const struct file_operations i915_display_crc_ctl_fops = { |
926321d5 | 4324 | .owner = THIS_MODULE, |
bd9db02f | 4325 | .open = display_crc_ctl_open, |
926321d5 DV |
4326 | .read = seq_read, |
4327 | .llseek = seq_lseek, | |
4328 | .release = single_release, | |
bd9db02f | 4329 | .write = display_crc_ctl_write |
926321d5 DV |
4330 | }; |
4331 | ||
eb3394fa TP |
4332 | static ssize_t i915_displayport_test_active_write(struct file *file, |
4333 | const char __user *ubuf, | |
4334 | size_t len, loff_t *offp) | |
4335 | { | |
4336 | char *input_buffer; | |
4337 | int status = 0; | |
eb3394fa TP |
4338 | struct drm_device *dev; |
4339 | struct drm_connector *connector; | |
4340 | struct list_head *connector_list; | |
4341 | struct intel_dp *intel_dp; | |
4342 | int val = 0; | |
4343 | ||
9aaffa34 | 4344 | dev = ((struct seq_file *)file->private_data)->private; |
eb3394fa | 4345 | |
eb3394fa TP |
4346 | connector_list = &dev->mode_config.connector_list; |
4347 | ||
4348 | if (len == 0) | |
4349 | return 0; | |
4350 | ||
4351 | input_buffer = kmalloc(len + 1, GFP_KERNEL); | |
4352 | if (!input_buffer) | |
4353 | return -ENOMEM; | |
4354 | ||
4355 | if (copy_from_user(input_buffer, ubuf, len)) { | |
4356 | status = -EFAULT; | |
4357 | goto out; | |
4358 | } | |
4359 | ||
4360 | input_buffer[len] = '\0'; | |
4361 | DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len); | |
4362 | ||
4363 | list_for_each_entry(connector, connector_list, head) { | |
4364 | ||
4365 | if (connector->connector_type != | |
4366 | DRM_MODE_CONNECTOR_DisplayPort) | |
4367 | continue; | |
4368 | ||
b8bb08ec | 4369 | if (connector->status == connector_status_connected && |
eb3394fa TP |
4370 | connector->encoder != NULL) { |
4371 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4372 | status = kstrtoint(input_buffer, 10, &val); | |
4373 | if (status < 0) | |
4374 | goto out; | |
4375 | DRM_DEBUG_DRIVER("Got %d for test active\n", val); | |
4376 | /* To prevent erroneous activation of the compliance | |
4377 | * testing code, only accept an actual value of 1 here | |
4378 | */ | |
4379 | if (val == 1) | |
4380 | intel_dp->compliance_test_active = 1; | |
4381 | else | |
4382 | intel_dp->compliance_test_active = 0; | |
4383 | } | |
4384 | } | |
4385 | out: | |
4386 | kfree(input_buffer); | |
4387 | if (status < 0) | |
4388 | return status; | |
4389 | ||
4390 | *offp += len; | |
4391 | return len; | |
4392 | } | |
4393 | ||
4394 | static int i915_displayport_test_active_show(struct seq_file *m, void *data) | |
4395 | { | |
4396 | struct drm_device *dev = m->private; | |
4397 | struct drm_connector *connector; | |
4398 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
4399 | struct intel_dp *intel_dp; | |
4400 | ||
eb3394fa TP |
4401 | list_for_each_entry(connector, connector_list, head) { |
4402 | ||
4403 | if (connector->connector_type != | |
4404 | DRM_MODE_CONNECTOR_DisplayPort) | |
4405 | continue; | |
4406 | ||
4407 | if (connector->status == connector_status_connected && | |
4408 | connector->encoder != NULL) { | |
4409 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4410 | if (intel_dp->compliance_test_active) | |
4411 | seq_puts(m, "1"); | |
4412 | else | |
4413 | seq_puts(m, "0"); | |
4414 | } else | |
4415 | seq_puts(m, "0"); | |
4416 | } | |
4417 | ||
4418 | return 0; | |
4419 | } | |
4420 | ||
4421 | static int i915_displayport_test_active_open(struct inode *inode, | |
4422 | struct file *file) | |
4423 | { | |
4424 | struct drm_device *dev = inode->i_private; | |
4425 | ||
4426 | return single_open(file, i915_displayport_test_active_show, dev); | |
4427 | } | |
4428 | ||
4429 | static const struct file_operations i915_displayport_test_active_fops = { | |
4430 | .owner = THIS_MODULE, | |
4431 | .open = i915_displayport_test_active_open, | |
4432 | .read = seq_read, | |
4433 | .llseek = seq_lseek, | |
4434 | .release = single_release, | |
4435 | .write = i915_displayport_test_active_write | |
4436 | }; | |
4437 | ||
4438 | static int i915_displayport_test_data_show(struct seq_file *m, void *data) | |
4439 | { | |
4440 | struct drm_device *dev = m->private; | |
4441 | struct drm_connector *connector; | |
4442 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
4443 | struct intel_dp *intel_dp; | |
4444 | ||
eb3394fa TP |
4445 | list_for_each_entry(connector, connector_list, head) { |
4446 | ||
4447 | if (connector->connector_type != | |
4448 | DRM_MODE_CONNECTOR_DisplayPort) | |
4449 | continue; | |
4450 | ||
4451 | if (connector->status == connector_status_connected && | |
4452 | connector->encoder != NULL) { | |
4453 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4454 | seq_printf(m, "%lx", intel_dp->compliance_test_data); | |
4455 | } else | |
4456 | seq_puts(m, "0"); | |
4457 | } | |
4458 | ||
4459 | return 0; | |
4460 | } | |
4461 | static int i915_displayport_test_data_open(struct inode *inode, | |
4462 | struct file *file) | |
4463 | { | |
4464 | struct drm_device *dev = inode->i_private; | |
4465 | ||
4466 | return single_open(file, i915_displayport_test_data_show, dev); | |
4467 | } | |
4468 | ||
4469 | static const struct file_operations i915_displayport_test_data_fops = { | |
4470 | .owner = THIS_MODULE, | |
4471 | .open = i915_displayport_test_data_open, | |
4472 | .read = seq_read, | |
4473 | .llseek = seq_lseek, | |
4474 | .release = single_release | |
4475 | }; | |
4476 | ||
4477 | static int i915_displayport_test_type_show(struct seq_file *m, void *data) | |
4478 | { | |
4479 | struct drm_device *dev = m->private; | |
4480 | struct drm_connector *connector; | |
4481 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
4482 | struct intel_dp *intel_dp; | |
4483 | ||
eb3394fa TP |
4484 | list_for_each_entry(connector, connector_list, head) { |
4485 | ||
4486 | if (connector->connector_type != | |
4487 | DRM_MODE_CONNECTOR_DisplayPort) | |
4488 | continue; | |
4489 | ||
4490 | if (connector->status == connector_status_connected && | |
4491 | connector->encoder != NULL) { | |
4492 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4493 | seq_printf(m, "%02lx", intel_dp->compliance_test_type); | |
4494 | } else | |
4495 | seq_puts(m, "0"); | |
4496 | } | |
4497 | ||
4498 | return 0; | |
4499 | } | |
4500 | ||
4501 | static int i915_displayport_test_type_open(struct inode *inode, | |
4502 | struct file *file) | |
4503 | { | |
4504 | struct drm_device *dev = inode->i_private; | |
4505 | ||
4506 | return single_open(file, i915_displayport_test_type_show, dev); | |
4507 | } | |
4508 | ||
4509 | static const struct file_operations i915_displayport_test_type_fops = { | |
4510 | .owner = THIS_MODULE, | |
4511 | .open = i915_displayport_test_type_open, | |
4512 | .read = seq_read, | |
4513 | .llseek = seq_lseek, | |
4514 | .release = single_release | |
4515 | }; | |
4516 | ||
97e94b22 | 4517 | static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) |
369a1342 VS |
4518 | { |
4519 | struct drm_device *dev = m->private; | |
369a1342 | 4520 | int level; |
de38b95c VS |
4521 | int num_levels; |
4522 | ||
4523 | if (IS_CHERRYVIEW(dev)) | |
4524 | num_levels = 3; | |
4525 | else if (IS_VALLEYVIEW(dev)) | |
4526 | num_levels = 1; | |
4527 | else | |
4528 | num_levels = ilk_wm_max_level(dev) + 1; | |
369a1342 VS |
4529 | |
4530 | drm_modeset_lock_all(dev); | |
4531 | ||
4532 | for (level = 0; level < num_levels; level++) { | |
4533 | unsigned int latency = wm[level]; | |
4534 | ||
97e94b22 DL |
4535 | /* |
4536 | * - WM1+ latency values in 0.5us units | |
de38b95c | 4537 | * - latencies are in us on gen9/vlv/chv |
97e94b22 | 4538 | */ |
666a4537 WB |
4539 | if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) || |
4540 | IS_CHERRYVIEW(dev)) | |
97e94b22 DL |
4541 | latency *= 10; |
4542 | else if (level > 0) | |
369a1342 VS |
4543 | latency *= 5; |
4544 | ||
4545 | seq_printf(m, "WM%d %u (%u.%u usec)\n", | |
97e94b22 | 4546 | level, wm[level], latency / 10, latency % 10); |
369a1342 VS |
4547 | } |
4548 | ||
4549 | drm_modeset_unlock_all(dev); | |
4550 | } | |
4551 | ||
4552 | static int pri_wm_latency_show(struct seq_file *m, void *data) | |
4553 | { | |
4554 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4555 | struct drm_i915_private *dev_priv = dev->dev_private; |
4556 | const uint16_t *latencies; | |
4557 | ||
4558 | if (INTEL_INFO(dev)->gen >= 9) | |
4559 | latencies = dev_priv->wm.skl_latency; | |
4560 | else | |
4561 | latencies = to_i915(dev)->wm.pri_latency; | |
369a1342 | 4562 | |
97e94b22 | 4563 | wm_latency_show(m, latencies); |
369a1342 VS |
4564 | |
4565 | return 0; | |
4566 | } | |
4567 | ||
4568 | static int spr_wm_latency_show(struct seq_file *m, void *data) | |
4569 | { | |
4570 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4571 | struct drm_i915_private *dev_priv = dev->dev_private; |
4572 | const uint16_t *latencies; | |
4573 | ||
4574 | if (INTEL_INFO(dev)->gen >= 9) | |
4575 | latencies = dev_priv->wm.skl_latency; | |
4576 | else | |
4577 | latencies = to_i915(dev)->wm.spr_latency; | |
369a1342 | 4578 | |
97e94b22 | 4579 | wm_latency_show(m, latencies); |
369a1342 VS |
4580 | |
4581 | return 0; | |
4582 | } | |
4583 | ||
4584 | static int cur_wm_latency_show(struct seq_file *m, void *data) | |
4585 | { | |
4586 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4587 | struct drm_i915_private *dev_priv = dev->dev_private; |
4588 | const uint16_t *latencies; | |
4589 | ||
4590 | if (INTEL_INFO(dev)->gen >= 9) | |
4591 | latencies = dev_priv->wm.skl_latency; | |
4592 | else | |
4593 | latencies = to_i915(dev)->wm.cur_latency; | |
369a1342 | 4594 | |
97e94b22 | 4595 | wm_latency_show(m, latencies); |
369a1342 VS |
4596 | |
4597 | return 0; | |
4598 | } | |
4599 | ||
4600 | static int pri_wm_latency_open(struct inode *inode, struct file *file) | |
4601 | { | |
4602 | struct drm_device *dev = inode->i_private; | |
4603 | ||
de38b95c | 4604 | if (INTEL_INFO(dev)->gen < 5) |
369a1342 VS |
4605 | return -ENODEV; |
4606 | ||
4607 | return single_open(file, pri_wm_latency_show, dev); | |
4608 | } | |
4609 | ||
4610 | static int spr_wm_latency_open(struct inode *inode, struct file *file) | |
4611 | { | |
4612 | struct drm_device *dev = inode->i_private; | |
4613 | ||
9ad0257c | 4614 | if (HAS_GMCH_DISPLAY(dev)) |
369a1342 VS |
4615 | return -ENODEV; |
4616 | ||
4617 | return single_open(file, spr_wm_latency_show, dev); | |
4618 | } | |
4619 | ||
4620 | static int cur_wm_latency_open(struct inode *inode, struct file *file) | |
4621 | { | |
4622 | struct drm_device *dev = inode->i_private; | |
4623 | ||
9ad0257c | 4624 | if (HAS_GMCH_DISPLAY(dev)) |
369a1342 VS |
4625 | return -ENODEV; |
4626 | ||
4627 | return single_open(file, cur_wm_latency_show, dev); | |
4628 | } | |
4629 | ||
4630 | static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, | |
97e94b22 | 4631 | size_t len, loff_t *offp, uint16_t wm[8]) |
369a1342 VS |
4632 | { |
4633 | struct seq_file *m = file->private_data; | |
4634 | struct drm_device *dev = m->private; | |
97e94b22 | 4635 | uint16_t new[8] = { 0 }; |
de38b95c | 4636 | int num_levels; |
369a1342 VS |
4637 | int level; |
4638 | int ret; | |
4639 | char tmp[32]; | |
4640 | ||
de38b95c VS |
4641 | if (IS_CHERRYVIEW(dev)) |
4642 | num_levels = 3; | |
4643 | else if (IS_VALLEYVIEW(dev)) | |
4644 | num_levels = 1; | |
4645 | else | |
4646 | num_levels = ilk_wm_max_level(dev) + 1; | |
4647 | ||
369a1342 VS |
4648 | if (len >= sizeof(tmp)) |
4649 | return -EINVAL; | |
4650 | ||
4651 | if (copy_from_user(tmp, ubuf, len)) | |
4652 | return -EFAULT; | |
4653 | ||
4654 | tmp[len] = '\0'; | |
4655 | ||
97e94b22 DL |
4656 | ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu", |
4657 | &new[0], &new[1], &new[2], &new[3], | |
4658 | &new[4], &new[5], &new[6], &new[7]); | |
369a1342 VS |
4659 | if (ret != num_levels) |
4660 | return -EINVAL; | |
4661 | ||
4662 | drm_modeset_lock_all(dev); | |
4663 | ||
4664 | for (level = 0; level < num_levels; level++) | |
4665 | wm[level] = new[level]; | |
4666 | ||
4667 | drm_modeset_unlock_all(dev); | |
4668 | ||
4669 | return len; | |
4670 | } | |
4671 | ||
4672 | ||
4673 | static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, | |
4674 | size_t len, loff_t *offp) | |
4675 | { | |
4676 | struct seq_file *m = file->private_data; | |
4677 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4678 | struct drm_i915_private *dev_priv = dev->dev_private; |
4679 | uint16_t *latencies; | |
369a1342 | 4680 | |
97e94b22 DL |
4681 | if (INTEL_INFO(dev)->gen >= 9) |
4682 | latencies = dev_priv->wm.skl_latency; | |
4683 | else | |
4684 | latencies = to_i915(dev)->wm.pri_latency; | |
4685 | ||
4686 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4687 | } |
4688 | ||
4689 | static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, | |
4690 | size_t len, loff_t *offp) | |
4691 | { | |
4692 | struct seq_file *m = file->private_data; | |
4693 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4694 | struct drm_i915_private *dev_priv = dev->dev_private; |
4695 | uint16_t *latencies; | |
369a1342 | 4696 | |
97e94b22 DL |
4697 | if (INTEL_INFO(dev)->gen >= 9) |
4698 | latencies = dev_priv->wm.skl_latency; | |
4699 | else | |
4700 | latencies = to_i915(dev)->wm.spr_latency; | |
4701 | ||
4702 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4703 | } |
4704 | ||
4705 | static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, | |
4706 | size_t len, loff_t *offp) | |
4707 | { | |
4708 | struct seq_file *m = file->private_data; | |
4709 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4710 | struct drm_i915_private *dev_priv = dev->dev_private; |
4711 | uint16_t *latencies; | |
4712 | ||
4713 | if (INTEL_INFO(dev)->gen >= 9) | |
4714 | latencies = dev_priv->wm.skl_latency; | |
4715 | else | |
4716 | latencies = to_i915(dev)->wm.cur_latency; | |
369a1342 | 4717 | |
97e94b22 | 4718 | return wm_latency_write(file, ubuf, len, offp, latencies); |
369a1342 VS |
4719 | } |
4720 | ||
4721 | static const struct file_operations i915_pri_wm_latency_fops = { | |
4722 | .owner = THIS_MODULE, | |
4723 | .open = pri_wm_latency_open, | |
4724 | .read = seq_read, | |
4725 | .llseek = seq_lseek, | |
4726 | .release = single_release, | |
4727 | .write = pri_wm_latency_write | |
4728 | }; | |
4729 | ||
4730 | static const struct file_operations i915_spr_wm_latency_fops = { | |
4731 | .owner = THIS_MODULE, | |
4732 | .open = spr_wm_latency_open, | |
4733 | .read = seq_read, | |
4734 | .llseek = seq_lseek, | |
4735 | .release = single_release, | |
4736 | .write = spr_wm_latency_write | |
4737 | }; | |
4738 | ||
4739 | static const struct file_operations i915_cur_wm_latency_fops = { | |
4740 | .owner = THIS_MODULE, | |
4741 | .open = cur_wm_latency_open, | |
4742 | .read = seq_read, | |
4743 | .llseek = seq_lseek, | |
4744 | .release = single_release, | |
4745 | .write = cur_wm_latency_write | |
4746 | }; | |
4747 | ||
647416f9 KC |
4748 | static int |
4749 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 4750 | { |
647416f9 | 4751 | struct drm_device *dev = data; |
e277a1f8 | 4752 | struct drm_i915_private *dev_priv = dev->dev_private; |
f3cd474b | 4753 | |
d98c52cf | 4754 | *val = i915_terminally_wedged(&dev_priv->gpu_error); |
f3cd474b | 4755 | |
647416f9 | 4756 | return 0; |
f3cd474b CW |
4757 | } |
4758 | ||
647416f9 KC |
4759 | static int |
4760 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 4761 | { |
647416f9 | 4762 | struct drm_device *dev = data; |
d46c0517 ID |
4763 | struct drm_i915_private *dev_priv = dev->dev_private; |
4764 | ||
b8d24a06 MK |
4765 | /* |
4766 | * There is no safeguard against this debugfs entry colliding | |
4767 | * with the hangcheck calling same i915_handle_error() in | |
4768 | * parallel, causing an explosion. For now we assume that the | |
4769 | * test harness is responsible enough not to inject gpu hangs | |
4770 | * while it is writing to 'i915_wedged' | |
4771 | */ | |
4772 | ||
d98c52cf | 4773 | if (i915_reset_in_progress(&dev_priv->gpu_error)) |
b8d24a06 MK |
4774 | return -EAGAIN; |
4775 | ||
d46c0517 | 4776 | intel_runtime_pm_get(dev_priv); |
f3cd474b | 4777 | |
c033666a | 4778 | i915_handle_error(dev_priv, val, |
58174462 | 4779 | "Manually setting wedged to %llu", val); |
d46c0517 ID |
4780 | |
4781 | intel_runtime_pm_put(dev_priv); | |
4782 | ||
647416f9 | 4783 | return 0; |
f3cd474b CW |
4784 | } |
4785 | ||
647416f9 KC |
4786 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
4787 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 4788 | "%llu\n"); |
f3cd474b | 4789 | |
647416f9 KC |
4790 | static int |
4791 | i915_ring_stop_get(void *data, u64 *val) | |
e5eb3d63 | 4792 | { |
647416f9 | 4793 | struct drm_device *dev = data; |
e277a1f8 | 4794 | struct drm_i915_private *dev_priv = dev->dev_private; |
e5eb3d63 | 4795 | |
647416f9 | 4796 | *val = dev_priv->gpu_error.stop_rings; |
e5eb3d63 | 4797 | |
647416f9 | 4798 | return 0; |
e5eb3d63 DV |
4799 | } |
4800 | ||
647416f9 KC |
4801 | static int |
4802 | i915_ring_stop_set(void *data, u64 val) | |
e5eb3d63 | 4803 | { |
647416f9 | 4804 | struct drm_device *dev = data; |
e5eb3d63 | 4805 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 4806 | int ret; |
e5eb3d63 | 4807 | |
647416f9 | 4808 | DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); |
e5eb3d63 | 4809 | |
22bcfc6a DV |
4810 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
4811 | if (ret) | |
4812 | return ret; | |
4813 | ||
99584db3 | 4814 | dev_priv->gpu_error.stop_rings = val; |
e5eb3d63 DV |
4815 | mutex_unlock(&dev->struct_mutex); |
4816 | ||
647416f9 | 4817 | return 0; |
e5eb3d63 DV |
4818 | } |
4819 | ||
647416f9 KC |
4820 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, |
4821 | i915_ring_stop_get, i915_ring_stop_set, | |
4822 | "0x%08llx\n"); | |
d5442303 | 4823 | |
094f9a54 CW |
4824 | static int |
4825 | i915_ring_missed_irq_get(void *data, u64 *val) | |
4826 | { | |
4827 | struct drm_device *dev = data; | |
4828 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4829 | ||
4830 | *val = dev_priv->gpu_error.missed_irq_rings; | |
4831 | return 0; | |
4832 | } | |
4833 | ||
4834 | static int | |
4835 | i915_ring_missed_irq_set(void *data, u64 val) | |
4836 | { | |
4837 | struct drm_device *dev = data; | |
4838 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4839 | int ret; | |
4840 | ||
4841 | /* Lock against concurrent debugfs callers */ | |
4842 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4843 | if (ret) | |
4844 | return ret; | |
4845 | dev_priv->gpu_error.missed_irq_rings = val; | |
4846 | mutex_unlock(&dev->struct_mutex); | |
4847 | ||
4848 | return 0; | |
4849 | } | |
4850 | ||
4851 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
4852 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
4853 | "0x%08llx\n"); | |
4854 | ||
4855 | static int | |
4856 | i915_ring_test_irq_get(void *data, u64 *val) | |
4857 | { | |
4858 | struct drm_device *dev = data; | |
4859 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4860 | ||
4861 | *val = dev_priv->gpu_error.test_irq_rings; | |
4862 | ||
4863 | return 0; | |
4864 | } | |
4865 | ||
4866 | static int | |
4867 | i915_ring_test_irq_set(void *data, u64 val) | |
4868 | { | |
4869 | struct drm_device *dev = data; | |
4870 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4871 | int ret; | |
4872 | ||
4873 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); | |
4874 | ||
4875 | /* Lock against concurrent debugfs callers */ | |
4876 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4877 | if (ret) | |
4878 | return ret; | |
4879 | ||
4880 | dev_priv->gpu_error.test_irq_rings = val; | |
4881 | mutex_unlock(&dev->struct_mutex); | |
4882 | ||
4883 | return 0; | |
4884 | } | |
4885 | ||
4886 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
4887 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
4888 | "0x%08llx\n"); | |
4889 | ||
dd624afd CW |
4890 | #define DROP_UNBOUND 0x1 |
4891 | #define DROP_BOUND 0x2 | |
4892 | #define DROP_RETIRE 0x4 | |
4893 | #define DROP_ACTIVE 0x8 | |
4894 | #define DROP_ALL (DROP_UNBOUND | \ | |
4895 | DROP_BOUND | \ | |
4896 | DROP_RETIRE | \ | |
4897 | DROP_ACTIVE) | |
647416f9 KC |
4898 | static int |
4899 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 4900 | { |
647416f9 | 4901 | *val = DROP_ALL; |
dd624afd | 4902 | |
647416f9 | 4903 | return 0; |
dd624afd CW |
4904 | } |
4905 | ||
647416f9 KC |
4906 | static int |
4907 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 4908 | { |
647416f9 | 4909 | struct drm_device *dev = data; |
dd624afd | 4910 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 4911 | int ret; |
dd624afd | 4912 | |
2f9fe5ff | 4913 | DRM_DEBUG("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
4914 | |
4915 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
4916 | * on ioctls on -EAGAIN. */ | |
4917 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4918 | if (ret) | |
4919 | return ret; | |
4920 | ||
4921 | if (val & DROP_ACTIVE) { | |
4922 | ret = i915_gpu_idle(dev); | |
4923 | if (ret) | |
4924 | goto unlock; | |
4925 | } | |
4926 | ||
4927 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
c033666a | 4928 | i915_gem_retire_requests(dev_priv); |
dd624afd | 4929 | |
21ab4e74 CW |
4930 | if (val & DROP_BOUND) |
4931 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND); | |
4ad72b7f | 4932 | |
21ab4e74 CW |
4933 | if (val & DROP_UNBOUND) |
4934 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND); | |
dd624afd CW |
4935 | |
4936 | unlock: | |
4937 | mutex_unlock(&dev->struct_mutex); | |
4938 | ||
647416f9 | 4939 | return ret; |
dd624afd CW |
4940 | } |
4941 | ||
647416f9 KC |
4942 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
4943 | i915_drop_caches_get, i915_drop_caches_set, | |
4944 | "0x%08llx\n"); | |
dd624afd | 4945 | |
647416f9 KC |
4946 | static int |
4947 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 4948 | { |
647416f9 | 4949 | struct drm_device *dev = data; |
e277a1f8 | 4950 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 4951 | int ret; |
004777cb | 4952 | |
daa3afb2 | 4953 | if (INTEL_INFO(dev)->gen < 6) |
004777cb DV |
4954 | return -ENODEV; |
4955 | ||
5c9669ce TR |
4956 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
4957 | ||
4fc688ce | 4958 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4959 | if (ret) |
4960 | return ret; | |
358733e9 | 4961 | |
7c59a9c1 | 4962 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); |
4fc688ce | 4963 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 4964 | |
647416f9 | 4965 | return 0; |
358733e9 JB |
4966 | } |
4967 | ||
647416f9 KC |
4968 | static int |
4969 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 4970 | { |
647416f9 | 4971 | struct drm_device *dev = data; |
358733e9 | 4972 | struct drm_i915_private *dev_priv = dev->dev_private; |
bc4d91f6 | 4973 | u32 hw_max, hw_min; |
647416f9 | 4974 | int ret; |
004777cb | 4975 | |
daa3afb2 | 4976 | if (INTEL_INFO(dev)->gen < 6) |
004777cb | 4977 | return -ENODEV; |
358733e9 | 4978 | |
5c9669ce TR |
4979 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
4980 | ||
647416f9 | 4981 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 4982 | |
4fc688ce | 4983 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4984 | if (ret) |
4985 | return ret; | |
4986 | ||
358733e9 JB |
4987 | /* |
4988 | * Turbo will still be enabled, but won't go above the set value. | |
4989 | */ | |
bc4d91f6 | 4990 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4991 | |
bc4d91f6 AG |
4992 | hw_max = dev_priv->rps.max_freq; |
4993 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 4994 | |
b39fb297 | 4995 | if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) { |
dd0a1aa1 JM |
4996 | mutex_unlock(&dev_priv->rps.hw_lock); |
4997 | return -EINVAL; | |
0a073b84 JB |
4998 | } |
4999 | ||
b39fb297 | 5000 | dev_priv->rps.max_freq_softlimit = val; |
dd0a1aa1 | 5001 | |
dc97997a | 5002 | intel_set_rps(dev_priv, val); |
dd0a1aa1 | 5003 | |
4fc688ce | 5004 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 5005 | |
647416f9 | 5006 | return 0; |
358733e9 JB |
5007 | } |
5008 | ||
647416f9 KC |
5009 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
5010 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 5011 | "%llu\n"); |
358733e9 | 5012 | |
647416f9 KC |
5013 | static int |
5014 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 5015 | { |
647416f9 | 5016 | struct drm_device *dev = data; |
e277a1f8 | 5017 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 5018 | int ret; |
004777cb | 5019 | |
daa3afb2 | 5020 | if (INTEL_INFO(dev)->gen < 6) |
004777cb DV |
5021 | return -ENODEV; |
5022 | ||
5c9669ce TR |
5023 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
5024 | ||
4fc688ce | 5025 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
5026 | if (ret) |
5027 | return ret; | |
1523c310 | 5028 | |
7c59a9c1 | 5029 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); |
4fc688ce | 5030 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 5031 | |
647416f9 | 5032 | return 0; |
1523c310 JB |
5033 | } |
5034 | ||
647416f9 KC |
5035 | static int |
5036 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 5037 | { |
647416f9 | 5038 | struct drm_device *dev = data; |
1523c310 | 5039 | struct drm_i915_private *dev_priv = dev->dev_private; |
bc4d91f6 | 5040 | u32 hw_max, hw_min; |
647416f9 | 5041 | int ret; |
004777cb | 5042 | |
daa3afb2 | 5043 | if (INTEL_INFO(dev)->gen < 6) |
004777cb | 5044 | return -ENODEV; |
1523c310 | 5045 | |
5c9669ce TR |
5046 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
5047 | ||
647416f9 | 5048 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 5049 | |
4fc688ce | 5050 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
5051 | if (ret) |
5052 | return ret; | |
5053 | ||
1523c310 JB |
5054 | /* |
5055 | * Turbo will still be enabled, but won't go below the set value. | |
5056 | */ | |
bc4d91f6 | 5057 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 5058 | |
bc4d91f6 AG |
5059 | hw_max = dev_priv->rps.max_freq; |
5060 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 5061 | |
b39fb297 | 5062 | if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) { |
dd0a1aa1 JM |
5063 | mutex_unlock(&dev_priv->rps.hw_lock); |
5064 | return -EINVAL; | |
0a073b84 | 5065 | } |
dd0a1aa1 | 5066 | |
b39fb297 | 5067 | dev_priv->rps.min_freq_softlimit = val; |
dd0a1aa1 | 5068 | |
dc97997a | 5069 | intel_set_rps(dev_priv, val); |
dd0a1aa1 | 5070 | |
4fc688ce | 5071 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 5072 | |
647416f9 | 5073 | return 0; |
1523c310 JB |
5074 | } |
5075 | ||
647416f9 KC |
5076 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
5077 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 5078 | "%llu\n"); |
1523c310 | 5079 | |
647416f9 KC |
5080 | static int |
5081 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 5082 | { |
647416f9 | 5083 | struct drm_device *dev = data; |
e277a1f8 | 5084 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 5085 | u32 snpcr; |
647416f9 | 5086 | int ret; |
07b7ddd9 | 5087 | |
004777cb DV |
5088 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
5089 | return -ENODEV; | |
5090 | ||
22bcfc6a DV |
5091 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
5092 | if (ret) | |
5093 | return ret; | |
c8c8fb33 | 5094 | intel_runtime_pm_get(dev_priv); |
22bcfc6a | 5095 | |
07b7ddd9 | 5096 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
c8c8fb33 PZ |
5097 | |
5098 | intel_runtime_pm_put(dev_priv); | |
07b7ddd9 JB |
5099 | mutex_unlock(&dev_priv->dev->struct_mutex); |
5100 | ||
647416f9 | 5101 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 5102 | |
647416f9 | 5103 | return 0; |
07b7ddd9 JB |
5104 | } |
5105 | ||
647416f9 KC |
5106 | static int |
5107 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 5108 | { |
647416f9 | 5109 | struct drm_device *dev = data; |
07b7ddd9 | 5110 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 5111 | u32 snpcr; |
07b7ddd9 | 5112 | |
004777cb DV |
5113 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
5114 | return -ENODEV; | |
5115 | ||
647416f9 | 5116 | if (val > 3) |
07b7ddd9 JB |
5117 | return -EINVAL; |
5118 | ||
c8c8fb33 | 5119 | intel_runtime_pm_get(dev_priv); |
647416f9 | 5120 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
5121 | |
5122 | /* Update the cache sharing policy here as well */ | |
5123 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
5124 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
5125 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
5126 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
5127 | ||
c8c8fb33 | 5128 | intel_runtime_pm_put(dev_priv); |
647416f9 | 5129 | return 0; |
07b7ddd9 JB |
5130 | } |
5131 | ||
647416f9 KC |
5132 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
5133 | i915_cache_sharing_get, i915_cache_sharing_set, | |
5134 | "%llu\n"); | |
07b7ddd9 | 5135 | |
5d39525a JM |
5136 | struct sseu_dev_status { |
5137 | unsigned int slice_total; | |
5138 | unsigned int subslice_total; | |
5139 | unsigned int subslice_per_slice; | |
5140 | unsigned int eu_total; | |
5141 | unsigned int eu_per_subslice; | |
5142 | }; | |
5143 | ||
5144 | static void cherryview_sseu_device_status(struct drm_device *dev, | |
5145 | struct sseu_dev_status *stat) | |
5146 | { | |
5147 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0a0b457f | 5148 | int ss_max = 2; |
5d39525a JM |
5149 | int ss; |
5150 | u32 sig1[ss_max], sig2[ss_max]; | |
5151 | ||
5152 | sig1[0] = I915_READ(CHV_POWER_SS0_SIG1); | |
5153 | sig1[1] = I915_READ(CHV_POWER_SS1_SIG1); | |
5154 | sig2[0] = I915_READ(CHV_POWER_SS0_SIG2); | |
5155 | sig2[1] = I915_READ(CHV_POWER_SS1_SIG2); | |
5156 | ||
5157 | for (ss = 0; ss < ss_max; ss++) { | |
5158 | unsigned int eu_cnt; | |
5159 | ||
5160 | if (sig1[ss] & CHV_SS_PG_ENABLE) | |
5161 | /* skip disabled subslice */ | |
5162 | continue; | |
5163 | ||
5164 | stat->slice_total = 1; | |
5165 | stat->subslice_per_slice++; | |
5166 | eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) + | |
5167 | ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) + | |
5168 | ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) + | |
5169 | ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2); | |
5170 | stat->eu_total += eu_cnt; | |
5171 | stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt); | |
5172 | } | |
5173 | stat->subslice_total = stat->subslice_per_slice; | |
5174 | } | |
5175 | ||
5176 | static void gen9_sseu_device_status(struct drm_device *dev, | |
5177 | struct sseu_dev_status *stat) | |
5178 | { | |
5179 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1c046bc1 | 5180 | int s_max = 3, ss_max = 4; |
5d39525a JM |
5181 | int s, ss; |
5182 | u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2]; | |
5183 | ||
1c046bc1 JM |
5184 | /* BXT has a single slice and at most 3 subslices. */ |
5185 | if (IS_BROXTON(dev)) { | |
5186 | s_max = 1; | |
5187 | ss_max = 3; | |
5188 | } | |
5189 | ||
5190 | for (s = 0; s < s_max; s++) { | |
5191 | s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s)); | |
5192 | eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s)); | |
5193 | eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s)); | |
5194 | } | |
5195 | ||
5d39525a JM |
5196 | eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | |
5197 | GEN9_PGCTL_SSA_EU19_ACK | | |
5198 | GEN9_PGCTL_SSA_EU210_ACK | | |
5199 | GEN9_PGCTL_SSA_EU311_ACK; | |
5200 | eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK | | |
5201 | GEN9_PGCTL_SSB_EU19_ACK | | |
5202 | GEN9_PGCTL_SSB_EU210_ACK | | |
5203 | GEN9_PGCTL_SSB_EU311_ACK; | |
5204 | ||
5205 | for (s = 0; s < s_max; s++) { | |
1c046bc1 JM |
5206 | unsigned int ss_cnt = 0; |
5207 | ||
5d39525a JM |
5208 | if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) |
5209 | /* skip disabled slice */ | |
5210 | continue; | |
5211 | ||
5212 | stat->slice_total++; | |
1c046bc1 | 5213 | |
ef11bdb3 | 5214 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
1c046bc1 JM |
5215 | ss_cnt = INTEL_INFO(dev)->subslice_per_slice; |
5216 | ||
5d39525a JM |
5217 | for (ss = 0; ss < ss_max; ss++) { |
5218 | unsigned int eu_cnt; | |
5219 | ||
1c046bc1 JM |
5220 | if (IS_BROXTON(dev) && |
5221 | !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) | |
5222 | /* skip disabled subslice */ | |
5223 | continue; | |
5224 | ||
5225 | if (IS_BROXTON(dev)) | |
5226 | ss_cnt++; | |
5227 | ||
5d39525a JM |
5228 | eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & |
5229 | eu_mask[ss%2]); | |
5230 | stat->eu_total += eu_cnt; | |
5231 | stat->eu_per_subslice = max(stat->eu_per_subslice, | |
5232 | eu_cnt); | |
5233 | } | |
1c046bc1 JM |
5234 | |
5235 | stat->subslice_total += ss_cnt; | |
5236 | stat->subslice_per_slice = max(stat->subslice_per_slice, | |
5237 | ss_cnt); | |
5d39525a JM |
5238 | } |
5239 | } | |
5240 | ||
91bedd34 ŁD |
5241 | static void broadwell_sseu_device_status(struct drm_device *dev, |
5242 | struct sseu_dev_status *stat) | |
5243 | { | |
5244 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5245 | int s; | |
5246 | u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO); | |
5247 | ||
5248 | stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK); | |
5249 | ||
5250 | if (stat->slice_total) { | |
5251 | stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice; | |
5252 | stat->subslice_total = stat->slice_total * | |
5253 | stat->subslice_per_slice; | |
5254 | stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice; | |
5255 | stat->eu_total = stat->eu_per_subslice * stat->subslice_total; | |
5256 | ||
5257 | /* subtract fused off EU(s) from enabled slice(s) */ | |
5258 | for (s = 0; s < stat->slice_total; s++) { | |
5259 | u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s]; | |
5260 | ||
5261 | stat->eu_total -= hweight8(subslice_7eu); | |
5262 | } | |
5263 | } | |
5264 | } | |
5265 | ||
3873218f JM |
5266 | static int i915_sseu_status(struct seq_file *m, void *unused) |
5267 | { | |
5268 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
5269 | struct drm_device *dev = node->minor->dev; | |
5d39525a | 5270 | struct sseu_dev_status stat; |
3873218f | 5271 | |
91bedd34 | 5272 | if (INTEL_INFO(dev)->gen < 8) |
3873218f JM |
5273 | return -ENODEV; |
5274 | ||
5275 | seq_puts(m, "SSEU Device Info\n"); | |
5276 | seq_printf(m, " Available Slice Total: %u\n", | |
5277 | INTEL_INFO(dev)->slice_total); | |
5278 | seq_printf(m, " Available Subslice Total: %u\n", | |
5279 | INTEL_INFO(dev)->subslice_total); | |
5280 | seq_printf(m, " Available Subslice Per Slice: %u\n", | |
5281 | INTEL_INFO(dev)->subslice_per_slice); | |
5282 | seq_printf(m, " Available EU Total: %u\n", | |
5283 | INTEL_INFO(dev)->eu_total); | |
5284 | seq_printf(m, " Available EU Per Subslice: %u\n", | |
5285 | INTEL_INFO(dev)->eu_per_subslice); | |
5286 | seq_printf(m, " Has Slice Power Gating: %s\n", | |
5287 | yesno(INTEL_INFO(dev)->has_slice_pg)); | |
5288 | seq_printf(m, " Has Subslice Power Gating: %s\n", | |
5289 | yesno(INTEL_INFO(dev)->has_subslice_pg)); | |
5290 | seq_printf(m, " Has EU Power Gating: %s\n", | |
5291 | yesno(INTEL_INFO(dev)->has_eu_pg)); | |
5292 | ||
7f992aba | 5293 | seq_puts(m, "SSEU Device Status\n"); |
5d39525a | 5294 | memset(&stat, 0, sizeof(stat)); |
5575f03a | 5295 | if (IS_CHERRYVIEW(dev)) { |
5d39525a | 5296 | cherryview_sseu_device_status(dev, &stat); |
91bedd34 ŁD |
5297 | } else if (IS_BROADWELL(dev)) { |
5298 | broadwell_sseu_device_status(dev, &stat); | |
1c046bc1 | 5299 | } else if (INTEL_INFO(dev)->gen >= 9) { |
5d39525a | 5300 | gen9_sseu_device_status(dev, &stat); |
7f992aba | 5301 | } |
5d39525a JM |
5302 | seq_printf(m, " Enabled Slice Total: %u\n", |
5303 | stat.slice_total); | |
5304 | seq_printf(m, " Enabled Subslice Total: %u\n", | |
5305 | stat.subslice_total); | |
5306 | seq_printf(m, " Enabled Subslice Per Slice: %u\n", | |
5307 | stat.subslice_per_slice); | |
5308 | seq_printf(m, " Enabled EU Total: %u\n", | |
5309 | stat.eu_total); | |
5310 | seq_printf(m, " Enabled EU Per Subslice: %u\n", | |
5311 | stat.eu_per_subslice); | |
7f992aba | 5312 | |
3873218f JM |
5313 | return 0; |
5314 | } | |
5315 | ||
6d794d42 BW |
5316 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
5317 | { | |
5318 | struct drm_device *dev = inode->i_private; | |
5319 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d794d42 | 5320 | |
075edca4 | 5321 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
5322 | return 0; |
5323 | ||
6daccb0b | 5324 | intel_runtime_pm_get(dev_priv); |
59bad947 | 5325 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
6d794d42 BW |
5326 | |
5327 | return 0; | |
5328 | } | |
5329 | ||
c43b5634 | 5330 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 BW |
5331 | { |
5332 | struct drm_device *dev = inode->i_private; | |
5333 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5334 | ||
075edca4 | 5335 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
5336 | return 0; |
5337 | ||
59bad947 | 5338 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
6daccb0b | 5339 | intel_runtime_pm_put(dev_priv); |
6d794d42 BW |
5340 | |
5341 | return 0; | |
5342 | } | |
5343 | ||
5344 | static const struct file_operations i915_forcewake_fops = { | |
5345 | .owner = THIS_MODULE, | |
5346 | .open = i915_forcewake_open, | |
5347 | .release = i915_forcewake_release, | |
5348 | }; | |
5349 | ||
5350 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
5351 | { | |
5352 | struct drm_device *dev = minor->dev; | |
5353 | struct dentry *ent; | |
5354 | ||
5355 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 5356 | S_IRUSR, |
6d794d42 BW |
5357 | root, dev, |
5358 | &i915_forcewake_fops); | |
f3c5fe97 WY |
5359 | if (!ent) |
5360 | return -ENOMEM; | |
6d794d42 | 5361 | |
8eb57294 | 5362 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
5363 | } |
5364 | ||
6a9c308d DV |
5365 | static int i915_debugfs_create(struct dentry *root, |
5366 | struct drm_minor *minor, | |
5367 | const char *name, | |
5368 | const struct file_operations *fops) | |
07b7ddd9 JB |
5369 | { |
5370 | struct drm_device *dev = minor->dev; | |
5371 | struct dentry *ent; | |
5372 | ||
6a9c308d | 5373 | ent = debugfs_create_file(name, |
07b7ddd9 JB |
5374 | S_IRUGO | S_IWUSR, |
5375 | root, dev, | |
6a9c308d | 5376 | fops); |
f3c5fe97 WY |
5377 | if (!ent) |
5378 | return -ENOMEM; | |
07b7ddd9 | 5379 | |
6a9c308d | 5380 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
5381 | } |
5382 | ||
06c5bf8c | 5383 | static const struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 5384 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 5385 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 5386 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
1b50247a | 5387 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
433e12f7 | 5388 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
433e12f7 | 5389 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
6d2b8885 | 5390 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
4e5359cd | 5391 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
5392 | {"i915_gem_request", i915_gem_request_info, 0}, |
5393 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 5394 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 5395 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
5396 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
5397 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
5398 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
9010ebfd | 5399 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
493018dc | 5400 | {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0}, |
8b417c26 | 5401 | {"i915_guc_info", i915_guc_info, 0}, |
fdf5d357 | 5402 | {"i915_guc_load_status", i915_guc_load_status_info, 0}, |
4c7e77fc | 5403 | {"i915_guc_log_dump", i915_guc_log_dump, 0}, |
adb4bd12 | 5404 | {"i915_frequency_info", i915_frequency_info, 0}, |
f654449a | 5405 | {"i915_hangcheck_info", i915_hangcheck_info, 0}, |
f97108d1 | 5406 | {"i915_drpc_info", i915_drpc_info, 0}, |
7648fa99 | 5407 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 5408 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
9a851789 | 5409 | {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0}, |
b5e50c3f | 5410 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 5411 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 5412 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 5413 | {"i915_opregion", i915_opregion, 0}, |
ada8f955 | 5414 | {"i915_vbt", i915_vbt, 0}, |
37811fcc | 5415 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 5416 | {"i915_context_status", i915_context_status, 0}, |
c0ab1ae9 | 5417 | {"i915_dump_lrc", i915_dump_lrc, 0}, |
4ba70e44 | 5418 | {"i915_execlists", i915_execlists, 0}, |
f65367b5 | 5419 | {"i915_forcewake_domains", i915_forcewake_domains, 0}, |
ea16a3cd | 5420 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 5421 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
63573eb7 | 5422 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 5423 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
d2e216d0 | 5424 | {"i915_sink_crc_eDP1", i915_sink_crc, 0}, |
ec013e7f | 5425 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
6455c870 | 5426 | {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, |
1da51581 | 5427 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
b7cec66d | 5428 | {"i915_dmc_info", i915_dmc_info, 0}, |
53f5e3ca | 5429 | {"i915_display_info", i915_display_info, 0}, |
e04934cf | 5430 | {"i915_semaphore_status", i915_semaphore_status, 0}, |
728e29d7 | 5431 | {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, |
11bed958 | 5432 | {"i915_dp_mst_info", i915_dp_mst_info, 0}, |
1ed1ef9d | 5433 | {"i915_wa_registers", i915_wa_registers, 0}, |
c5511e44 | 5434 | {"i915_ddb_info", i915_ddb_info, 0}, |
3873218f | 5435 | {"i915_sseu_status", i915_sseu_status, 0}, |
a54746e3 | 5436 | {"i915_drrs_status", i915_drrs_status, 0}, |
1854d5ca | 5437 | {"i915_rps_boost_info", i915_rps_boost_info, 0}, |
2017263e | 5438 | }; |
27c202ad | 5439 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 5440 | |
06c5bf8c | 5441 | static const struct i915_debugfs_files { |
34b9674c DV |
5442 | const char *name; |
5443 | const struct file_operations *fops; | |
5444 | } i915_debugfs_files[] = { | |
5445 | {"i915_wedged", &i915_wedged_fops}, | |
5446 | {"i915_max_freq", &i915_max_freq_fops}, | |
5447 | {"i915_min_freq", &i915_min_freq_fops}, | |
5448 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
5449 | {"i915_ring_stop", &i915_ring_stop_fops}, | |
094f9a54 CW |
5450 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
5451 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c DV |
5452 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
5453 | {"i915_error_state", &i915_error_state_fops}, | |
5454 | {"i915_next_seqno", &i915_next_seqno_fops}, | |
bd9db02f | 5455 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
369a1342 VS |
5456 | {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, |
5457 | {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, | |
5458 | {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, | |
da46f936 | 5459 | {"i915_fbc_false_color", &i915_fbc_fc_fops}, |
eb3394fa TP |
5460 | {"i915_dp_test_data", &i915_displayport_test_data_fops}, |
5461 | {"i915_dp_test_type", &i915_displayport_test_type_fops}, | |
5462 | {"i915_dp_test_active", &i915_displayport_test_active_fops} | |
34b9674c DV |
5463 | }; |
5464 | ||
07144428 DL |
5465 | void intel_display_crc_init(struct drm_device *dev) |
5466 | { | |
5467 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b378360e | 5468 | enum pipe pipe; |
07144428 | 5469 | |
055e393f | 5470 | for_each_pipe(dev_priv, pipe) { |
b378360e | 5471 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
07144428 | 5472 | |
d538bbdf DL |
5473 | pipe_crc->opened = false; |
5474 | spin_lock_init(&pipe_crc->lock); | |
07144428 DL |
5475 | init_waitqueue_head(&pipe_crc->wq); |
5476 | } | |
5477 | } | |
5478 | ||
27c202ad | 5479 | int i915_debugfs_init(struct drm_minor *minor) |
2017263e | 5480 | { |
34b9674c | 5481 | int ret, i; |
f3cd474b | 5482 | |
6d794d42 | 5483 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
5484 | if (ret) |
5485 | return ret; | |
6a9c308d | 5486 | |
07144428 DL |
5487 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
5488 | ret = i915_pipe_crc_create(minor->debugfs_root, minor, i); | |
5489 | if (ret) | |
5490 | return ret; | |
5491 | } | |
5492 | ||
34b9674c DV |
5493 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
5494 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
5495 | i915_debugfs_files[i].name, | |
5496 | i915_debugfs_files[i].fops); | |
5497 | if (ret) | |
5498 | return ret; | |
5499 | } | |
40633219 | 5500 | |
27c202ad BG |
5501 | return drm_debugfs_create_files(i915_debugfs_list, |
5502 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
5503 | minor->debugfs_root, minor); |
5504 | } | |
5505 | ||
27c202ad | 5506 | void i915_debugfs_cleanup(struct drm_minor *minor) |
2017263e | 5507 | { |
34b9674c DV |
5508 | int i; |
5509 | ||
27c202ad BG |
5510 | drm_debugfs_remove_files(i915_debugfs_list, |
5511 | I915_DEBUGFS_ENTRIES, minor); | |
07144428 | 5512 | |
6d794d42 BW |
5513 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
5514 | 1, minor); | |
07144428 | 5515 | |
e309a997 | 5516 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
07144428 DL |
5517 | struct drm_info_list *info_list = |
5518 | (struct drm_info_list *)&i915_pipe_crc_data[i]; | |
5519 | ||
5520 | drm_debugfs_remove_files(info_list, 1, minor); | |
5521 | } | |
5522 | ||
34b9674c DV |
5523 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
5524 | struct drm_info_list *info_list = | |
5525 | (struct drm_info_list *) i915_debugfs_files[i].fops; | |
5526 | ||
5527 | drm_debugfs_remove_files(info_list, 1, minor); | |
5528 | } | |
2017263e | 5529 | } |
aa7471d2 JN |
5530 | |
5531 | struct dpcd_block { | |
5532 | /* DPCD dump start address. */ | |
5533 | unsigned int offset; | |
5534 | /* DPCD dump end address, inclusive. If unset, .size will be used. */ | |
5535 | unsigned int end; | |
5536 | /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */ | |
5537 | size_t size; | |
5538 | /* Only valid for eDP. */ | |
5539 | bool edp; | |
5540 | }; | |
5541 | ||
5542 | static const struct dpcd_block i915_dpcd_debug[] = { | |
5543 | { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE }, | |
5544 | { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS }, | |
5545 | { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 }, | |
5546 | { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET }, | |
5547 | { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 }, | |
5548 | { .offset = DP_SET_POWER }, | |
5549 | { .offset = DP_EDP_DPCD_REV }, | |
5550 | { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 }, | |
5551 | { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB }, | |
5552 | { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET }, | |
5553 | }; | |
5554 | ||
5555 | static int i915_dpcd_show(struct seq_file *m, void *data) | |
5556 | { | |
5557 | struct drm_connector *connector = m->private; | |
5558 | struct intel_dp *intel_dp = | |
5559 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
5560 | uint8_t buf[16]; | |
5561 | ssize_t err; | |
5562 | int i; | |
5563 | ||
5c1a8875 MK |
5564 | if (connector->status != connector_status_connected) |
5565 | return -ENODEV; | |
5566 | ||
aa7471d2 JN |
5567 | for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) { |
5568 | const struct dpcd_block *b = &i915_dpcd_debug[i]; | |
5569 | size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1); | |
5570 | ||
5571 | if (b->edp && | |
5572 | connector->connector_type != DRM_MODE_CONNECTOR_eDP) | |
5573 | continue; | |
5574 | ||
5575 | /* low tech for now */ | |
5576 | if (WARN_ON(size > sizeof(buf))) | |
5577 | continue; | |
5578 | ||
5579 | err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size); | |
5580 | if (err <= 0) { | |
5581 | DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n", | |
5582 | size, b->offset, err); | |
5583 | continue; | |
5584 | } | |
5585 | ||
5586 | seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf); | |
b3f9d7d7 | 5587 | } |
aa7471d2 JN |
5588 | |
5589 | return 0; | |
5590 | } | |
5591 | ||
5592 | static int i915_dpcd_open(struct inode *inode, struct file *file) | |
5593 | { | |
5594 | return single_open(file, i915_dpcd_show, inode->i_private); | |
5595 | } | |
5596 | ||
5597 | static const struct file_operations i915_dpcd_fops = { | |
5598 | .owner = THIS_MODULE, | |
5599 | .open = i915_dpcd_open, | |
5600 | .read = seq_read, | |
5601 | .llseek = seq_lseek, | |
5602 | .release = single_release, | |
5603 | }; | |
5604 | ||
5605 | /** | |
5606 | * i915_debugfs_connector_add - add i915 specific connector debugfs files | |
5607 | * @connector: pointer to a registered drm_connector | |
5608 | * | |
5609 | * Cleanup will be done by drm_connector_unregister() through a call to | |
5610 | * drm_debugfs_connector_remove(). | |
5611 | * | |
5612 | * Returns 0 on success, negative error codes on error. | |
5613 | */ | |
5614 | int i915_debugfs_connector_add(struct drm_connector *connector) | |
5615 | { | |
5616 | struct dentry *root = connector->debugfs_entry; | |
5617 | ||
5618 | /* The connector must have been registered beforehands. */ | |
5619 | if (!root) | |
5620 | return -ENODEV; | |
5621 | ||
5622 | if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || | |
5623 | connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
5624 | debugfs_create_file("i915_dpcd", S_IRUGO, root, connector, | |
5625 | &i915_dpcd_fops); | |
5626 | ||
5627 | return 0; | |
5628 | } |