[linux-block.git] / drivers / gpu / drm / i915 / gvt / vgpu.c

/*
 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 * Authors:
 *    Eddie Dong <eddie.dong@intel.com>
 *    Kevin Tian <kevin.tian@intel.com>
 *
 * Contributors:
 *    Ping Gao <ping.a.gao@intel.com>
 *    Zhi Wang <zhi.a.wang@intel.com>
 *    Bing Niu <bing.niu@intel.com>
 *
 */

#include "i915_drv.h"
#include "gvt.h"
#include "i915_pvinfo.h"

void populate_pvinfo_page(struct intel_vgpu *vgpu)
{
	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
	/* setup the ballooning information */
	vgpu_vreg64_t(vgpu, vgtif_reg(magic)) = VGT_MAGIC;
	vgpu_vreg_t(vgpu, vgtif_reg(version_major)) = 1;
	vgpu_vreg_t(vgpu, vgtif_reg(version_minor)) = 0;
	vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
	vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;

	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_PPGTT;
	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;

	vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
		vgpu_aperture_gmadr_base(vgpu);
	vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) =
		vgpu_aperture_sz(vgpu);
	vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) =
		vgpu_hidden_gmadr_base(vgpu);
	vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.size)) =
		vgpu_hidden_sz(vgpu);

	vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu);

	vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)) = UINT_MAX;
	vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot)) = UINT_MAX;

	gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id);
	gvt_dbg_core("aperture base [GMADR] 0x%llx size 0x%llx\n",
		vgpu_aperture_gmadr_base(vgpu), vgpu_aperture_sz(vgpu));
	gvt_dbg_core("hidden base [GMADR] 0x%llx size=0x%llx\n",
		vgpu_hidden_gmadr_base(vgpu), vgpu_hidden_sz(vgpu));
	gvt_dbg_core("fence size %d\n", vgpu_fence_sz(vgpu));

	drm_WARN_ON(&i915->drm, sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
}

/*
 * vGPU type name is defined as GVTg_Vx_y which contains the physical GPU
 * generation type (e.g V4 as BDW server, V5 as SKL server).
 *
 * Depening on the physical SKU resource, we might see vGPU types like
 * GVTg_V4_8, GVTg_V4_4, GVTg_V4_2, etc. We can create different types of
 * vGPU on same physical GPU depending on available resource. Each vGPU
 * type will have a different number of avail_instance to indicate how
 * many vGPU instance can be created for this type.
 */
#define VGPU_MAX_WEIGHT 16
#define VGPU_WEIGHT(vgpu_num)	\
	(VGPU_MAX_WEIGHT / (vgpu_num))

static const struct intel_vgpu_config intel_vgpu_configs[] = {
	{ MB_TO_BYTES(64), MB_TO_BYTES(384), 4, VGPU_WEIGHT(8), GVT_EDID_1024_768, "8" },
	{ MB_TO_BYTES(128), MB_TO_BYTES(512), 4, VGPU_WEIGHT(4), GVT_EDID_1920_1200, "4" },
	{ MB_TO_BYTES(256), MB_TO_BYTES(1024), 4, VGPU_WEIGHT(2), GVT_EDID_1920_1200, "2" },
	{ MB_TO_BYTES(512), MB_TO_BYTES(2048), 4, VGPU_WEIGHT(1), GVT_EDID_1920_1200, "1" },
};

/**
 * intel_gvt_init_vgpu_types - initialize vGPU type list
 * @gvt : GVT device
 *
 * Initialize vGPU type list based on available resource.
 *
 */
int intel_gvt_init_vgpu_types(struct intel_gvt *gvt)
{
	unsigned int low_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE;
	unsigned int high_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE;
	unsigned int num_types = ARRAY_SIZE(intel_vgpu_configs);
	unsigned int i;

	gvt->types = kcalloc(num_types, sizeof(struct intel_vgpu_type),
			     GFP_KERNEL);
	if (!gvt->types)
		return -ENOMEM;

	gvt->mdev_types = kcalloc(num_types, sizeof(*gvt->mdev_types),
			     GFP_KERNEL);
	if (!gvt->mdev_types)
		goto out_free_types;

	for (i = 0; i < num_types; ++i) {
		const struct intel_vgpu_config *conf = &intel_vgpu_configs[i];

		if (low_avail / conf->low_mm == 0)
			break;
		if (conf->weight < 1 || conf->weight > VGPU_MAX_WEIGHT)
			goto out_free_mdev_types;

		sprintf(gvt->types[i].name, "GVTg_V%u_%s",
			GRAPHICS_VER(gvt->gt->i915) == 8 ? 4 : 5, conf->name);
		gvt->types[i].conf = conf;

		gvt_dbg_core("type[%d]: %s avail %u low %u high %u fence %u weight %u res %s\n",
			     i, gvt->types[i].name,
			     min(low_avail / conf->low_mm,
				 high_avail / conf->high_mm),
			     conf->low_mm, conf->high_mm, conf->fence,
			     conf->weight, vgpu_edid_str(conf->edid));

		gvt->mdev_types[i] = &gvt->types[i].type;
		gvt->mdev_types[i]->sysfs_name = gvt->types[i].name;
	}

	gvt->num_types = i;
	return 0;

out_free_mdev_types:
	kfree(gvt->mdev_types);
out_free_types:
	kfree(gvt->types);
	return -EINVAL;
}

void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt)
{
	kfree(gvt->mdev_types);
	kfree(gvt->types);
}

/**
 * intel_gvt_active_vgpu - activate a virtual GPU
 * @vgpu: virtual GPU
 *
 * This function is called when user wants to activate a virtual GPU.
 *
 */
void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu)
{
	mutex_lock(&vgpu->vgpu_lock);
	vgpu->active = true;
	mutex_unlock(&vgpu->vgpu_lock);
}

/**
 * intel_gvt_deactive_vgpu - deactivate a virtual GPU
 * @vgpu: virtual GPU
 *
 * This function is called when user wants to deactivate a virtual GPU.
 * The virtual GPU will be stopped.
 *
 */
void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu)
{
	mutex_lock(&vgpu->vgpu_lock);

	vgpu->active = false;

	if (atomic_read(&vgpu->submission.running_workload_num)) {
		mutex_unlock(&vgpu->vgpu_lock);
		intel_gvt_wait_vgpu_idle(vgpu);
		mutex_lock(&vgpu->vgpu_lock);
	}

	intel_vgpu_stop_schedule(vgpu);

	mutex_unlock(&vgpu->vgpu_lock);
}

/**
 * intel_gvt_release_vgpu - release a virtual GPU
 * @vgpu: virtual GPU
 *
 * This function is called when user wants to release a virtual GPU.
 * The virtual GPU will be stopped and all runtime information will be
 * destroyed.
 *
 */
void intel_gvt_release_vgpu(struct intel_vgpu *vgpu)
{
	intel_gvt_deactivate_vgpu(vgpu);

	mutex_lock(&vgpu->vgpu_lock);
	vgpu->d3_entered = false;
	intel_vgpu_clean_workloads(vgpu, ALL_ENGINES);
	intel_vgpu_dmabuf_cleanup(vgpu);
	mutex_unlock(&vgpu->vgpu_lock);
}

/**
 * intel_gvt_destroy_vgpu - destroy a virtual GPU
 * @vgpu: virtual GPU
 *
 * This function is called when user wants to destroy a virtual GPU.
 *
 */
void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu)
{
	struct intel_gvt *gvt = vgpu->gvt;
	struct drm_i915_private *i915 = gvt->gt->i915;

	drm_WARN(&i915->drm, vgpu->active, "vGPU is still active!\n");

	/*
	 * remove idr first so later clean can judge if need to stop
	 * service if no active vgpu.
	 */
	mutex_lock(&gvt->lock);
	idr_remove(&gvt->vgpu_idr, vgpu->id);
	mutex_unlock(&gvt->lock);

	mutex_lock(&vgpu->vgpu_lock);
	intel_gvt_debugfs_remove_vgpu(vgpu);
	intel_vgpu_clean_sched_policy(vgpu);
	intel_vgpu_clean_submission(vgpu);
	intel_vgpu_clean_display(vgpu);
	intel_vgpu_clean_opregion(vgpu);
	intel_vgpu_reset_ggtt(vgpu, true);
	intel_vgpu_clean_gtt(vgpu);
	intel_vgpu_detach_regions(vgpu);
	intel_vgpu_free_resource(vgpu);
	intel_vgpu_clean_mmio(vgpu);
	intel_vgpu_dmabuf_cleanup(vgpu);
	mutex_unlock(&vgpu->vgpu_lock);
}

#define IDLE_VGPU_IDR 0

/**
 * intel_gvt_create_idle_vgpu - create an idle virtual GPU
 * @gvt: GVT device
 *
 * This function is called when user wants to create an idle virtual GPU.
 *
 * Returns:
 * pointer to intel_vgpu, error pointer if failed.
 */
struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt)
{
	struct intel_vgpu *vgpu;
	enum intel_engine_id i;
	int ret;

	vgpu = vzalloc(sizeof(*vgpu));
	if (!vgpu)
		return ERR_PTR(-ENOMEM);

	vgpu->id = IDLE_VGPU_IDR;
	vgpu->gvt = gvt;
	mutex_init(&vgpu->vgpu_lock);

	for (i = 0; i < I915_NUM_ENGINES; i++)
		INIT_LIST_HEAD(&vgpu->submission.workload_q_head[i]);

	ret = intel_vgpu_init_sched_policy(vgpu);
	if (ret)
		goto out_free_vgpu;

	vgpu->active = false;

	return vgpu;

out_free_vgpu:
	vfree(vgpu);
	return ERR_PTR(ret);
}

/**
 * intel_gvt_destroy_vgpu - destroy an idle virtual GPU
 * @vgpu: virtual GPU
 *
 * This function is called when user wants to destroy an idle virtual GPU.
 *
 */
void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu)
{
	mutex_lock(&vgpu->vgpu_lock);
	intel_vgpu_clean_sched_policy(vgpu);
	mutex_unlock(&vgpu->vgpu_lock);

	vfree(vgpu);
}

int intel_gvt_create_vgpu(struct intel_vgpu *vgpu,
		const struct intel_vgpu_config *conf)
{
	struct intel_gvt *gvt = vgpu->gvt;
	struct drm_i915_private *dev_priv = gvt->gt->i915;
	int ret;

	gvt_dbg_core("low %u MB high %u MB fence %u\n",
			BYTES_TO_MB(conf->low_mm), BYTES_TO_MB(conf->high_mm),
			conf->fence);

	mutex_lock(&gvt->lock);
	ret = idr_alloc(&gvt->vgpu_idr, vgpu, IDLE_VGPU_IDR + 1, GVT_MAX_VGPU,
		GFP_KERNEL);
	if (ret < 0)
		goto out_unlock;;

	vgpu->id = ret;
	vgpu->sched_ctl.weight = conf->weight;
	mutex_init(&vgpu->vgpu_lock);
	mutex_init(&vgpu->dmabuf_lock);
	INIT_LIST_HEAD(&vgpu->dmabuf_obj_list_head);
	INIT_RADIX_TREE(&vgpu->page_track_tree, GFP_KERNEL);
	idr_init_base(&vgpu->object_idr, 1);
	intel_vgpu_init_cfg_space(vgpu, 1);
	vgpu->d3_entered = false;

	ret = intel_vgpu_init_mmio(vgpu);
	if (ret)
		goto out_clean_idr;

	ret = intel_vgpu_alloc_resource(vgpu, conf);
	if (ret)
		goto out_clean_vgpu_mmio;

	populate_pvinfo_page(vgpu);

	ret = intel_vgpu_init_gtt(vgpu);
	if (ret)
		goto out_clean_vgpu_resource;

	ret = intel_vgpu_init_opregion(vgpu);
	if (ret)
		goto out_clean_gtt;

	ret = intel_vgpu_init_display(vgpu, conf->edid);
	if (ret)
		goto out_clean_opregion;

	ret = intel_vgpu_setup_submission(vgpu);
	if (ret)
		goto out_clean_display;

	ret = intel_vgpu_init_sched_policy(vgpu);
	if (ret)
		goto out_clean_submission;

	intel_gvt_debugfs_add_vgpu(vgpu);

	ret = intel_gvt_set_opregion(vgpu);
	if (ret)
		goto out_clean_sched_policy;

	if (IS_BROADWELL(dev_priv) || IS_BROXTON(dev_priv))
		ret = intel_gvt_set_edid(vgpu, PORT_B);
	else
		ret = intel_gvt_set_edid(vgpu, PORT_D);
	if (ret)
		goto out_clean_sched_policy;

	intel_gvt_update_reg_whitelist(vgpu);
	mutex_unlock(&gvt->lock);
	return 0;

out_clean_sched_policy:
	intel_vgpu_clean_sched_policy(vgpu);
out_clean_submission:
	intel_vgpu_clean_submission(vgpu);
out_clean_display:
	intel_vgpu_clean_display(vgpu);
out_clean_opregion:
	intel_vgpu_clean_opregion(vgpu);
out_clean_gtt:
	intel_vgpu_clean_gtt(vgpu);
out_clean_vgpu_resource:
	intel_vgpu_free_resource(vgpu);
out_clean_vgpu_mmio:
	intel_vgpu_clean_mmio(vgpu);
out_clean_idr:
	idr_remove(&gvt->vgpu_idr, vgpu->id);
out_unlock:
	mutex_unlock(&gvt->lock);
	return ret;
}

/**
 * intel_gvt_reset_vgpu_locked - reset a virtual GPU by DMLR or GT reset
 * @vgpu: virtual GPU
 * @dmlr: vGPU Device Model Level Reset or GT Reset
 * @engine_mask: engines to reset for GT reset
 *
 * This function is called when user wants to reset a virtual GPU through
 * device model reset or GT reset. The caller should hold the vgpu lock.
 *
 * vGPU Device Model Level Reset (DMLR) simulates the PCI level reset to reset
 * the whole vGPU to default state as when it is created. This vGPU function
 * is required both for functionary and security concerns.The ultimate goal
 * of vGPU FLR is that reuse a vGPU instance by virtual machines. When we
 * assign a vGPU to a virtual machine we must isse such reset first.
 *
 * Full GT Reset and Per-Engine GT Reset are soft reset flow for GPU engines
 * (Render, Blitter, Video, Video Enhancement). It is defined by GPU Spec.
 * Unlike the FLR, GT reset only reset particular resource of a vGPU per
 * the reset request. Guest driver can issue a GT reset by programming the
 * virtual GDRST register to reset specific virtual GPU engine or all
 * engines.
 *
 * The parameter dev_level is to identify if we will do DMLR or GT reset.
 * The parameter engine_mask is to specific the engines that need to be
 * resetted. If value ALL_ENGINES is given for engine_mask, it means
 * the caller requests a full GT reset that we will reset all virtual
 * GPU engines. For FLR, engine_mask is ignored.
 */
void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
				 intel_engine_mask_t engine_mask)
{
	struct intel_gvt *gvt = vgpu->gvt;
	struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
	intel_engine_mask_t resetting_eng = dmlr ? ALL_ENGINES : engine_mask;

	gvt_dbg_core("------------------------------------------\n");
	gvt_dbg_core("resseting vgpu%d, dmlr %d, engine_mask %08x\n",
		     vgpu->id, dmlr, engine_mask);

	vgpu->resetting_eng = resetting_eng;

	intel_vgpu_stop_schedule(vgpu);
	/*
	 * The current_vgpu will set to NULL after stopping the
	 * scheduler when the reset is triggered by current vgpu.
	 */
	if (scheduler->current_vgpu == NULL) {
		mutex_unlock(&vgpu->vgpu_lock);
		intel_gvt_wait_vgpu_idle(vgpu);
		mutex_lock(&vgpu->vgpu_lock);
	}

	intel_vgpu_reset_submission(vgpu, resetting_eng);
	/* full GPU reset or device model level reset */
	if (engine_mask == ALL_ENGINES || dmlr) {
		intel_vgpu_select_submission_ops(vgpu, ALL_ENGINES, 0);
		if (engine_mask == ALL_ENGINES)
			intel_vgpu_invalidate_ppgtt(vgpu);
		/*fence will not be reset during virtual reset */
		if (dmlr) {
			if(!vgpu->d3_entered) {
				intel_vgpu_invalidate_ppgtt(vgpu);
				intel_vgpu_destroy_all_ppgtt_mm(vgpu);
			}
			intel_vgpu_reset_ggtt(vgpu, true);
			intel_vgpu_reset_resource(vgpu);
		}

		intel_vgpu_reset_mmio(vgpu, dmlr);
		populate_pvinfo_page(vgpu);

		if (dmlr) {
			intel_vgpu_reset_display(vgpu);
			intel_vgpu_reset_cfg_space(vgpu);
			/* only reset the failsafe mode when dmlr reset */
			vgpu->failsafe = false;
			/*
			 * PCI_D0 is set before dmlr, so reset d3_entered here
			 * after done using.
			 */
			if(vgpu->d3_entered)
				vgpu->d3_entered = false;
			else
				vgpu->pv_notified = false;
		}
	}

	vgpu->resetting_eng = 0;
	gvt_dbg_core("reset vgpu%d done\n", vgpu->id);
	gvt_dbg_core("------------------------------------------\n");
}

/**
 * intel_gvt_reset_vgpu - reset a virtual GPU (Function Level)
 * @vgpu: virtual GPU
 *
 * This function is called when user wants to reset a virtual GPU.
 *
 */
void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu)
{
	mutex_lock(&vgpu->vgpu_lock);
	intel_gvt_reset_vgpu_locked(vgpu, true, 0);
	mutex_unlock(&vgpu->vgpu_lock);
}
Commit	Line	Data
82d375d1 ZW	1	/*
	2	* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	20	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	21	* SOFTWARE.
	22	*
	23	* Authors:
	24	* Eddie Dong <eddie.dong@intel.com>
	25	* Kevin Tian <kevin.tian@intel.com>
	26	*
	27	* Contributors:
	28	* Ping Gao <ping.a.gao@intel.com>
	29	* Zhi Wang <zhi.a.wang@intel.com>
	30	* Bing Niu <bing.niu@intel.com>
	31	*
	32	*/
	33
	34	#include "i915_drv.h"
feddf6e8 ZW	35	#include "gvt.h"
feddf6e8 ZW	36	#include "i915_pvinfo.h"
82d375d1	37
23736d1b	38	void populate_pvinfo_page(struct intel_vgpu *vgpu)
82d375d1	39	{
a61ac1e7	40	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
82d375d1	41	/* setup the ballooning information */
90551a12 ZW	42	vgpu_vreg64_t(vgpu, vgtif_reg(magic)) = VGT_MAGIC;
	43	vgpu_vreg_t(vgpu, vgtif_reg(version_major)) = 1;
	44	vgpu_vreg_t(vgpu, vgtif_reg(version_minor)) = 0;
	45	vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
	46	vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
a2ae95af	47
ca6ac684	48	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_PPGTT;
90551a12	49	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) \|= VGT_CAPS_HWSP_EMULATION;
aa36ed6d	50	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) \|= VGT_CAPS_HUGE_GTT;
a2ae95af	51
90551a12	52	vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
82d375d1	53	vgpu_aperture_gmadr_base(vgpu);
90551a12	54	vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) =
82d375d1	55	vgpu_aperture_sz(vgpu);
90551a12	56	vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) =
82d375d1	57	vgpu_hidden_gmadr_base(vgpu);
90551a12	58	vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.size)) =
82d375d1 ZW	59	vgpu_hidden_sz(vgpu);
82d375d1 ZW	60
90551a12	61	vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu);
82d375d1	62
1c6ccad8 TZ	63	vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)) = UINT_MAX;
	64	vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot)) = UINT_MAX;
	65
82d375d1 ZW	66	gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id);
	67	gvt_dbg_core("aperture base [GMADR] 0x%llx size 0x%llx\n",
	68	vgpu_aperture_gmadr_base(vgpu), vgpu_aperture_sz(vgpu));
	69	gvt_dbg_core("hidden base [GMADR] 0x%llx size=0x%llx\n",
	70	vgpu_hidden_gmadr_base(vgpu), vgpu_hidden_sz(vgpu));
	71	gvt_dbg_core("fence size %d\n", vgpu_fence_sz(vgpu));
	72
12d58619	73	drm_WARN_ON(&i915->drm, sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
82d375d1 ZW	74	}
82d375d1 ZW	75
1aa3834f CH	76	/*
	77	* vGPU type name is defined as GVTg_Vx_y which contains the physical GPU
	78	* generation type (e.g V4 as BDW server, V5 as SKL server).
	79	*
	80	* Depening on the physical SKU resource, we might see vGPU types like
	81	* GVTg_V4_8, GVTg_V4_4, GVTg_V4_2, etc. We can create different types of
	82	* vGPU on same physical GPU depending on available resource. Each vGPU
	83	* type will have a different number of avail_instance to indicate how
	84	* many vGPU instance can be created for this type.
	85	*/
bc90d097 PG	86	#define VGPU_MAX_WEIGHT 16
	87	#define VGPU_WEIGHT(vgpu_num) \
	88	(VGPU_MAX_WEIGHT / (vgpu_num))
	89
1aa3834f	90	static const struct intel_vgpu_config intel_vgpu_configs[] = {
bc90d097 PG	91	{ MB_TO_BYTES(64), MB_TO_BYTES(384), 4, VGPU_WEIGHT(8), GVT_EDID_1024_768, "8" },
	92	{ MB_TO_BYTES(128), MB_TO_BYTES(512), 4, VGPU_WEIGHT(4), GVT_EDID_1920_1200, "4" },
	93	{ MB_TO_BYTES(256), MB_TO_BYTES(1024), 4, VGPU_WEIGHT(2), GVT_EDID_1920_1200, "2" },
	94	{ MB_TO_BYTES(512), MB_TO_BYTES(2048), 4, VGPU_WEIGHT(1), GVT_EDID_1920_1200, "1" },
191020b6 ZW	95	};
191020b6 ZW	96
1f31c829 ZW	97	/**
	98	* intel_gvt_init_vgpu_types - initialize vGPU type list
	99	* @gvt : GVT device
	100	*
	101	* Initialize vGPU type list based on available resource.
	102	*
	103	*/
	104	int intel_gvt_init_vgpu_types(struct intel_gvt *gvt)
	105	{
1aa3834f CH	106	unsigned int low_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE;
	107	unsigned int high_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE;
	108	unsigned int num_types = ARRAY_SIZE(intel_vgpu_configs);
	109	unsigned int i;
1f31c829	110
6396bb22	111	gvt->types = kcalloc(num_types, sizeof(struct intel_vgpu_type),
1f31c829 ZW	112	GFP_KERNEL);
	113	if (!gvt->types)
	114	return -ENOMEM;
	115
da44c340 CH	116	gvt->mdev_types = kcalloc(num_types, sizeof(*gvt->mdev_types),
	117	GFP_KERNEL);
	118	if (!gvt->mdev_types)
	119	goto out_free_types;
	120
1f31c829	121	for (i = 0; i < num_types; ++i) {
1aa3834f	122	const struct intel_vgpu_config *conf = &intel_vgpu_configs[i];
bc90d097	123
1aa3834f CH	124	if (low_avail / conf->low_mm == 0)
	125	break;
	126	if (conf->weight < 1 \|\| conf->weight > VGPU_MAX_WEIGHT)
da44c340	127	goto out_free_mdev_types;
bc90d097	128
1aa3834f CH	129	sprintf(gvt->types[i].name, "GVTg_V%u_%s",
	130	GRAPHICS_VER(gvt->gt->i915) == 8 ? 4 : 5, conf->name);
	131	gvt->types[i].conf = conf;
1f31c829	132
bc90d097	133	gvt_dbg_core("type[%d]: %s avail %u low %u high %u fence %u weight %u res %s\n",
f2fbc72e CH	134	i, gvt->types[i].name,
	135	min(low_avail / conf->low_mm,
	136	high_avail / conf->high_mm),
1aa3834f CH	137	conf->low_mm, conf->high_mm, conf->fence,
1aa3834f CH	138	conf->weight, vgpu_edid_str(conf->edid));
da44c340 CH	139
	140	gvt->mdev_types[i] = &gvt->types[i].type;
	141	gvt->mdev_types[i]->sysfs_name = gvt->types[i].name;
1f31c829 ZW	142	}
	143
	144	gvt->num_types = i;
	145	return 0;
98828955	146
da44c340 CH	147	out_free_mdev_types:
da44c340 CH	148	kfree(gvt->mdev_types);
98828955 CH	149	out_free_types:
	150	kfree(gvt->types);
	151	return -EINVAL;
1f31c829 ZW	152	}
	153
	154	void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt)
	155	{
da44c340	156	kfree(gvt->mdev_types);
1f31c829 ZW	157	kfree(gvt->types);
	158	}
	159
82d375d1	160	/**
b79c52ae	161	* intel_gvt_active_vgpu - activate a virtual GPU
82d375d1 ZW	162	* @vgpu: virtual GPU
82d375d1 ZW	163	*
b79c52ae	164	* This function is called when user wants to activate a virtual GPU.
82d375d1 ZW	165	*
82d375d1 ZW	166	*/
b79c52ae ZW	167	void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu)
b79c52ae ZW	168	{
6d44694d	169	mutex_lock(&vgpu->vgpu_lock);
b79c52ae	170	vgpu->active = true;
6d44694d	171	mutex_unlock(&vgpu->vgpu_lock);
b79c52ae ZW	172	}
	173
	174	/**
	175	* intel_gvt_deactive_vgpu - deactivate a virtual GPU
	176	* @vgpu: virtual GPU
	177	*
	178	* This function is called when user wants to deactivate a virtual GPU.
f9090d4c	179	* The virtual GPU will be stopped.
b79c52ae ZW	180	*
	181	*/
	182	void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu)
82d375d1	183	{
f25a49ab	184	mutex_lock(&vgpu->vgpu_lock);
82d375d1 ZW	185
82d375d1 ZW	186	vgpu->active = false;
82d375d1	187
1406a14b	188	if (atomic_read(&vgpu->submission.running_workload_num)) {
f25a49ab	189	mutex_unlock(&vgpu->vgpu_lock);
4b63960e	190	intel_gvt_wait_vgpu_idle(vgpu);
f25a49ab	191	mutex_lock(&vgpu->vgpu_lock);
4b63960e ZW	192	}
	193
	194	intel_vgpu_stop_schedule(vgpu);
b79c52ae	195
f25a49ab	196	mutex_unlock(&vgpu->vgpu_lock);
b79c52ae ZW	197	}
b79c52ae ZW	198
f9090d4c HY	199	/**
	200	* intel_gvt_release_vgpu - release a virtual GPU
	201	* @vgpu: virtual GPU
	202	*
	203	* This function is called when user wants to release a virtual GPU.
	204	* The virtual GPU will be stopped and all runtime information will be
	205	* destroyed.
	206	*
	207	*/
	208	void intel_gvt_release_vgpu(struct intel_vgpu *vgpu)
	209	{
	210	intel_gvt_deactivate_vgpu(vgpu);
	211
	212	mutex_lock(&vgpu->vgpu_lock);
ba25d977	213	vgpu->d3_entered = false;
f9090d4c HY	214	intel_vgpu_clean_workloads(vgpu, ALL_ENGINES);
	215	intel_vgpu_dmabuf_cleanup(vgpu);
	216	mutex_unlock(&vgpu->vgpu_lock);
	217	}
	218
b79c52ae ZW	219	/**
	220	* intel_gvt_destroy_vgpu - destroy a virtual GPU
	221	* @vgpu: virtual GPU
	222	*
	223	* This function is called when user wants to destroy a virtual GPU.
	224	*
	225	*/
	226	void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu)
	227	{
	228	struct intel_gvt *gvt = vgpu->gvt;
a61ac1e7	229	struct drm_i915_private *i915 = gvt->gt->i915;
b79c52ae	230
12d58619	231	drm_WARN(&i915->drm, vgpu->active, "vGPU is still active!\n");
b79c52ae	232
04d6067f ZW	233	/*
	234	* remove idr first so later clean can judge if need to stop
	235	* service if no active vgpu.
	236	*/
	237	mutex_lock(&gvt->lock);
	238	idr_remove(&gvt->vgpu_idr, vgpu->id);
	239	mutex_unlock(&gvt->lock);
	240
	241	mutex_lock(&vgpu->vgpu_lock);
bc7b0be3	242	intel_gvt_debugfs_remove_vgpu(vgpu);
4b63960e	243	intel_vgpu_clean_sched_policy(vgpu);
874b6a91	244	intel_vgpu_clean_submission(vgpu);
04d348ae	245	intel_vgpu_clean_display(vgpu);
4d60c5fd	246	intel_vgpu_clean_opregion(vgpu);
7759ca3a	247	intel_vgpu_reset_ggtt(vgpu, true);
2707e444	248	intel_vgpu_clean_gtt(vgpu);
4c705ad0	249	intel_vgpu_detach_regions(vgpu);
82d375d1	250	intel_vgpu_free_resource(vgpu);
cdcc4347	251	intel_vgpu_clean_mmio(vgpu);
e546e281	252	intel_vgpu_dmabuf_cleanup(vgpu);
f25a49ab	253	mutex_unlock(&vgpu->vgpu_lock);
82d375d1 ZW	254	}
82d375d1 ZW	255
afe04fbe PG	256	#define IDLE_VGPU_IDR 0
	257
	258	/**
	259	* intel_gvt_create_idle_vgpu - create an idle virtual GPU
	260	* @gvt: GVT device
	261	*
	262	* This function is called when user wants to create an idle virtual GPU.
	263	*
	264	* Returns:
	265	* pointer to intel_vgpu, error pointer if failed.
	266	*/
	267	struct intel_vgpu intel_gvt_create_idle_vgpu(struct intel_gvt gvt)
	268	{
	269	struct intel_vgpu *vgpu;
	270	enum intel_engine_id i;
	271	int ret;
	272
	273	vgpu = vzalloc(sizeof(*vgpu));
	274	if (!vgpu)
	275	return ERR_PTR(-ENOMEM);
	276
	277	vgpu->id = IDLE_VGPU_IDR;
	278	vgpu->gvt = gvt;
f25a49ab	279	mutex_init(&vgpu->vgpu_lock);
afe04fbe PG	280
afe04fbe PG	281	for (i = 0; i < I915_NUM_ENGINES; i++)
1406a14b	282	INIT_LIST_HEAD(&vgpu->submission.workload_q_head[i]);
afe04fbe PG	283
	284	ret = intel_vgpu_init_sched_policy(vgpu);
	285	if (ret)
	286	goto out_free_vgpu;
	287
	288	vgpu->active = false;
	289
	290	return vgpu;
	291
	292	out_free_vgpu:
	293	vfree(vgpu);
	294	return ERR_PTR(ret);
	295	}
	296
	297	/**
	298	* intel_gvt_destroy_vgpu - destroy an idle virtual GPU
	299	* @vgpu: virtual GPU
	300	*
	301	* This function is called when user wants to destroy an idle virtual GPU.
	302	*
	303	*/
	304	void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu)
	305	{
f25a49ab	306	mutex_lock(&vgpu->vgpu_lock);
afe04fbe	307	intel_vgpu_clean_sched_policy(vgpu);
f25a49ab CX	308	mutex_unlock(&vgpu->vgpu_lock);
f25a49ab CX	309
afe04fbe PG	310	vfree(vgpu);
	311	}
	312
1aa3834f CH	313	int intel_gvt_create_vgpu(struct intel_vgpu *vgpu,
1aa3834f CH	314	const struct intel_vgpu_config *conf)
82d375d1	315	{
a5ddd2a9	316	struct intel_gvt *gvt = vgpu->gvt;
28284943	317	struct drm_i915_private *dev_priv = gvt->gt->i915;
82d375d1 ZW	318	int ret;
82d375d1 ZW	319
1aa3834f CH	320	gvt_dbg_core("low %u MB high %u MB fence %u\n",
	321	BYTES_TO_MB(conf->low_mm), BYTES_TO_MB(conf->high_mm),
	322	conf->fence);
82d375d1	323
1aa3834f	324	mutex_lock(&gvt->lock);
afe04fbe PG	325	ret = idr_alloc(&gvt->vgpu_idr, vgpu, IDLE_VGPU_IDR + 1, GVT_MAX_VGPU,
afe04fbe PG	326	GFP_KERNEL);
82d375d1	327	if (ret < 0)
1aa3834f	328	goto out_unlock;;
82d375d1 ZW	329
82d375d1 ZW	330	vgpu->id = ret;
1aa3834f	331	vgpu->sched_ctl.weight = conf->weight;
f25a49ab	332	mutex_init(&vgpu->vgpu_lock);
d6c6113b	333	mutex_init(&vgpu->dmabuf_lock);
e546e281	334	INIT_LIST_HEAD(&vgpu->dmabuf_obj_list_head);
e502a2af	335	INIT_RADIX_TREE(&vgpu->page_track_tree, GFP_KERNEL);
64e65f44	336	idr_init_base(&vgpu->object_idr, 1);
1aa3834f	337	intel_vgpu_init_cfg_space(vgpu, 1);
ba25d977	338	vgpu->d3_entered = false;
82d375d1	339
cdcc4347	340	ret = intel_vgpu_init_mmio(vgpu);
82d375d1	341	if (ret)
4e537891	342	goto out_clean_idr;
82d375d1	343
1aa3834f	344	ret = intel_vgpu_alloc_resource(vgpu, conf);
82d375d1 ZW	345	if (ret)
	346	goto out_clean_vgpu_mmio;
	347
	348	populate_pvinfo_page(vgpu);
	349
2707e444 ZW	350	ret = intel_vgpu_init_gtt(vgpu);
2707e444 ZW	351	if (ret)
62980cac	352	goto out_clean_vgpu_resource;
2707e444	353
4dff110b	354	ret = intel_vgpu_init_opregion(vgpu);
04d348ae	355	if (ret)
8f89743b	356	goto out_clean_gtt;
04d348ae	357
1aa3834f	358	ret = intel_vgpu_init_display(vgpu, conf->edid);
4dff110b XZ	359	if (ret)
	360	goto out_clean_opregion;
	361
874b6a91	362	ret = intel_vgpu_setup_submission(vgpu);
e4734057	363	if (ret)
ad1d3636	364	goto out_clean_display;
e4734057	365
4b63960e ZW	366	ret = intel_vgpu_init_sched_policy(vgpu);
4b63960e ZW	367	if (ret)
ad1d3636	368	goto out_clean_submission;
4b63960e	369
f8871ec8	370	intel_gvt_debugfs_add_vgpu(vgpu);
bc7b0be3	371
f9399b0e	372	ret = intel_gvt_set_opregion(vgpu);
b851adea TZ	373	if (ret)
	374	goto out_clean_sched_policy;
	375
4ceb06e7	376	if (IS_BROADWELL(dev_priv) \|\| IS_BROXTON(dev_priv))
f9399b0e	377	ret = intel_gvt_set_edid(vgpu, PORT_B);
4ceb06e7	378	else
f9399b0e	379	ret = intel_gvt_set_edid(vgpu, PORT_D);
39c68e87 HY	380	if (ret)
	381	goto out_clean_sched_policy;
	382
1aa3834f CH	383	intel_gvt_update_reg_whitelist(vgpu);
1aa3834f CH	384	mutex_unlock(&gvt->lock);
a5ddd2a9	385	return 0;
82d375d1	386
bc7b0be3 CD	387	out_clean_sched_policy:
bc7b0be3 CD	388	intel_vgpu_clean_sched_policy(vgpu);
ad1d3636	389	out_clean_submission:
874b6a91	390	intel_vgpu_clean_submission(vgpu);
8453d674 ZW	391	out_clean_display:
8453d674 ZW	392	intel_vgpu_clean_display(vgpu);
4dff110b XZ	393	out_clean_opregion:
4dff110b XZ	394	intel_vgpu_clean_opregion(vgpu);
4d60c5fd ZW	395	out_clean_gtt:
4d60c5fd ZW	396	intel_vgpu_clean_gtt(vgpu);
82d375d1 ZW	397	out_clean_vgpu_resource:
	398	intel_vgpu_free_resource(vgpu);
	399	out_clean_vgpu_mmio:
cdcc4347	400	intel_vgpu_clean_mmio(vgpu);
4e537891 JS	401	out_clean_idr:
4e537891 JS	402	idr_remove(&gvt->vgpu_idr, vgpu->id);
1aa3834f	403	out_unlock:
f25a49ab	404	mutex_unlock(&gvt->lock);
a5ddd2a9	405	return ret;
1f31c829	406	}
9ec1e66b JS	407
9ec1e66b JS	408	/**
cfe65f40 CD	409	* intel_gvt_reset_vgpu_locked - reset a virtual GPU by DMLR or GT reset
	410	* @vgpu: virtual GPU
	411	* @dmlr: vGPU Device Model Level Reset or GT Reset
	412	* @engine_mask: engines to reset for GT reset
	413	*
	414	* This function is called when user wants to reset a virtual GPU through
f25a49ab	415	* device model reset or GT reset. The caller should hold the vgpu lock.
cfe65f40 CD	416	*
	417	* vGPU Device Model Level Reset (DMLR) simulates the PCI level reset to reset
	418	* the whole vGPU to default state as when it is created. This vGPU function
	419	* is required both for functionary and security concerns.The ultimate goal
	420	* of vGPU FLR is that reuse a vGPU instance by virtual machines. When we
	421	* assign a vGPU to a virtual machine we must isse such reset first.
	422	*
	423	* Full GT Reset and Per-Engine GT Reset are soft reset flow for GPU engines
	424	* (Render, Blitter, Video, Video Enhancement). It is defined by GPU Spec.
	425	* Unlike the FLR, GT reset only reset particular resource of a vGPU per
	426	* the reset request. Guest driver can issue a GT reset by programming the
	427	* virtual GDRST register to reset specific virtual GPU engine or all
	428	* engines.
	429	*
	430	* The parameter dev_level is to identify if we will do DMLR or GT reset.
	431	* The parameter engine_mask is to specific the engines that need to be
	432	* resetted. If value ALL_ENGINES is given for engine_mask, it means
	433	* the caller requests a full GT reset that we will reset all virtual
	434	* GPU engines. For FLR, engine_mask is ignored.
	435	*/
	436	void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
3a891a62	437	intel_engine_mask_t engine_mask)
cfe65f40 CD	438	{
	439	struct intel_gvt *gvt = vgpu->gvt;
	440	struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
3a891a62	441	intel_engine_mask_t resetting_eng = dmlr ? ALL_ENGINES : engine_mask;
cfe65f40 CD	442
	443	gvt_dbg_core("------------------------------------------\n");
	444	gvt_dbg_core("resseting vgpu%d, dmlr %d, engine_mask %08x\n",
	445	vgpu->id, dmlr, engine_mask);
6184cc8d CD	446
6184cc8d CD	447	vgpu->resetting_eng = resetting_eng;
cfe65f40 CD	448
	449	intel_vgpu_stop_schedule(vgpu);
	450	/*
	451	* The current_vgpu will set to NULL after stopping the
	452	* scheduler when the reset is triggered by current vgpu.
	453	*/
	454	if (scheduler->current_vgpu == NULL) {
f25a49ab	455	mutex_unlock(&vgpu->vgpu_lock);
cfe65f40	456	intel_gvt_wait_vgpu_idle(vgpu);
f25a49ab	457	mutex_lock(&vgpu->vgpu_lock);
cfe65f40 CD	458	}
cfe65f40 CD	459
06bb372f	460	intel_vgpu_reset_submission(vgpu, resetting_eng);
cfe65f40 CD	461	/* full GPU reset or device model level reset */
cfe65f40 CD	462	if (engine_mask == ALL_ENGINES \|\| dmlr) {
7569a06d	463	intel_vgpu_select_submission_ops(vgpu, ALL_ENGINES, 0);
ba25d977 CX	464	if (engine_mask == ALL_ENGINES)
ba25d977 CX	465	intel_vgpu_invalidate_ppgtt(vgpu);
615c16a9	466	/fence will not be reset during virtual reset /
4d3e67bb	467	if (dmlr) {
ba25d977 CX	468	if(!vgpu->d3_entered) {
	469	intel_vgpu_invalidate_ppgtt(vgpu);
	470	intel_vgpu_destroy_all_ppgtt_mm(vgpu);
	471	}
	472	intel_vgpu_reset_ggtt(vgpu, true);
615c16a9	473	intel_vgpu_reset_resource(vgpu);
4d3e67bb	474	}
615c16a9	475
615c16a9	476	intel_vgpu_reset_mmio(vgpu, dmlr);
cfe65f40 CD	477	populate_pvinfo_page(vgpu);
cfe65f40 CD	478
fd64be63	479	if (dmlr) {
3eb55e6f	480	intel_vgpu_reset_display(vgpu);
cfe65f40	481	intel_vgpu_reset_cfg_space(vgpu);
fd64be63 MH	482	/* only reset the failsafe mode when dmlr reset */
fd64be63 MH	483	vgpu->failsafe = false;
ba25d977 CX	484	/*
	485	* PCI_D0 is set before dmlr, so reset d3_entered here
	486	* after done using.
	487	*/
	488	if(vgpu->d3_entered)
	489	vgpu->d3_entered = false;
9e7c0efa CX	490	else
9e7c0efa CX	491	vgpu->pv_notified = false;
fd64be63	492	}
cfe65f40 CD	493	}
cfe65f40 CD	494
6184cc8d	495	vgpu->resetting_eng = 0;
cfe65f40 CD	496	gvt_dbg_core("reset vgpu%d done\n", vgpu->id);
	497	gvt_dbg_core("------------------------------------------\n");
	498	}
	499
	500	/**
	501	* intel_gvt_reset_vgpu - reset a virtual GPU (Function Level)
9ec1e66b JS	502	* @vgpu: virtual GPU
	503	*
	504	* This function is called when user wants to reset a virtual GPU.
	505	*
	506	*/
	507	void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu)
	508	{
f25a49ab	509	mutex_lock(&vgpu->vgpu_lock);
cfe65f40	510	intel_gvt_reset_vgpu_locked(vgpu, true, 0);
f25a49ab	511	mutex_unlock(&vgpu->vgpu_lock);
9ec1e66b	512	}