[linux-2.6-block.git] / drivers / gpu / drm / i915 / gvt / sched_policy.c

/*
 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 * Authors:
 *    Anhua Xu
 *    Kevin Tian <kevin.tian@intel.com>
 *
 * Contributors:
 *    Min He <min.he@intel.com>
 *    Bing Niu <bing.niu@intel.com>
 *    Zhi Wang <zhi.a.wang@intel.com>
 *
 */

#include "i915_drv.h"
#include "gvt.h"

static bool vgpu_has_pending_workload(struct intel_vgpu *vgpu)
{
	enum intel_engine_id i;
	struct intel_engine_cs *engine;

	for_each_engine(engine, vgpu->gvt->dev_priv, i) {
		if (!list_empty(workload_q_head(vgpu, i)))
			return true;
	}

	return false;
}

struct vgpu_sched_data {
	struct list_head lru_list;
	struct intel_vgpu *vgpu;

	ktime_t sched_in_time;
	ktime_t sched_out_time;
	ktime_t sched_time;
	ktime_t left_ts;
	ktime_t allocated_ts;

	struct vgpu_sched_ctl sched_ctl;
};

struct gvt_sched_data {
	struct intel_gvt *gvt;
	struct hrtimer timer;
	unsigned long period;
	struct list_head lru_runq_head;
};

static void vgpu_update_timeslice(struct intel_vgpu *pre_vgpu)
{
	ktime_t delta_ts;
	struct vgpu_sched_data *vgpu_data = pre_vgpu->sched_data;

	delta_ts = vgpu_data->sched_out_time - vgpu_data->sched_in_time;

	vgpu_data->sched_time += delta_ts;
	vgpu_data->left_ts -= delta_ts;
}

#define GVT_TS_BALANCE_PERIOD_MS 100
#define GVT_TS_BALANCE_STAGE_NUM 10

static void gvt_balance_timeslice(struct gvt_sched_data *sched_data)
{
	struct vgpu_sched_data *vgpu_data;
	struct list_head *pos;
	static uint64_t stage_check;
	int stage = stage_check++ % GVT_TS_BALANCE_STAGE_NUM;

	/* The timeslice accumulation reset at stage 0, which is
	 * allocated again without adding previous debt.
	 */
	if (stage == 0) {
		int total_weight = 0;
		ktime_t fair_timeslice;

		list_for_each(pos, &sched_data->lru_runq_head) {
			vgpu_data = container_of(pos, struct vgpu_sched_data, lru_list);
			total_weight += vgpu_data->sched_ctl.weight;
		}

		list_for_each(pos, &sched_data->lru_runq_head) {
			vgpu_data = container_of(pos, struct vgpu_sched_data, lru_list);
			fair_timeslice = ms_to_ktime(GVT_TS_BALANCE_PERIOD_MS) *
						vgpu_data->sched_ctl.weight /
						total_weight;

			vgpu_data->allocated_ts = fair_timeslice;
			vgpu_data->left_ts = vgpu_data->allocated_ts;
		}
	} else {
		list_for_each(pos, &sched_data->lru_runq_head) {
			vgpu_data = container_of(pos, struct vgpu_sched_data, lru_list);

			/* timeslice for next 100ms should add the left/debt
			 * slice of previous stages.
			 */
			vgpu_data->left_ts += vgpu_data->allocated_ts;
		}
	}
}

static void try_to_schedule_next_vgpu(struct intel_gvt *gvt)
{
	struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
	enum intel_engine_id i;
	struct intel_engine_cs *engine;
	struct vgpu_sched_data *vgpu_data;
	ktime_t cur_time;

	/* no target to schedule */
	if (!scheduler->next_vgpu)
		return;

	gvt_dbg_sched("try to schedule next vgpu %d\n",
			scheduler->next_vgpu->id);

	/*
	 * after the flag is set, workload dispatch thread will
	 * stop dispatching workload for current vgpu
	 */
	scheduler->need_reschedule = true;

	/* still have uncompleted workload? */
	for_each_engine(engine, gvt->dev_priv, i) {
		if (scheduler->current_workload[i]) {
			gvt_dbg_sched("still have running workload\n");
			return;
		}
	}

	gvt_dbg_sched("switch to next vgpu %d\n",
			scheduler->next_vgpu->id);

	cur_time = ktime_get();
	if (scheduler->current_vgpu) {
		vgpu_data = scheduler->current_vgpu->sched_data;
		vgpu_data->sched_out_time = cur_time;
		vgpu_update_timeslice(scheduler->current_vgpu);
	}
	vgpu_data = scheduler->next_vgpu->sched_data;
	vgpu_data->sched_in_time = cur_time;

	/* switch current vgpu */
	scheduler->current_vgpu = scheduler->next_vgpu;
	scheduler->next_vgpu = NULL;

	scheduler->need_reschedule = false;

	/* wake up workload dispatch thread */
	for_each_engine(engine, gvt->dev_priv, i)
		wake_up(&scheduler->waitq[i]);
}

static struct intel_vgpu *find_busy_vgpu(struct gvt_sched_data *sched_data)
{
	struct vgpu_sched_data *vgpu_data;
	struct intel_vgpu *vgpu = NULL;
	struct list_head *head = &sched_data->lru_runq_head;
	struct list_head *pos;

	/* search a vgpu with pending workload */
	list_for_each(pos, head) {

		vgpu_data = container_of(pos, struct vgpu_sched_data, lru_list);
		if (!vgpu_has_pending_workload(vgpu_data->vgpu))
			continue;

		vgpu = vgpu_data->vgpu;
		break;
	}

	return vgpu;
}

/* in nanosecond */
#define GVT_DEFAULT_TIME_SLICE 1000000

static void tbs_sched_func(struct gvt_sched_data *sched_data)
{
	struct intel_gvt *gvt = sched_data->gvt;
	struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
	struct vgpu_sched_data *vgpu_data;
	struct intel_vgpu *vgpu = NULL;
	static uint64_t timer_check;

	if (!(timer_check++ % GVT_TS_BALANCE_PERIOD_MS))
		gvt_balance_timeslice(sched_data);

	/* no active vgpu or has already had a target */
	if (list_empty(&sched_data->lru_runq_head) || scheduler->next_vgpu)
		goto out;

	vgpu = find_busy_vgpu(sched_data);
	if (vgpu) {
		scheduler->next_vgpu = vgpu;

		/* Move the last used vGPU to the tail of lru_list */
		vgpu_data = vgpu->sched_data;
		list_del_init(&vgpu_data->lru_list);
		list_add_tail(&vgpu_data->lru_list,
				&sched_data->lru_runq_head);

		gvt_dbg_sched("pick next vgpu %d\n", vgpu->id);
	}
out:
	if (scheduler->next_vgpu) {
		gvt_dbg_sched("try to schedule next vgpu %d\n",
				scheduler->next_vgpu->id);
		try_to_schedule_next_vgpu(gvt);
	}
}

void intel_gvt_schedule(struct intel_gvt *gvt)
{
	struct gvt_sched_data *sched_data = gvt->scheduler.sched_data;

	mutex_lock(&gvt->lock);
	tbs_sched_func(sched_data);
	mutex_unlock(&gvt->lock);
}

static enum hrtimer_restart tbs_timer_fn(struct hrtimer *timer_data)
{
	struct gvt_sched_data *data;

	data = container_of(timer_data, struct gvt_sched_data, timer);

	intel_gvt_request_service(data->gvt, INTEL_GVT_REQUEST_SCHED);

	hrtimer_add_expires_ns(&data->timer, data->period);

	return HRTIMER_RESTART;
}

static int tbs_sched_init(struct intel_gvt *gvt)
{
	struct intel_gvt_workload_scheduler *scheduler =
		&gvt->scheduler;

	struct gvt_sched_data *data;

	data = kzalloc(sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	INIT_LIST_HEAD(&data->lru_runq_head);
	hrtimer_init(&data->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
	data->timer.function = tbs_timer_fn;
	data->period = GVT_DEFAULT_TIME_SLICE;
	data->gvt = gvt;

	scheduler->sched_data = data;

	return 0;
}

static void tbs_sched_clean(struct intel_gvt *gvt)
{
	struct intel_gvt_workload_scheduler *scheduler =
		&gvt->scheduler;
	struct gvt_sched_data *data = scheduler->sched_data;

	hrtimer_cancel(&data->timer);

	kfree(data);
	scheduler->sched_data = NULL;
}

static int tbs_sched_init_vgpu(struct intel_vgpu *vgpu)
{
	struct vgpu_sched_data *data;

	data = kzalloc(sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->sched_ctl.weight = vgpu->sched_ctl.weight;
	data->vgpu = vgpu;
	INIT_LIST_HEAD(&data->lru_list);

	vgpu->sched_data = data;

	return 0;
}

static void tbs_sched_clean_vgpu(struct intel_vgpu *vgpu)
{
	kfree(vgpu->sched_data);
	vgpu->sched_data = NULL;
}

static void tbs_sched_start_schedule(struct intel_vgpu *vgpu)
{
	struct gvt_sched_data *sched_data = vgpu->gvt->scheduler.sched_data;
	struct vgpu_sched_data *vgpu_data = vgpu->sched_data;

	if (!list_empty(&vgpu_data->lru_list))
		return;

	list_add_tail(&vgpu_data->lru_list, &sched_data->lru_runq_head);

	if (!hrtimer_active(&sched_data->timer))
		hrtimer_start(&sched_data->timer, ktime_add_ns(ktime_get(),
			sched_data->period), HRTIMER_MODE_ABS);
}

static void tbs_sched_stop_schedule(struct intel_vgpu *vgpu)
{
	struct vgpu_sched_data *vgpu_data = vgpu->sched_data;

	list_del_init(&vgpu_data->lru_list);
}

static struct intel_gvt_sched_policy_ops tbs_schedule_ops = {
	.init = tbs_sched_init,
	.clean = tbs_sched_clean,
	.init_vgpu = tbs_sched_init_vgpu,
	.clean_vgpu = tbs_sched_clean_vgpu,
	.start_schedule = tbs_sched_start_schedule,
	.stop_schedule = tbs_sched_stop_schedule,
};

int intel_gvt_init_sched_policy(struct intel_gvt *gvt)
{
	gvt->scheduler.sched_ops = &tbs_schedule_ops;

	return gvt->scheduler.sched_ops->init(gvt);
}

void intel_gvt_clean_sched_policy(struct intel_gvt *gvt)
{
	gvt->scheduler.sched_ops->clean(gvt);
}

int intel_vgpu_init_sched_policy(struct intel_vgpu *vgpu)
{
	return vgpu->gvt->scheduler.sched_ops->init_vgpu(vgpu);
}

void intel_vgpu_clean_sched_policy(struct intel_vgpu *vgpu)
{
	vgpu->gvt->scheduler.sched_ops->clean_vgpu(vgpu);
}

void intel_vgpu_start_schedule(struct intel_vgpu *vgpu)
{
	gvt_dbg_core("vgpu%d: start schedule\n", vgpu->id);

	vgpu->gvt->scheduler.sched_ops->start_schedule(vgpu);
}

void intel_vgpu_stop_schedule(struct intel_vgpu *vgpu)
{
	struct intel_gvt_workload_scheduler *scheduler =
		&vgpu->gvt->scheduler;

	gvt_dbg_core("vgpu%d: stop schedule\n", vgpu->id);

	scheduler->sched_ops->stop_schedule(vgpu);

	if (scheduler->next_vgpu == vgpu)
		scheduler->next_vgpu = NULL;

	if (scheduler->current_vgpu == vgpu) {
		/* stop workload dispatching */
		scheduler->need_reschedule = true;
		scheduler->current_vgpu = NULL;
	}
}
Commit	Line	Data
4b63960e ZW	1	/*
	2	* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	20	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	21	* SOFTWARE.
	22	*
	23	* Authors:
	24	* Anhua Xu
	25	* Kevin Tian <kevin.tian@intel.com>
	26	*
	27	* Contributors:
	28	* Min He <min.he@intel.com>
	29	* Bing Niu <bing.niu@intel.com>
	30	* Zhi Wang <zhi.a.wang@intel.com>
	31	*
	32	*/
	33
	34	#include "i915_drv.h"
feddf6e8	35	#include "gvt.h"
4b63960e ZW	36
	37	static bool vgpu_has_pending_workload(struct intel_vgpu *vgpu)
	38	{
0fac21e7 ZW	39	enum intel_engine_id i;
0fac21e7 ZW	40	struct intel_engine_cs *engine;
4b63960e	41
0fac21e7	42	for_each_engine(engine, vgpu->gvt->dev_priv, i) {
4b63960e ZW	43	if (!list_empty(workload_q_head(vgpu, i)))
	44	return true;
	45	}
	46
	47	return false;
	48	}
	49
f6504cce	50	struct vgpu_sched_data {
32356920	51	struct list_head lru_list;
f6504cce PG	52	struct intel_vgpu *vgpu;
	53
	54	ktime_t sched_in_time;
	55	ktime_t sched_out_time;
	56	ktime_t sched_time;
	57	ktime_t left_ts;
	58	ktime_t allocated_ts;
	59
	60	struct vgpu_sched_ctl sched_ctl;
	61	};
	62
	63	struct gvt_sched_data {
	64	struct intel_gvt *gvt;
	65	struct hrtimer timer;
	66	unsigned long period;
32356920	67	struct list_head lru_runq_head;
f6504cce PG	68	};
f6504cce PG	69
39d467c2 PG	70	static void vgpu_update_timeslice(struct intel_vgpu *pre_vgpu)
	71	{
	72	ktime_t delta_ts;
	73	struct vgpu_sched_data *vgpu_data = pre_vgpu->sched_data;
	74
	75	delta_ts = vgpu_data->sched_out_time - vgpu_data->sched_in_time;
	76
	77	vgpu_data->sched_time += delta_ts;
	78	vgpu_data->left_ts -= delta_ts;
	79	}
	80
	81	#define GVT_TS_BALANCE_PERIOD_MS 100
	82	#define GVT_TS_BALANCE_STAGE_NUM 10
	83
	84	static void gvt_balance_timeslice(struct gvt_sched_data *sched_data)
	85	{
	86	struct vgpu_sched_data *vgpu_data;
	87	struct list_head *pos;
	88	static uint64_t stage_check;
	89	int stage = stage_check++ % GVT_TS_BALANCE_STAGE_NUM;
	90
	91	/* The timeslice accumulation reset at stage 0, which is
	92	* allocated again without adding previous debt.
	93	*/
	94	if (stage == 0) {
	95	int total_weight = 0;
	96	ktime_t fair_timeslice;
	97
	98	list_for_each(pos, &sched_data->lru_runq_head) {
	99	vgpu_data = container_of(pos, struct vgpu_sched_data, lru_list);
	100	total_weight += vgpu_data->sched_ctl.weight;
	101	}
	102
	103	list_for_each(pos, &sched_data->lru_runq_head) {
	104	vgpu_data = container_of(pos, struct vgpu_sched_data, lru_list);
	105	fair_timeslice = ms_to_ktime(GVT_TS_BALANCE_PERIOD_MS) *
	106	vgpu_data->sched_ctl.weight /
	107	total_weight;
	108
	109	vgpu_data->allocated_ts = fair_timeslice;
	110	vgpu_data->left_ts = vgpu_data->allocated_ts;
	111	}
	112	} else {
	113	list_for_each(pos, &sched_data->lru_runq_head) {
	114	vgpu_data = container_of(pos, struct vgpu_sched_data, lru_list);
	115
	116	/* timeslice for next 100ms should add the left/debt
	117	* slice of previous stages.
	118	*/
	119	vgpu_data->left_ts += vgpu_data->allocated_ts;
	120	}
	121	}
	122	}
	123
4b63960e ZW	124	static void try_to_schedule_next_vgpu(struct intel_gvt *gvt)
	125	{
	126	struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
0fac21e7 ZW	127	enum intel_engine_id i;
0fac21e7 ZW	128	struct intel_engine_cs *engine;
f6504cce PG	129	struct vgpu_sched_data *vgpu_data;
f6504cce PG	130	ktime_t cur_time;
4b63960e ZW	131
	132	/* no target to schedule */
	133	if (!scheduler->next_vgpu)
	134	return;
	135
	136	gvt_dbg_sched("try to schedule next vgpu %d\n",
	137	scheduler->next_vgpu->id);
	138
	139	/*
	140	* after the flag is set, workload dispatch thread will
	141	* stop dispatching workload for current vgpu
	142	*/
	143	scheduler->need_reschedule = true;
	144
	145	/* still have uncompleted workload? */
0fac21e7	146	for_each_engine(engine, gvt->dev_priv, i) {
4b63960e ZW	147	if (scheduler->current_workload[i]) {
	148	gvt_dbg_sched("still have running workload\n");
	149	return;
	150	}
	151	}
	152
	153	gvt_dbg_sched("switch to next vgpu %d\n",
	154	scheduler->next_vgpu->id);
	155
f6504cce PG	156	cur_time = ktime_get();
	157	if (scheduler->current_vgpu) {
	158	vgpu_data = scheduler->current_vgpu->sched_data;
	159	vgpu_data->sched_out_time = cur_time;
39d467c2	160	vgpu_update_timeslice(scheduler->current_vgpu);
f6504cce PG	161	}
	162	vgpu_data = scheduler->next_vgpu->sched_data;
	163	vgpu_data->sched_in_time = cur_time;
	164
4b63960e ZW	165	/* switch current vgpu */
	166	scheduler->current_vgpu = scheduler->next_vgpu;
	167	scheduler->next_vgpu = NULL;
	168
	169	scheduler->need_reschedule = false;
	170
	171	/* wake up workload dispatch thread */
0fac21e7	172	for_each_engine(engine, gvt->dev_priv, i)
4b63960e ZW	173	wake_up(&scheduler->waitq[i]);
	174	}
	175
32356920	176	static struct intel_vgpu find_busy_vgpu(struct gvt_sched_data sched_data)
4b63960e	177	{
f6504cce	178	struct vgpu_sched_data *vgpu_data;
4b63960e	179	struct intel_vgpu *vgpu = NULL;
32356920 PG	180	struct list_head *head = &sched_data->lru_runq_head;
32356920 PG	181	struct list_head *pos;
4b63960e ZW	182
	183	/* search a vgpu with pending workload */
	184	list_for_each(pos, head) {
4b63960e	185
32356920	186	vgpu_data = container_of(pos, struct vgpu_sched_data, lru_list);
4b63960e ZW	187	if (!vgpu_has_pending_workload(vgpu_data->vgpu))
	188	continue;
	189
	190	vgpu = vgpu_data->vgpu;
	191	break;
	192	}
	193
32356920 PG	194	return vgpu;
	195	}
	196
	197	/* in nanosecond */
	198	#define GVT_DEFAULT_TIME_SLICE 1000000
	199
	200	static void tbs_sched_func(struct gvt_sched_data *sched_data)
	201	{
	202	struct intel_gvt *gvt = sched_data->gvt;
	203	struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
	204	struct vgpu_sched_data *vgpu_data;
	205	struct intel_vgpu *vgpu = NULL;
39d467c2 PG	206	static uint64_t timer_check;
	207
	208	if (!(timer_check++ % GVT_TS_BALANCE_PERIOD_MS))
	209	gvt_balance_timeslice(sched_data);
32356920 PG	210
	211	/* no active vgpu or has already had a target */
	212	if (list_empty(&sched_data->lru_runq_head) \|\| scheduler->next_vgpu)
	213	goto out;
	214
	215	vgpu = find_busy_vgpu(sched_data);
4b63960e ZW	216	if (vgpu) {
4b63960e ZW	217	scheduler->next_vgpu = vgpu;
32356920 PG	218
	219	/* Move the last used vGPU to the tail of lru_list */
	220	vgpu_data = vgpu->sched_data;
	221	list_del_init(&vgpu_data->lru_list);
	222	list_add_tail(&vgpu_data->lru_list,
	223	&sched_data->lru_runq_head);
	224
4b63960e ZW	225	gvt_dbg_sched("pick next vgpu %d\n", vgpu->id);
	226	}
	227	out:
	228	if (scheduler->next_vgpu) {
	229	gvt_dbg_sched("try to schedule next vgpu %d\n",
	230	scheduler->next_vgpu->id);
	231	try_to_schedule_next_vgpu(gvt);
	232	}
91d0101a	233	}
4b63960e	234
91d0101a PG	235	void intel_gvt_schedule(struct intel_gvt *gvt)
91d0101a PG	236	{
f6504cce	237	struct gvt_sched_data *sched_data = gvt->scheduler.sched_data;
4b63960e	238
91d0101a PG	239	mutex_lock(&gvt->lock);
91d0101a PG	240	tbs_sched_func(sched_data);
4b63960e ZW	241	mutex_unlock(&gvt->lock);
	242	}
	243
91d0101a PG	244	static enum hrtimer_restart tbs_timer_fn(struct hrtimer *timer_data)
91d0101a PG	245	{
f6504cce	246	struct gvt_sched_data *data;
91d0101a	247
f6504cce	248	data = container_of(timer_data, struct gvt_sched_data, timer);
91d0101a PG	249
	250	intel_gvt_request_service(data->gvt, INTEL_GVT_REQUEST_SCHED);
	251
	252	hrtimer_add_expires_ns(&data->timer, data->period);
	253
	254	return HRTIMER_RESTART;
	255	}
	256
4b63960e ZW	257	static int tbs_sched_init(struct intel_gvt *gvt)
	258	{
	259	struct intel_gvt_workload_scheduler *scheduler =
	260	&gvt->scheduler;
	261
f6504cce	262	struct gvt_sched_data *data;
4b63960e ZW	263
	264	data = kzalloc(sizeof(*data), GFP_KERNEL);
	265	if (!data)
	266	return -ENOMEM;
	267
32356920	268	INIT_LIST_HEAD(&data->lru_runq_head);
91d0101a PG	269	hrtimer_init(&data->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
91d0101a PG	270	data->timer.function = tbs_timer_fn;
4b63960e ZW	271	data->period = GVT_DEFAULT_TIME_SLICE;
	272	data->gvt = gvt;
	273
	274	scheduler->sched_data = data;
91d0101a	275
4b63960e ZW	276	return 0;
	277	}
	278
	279	static void tbs_sched_clean(struct intel_gvt *gvt)
	280	{
	281	struct intel_gvt_workload_scheduler *scheduler =
	282	&gvt->scheduler;
f6504cce	283	struct gvt_sched_data *data = scheduler->sched_data;
4b63960e	284
91d0101a PG	285	hrtimer_cancel(&data->timer);
91d0101a PG	286
4b63960e ZW	287	kfree(data);
	288	scheduler->sched_data = NULL;
	289	}
	290
	291	static int tbs_sched_init_vgpu(struct intel_vgpu *vgpu)
	292	{
f6504cce	293	struct vgpu_sched_data *data;
4b63960e ZW	294
	295	data = kzalloc(sizeof(*data), GFP_KERNEL);
	296	if (!data)
	297	return -ENOMEM;
	298
bc90d097	299	data->sched_ctl.weight = vgpu->sched_ctl.weight;
4b63960e	300	data->vgpu = vgpu;
32356920	301	INIT_LIST_HEAD(&data->lru_list);
4b63960e ZW	302
4b63960e ZW	303	vgpu->sched_data = data;
91d0101a	304
4b63960e ZW	305	return 0;
	306	}
	307
	308	static void tbs_sched_clean_vgpu(struct intel_vgpu *vgpu)
	309	{
	310	kfree(vgpu->sched_data);
	311	vgpu->sched_data = NULL;
	312	}
	313
	314	static void tbs_sched_start_schedule(struct intel_vgpu *vgpu)
	315	{
f6504cce PG	316	struct gvt_sched_data *sched_data = vgpu->gvt->scheduler.sched_data;
f6504cce PG	317	struct vgpu_sched_data *vgpu_data = vgpu->sched_data;
4b63960e	318
32356920	319	if (!list_empty(&vgpu_data->lru_list))
4b63960e ZW	320	return;
4b63960e ZW	321
32356920	322	list_add_tail(&vgpu_data->lru_list, &sched_data->lru_runq_head);
91d0101a PG	323
	324	if (!hrtimer_active(&sched_data->timer))
	325	hrtimer_start(&sched_data->timer, ktime_add_ns(ktime_get(),
	326	sched_data->period), HRTIMER_MODE_ABS);
4b63960e ZW	327	}
	328
	329	static void tbs_sched_stop_schedule(struct intel_vgpu *vgpu)
	330	{
f6504cce	331	struct vgpu_sched_data *vgpu_data = vgpu->sched_data;
4b63960e	332
32356920	333	list_del_init(&vgpu_data->lru_list);
4b63960e ZW	334	}
4b63960e ZW	335
999ccb40	336	static struct intel_gvt_sched_policy_ops tbs_schedule_ops = {
4b63960e ZW	337	.init = tbs_sched_init,
	338	.clean = tbs_sched_clean,
	339	.init_vgpu = tbs_sched_init_vgpu,
	340	.clean_vgpu = tbs_sched_clean_vgpu,
	341	.start_schedule = tbs_sched_start_schedule,
	342	.stop_schedule = tbs_sched_stop_schedule,
	343	};
	344
	345	int intel_gvt_init_sched_policy(struct intel_gvt *gvt)
	346	{
	347	gvt->scheduler.sched_ops = &tbs_schedule_ops;
	348
	349	return gvt->scheduler.sched_ops->init(gvt);
	350	}
	351
	352	void intel_gvt_clean_sched_policy(struct intel_gvt *gvt)
	353	{
	354	gvt->scheduler.sched_ops->clean(gvt);
	355	}
	356
	357	int intel_vgpu_init_sched_policy(struct intel_vgpu *vgpu)
	358	{
	359	return vgpu->gvt->scheduler.sched_ops->init_vgpu(vgpu);
	360	}
	361
	362	void intel_vgpu_clean_sched_policy(struct intel_vgpu *vgpu)
	363	{
	364	vgpu->gvt->scheduler.sched_ops->clean_vgpu(vgpu);
	365	}
	366
	367	void intel_vgpu_start_schedule(struct intel_vgpu *vgpu)
	368	{
	369	gvt_dbg_core("vgpu%d: start schedule\n", vgpu->id);
	370
	371	vgpu->gvt->scheduler.sched_ops->start_schedule(vgpu);
	372	}
	373
	374	void intel_vgpu_stop_schedule(struct intel_vgpu *vgpu)
	375	{
	376	struct intel_gvt_workload_scheduler *scheduler =
	377	&vgpu->gvt->scheduler;
	378
	379	gvt_dbg_core("vgpu%d: stop schedule\n", vgpu->id);
	380
	381	scheduler->sched_ops->stop_schedule(vgpu);
	382
	383	if (scheduler->next_vgpu == vgpu)
	384	scheduler->next_vgpu = NULL;
	385
	386	if (scheduler->current_vgpu == vgpu) {
	387	/* stop workload dispatching */
	388	scheduler->need_reschedule = true;
	389	scheduler->current_vgpu = NULL;
	390	}
	391	}