[linux-2.6-block.git] / drivers / gpu / drm / i915 / gvt / sched_policy.c

/*
 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 * Authors:
 *    Anhua Xu
 *    Kevin Tian <kevin.tian@intel.com>
 *
 * Contributors:
 *    Min He <min.he@intel.com>
 *    Bing Niu <bing.niu@intel.com>
 *    Zhi Wang <zhi.a.wang@intel.com>
 *
 */

#include "i915_drv.h"
#include "gvt.h"

static bool vgpu_has_pending_workload(struct intel_vgpu *vgpu)
{
	enum intel_engine_id i;
	struct intel_engine_cs *engine;

	for_each_engine(engine, vgpu->gvt->gt, i) {
		if (!list_empty(workload_q_head(vgpu, engine)))
			return true;
	}

	return false;
}

/* We give 2 seconds higher prio for vGPU during start */
#define GVT_SCHED_VGPU_PRI_TIME  2

struct vgpu_sched_data {
	struct list_head lru_list;
	struct intel_vgpu *vgpu;
	bool active;
	bool pri_sched;
	ktime_t pri_time;
	ktime_t sched_in_time;
	ktime_t sched_time;
	ktime_t left_ts;
	ktime_t allocated_ts;

	struct vgpu_sched_ctl sched_ctl;
};

struct gvt_sched_data {
	struct intel_gvt *gvt;
	struct hrtimer timer;
	unsigned long period;
	struct list_head lru_runq_head;
	ktime_t expire_time;
};

static void vgpu_update_timeslice(struct intel_vgpu *vgpu, ktime_t cur_time)
{
	ktime_t delta_ts;
	struct vgpu_sched_data *vgpu_data;

	if (!vgpu || vgpu == vgpu->gvt->idle_vgpu)
		return;

	vgpu_data = vgpu->sched_data;
	delta_ts = ktime_sub(cur_time, vgpu_data->sched_in_time);
	vgpu_data->sched_time = ktime_add(vgpu_data->sched_time, delta_ts);
	vgpu_data->left_ts = ktime_sub(vgpu_data->left_ts, delta_ts);
	vgpu_data->sched_in_time = cur_time;
}

#define GVT_TS_BALANCE_PERIOD_MS 100
#define GVT_TS_BALANCE_STAGE_NUM 10

static void gvt_balance_timeslice(struct gvt_sched_data *sched_data)
{
	struct vgpu_sched_data *vgpu_data;
	struct list_head *pos;
	static u64 stage_check;
	int stage = stage_check++ % GVT_TS_BALANCE_STAGE_NUM;

	/* The timeslice accumulation reset at stage 0, which is
	 * allocated again without adding previous debt.
	 */
	if (stage == 0) {
		int total_weight = 0;
		ktime_t fair_timeslice;

		list_for_each(pos, &sched_data->lru_runq_head) {
			vgpu_data = container_of(pos, struct vgpu_sched_data, lru_list);
			total_weight += vgpu_data->sched_ctl.weight;
		}

		list_for_each(pos, &sched_data->lru_runq_head) {
			vgpu_data = container_of(pos, struct vgpu_sched_data, lru_list);
			fair_timeslice = ktime_divns(ms_to_ktime(GVT_TS_BALANCE_PERIOD_MS),
						     total_weight) * vgpu_data->sched_ctl.weight;

			vgpu_data->allocated_ts = fair_timeslice;
			vgpu_data->left_ts = vgpu_data->allocated_ts;
		}
	} else {
		list_for_each(pos, &sched_data->lru_runq_head) {
			vgpu_data = container_of(pos, struct vgpu_sched_data, lru_list);

			/* timeslice for next 100ms should add the left/debt
			 * slice of previous stages.
			 */
			vgpu_data->left_ts += vgpu_data->allocated_ts;
		}
	}
}

static void try_to_schedule_next_vgpu(struct intel_gvt *gvt)
{
	struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
	enum intel_engine_id i;
	struct intel_engine_cs *engine;
	struct vgpu_sched_data *vgpu_data;
	ktime_t cur_time;

	/* no need to schedule if next_vgpu is the same with current_vgpu,
	 * let scheduler chose next_vgpu again by setting it to NULL.
	 */
	if (scheduler->next_vgpu == scheduler->current_vgpu) {
		scheduler->next_vgpu = NULL;
		return;
	}

	/*
	 * after the flag is set, workload dispatch thread will
	 * stop dispatching workload for current vgpu
	 */
	scheduler->need_reschedule = true;

	/* still have uncompleted workload? */
	for_each_engine(engine, gvt->gt, i) {
		if (scheduler->current_workload[engine->id])
			return;
	}

	cur_time = ktime_get();
	vgpu_update_timeslice(scheduler->current_vgpu, cur_time);
	vgpu_data = scheduler->next_vgpu->sched_data;
	vgpu_data->sched_in_time = cur_time;

	/* switch current vgpu */
	scheduler->current_vgpu = scheduler->next_vgpu;
	scheduler->next_vgpu = NULL;

	scheduler->need_reschedule = false;

	/* wake up workload dispatch thread */
	for_each_engine(engine, gvt->gt, i)
		wake_up(&scheduler->waitq[engine->id]);
}

static struct intel_vgpu *find_busy_vgpu(struct gvt_sched_data *sched_data)
{
	struct vgpu_sched_data *vgpu_data;
	struct intel_vgpu *vgpu = NULL;
	struct list_head *head = &sched_data->lru_runq_head;
	struct list_head *pos;

	/* search a vgpu with pending workload */
	list_for_each(pos, head) {

		vgpu_data = container_of(pos, struct vgpu_sched_data, lru_list);
		if (!vgpu_has_pending_workload(vgpu_data->vgpu))
			continue;

		if (vgpu_data->pri_sched) {
			if (ktime_before(ktime_get(), vgpu_data->pri_time)) {
				vgpu = vgpu_data->vgpu;
				break;
			} else
				vgpu_data->pri_sched = false;
		}

		/* Return the vGPU only if it has time slice left */
		if (vgpu_data->left_ts > 0) {
			vgpu = vgpu_data->vgpu;
			break;
		}
	}

	return vgpu;
}

/* in nanosecond */
#define GVT_DEFAULT_TIME_SLICE 1000000

static void tbs_sched_func(struct gvt_sched_data *sched_data)
{
	struct intel_gvt *gvt = sched_data->gvt;
	struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
	struct vgpu_sched_data *vgpu_data;
	struct intel_vgpu *vgpu = NULL;

	/* no active vgpu or has already had a target */
	if (list_empty(&sched_data->lru_runq_head) || scheduler->next_vgpu)
		goto out;

	vgpu = find_busy_vgpu(sched_data);
	if (vgpu) {
		scheduler->next_vgpu = vgpu;
		vgpu_data = vgpu->sched_data;
		if (!vgpu_data->pri_sched) {
			/* Move the last used vGPU to the tail of lru_list */
			list_del_init(&vgpu_data->lru_list);
			list_add_tail(&vgpu_data->lru_list,
				      &sched_data->lru_runq_head);
		}
	} else {
		scheduler->next_vgpu = gvt->idle_vgpu;
	}
out:
	if (scheduler->next_vgpu)
		try_to_schedule_next_vgpu(gvt);
}

void intel_gvt_schedule(struct intel_gvt *gvt)
{
	struct gvt_sched_data *sched_data = gvt->scheduler.sched_data;
	ktime_t cur_time;

	mutex_lock(&gvt->sched_lock);
	cur_time = ktime_get();

	if (test_and_clear_bit(INTEL_GVT_REQUEST_SCHED,
				(void *)&gvt->service_request)) {
		if (cur_time >= sched_data->expire_time) {
			gvt_balance_timeslice(sched_data);
			sched_data->expire_time = ktime_add_ms(
				cur_time, GVT_TS_BALANCE_PERIOD_MS);
		}
	}
	clear_bit(INTEL_GVT_REQUEST_EVENT_SCHED, (void *)&gvt->service_request);

	vgpu_update_timeslice(gvt->scheduler.current_vgpu, cur_time);
	tbs_sched_func(sched_data);

	mutex_unlock(&gvt->sched_lock);
}

static enum hrtimer_restart tbs_timer_fn(struct hrtimer *timer_data)
{
	struct gvt_sched_data *data;

	data = container_of(timer_data, struct gvt_sched_data, timer);

	intel_gvt_request_service(data->gvt, INTEL_GVT_REQUEST_SCHED);

	hrtimer_add_expires_ns(&data->timer, data->period);

	return HRTIMER_RESTART;
}

static int tbs_sched_init(struct intel_gvt *gvt)
{
	struct intel_gvt_workload_scheduler *scheduler =
		&gvt->scheduler;

	struct gvt_sched_data *data;

	data = kzalloc(sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	INIT_LIST_HEAD(&data->lru_runq_head);
	hrtimer_init(&data->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
	data->timer.function = tbs_timer_fn;
	data->period = GVT_DEFAULT_TIME_SLICE;
	data->gvt = gvt;

	scheduler->sched_data = data;

	return 0;
}

static void tbs_sched_clean(struct intel_gvt *gvt)
{
	struct intel_gvt_workload_scheduler *scheduler =
		&gvt->scheduler;
	struct gvt_sched_data *data = scheduler->sched_data;

	hrtimer_cancel(&data->timer);

	kfree(data);
	scheduler->sched_data = NULL;
}

static int tbs_sched_init_vgpu(struct intel_vgpu *vgpu)
{
	struct vgpu_sched_data *data;

	data = kzalloc(sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->sched_ctl.weight = vgpu->sched_ctl.weight;
	data->vgpu = vgpu;
	INIT_LIST_HEAD(&data->lru_list);

	vgpu->sched_data = data;

	return 0;
}

static void tbs_sched_clean_vgpu(struct intel_vgpu *vgpu)
{
	struct intel_gvt *gvt = vgpu->gvt;
	struct gvt_sched_data *sched_data = gvt->scheduler.sched_data;

	kfree(vgpu->sched_data);
	vgpu->sched_data = NULL;

	/* this vgpu id has been removed */
	if (idr_is_empty(&gvt->vgpu_idr))
		hrtimer_cancel(&sched_data->timer);
}

static void tbs_sched_start_schedule(struct intel_vgpu *vgpu)
{
	struct gvt_sched_data *sched_data = vgpu->gvt->scheduler.sched_data;
	struct vgpu_sched_data *vgpu_data = vgpu->sched_data;
	ktime_t now;

	if (!list_empty(&vgpu_data->lru_list))
		return;

	now = ktime_get();
	vgpu_data->pri_time = ktime_add(now,
					ktime_set(GVT_SCHED_VGPU_PRI_TIME, 0));
	vgpu_data->pri_sched = true;

	list_add(&vgpu_data->lru_list, &sched_data->lru_runq_head);

	if (!hrtimer_active(&sched_data->timer))
		hrtimer_start(&sched_data->timer, ktime_add_ns(ktime_get(),
			sched_data->period), HRTIMER_MODE_ABS);
	vgpu_data->active = true;
}

static void tbs_sched_stop_schedule(struct intel_vgpu *vgpu)
{
	struct vgpu_sched_data *vgpu_data = vgpu->sched_data;

	list_del_init(&vgpu_data->lru_list);
	vgpu_data->active = false;
}

static const struct intel_gvt_sched_policy_ops tbs_schedule_ops = {
	.init = tbs_sched_init,
	.clean = tbs_sched_clean,
	.init_vgpu = tbs_sched_init_vgpu,
	.clean_vgpu = tbs_sched_clean_vgpu,
	.start_schedule = tbs_sched_start_schedule,
	.stop_schedule = tbs_sched_stop_schedule,
};

int intel_gvt_init_sched_policy(struct intel_gvt *gvt)
{
	int ret;

	mutex_lock(&gvt->sched_lock);
	gvt->scheduler.sched_ops = &tbs_schedule_ops;
	ret = gvt->scheduler.sched_ops->init(gvt);
	mutex_unlock(&gvt->sched_lock);

	return ret;
}

void intel_gvt_clean_sched_policy(struct intel_gvt *gvt)
{
	mutex_lock(&gvt->sched_lock);
	gvt->scheduler.sched_ops->clean(gvt);
	mutex_unlock(&gvt->sched_lock);
}

/* for per-vgpu scheduler policy, there are 2 per-vgpu data:
 * sched_data, and sched_ctl. We see these 2 data as part of
 * the global scheduler which are proteced by gvt->sched_lock.
 * Caller should make their decision if the vgpu_lock should
 * be hold outside.
 */

int intel_vgpu_init_sched_policy(struct intel_vgpu *vgpu)
{
	int ret;

	mutex_lock(&vgpu->gvt->sched_lock);
	ret = vgpu->gvt->scheduler.sched_ops->init_vgpu(vgpu);
	mutex_unlock(&vgpu->gvt->sched_lock);

	return ret;
}

void intel_vgpu_clean_sched_policy(struct intel_vgpu *vgpu)
{
	mutex_lock(&vgpu->gvt->sched_lock);
	vgpu->gvt->scheduler.sched_ops->clean_vgpu(vgpu);
	mutex_unlock(&vgpu->gvt->sched_lock);
}

void intel_vgpu_start_schedule(struct intel_vgpu *vgpu)
{
	struct vgpu_sched_data *vgpu_data = vgpu->sched_data;

	mutex_lock(&vgpu->gvt->sched_lock);
	if (!vgpu_data->active) {
		gvt_dbg_core("vgpu%d: start schedule\n", vgpu->id);
		vgpu->gvt->scheduler.sched_ops->start_schedule(vgpu);
	}
	mutex_unlock(&vgpu->gvt->sched_lock);
}

void intel_gvt_kick_schedule(struct intel_gvt *gvt)
{
	mutex_lock(&gvt->sched_lock);
	intel_gvt_request_service(gvt, INTEL_GVT_REQUEST_EVENT_SCHED);
	mutex_unlock(&gvt->sched_lock);
}

void intel_vgpu_stop_schedule(struct intel_vgpu *vgpu)
{
	struct intel_gvt_workload_scheduler *scheduler =
		&vgpu->gvt->scheduler;
	struct vgpu_sched_data *vgpu_data = vgpu->sched_data;
	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
	struct intel_engine_cs *engine;
	enum intel_engine_id id;

	if (!vgpu_data->active)
		return;

	gvt_dbg_core("vgpu%d: stop schedule\n", vgpu->id);

	mutex_lock(&vgpu->gvt->sched_lock);
	scheduler->sched_ops->stop_schedule(vgpu);

	if (scheduler->next_vgpu == vgpu)
		scheduler->next_vgpu = NULL;

	if (scheduler->current_vgpu == vgpu) {
		/* stop workload dispatching */
		scheduler->need_reschedule = true;
		scheduler->current_vgpu = NULL;
	}

	intel_runtime_pm_get(&dev_priv->runtime_pm);
	spin_lock_bh(&scheduler->mmio_context_lock);
	for_each_engine(engine, vgpu->gvt->gt, id) {
		if (scheduler->engine_owner[engine->id] == vgpu) {
			intel_gvt_switch_mmio(vgpu, NULL, engine);
			scheduler->engine_owner[engine->id] = NULL;
		}
	}
	spin_unlock_bh(&scheduler->mmio_context_lock);
	intel_runtime_pm_put_unchecked(&dev_priv->runtime_pm);
	mutex_unlock(&vgpu->gvt->sched_lock);
}
Commit	Line	Data
4b63960e ZW	1	/*
	2	* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	20	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	21	* SOFTWARE.
	22	*
	23	* Authors:
	24	* Anhua Xu
	25	* Kevin Tian <kevin.tian@intel.com>
	26	*
	27	* Contributors:
	28	* Min He <min.he@intel.com>
	29	* Bing Niu <bing.niu@intel.com>
	30	* Zhi Wang <zhi.a.wang@intel.com>
	31	*
	32	*/
	33
	34	#include "i915_drv.h"
feddf6e8	35	#include "gvt.h"
4b63960e ZW	36
	37	static bool vgpu_has_pending_workload(struct intel_vgpu *vgpu)
	38	{
0fac21e7 ZW	39	enum intel_engine_id i;
0fac21e7 ZW	40	struct intel_engine_cs *engine;
4b63960e	41
a61ac1e7	42	for_each_engine(engine, vgpu->gvt->gt, i) {
8fde4107	43	if (!list_empty(workload_q_head(vgpu, engine)))
4b63960e ZW	44	return true;
	45	}
	46
	47	return false;
	48	}
	49
54ff01fd ZW	50	/* We give 2 seconds higher prio for vGPU during start */
	51	#define GVT_SCHED_VGPU_PRI_TIME 2
	52
f6504cce	53	struct vgpu_sched_data {
32356920	54	struct list_head lru_list;
f6504cce	55	struct intel_vgpu *vgpu;
9212b13f	56	bool active;
54ff01fd ZW	57	bool pri_sched;
54ff01fd ZW	58	ktime_t pri_time;
f6504cce	59	ktime_t sched_in_time;
f6504cce PG	60	ktime_t sched_time;
	61	ktime_t left_ts;
	62	ktime_t allocated_ts;
	63
	64	struct vgpu_sched_ctl sched_ctl;
	65	};
	66
	67	struct gvt_sched_data {
	68	struct intel_gvt *gvt;
	69	struct hrtimer timer;
	70	unsigned long period;
32356920	71	struct list_head lru_runq_head;
292bb0d3	72	ktime_t expire_time;
f6504cce PG	73	};
f6504cce PG	74
89babe7c	75	static void vgpu_update_timeslice(struct intel_vgpu *vgpu, ktime_t cur_time)
39d467c2 PG	76	{
39d467c2 PG	77	ktime_t delta_ts;
89babe7c	78	struct vgpu_sched_data *vgpu_data;
39d467c2	79
89babe7c ZG	80	if (!vgpu \|\| vgpu == vgpu->gvt->idle_vgpu)
89babe7c ZG	81	return;
39d467c2	82
89babe7c ZG	83	vgpu_data = vgpu->sched_data;
	84	delta_ts = ktime_sub(cur_time, vgpu_data->sched_in_time);
	85	vgpu_data->sched_time = ktime_add(vgpu_data->sched_time, delta_ts);
	86	vgpu_data->left_ts = ktime_sub(vgpu_data->left_ts, delta_ts);
	87	vgpu_data->sched_in_time = cur_time;
39d467c2 PG	88	}
	89
	90	#define GVT_TS_BALANCE_PERIOD_MS 100
	91	#define GVT_TS_BALANCE_STAGE_NUM 10
	92
	93	static void gvt_balance_timeslice(struct gvt_sched_data *sched_data)
	94	{
	95	struct vgpu_sched_data *vgpu_data;
	96	struct list_head *pos;
2e679d48	97	static u64 stage_check;
39d467c2 PG	98	int stage = stage_check++ % GVT_TS_BALANCE_STAGE_NUM;
	99
	100	/* The timeslice accumulation reset at stage 0, which is
	101	* allocated again without adding previous debt.
	102	*/
	103	if (stage == 0) {
	104	int total_weight = 0;
	105	ktime_t fair_timeslice;
	106
	107	list_for_each(pos, &sched_data->lru_runq_head) {
	108	vgpu_data = container_of(pos, struct vgpu_sched_data, lru_list);
	109	total_weight += vgpu_data->sched_ctl.weight;
	110	}
	111
	112	list_for_each(pos, &sched_data->lru_runq_head) {
	113	vgpu_data = container_of(pos, struct vgpu_sched_data, lru_list);
98039845 ZW	114	fair_timeslice = ktime_divns(ms_to_ktime(GVT_TS_BALANCE_PERIOD_MS),
98039845 ZW	115	total_weight) * vgpu_data->sched_ctl.weight;
39d467c2 PG	116
	117	vgpu_data->allocated_ts = fair_timeslice;
	118	vgpu_data->left_ts = vgpu_data->allocated_ts;
	119	}
	120	} else {
	121	list_for_each(pos, &sched_data->lru_runq_head) {
	122	vgpu_data = container_of(pos, struct vgpu_sched_data, lru_list);
	123
	124	/* timeslice for next 100ms should add the left/debt
	125	* slice of previous stages.
	126	*/
	127	vgpu_data->left_ts += vgpu_data->allocated_ts;
	128	}
	129	}
	130	}
	131
4b63960e ZW	132	static void try_to_schedule_next_vgpu(struct intel_gvt *gvt)
	133	{
	134	struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
0fac21e7 ZW	135	enum intel_engine_id i;
0fac21e7 ZW	136	struct intel_engine_cs *engine;
f6504cce PG	137	struct vgpu_sched_data *vgpu_data;
f6504cce PG	138	ktime_t cur_time;
4b63960e	139
ae157902 PG	140	/* no need to schedule if next_vgpu is the same with current_vgpu,
	141	* let scheduler chose next_vgpu again by setting it to NULL.
	142	*/
	143	if (scheduler->next_vgpu == scheduler->current_vgpu) {
	144	scheduler->next_vgpu = NULL;
4b63960e	145	return;
ae157902	146	}
4b63960e	147
4b63960e ZW	148	/*
	149	* after the flag is set, workload dispatch thread will
	150	* stop dispatching workload for current vgpu
	151	*/
	152	scheduler->need_reschedule = true;
	153
	154	/* still have uncompleted workload? */
a61ac1e7 CW	155	for_each_engine(engine, gvt->gt, i) {
a61ac1e7 CW	156	if (scheduler->current_workload[engine->id])
4b63960e	157	return;
4b63960e ZW	158	}
4b63960e ZW	159
f6504cce	160	cur_time = ktime_get();
89babe7c	161	vgpu_update_timeslice(scheduler->current_vgpu, cur_time);
f6504cce PG	162	vgpu_data = scheduler->next_vgpu->sched_data;
	163	vgpu_data->sched_in_time = cur_time;
	164
4b63960e ZW	165	/* switch current vgpu */
	166	scheduler->current_vgpu = scheduler->next_vgpu;
	167	scheduler->next_vgpu = NULL;
	168
	169	scheduler->need_reschedule = false;
	170
	171	/* wake up workload dispatch thread */
a61ac1e7 CW	172	for_each_engine(engine, gvt->gt, i)
a61ac1e7 CW	173	wake_up(&scheduler->waitq[engine->id]);
4b63960e ZW	174	}
4b63960e ZW	175
32356920	176	static struct intel_vgpu find_busy_vgpu(struct gvt_sched_data sched_data)
4b63960e	177	{
f6504cce	178	struct vgpu_sched_data *vgpu_data;
4b63960e	179	struct intel_vgpu *vgpu = NULL;
32356920 PG	180	struct list_head *head = &sched_data->lru_runq_head;
32356920 PG	181	struct list_head *pos;
4b63960e ZW	182
	183	/* search a vgpu with pending workload */
	184	list_for_each(pos, head) {
4b63960e	185
32356920	186	vgpu_data = container_of(pos, struct vgpu_sched_data, lru_list);
4b63960e ZW	187	if (!vgpu_has_pending_workload(vgpu_data->vgpu))
	188	continue;
	189
54ff01fd ZW	190	if (vgpu_data->pri_sched) {
	191	if (ktime_before(ktime_get(), vgpu_data->pri_time)) {
	192	vgpu = vgpu_data->vgpu;
	193	break;
	194	} else
	195	vgpu_data->pri_sched = false;
	196	}
	197
b35f34d1 PG	198	/* Return the vGPU only if it has time slice left */
	199	if (vgpu_data->left_ts > 0) {
	200	vgpu = vgpu_data->vgpu;
	201	break;
	202	}
4b63960e ZW	203	}
4b63960e ZW	204
32356920 PG	205	return vgpu;
	206	}
	207
	208	/* in nanosecond */
	209	#define GVT_DEFAULT_TIME_SLICE 1000000
	210
	211	static void tbs_sched_func(struct gvt_sched_data *sched_data)
	212	{
	213	struct intel_gvt *gvt = sched_data->gvt;
	214	struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
	215	struct vgpu_sched_data *vgpu_data;
	216	struct intel_vgpu *vgpu = NULL;
54ff01fd	217
32356920 PG	218	/* no active vgpu or has already had a target */
	219	if (list_empty(&sched_data->lru_runq_head) \|\| scheduler->next_vgpu)
	220	goto out;
	221
	222	vgpu = find_busy_vgpu(sched_data);
4b63960e ZW	223	if (vgpu) {
4b63960e ZW	224	scheduler->next_vgpu = vgpu;
32356920	225	vgpu_data = vgpu->sched_data;
54ff01fd ZW	226	if (!vgpu_data->pri_sched) {
	227	/* Move the last used vGPU to the tail of lru_list */
	228	list_del_init(&vgpu_data->lru_list);
	229	list_add_tail(&vgpu_data->lru_list,
	230	&sched_data->lru_runq_head);
	231	}
b35f34d1 PG	232	} else {
b35f34d1 PG	233	scheduler->next_vgpu = gvt->idle_vgpu;
4b63960e ZW	234	}
4b63960e ZW	235	out:
0b063bd3	236	if (scheduler->next_vgpu)
4b63960e	237	try_to_schedule_next_vgpu(gvt);
91d0101a	238	}
4b63960e	239
91d0101a PG	240	void intel_gvt_schedule(struct intel_gvt *gvt)
91d0101a PG	241	{
f6504cce	242	struct gvt_sched_data *sched_data = gvt->scheduler.sched_data;
89babe7c	243	ktime_t cur_time;
4b63960e	244
9a512e23	245	mutex_lock(&gvt->sched_lock);
89babe7c	246	cur_time = ktime_get();
c713cb2f PG	247
	248	if (test_and_clear_bit(INTEL_GVT_REQUEST_SCHED,
	249	(void *)&gvt->service_request)) {
292bb0d3	250	if (cur_time >= sched_data->expire_time) {
c713cb2f	251	gvt_balance_timeslice(sched_data);
292bb0d3 ZG	252	sched_data->expire_time = ktime_add_ms(
	253	cur_time, GVT_TS_BALANCE_PERIOD_MS);
	254	}
c713cb2f PG	255	}
	256	clear_bit(INTEL_GVT_REQUEST_EVENT_SCHED, (void *)&gvt->service_request);
	257
89babe7c	258	vgpu_update_timeslice(gvt->scheduler.current_vgpu, cur_time);
91d0101a	259	tbs_sched_func(sched_data);
c713cb2f	260
9a512e23	261	mutex_unlock(&gvt->sched_lock);
4b63960e ZW	262	}
4b63960e ZW	263
91d0101a PG	264	static enum hrtimer_restart tbs_timer_fn(struct hrtimer *timer_data)
91d0101a PG	265	{
f6504cce	266	struct gvt_sched_data *data;
91d0101a	267
f6504cce	268	data = container_of(timer_data, struct gvt_sched_data, timer);
91d0101a PG	269
	270	intel_gvt_request_service(data->gvt, INTEL_GVT_REQUEST_SCHED);
	271
	272	hrtimer_add_expires_ns(&data->timer, data->period);
	273
	274	return HRTIMER_RESTART;
	275	}
	276
4b63960e ZW	277	static int tbs_sched_init(struct intel_gvt *gvt)
	278	{
	279	struct intel_gvt_workload_scheduler *scheduler =
	280	&gvt->scheduler;
	281
f6504cce	282	struct gvt_sched_data *data;
4b63960e ZW	283
	284	data = kzalloc(sizeof(*data), GFP_KERNEL);
	285	if (!data)
	286	return -ENOMEM;
	287
32356920	288	INIT_LIST_HEAD(&data->lru_runq_head);
91d0101a PG	289	hrtimer_init(&data->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
91d0101a PG	290	data->timer.function = tbs_timer_fn;
4b63960e ZW	291	data->period = GVT_DEFAULT_TIME_SLICE;
	292	data->gvt = gvt;
	293
	294	scheduler->sched_data = data;
91d0101a	295
4b63960e ZW	296	return 0;
	297	}
	298
	299	static void tbs_sched_clean(struct intel_gvt *gvt)
	300	{
	301	struct intel_gvt_workload_scheduler *scheduler =
	302	&gvt->scheduler;
f6504cce	303	struct gvt_sched_data *data = scheduler->sched_data;
4b63960e	304
91d0101a PG	305	hrtimer_cancel(&data->timer);
91d0101a PG	306
4b63960e ZW	307	kfree(data);
	308	scheduler->sched_data = NULL;
	309	}
	310
	311	static int tbs_sched_init_vgpu(struct intel_vgpu *vgpu)
	312	{
f6504cce	313	struct vgpu_sched_data *data;
4b63960e ZW	314
	315	data = kzalloc(sizeof(*data), GFP_KERNEL);
	316	if (!data)
	317	return -ENOMEM;
	318
bc90d097	319	data->sched_ctl.weight = vgpu->sched_ctl.weight;
4b63960e	320	data->vgpu = vgpu;
32356920	321	INIT_LIST_HEAD(&data->lru_list);
4b63960e ZW	322
4b63960e ZW	323	vgpu->sched_data = data;
91d0101a	324
4b63960e ZW	325	return 0;
	326	}
	327
	328	static void tbs_sched_clean_vgpu(struct intel_vgpu *vgpu)
	329	{
61a66947 ZW	330	struct intel_gvt *gvt = vgpu->gvt;
	331	struct gvt_sched_data *sched_data = gvt->scheduler.sched_data;
	332
4b63960e ZW	333	kfree(vgpu->sched_data);
4b63960e ZW	334	vgpu->sched_data = NULL;
61a66947 ZW	335
	336	/* this vgpu id has been removed */
	337	if (idr_is_empty(&gvt->vgpu_idr))
	338	hrtimer_cancel(&sched_data->timer);
4b63960e ZW	339	}
	340
	341	static void tbs_sched_start_schedule(struct intel_vgpu *vgpu)
	342	{
f6504cce PG	343	struct gvt_sched_data *sched_data = vgpu->gvt->scheduler.sched_data;
f6504cce PG	344	struct vgpu_sched_data *vgpu_data = vgpu->sched_data;
54ff01fd	345	ktime_t now;
4b63960e	346
32356920	347	if (!list_empty(&vgpu_data->lru_list))
4b63960e ZW	348	return;
4b63960e ZW	349
54ff01fd ZW	350	now = ktime_get();
	351	vgpu_data->pri_time = ktime_add(now,
	352	ktime_set(GVT_SCHED_VGPU_PRI_TIME, 0));
	353	vgpu_data->pri_sched = true;
	354
	355	list_add(&vgpu_data->lru_list, &sched_data->lru_runq_head);
91d0101a PG	356
	357	if (!hrtimer_active(&sched_data->timer))
	358	hrtimer_start(&sched_data->timer, ktime_add_ns(ktime_get(),
	359	sched_data->period), HRTIMER_MODE_ABS);
9212b13f	360	vgpu_data->active = true;
4b63960e ZW	361	}
	362
	363	static void tbs_sched_stop_schedule(struct intel_vgpu *vgpu)
	364	{
f6504cce	365	struct vgpu_sched_data *vgpu_data = vgpu->sched_data;
4b63960e	366
32356920	367	list_del_init(&vgpu_data->lru_list);
9212b13f	368	vgpu_data->active = false;
4b63960e ZW	369	}
4b63960e ZW	370
46420777	371	static const struct intel_gvt_sched_policy_ops tbs_schedule_ops = {
4b63960e ZW	372	.init = tbs_sched_init,
	373	.clean = tbs_sched_clean,
	374	.init_vgpu = tbs_sched_init_vgpu,
	375	.clean_vgpu = tbs_sched_clean_vgpu,
	376	.start_schedule = tbs_sched_start_schedule,
	377	.stop_schedule = tbs_sched_stop_schedule,
	378	};
	379
	380	int intel_gvt_init_sched_policy(struct intel_gvt *gvt)
	381	{
9a512e23 CX	382	int ret;
	383
	384	mutex_lock(&gvt->sched_lock);
4b63960e	385	gvt->scheduler.sched_ops = &tbs_schedule_ops;
9a512e23 CX	386	ret = gvt->scheduler.sched_ops->init(gvt);
9a512e23 CX	387	mutex_unlock(&gvt->sched_lock);
4b63960e	388
9a512e23	389	return ret;
4b63960e ZW	390	}
	391
	392	void intel_gvt_clean_sched_policy(struct intel_gvt *gvt)
	393	{
9a512e23	394	mutex_lock(&gvt->sched_lock);
4b63960e	395	gvt->scheduler.sched_ops->clean(gvt);
9a512e23	396	mutex_unlock(&gvt->sched_lock);
4b63960e ZW	397	}
4b63960e ZW	398
9a512e23 CX	399	/* for per-vgpu scheduler policy, there are 2 per-vgpu data:
	400	* sched_data, and sched_ctl. We see these 2 data as part of
	401	* the global scheduler which are proteced by gvt->sched_lock.
	402	* Caller should make their decision if the vgpu_lock should
	403	* be hold outside.
	404	*/
	405
4b63960e ZW	406	int intel_vgpu_init_sched_policy(struct intel_vgpu *vgpu)
4b63960e ZW	407	{
9a512e23 CX	408	int ret;
	409
	410	mutex_lock(&vgpu->gvt->sched_lock);
	411	ret = vgpu->gvt->scheduler.sched_ops->init_vgpu(vgpu);
	412	mutex_unlock(&vgpu->gvt->sched_lock);
	413
	414	return ret;
4b63960e ZW	415	}
	416
	417	void intel_vgpu_clean_sched_policy(struct intel_vgpu *vgpu)
	418	{
9a512e23	419	mutex_lock(&vgpu->gvt->sched_lock);
4b63960e	420	vgpu->gvt->scheduler.sched_ops->clean_vgpu(vgpu);
9a512e23	421	mutex_unlock(&vgpu->gvt->sched_lock);
4b63960e ZW	422	}
	423
	424	void intel_vgpu_start_schedule(struct intel_vgpu *vgpu)
	425	{
9212b13f	426	struct vgpu_sched_data *vgpu_data = vgpu->sched_data;
4b63960e	427
9a512e23	428	mutex_lock(&vgpu->gvt->sched_lock);
9212b13f WL	429	if (!vgpu_data->active) {
	430	gvt_dbg_core("vgpu%d: start schedule\n", vgpu->id);
	431	vgpu->gvt->scheduler.sched_ops->start_schedule(vgpu);
	432	}
9a512e23	433	mutex_unlock(&vgpu->gvt->sched_lock);
4b63960e ZW	434	}
4b63960e ZW	435
c130456c CD	436	void intel_gvt_kick_schedule(struct intel_gvt *gvt)
c130456c CD	437	{
9a512e23	438	mutex_lock(&gvt->sched_lock);
c130456c	439	intel_gvt_request_service(gvt, INTEL_GVT_REQUEST_EVENT_SCHED);
9a512e23	440	mutex_unlock(&gvt->sched_lock);
c130456c CD	441	}
c130456c CD	442
4b63960e ZW	443	void intel_vgpu_stop_schedule(struct intel_vgpu *vgpu)
	444	{
	445	struct intel_gvt_workload_scheduler *scheduler =
	446	&vgpu->gvt->scheduler;
9212b13f	447	struct vgpu_sched_data *vgpu_data = vgpu->sched_data;
a61ac1e7	448	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
8fde4107 CW	449	struct intel_engine_cs *engine;
8fde4107 CW	450	enum intel_engine_id id;
9212b13f WL	451
	452	if (!vgpu_data->active)
	453	return;
4b63960e ZW	454
	455	gvt_dbg_core("vgpu%d: stop schedule\n", vgpu->id);
	456
9a512e23	457	mutex_lock(&vgpu->gvt->sched_lock);
4b63960e ZW	458	scheduler->sched_ops->stop_schedule(vgpu);
	459
	460	if (scheduler->next_vgpu == vgpu)
	461	scheduler->next_vgpu = NULL;
	462
	463	if (scheduler->current_vgpu == vgpu) {
	464	/* stop workload dispatching */
	465	scheduler->need_reschedule = true;
	466	scheduler->current_vgpu = NULL;
	467	}
ba3ee006	468
d858d569	469	intel_runtime_pm_get(&dev_priv->runtime_pm);
ba3ee006	470	spin_lock_bh(&scheduler->mmio_context_lock);
a61ac1e7	471	for_each_engine(engine, vgpu->gvt->gt, id) {
8fde4107 CW	472	if (scheduler->engine_owner[engine->id] == vgpu) {
	473	intel_gvt_switch_mmio(vgpu, NULL, engine);
	474	scheduler->engine_owner[engine->id] = NULL;
ba3ee006 CD	475	}
	476	}
	477	spin_unlock_bh(&scheduler->mmio_context_lock);
d858d569	478	intel_runtime_pm_put_unchecked(&dev_priv->runtime_pm);
9a512e23	479	mutex_unlock(&vgpu->gvt->sched_lock);
4b63960e	480	}