[linux-2.6-block.git] / drivers / gpu / drm / i915 / gvt / mmio.h

/*
 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 * Authors:
 *    Ke Yu
 *    Kevin Tian <kevin.tian@intel.com>
 *    Dexuan Cui
 *
 * Contributors:
 *    Tina Zhang <tina.zhang@intel.com>
 *    Min He <min.he@intel.com>
 *    Niu Bing <bing.niu@intel.com>
 *    Zhi Wang <zhi.a.wang@intel.com>
 *
 */

#ifndef _GVT_MMIO_H_
#define _GVT_MMIO_H_

struct intel_gvt;
struct intel_vgpu;

#define D_BDW   (1 << 0)
#define D_SKL	(1 << 1)
#define D_KBL	(1 << 2)

#define D_GEN9PLUS	(D_SKL | D_KBL)
#define D_GEN8PLUS	(D_BDW | D_SKL | D_KBL)

#define D_SKL_PLUS	(D_SKL | D_KBL)
#define D_BDW_PLUS	(D_BDW | D_SKL | D_KBL)

#define D_PRE_SKL	(D_BDW)
#define D_ALL		(D_BDW | D_SKL | D_KBL)

typedef int (*gvt_mmio_func)(struct intel_vgpu *, unsigned int, void *,
			     unsigned int);

struct intel_gvt_mmio_info {
	u32 offset;
	u64 ro_mask;
	u32 device;
	gvt_mmio_func read;
	gvt_mmio_func write;
	u32 addr_range;
	struct hlist_node node;
};

unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt);
bool intel_gvt_match_device(struct intel_gvt *gvt, unsigned long device);

int intel_gvt_setup_mmio_info(struct intel_gvt *gvt);
void intel_gvt_clean_mmio_info(struct intel_gvt *gvt);

#define INTEL_GVT_MMIO_OFFSET(reg) ({ \
	typeof(reg) __reg = reg; \
	u32 *offset = (u32 *)&__reg; \
	*offset; \
})

int intel_vgpu_init_mmio(struct intel_vgpu *vgpu);
void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu);
void intel_vgpu_clean_mmio(struct intel_vgpu *vgpu);

int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa);

int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa,
				void *p_data, unsigned int bytes);
int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa,
				void *p_data, unsigned int bytes);

int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
				 void *p_data, unsigned int bytes);
int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
				  void *p_data, unsigned int bytes);

bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
					  unsigned int offset);

int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset,
			   void *pdata, unsigned int bytes, bool is_read);

#endif
Commit	Line	Data
12d14cc4 ZW	1	/*
	2	* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	20	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	21	* SOFTWARE.
	22	*
	23	* Authors:
	24	* Ke Yu
	25	* Kevin Tian <kevin.tian@intel.com>
	26	* Dexuan Cui
	27	*
	28	* Contributors:
	29	* Tina Zhang <tina.zhang@intel.com>
	30	* Min He <min.he@intel.com>
	31	* Niu Bing <bing.niu@intel.com>
	32	* Zhi Wang <zhi.a.wang@intel.com>
	33	*
	34	*/
	35
	36	#ifndef _GVT_MMIO_H_
	37	#define _GVT_MMIO_H_
	38
	39	struct intel_gvt;
	40	struct intel_vgpu;
	41
a1dcba90	42	#define D_BDW (1 << 0)
	43	#define D_SKL (1 << 1)
	44	#define D_KBL (1 << 2)
12d14cc4	45
18af19db XH	46	#define D_GEN9PLUS (D_SKL \| D_KBL)
18af19db XH	47	#define D_GEN8PLUS (D_BDW \| D_SKL \| D_KBL)
12d14cc4	48
18af19db XH	49	#define D_SKL_PLUS (D_SKL \| D_KBL)
18af19db XH	50	#define D_BDW_PLUS (D_BDW \| D_SKL \| D_KBL)
12d14cc4	51
a1dcba90	52	#define D_PRE_SKL (D_BDW)
a1dcba90	53	#define D_ALL (D_BDW \| D_SKL \| D_KBL)
12d14cc4	54
65f9f6fe CD	55	typedef int (gvt_mmio_func)(struct intel_vgpu , unsigned int, void *,
	56	unsigned int);
	57
12d14cc4 ZW	58	struct intel_gvt_mmio_info {
12d14cc4 ZW	59	u32 offset;
12d14cc4 ZW	60	u64 ro_mask;
12d14cc4 ZW	61	u32 device;
65f9f6fe CD	62	gvt_mmio_func read;
65f9f6fe CD	63	gvt_mmio_func write;
12d14cc4 ZW	64	u32 addr_range;
	65	struct hlist_node node;
	66	};
	67
	68	unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt);
	69	bool intel_gvt_match_device(struct intel_gvt *gvt, unsigned long device);
	70
	71	int intel_gvt_setup_mmio_info(struct intel_gvt *gvt);
	72	void intel_gvt_clean_mmio_info(struct intel_gvt *gvt);
	73
12d14cc4 ZW	74	#define INTEL_GVT_MMIO_OFFSET(reg) ({ \
	75	typeof(reg) __reg = reg; \
	76	u32 offset = (u32 )&__reg; \
	77	*offset; \
	78	})
	79
cdcc4347	80	int intel_vgpu_init_mmio(struct intel_vgpu *vgpu);
97d58f7d	81	void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu);
cdcc4347 CD	82	void intel_vgpu_clean_mmio(struct intel_vgpu *vgpu);
cdcc4347 CD	83
e39c5add	84	int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa);
9ec1e66b JS	85
	86	int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa,
	87	void *p_data, unsigned int bytes);
	88	int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa,
	89	void *p_data, unsigned int bytes);
5c6d4c67	90
e39c5add ZW	91	int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
	92	void *p_data, unsigned int bytes);
	93	int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
	94	void *p_data, unsigned int bytes);
4938ca90 ZY	95
	96	bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
	97	unsigned int offset);
65f9f6fe CD	98
	99	int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset,
	100	void *pdata, unsigned int bytes, bool is_read);
	101
12d14cc4	102	#endif