Commit | Line | Data |
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f30437c5 JS |
1 | /* |
2 | * KVMGT - the implementation of Intel mediated pass-through framework for KVM | |
3 | * | |
cba619cb | 4 | * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. |
f30437c5 JS |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
23 | * SOFTWARE. | |
24 | * | |
25 | * Authors: | |
26 | * Kevin Tian <kevin.tian@intel.com> | |
27 | * Jike Song <jike.song@intel.com> | |
28 | * Xiaoguang Chen <xiaoguang.chen@intel.com> | |
cba619cb CH |
29 | * Eddie Dong <eddie.dong@intel.com> |
30 | * | |
31 | * Contributors: | |
32 | * Niu Bing <bing.niu@intel.com> | |
33 | * Zhi Wang <zhi.a.wang@intel.com> | |
f30437c5 JS |
34 | */ |
35 | ||
36 | #include <linux/init.h> | |
37 | #include <linux/device.h> | |
38 | #include <linux/mm.h> | |
9bf5b9eb | 39 | #include <linux/kthread.h> |
0a1b60d7 | 40 | #include <linux/sched/mm.h> |
f30437c5 JS |
41 | #include <linux/types.h> |
42 | #include <linux/list.h> | |
43 | #include <linux/rbtree.h> | |
44 | #include <linux/spinlock.h> | |
45 | #include <linux/eventfd.h> | |
46 | #include <linux/uuid.h> | |
659643f7 | 47 | #include <linux/mdev.h> |
6846dfeb | 48 | #include <linux/debugfs.h> |
f30437c5 | 49 | |
de5372da GS |
50 | #include <linux/nospec.h> |
51 | ||
a4c260de JN |
52 | #include <drm/drm_edid.h> |
53 | ||
f30437c5 | 54 | #include "i915_drv.h" |
8b750bf7 | 55 | #include "intel_gvt.h" |
f30437c5 JS |
56 | #include "gvt.h" |
57 | ||
8b750bf7 CH |
58 | MODULE_IMPORT_NS(DMA_BUF); |
59 | MODULE_IMPORT_NS(I915_GVT); | |
60 | ||
f30437c5 JS |
61 | /* helper macros copied from vfio-pci */ |
62 | #define VFIO_PCI_OFFSET_SHIFT 40 | |
63 | #define VFIO_PCI_OFFSET_TO_INDEX(off) (off >> VFIO_PCI_OFFSET_SHIFT) | |
64 | #define VFIO_PCI_INDEX_TO_OFFSET(index) ((u64)(index) << VFIO_PCI_OFFSET_SHIFT) | |
65 | #define VFIO_PCI_OFFSET_MASK (((u64)(1) << VFIO_PCI_OFFSET_SHIFT) - 1) | |
66 | ||
39c68e87 HY |
67 | #define EDID_BLOB_OFFSET (PAGE_SIZE/2) |
68 | ||
b851adea TZ |
69 | #define OPREGION_SIGNATURE "IntelGraphicsMem" |
70 | ||
71 | struct vfio_region; | |
72 | struct intel_vgpu_regops { | |
73 | size_t (*rw)(struct intel_vgpu *vgpu, char *buf, | |
74 | size_t count, loff_t *ppos, bool iswrite); | |
75 | void (*release)(struct intel_vgpu *vgpu, | |
76 | struct vfio_region *region); | |
77 | }; | |
78 | ||
f30437c5 JS |
79 | struct vfio_region { |
80 | u32 type; | |
81 | u32 subtype; | |
82 | size_t size; | |
83 | u32 flags; | |
b851adea TZ |
84 | const struct intel_vgpu_regops *ops; |
85 | void *data; | |
f30437c5 JS |
86 | }; |
87 | ||
39c68e87 HY |
88 | struct vfio_edid_region { |
89 | struct vfio_region_gfx_edid vfio_edid_regs; | |
90 | void *edid_blob; | |
91 | }; | |
92 | ||
f30437c5 JS |
93 | struct kvmgt_pgfn { |
94 | gfn_t gfn; | |
95 | struct hlist_node hnode; | |
96 | }; | |
97 | ||
f30437c5 | 98 | struct gvt_dma { |
cf4ee73f CD |
99 | struct intel_vgpu *vgpu; |
100 | struct rb_node gfn_node; | |
101 | struct rb_node dma_addr_node; | |
f30437c5 | 102 | gfn_t gfn; |
cf4ee73f | 103 | dma_addr_t dma_addr; |
79e542f5 | 104 | unsigned long size; |
cf4ee73f | 105 | struct kref ref; |
f30437c5 JS |
106 | }; |
107 | ||
978cf586 CH |
108 | #define vfio_dev_to_vgpu(vfio_dev) \ |
109 | container_of((vfio_dev), struct intel_vgpu, vfio_device) | |
110 | ||
0e09f406 CH |
111 | static void kvmgt_page_track_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
112 | const u8 *val, int len, | |
113 | struct kvm_page_track_notifier_node *node); | |
114 | static void kvmgt_page_track_flush_slot(struct kvm *kvm, | |
115 | struct kvm_memory_slot *slot, | |
116 | struct kvm_page_track_notifier_node *node); | |
117 | ||
145e06b5 ZW |
118 | static ssize_t available_instances_show(struct mdev_type *mtype, |
119 | struct mdev_type_attribute *attr, | |
120 | char *buf) | |
121 | { | |
122 | struct intel_vgpu_type *type; | |
123 | unsigned int num = 0; | |
124 | struct intel_gvt *gvt = kdev_to_i915(mtype_get_parent_dev(mtype))->gvt; | |
125 | ||
126 | type = &gvt->types[mtype_get_type_group_id(mtype)]; | |
127 | if (!type) | |
128 | num = 0; | |
129 | else | |
130 | num = type->avail_instance; | |
131 | ||
132 | return sprintf(buf, "%u\n", num); | |
133 | } | |
134 | ||
135 | static ssize_t device_api_show(struct mdev_type *mtype, | |
136 | struct mdev_type_attribute *attr, char *buf) | |
137 | { | |
138 | return sprintf(buf, "%s\n", VFIO_DEVICE_API_PCI_STRING); | |
139 | } | |
140 | ||
141 | static ssize_t description_show(struct mdev_type *mtype, | |
142 | struct mdev_type_attribute *attr, char *buf) | |
143 | { | |
144 | struct intel_vgpu_type *type; | |
145 | struct intel_gvt *gvt = kdev_to_i915(mtype_get_parent_dev(mtype))->gvt; | |
146 | ||
147 | type = &gvt->types[mtype_get_type_group_id(mtype)]; | |
148 | if (!type) | |
149 | return 0; | |
150 | ||
151 | return sprintf(buf, "low_gm_size: %dMB\nhigh_gm_size: %dMB\n" | |
152 | "fence: %d\nresolution: %s\n" | |
153 | "weight: %d\n", | |
154 | BYTES_TO_MB(type->low_gm_size), | |
155 | BYTES_TO_MB(type->high_gm_size), | |
156 | type->fence, vgpu_edid_str(type->resolution), | |
157 | type->weight); | |
158 | } | |
159 | ||
43d26c4f ZW |
160 | static ssize_t name_show(struct mdev_type *mtype, |
161 | struct mdev_type_attribute *attr, char *buf) | |
162 | { | |
163 | struct intel_vgpu_type *type; | |
164 | struct intel_gvt *gvt = kdev_to_i915(mtype_get_parent_dev(mtype))->gvt; | |
165 | ||
166 | type = &gvt->types[mtype_get_type_group_id(mtype)]; | |
167 | if (!type) | |
168 | return 0; | |
169 | ||
170 | return sprintf(buf, "%s\n", type->name); | |
171 | } | |
172 | ||
145e06b5 ZW |
173 | static MDEV_TYPE_ATTR_RO(available_instances); |
174 | static MDEV_TYPE_ATTR_RO(device_api); | |
175 | static MDEV_TYPE_ATTR_RO(description); | |
43d26c4f | 176 | static MDEV_TYPE_ATTR_RO(name); |
145e06b5 ZW |
177 | |
178 | static struct attribute *gvt_type_attrs[] = { | |
179 | &mdev_type_attr_available_instances.attr, | |
180 | &mdev_type_attr_device_api.attr, | |
181 | &mdev_type_attr_description.attr, | |
43d26c4f | 182 | &mdev_type_attr_name.attr, |
145e06b5 ZW |
183 | NULL, |
184 | }; | |
185 | ||
186 | static struct attribute_group *gvt_vgpu_type_groups[] = { | |
187 | [0 ... NR_MAX_INTEL_VGPU_TYPES - 1] = NULL, | |
188 | }; | |
189 | ||
cba619cb | 190 | static int intel_gvt_init_vgpu_type_groups(struct intel_gvt *gvt) |
145e06b5 ZW |
191 | { |
192 | int i, j; | |
193 | struct intel_vgpu_type *type; | |
194 | struct attribute_group *group; | |
195 | ||
196 | for (i = 0; i < gvt->num_types; i++) { | |
197 | type = &gvt->types[i]; | |
198 | ||
199 | group = kzalloc(sizeof(struct attribute_group), GFP_KERNEL); | |
200 | if (!group) | |
201 | goto unwind; | |
202 | ||
203 | group->name = type->name; | |
204 | group->attrs = gvt_type_attrs; | |
205 | gvt_vgpu_type_groups[i] = group; | |
206 | } | |
207 | ||
208 | return 0; | |
209 | ||
210 | unwind: | |
211 | for (j = 0; j < i; j++) { | |
212 | group = gvt_vgpu_type_groups[j]; | |
213 | kfree(group); | |
214 | } | |
215 | ||
216 | return -ENOMEM; | |
217 | } | |
218 | ||
cba619cb | 219 | static void intel_gvt_cleanup_vgpu_type_groups(struct intel_gvt *gvt) |
145e06b5 ZW |
220 | { |
221 | int i; | |
222 | struct attribute_group *group; | |
223 | ||
224 | for (i = 0; i < gvt->num_types; i++) { | |
225 | group = gvt_vgpu_type_groups[i]; | |
226 | gvt_vgpu_type_groups[i] = NULL; | |
227 | kfree(group); | |
228 | } | |
229 | } | |
230 | ||
79e542f5 CD |
231 | static void gvt_unpin_guest_page(struct intel_vgpu *vgpu, unsigned long gfn, |
232 | unsigned long size) | |
233 | { | |
44abdd16 NC |
234 | vfio_unpin_pages(&vgpu->vfio_device, gfn << PAGE_SHIFT, |
235 | DIV_ROUND_UP(size, PAGE_SIZE)); | |
79e542f5 CD |
236 | } |
237 | ||
238 | /* Pin a normal or compound guest page for dma. */ | |
239 | static int gvt_pin_guest_page(struct intel_vgpu *vgpu, unsigned long gfn, | |
240 | unsigned long size, struct page **page) | |
241 | { | |
2c9e8c01 | 242 | int total_pages = DIV_ROUND_UP(size, PAGE_SIZE); |
34a255e6 | 243 | struct page *base_page = NULL; |
79e542f5 CD |
244 | int npage; |
245 | int ret; | |
246 | ||
79e542f5 CD |
247 | /* |
248 | * We pin the pages one-by-one to avoid allocating a big arrary | |
249 | * on stack to hold pfns. | |
250 | */ | |
251 | for (npage = 0; npage < total_pages; npage++) { | |
44abdd16 | 252 | dma_addr_t cur_iova = (gfn + npage) << PAGE_SHIFT; |
34a255e6 | 253 | struct page *cur_page; |
79e542f5 | 254 | |
44abdd16 | 255 | ret = vfio_pin_pages(&vgpu->vfio_device, cur_iova, 1, |
34a255e6 | 256 | IOMMU_READ | IOMMU_WRITE, &cur_page); |
79e542f5 | 257 | if (ret != 1) { |
44abdd16 NC |
258 | gvt_vgpu_err("vfio_pin_pages failed for iova %pad, ret %d\n", |
259 | &cur_iova, ret); | |
79e542f5 CD |
260 | goto err; |
261 | } | |
262 | ||
79e542f5 | 263 | if (npage == 0) |
34a255e6 NC |
264 | base_page = cur_page; |
265 | else if (base_page + npage != cur_page) { | |
79e542f5 CD |
266 | gvt_vgpu_err("The pages are not continuous\n"); |
267 | ret = -EINVAL; | |
268 | npage++; | |
269 | goto err; | |
270 | } | |
271 | } | |
272 | ||
34a255e6 | 273 | *page = base_page; |
79e542f5 CD |
274 | return 0; |
275 | err: | |
276 | gvt_unpin_guest_page(vgpu, gfn, npage * PAGE_SIZE); | |
277 | return ret; | |
278 | } | |
279 | ||
cf4ee73f | 280 | static int gvt_dma_map_page(struct intel_vgpu *vgpu, unsigned long gfn, |
79e542f5 | 281 | dma_addr_t *dma_addr, unsigned long size) |
b86dc6ed | 282 | { |
9ff06c38 | 283 | struct device *dev = vgpu->gvt->gt->i915->drm.dev; |
79e542f5 | 284 | struct page *page = NULL; |
cf4ee73f | 285 | int ret; |
b86dc6ed | 286 | |
79e542f5 CD |
287 | ret = gvt_pin_guest_page(vgpu, gfn, size, &page); |
288 | if (ret) | |
289 | return ret; | |
b86dc6ed | 290 | |
cf4ee73f | 291 | /* Setup DMA mapping. */ |
c4f61203 | 292 | *dma_addr = dma_map_page(dev, page, 0, size, DMA_BIDIRECTIONAL); |
13bdff33 | 293 | if (dma_mapping_error(dev, *dma_addr)) { |
79e542f5 CD |
294 | gvt_vgpu_err("DMA mapping failed for pfn 0x%lx, ret %d\n", |
295 | page_to_pfn(page), ret); | |
296 | gvt_unpin_guest_page(vgpu, gfn, size); | |
13bdff33 | 297 | return -ENOMEM; |
cf4ee73f | 298 | } |
b86dc6ed | 299 | |
13bdff33 | 300 | return 0; |
b86dc6ed CD |
301 | } |
302 | ||
cf4ee73f | 303 | static void gvt_dma_unmap_page(struct intel_vgpu *vgpu, unsigned long gfn, |
79e542f5 | 304 | dma_addr_t dma_addr, unsigned long size) |
b86dc6ed | 305 | { |
9ff06c38 | 306 | struct device *dev = vgpu->gvt->gt->i915->drm.dev; |
b86dc6ed | 307 | |
c4f61203 | 308 | dma_unmap_page(dev, dma_addr, size, DMA_BIDIRECTIONAL); |
79e542f5 | 309 | gvt_unpin_guest_page(vgpu, gfn, size); |
b86dc6ed CD |
310 | } |
311 | ||
cf4ee73f CD |
312 | static struct gvt_dma *__gvt_cache_find_dma_addr(struct intel_vgpu *vgpu, |
313 | dma_addr_t dma_addr) | |
f30437c5 | 314 | { |
62980cac | 315 | struct rb_node *node = vgpu->dma_addr_cache.rb_node; |
cf4ee73f | 316 | struct gvt_dma *itr; |
f30437c5 JS |
317 | |
318 | while (node) { | |
cf4ee73f | 319 | itr = rb_entry(node, struct gvt_dma, dma_addr_node); |
f30437c5 | 320 | |
cf4ee73f | 321 | if (dma_addr < itr->dma_addr) |
f30437c5 | 322 | node = node->rb_left; |
cf4ee73f | 323 | else if (dma_addr > itr->dma_addr) |
f30437c5 | 324 | node = node->rb_right; |
cf4ee73f CD |
325 | else |
326 | return itr; | |
f30437c5 | 327 | } |
cf4ee73f | 328 | return NULL; |
f30437c5 JS |
329 | } |
330 | ||
cf4ee73f | 331 | static struct gvt_dma *__gvt_cache_find_gfn(struct intel_vgpu *vgpu, gfn_t gfn) |
f30437c5 | 332 | { |
62980cac | 333 | struct rb_node *node = vgpu->gfn_cache.rb_node; |
cf4ee73f | 334 | struct gvt_dma *itr; |
f30437c5 | 335 | |
cf4ee73f CD |
336 | while (node) { |
337 | itr = rb_entry(node, struct gvt_dma, gfn_node); | |
f30437c5 | 338 | |
cf4ee73f CD |
339 | if (gfn < itr->gfn) |
340 | node = node->rb_left; | |
341 | else if (gfn > itr->gfn) | |
342 | node = node->rb_right; | |
343 | else | |
344 | return itr; | |
345 | } | |
346 | return NULL; | |
f30437c5 JS |
347 | } |
348 | ||
5cd4223e | 349 | static int __gvt_cache_add(struct intel_vgpu *vgpu, gfn_t gfn, |
79e542f5 | 350 | dma_addr_t dma_addr, unsigned long size) |
f30437c5 JS |
351 | { |
352 | struct gvt_dma *new, *itr; | |
cf4ee73f | 353 | struct rb_node **link, *parent = NULL; |
f30437c5 JS |
354 | |
355 | new = kzalloc(sizeof(struct gvt_dma), GFP_KERNEL); | |
356 | if (!new) | |
5cd4223e | 357 | return -ENOMEM; |
f30437c5 | 358 | |
cf4ee73f | 359 | new->vgpu = vgpu; |
f30437c5 | 360 | new->gfn = gfn; |
cf4ee73f | 361 | new->dma_addr = dma_addr; |
79e542f5 | 362 | new->size = size; |
cf4ee73f | 363 | kref_init(&new->ref); |
f30437c5 | 364 | |
cf4ee73f | 365 | /* gfn_cache maps gfn to struct gvt_dma. */ |
62980cac | 366 | link = &vgpu->gfn_cache.rb_node; |
f30437c5 JS |
367 | while (*link) { |
368 | parent = *link; | |
cf4ee73f | 369 | itr = rb_entry(parent, struct gvt_dma, gfn_node); |
f30437c5 | 370 | |
cf4ee73f | 371 | if (gfn < itr->gfn) |
f30437c5 JS |
372 | link = &parent->rb_left; |
373 | else | |
374 | link = &parent->rb_right; | |
375 | } | |
cf4ee73f | 376 | rb_link_node(&new->gfn_node, parent, link); |
62980cac | 377 | rb_insert_color(&new->gfn_node, &vgpu->gfn_cache); |
f30437c5 | 378 | |
cf4ee73f CD |
379 | /* dma_addr_cache maps dma addr to struct gvt_dma. */ |
380 | parent = NULL; | |
62980cac | 381 | link = &vgpu->dma_addr_cache.rb_node; |
cf4ee73f CD |
382 | while (*link) { |
383 | parent = *link; | |
384 | itr = rb_entry(parent, struct gvt_dma, dma_addr_node); | |
f30437c5 | 385 | |
cf4ee73f CD |
386 | if (dma_addr < itr->dma_addr) |
387 | link = &parent->rb_left; | |
388 | else | |
389 | link = &parent->rb_right; | |
390 | } | |
391 | rb_link_node(&new->dma_addr_node, parent, link); | |
62980cac | 392 | rb_insert_color(&new->dma_addr_node, &vgpu->dma_addr_cache); |
6846dfeb | 393 | |
62980cac | 394 | vgpu->nr_cache_entries++; |
5cd4223e | 395 | return 0; |
f30437c5 JS |
396 | } |
397 | ||
398 | static void __gvt_cache_remove_entry(struct intel_vgpu *vgpu, | |
399 | struct gvt_dma *entry) | |
400 | { | |
62980cac CH |
401 | rb_erase(&entry->gfn_node, &vgpu->gfn_cache); |
402 | rb_erase(&entry->dma_addr_node, &vgpu->dma_addr_cache); | |
f30437c5 | 403 | kfree(entry); |
62980cac | 404 | vgpu->nr_cache_entries--; |
f30437c5 JS |
405 | } |
406 | ||
f30437c5 JS |
407 | static void gvt_cache_destroy(struct intel_vgpu *vgpu) |
408 | { | |
409 | struct gvt_dma *dma; | |
410 | struct rb_node *node = NULL; | |
f30437c5 | 411 | |
f16bd3dd | 412 | for (;;) { |
62980cac CH |
413 | mutex_lock(&vgpu->cache_lock); |
414 | node = rb_first(&vgpu->gfn_cache); | |
f16bd3dd | 415 | if (!node) { |
62980cac | 416 | mutex_unlock(&vgpu->cache_lock); |
f16bd3dd CD |
417 | break; |
418 | } | |
cf4ee73f | 419 | dma = rb_entry(node, struct gvt_dma, gfn_node); |
79e542f5 | 420 | gvt_dma_unmap_page(vgpu, dma->gfn, dma->dma_addr, dma->size); |
f30437c5 | 421 | __gvt_cache_remove_entry(vgpu, dma); |
62980cac | 422 | mutex_unlock(&vgpu->cache_lock); |
f30437c5 | 423 | } |
f30437c5 JS |
424 | } |
425 | ||
cf4ee73f CD |
426 | static void gvt_cache_init(struct intel_vgpu *vgpu) |
427 | { | |
62980cac CH |
428 | vgpu->gfn_cache = RB_ROOT; |
429 | vgpu->dma_addr_cache = RB_ROOT; | |
430 | vgpu->nr_cache_entries = 0; | |
431 | mutex_init(&vgpu->cache_lock); | |
cf4ee73f CD |
432 | } |
433 | ||
10ddb962 | 434 | static void kvmgt_protect_table_init(struct intel_vgpu *info) |
f30437c5 JS |
435 | { |
436 | hash_init(info->ptable); | |
437 | } | |
438 | ||
10ddb962 | 439 | static void kvmgt_protect_table_destroy(struct intel_vgpu *info) |
f30437c5 JS |
440 | { |
441 | struct kvmgt_pgfn *p; | |
442 | struct hlist_node *tmp; | |
443 | int i; | |
444 | ||
445 | hash_for_each_safe(info->ptable, i, tmp, p, hnode) { | |
446 | hash_del(&p->hnode); | |
447 | kfree(p); | |
448 | } | |
449 | } | |
450 | ||
451 | static struct kvmgt_pgfn * | |
10ddb962 | 452 | __kvmgt_protect_table_find(struct intel_vgpu *info, gfn_t gfn) |
f30437c5 JS |
453 | { |
454 | struct kvmgt_pgfn *p, *res = NULL; | |
455 | ||
456 | hash_for_each_possible(info->ptable, p, hnode, gfn) { | |
457 | if (gfn == p->gfn) { | |
458 | res = p; | |
459 | break; | |
460 | } | |
461 | } | |
462 | ||
463 | return res; | |
464 | } | |
465 | ||
10ddb962 | 466 | static bool kvmgt_gfn_is_write_protected(struct intel_vgpu *info, gfn_t gfn) |
f30437c5 JS |
467 | { |
468 | struct kvmgt_pgfn *p; | |
469 | ||
470 | p = __kvmgt_protect_table_find(info, gfn); | |
471 | return !!p; | |
472 | } | |
473 | ||
10ddb962 | 474 | static void kvmgt_protect_table_add(struct intel_vgpu *info, gfn_t gfn) |
f30437c5 JS |
475 | { |
476 | struct kvmgt_pgfn *p; | |
477 | ||
478 | if (kvmgt_gfn_is_write_protected(info, gfn)) | |
479 | return; | |
480 | ||
c55b1de0 | 481 | p = kzalloc(sizeof(struct kvmgt_pgfn), GFP_ATOMIC); |
f30437c5 JS |
482 | if (WARN(!p, "gfn: 0x%llx\n", gfn)) |
483 | return; | |
484 | ||
485 | p->gfn = gfn; | |
486 | hash_add(info->ptable, &p->hnode, gfn); | |
487 | } | |
488 | ||
10ddb962 | 489 | static void kvmgt_protect_table_del(struct intel_vgpu *info, gfn_t gfn) |
f30437c5 JS |
490 | { |
491 | struct kvmgt_pgfn *p; | |
492 | ||
493 | p = __kvmgt_protect_table_find(info, gfn); | |
494 | if (p) { | |
495 | hash_del(&p->hnode); | |
496 | kfree(p); | |
497 | } | |
498 | } | |
499 | ||
b851adea TZ |
500 | static size_t intel_vgpu_reg_rw_opregion(struct intel_vgpu *vgpu, char *buf, |
501 | size_t count, loff_t *ppos, bool iswrite) | |
502 | { | |
503 | unsigned int i = VFIO_PCI_OFFSET_TO_INDEX(*ppos) - | |
504 | VFIO_PCI_NUM_REGIONS; | |
62980cac | 505 | void *base = vgpu->region[i].data; |
b851adea TZ |
506 | loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK; |
507 | ||
06d63c48 | 508 | |
62980cac | 509 | if (pos >= vgpu->region[i].size || iswrite) { |
b851adea TZ |
510 | gvt_vgpu_err("invalid op or offset for Intel vgpu OpRegion\n"); |
511 | return -EINVAL; | |
512 | } | |
62980cac | 513 | count = min(count, (size_t)(vgpu->region[i].size - pos)); |
b851adea TZ |
514 | memcpy(buf, base + pos, count); |
515 | ||
516 | return count; | |
517 | } | |
518 | ||
519 | static void intel_vgpu_reg_release_opregion(struct intel_vgpu *vgpu, | |
520 | struct vfio_region *region) | |
521 | { | |
522 | } | |
523 | ||
524 | static const struct intel_vgpu_regops intel_vgpu_regops_opregion = { | |
525 | .rw = intel_vgpu_reg_rw_opregion, | |
526 | .release = intel_vgpu_reg_release_opregion, | |
527 | }; | |
528 | ||
39c68e87 HY |
529 | static int handle_edid_regs(struct intel_vgpu *vgpu, |
530 | struct vfio_edid_region *region, char *buf, | |
531 | size_t count, u16 offset, bool is_write) | |
532 | { | |
533 | struct vfio_region_gfx_edid *regs = ®ion->vfio_edid_regs; | |
534 | unsigned int data; | |
535 | ||
536 | if (offset + count > sizeof(*regs)) | |
537 | return -EINVAL; | |
538 | ||
539 | if (count != 4) | |
540 | return -EINVAL; | |
541 | ||
542 | if (is_write) { | |
543 | data = *((unsigned int *)buf); | |
544 | switch (offset) { | |
545 | case offsetof(struct vfio_region_gfx_edid, link_state): | |
546 | if (data == VFIO_DEVICE_GFX_LINK_STATE_UP) { | |
547 | if (!drm_edid_block_valid( | |
548 | (u8 *)region->edid_blob, | |
549 | 0, | |
550 | true, | |
551 | NULL)) { | |
552 | gvt_vgpu_err("invalid EDID blob\n"); | |
553 | return -EINVAL; | |
554 | } | |
675e5c4a | 555 | intel_vgpu_emulate_hotplug(vgpu, true); |
39c68e87 | 556 | } else if (data == VFIO_DEVICE_GFX_LINK_STATE_DOWN) |
675e5c4a | 557 | intel_vgpu_emulate_hotplug(vgpu, false); |
39c68e87 HY |
558 | else { |
559 | gvt_vgpu_err("invalid EDID link state %d\n", | |
560 | regs->link_state); | |
561 | return -EINVAL; | |
562 | } | |
563 | regs->link_state = data; | |
564 | break; | |
565 | case offsetof(struct vfio_region_gfx_edid, edid_size): | |
566 | if (data > regs->edid_max_size) { | |
567 | gvt_vgpu_err("EDID size is bigger than %d!\n", | |
568 | regs->edid_max_size); | |
569 | return -EINVAL; | |
570 | } | |
571 | regs->edid_size = data; | |
572 | break; | |
573 | default: | |
574 | /* read-only regs */ | |
575 | gvt_vgpu_err("write read-only EDID region at offset %d\n", | |
576 | offset); | |
577 | return -EPERM; | |
578 | } | |
579 | } else { | |
580 | memcpy(buf, (char *)regs + offset, count); | |
581 | } | |
582 | ||
583 | return count; | |
584 | } | |
585 | ||
586 | static int handle_edid_blob(struct vfio_edid_region *region, char *buf, | |
587 | size_t count, u16 offset, bool is_write) | |
588 | { | |
589 | if (offset + count > region->vfio_edid_regs.edid_size) | |
590 | return -EINVAL; | |
591 | ||
592 | if (is_write) | |
593 | memcpy(region->edid_blob + offset, buf, count); | |
594 | else | |
595 | memcpy(buf, region->edid_blob + offset, count); | |
596 | ||
597 | return count; | |
598 | } | |
599 | ||
600 | static size_t intel_vgpu_reg_rw_edid(struct intel_vgpu *vgpu, char *buf, | |
601 | size_t count, loff_t *ppos, bool iswrite) | |
602 | { | |
603 | int ret; | |
604 | unsigned int i = VFIO_PCI_OFFSET_TO_INDEX(*ppos) - | |
605 | VFIO_PCI_NUM_REGIONS; | |
62980cac | 606 | struct vfio_edid_region *region = vgpu->region[i].data; |
39c68e87 HY |
607 | loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK; |
608 | ||
609 | if (pos < region->vfio_edid_regs.edid_offset) { | |
610 | ret = handle_edid_regs(vgpu, region, buf, count, pos, iswrite); | |
611 | } else { | |
612 | pos -= EDID_BLOB_OFFSET; | |
613 | ret = handle_edid_blob(region, buf, count, pos, iswrite); | |
614 | } | |
615 | ||
616 | if (ret < 0) | |
617 | gvt_vgpu_err("failed to access EDID region\n"); | |
618 | ||
619 | return ret; | |
620 | } | |
621 | ||
622 | static void intel_vgpu_reg_release_edid(struct intel_vgpu *vgpu, | |
623 | struct vfio_region *region) | |
624 | { | |
625 | kfree(region->data); | |
626 | } | |
627 | ||
628 | static const struct intel_vgpu_regops intel_vgpu_regops_edid = { | |
629 | .rw = intel_vgpu_reg_rw_edid, | |
630 | .release = intel_vgpu_reg_release_edid, | |
631 | }; | |
632 | ||
b851adea TZ |
633 | static int intel_vgpu_register_reg(struct intel_vgpu *vgpu, |
634 | unsigned int type, unsigned int subtype, | |
635 | const struct intel_vgpu_regops *ops, | |
636 | size_t size, u32 flags, void *data) | |
637 | { | |
638 | struct vfio_region *region; | |
639 | ||
62980cac CH |
640 | region = krealloc(vgpu->region, |
641 | (vgpu->num_regions + 1) * sizeof(*region), | |
b851adea TZ |
642 | GFP_KERNEL); |
643 | if (!region) | |
644 | return -ENOMEM; | |
645 | ||
62980cac CH |
646 | vgpu->region = region; |
647 | vgpu->region[vgpu->num_regions].type = type; | |
648 | vgpu->region[vgpu->num_regions].subtype = subtype; | |
649 | vgpu->region[vgpu->num_regions].ops = ops; | |
650 | vgpu->region[vgpu->num_regions].size = size; | |
651 | vgpu->region[vgpu->num_regions].flags = flags; | |
652 | vgpu->region[vgpu->num_regions].data = data; | |
653 | vgpu->num_regions++; | |
e546e281 TZ |
654 | return 0; |
655 | } | |
656 | ||
f9399b0e | 657 | int intel_gvt_set_opregion(struct intel_vgpu *vgpu) |
b851adea | 658 | { |
b851adea TZ |
659 | void *base; |
660 | int ret; | |
661 | ||
662 | /* Each vgpu has its own opregion, although VFIO would create another | |
663 | * one later. This one is used to expose opregion to VFIO. And the | |
664 | * other one created by VFIO later, is used by guest actually. | |
665 | */ | |
666 | base = vgpu_opregion(vgpu)->va; | |
667 | if (!base) | |
668 | return -ENOMEM; | |
669 | ||
670 | if (memcmp(base, OPREGION_SIGNATURE, 16)) { | |
671 | memunmap(base); | |
672 | return -EINVAL; | |
673 | } | |
674 | ||
675 | ret = intel_vgpu_register_reg(vgpu, | |
676 | PCI_VENDOR_ID_INTEL | VFIO_REGION_TYPE_PCI_VENDOR_TYPE, | |
677 | VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION, | |
678 | &intel_vgpu_regops_opregion, OPREGION_SIZE, | |
679 | VFIO_REGION_INFO_FLAG_READ, base); | |
680 | ||
681 | return ret; | |
682 | } | |
683 | ||
f9399b0e | 684 | int intel_gvt_set_edid(struct intel_vgpu *vgpu, int port_num) |
39c68e87 | 685 | { |
39c68e87 HY |
686 | struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); |
687 | struct vfio_edid_region *base; | |
688 | int ret; | |
689 | ||
690 | base = kzalloc(sizeof(*base), GFP_KERNEL); | |
691 | if (!base) | |
692 | return -ENOMEM; | |
693 | ||
694 | /* TODO: Add multi-port and EDID extension block support */ | |
695 | base->vfio_edid_regs.edid_offset = EDID_BLOB_OFFSET; | |
696 | base->vfio_edid_regs.edid_max_size = EDID_SIZE; | |
697 | base->vfio_edid_regs.edid_size = EDID_SIZE; | |
698 | base->vfio_edid_regs.max_xres = vgpu_edid_xres(port->id); | |
699 | base->vfio_edid_regs.max_yres = vgpu_edid_yres(port->id); | |
700 | base->edid_blob = port->edid->edid_block; | |
701 | ||
702 | ret = intel_vgpu_register_reg(vgpu, | |
703 | VFIO_REGION_TYPE_GFX, | |
704 | VFIO_REGION_SUBTYPE_GFX_EDID, | |
705 | &intel_vgpu_regops_edid, EDID_SIZE, | |
706 | VFIO_REGION_INFO_FLAG_READ | | |
707 | VFIO_REGION_INFO_FLAG_WRITE | | |
708 | VFIO_REGION_INFO_FLAG_CAPS, base); | |
709 | ||
710 | return ret; | |
711 | } | |
712 | ||
ce4b4657 JG |
713 | static void intel_vgpu_dma_unmap(struct vfio_device *vfio_dev, u64 iova, |
714 | u64 length) | |
659643f7 | 715 | { |
ce4b4657 JG |
716 | struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); |
717 | struct gvt_dma *entry; | |
718 | u64 iov_pfn = iova >> PAGE_SHIFT; | |
719 | u64 end_iov_pfn = iov_pfn + length / PAGE_SIZE; | |
720 | ||
721 | mutex_lock(&vgpu->cache_lock); | |
722 | for (; iov_pfn < end_iov_pfn; iov_pfn++) { | |
723 | entry = __gvt_cache_find_gfn(vgpu, iov_pfn); | |
724 | if (!entry) | |
725 | continue; | |
659643f7 | 726 | |
ce4b4657 JG |
727 | gvt_dma_unmap_page(vgpu, entry->gfn, entry->dma_addr, |
728 | entry->size); | |
729 | __gvt_cache_remove_entry(vgpu, entry); | |
659643f7 | 730 | } |
ce4b4657 | 731 | mutex_unlock(&vgpu->cache_lock); |
659643f7 JS |
732 | } |
733 | ||
0e09f406 CH |
734 | static bool __kvmgt_vgpu_exist(struct intel_vgpu *vgpu) |
735 | { | |
736 | struct intel_vgpu *itr; | |
737 | int id; | |
738 | bool ret = false; | |
739 | ||
740 | mutex_lock(&vgpu->gvt->lock); | |
741 | for_each_active_vgpu(vgpu->gvt, itr, id) { | |
742 | if (!itr->attached) | |
743 | continue; | |
744 | ||
421cfe65 | 745 | if (vgpu->vfio_device.kvm == itr->vfio_device.kvm) { |
0e09f406 CH |
746 | ret = true; |
747 | goto out; | |
748 | } | |
749 | } | |
750 | out: | |
751 | mutex_unlock(&vgpu->gvt->lock); | |
752 | return ret; | |
753 | } | |
754 | ||
978cf586 | 755 | static int intel_vgpu_open_device(struct vfio_device *vfio_dev) |
659643f7 | 756 | { |
978cf586 | 757 | struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); |
659643f7 | 758 | |
0e09f406 | 759 | if (vgpu->attached) |
ce4b4657 | 760 | return -EEXIST; |
0e09f406 | 761 | |
421cfe65 MR |
762 | if (!vgpu->vfio_device.kvm || |
763 | vgpu->vfio_device.kvm->mm != current->mm) { | |
0e09f406 | 764 | gvt_vgpu_err("KVM is required to use Intel vGPU\n"); |
ce4b4657 | 765 | return -ESRCH; |
0e09f406 CH |
766 | } |
767 | ||
421cfe65 MR |
768 | kvm_get_kvm(vgpu->vfio_device.kvm); |
769 | ||
0e09f406 | 770 | if (__kvmgt_vgpu_exist(vgpu)) |
ce4b4657 | 771 | return -EEXIST; |
364fb6b7 | 772 | |
0e09f406 | 773 | vgpu->attached = true; |
0e09f406 CH |
774 | |
775 | kvmgt_protect_table_init(vgpu); | |
776 | gvt_cache_init(vgpu); | |
777 | ||
778 | vgpu->track_node.track_write = kvmgt_page_track_write; | |
779 | vgpu->track_node.track_flush_slot = kvmgt_page_track_flush_slot; | |
421cfe65 MR |
780 | kvm_page_track_register_notifier(vgpu->vfio_device.kvm, |
781 | &vgpu->track_node); | |
0e09f406 CH |
782 | |
783 | debugfs_create_ulong(KVMGT_DEBUGFS_FILENAME, 0444, vgpu->debugfs, | |
784 | &vgpu->nr_cache_entries); | |
785 | ||
675e5c4a | 786 | intel_gvt_activate_vgpu(vgpu); |
b79c52ae | 787 | |
62980cac | 788 | atomic_set(&vgpu->released, 0); |
0e09f406 | 789 | return 0; |
659643f7 JS |
790 | } |
791 | ||
d54e7934 XZ |
792 | static void intel_vgpu_release_msi_eventfd_ctx(struct intel_vgpu *vgpu) |
793 | { | |
794 | struct eventfd_ctx *trigger; | |
795 | ||
62980cac | 796 | trigger = vgpu->msi_trigger; |
d54e7934 XZ |
797 | if (trigger) { |
798 | eventfd_ctx_put(trigger); | |
62980cac | 799 | vgpu->msi_trigger = NULL; |
d54e7934 XZ |
800 | } |
801 | } | |
802 | ||
421cfe65 | 803 | static void intel_vgpu_close_device(struct vfio_device *vfio_dev) |
659643f7 | 804 | { |
421cfe65 | 805 | struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); |
659643f7 | 806 | |
3c340d05 | 807 | if (!vgpu->attached) |
659643f7 JS |
808 | return; |
809 | ||
62980cac | 810 | if (atomic_cmpxchg(&vgpu->released, 0, 1)) |
364fb6b7 JS |
811 | return; |
812 | ||
675e5c4a | 813 | intel_gvt_release_vgpu(vgpu); |
b79c52ae | 814 | |
0e09f406 CH |
815 | debugfs_remove(debugfs_lookup(KVMGT_DEBUGFS_FILENAME, vgpu->debugfs)); |
816 | ||
421cfe65 MR |
817 | kvm_page_track_unregister_notifier(vgpu->vfio_device.kvm, |
818 | &vgpu->track_node); | |
0e09f406 CH |
819 | kvmgt_protect_table_destroy(vgpu); |
820 | gvt_cache_destroy(vgpu); | |
364fb6b7 | 821 | |
d54e7934 XZ |
822 | intel_vgpu_release_msi_eventfd_ctx(vgpu); |
823 | ||
3c340d05 | 824 | vgpu->attached = false; |
8ff842fd | 825 | |
421cfe65 MR |
826 | if (vgpu->vfio_device.kvm) |
827 | kvm_put_kvm(vgpu->vfio_device.kvm); | |
659643f7 JS |
828 | } |
829 | ||
2e679d48 | 830 | static u64 intel_vgpu_get_bar_addr(struct intel_vgpu *vgpu, int bar) |
659643f7 JS |
831 | { |
832 | u32 start_lo, start_hi; | |
833 | u32 mem_type; | |
659643f7 | 834 | |
f090a00d | 835 | start_lo = (*(u32 *)(vgpu->cfg_space.virtual_cfg_space + bar)) & |
659643f7 | 836 | PCI_BASE_ADDRESS_MEM_MASK; |
f090a00d | 837 | mem_type = (*(u32 *)(vgpu->cfg_space.virtual_cfg_space + bar)) & |
659643f7 JS |
838 | PCI_BASE_ADDRESS_MEM_TYPE_MASK; |
839 | ||
840 | switch (mem_type) { | |
841 | case PCI_BASE_ADDRESS_MEM_TYPE_64: | |
842 | start_hi = (*(u32 *)(vgpu->cfg_space.virtual_cfg_space | |
f090a00d | 843 | + bar + 4)); |
659643f7 JS |
844 | break; |
845 | case PCI_BASE_ADDRESS_MEM_TYPE_32: | |
846 | case PCI_BASE_ADDRESS_MEM_TYPE_1M: | |
847 | /* 1M mem BAR treated as 32-bit BAR */ | |
848 | default: | |
849 | /* mem unknown type treated as 32-bit BAR */ | |
850 | start_hi = 0; | |
851 | break; | |
852 | } | |
853 | ||
854 | return ((u64)start_hi << 32) | start_lo; | |
855 | } | |
856 | ||
2e679d48 | 857 | static int intel_vgpu_bar_rw(struct intel_vgpu *vgpu, int bar, u64 off, |
f090a00d CD |
858 | void *buf, unsigned int count, bool is_write) |
859 | { | |
2e679d48 | 860 | u64 bar_start = intel_vgpu_get_bar_addr(vgpu, bar); |
f090a00d CD |
861 | int ret; |
862 | ||
863 | if (is_write) | |
675e5c4a | 864 | ret = intel_vgpu_emulate_mmio_write(vgpu, |
f090a00d CD |
865 | bar_start + off, buf, count); |
866 | else | |
675e5c4a | 867 | ret = intel_vgpu_emulate_mmio_read(vgpu, |
f090a00d CD |
868 | bar_start + off, buf, count); |
869 | return ret; | |
870 | } | |
871 | ||
2e679d48 | 872 | static inline bool intel_vgpu_in_aperture(struct intel_vgpu *vgpu, u64 off) |
d480b28a CD |
873 | { |
874 | return off >= vgpu_aperture_offset(vgpu) && | |
875 | off < vgpu_aperture_offset(vgpu) + vgpu_aperture_sz(vgpu); | |
876 | } | |
877 | ||
2e679d48 | 878 | static int intel_vgpu_aperture_rw(struct intel_vgpu *vgpu, u64 off, |
d480b28a CD |
879 | void *buf, unsigned long count, bool is_write) |
880 | { | |
196a6627 | 881 | void __iomem *aperture_va; |
d480b28a CD |
882 | |
883 | if (!intel_vgpu_in_aperture(vgpu, off) || | |
884 | !intel_vgpu_in_aperture(vgpu, off + count)) { | |
885 | gvt_vgpu_err("Invalid aperture offset %llu\n", off); | |
886 | return -EINVAL; | |
887 | } | |
888 | ||
a61ac1e7 | 889 | aperture_va = io_mapping_map_wc(&vgpu->gvt->gt->ggtt->iomap, |
d480b28a CD |
890 | ALIGN_DOWN(off, PAGE_SIZE), |
891 | count + offset_in_page(off)); | |
892 | if (!aperture_va) | |
893 | return -EIO; | |
894 | ||
895 | if (is_write) | |
196a6627 | 896 | memcpy_toio(aperture_va + offset_in_page(off), buf, count); |
d480b28a | 897 | else |
196a6627 | 898 | memcpy_fromio(buf, aperture_va + offset_in_page(off), count); |
d480b28a CD |
899 | |
900 | io_mapping_unmap(aperture_va); | |
901 | ||
902 | return 0; | |
903 | } | |
904 | ||
7f11e689 | 905 | static ssize_t intel_vgpu_rw(struct intel_vgpu *vgpu, char *buf, |
659643f7 JS |
906 | size_t count, loff_t *ppos, bool is_write) |
907 | { | |
659643f7 | 908 | unsigned int index = VFIO_PCI_OFFSET_TO_INDEX(*ppos); |
2e679d48 | 909 | u64 pos = *ppos & VFIO_PCI_OFFSET_MASK; |
659643f7 JS |
910 | int ret = -EINVAL; |
911 | ||
912 | ||
62980cac | 913 | if (index >= VFIO_PCI_NUM_REGIONS + vgpu->num_regions) { |
695fbc08 | 914 | gvt_vgpu_err("invalid index: %u\n", index); |
659643f7 JS |
915 | return -EINVAL; |
916 | } | |
917 | ||
918 | switch (index) { | |
919 | case VFIO_PCI_CONFIG_REGION_INDEX: | |
920 | if (is_write) | |
675e5c4a | 921 | ret = intel_vgpu_emulate_cfg_write(vgpu, pos, |
659643f7 JS |
922 | buf, count); |
923 | else | |
675e5c4a | 924 | ret = intel_vgpu_emulate_cfg_read(vgpu, pos, |
659643f7 JS |
925 | buf, count); |
926 | break; | |
927 | case VFIO_PCI_BAR0_REGION_INDEX: | |
f090a00d CD |
928 | ret = intel_vgpu_bar_rw(vgpu, PCI_BASE_ADDRESS_0, pos, |
929 | buf, count, is_write); | |
659643f7 JS |
930 | break; |
931 | case VFIO_PCI_BAR2_REGION_INDEX: | |
d480b28a | 932 | ret = intel_vgpu_aperture_rw(vgpu, pos, buf, count, is_write); |
f090a00d CD |
933 | break; |
934 | case VFIO_PCI_BAR1_REGION_INDEX: | |
659643f7 JS |
935 | case VFIO_PCI_BAR3_REGION_INDEX: |
936 | case VFIO_PCI_BAR4_REGION_INDEX: | |
937 | case VFIO_PCI_BAR5_REGION_INDEX: | |
938 | case VFIO_PCI_VGA_REGION_INDEX: | |
939 | case VFIO_PCI_ROM_REGION_INDEX: | |
b851adea | 940 | break; |
659643f7 | 941 | default: |
62980cac | 942 | if (index >= VFIO_PCI_NUM_REGIONS + vgpu->num_regions) |
b851adea TZ |
943 | return -EINVAL; |
944 | ||
945 | index -= VFIO_PCI_NUM_REGIONS; | |
62980cac | 946 | return vgpu->region[index].ops->rw(vgpu, buf, count, |
b851adea | 947 | ppos, is_write); |
659643f7 JS |
948 | } |
949 | ||
950 | return ret == 0 ? count : ret; | |
951 | } | |
952 | ||
7f11e689 | 953 | static bool gtt_entry(struct intel_vgpu *vgpu, loff_t *ppos) |
a26ca6ad | 954 | { |
a26ca6ad TZ |
955 | unsigned int index = VFIO_PCI_OFFSET_TO_INDEX(*ppos); |
956 | struct intel_gvt *gvt = vgpu->gvt; | |
957 | int offset; | |
958 | ||
959 | /* Only allow MMIO GGTT entry access */ | |
960 | if (index != PCI_BASE_ADDRESS_0) | |
961 | return false; | |
962 | ||
963 | offset = (u64)(*ppos & VFIO_PCI_OFFSET_MASK) - | |
964 | intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_0); | |
965 | ||
966 | return (offset >= gvt->device_info.gtt_start_offset && | |
967 | offset < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt)) ? | |
968 | true : false; | |
969 | } | |
970 | ||
978cf586 | 971 | static ssize_t intel_vgpu_read(struct vfio_device *vfio_dev, char __user *buf, |
659643f7 JS |
972 | size_t count, loff_t *ppos) |
973 | { | |
978cf586 | 974 | struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); |
659643f7 JS |
975 | unsigned int done = 0; |
976 | int ret; | |
977 | ||
978 | while (count) { | |
979 | size_t filled; | |
980 | ||
a26ca6ad TZ |
981 | /* Only support GGTT entry 8 bytes read */ |
982 | if (count >= 8 && !(*ppos % 8) && | |
7f11e689 | 983 | gtt_entry(vgpu, ppos)) { |
a26ca6ad TZ |
984 | u64 val; |
985 | ||
7f11e689 | 986 | ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val), |
a26ca6ad TZ |
987 | ppos, false); |
988 | if (ret <= 0) | |
989 | goto read_err; | |
990 | ||
991 | if (copy_to_user(buf, &val, sizeof(val))) | |
992 | goto read_err; | |
993 | ||
994 | filled = 8; | |
995 | } else if (count >= 4 && !(*ppos % 4)) { | |
659643f7 JS |
996 | u32 val; |
997 | ||
7f11e689 | 998 | ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val), |
659643f7 JS |
999 | ppos, false); |
1000 | if (ret <= 0) | |
1001 | goto read_err; | |
1002 | ||
1003 | if (copy_to_user(buf, &val, sizeof(val))) | |
1004 | goto read_err; | |
1005 | ||
1006 | filled = 4; | |
1007 | } else if (count >= 2 && !(*ppos % 2)) { | |
1008 | u16 val; | |
1009 | ||
7f11e689 | 1010 | ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val), |
659643f7 JS |
1011 | ppos, false); |
1012 | if (ret <= 0) | |
1013 | goto read_err; | |
1014 | ||
1015 | if (copy_to_user(buf, &val, sizeof(val))) | |
1016 | goto read_err; | |
1017 | ||
1018 | filled = 2; | |
1019 | } else { | |
1020 | u8 val; | |
1021 | ||
7f11e689 | 1022 | ret = intel_vgpu_rw(vgpu, &val, sizeof(val), ppos, |
659643f7 JS |
1023 | false); |
1024 | if (ret <= 0) | |
1025 | goto read_err; | |
1026 | ||
1027 | if (copy_to_user(buf, &val, sizeof(val))) | |
1028 | goto read_err; | |
1029 | ||
1030 | filled = 1; | |
1031 | } | |
1032 | ||
1033 | count -= filled; | |
1034 | done += filled; | |
1035 | *ppos += filled; | |
1036 | buf += filled; | |
1037 | } | |
1038 | ||
1039 | return done; | |
1040 | ||
1041 | read_err: | |
1042 | return -EFAULT; | |
1043 | } | |
1044 | ||
978cf586 | 1045 | static ssize_t intel_vgpu_write(struct vfio_device *vfio_dev, |
659643f7 JS |
1046 | const char __user *buf, |
1047 | size_t count, loff_t *ppos) | |
1048 | { | |
978cf586 | 1049 | struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); |
659643f7 JS |
1050 | unsigned int done = 0; |
1051 | int ret; | |
1052 | ||
1053 | while (count) { | |
1054 | size_t filled; | |
1055 | ||
a26ca6ad TZ |
1056 | /* Only support GGTT entry 8 bytes write */ |
1057 | if (count >= 8 && !(*ppos % 8) && | |
7f11e689 | 1058 | gtt_entry(vgpu, ppos)) { |
a26ca6ad TZ |
1059 | u64 val; |
1060 | ||
1061 | if (copy_from_user(&val, buf, sizeof(val))) | |
1062 | goto write_err; | |
1063 | ||
7f11e689 | 1064 | ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val), |
a26ca6ad TZ |
1065 | ppos, true); |
1066 | if (ret <= 0) | |
1067 | goto write_err; | |
1068 | ||
1069 | filled = 8; | |
1070 | } else if (count >= 4 && !(*ppos % 4)) { | |
659643f7 JS |
1071 | u32 val; |
1072 | ||
1073 | if (copy_from_user(&val, buf, sizeof(val))) | |
1074 | goto write_err; | |
1075 | ||
7f11e689 | 1076 | ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val), |
659643f7 JS |
1077 | ppos, true); |
1078 | if (ret <= 0) | |
1079 | goto write_err; | |
1080 | ||
1081 | filled = 4; | |
1082 | } else if (count >= 2 && !(*ppos % 2)) { | |
1083 | u16 val; | |
1084 | ||
1085 | if (copy_from_user(&val, buf, sizeof(val))) | |
1086 | goto write_err; | |
1087 | ||
7f11e689 | 1088 | ret = intel_vgpu_rw(vgpu, (char *)&val, |
659643f7 JS |
1089 | sizeof(val), ppos, true); |
1090 | if (ret <= 0) | |
1091 | goto write_err; | |
1092 | ||
1093 | filled = 2; | |
1094 | } else { | |
1095 | u8 val; | |
1096 | ||
1097 | if (copy_from_user(&val, buf, sizeof(val))) | |
1098 | goto write_err; | |
1099 | ||
7f11e689 | 1100 | ret = intel_vgpu_rw(vgpu, &val, sizeof(val), |
659643f7 JS |
1101 | ppos, true); |
1102 | if (ret <= 0) | |
1103 | goto write_err; | |
1104 | ||
1105 | filled = 1; | |
1106 | } | |
1107 | ||
1108 | count -= filled; | |
1109 | done += filled; | |
1110 | *ppos += filled; | |
1111 | buf += filled; | |
1112 | } | |
1113 | ||
1114 | return done; | |
1115 | write_err: | |
1116 | return -EFAULT; | |
1117 | } | |
1118 | ||
978cf586 CH |
1119 | static int intel_vgpu_mmap(struct vfio_device *vfio_dev, |
1120 | struct vm_area_struct *vma) | |
659643f7 | 1121 | { |
978cf586 | 1122 | struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); |
659643f7 JS |
1123 | unsigned int index; |
1124 | u64 virtaddr; | |
51b00d85 | 1125 | unsigned long req_size, pgoff, req_start; |
659643f7 | 1126 | pgprot_t pg_prot; |
659643f7 JS |
1127 | |
1128 | index = vma->vm_pgoff >> (VFIO_PCI_OFFSET_SHIFT - PAGE_SHIFT); | |
1129 | if (index >= VFIO_PCI_ROM_REGION_INDEX) | |
1130 | return -EINVAL; | |
1131 | ||
1132 | if (vma->vm_end < vma->vm_start) | |
1133 | return -EINVAL; | |
1134 | if ((vma->vm_flags & VM_SHARED) == 0) | |
1135 | return -EINVAL; | |
1136 | if (index != VFIO_PCI_BAR2_REGION_INDEX) | |
1137 | return -EINVAL; | |
1138 | ||
1139 | pg_prot = vma->vm_page_prot; | |
1140 | virtaddr = vma->vm_start; | |
1141 | req_size = vma->vm_end - vma->vm_start; | |
51b00d85 ZW |
1142 | pgoff = vma->vm_pgoff & |
1143 | ((1U << (VFIO_PCI_OFFSET_SHIFT - PAGE_SHIFT)) - 1); | |
1144 | req_start = pgoff << PAGE_SHIFT; | |
1145 | ||
1146 | if (!intel_vgpu_in_aperture(vgpu, req_start)) | |
1147 | return -EINVAL; | |
1148 | if (req_start + req_size > | |
1149 | vgpu_aperture_offset(vgpu) + vgpu_aperture_sz(vgpu)) | |
1150 | return -EINVAL; | |
1151 | ||
1152 | pgoff = (gvt_aperture_pa_base(vgpu->gvt) >> PAGE_SHIFT) + pgoff; | |
659643f7 JS |
1153 | |
1154 | return remap_pfn_range(vma, virtaddr, pgoff, req_size, pg_prot); | |
1155 | } | |
1156 | ||
1157 | static int intel_vgpu_get_irq_count(struct intel_vgpu *vgpu, int type) | |
1158 | { | |
1159 | if (type == VFIO_PCI_INTX_IRQ_INDEX || type == VFIO_PCI_MSI_IRQ_INDEX) | |
1160 | return 1; | |
1161 | ||
1162 | return 0; | |
1163 | } | |
1164 | ||
1165 | static int intel_vgpu_set_intx_mask(struct intel_vgpu *vgpu, | |
1166 | unsigned int index, unsigned int start, | |
2e679d48 | 1167 | unsigned int count, u32 flags, |
659643f7 JS |
1168 | void *data) |
1169 | { | |
1170 | return 0; | |
1171 | } | |
1172 | ||
1173 | static int intel_vgpu_set_intx_unmask(struct intel_vgpu *vgpu, | |
1174 | unsigned int index, unsigned int start, | |
2e679d48 | 1175 | unsigned int count, u32 flags, void *data) |
659643f7 JS |
1176 | { |
1177 | return 0; | |
1178 | } | |
1179 | ||
1180 | static int intel_vgpu_set_intx_trigger(struct intel_vgpu *vgpu, | |
1181 | unsigned int index, unsigned int start, unsigned int count, | |
2e679d48 | 1182 | u32 flags, void *data) |
659643f7 JS |
1183 | { |
1184 | return 0; | |
1185 | } | |
1186 | ||
1187 | static int intel_vgpu_set_msi_trigger(struct intel_vgpu *vgpu, | |
1188 | unsigned int index, unsigned int start, unsigned int count, | |
2e679d48 | 1189 | u32 flags, void *data) |
659643f7 JS |
1190 | { |
1191 | struct eventfd_ctx *trigger; | |
1192 | ||
1193 | if (flags & VFIO_IRQ_SET_DATA_EVENTFD) { | |
1194 | int fd = *(int *)data; | |
1195 | ||
1196 | trigger = eventfd_ctx_fdget(fd); | |
1197 | if (IS_ERR(trigger)) { | |
695fbc08 | 1198 | gvt_vgpu_err("eventfd_ctx_fdget failed\n"); |
659643f7 JS |
1199 | return PTR_ERR(trigger); |
1200 | } | |
62980cac | 1201 | vgpu->msi_trigger = trigger; |
d54e7934 XZ |
1202 | } else if ((flags & VFIO_IRQ_SET_DATA_NONE) && !count) |
1203 | intel_vgpu_release_msi_eventfd_ctx(vgpu); | |
659643f7 JS |
1204 | |
1205 | return 0; | |
1206 | } | |
1207 | ||
2e679d48 | 1208 | static int intel_vgpu_set_irqs(struct intel_vgpu *vgpu, u32 flags, |
659643f7 JS |
1209 | unsigned int index, unsigned int start, unsigned int count, |
1210 | void *data) | |
1211 | { | |
1212 | int (*func)(struct intel_vgpu *vgpu, unsigned int index, | |
2e679d48 | 1213 | unsigned int start, unsigned int count, u32 flags, |
659643f7 JS |
1214 | void *data) = NULL; |
1215 | ||
1216 | switch (index) { | |
1217 | case VFIO_PCI_INTX_IRQ_INDEX: | |
1218 | switch (flags & VFIO_IRQ_SET_ACTION_TYPE_MASK) { | |
1219 | case VFIO_IRQ_SET_ACTION_MASK: | |
1220 | func = intel_vgpu_set_intx_mask; | |
1221 | break; | |
1222 | case VFIO_IRQ_SET_ACTION_UNMASK: | |
1223 | func = intel_vgpu_set_intx_unmask; | |
1224 | break; | |
1225 | case VFIO_IRQ_SET_ACTION_TRIGGER: | |
1226 | func = intel_vgpu_set_intx_trigger; | |
1227 | break; | |
1228 | } | |
1229 | break; | |
1230 | case VFIO_PCI_MSI_IRQ_INDEX: | |
1231 | switch (flags & VFIO_IRQ_SET_ACTION_TYPE_MASK) { | |
1232 | case VFIO_IRQ_SET_ACTION_MASK: | |
1233 | case VFIO_IRQ_SET_ACTION_UNMASK: | |
1234 | /* XXX Need masking support exported */ | |
1235 | break; | |
1236 | case VFIO_IRQ_SET_ACTION_TRIGGER: | |
1237 | func = intel_vgpu_set_msi_trigger; | |
1238 | break; | |
1239 | } | |
1240 | break; | |
1241 | } | |
1242 | ||
1243 | if (!func) | |
1244 | return -ENOTTY; | |
1245 | ||
1246 | return func(vgpu, index, start, count, flags, data); | |
1247 | } | |
1248 | ||
978cf586 | 1249 | static long intel_vgpu_ioctl(struct vfio_device *vfio_dev, unsigned int cmd, |
659643f7 JS |
1250 | unsigned long arg) |
1251 | { | |
978cf586 | 1252 | struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); |
659643f7 JS |
1253 | unsigned long minsz; |
1254 | ||
1255 | gvt_dbg_core("vgpu%d ioctl, cmd: %d\n", vgpu->id, cmd); | |
1256 | ||
1257 | if (cmd == VFIO_DEVICE_GET_INFO) { | |
1258 | struct vfio_device_info info; | |
1259 | ||
1260 | minsz = offsetofend(struct vfio_device_info, num_irqs); | |
1261 | ||
1262 | if (copy_from_user(&info, (void __user *)arg, minsz)) | |
1263 | return -EFAULT; | |
1264 | ||
1265 | if (info.argsz < minsz) | |
1266 | return -EINVAL; | |
1267 | ||
1268 | info.flags = VFIO_DEVICE_FLAGS_PCI; | |
1269 | info.flags |= VFIO_DEVICE_FLAGS_RESET; | |
b851adea | 1270 | info.num_regions = VFIO_PCI_NUM_REGIONS + |
62980cac | 1271 | vgpu->num_regions; |
659643f7 JS |
1272 | info.num_irqs = VFIO_PCI_NUM_IRQS; |
1273 | ||
1274 | return copy_to_user((void __user *)arg, &info, minsz) ? | |
1275 | -EFAULT : 0; | |
1276 | ||
1277 | } else if (cmd == VFIO_DEVICE_GET_REGION_INFO) { | |
1278 | struct vfio_region_info info; | |
1279 | struct vfio_info_cap caps = { .buf = NULL, .size = 0 }; | |
de5372da GS |
1280 | unsigned int i; |
1281 | int ret; | |
659643f7 | 1282 | struct vfio_region_info_cap_sparse_mmap *sparse = NULL; |
659643f7 JS |
1283 | int nr_areas = 1; |
1284 | int cap_type_id; | |
1285 | ||
1286 | minsz = offsetofend(struct vfio_region_info, offset); | |
1287 | ||
1288 | if (copy_from_user(&info, (void __user *)arg, minsz)) | |
1289 | return -EFAULT; | |
1290 | ||
1291 | if (info.argsz < minsz) | |
1292 | return -EINVAL; | |
1293 | ||
1294 | switch (info.index) { | |
1295 | case VFIO_PCI_CONFIG_REGION_INDEX: | |
1296 | info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); | |
02d578e5 | 1297 | info.size = vgpu->gvt->device_info.cfg_space_size; |
659643f7 JS |
1298 | info.flags = VFIO_REGION_INFO_FLAG_READ | |
1299 | VFIO_REGION_INFO_FLAG_WRITE; | |
1300 | break; | |
1301 | case VFIO_PCI_BAR0_REGION_INDEX: | |
1302 | info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); | |
1303 | info.size = vgpu->cfg_space.bar[info.index].size; | |
1304 | if (!info.size) { | |
1305 | info.flags = 0; | |
1306 | break; | |
1307 | } | |
1308 | ||
1309 | info.flags = VFIO_REGION_INFO_FLAG_READ | | |
1310 | VFIO_REGION_INFO_FLAG_WRITE; | |
1311 | break; | |
1312 | case VFIO_PCI_BAR1_REGION_INDEX: | |
1313 | info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); | |
1314 | info.size = 0; | |
1315 | info.flags = 0; | |
1316 | break; | |
1317 | case VFIO_PCI_BAR2_REGION_INDEX: | |
1318 | info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); | |
1319 | info.flags = VFIO_REGION_INFO_FLAG_CAPS | | |
1320 | VFIO_REGION_INFO_FLAG_MMAP | | |
1321 | VFIO_REGION_INFO_FLAG_READ | | |
1322 | VFIO_REGION_INFO_FLAG_WRITE; | |
1323 | info.size = gvt_aperture_sz(vgpu->gvt); | |
1324 | ||
cd3e0583 GS |
1325 | sparse = kzalloc(struct_size(sparse, areas, nr_areas), |
1326 | GFP_KERNEL); | |
659643f7 JS |
1327 | if (!sparse) |
1328 | return -ENOMEM; | |
1329 | ||
dda01f78 AW |
1330 | sparse->header.id = VFIO_REGION_INFO_CAP_SPARSE_MMAP; |
1331 | sparse->header.version = 1; | |
659643f7 JS |
1332 | sparse->nr_areas = nr_areas; |
1333 | cap_type_id = VFIO_REGION_INFO_CAP_SPARSE_MMAP; | |
1334 | sparse->areas[0].offset = | |
1335 | PAGE_ALIGN(vgpu_aperture_offset(vgpu)); | |
1336 | sparse->areas[0].size = vgpu_aperture_sz(vgpu); | |
659643f7 JS |
1337 | break; |
1338 | ||
1339 | case VFIO_PCI_BAR3_REGION_INDEX ... VFIO_PCI_BAR5_REGION_INDEX: | |
1340 | info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); | |
1341 | info.size = 0; | |
659643f7 | 1342 | info.flags = 0; |
072ec93d | 1343 | |
659643f7 JS |
1344 | gvt_dbg_core("get region info bar:%d\n", info.index); |
1345 | break; | |
1346 | ||
1347 | case VFIO_PCI_ROM_REGION_INDEX: | |
1348 | case VFIO_PCI_VGA_REGION_INDEX: | |
072ec93d PZ |
1349 | info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); |
1350 | info.size = 0; | |
1351 | info.flags = 0; | |
1352 | ||
659643f7 JS |
1353 | gvt_dbg_core("get region info index:%d\n", info.index); |
1354 | break; | |
1355 | default: | |
1356 | { | |
dda01f78 AW |
1357 | struct vfio_region_info_cap_type cap_type = { |
1358 | .header.id = VFIO_REGION_INFO_CAP_TYPE, | |
1359 | .header.version = 1 }; | |
659643f7 JS |
1360 | |
1361 | if (info.index >= VFIO_PCI_NUM_REGIONS + | |
62980cac | 1362 | vgpu->num_regions) |
659643f7 | 1363 | return -EINVAL; |
de5372da GS |
1364 | info.index = |
1365 | array_index_nospec(info.index, | |
1366 | VFIO_PCI_NUM_REGIONS + | |
62980cac | 1367 | vgpu->num_regions); |
659643f7 JS |
1368 | |
1369 | i = info.index - VFIO_PCI_NUM_REGIONS; | |
1370 | ||
1371 | info.offset = | |
1372 | VFIO_PCI_INDEX_TO_OFFSET(info.index); | |
62980cac CH |
1373 | info.size = vgpu->region[i].size; |
1374 | info.flags = vgpu->region[i].flags; | |
659643f7 | 1375 | |
62980cac CH |
1376 | cap_type.type = vgpu->region[i].type; |
1377 | cap_type.subtype = vgpu->region[i].subtype; | |
659643f7 JS |
1378 | |
1379 | ret = vfio_info_add_capability(&caps, | |
dda01f78 AW |
1380 | &cap_type.header, |
1381 | sizeof(cap_type)); | |
659643f7 JS |
1382 | if (ret) |
1383 | return ret; | |
1384 | } | |
1385 | } | |
1386 | ||
1387 | if ((info.flags & VFIO_REGION_INFO_FLAG_CAPS) && sparse) { | |
1388 | switch (cap_type_id) { | |
1389 | case VFIO_REGION_INFO_CAP_SPARSE_MMAP: | |
1390 | ret = vfio_info_add_capability(&caps, | |
cd3e0583 GS |
1391 | &sparse->header, |
1392 | struct_size(sparse, areas, | |
1393 | sparse->nr_areas)); | |
7590ebb8 YW |
1394 | if (ret) { |
1395 | kfree(sparse); | |
659643f7 | 1396 | return ret; |
7590ebb8 | 1397 | } |
659643f7 JS |
1398 | break; |
1399 | default: | |
7590ebb8 | 1400 | kfree(sparse); |
659643f7 JS |
1401 | return -EINVAL; |
1402 | } | |
1403 | } | |
1404 | ||
1405 | if (caps.size) { | |
b851adea | 1406 | info.flags |= VFIO_REGION_INFO_FLAG_CAPS; |
659643f7 JS |
1407 | if (info.argsz < sizeof(info) + caps.size) { |
1408 | info.argsz = sizeof(info) + caps.size; | |
1409 | info.cap_offset = 0; | |
1410 | } else { | |
1411 | vfio_info_cap_shift(&caps, sizeof(info)); | |
1412 | if (copy_to_user((void __user *)arg + | |
1413 | sizeof(info), caps.buf, | |
1414 | caps.size)) { | |
1415 | kfree(caps.buf); | |
7590ebb8 | 1416 | kfree(sparse); |
659643f7 JS |
1417 | return -EFAULT; |
1418 | } | |
1419 | info.cap_offset = sizeof(info); | |
1420 | } | |
1421 | ||
1422 | kfree(caps.buf); | |
1423 | } | |
1424 | ||
7590ebb8 | 1425 | kfree(sparse); |
659643f7 JS |
1426 | return copy_to_user((void __user *)arg, &info, minsz) ? |
1427 | -EFAULT : 0; | |
1428 | } else if (cmd == VFIO_DEVICE_GET_IRQ_INFO) { | |
1429 | struct vfio_irq_info info; | |
1430 | ||
1431 | minsz = offsetofend(struct vfio_irq_info, count); | |
1432 | ||
1433 | if (copy_from_user(&info, (void __user *)arg, minsz)) | |
1434 | return -EFAULT; | |
1435 | ||
1436 | if (info.argsz < minsz || info.index >= VFIO_PCI_NUM_IRQS) | |
1437 | return -EINVAL; | |
1438 | ||
1439 | switch (info.index) { | |
1440 | case VFIO_PCI_INTX_IRQ_INDEX: | |
1441 | case VFIO_PCI_MSI_IRQ_INDEX: | |
1442 | break; | |
1443 | default: | |
1444 | return -EINVAL; | |
1445 | } | |
1446 | ||
1447 | info.flags = VFIO_IRQ_INFO_EVENTFD; | |
1448 | ||
1449 | info.count = intel_vgpu_get_irq_count(vgpu, info.index); | |
1450 | ||
1451 | if (info.index == VFIO_PCI_INTX_IRQ_INDEX) | |
1452 | info.flags |= (VFIO_IRQ_INFO_MASKABLE | | |
1453 | VFIO_IRQ_INFO_AUTOMASKED); | |
1454 | else | |
1455 | info.flags |= VFIO_IRQ_INFO_NORESIZE; | |
1456 | ||
1457 | return copy_to_user((void __user *)arg, &info, minsz) ? | |
1458 | -EFAULT : 0; | |
1459 | } else if (cmd == VFIO_DEVICE_SET_IRQS) { | |
1460 | struct vfio_irq_set hdr; | |
1461 | u8 *data = NULL; | |
1462 | int ret = 0; | |
1463 | size_t data_size = 0; | |
1464 | ||
1465 | minsz = offsetofend(struct vfio_irq_set, count); | |
1466 | ||
1467 | if (copy_from_user(&hdr, (void __user *)arg, minsz)) | |
1468 | return -EFAULT; | |
1469 | ||
1470 | if (!(hdr.flags & VFIO_IRQ_SET_DATA_NONE)) { | |
1471 | int max = intel_vgpu_get_irq_count(vgpu, hdr.index); | |
1472 | ||
1473 | ret = vfio_set_irqs_validate_and_prepare(&hdr, max, | |
1474 | VFIO_PCI_NUM_IRQS, &data_size); | |
1475 | if (ret) { | |
695fbc08 | 1476 | gvt_vgpu_err("intel:vfio_set_irqs_validate_and_prepare failed\n"); |
659643f7 JS |
1477 | return -EINVAL; |
1478 | } | |
1479 | if (data_size) { | |
1480 | data = memdup_user((void __user *)(arg + minsz), | |
1481 | data_size); | |
1482 | if (IS_ERR(data)) | |
1483 | return PTR_ERR(data); | |
1484 | } | |
1485 | } | |
1486 | ||
1487 | ret = intel_vgpu_set_irqs(vgpu, hdr.flags, hdr.index, | |
1488 | hdr.start, hdr.count, data); | |
1489 | kfree(data); | |
1490 | ||
1491 | return ret; | |
1492 | } else if (cmd == VFIO_DEVICE_RESET) { | |
675e5c4a | 1493 | intel_gvt_reset_vgpu(vgpu); |
659643f7 | 1494 | return 0; |
e546e281 TZ |
1495 | } else if (cmd == VFIO_DEVICE_QUERY_GFX_PLANE) { |
1496 | struct vfio_device_gfx_plane_info dmabuf; | |
1497 | int ret = 0; | |
1498 | ||
1499 | minsz = offsetofend(struct vfio_device_gfx_plane_info, | |
1500 | dmabuf_id); | |
1501 | if (copy_from_user(&dmabuf, (void __user *)arg, minsz)) | |
1502 | return -EFAULT; | |
1503 | if (dmabuf.argsz < minsz) | |
1504 | return -EINVAL; | |
1505 | ||
675e5c4a | 1506 | ret = intel_vgpu_query_plane(vgpu, &dmabuf); |
e546e281 TZ |
1507 | if (ret != 0) |
1508 | return ret; | |
1509 | ||
1510 | return copy_to_user((void __user *)arg, &dmabuf, minsz) ? | |
1511 | -EFAULT : 0; | |
1512 | } else if (cmd == VFIO_DEVICE_GET_GFX_DMABUF) { | |
1513 | __u32 dmabuf_id; | |
e546e281 TZ |
1514 | |
1515 | if (get_user(dmabuf_id, (__u32 __user *)arg)) | |
1516 | return -EFAULT; | |
675e5c4a | 1517 | return intel_vgpu_get_dmabuf(vgpu, dmabuf_id); |
659643f7 JS |
1518 | } |
1519 | ||
9f591ae6 | 1520 | return -ENOTTY; |
659643f7 JS |
1521 | } |
1522 | ||
7a7a6561 ZW |
1523 | static ssize_t |
1524 | vgpu_id_show(struct device *dev, struct device_attribute *attr, | |
1525 | char *buf) | |
1526 | { | |
978cf586 | 1527 | struct intel_vgpu *vgpu = dev_get_drvdata(dev); |
7a7a6561 | 1528 | |
978cf586 | 1529 | return sprintf(buf, "%d\n", vgpu->id); |
7a7a6561 ZW |
1530 | } |
1531 | ||
1532 | static DEVICE_ATTR_RO(vgpu_id); | |
1533 | ||
1534 | static struct attribute *intel_vgpu_attrs[] = { | |
1535 | &dev_attr_vgpu_id.attr, | |
1536 | NULL | |
1537 | }; | |
1538 | ||
1539 | static const struct attribute_group intel_vgpu_group = { | |
1540 | .name = "intel_vgpu", | |
1541 | .attrs = intel_vgpu_attrs, | |
1542 | }; | |
1543 | ||
1544 | static const struct attribute_group *intel_vgpu_groups[] = { | |
1545 | &intel_vgpu_group, | |
1546 | NULL, | |
1547 | }; | |
1548 | ||
a5ddd2a9 KT |
1549 | static int intel_vgpu_init_dev(struct vfio_device *vfio_dev) |
1550 | { | |
1551 | struct mdev_device *mdev = to_mdev_device(vfio_dev->dev); | |
1552 | struct device *pdev = mdev_parent_dev(mdev); | |
1553 | struct intel_gvt *gvt = kdev_to_i915(pdev)->gvt; | |
1554 | struct intel_vgpu_type *type; | |
1555 | struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); | |
1556 | ||
1557 | type = &gvt->types[mdev_get_type_group_id(mdev)]; | |
1558 | if (!type) | |
1559 | return -EINVAL; | |
1560 | ||
1561 | vgpu->gvt = gvt; | |
1562 | return intel_gvt_create_vgpu(vgpu, type); | |
1563 | } | |
1564 | ||
1565 | static void intel_vgpu_release_dev(struct vfio_device *vfio_dev) | |
1566 | { | |
1567 | struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); | |
1568 | ||
1569 | intel_gvt_destroy_vgpu(vgpu); | |
1570 | vfio_free_device(vfio_dev); | |
1571 | } | |
1572 | ||
978cf586 | 1573 | static const struct vfio_device_ops intel_vgpu_dev_ops = { |
a5ddd2a9 KT |
1574 | .init = intel_vgpu_init_dev, |
1575 | .release = intel_vgpu_release_dev, | |
978cf586 CH |
1576 | .open_device = intel_vgpu_open_device, |
1577 | .close_device = intel_vgpu_close_device, | |
1578 | .read = intel_vgpu_read, | |
1579 | .write = intel_vgpu_write, | |
1580 | .mmap = intel_vgpu_mmap, | |
1581 | .ioctl = intel_vgpu_ioctl, | |
ce4b4657 | 1582 | .dma_unmap = intel_vgpu_dma_unmap, |
978cf586 | 1583 | }; |
659643f7 | 1584 | |
978cf586 CH |
1585 | static int intel_vgpu_probe(struct mdev_device *mdev) |
1586 | { | |
978cf586 CH |
1587 | struct intel_vgpu *vgpu; |
1588 | int ret; | |
1589 | ||
a5ddd2a9 KT |
1590 | vgpu = vfio_alloc_device(intel_vgpu, vfio_device, &mdev->dev, |
1591 | &intel_vgpu_dev_ops); | |
978cf586 CH |
1592 | if (IS_ERR(vgpu)) { |
1593 | gvt_err("failed to create intel vgpu: %ld\n", PTR_ERR(vgpu)); | |
1594 | return PTR_ERR(vgpu); | |
1595 | } | |
659643f7 | 1596 | |
978cf586 CH |
1597 | dev_set_drvdata(&mdev->dev, vgpu); |
1598 | ret = vfio_register_emulated_iommu_dev(&vgpu->vfio_device); | |
a5ddd2a9 KT |
1599 | if (ret) |
1600 | goto out_put_vdev; | |
978cf586 CH |
1601 | |
1602 | gvt_dbg_core("intel_vgpu_create succeeded for mdev: %s\n", | |
1603 | dev_name(mdev_dev(mdev))); | |
1604 | return 0; | |
a5ddd2a9 KT |
1605 | |
1606 | out_put_vdev: | |
1607 | vfio_put_device(&vgpu->vfio_device); | |
1608 | return ret; | |
978cf586 CH |
1609 | } |
1610 | ||
1611 | static void intel_vgpu_remove(struct mdev_device *mdev) | |
1612 | { | |
1613 | struct intel_vgpu *vgpu = dev_get_drvdata(&mdev->dev); | |
1614 | ||
1615 | if (WARN_ON_ONCE(vgpu->attached)) | |
1616 | return; | |
a5ddd2a9 | 1617 | |
f423fa1b | 1618 | vfio_unregister_group_dev(&vgpu->vfio_device); |
a5ddd2a9 | 1619 | vfio_put_device(&vgpu->vfio_device); |
978cf586 CH |
1620 | } |
1621 | ||
1622 | static struct mdev_driver intel_vgpu_mdev_driver = { | |
1623 | .driver = { | |
1624 | .name = "intel_vgpu_mdev", | |
1625 | .owner = THIS_MODULE, | |
1626 | .dev_groups = intel_vgpu_groups, | |
1627 | }, | |
1628 | .probe = intel_vgpu_probe, | |
1629 | .remove = intel_vgpu_remove, | |
978cf586 | 1630 | .supported_type_groups = gvt_vgpu_type_groups, |
659643f7 JS |
1631 | }; |
1632 | ||
4c2baaaf | 1633 | int intel_gvt_page_track_add(struct intel_vgpu *info, u64 gfn) |
f30437c5 | 1634 | { |
421cfe65 | 1635 | struct kvm *kvm = info->vfio_device.kvm; |
f30437c5 JS |
1636 | struct kvm_memory_slot *slot; |
1637 | int idx; | |
1638 | ||
3c340d05 | 1639 | if (!info->attached) |
659643f7 JS |
1640 | return -ESRCH; |
1641 | ||
f30437c5 JS |
1642 | idx = srcu_read_lock(&kvm->srcu); |
1643 | slot = gfn_to_memslot(kvm, gfn); | |
faaaa53b JS |
1644 | if (!slot) { |
1645 | srcu_read_unlock(&kvm->srcu, idx); | |
1646 | return -EINVAL; | |
1647 | } | |
f30437c5 | 1648 | |
e36b250e | 1649 | write_lock(&kvm->mmu_lock); |
f30437c5 JS |
1650 | |
1651 | if (kvmgt_gfn_is_write_protected(info, gfn)) | |
1652 | goto out; | |
1653 | ||
1654 | kvm_slot_page_track_add_page(kvm, slot, gfn, KVM_PAGE_TRACK_WRITE); | |
1655 | kvmgt_protect_table_add(info, gfn); | |
1656 | ||
1657 | out: | |
e36b250e | 1658 | write_unlock(&kvm->mmu_lock); |
f30437c5 JS |
1659 | srcu_read_unlock(&kvm->srcu, idx); |
1660 | return 0; | |
1661 | } | |
1662 | ||
4c2baaaf | 1663 | int intel_gvt_page_track_remove(struct intel_vgpu *info, u64 gfn) |
f30437c5 | 1664 | { |
421cfe65 | 1665 | struct kvm *kvm = info->vfio_device.kvm; |
f30437c5 JS |
1666 | struct kvm_memory_slot *slot; |
1667 | int idx; | |
1668 | ||
3c340d05 | 1669 | if (!info->attached) |
659643f7 JS |
1670 | return 0; |
1671 | ||
f30437c5 JS |
1672 | idx = srcu_read_lock(&kvm->srcu); |
1673 | slot = gfn_to_memslot(kvm, gfn); | |
faaaa53b JS |
1674 | if (!slot) { |
1675 | srcu_read_unlock(&kvm->srcu, idx); | |
1676 | return -EINVAL; | |
1677 | } | |
f30437c5 | 1678 | |
e36b250e | 1679 | write_lock(&kvm->mmu_lock); |
f30437c5 JS |
1680 | |
1681 | if (!kvmgt_gfn_is_write_protected(info, gfn)) | |
1682 | goto out; | |
1683 | ||
1684 | kvm_slot_page_track_remove_page(kvm, slot, gfn, KVM_PAGE_TRACK_WRITE); | |
1685 | kvmgt_protect_table_del(info, gfn); | |
1686 | ||
1687 | out: | |
e36b250e | 1688 | write_unlock(&kvm->mmu_lock); |
f30437c5 JS |
1689 | srcu_read_unlock(&kvm->srcu, idx); |
1690 | return 0; | |
1691 | } | |
1692 | ||
1693 | static void kvmgt_page_track_write(struct kvm_vcpu *vcpu, gpa_t gpa, | |
1694 | const u8 *val, int len, | |
1695 | struct kvm_page_track_notifier_node *node) | |
1696 | { | |
10ddb962 CH |
1697 | struct intel_vgpu *info = |
1698 | container_of(node, struct intel_vgpu, track_node); | |
f30437c5 JS |
1699 | |
1700 | if (kvmgt_gfn_is_write_protected(info, gpa_to_gfn(gpa))) | |
10ddb962 | 1701 | intel_vgpu_page_track_handler(info, gpa, |
4fafba2d | 1702 | (void *)val, len); |
f30437c5 JS |
1703 | } |
1704 | ||
1705 | static void kvmgt_page_track_flush_slot(struct kvm *kvm, | |
1706 | struct kvm_memory_slot *slot, | |
1707 | struct kvm_page_track_notifier_node *node) | |
1708 | { | |
1709 | int i; | |
1710 | gfn_t gfn; | |
10ddb962 CH |
1711 | struct intel_vgpu *info = |
1712 | container_of(node, struct intel_vgpu, track_node); | |
f30437c5 | 1713 | |
e36b250e | 1714 | write_lock(&kvm->mmu_lock); |
f30437c5 JS |
1715 | for (i = 0; i < slot->npages; i++) { |
1716 | gfn = slot->base_gfn + i; | |
1717 | if (kvmgt_gfn_is_write_protected(info, gfn)) { | |
1718 | kvm_slot_page_track_remove_page(kvm, slot, gfn, | |
1719 | KVM_PAGE_TRACK_WRITE); | |
1720 | kvmgt_protect_table_del(info, gfn); | |
1721 | } | |
1722 | } | |
e36b250e | 1723 | write_unlock(&kvm->mmu_lock); |
f30437c5 JS |
1724 | } |
1725 | ||
4c705ad0 | 1726 | void intel_vgpu_detach_regions(struct intel_vgpu *vgpu) |
f30437c5 | 1727 | { |
6c2d0f99 | 1728 | int i; |
6c2d0f99 | 1729 | |
62980cac | 1730 | if (!vgpu->region) |
6c2d0f99 HY |
1731 | return; |
1732 | ||
62980cac CH |
1733 | for (i = 0; i < vgpu->num_regions; i++) |
1734 | if (vgpu->region[i].ops->release) | |
1735 | vgpu->region[i].ops->release(vgpu, | |
1736 | &vgpu->region[i]); | |
1737 | vgpu->num_regions = 0; | |
1738 | kfree(vgpu->region); | |
1739 | vgpu->region = NULL; | |
f30437c5 JS |
1740 | } |
1741 | ||
8398eee8 | 1742 | int intel_gvt_dma_map_guest_page(struct intel_vgpu *vgpu, unsigned long gfn, |
79e542f5 | 1743 | unsigned long size, dma_addr_t *dma_addr) |
cf4ee73f | 1744 | { |
cf4ee73f CD |
1745 | struct gvt_dma *entry; |
1746 | int ret; | |
1747 | ||
3c340d05 | 1748 | if (!vgpu->attached) |
cf4ee73f CD |
1749 | return -EINVAL; |
1750 | ||
62980cac | 1751 | mutex_lock(&vgpu->cache_lock); |
cf4ee73f | 1752 | |
06d63c48 | 1753 | entry = __gvt_cache_find_gfn(vgpu, gfn); |
cf4ee73f | 1754 | if (!entry) { |
7366aeb7 XZ |
1755 | ret = gvt_dma_map_page(vgpu, gfn, dma_addr, size); |
1756 | if (ret) | |
1757 | goto err_unlock; | |
1758 | ||
06d63c48 | 1759 | ret = __gvt_cache_add(vgpu, gfn, *dma_addr, size); |
7366aeb7 XZ |
1760 | if (ret) |
1761 | goto err_unmap; | |
1762 | } else if (entry->size != size) { | |
1763 | /* the same gfn with different size: unmap and re-map */ | |
1764 | gvt_dma_unmap_page(vgpu, gfn, entry->dma_addr, entry->size); | |
1765 | __gvt_cache_remove_entry(vgpu, entry); | |
1766 | ||
79e542f5 | 1767 | ret = gvt_dma_map_page(vgpu, gfn, dma_addr, size); |
5cd4223e CD |
1768 | if (ret) |
1769 | goto err_unlock; | |
1770 | ||
06d63c48 | 1771 | ret = __gvt_cache_add(vgpu, gfn, *dma_addr, size); |
5cd4223e CD |
1772 | if (ret) |
1773 | goto err_unmap; | |
cf4ee73f CD |
1774 | } else { |
1775 | kref_get(&entry->ref); | |
1776 | *dma_addr = entry->dma_addr; | |
4a0b3444 | 1777 | } |
f30437c5 | 1778 | |
62980cac | 1779 | mutex_unlock(&vgpu->cache_lock); |
cf4ee73f | 1780 | return 0; |
5cd4223e CD |
1781 | |
1782 | err_unmap: | |
79e542f5 | 1783 | gvt_dma_unmap_page(vgpu, gfn, *dma_addr, size); |
5cd4223e | 1784 | err_unlock: |
62980cac | 1785 | mutex_unlock(&vgpu->cache_lock); |
5cd4223e | 1786 | return ret; |
cf4ee73f CD |
1787 | } |
1788 | ||
91879bba | 1789 | int intel_gvt_dma_pin_guest_page(struct intel_vgpu *vgpu, dma_addr_t dma_addr) |
9f674c81 | 1790 | { |
9f674c81 TZ |
1791 | struct gvt_dma *entry; |
1792 | int ret = 0; | |
1793 | ||
3c340d05 | 1794 | if (!vgpu->attached) |
9f674c81 TZ |
1795 | return -ENODEV; |
1796 | ||
10ddb962 CH |
1797 | mutex_lock(&vgpu->cache_lock); |
1798 | entry = __gvt_cache_find_dma_addr(vgpu, dma_addr); | |
9f674c81 TZ |
1799 | if (entry) |
1800 | kref_get(&entry->ref); | |
1801 | else | |
1802 | ret = -ENOMEM; | |
10ddb962 | 1803 | mutex_unlock(&vgpu->cache_lock); |
9f674c81 TZ |
1804 | |
1805 | return ret; | |
1806 | } | |
1807 | ||
cf4ee73f CD |
1808 | static void __gvt_dma_release(struct kref *ref) |
1809 | { | |
1810 | struct gvt_dma *entry = container_of(ref, typeof(*entry), ref); | |
1811 | ||
79e542f5 CD |
1812 | gvt_dma_unmap_page(entry->vgpu, entry->gfn, entry->dma_addr, |
1813 | entry->size); | |
cf4ee73f CD |
1814 | __gvt_cache_remove_entry(entry->vgpu, entry); |
1815 | } | |
1816 | ||
8398eee8 | 1817 | void intel_gvt_dma_unmap_guest_page(struct intel_vgpu *vgpu, |
3c340d05 | 1818 | dma_addr_t dma_addr) |
cf4ee73f | 1819 | { |
cf4ee73f CD |
1820 | struct gvt_dma *entry; |
1821 | ||
3c340d05 | 1822 | if (!vgpu->attached) |
cf4ee73f CD |
1823 | return; |
1824 | ||
62980cac | 1825 | mutex_lock(&vgpu->cache_lock); |
06d63c48 | 1826 | entry = __gvt_cache_find_dma_addr(vgpu, dma_addr); |
cf4ee73f CD |
1827 | if (entry) |
1828 | kref_put(&entry->ref, __gvt_dma_release); | |
62980cac | 1829 | mutex_unlock(&vgpu->cache_lock); |
f30437c5 JS |
1830 | } |
1831 | ||
cba619cb CH |
1832 | static void init_device_info(struct intel_gvt *gvt) |
1833 | { | |
1834 | struct intel_gvt_device_info *info = &gvt->device_info; | |
1835 | struct pci_dev *pdev = to_pci_dev(gvt->gt->i915->drm.dev); | |
1836 | ||
1837 | info->max_support_vgpus = 8; | |
1838 | info->cfg_space_size = PCI_CFG_SPACE_EXP_SIZE; | |
1839 | info->mmio_size = 2 * 1024 * 1024; | |
1840 | info->mmio_bar = 0; | |
1841 | info->gtt_start_offset = 8 * 1024 * 1024; | |
1842 | info->gtt_entry_size = 8; | |
1843 | info->gtt_entry_size_shift = 3; | |
1844 | info->gmadr_bytes_in_cmd = 8; | |
1845 | info->max_surface_size = 36 * 1024 * 1024; | |
1846 | info->msi_cap_offset = pdev->msi_cap; | |
1847 | } | |
1848 | ||
1849 | static void intel_gvt_test_and_emulate_vblank(struct intel_gvt *gvt) | |
1850 | { | |
1851 | struct intel_vgpu *vgpu; | |
1852 | int id; | |
1853 | ||
1854 | mutex_lock(&gvt->lock); | |
1855 | idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) { | |
1856 | if (test_and_clear_bit(INTEL_GVT_REQUEST_EMULATE_VBLANK + id, | |
1857 | (void *)&gvt->service_request)) { | |
1858 | if (vgpu->active) | |
1859 | intel_vgpu_emulate_vblank(vgpu); | |
1860 | } | |
1861 | } | |
1862 | mutex_unlock(&gvt->lock); | |
1863 | } | |
1864 | ||
1865 | static int gvt_service_thread(void *data) | |
1866 | { | |
1867 | struct intel_gvt *gvt = (struct intel_gvt *)data; | |
1868 | int ret; | |
1869 | ||
1870 | gvt_dbg_core("service thread start\n"); | |
1871 | ||
1872 | while (!kthread_should_stop()) { | |
1873 | ret = wait_event_interruptible(gvt->service_thread_wq, | |
1874 | kthread_should_stop() || gvt->service_request); | |
1875 | ||
1876 | if (kthread_should_stop()) | |
1877 | break; | |
1878 | ||
1879 | if (WARN_ONCE(ret, "service thread is waken up by signal.\n")) | |
1880 | continue; | |
1881 | ||
1882 | intel_gvt_test_and_emulate_vblank(gvt); | |
1883 | ||
1884 | if (test_bit(INTEL_GVT_REQUEST_SCHED, | |
1885 | (void *)&gvt->service_request) || | |
1886 | test_bit(INTEL_GVT_REQUEST_EVENT_SCHED, | |
1887 | (void *)&gvt->service_request)) { | |
1888 | intel_gvt_schedule(gvt); | |
1889 | } | |
1890 | } | |
1891 | ||
1892 | return 0; | |
1893 | } | |
1894 | ||
1895 | static void clean_service_thread(struct intel_gvt *gvt) | |
1896 | { | |
1897 | kthread_stop(gvt->service_thread); | |
1898 | } | |
1899 | ||
1900 | static int init_service_thread(struct intel_gvt *gvt) | |
1901 | { | |
1902 | init_waitqueue_head(&gvt->service_thread_wq); | |
1903 | ||
1904 | gvt->service_thread = kthread_run(gvt_service_thread, | |
1905 | gvt, "gvt_service_thread"); | |
1906 | if (IS_ERR(gvt->service_thread)) { | |
1907 | gvt_err("fail to start service thread.\n"); | |
1908 | return PTR_ERR(gvt->service_thread); | |
1909 | } | |
1910 | return 0; | |
1911 | } | |
1912 | ||
1913 | /** | |
1914 | * intel_gvt_clean_device - clean a GVT device | |
1915 | * @i915: i915 private | |
1916 | * | |
1917 | * This function is called at the driver unloading stage, to free the | |
1918 | * resources owned by a GVT device. | |
1919 | * | |
1920 | */ | |
1921 | static void intel_gvt_clean_device(struct drm_i915_private *i915) | |
1922 | { | |
1923 | struct intel_gvt *gvt = fetch_and_zero(&i915->gvt); | |
1924 | ||
1925 | if (drm_WARN_ON(&i915->drm, !gvt)) | |
1926 | return; | |
1927 | ||
1928 | mdev_unregister_device(i915->drm.dev); | |
1929 | intel_gvt_cleanup_vgpu_type_groups(gvt); | |
1930 | intel_gvt_destroy_idle_vgpu(gvt->idle_vgpu); | |
1931 | intel_gvt_clean_vgpu_types(gvt); | |
1932 | ||
1933 | intel_gvt_debugfs_clean(gvt); | |
1934 | clean_service_thread(gvt); | |
1935 | intel_gvt_clean_cmd_parser(gvt); | |
1936 | intel_gvt_clean_sched_policy(gvt); | |
1937 | intel_gvt_clean_workload_scheduler(gvt); | |
1938 | intel_gvt_clean_gtt(gvt); | |
1939 | intel_gvt_free_firmware(gvt); | |
1940 | intel_gvt_clean_mmio_info(gvt); | |
1941 | idr_destroy(&gvt->vgpu_idr); | |
1942 | ||
1943 | kfree(i915->gvt); | |
1944 | } | |
1945 | ||
1946 | /** | |
1947 | * intel_gvt_init_device - initialize a GVT device | |
1948 | * @i915: drm i915 private data | |
1949 | * | |
1950 | * This function is called at the initialization stage, to initialize | |
1951 | * necessary GVT components. | |
1952 | * | |
1953 | * Returns: | |
1954 | * Zero on success, negative error code if failed. | |
1955 | * | |
1956 | */ | |
1957 | static int intel_gvt_init_device(struct drm_i915_private *i915) | |
1958 | { | |
1959 | struct intel_gvt *gvt; | |
1960 | struct intel_vgpu *vgpu; | |
1961 | int ret; | |
1962 | ||
1963 | if (drm_WARN_ON(&i915->drm, i915->gvt)) | |
1964 | return -EEXIST; | |
1965 | ||
1966 | gvt = kzalloc(sizeof(struct intel_gvt), GFP_KERNEL); | |
1967 | if (!gvt) | |
1968 | return -ENOMEM; | |
1969 | ||
1970 | gvt_dbg_core("init gvt device\n"); | |
1971 | ||
1972 | idr_init_base(&gvt->vgpu_idr, 1); | |
1973 | spin_lock_init(&gvt->scheduler.mmio_context_lock); | |
1974 | mutex_init(&gvt->lock); | |
1975 | mutex_init(&gvt->sched_lock); | |
1976 | gvt->gt = to_gt(i915); | |
1977 | i915->gvt = gvt; | |
1978 | ||
1979 | init_device_info(gvt); | |
1980 | ||
1981 | ret = intel_gvt_setup_mmio_info(gvt); | |
1982 | if (ret) | |
1983 | goto out_clean_idr; | |
1984 | ||
1985 | intel_gvt_init_engine_mmio_context(gvt); | |
1986 | ||
1987 | ret = intel_gvt_load_firmware(gvt); | |
1988 | if (ret) | |
1989 | goto out_clean_mmio_info; | |
1990 | ||
1991 | ret = intel_gvt_init_irq(gvt); | |
1992 | if (ret) | |
1993 | goto out_free_firmware; | |
1994 | ||
1995 | ret = intel_gvt_init_gtt(gvt); | |
1996 | if (ret) | |
1997 | goto out_free_firmware; | |
1998 | ||
1999 | ret = intel_gvt_init_workload_scheduler(gvt); | |
2000 | if (ret) | |
2001 | goto out_clean_gtt; | |
2002 | ||
2003 | ret = intel_gvt_init_sched_policy(gvt); | |
2004 | if (ret) | |
2005 | goto out_clean_workload_scheduler; | |
2006 | ||
2007 | ret = intel_gvt_init_cmd_parser(gvt); | |
2008 | if (ret) | |
2009 | goto out_clean_sched_policy; | |
2010 | ||
2011 | ret = init_service_thread(gvt); | |
2012 | if (ret) | |
2013 | goto out_clean_cmd_parser; | |
2014 | ||
2015 | ret = intel_gvt_init_vgpu_types(gvt); | |
2016 | if (ret) | |
2017 | goto out_clean_thread; | |
2018 | ||
2019 | vgpu = intel_gvt_create_idle_vgpu(gvt); | |
2020 | if (IS_ERR(vgpu)) { | |
2021 | ret = PTR_ERR(vgpu); | |
2022 | gvt_err("failed to create idle vgpu\n"); | |
2023 | goto out_clean_types; | |
2024 | } | |
2025 | gvt->idle_vgpu = vgpu; | |
2026 | ||
2027 | intel_gvt_debugfs_init(gvt); | |
2028 | ||
2029 | ret = intel_gvt_init_vgpu_type_groups(gvt); | |
2030 | if (ret) | |
2031 | goto out_destroy_idle_vgpu; | |
2032 | ||
6b42f491 | 2033 | ret = mdev_register_device(i915->drm.dev, &intel_vgpu_mdev_driver); |
cba619cb CH |
2034 | if (ret) |
2035 | goto out_cleanup_vgpu_type_groups; | |
2036 | ||
2037 | gvt_dbg_core("gvt device initialization is done\n"); | |
2038 | return 0; | |
2039 | ||
2040 | out_cleanup_vgpu_type_groups: | |
2041 | intel_gvt_cleanup_vgpu_type_groups(gvt); | |
2042 | out_destroy_idle_vgpu: | |
2043 | intel_gvt_destroy_idle_vgpu(gvt->idle_vgpu); | |
2044 | intel_gvt_debugfs_clean(gvt); | |
2045 | out_clean_types: | |
2046 | intel_gvt_clean_vgpu_types(gvt); | |
2047 | out_clean_thread: | |
2048 | clean_service_thread(gvt); | |
2049 | out_clean_cmd_parser: | |
2050 | intel_gvt_clean_cmd_parser(gvt); | |
2051 | out_clean_sched_policy: | |
2052 | intel_gvt_clean_sched_policy(gvt); | |
2053 | out_clean_workload_scheduler: | |
2054 | intel_gvt_clean_workload_scheduler(gvt); | |
2055 | out_clean_gtt: | |
2056 | intel_gvt_clean_gtt(gvt); | |
2057 | out_free_firmware: | |
2058 | intel_gvt_free_firmware(gvt); | |
2059 | out_clean_mmio_info: | |
2060 | intel_gvt_clean_mmio_info(gvt); | |
2061 | out_clean_idr: | |
2062 | idr_destroy(&gvt->vgpu_idr); | |
2063 | kfree(gvt); | |
2064 | i915->gvt = NULL; | |
2065 | return ret; | |
2066 | } | |
2067 | ||
2068 | static void intel_gvt_pm_resume(struct drm_i915_private *i915) | |
2069 | { | |
2070 | struct intel_gvt *gvt = i915->gvt; | |
2071 | ||
2072 | intel_gvt_restore_fence(gvt); | |
2073 | intel_gvt_restore_mmio(gvt); | |
2074 | intel_gvt_restore_ggtt(gvt); | |
2075 | } | |
2076 | ||
2077 | static const struct intel_vgpu_ops intel_gvt_vgpu_ops = { | |
2078 | .init_device = intel_gvt_init_device, | |
2079 | .clean_device = intel_gvt_clean_device, | |
2080 | .pm_resume = intel_gvt_pm_resume, | |
2081 | }; | |
2082 | ||
f30437c5 JS |
2083 | static int __init kvmgt_init(void) |
2084 | { | |
978cf586 CH |
2085 | int ret; |
2086 | ||
2087 | ret = intel_gvt_set_ops(&intel_gvt_vgpu_ops); | |
2088 | if (ret) | |
2089 | return ret; | |
2090 | ||
2091 | ret = mdev_register_driver(&intel_vgpu_mdev_driver); | |
2092 | if (ret) | |
2093 | intel_gvt_clear_ops(&intel_gvt_vgpu_ops); | |
2094 | return ret; | |
f30437c5 JS |
2095 | } |
2096 | ||
2097 | static void __exit kvmgt_exit(void) | |
2098 | { | |
978cf586 | 2099 | mdev_unregister_driver(&intel_vgpu_mdev_driver); |
8b750bf7 | 2100 | intel_gvt_clear_ops(&intel_gvt_vgpu_ops); |
f30437c5 JS |
2101 | } |
2102 | ||
2103 | module_init(kvmgt_init); | |
2104 | module_exit(kvmgt_exit); | |
2105 | ||
2106 | MODULE_LICENSE("GPL and additional rights"); | |
2107 | MODULE_AUTHOR("Intel Corporation"); |