Commit | Line | Data |
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f30437c5 JS |
1 | /* |
2 | * KVMGT - the implementation of Intel mediated pass-through framework for KVM | |
3 | * | |
cba619cb | 4 | * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. |
f30437c5 JS |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
23 | * SOFTWARE. | |
24 | * | |
25 | * Authors: | |
26 | * Kevin Tian <kevin.tian@intel.com> | |
27 | * Jike Song <jike.song@intel.com> | |
28 | * Xiaoguang Chen <xiaoguang.chen@intel.com> | |
cba619cb CH |
29 | * Eddie Dong <eddie.dong@intel.com> |
30 | * | |
31 | * Contributors: | |
32 | * Niu Bing <bing.niu@intel.com> | |
33 | * Zhi Wang <zhi.a.wang@intel.com> | |
f30437c5 JS |
34 | */ |
35 | ||
36 | #include <linux/init.h> | |
37 | #include <linux/device.h> | |
38 | #include <linux/mm.h> | |
9bf5b9eb | 39 | #include <linux/kthread.h> |
0a1b60d7 | 40 | #include <linux/sched/mm.h> |
f30437c5 JS |
41 | #include <linux/types.h> |
42 | #include <linux/list.h> | |
43 | #include <linux/rbtree.h> | |
44 | #include <linux/spinlock.h> | |
45 | #include <linux/eventfd.h> | |
46 | #include <linux/uuid.h> | |
659643f7 | 47 | #include <linux/mdev.h> |
6846dfeb | 48 | #include <linux/debugfs.h> |
f30437c5 | 49 | |
de5372da GS |
50 | #include <linux/nospec.h> |
51 | ||
a4c260de JN |
52 | #include <drm/drm_edid.h> |
53 | ||
f30437c5 | 54 | #include "i915_drv.h" |
8b750bf7 | 55 | #include "intel_gvt.h" |
f30437c5 JS |
56 | #include "gvt.h" |
57 | ||
8b750bf7 CH |
58 | MODULE_IMPORT_NS(DMA_BUF); |
59 | MODULE_IMPORT_NS(I915_GVT); | |
60 | ||
f30437c5 JS |
61 | /* helper macros copied from vfio-pci */ |
62 | #define VFIO_PCI_OFFSET_SHIFT 40 | |
63 | #define VFIO_PCI_OFFSET_TO_INDEX(off) (off >> VFIO_PCI_OFFSET_SHIFT) | |
64 | #define VFIO_PCI_INDEX_TO_OFFSET(index) ((u64)(index) << VFIO_PCI_OFFSET_SHIFT) | |
65 | #define VFIO_PCI_OFFSET_MASK (((u64)(1) << VFIO_PCI_OFFSET_SHIFT) - 1) | |
66 | ||
39c68e87 HY |
67 | #define EDID_BLOB_OFFSET (PAGE_SIZE/2) |
68 | ||
b851adea TZ |
69 | #define OPREGION_SIGNATURE "IntelGraphicsMem" |
70 | ||
71 | struct vfio_region; | |
72 | struct intel_vgpu_regops { | |
73 | size_t (*rw)(struct intel_vgpu *vgpu, char *buf, | |
74 | size_t count, loff_t *ppos, bool iswrite); | |
75 | void (*release)(struct intel_vgpu *vgpu, | |
76 | struct vfio_region *region); | |
77 | }; | |
78 | ||
f30437c5 JS |
79 | struct vfio_region { |
80 | u32 type; | |
81 | u32 subtype; | |
82 | size_t size; | |
83 | u32 flags; | |
b851adea TZ |
84 | const struct intel_vgpu_regops *ops; |
85 | void *data; | |
f30437c5 JS |
86 | }; |
87 | ||
39c68e87 HY |
88 | struct vfio_edid_region { |
89 | struct vfio_region_gfx_edid vfio_edid_regs; | |
90 | void *edid_blob; | |
91 | }; | |
92 | ||
f30437c5 JS |
93 | struct kvmgt_pgfn { |
94 | gfn_t gfn; | |
95 | struct hlist_node hnode; | |
96 | }; | |
97 | ||
f30437c5 | 98 | struct gvt_dma { |
cf4ee73f CD |
99 | struct intel_vgpu *vgpu; |
100 | struct rb_node gfn_node; | |
101 | struct rb_node dma_addr_node; | |
f30437c5 | 102 | gfn_t gfn; |
cf4ee73f | 103 | dma_addr_t dma_addr; |
79e542f5 | 104 | unsigned long size; |
cf4ee73f | 105 | struct kref ref; |
f30437c5 JS |
106 | }; |
107 | ||
978cf586 CH |
108 | #define vfio_dev_to_vgpu(vfio_dev) \ |
109 | container_of((vfio_dev), struct intel_vgpu, vfio_device) | |
110 | ||
0e09f406 CH |
111 | static void kvmgt_page_track_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
112 | const u8 *val, int len, | |
113 | struct kvm_page_track_notifier_node *node); | |
114 | static void kvmgt_page_track_flush_slot(struct kvm *kvm, | |
115 | struct kvm_memory_slot *slot, | |
116 | struct kvm_page_track_notifier_node *node); | |
117 | ||
145e06b5 ZW |
118 | static ssize_t available_instances_show(struct mdev_type *mtype, |
119 | struct mdev_type_attribute *attr, | |
120 | char *buf) | |
121 | { | |
122 | struct intel_vgpu_type *type; | |
123 | unsigned int num = 0; | |
124 | struct intel_gvt *gvt = kdev_to_i915(mtype_get_parent_dev(mtype))->gvt; | |
125 | ||
126 | type = &gvt->types[mtype_get_type_group_id(mtype)]; | |
127 | if (!type) | |
128 | num = 0; | |
129 | else | |
130 | num = type->avail_instance; | |
131 | ||
132 | return sprintf(buf, "%u\n", num); | |
133 | } | |
134 | ||
135 | static ssize_t device_api_show(struct mdev_type *mtype, | |
136 | struct mdev_type_attribute *attr, char *buf) | |
137 | { | |
138 | return sprintf(buf, "%s\n", VFIO_DEVICE_API_PCI_STRING); | |
139 | } | |
140 | ||
141 | static ssize_t description_show(struct mdev_type *mtype, | |
142 | struct mdev_type_attribute *attr, char *buf) | |
143 | { | |
144 | struct intel_vgpu_type *type; | |
145 | struct intel_gvt *gvt = kdev_to_i915(mtype_get_parent_dev(mtype))->gvt; | |
146 | ||
147 | type = &gvt->types[mtype_get_type_group_id(mtype)]; | |
148 | if (!type) | |
149 | return 0; | |
150 | ||
151 | return sprintf(buf, "low_gm_size: %dMB\nhigh_gm_size: %dMB\n" | |
152 | "fence: %d\nresolution: %s\n" | |
153 | "weight: %d\n", | |
154 | BYTES_TO_MB(type->low_gm_size), | |
155 | BYTES_TO_MB(type->high_gm_size), | |
156 | type->fence, vgpu_edid_str(type->resolution), | |
157 | type->weight); | |
158 | } | |
159 | ||
43d26c4f ZW |
160 | static ssize_t name_show(struct mdev_type *mtype, |
161 | struct mdev_type_attribute *attr, char *buf) | |
162 | { | |
163 | struct intel_vgpu_type *type; | |
164 | struct intel_gvt *gvt = kdev_to_i915(mtype_get_parent_dev(mtype))->gvt; | |
165 | ||
166 | type = &gvt->types[mtype_get_type_group_id(mtype)]; | |
167 | if (!type) | |
168 | return 0; | |
169 | ||
170 | return sprintf(buf, "%s\n", type->name); | |
171 | } | |
172 | ||
145e06b5 ZW |
173 | static MDEV_TYPE_ATTR_RO(available_instances); |
174 | static MDEV_TYPE_ATTR_RO(device_api); | |
175 | static MDEV_TYPE_ATTR_RO(description); | |
43d26c4f | 176 | static MDEV_TYPE_ATTR_RO(name); |
145e06b5 ZW |
177 | |
178 | static struct attribute *gvt_type_attrs[] = { | |
179 | &mdev_type_attr_available_instances.attr, | |
180 | &mdev_type_attr_device_api.attr, | |
181 | &mdev_type_attr_description.attr, | |
43d26c4f | 182 | &mdev_type_attr_name.attr, |
145e06b5 ZW |
183 | NULL, |
184 | }; | |
185 | ||
186 | static struct attribute_group *gvt_vgpu_type_groups[] = { | |
187 | [0 ... NR_MAX_INTEL_VGPU_TYPES - 1] = NULL, | |
188 | }; | |
189 | ||
cba619cb | 190 | static int intel_gvt_init_vgpu_type_groups(struct intel_gvt *gvt) |
145e06b5 ZW |
191 | { |
192 | int i, j; | |
193 | struct intel_vgpu_type *type; | |
194 | struct attribute_group *group; | |
195 | ||
196 | for (i = 0; i < gvt->num_types; i++) { | |
197 | type = &gvt->types[i]; | |
198 | ||
199 | group = kzalloc(sizeof(struct attribute_group), GFP_KERNEL); | |
200 | if (!group) | |
201 | goto unwind; | |
202 | ||
203 | group->name = type->name; | |
204 | group->attrs = gvt_type_attrs; | |
205 | gvt_vgpu_type_groups[i] = group; | |
206 | } | |
207 | ||
208 | return 0; | |
209 | ||
210 | unwind: | |
211 | for (j = 0; j < i; j++) { | |
212 | group = gvt_vgpu_type_groups[j]; | |
213 | kfree(group); | |
214 | } | |
215 | ||
216 | return -ENOMEM; | |
217 | } | |
218 | ||
cba619cb | 219 | static void intel_gvt_cleanup_vgpu_type_groups(struct intel_gvt *gvt) |
145e06b5 ZW |
220 | { |
221 | int i; | |
222 | struct attribute_group *group; | |
223 | ||
224 | for (i = 0; i < gvt->num_types; i++) { | |
225 | group = gvt_vgpu_type_groups[i]; | |
226 | gvt_vgpu_type_groups[i] = NULL; | |
227 | kfree(group); | |
228 | } | |
229 | } | |
230 | ||
659643f7 | 231 | static void intel_vgpu_release_work(struct work_struct *work); |
659643f7 | 232 | |
79e542f5 CD |
233 | static void gvt_unpin_guest_page(struct intel_vgpu *vgpu, unsigned long gfn, |
234 | unsigned long size) | |
235 | { | |
a61ac1e7 | 236 | struct drm_i915_private *i915 = vgpu->gvt->gt->i915; |
79e542f5 CD |
237 | int total_pages; |
238 | int npage; | |
239 | int ret; | |
240 | ||
241 | total_pages = roundup(size, PAGE_SIZE) / PAGE_SIZE; | |
242 | ||
243 | for (npage = 0; npage < total_pages; npage++) { | |
244 | unsigned long cur_gfn = gfn + npage; | |
245 | ||
62980cac | 246 | ret = vfio_group_unpin_pages(vgpu->vfio_group, &cur_gfn, 1); |
12d58619 | 247 | drm_WARN_ON(&i915->drm, ret != 1); |
79e542f5 CD |
248 | } |
249 | } | |
250 | ||
251 | /* Pin a normal or compound guest page for dma. */ | |
252 | static int gvt_pin_guest_page(struct intel_vgpu *vgpu, unsigned long gfn, | |
253 | unsigned long size, struct page **page) | |
254 | { | |
255 | unsigned long base_pfn = 0; | |
256 | int total_pages; | |
257 | int npage; | |
258 | int ret; | |
259 | ||
260 | total_pages = roundup(size, PAGE_SIZE) / PAGE_SIZE; | |
261 | /* | |
262 | * We pin the pages one-by-one to avoid allocating a big arrary | |
263 | * on stack to hold pfns. | |
264 | */ | |
265 | for (npage = 0; npage < total_pages; npage++) { | |
266 | unsigned long cur_gfn = gfn + npage; | |
267 | unsigned long pfn; | |
268 | ||
62980cac | 269 | ret = vfio_group_pin_pages(vgpu->vfio_group, &cur_gfn, 1, |
ec7301d5 | 270 | IOMMU_READ | IOMMU_WRITE, &pfn); |
79e542f5 CD |
271 | if (ret != 1) { |
272 | gvt_vgpu_err("vfio_pin_pages failed for gfn 0x%lx, ret %d\n", | |
273 | cur_gfn, ret); | |
274 | goto err; | |
275 | } | |
276 | ||
277 | if (!pfn_valid(pfn)) { | |
278 | gvt_vgpu_err("pfn 0x%lx is not mem backed\n", pfn); | |
279 | npage++; | |
280 | ret = -EFAULT; | |
281 | goto err; | |
282 | } | |
283 | ||
284 | if (npage == 0) | |
285 | base_pfn = pfn; | |
286 | else if (base_pfn + npage != pfn) { | |
287 | gvt_vgpu_err("The pages are not continuous\n"); | |
288 | ret = -EINVAL; | |
289 | npage++; | |
290 | goto err; | |
291 | } | |
292 | } | |
293 | ||
294 | *page = pfn_to_page(base_pfn); | |
295 | return 0; | |
296 | err: | |
297 | gvt_unpin_guest_page(vgpu, gfn, npage * PAGE_SIZE); | |
298 | return ret; | |
299 | } | |
300 | ||
cf4ee73f | 301 | static int gvt_dma_map_page(struct intel_vgpu *vgpu, unsigned long gfn, |
79e542f5 | 302 | dma_addr_t *dma_addr, unsigned long size) |
b86dc6ed | 303 | { |
9ff06c38 | 304 | struct device *dev = vgpu->gvt->gt->i915->drm.dev; |
79e542f5 | 305 | struct page *page = NULL; |
cf4ee73f | 306 | int ret; |
b86dc6ed | 307 | |
79e542f5 CD |
308 | ret = gvt_pin_guest_page(vgpu, gfn, size, &page); |
309 | if (ret) | |
310 | return ret; | |
b86dc6ed | 311 | |
cf4ee73f | 312 | /* Setup DMA mapping. */ |
c4f61203 | 313 | *dma_addr = dma_map_page(dev, page, 0, size, DMA_BIDIRECTIONAL); |
13bdff33 | 314 | if (dma_mapping_error(dev, *dma_addr)) { |
79e542f5 CD |
315 | gvt_vgpu_err("DMA mapping failed for pfn 0x%lx, ret %d\n", |
316 | page_to_pfn(page), ret); | |
317 | gvt_unpin_guest_page(vgpu, gfn, size); | |
13bdff33 | 318 | return -ENOMEM; |
cf4ee73f | 319 | } |
b86dc6ed | 320 | |
13bdff33 | 321 | return 0; |
b86dc6ed CD |
322 | } |
323 | ||
cf4ee73f | 324 | static void gvt_dma_unmap_page(struct intel_vgpu *vgpu, unsigned long gfn, |
79e542f5 | 325 | dma_addr_t dma_addr, unsigned long size) |
b86dc6ed | 326 | { |
9ff06c38 | 327 | struct device *dev = vgpu->gvt->gt->i915->drm.dev; |
b86dc6ed | 328 | |
c4f61203 | 329 | dma_unmap_page(dev, dma_addr, size, DMA_BIDIRECTIONAL); |
79e542f5 | 330 | gvt_unpin_guest_page(vgpu, gfn, size); |
b86dc6ed CD |
331 | } |
332 | ||
cf4ee73f CD |
333 | static struct gvt_dma *__gvt_cache_find_dma_addr(struct intel_vgpu *vgpu, |
334 | dma_addr_t dma_addr) | |
f30437c5 | 335 | { |
62980cac | 336 | struct rb_node *node = vgpu->dma_addr_cache.rb_node; |
cf4ee73f | 337 | struct gvt_dma *itr; |
f30437c5 JS |
338 | |
339 | while (node) { | |
cf4ee73f | 340 | itr = rb_entry(node, struct gvt_dma, dma_addr_node); |
f30437c5 | 341 | |
cf4ee73f | 342 | if (dma_addr < itr->dma_addr) |
f30437c5 | 343 | node = node->rb_left; |
cf4ee73f | 344 | else if (dma_addr > itr->dma_addr) |
f30437c5 | 345 | node = node->rb_right; |
cf4ee73f CD |
346 | else |
347 | return itr; | |
f30437c5 | 348 | } |
cf4ee73f | 349 | return NULL; |
f30437c5 JS |
350 | } |
351 | ||
cf4ee73f | 352 | static struct gvt_dma *__gvt_cache_find_gfn(struct intel_vgpu *vgpu, gfn_t gfn) |
f30437c5 | 353 | { |
62980cac | 354 | struct rb_node *node = vgpu->gfn_cache.rb_node; |
cf4ee73f | 355 | struct gvt_dma *itr; |
f30437c5 | 356 | |
cf4ee73f CD |
357 | while (node) { |
358 | itr = rb_entry(node, struct gvt_dma, gfn_node); | |
f30437c5 | 359 | |
cf4ee73f CD |
360 | if (gfn < itr->gfn) |
361 | node = node->rb_left; | |
362 | else if (gfn > itr->gfn) | |
363 | node = node->rb_right; | |
364 | else | |
365 | return itr; | |
366 | } | |
367 | return NULL; | |
f30437c5 JS |
368 | } |
369 | ||
5cd4223e | 370 | static int __gvt_cache_add(struct intel_vgpu *vgpu, gfn_t gfn, |
79e542f5 | 371 | dma_addr_t dma_addr, unsigned long size) |
f30437c5 JS |
372 | { |
373 | struct gvt_dma *new, *itr; | |
cf4ee73f | 374 | struct rb_node **link, *parent = NULL; |
f30437c5 JS |
375 | |
376 | new = kzalloc(sizeof(struct gvt_dma), GFP_KERNEL); | |
377 | if (!new) | |
5cd4223e | 378 | return -ENOMEM; |
f30437c5 | 379 | |
cf4ee73f | 380 | new->vgpu = vgpu; |
f30437c5 | 381 | new->gfn = gfn; |
cf4ee73f | 382 | new->dma_addr = dma_addr; |
79e542f5 | 383 | new->size = size; |
cf4ee73f | 384 | kref_init(&new->ref); |
f30437c5 | 385 | |
cf4ee73f | 386 | /* gfn_cache maps gfn to struct gvt_dma. */ |
62980cac | 387 | link = &vgpu->gfn_cache.rb_node; |
f30437c5 JS |
388 | while (*link) { |
389 | parent = *link; | |
cf4ee73f | 390 | itr = rb_entry(parent, struct gvt_dma, gfn_node); |
f30437c5 | 391 | |
cf4ee73f | 392 | if (gfn < itr->gfn) |
f30437c5 JS |
393 | link = &parent->rb_left; |
394 | else | |
395 | link = &parent->rb_right; | |
396 | } | |
cf4ee73f | 397 | rb_link_node(&new->gfn_node, parent, link); |
62980cac | 398 | rb_insert_color(&new->gfn_node, &vgpu->gfn_cache); |
f30437c5 | 399 | |
cf4ee73f CD |
400 | /* dma_addr_cache maps dma addr to struct gvt_dma. */ |
401 | parent = NULL; | |
62980cac | 402 | link = &vgpu->dma_addr_cache.rb_node; |
cf4ee73f CD |
403 | while (*link) { |
404 | parent = *link; | |
405 | itr = rb_entry(parent, struct gvt_dma, dma_addr_node); | |
f30437c5 | 406 | |
cf4ee73f CD |
407 | if (dma_addr < itr->dma_addr) |
408 | link = &parent->rb_left; | |
409 | else | |
410 | link = &parent->rb_right; | |
411 | } | |
412 | rb_link_node(&new->dma_addr_node, parent, link); | |
62980cac | 413 | rb_insert_color(&new->dma_addr_node, &vgpu->dma_addr_cache); |
6846dfeb | 414 | |
62980cac | 415 | vgpu->nr_cache_entries++; |
5cd4223e | 416 | return 0; |
f30437c5 JS |
417 | } |
418 | ||
419 | static void __gvt_cache_remove_entry(struct intel_vgpu *vgpu, | |
420 | struct gvt_dma *entry) | |
421 | { | |
62980cac CH |
422 | rb_erase(&entry->gfn_node, &vgpu->gfn_cache); |
423 | rb_erase(&entry->dma_addr_node, &vgpu->dma_addr_cache); | |
f30437c5 | 424 | kfree(entry); |
62980cac | 425 | vgpu->nr_cache_entries--; |
f30437c5 JS |
426 | } |
427 | ||
f30437c5 JS |
428 | static void gvt_cache_destroy(struct intel_vgpu *vgpu) |
429 | { | |
430 | struct gvt_dma *dma; | |
431 | struct rb_node *node = NULL; | |
f30437c5 | 432 | |
f16bd3dd | 433 | for (;;) { |
62980cac CH |
434 | mutex_lock(&vgpu->cache_lock); |
435 | node = rb_first(&vgpu->gfn_cache); | |
f16bd3dd | 436 | if (!node) { |
62980cac | 437 | mutex_unlock(&vgpu->cache_lock); |
f16bd3dd CD |
438 | break; |
439 | } | |
cf4ee73f | 440 | dma = rb_entry(node, struct gvt_dma, gfn_node); |
79e542f5 | 441 | gvt_dma_unmap_page(vgpu, dma->gfn, dma->dma_addr, dma->size); |
f30437c5 | 442 | __gvt_cache_remove_entry(vgpu, dma); |
62980cac | 443 | mutex_unlock(&vgpu->cache_lock); |
f30437c5 | 444 | } |
f30437c5 JS |
445 | } |
446 | ||
cf4ee73f CD |
447 | static void gvt_cache_init(struct intel_vgpu *vgpu) |
448 | { | |
62980cac CH |
449 | vgpu->gfn_cache = RB_ROOT; |
450 | vgpu->dma_addr_cache = RB_ROOT; | |
451 | vgpu->nr_cache_entries = 0; | |
452 | mutex_init(&vgpu->cache_lock); | |
cf4ee73f CD |
453 | } |
454 | ||
10ddb962 | 455 | static void kvmgt_protect_table_init(struct intel_vgpu *info) |
f30437c5 JS |
456 | { |
457 | hash_init(info->ptable); | |
458 | } | |
459 | ||
10ddb962 | 460 | static void kvmgt_protect_table_destroy(struct intel_vgpu *info) |
f30437c5 JS |
461 | { |
462 | struct kvmgt_pgfn *p; | |
463 | struct hlist_node *tmp; | |
464 | int i; | |
465 | ||
466 | hash_for_each_safe(info->ptable, i, tmp, p, hnode) { | |
467 | hash_del(&p->hnode); | |
468 | kfree(p); | |
469 | } | |
470 | } | |
471 | ||
472 | static struct kvmgt_pgfn * | |
10ddb962 | 473 | __kvmgt_protect_table_find(struct intel_vgpu *info, gfn_t gfn) |
f30437c5 JS |
474 | { |
475 | struct kvmgt_pgfn *p, *res = NULL; | |
476 | ||
477 | hash_for_each_possible(info->ptable, p, hnode, gfn) { | |
478 | if (gfn == p->gfn) { | |
479 | res = p; | |
480 | break; | |
481 | } | |
482 | } | |
483 | ||
484 | return res; | |
485 | } | |
486 | ||
10ddb962 | 487 | static bool kvmgt_gfn_is_write_protected(struct intel_vgpu *info, gfn_t gfn) |
f30437c5 JS |
488 | { |
489 | struct kvmgt_pgfn *p; | |
490 | ||
491 | p = __kvmgt_protect_table_find(info, gfn); | |
492 | return !!p; | |
493 | } | |
494 | ||
10ddb962 | 495 | static void kvmgt_protect_table_add(struct intel_vgpu *info, gfn_t gfn) |
f30437c5 JS |
496 | { |
497 | struct kvmgt_pgfn *p; | |
498 | ||
499 | if (kvmgt_gfn_is_write_protected(info, gfn)) | |
500 | return; | |
501 | ||
c55b1de0 | 502 | p = kzalloc(sizeof(struct kvmgt_pgfn), GFP_ATOMIC); |
f30437c5 JS |
503 | if (WARN(!p, "gfn: 0x%llx\n", gfn)) |
504 | return; | |
505 | ||
506 | p->gfn = gfn; | |
507 | hash_add(info->ptable, &p->hnode, gfn); | |
508 | } | |
509 | ||
10ddb962 | 510 | static void kvmgt_protect_table_del(struct intel_vgpu *info, gfn_t gfn) |
f30437c5 JS |
511 | { |
512 | struct kvmgt_pgfn *p; | |
513 | ||
514 | p = __kvmgt_protect_table_find(info, gfn); | |
515 | if (p) { | |
516 | hash_del(&p->hnode); | |
517 | kfree(p); | |
518 | } | |
519 | } | |
520 | ||
b851adea TZ |
521 | static size_t intel_vgpu_reg_rw_opregion(struct intel_vgpu *vgpu, char *buf, |
522 | size_t count, loff_t *ppos, bool iswrite) | |
523 | { | |
524 | unsigned int i = VFIO_PCI_OFFSET_TO_INDEX(*ppos) - | |
525 | VFIO_PCI_NUM_REGIONS; | |
62980cac | 526 | void *base = vgpu->region[i].data; |
b851adea TZ |
527 | loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK; |
528 | ||
06d63c48 | 529 | |
62980cac | 530 | if (pos >= vgpu->region[i].size || iswrite) { |
b851adea TZ |
531 | gvt_vgpu_err("invalid op or offset for Intel vgpu OpRegion\n"); |
532 | return -EINVAL; | |
533 | } | |
62980cac | 534 | count = min(count, (size_t)(vgpu->region[i].size - pos)); |
b851adea TZ |
535 | memcpy(buf, base + pos, count); |
536 | ||
537 | return count; | |
538 | } | |
539 | ||
540 | static void intel_vgpu_reg_release_opregion(struct intel_vgpu *vgpu, | |
541 | struct vfio_region *region) | |
542 | { | |
543 | } | |
544 | ||
545 | static const struct intel_vgpu_regops intel_vgpu_regops_opregion = { | |
546 | .rw = intel_vgpu_reg_rw_opregion, | |
547 | .release = intel_vgpu_reg_release_opregion, | |
548 | }; | |
549 | ||
39c68e87 HY |
550 | static int handle_edid_regs(struct intel_vgpu *vgpu, |
551 | struct vfio_edid_region *region, char *buf, | |
552 | size_t count, u16 offset, bool is_write) | |
553 | { | |
554 | struct vfio_region_gfx_edid *regs = ®ion->vfio_edid_regs; | |
555 | unsigned int data; | |
556 | ||
557 | if (offset + count > sizeof(*regs)) | |
558 | return -EINVAL; | |
559 | ||
560 | if (count != 4) | |
561 | return -EINVAL; | |
562 | ||
563 | if (is_write) { | |
564 | data = *((unsigned int *)buf); | |
565 | switch (offset) { | |
566 | case offsetof(struct vfio_region_gfx_edid, link_state): | |
567 | if (data == VFIO_DEVICE_GFX_LINK_STATE_UP) { | |
568 | if (!drm_edid_block_valid( | |
569 | (u8 *)region->edid_blob, | |
570 | 0, | |
571 | true, | |
572 | NULL)) { | |
573 | gvt_vgpu_err("invalid EDID blob\n"); | |
574 | return -EINVAL; | |
575 | } | |
675e5c4a | 576 | intel_vgpu_emulate_hotplug(vgpu, true); |
39c68e87 | 577 | } else if (data == VFIO_DEVICE_GFX_LINK_STATE_DOWN) |
675e5c4a | 578 | intel_vgpu_emulate_hotplug(vgpu, false); |
39c68e87 HY |
579 | else { |
580 | gvt_vgpu_err("invalid EDID link state %d\n", | |
581 | regs->link_state); | |
582 | return -EINVAL; | |
583 | } | |
584 | regs->link_state = data; | |
585 | break; | |
586 | case offsetof(struct vfio_region_gfx_edid, edid_size): | |
587 | if (data > regs->edid_max_size) { | |
588 | gvt_vgpu_err("EDID size is bigger than %d!\n", | |
589 | regs->edid_max_size); | |
590 | return -EINVAL; | |
591 | } | |
592 | regs->edid_size = data; | |
593 | break; | |
594 | default: | |
595 | /* read-only regs */ | |
596 | gvt_vgpu_err("write read-only EDID region at offset %d\n", | |
597 | offset); | |
598 | return -EPERM; | |
599 | } | |
600 | } else { | |
601 | memcpy(buf, (char *)regs + offset, count); | |
602 | } | |
603 | ||
604 | return count; | |
605 | } | |
606 | ||
607 | static int handle_edid_blob(struct vfio_edid_region *region, char *buf, | |
608 | size_t count, u16 offset, bool is_write) | |
609 | { | |
610 | if (offset + count > region->vfio_edid_regs.edid_size) | |
611 | return -EINVAL; | |
612 | ||
613 | if (is_write) | |
614 | memcpy(region->edid_blob + offset, buf, count); | |
615 | else | |
616 | memcpy(buf, region->edid_blob + offset, count); | |
617 | ||
618 | return count; | |
619 | } | |
620 | ||
621 | static size_t intel_vgpu_reg_rw_edid(struct intel_vgpu *vgpu, char *buf, | |
622 | size_t count, loff_t *ppos, bool iswrite) | |
623 | { | |
624 | int ret; | |
625 | unsigned int i = VFIO_PCI_OFFSET_TO_INDEX(*ppos) - | |
626 | VFIO_PCI_NUM_REGIONS; | |
62980cac | 627 | struct vfio_edid_region *region = vgpu->region[i].data; |
39c68e87 HY |
628 | loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK; |
629 | ||
630 | if (pos < region->vfio_edid_regs.edid_offset) { | |
631 | ret = handle_edid_regs(vgpu, region, buf, count, pos, iswrite); | |
632 | } else { | |
633 | pos -= EDID_BLOB_OFFSET; | |
634 | ret = handle_edid_blob(region, buf, count, pos, iswrite); | |
635 | } | |
636 | ||
637 | if (ret < 0) | |
638 | gvt_vgpu_err("failed to access EDID region\n"); | |
639 | ||
640 | return ret; | |
641 | } | |
642 | ||
643 | static void intel_vgpu_reg_release_edid(struct intel_vgpu *vgpu, | |
644 | struct vfio_region *region) | |
645 | { | |
646 | kfree(region->data); | |
647 | } | |
648 | ||
649 | static const struct intel_vgpu_regops intel_vgpu_regops_edid = { | |
650 | .rw = intel_vgpu_reg_rw_edid, | |
651 | .release = intel_vgpu_reg_release_edid, | |
652 | }; | |
653 | ||
b851adea TZ |
654 | static int intel_vgpu_register_reg(struct intel_vgpu *vgpu, |
655 | unsigned int type, unsigned int subtype, | |
656 | const struct intel_vgpu_regops *ops, | |
657 | size_t size, u32 flags, void *data) | |
658 | { | |
659 | struct vfio_region *region; | |
660 | ||
62980cac CH |
661 | region = krealloc(vgpu->region, |
662 | (vgpu->num_regions + 1) * sizeof(*region), | |
b851adea TZ |
663 | GFP_KERNEL); |
664 | if (!region) | |
665 | return -ENOMEM; | |
666 | ||
62980cac CH |
667 | vgpu->region = region; |
668 | vgpu->region[vgpu->num_regions].type = type; | |
669 | vgpu->region[vgpu->num_regions].subtype = subtype; | |
670 | vgpu->region[vgpu->num_regions].ops = ops; | |
671 | vgpu->region[vgpu->num_regions].size = size; | |
672 | vgpu->region[vgpu->num_regions].flags = flags; | |
673 | vgpu->region[vgpu->num_regions].data = data; | |
674 | vgpu->num_regions++; | |
e546e281 TZ |
675 | return 0; |
676 | } | |
677 | ||
f9399b0e | 678 | int intel_gvt_set_opregion(struct intel_vgpu *vgpu) |
b851adea | 679 | { |
b851adea TZ |
680 | void *base; |
681 | int ret; | |
682 | ||
683 | /* Each vgpu has its own opregion, although VFIO would create another | |
684 | * one later. This one is used to expose opregion to VFIO. And the | |
685 | * other one created by VFIO later, is used by guest actually. | |
686 | */ | |
687 | base = vgpu_opregion(vgpu)->va; | |
688 | if (!base) | |
689 | return -ENOMEM; | |
690 | ||
691 | if (memcmp(base, OPREGION_SIGNATURE, 16)) { | |
692 | memunmap(base); | |
693 | return -EINVAL; | |
694 | } | |
695 | ||
696 | ret = intel_vgpu_register_reg(vgpu, | |
697 | PCI_VENDOR_ID_INTEL | VFIO_REGION_TYPE_PCI_VENDOR_TYPE, | |
698 | VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION, | |
699 | &intel_vgpu_regops_opregion, OPREGION_SIZE, | |
700 | VFIO_REGION_INFO_FLAG_READ, base); | |
701 | ||
702 | return ret; | |
703 | } | |
704 | ||
f9399b0e | 705 | int intel_gvt_set_edid(struct intel_vgpu *vgpu, int port_num) |
39c68e87 | 706 | { |
39c68e87 HY |
707 | struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); |
708 | struct vfio_edid_region *base; | |
709 | int ret; | |
710 | ||
711 | base = kzalloc(sizeof(*base), GFP_KERNEL); | |
712 | if (!base) | |
713 | return -ENOMEM; | |
714 | ||
715 | /* TODO: Add multi-port and EDID extension block support */ | |
716 | base->vfio_edid_regs.edid_offset = EDID_BLOB_OFFSET; | |
717 | base->vfio_edid_regs.edid_max_size = EDID_SIZE; | |
718 | base->vfio_edid_regs.edid_size = EDID_SIZE; | |
719 | base->vfio_edid_regs.max_xres = vgpu_edid_xres(port->id); | |
720 | base->vfio_edid_regs.max_yres = vgpu_edid_yres(port->id); | |
721 | base->edid_blob = port->edid->edid_block; | |
722 | ||
723 | ret = intel_vgpu_register_reg(vgpu, | |
724 | VFIO_REGION_TYPE_GFX, | |
725 | VFIO_REGION_SUBTYPE_GFX_EDID, | |
726 | &intel_vgpu_regops_edid, EDID_SIZE, | |
727 | VFIO_REGION_INFO_FLAG_READ | | |
728 | VFIO_REGION_INFO_FLAG_WRITE | | |
729 | VFIO_REGION_INFO_FLAG_CAPS, base); | |
730 | ||
731 | return ret; | |
732 | } | |
733 | ||
659643f7 JS |
734 | static int intel_vgpu_iommu_notifier(struct notifier_block *nb, |
735 | unsigned long action, void *data) | |
736 | { | |
62980cac CH |
737 | struct intel_vgpu *vgpu = |
738 | container_of(nb, struct intel_vgpu, iommu_notifier); | |
659643f7 JS |
739 | |
740 | if (action == VFIO_IOMMU_NOTIFY_DMA_UNMAP) { | |
741 | struct vfio_iommu_type1_dma_unmap *unmap = data; | |
cf4ee73f CD |
742 | struct gvt_dma *entry; |
743 | unsigned long iov_pfn, end_iov_pfn; | |
744 | ||
745 | iov_pfn = unmap->iova >> PAGE_SHIFT; | |
746 | end_iov_pfn = iov_pfn + unmap->size / PAGE_SIZE; | |
659643f7 | 747 | |
62980cac | 748 | mutex_lock(&vgpu->cache_lock); |
cf4ee73f CD |
749 | for (; iov_pfn < end_iov_pfn; iov_pfn++) { |
750 | entry = __gvt_cache_find_gfn(vgpu, iov_pfn); | |
751 | if (!entry) | |
752 | continue; | |
659643f7 | 753 | |
79e542f5 CD |
754 | gvt_dma_unmap_page(vgpu, entry->gfn, entry->dma_addr, |
755 | entry->size); | |
cf4ee73f CD |
756 | __gvt_cache_remove_entry(vgpu, entry); |
757 | } | |
62980cac | 758 | mutex_unlock(&vgpu->cache_lock); |
659643f7 JS |
759 | } |
760 | ||
761 | return NOTIFY_OK; | |
762 | } | |
763 | ||
764 | static int intel_vgpu_group_notifier(struct notifier_block *nb, | |
765 | unsigned long action, void *data) | |
766 | { | |
62980cac CH |
767 | struct intel_vgpu *vgpu = |
768 | container_of(nb, struct intel_vgpu, group_notifier); | |
659643f7 JS |
769 | |
770 | /* the only action we care about */ | |
771 | if (action == VFIO_GROUP_NOTIFY_SET_KVM) { | |
62980cac | 772 | vgpu->kvm = data; |
659643f7 JS |
773 | |
774 | if (!data) | |
62980cac | 775 | schedule_work(&vgpu->release_work); |
659643f7 JS |
776 | } |
777 | ||
778 | return NOTIFY_OK; | |
779 | } | |
780 | ||
0e09f406 CH |
781 | static bool __kvmgt_vgpu_exist(struct intel_vgpu *vgpu) |
782 | { | |
783 | struct intel_vgpu *itr; | |
784 | int id; | |
785 | bool ret = false; | |
786 | ||
787 | mutex_lock(&vgpu->gvt->lock); | |
788 | for_each_active_vgpu(vgpu->gvt, itr, id) { | |
789 | if (!itr->attached) | |
790 | continue; | |
791 | ||
792 | if (vgpu->kvm == itr->kvm) { | |
793 | ret = true; | |
794 | goto out; | |
795 | } | |
796 | } | |
797 | out: | |
798 | mutex_unlock(&vgpu->gvt->lock); | |
799 | return ret; | |
800 | } | |
801 | ||
978cf586 | 802 | static int intel_vgpu_open_device(struct vfio_device *vfio_dev) |
659643f7 | 803 | { |
978cf586 | 804 | struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); |
659643f7 JS |
805 | unsigned long events; |
806 | int ret; | |
776d95b7 | 807 | struct vfio_group *vfio_group; |
659643f7 | 808 | |
62980cac CH |
809 | vgpu->iommu_notifier.notifier_call = intel_vgpu_iommu_notifier; |
810 | vgpu->group_notifier.notifier_call = intel_vgpu_group_notifier; | |
659643f7 JS |
811 | |
812 | events = VFIO_IOMMU_NOTIFY_DMA_UNMAP; | |
978cf586 | 813 | ret = vfio_register_notifier(vfio_dev->dev, VFIO_IOMMU_NOTIFY, &events, |
62980cac | 814 | &vgpu->iommu_notifier); |
659643f7 | 815 | if (ret != 0) { |
695fbc08 TZ |
816 | gvt_vgpu_err("vfio_register_notifier for iommu failed: %d\n", |
817 | ret); | |
659643f7 JS |
818 | goto out; |
819 | } | |
820 | ||
821 | events = VFIO_GROUP_NOTIFY_SET_KVM; | |
978cf586 | 822 | ret = vfio_register_notifier(vfio_dev->dev, VFIO_GROUP_NOTIFY, &events, |
62980cac | 823 | &vgpu->group_notifier); |
659643f7 | 824 | if (ret != 0) { |
695fbc08 TZ |
825 | gvt_vgpu_err("vfio_register_notifier for group failed: %d\n", |
826 | ret); | |
659643f7 JS |
827 | goto undo_iommu; |
828 | } | |
829 | ||
978cf586 CH |
830 | vfio_group = |
831 | vfio_group_get_external_user_from_dev(vgpu->vfio_device.dev); | |
776d95b7 YZ |
832 | if (IS_ERR_OR_NULL(vfio_group)) { |
833 | ret = !vfio_group ? -EFAULT : PTR_ERR(vfio_group); | |
834 | gvt_vgpu_err("vfio_group_get_external_user_from_dev failed\n"); | |
835 | goto undo_register; | |
836 | } | |
62980cac | 837 | vgpu->vfio_group = vfio_group; |
776d95b7 | 838 | |
0e09f406 CH |
839 | ret = -EEXIST; |
840 | if (vgpu->attached) | |
841 | goto undo_group; | |
842 | ||
843 | ret = -ESRCH; | |
844 | if (!vgpu->kvm || vgpu->kvm->mm != current->mm) { | |
845 | gvt_vgpu_err("KVM is required to use Intel vGPU\n"); | |
846 | goto undo_group; | |
847 | } | |
848 | ||
849 | ret = -EEXIST; | |
850 | if (__kvmgt_vgpu_exist(vgpu)) | |
364fb6b7 JS |
851 | goto undo_group; |
852 | ||
0e09f406 CH |
853 | vgpu->attached = true; |
854 | kvm_get_kvm(vgpu->kvm); | |
855 | ||
856 | kvmgt_protect_table_init(vgpu); | |
857 | gvt_cache_init(vgpu); | |
858 | ||
859 | vgpu->track_node.track_write = kvmgt_page_track_write; | |
860 | vgpu->track_node.track_flush_slot = kvmgt_page_track_flush_slot; | |
861 | kvm_page_track_register_notifier(vgpu->kvm, &vgpu->track_node); | |
862 | ||
863 | debugfs_create_ulong(KVMGT_DEBUGFS_FILENAME, 0444, vgpu->debugfs, | |
864 | &vgpu->nr_cache_entries); | |
865 | ||
675e5c4a | 866 | intel_gvt_activate_vgpu(vgpu); |
b79c52ae | 867 | |
62980cac | 868 | atomic_set(&vgpu->released, 0); |
0e09f406 | 869 | return 0; |
364fb6b7 JS |
870 | |
871 | undo_group: | |
62980cac CH |
872 | vfio_group_put_external_user(vgpu->vfio_group); |
873 | vgpu->vfio_group = NULL; | |
776d95b7 YZ |
874 | |
875 | undo_register: | |
978cf586 | 876 | vfio_unregister_notifier(vfio_dev->dev, VFIO_GROUP_NOTIFY, |
62980cac | 877 | &vgpu->group_notifier); |
659643f7 JS |
878 | |
879 | undo_iommu: | |
978cf586 | 880 | vfio_unregister_notifier(vfio_dev->dev, VFIO_IOMMU_NOTIFY, |
62980cac | 881 | &vgpu->iommu_notifier); |
659643f7 JS |
882 | out: |
883 | return ret; | |
884 | } | |
885 | ||
d54e7934 XZ |
886 | static void intel_vgpu_release_msi_eventfd_ctx(struct intel_vgpu *vgpu) |
887 | { | |
888 | struct eventfd_ctx *trigger; | |
889 | ||
62980cac | 890 | trigger = vgpu->msi_trigger; |
d54e7934 XZ |
891 | if (trigger) { |
892 | eventfd_ctx_put(trigger); | |
62980cac | 893 | vgpu->msi_trigger = NULL; |
d54e7934 XZ |
894 | } |
895 | } | |
896 | ||
659643f7 JS |
897 | static void __intel_vgpu_release(struct intel_vgpu *vgpu) |
898 | { | |
a61ac1e7 | 899 | struct drm_i915_private *i915 = vgpu->gvt->gt->i915; |
364fb6b7 | 900 | int ret; |
659643f7 | 901 | |
3c340d05 | 902 | if (!vgpu->attached) |
659643f7 JS |
903 | return; |
904 | ||
62980cac | 905 | if (atomic_cmpxchg(&vgpu->released, 0, 1)) |
364fb6b7 JS |
906 | return; |
907 | ||
675e5c4a | 908 | intel_gvt_release_vgpu(vgpu); |
b79c52ae | 909 | |
978cf586 | 910 | ret = vfio_unregister_notifier(vgpu->vfio_device.dev, VFIO_IOMMU_NOTIFY, |
62980cac | 911 | &vgpu->iommu_notifier); |
12d58619 PB |
912 | drm_WARN(&i915->drm, ret, |
913 | "vfio_unregister_notifier for iommu failed: %d\n", ret); | |
364fb6b7 | 914 | |
978cf586 | 915 | ret = vfio_unregister_notifier(vgpu->vfio_device.dev, VFIO_GROUP_NOTIFY, |
62980cac | 916 | &vgpu->group_notifier); |
12d58619 PB |
917 | drm_WARN(&i915->drm, ret, |
918 | "vfio_unregister_notifier for group failed: %d\n", ret); | |
659643f7 | 919 | |
0e09f406 CH |
920 | debugfs_remove(debugfs_lookup(KVMGT_DEBUGFS_FILENAME, vgpu->debugfs)); |
921 | ||
922 | kvm_page_track_unregister_notifier(vgpu->kvm, &vgpu->track_node); | |
923 | kvm_put_kvm(vgpu->kvm); | |
924 | kvmgt_protect_table_destroy(vgpu); | |
925 | gvt_cache_destroy(vgpu); | |
364fb6b7 | 926 | |
d54e7934 | 927 | intel_vgpu_release_msi_eventfd_ctx(vgpu); |
62980cac | 928 | vfio_group_put_external_user(vgpu->vfio_group); |
d54e7934 | 929 | |
62980cac | 930 | vgpu->kvm = NULL; |
3c340d05 | 931 | vgpu->attached = false; |
659643f7 JS |
932 | } |
933 | ||
978cf586 | 934 | static void intel_vgpu_close_device(struct vfio_device *vfio_dev) |
659643f7 | 935 | { |
978cf586 | 936 | __intel_vgpu_release(vfio_dev_to_vgpu(vfio_dev)); |
659643f7 JS |
937 | } |
938 | ||
939 | static void intel_vgpu_release_work(struct work_struct *work) | |
940 | { | |
62980cac CH |
941 | struct intel_vgpu *vgpu = |
942 | container_of(work, struct intel_vgpu, release_work); | |
8ff842fd | 943 | |
62980cac | 944 | __intel_vgpu_release(vgpu); |
659643f7 JS |
945 | } |
946 | ||
2e679d48 | 947 | static u64 intel_vgpu_get_bar_addr(struct intel_vgpu *vgpu, int bar) |
659643f7 JS |
948 | { |
949 | u32 start_lo, start_hi; | |
950 | u32 mem_type; | |
659643f7 | 951 | |
f090a00d | 952 | start_lo = (*(u32 *)(vgpu->cfg_space.virtual_cfg_space + bar)) & |
659643f7 | 953 | PCI_BASE_ADDRESS_MEM_MASK; |
f090a00d | 954 | mem_type = (*(u32 *)(vgpu->cfg_space.virtual_cfg_space + bar)) & |
659643f7 JS |
955 | PCI_BASE_ADDRESS_MEM_TYPE_MASK; |
956 | ||
957 | switch (mem_type) { | |
958 | case PCI_BASE_ADDRESS_MEM_TYPE_64: | |
959 | start_hi = (*(u32 *)(vgpu->cfg_space.virtual_cfg_space | |
f090a00d | 960 | + bar + 4)); |
659643f7 JS |
961 | break; |
962 | case PCI_BASE_ADDRESS_MEM_TYPE_32: | |
963 | case PCI_BASE_ADDRESS_MEM_TYPE_1M: | |
964 | /* 1M mem BAR treated as 32-bit BAR */ | |
965 | default: | |
966 | /* mem unknown type treated as 32-bit BAR */ | |
967 | start_hi = 0; | |
968 | break; | |
969 | } | |
970 | ||
971 | return ((u64)start_hi << 32) | start_lo; | |
972 | } | |
973 | ||
2e679d48 | 974 | static int intel_vgpu_bar_rw(struct intel_vgpu *vgpu, int bar, u64 off, |
f090a00d CD |
975 | void *buf, unsigned int count, bool is_write) |
976 | { | |
2e679d48 | 977 | u64 bar_start = intel_vgpu_get_bar_addr(vgpu, bar); |
f090a00d CD |
978 | int ret; |
979 | ||
980 | if (is_write) | |
675e5c4a | 981 | ret = intel_vgpu_emulate_mmio_write(vgpu, |
f090a00d CD |
982 | bar_start + off, buf, count); |
983 | else | |
675e5c4a | 984 | ret = intel_vgpu_emulate_mmio_read(vgpu, |
f090a00d CD |
985 | bar_start + off, buf, count); |
986 | return ret; | |
987 | } | |
988 | ||
2e679d48 | 989 | static inline bool intel_vgpu_in_aperture(struct intel_vgpu *vgpu, u64 off) |
d480b28a CD |
990 | { |
991 | return off >= vgpu_aperture_offset(vgpu) && | |
992 | off < vgpu_aperture_offset(vgpu) + vgpu_aperture_sz(vgpu); | |
993 | } | |
994 | ||
2e679d48 | 995 | static int intel_vgpu_aperture_rw(struct intel_vgpu *vgpu, u64 off, |
d480b28a CD |
996 | void *buf, unsigned long count, bool is_write) |
997 | { | |
196a6627 | 998 | void __iomem *aperture_va; |
d480b28a CD |
999 | |
1000 | if (!intel_vgpu_in_aperture(vgpu, off) || | |
1001 | !intel_vgpu_in_aperture(vgpu, off + count)) { | |
1002 | gvt_vgpu_err("Invalid aperture offset %llu\n", off); | |
1003 | return -EINVAL; | |
1004 | } | |
1005 | ||
a61ac1e7 | 1006 | aperture_va = io_mapping_map_wc(&vgpu->gvt->gt->ggtt->iomap, |
d480b28a CD |
1007 | ALIGN_DOWN(off, PAGE_SIZE), |
1008 | count + offset_in_page(off)); | |
1009 | if (!aperture_va) | |
1010 | return -EIO; | |
1011 | ||
1012 | if (is_write) | |
196a6627 | 1013 | memcpy_toio(aperture_va + offset_in_page(off), buf, count); |
d480b28a | 1014 | else |
196a6627 | 1015 | memcpy_fromio(buf, aperture_va + offset_in_page(off), count); |
d480b28a CD |
1016 | |
1017 | io_mapping_unmap(aperture_va); | |
1018 | ||
1019 | return 0; | |
1020 | } | |
1021 | ||
7f11e689 | 1022 | static ssize_t intel_vgpu_rw(struct intel_vgpu *vgpu, char *buf, |
659643f7 JS |
1023 | size_t count, loff_t *ppos, bool is_write) |
1024 | { | |
659643f7 | 1025 | unsigned int index = VFIO_PCI_OFFSET_TO_INDEX(*ppos); |
2e679d48 | 1026 | u64 pos = *ppos & VFIO_PCI_OFFSET_MASK; |
659643f7 JS |
1027 | int ret = -EINVAL; |
1028 | ||
1029 | ||
62980cac | 1030 | if (index >= VFIO_PCI_NUM_REGIONS + vgpu->num_regions) { |
695fbc08 | 1031 | gvt_vgpu_err("invalid index: %u\n", index); |
659643f7 JS |
1032 | return -EINVAL; |
1033 | } | |
1034 | ||
1035 | switch (index) { | |
1036 | case VFIO_PCI_CONFIG_REGION_INDEX: | |
1037 | if (is_write) | |
675e5c4a | 1038 | ret = intel_vgpu_emulate_cfg_write(vgpu, pos, |
659643f7 JS |
1039 | buf, count); |
1040 | else | |
675e5c4a | 1041 | ret = intel_vgpu_emulate_cfg_read(vgpu, pos, |
659643f7 JS |
1042 | buf, count); |
1043 | break; | |
1044 | case VFIO_PCI_BAR0_REGION_INDEX: | |
f090a00d CD |
1045 | ret = intel_vgpu_bar_rw(vgpu, PCI_BASE_ADDRESS_0, pos, |
1046 | buf, count, is_write); | |
659643f7 JS |
1047 | break; |
1048 | case VFIO_PCI_BAR2_REGION_INDEX: | |
d480b28a | 1049 | ret = intel_vgpu_aperture_rw(vgpu, pos, buf, count, is_write); |
f090a00d CD |
1050 | break; |
1051 | case VFIO_PCI_BAR1_REGION_INDEX: | |
659643f7 JS |
1052 | case VFIO_PCI_BAR3_REGION_INDEX: |
1053 | case VFIO_PCI_BAR4_REGION_INDEX: | |
1054 | case VFIO_PCI_BAR5_REGION_INDEX: | |
1055 | case VFIO_PCI_VGA_REGION_INDEX: | |
1056 | case VFIO_PCI_ROM_REGION_INDEX: | |
b851adea | 1057 | break; |
659643f7 | 1058 | default: |
62980cac | 1059 | if (index >= VFIO_PCI_NUM_REGIONS + vgpu->num_regions) |
b851adea TZ |
1060 | return -EINVAL; |
1061 | ||
1062 | index -= VFIO_PCI_NUM_REGIONS; | |
62980cac | 1063 | return vgpu->region[index].ops->rw(vgpu, buf, count, |
b851adea | 1064 | ppos, is_write); |
659643f7 JS |
1065 | } |
1066 | ||
1067 | return ret == 0 ? count : ret; | |
1068 | } | |
1069 | ||
7f11e689 | 1070 | static bool gtt_entry(struct intel_vgpu *vgpu, loff_t *ppos) |
a26ca6ad | 1071 | { |
a26ca6ad TZ |
1072 | unsigned int index = VFIO_PCI_OFFSET_TO_INDEX(*ppos); |
1073 | struct intel_gvt *gvt = vgpu->gvt; | |
1074 | int offset; | |
1075 | ||
1076 | /* Only allow MMIO GGTT entry access */ | |
1077 | if (index != PCI_BASE_ADDRESS_0) | |
1078 | return false; | |
1079 | ||
1080 | offset = (u64)(*ppos & VFIO_PCI_OFFSET_MASK) - | |
1081 | intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_0); | |
1082 | ||
1083 | return (offset >= gvt->device_info.gtt_start_offset && | |
1084 | offset < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt)) ? | |
1085 | true : false; | |
1086 | } | |
1087 | ||
978cf586 | 1088 | static ssize_t intel_vgpu_read(struct vfio_device *vfio_dev, char __user *buf, |
659643f7 JS |
1089 | size_t count, loff_t *ppos) |
1090 | { | |
978cf586 | 1091 | struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); |
659643f7 JS |
1092 | unsigned int done = 0; |
1093 | int ret; | |
1094 | ||
1095 | while (count) { | |
1096 | size_t filled; | |
1097 | ||
a26ca6ad TZ |
1098 | /* Only support GGTT entry 8 bytes read */ |
1099 | if (count >= 8 && !(*ppos % 8) && | |
7f11e689 | 1100 | gtt_entry(vgpu, ppos)) { |
a26ca6ad TZ |
1101 | u64 val; |
1102 | ||
7f11e689 | 1103 | ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val), |
a26ca6ad TZ |
1104 | ppos, false); |
1105 | if (ret <= 0) | |
1106 | goto read_err; | |
1107 | ||
1108 | if (copy_to_user(buf, &val, sizeof(val))) | |
1109 | goto read_err; | |
1110 | ||
1111 | filled = 8; | |
1112 | } else if (count >= 4 && !(*ppos % 4)) { | |
659643f7 JS |
1113 | u32 val; |
1114 | ||
7f11e689 | 1115 | ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val), |
659643f7 JS |
1116 | ppos, false); |
1117 | if (ret <= 0) | |
1118 | goto read_err; | |
1119 | ||
1120 | if (copy_to_user(buf, &val, sizeof(val))) | |
1121 | goto read_err; | |
1122 | ||
1123 | filled = 4; | |
1124 | } else if (count >= 2 && !(*ppos % 2)) { | |
1125 | u16 val; | |
1126 | ||
7f11e689 | 1127 | ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val), |
659643f7 JS |
1128 | ppos, false); |
1129 | if (ret <= 0) | |
1130 | goto read_err; | |
1131 | ||
1132 | if (copy_to_user(buf, &val, sizeof(val))) | |
1133 | goto read_err; | |
1134 | ||
1135 | filled = 2; | |
1136 | } else { | |
1137 | u8 val; | |
1138 | ||
7f11e689 | 1139 | ret = intel_vgpu_rw(vgpu, &val, sizeof(val), ppos, |
659643f7 JS |
1140 | false); |
1141 | if (ret <= 0) | |
1142 | goto read_err; | |
1143 | ||
1144 | if (copy_to_user(buf, &val, sizeof(val))) | |
1145 | goto read_err; | |
1146 | ||
1147 | filled = 1; | |
1148 | } | |
1149 | ||
1150 | count -= filled; | |
1151 | done += filled; | |
1152 | *ppos += filled; | |
1153 | buf += filled; | |
1154 | } | |
1155 | ||
1156 | return done; | |
1157 | ||
1158 | read_err: | |
1159 | return -EFAULT; | |
1160 | } | |
1161 | ||
978cf586 | 1162 | static ssize_t intel_vgpu_write(struct vfio_device *vfio_dev, |
659643f7 JS |
1163 | const char __user *buf, |
1164 | size_t count, loff_t *ppos) | |
1165 | { | |
978cf586 | 1166 | struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); |
659643f7 JS |
1167 | unsigned int done = 0; |
1168 | int ret; | |
1169 | ||
1170 | while (count) { | |
1171 | size_t filled; | |
1172 | ||
a26ca6ad TZ |
1173 | /* Only support GGTT entry 8 bytes write */ |
1174 | if (count >= 8 && !(*ppos % 8) && | |
7f11e689 | 1175 | gtt_entry(vgpu, ppos)) { |
a26ca6ad TZ |
1176 | u64 val; |
1177 | ||
1178 | if (copy_from_user(&val, buf, sizeof(val))) | |
1179 | goto write_err; | |
1180 | ||
7f11e689 | 1181 | ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val), |
a26ca6ad TZ |
1182 | ppos, true); |
1183 | if (ret <= 0) | |
1184 | goto write_err; | |
1185 | ||
1186 | filled = 8; | |
1187 | } else if (count >= 4 && !(*ppos % 4)) { | |
659643f7 JS |
1188 | u32 val; |
1189 | ||
1190 | if (copy_from_user(&val, buf, sizeof(val))) | |
1191 | goto write_err; | |
1192 | ||
7f11e689 | 1193 | ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val), |
659643f7 JS |
1194 | ppos, true); |
1195 | if (ret <= 0) | |
1196 | goto write_err; | |
1197 | ||
1198 | filled = 4; | |
1199 | } else if (count >= 2 && !(*ppos % 2)) { | |
1200 | u16 val; | |
1201 | ||
1202 | if (copy_from_user(&val, buf, sizeof(val))) | |
1203 | goto write_err; | |
1204 | ||
7f11e689 | 1205 | ret = intel_vgpu_rw(vgpu, (char *)&val, |
659643f7 JS |
1206 | sizeof(val), ppos, true); |
1207 | if (ret <= 0) | |
1208 | goto write_err; | |
1209 | ||
1210 | filled = 2; | |
1211 | } else { | |
1212 | u8 val; | |
1213 | ||
1214 | if (copy_from_user(&val, buf, sizeof(val))) | |
1215 | goto write_err; | |
1216 | ||
7f11e689 | 1217 | ret = intel_vgpu_rw(vgpu, &val, sizeof(val), |
659643f7 JS |
1218 | ppos, true); |
1219 | if (ret <= 0) | |
1220 | goto write_err; | |
1221 | ||
1222 | filled = 1; | |
1223 | } | |
1224 | ||
1225 | count -= filled; | |
1226 | done += filled; | |
1227 | *ppos += filled; | |
1228 | buf += filled; | |
1229 | } | |
1230 | ||
1231 | return done; | |
1232 | write_err: | |
1233 | return -EFAULT; | |
1234 | } | |
1235 | ||
978cf586 CH |
1236 | static int intel_vgpu_mmap(struct vfio_device *vfio_dev, |
1237 | struct vm_area_struct *vma) | |
659643f7 | 1238 | { |
978cf586 | 1239 | struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); |
659643f7 JS |
1240 | unsigned int index; |
1241 | u64 virtaddr; | |
51b00d85 | 1242 | unsigned long req_size, pgoff, req_start; |
659643f7 | 1243 | pgprot_t pg_prot; |
659643f7 JS |
1244 | |
1245 | index = vma->vm_pgoff >> (VFIO_PCI_OFFSET_SHIFT - PAGE_SHIFT); | |
1246 | if (index >= VFIO_PCI_ROM_REGION_INDEX) | |
1247 | return -EINVAL; | |
1248 | ||
1249 | if (vma->vm_end < vma->vm_start) | |
1250 | return -EINVAL; | |
1251 | if ((vma->vm_flags & VM_SHARED) == 0) | |
1252 | return -EINVAL; | |
1253 | if (index != VFIO_PCI_BAR2_REGION_INDEX) | |
1254 | return -EINVAL; | |
1255 | ||
1256 | pg_prot = vma->vm_page_prot; | |
1257 | virtaddr = vma->vm_start; | |
1258 | req_size = vma->vm_end - vma->vm_start; | |
51b00d85 ZW |
1259 | pgoff = vma->vm_pgoff & |
1260 | ((1U << (VFIO_PCI_OFFSET_SHIFT - PAGE_SHIFT)) - 1); | |
1261 | req_start = pgoff << PAGE_SHIFT; | |
1262 | ||
1263 | if (!intel_vgpu_in_aperture(vgpu, req_start)) | |
1264 | return -EINVAL; | |
1265 | if (req_start + req_size > | |
1266 | vgpu_aperture_offset(vgpu) + vgpu_aperture_sz(vgpu)) | |
1267 | return -EINVAL; | |
1268 | ||
1269 | pgoff = (gvt_aperture_pa_base(vgpu->gvt) >> PAGE_SHIFT) + pgoff; | |
659643f7 JS |
1270 | |
1271 | return remap_pfn_range(vma, virtaddr, pgoff, req_size, pg_prot); | |
1272 | } | |
1273 | ||
1274 | static int intel_vgpu_get_irq_count(struct intel_vgpu *vgpu, int type) | |
1275 | { | |
1276 | if (type == VFIO_PCI_INTX_IRQ_INDEX || type == VFIO_PCI_MSI_IRQ_INDEX) | |
1277 | return 1; | |
1278 | ||
1279 | return 0; | |
1280 | } | |
1281 | ||
1282 | static int intel_vgpu_set_intx_mask(struct intel_vgpu *vgpu, | |
1283 | unsigned int index, unsigned int start, | |
2e679d48 | 1284 | unsigned int count, u32 flags, |
659643f7 JS |
1285 | void *data) |
1286 | { | |
1287 | return 0; | |
1288 | } | |
1289 | ||
1290 | static int intel_vgpu_set_intx_unmask(struct intel_vgpu *vgpu, | |
1291 | unsigned int index, unsigned int start, | |
2e679d48 | 1292 | unsigned int count, u32 flags, void *data) |
659643f7 JS |
1293 | { |
1294 | return 0; | |
1295 | } | |
1296 | ||
1297 | static int intel_vgpu_set_intx_trigger(struct intel_vgpu *vgpu, | |
1298 | unsigned int index, unsigned int start, unsigned int count, | |
2e679d48 | 1299 | u32 flags, void *data) |
659643f7 JS |
1300 | { |
1301 | return 0; | |
1302 | } | |
1303 | ||
1304 | static int intel_vgpu_set_msi_trigger(struct intel_vgpu *vgpu, | |
1305 | unsigned int index, unsigned int start, unsigned int count, | |
2e679d48 | 1306 | u32 flags, void *data) |
659643f7 JS |
1307 | { |
1308 | struct eventfd_ctx *trigger; | |
1309 | ||
1310 | if (flags & VFIO_IRQ_SET_DATA_EVENTFD) { | |
1311 | int fd = *(int *)data; | |
1312 | ||
1313 | trigger = eventfd_ctx_fdget(fd); | |
1314 | if (IS_ERR(trigger)) { | |
695fbc08 | 1315 | gvt_vgpu_err("eventfd_ctx_fdget failed\n"); |
659643f7 JS |
1316 | return PTR_ERR(trigger); |
1317 | } | |
62980cac | 1318 | vgpu->msi_trigger = trigger; |
d54e7934 XZ |
1319 | } else if ((flags & VFIO_IRQ_SET_DATA_NONE) && !count) |
1320 | intel_vgpu_release_msi_eventfd_ctx(vgpu); | |
659643f7 JS |
1321 | |
1322 | return 0; | |
1323 | } | |
1324 | ||
2e679d48 | 1325 | static int intel_vgpu_set_irqs(struct intel_vgpu *vgpu, u32 flags, |
659643f7 JS |
1326 | unsigned int index, unsigned int start, unsigned int count, |
1327 | void *data) | |
1328 | { | |
1329 | int (*func)(struct intel_vgpu *vgpu, unsigned int index, | |
2e679d48 | 1330 | unsigned int start, unsigned int count, u32 flags, |
659643f7 JS |
1331 | void *data) = NULL; |
1332 | ||
1333 | switch (index) { | |
1334 | case VFIO_PCI_INTX_IRQ_INDEX: | |
1335 | switch (flags & VFIO_IRQ_SET_ACTION_TYPE_MASK) { | |
1336 | case VFIO_IRQ_SET_ACTION_MASK: | |
1337 | func = intel_vgpu_set_intx_mask; | |
1338 | break; | |
1339 | case VFIO_IRQ_SET_ACTION_UNMASK: | |
1340 | func = intel_vgpu_set_intx_unmask; | |
1341 | break; | |
1342 | case VFIO_IRQ_SET_ACTION_TRIGGER: | |
1343 | func = intel_vgpu_set_intx_trigger; | |
1344 | break; | |
1345 | } | |
1346 | break; | |
1347 | case VFIO_PCI_MSI_IRQ_INDEX: | |
1348 | switch (flags & VFIO_IRQ_SET_ACTION_TYPE_MASK) { | |
1349 | case VFIO_IRQ_SET_ACTION_MASK: | |
1350 | case VFIO_IRQ_SET_ACTION_UNMASK: | |
1351 | /* XXX Need masking support exported */ | |
1352 | break; | |
1353 | case VFIO_IRQ_SET_ACTION_TRIGGER: | |
1354 | func = intel_vgpu_set_msi_trigger; | |
1355 | break; | |
1356 | } | |
1357 | break; | |
1358 | } | |
1359 | ||
1360 | if (!func) | |
1361 | return -ENOTTY; | |
1362 | ||
1363 | return func(vgpu, index, start, count, flags, data); | |
1364 | } | |
1365 | ||
978cf586 | 1366 | static long intel_vgpu_ioctl(struct vfio_device *vfio_dev, unsigned int cmd, |
659643f7 JS |
1367 | unsigned long arg) |
1368 | { | |
978cf586 | 1369 | struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); |
659643f7 JS |
1370 | unsigned long minsz; |
1371 | ||
1372 | gvt_dbg_core("vgpu%d ioctl, cmd: %d\n", vgpu->id, cmd); | |
1373 | ||
1374 | if (cmd == VFIO_DEVICE_GET_INFO) { | |
1375 | struct vfio_device_info info; | |
1376 | ||
1377 | minsz = offsetofend(struct vfio_device_info, num_irqs); | |
1378 | ||
1379 | if (copy_from_user(&info, (void __user *)arg, minsz)) | |
1380 | return -EFAULT; | |
1381 | ||
1382 | if (info.argsz < minsz) | |
1383 | return -EINVAL; | |
1384 | ||
1385 | info.flags = VFIO_DEVICE_FLAGS_PCI; | |
1386 | info.flags |= VFIO_DEVICE_FLAGS_RESET; | |
b851adea | 1387 | info.num_regions = VFIO_PCI_NUM_REGIONS + |
62980cac | 1388 | vgpu->num_regions; |
659643f7 JS |
1389 | info.num_irqs = VFIO_PCI_NUM_IRQS; |
1390 | ||
1391 | return copy_to_user((void __user *)arg, &info, minsz) ? | |
1392 | -EFAULT : 0; | |
1393 | ||
1394 | } else if (cmd == VFIO_DEVICE_GET_REGION_INFO) { | |
1395 | struct vfio_region_info info; | |
1396 | struct vfio_info_cap caps = { .buf = NULL, .size = 0 }; | |
de5372da GS |
1397 | unsigned int i; |
1398 | int ret; | |
659643f7 | 1399 | struct vfio_region_info_cap_sparse_mmap *sparse = NULL; |
659643f7 JS |
1400 | int nr_areas = 1; |
1401 | int cap_type_id; | |
1402 | ||
1403 | minsz = offsetofend(struct vfio_region_info, offset); | |
1404 | ||
1405 | if (copy_from_user(&info, (void __user *)arg, minsz)) | |
1406 | return -EFAULT; | |
1407 | ||
1408 | if (info.argsz < minsz) | |
1409 | return -EINVAL; | |
1410 | ||
1411 | switch (info.index) { | |
1412 | case VFIO_PCI_CONFIG_REGION_INDEX: | |
1413 | info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); | |
02d578e5 | 1414 | info.size = vgpu->gvt->device_info.cfg_space_size; |
659643f7 JS |
1415 | info.flags = VFIO_REGION_INFO_FLAG_READ | |
1416 | VFIO_REGION_INFO_FLAG_WRITE; | |
1417 | break; | |
1418 | case VFIO_PCI_BAR0_REGION_INDEX: | |
1419 | info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); | |
1420 | info.size = vgpu->cfg_space.bar[info.index].size; | |
1421 | if (!info.size) { | |
1422 | info.flags = 0; | |
1423 | break; | |
1424 | } | |
1425 | ||
1426 | info.flags = VFIO_REGION_INFO_FLAG_READ | | |
1427 | VFIO_REGION_INFO_FLAG_WRITE; | |
1428 | break; | |
1429 | case VFIO_PCI_BAR1_REGION_INDEX: | |
1430 | info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); | |
1431 | info.size = 0; | |
1432 | info.flags = 0; | |
1433 | break; | |
1434 | case VFIO_PCI_BAR2_REGION_INDEX: | |
1435 | info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); | |
1436 | info.flags = VFIO_REGION_INFO_FLAG_CAPS | | |
1437 | VFIO_REGION_INFO_FLAG_MMAP | | |
1438 | VFIO_REGION_INFO_FLAG_READ | | |
1439 | VFIO_REGION_INFO_FLAG_WRITE; | |
1440 | info.size = gvt_aperture_sz(vgpu->gvt); | |
1441 | ||
cd3e0583 GS |
1442 | sparse = kzalloc(struct_size(sparse, areas, nr_areas), |
1443 | GFP_KERNEL); | |
659643f7 JS |
1444 | if (!sparse) |
1445 | return -ENOMEM; | |
1446 | ||
dda01f78 AW |
1447 | sparse->header.id = VFIO_REGION_INFO_CAP_SPARSE_MMAP; |
1448 | sparse->header.version = 1; | |
659643f7 JS |
1449 | sparse->nr_areas = nr_areas; |
1450 | cap_type_id = VFIO_REGION_INFO_CAP_SPARSE_MMAP; | |
1451 | sparse->areas[0].offset = | |
1452 | PAGE_ALIGN(vgpu_aperture_offset(vgpu)); | |
1453 | sparse->areas[0].size = vgpu_aperture_sz(vgpu); | |
659643f7 JS |
1454 | break; |
1455 | ||
1456 | case VFIO_PCI_BAR3_REGION_INDEX ... VFIO_PCI_BAR5_REGION_INDEX: | |
1457 | info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); | |
1458 | info.size = 0; | |
659643f7 | 1459 | info.flags = 0; |
072ec93d | 1460 | |
659643f7 JS |
1461 | gvt_dbg_core("get region info bar:%d\n", info.index); |
1462 | break; | |
1463 | ||
1464 | case VFIO_PCI_ROM_REGION_INDEX: | |
1465 | case VFIO_PCI_VGA_REGION_INDEX: | |
072ec93d PZ |
1466 | info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); |
1467 | info.size = 0; | |
1468 | info.flags = 0; | |
1469 | ||
659643f7 JS |
1470 | gvt_dbg_core("get region info index:%d\n", info.index); |
1471 | break; | |
1472 | default: | |
1473 | { | |
dda01f78 AW |
1474 | struct vfio_region_info_cap_type cap_type = { |
1475 | .header.id = VFIO_REGION_INFO_CAP_TYPE, | |
1476 | .header.version = 1 }; | |
659643f7 JS |
1477 | |
1478 | if (info.index >= VFIO_PCI_NUM_REGIONS + | |
62980cac | 1479 | vgpu->num_regions) |
659643f7 | 1480 | return -EINVAL; |
de5372da GS |
1481 | info.index = |
1482 | array_index_nospec(info.index, | |
1483 | VFIO_PCI_NUM_REGIONS + | |
62980cac | 1484 | vgpu->num_regions); |
659643f7 JS |
1485 | |
1486 | i = info.index - VFIO_PCI_NUM_REGIONS; | |
1487 | ||
1488 | info.offset = | |
1489 | VFIO_PCI_INDEX_TO_OFFSET(info.index); | |
62980cac CH |
1490 | info.size = vgpu->region[i].size; |
1491 | info.flags = vgpu->region[i].flags; | |
659643f7 | 1492 | |
62980cac CH |
1493 | cap_type.type = vgpu->region[i].type; |
1494 | cap_type.subtype = vgpu->region[i].subtype; | |
659643f7 JS |
1495 | |
1496 | ret = vfio_info_add_capability(&caps, | |
dda01f78 AW |
1497 | &cap_type.header, |
1498 | sizeof(cap_type)); | |
659643f7 JS |
1499 | if (ret) |
1500 | return ret; | |
1501 | } | |
1502 | } | |
1503 | ||
1504 | if ((info.flags & VFIO_REGION_INFO_FLAG_CAPS) && sparse) { | |
1505 | switch (cap_type_id) { | |
1506 | case VFIO_REGION_INFO_CAP_SPARSE_MMAP: | |
1507 | ret = vfio_info_add_capability(&caps, | |
cd3e0583 GS |
1508 | &sparse->header, |
1509 | struct_size(sparse, areas, | |
1510 | sparse->nr_areas)); | |
7590ebb8 YW |
1511 | if (ret) { |
1512 | kfree(sparse); | |
659643f7 | 1513 | return ret; |
7590ebb8 | 1514 | } |
659643f7 JS |
1515 | break; |
1516 | default: | |
7590ebb8 | 1517 | kfree(sparse); |
659643f7 JS |
1518 | return -EINVAL; |
1519 | } | |
1520 | } | |
1521 | ||
1522 | if (caps.size) { | |
b851adea | 1523 | info.flags |= VFIO_REGION_INFO_FLAG_CAPS; |
659643f7 JS |
1524 | if (info.argsz < sizeof(info) + caps.size) { |
1525 | info.argsz = sizeof(info) + caps.size; | |
1526 | info.cap_offset = 0; | |
1527 | } else { | |
1528 | vfio_info_cap_shift(&caps, sizeof(info)); | |
1529 | if (copy_to_user((void __user *)arg + | |
1530 | sizeof(info), caps.buf, | |
1531 | caps.size)) { | |
1532 | kfree(caps.buf); | |
7590ebb8 | 1533 | kfree(sparse); |
659643f7 JS |
1534 | return -EFAULT; |
1535 | } | |
1536 | info.cap_offset = sizeof(info); | |
1537 | } | |
1538 | ||
1539 | kfree(caps.buf); | |
1540 | } | |
1541 | ||
7590ebb8 | 1542 | kfree(sparse); |
659643f7 JS |
1543 | return copy_to_user((void __user *)arg, &info, minsz) ? |
1544 | -EFAULT : 0; | |
1545 | } else if (cmd == VFIO_DEVICE_GET_IRQ_INFO) { | |
1546 | struct vfio_irq_info info; | |
1547 | ||
1548 | minsz = offsetofend(struct vfio_irq_info, count); | |
1549 | ||
1550 | if (copy_from_user(&info, (void __user *)arg, minsz)) | |
1551 | return -EFAULT; | |
1552 | ||
1553 | if (info.argsz < minsz || info.index >= VFIO_PCI_NUM_IRQS) | |
1554 | return -EINVAL; | |
1555 | ||
1556 | switch (info.index) { | |
1557 | case VFIO_PCI_INTX_IRQ_INDEX: | |
1558 | case VFIO_PCI_MSI_IRQ_INDEX: | |
1559 | break; | |
1560 | default: | |
1561 | return -EINVAL; | |
1562 | } | |
1563 | ||
1564 | info.flags = VFIO_IRQ_INFO_EVENTFD; | |
1565 | ||
1566 | info.count = intel_vgpu_get_irq_count(vgpu, info.index); | |
1567 | ||
1568 | if (info.index == VFIO_PCI_INTX_IRQ_INDEX) | |
1569 | info.flags |= (VFIO_IRQ_INFO_MASKABLE | | |
1570 | VFIO_IRQ_INFO_AUTOMASKED); | |
1571 | else | |
1572 | info.flags |= VFIO_IRQ_INFO_NORESIZE; | |
1573 | ||
1574 | return copy_to_user((void __user *)arg, &info, minsz) ? | |
1575 | -EFAULT : 0; | |
1576 | } else if (cmd == VFIO_DEVICE_SET_IRQS) { | |
1577 | struct vfio_irq_set hdr; | |
1578 | u8 *data = NULL; | |
1579 | int ret = 0; | |
1580 | size_t data_size = 0; | |
1581 | ||
1582 | minsz = offsetofend(struct vfio_irq_set, count); | |
1583 | ||
1584 | if (copy_from_user(&hdr, (void __user *)arg, minsz)) | |
1585 | return -EFAULT; | |
1586 | ||
1587 | if (!(hdr.flags & VFIO_IRQ_SET_DATA_NONE)) { | |
1588 | int max = intel_vgpu_get_irq_count(vgpu, hdr.index); | |
1589 | ||
1590 | ret = vfio_set_irqs_validate_and_prepare(&hdr, max, | |
1591 | VFIO_PCI_NUM_IRQS, &data_size); | |
1592 | if (ret) { | |
695fbc08 | 1593 | gvt_vgpu_err("intel:vfio_set_irqs_validate_and_prepare failed\n"); |
659643f7 JS |
1594 | return -EINVAL; |
1595 | } | |
1596 | if (data_size) { | |
1597 | data = memdup_user((void __user *)(arg + minsz), | |
1598 | data_size); | |
1599 | if (IS_ERR(data)) | |
1600 | return PTR_ERR(data); | |
1601 | } | |
1602 | } | |
1603 | ||
1604 | ret = intel_vgpu_set_irqs(vgpu, hdr.flags, hdr.index, | |
1605 | hdr.start, hdr.count, data); | |
1606 | kfree(data); | |
1607 | ||
1608 | return ret; | |
1609 | } else if (cmd == VFIO_DEVICE_RESET) { | |
675e5c4a | 1610 | intel_gvt_reset_vgpu(vgpu); |
659643f7 | 1611 | return 0; |
e546e281 TZ |
1612 | } else if (cmd == VFIO_DEVICE_QUERY_GFX_PLANE) { |
1613 | struct vfio_device_gfx_plane_info dmabuf; | |
1614 | int ret = 0; | |
1615 | ||
1616 | minsz = offsetofend(struct vfio_device_gfx_plane_info, | |
1617 | dmabuf_id); | |
1618 | if (copy_from_user(&dmabuf, (void __user *)arg, minsz)) | |
1619 | return -EFAULT; | |
1620 | if (dmabuf.argsz < minsz) | |
1621 | return -EINVAL; | |
1622 | ||
675e5c4a | 1623 | ret = intel_vgpu_query_plane(vgpu, &dmabuf); |
e546e281 TZ |
1624 | if (ret != 0) |
1625 | return ret; | |
1626 | ||
1627 | return copy_to_user((void __user *)arg, &dmabuf, minsz) ? | |
1628 | -EFAULT : 0; | |
1629 | } else if (cmd == VFIO_DEVICE_GET_GFX_DMABUF) { | |
1630 | __u32 dmabuf_id; | |
e546e281 TZ |
1631 | |
1632 | if (get_user(dmabuf_id, (__u32 __user *)arg)) | |
1633 | return -EFAULT; | |
675e5c4a | 1634 | return intel_vgpu_get_dmabuf(vgpu, dmabuf_id); |
659643f7 JS |
1635 | } |
1636 | ||
9f591ae6 | 1637 | return -ENOTTY; |
659643f7 JS |
1638 | } |
1639 | ||
7a7a6561 ZW |
1640 | static ssize_t |
1641 | vgpu_id_show(struct device *dev, struct device_attribute *attr, | |
1642 | char *buf) | |
1643 | { | |
978cf586 | 1644 | struct intel_vgpu *vgpu = dev_get_drvdata(dev); |
7a7a6561 | 1645 | |
978cf586 | 1646 | return sprintf(buf, "%d\n", vgpu->id); |
7a7a6561 ZW |
1647 | } |
1648 | ||
1649 | static DEVICE_ATTR_RO(vgpu_id); | |
1650 | ||
1651 | static struct attribute *intel_vgpu_attrs[] = { | |
1652 | &dev_attr_vgpu_id.attr, | |
1653 | NULL | |
1654 | }; | |
1655 | ||
1656 | static const struct attribute_group intel_vgpu_group = { | |
1657 | .name = "intel_vgpu", | |
1658 | .attrs = intel_vgpu_attrs, | |
1659 | }; | |
1660 | ||
1661 | static const struct attribute_group *intel_vgpu_groups[] = { | |
1662 | &intel_vgpu_group, | |
1663 | NULL, | |
1664 | }; | |
1665 | ||
978cf586 CH |
1666 | static const struct vfio_device_ops intel_vgpu_dev_ops = { |
1667 | .open_device = intel_vgpu_open_device, | |
1668 | .close_device = intel_vgpu_close_device, | |
1669 | .read = intel_vgpu_read, | |
1670 | .write = intel_vgpu_write, | |
1671 | .mmap = intel_vgpu_mmap, | |
1672 | .ioctl = intel_vgpu_ioctl, | |
1673 | }; | |
659643f7 | 1674 | |
978cf586 CH |
1675 | static int intel_vgpu_probe(struct mdev_device *mdev) |
1676 | { | |
1677 | struct device *pdev = mdev_parent_dev(mdev); | |
1678 | struct intel_gvt *gvt = kdev_to_i915(pdev)->gvt; | |
1679 | struct intel_vgpu_type *type; | |
1680 | struct intel_vgpu *vgpu; | |
1681 | int ret; | |
1682 | ||
1683 | type = &gvt->types[mdev_get_type_group_id(mdev)]; | |
1684 | if (!type) | |
1685 | return -EINVAL; | |
1686 | ||
1687 | vgpu = intel_gvt_create_vgpu(gvt, type); | |
1688 | if (IS_ERR(vgpu)) { | |
1689 | gvt_err("failed to create intel vgpu: %ld\n", PTR_ERR(vgpu)); | |
1690 | return PTR_ERR(vgpu); | |
1691 | } | |
659643f7 | 1692 | |
978cf586 CH |
1693 | INIT_WORK(&vgpu->release_work, intel_vgpu_release_work); |
1694 | vfio_init_group_dev(&vgpu->vfio_device, &mdev->dev, | |
1695 | &intel_vgpu_dev_ops); | |
1696 | ||
1697 | dev_set_drvdata(&mdev->dev, vgpu); | |
1698 | ret = vfio_register_emulated_iommu_dev(&vgpu->vfio_device); | |
1699 | if (ret) { | |
1700 | intel_gvt_destroy_vgpu(vgpu); | |
1701 | return ret; | |
1702 | } | |
1703 | ||
1704 | gvt_dbg_core("intel_vgpu_create succeeded for mdev: %s\n", | |
1705 | dev_name(mdev_dev(mdev))); | |
1706 | return 0; | |
1707 | } | |
1708 | ||
1709 | static void intel_vgpu_remove(struct mdev_device *mdev) | |
1710 | { | |
1711 | struct intel_vgpu *vgpu = dev_get_drvdata(&mdev->dev); | |
1712 | ||
1713 | if (WARN_ON_ONCE(vgpu->attached)) | |
1714 | return; | |
1715 | intel_gvt_destroy_vgpu(vgpu); | |
1716 | } | |
1717 | ||
1718 | static struct mdev_driver intel_vgpu_mdev_driver = { | |
1719 | .driver = { | |
1720 | .name = "intel_vgpu_mdev", | |
1721 | .owner = THIS_MODULE, | |
1722 | .dev_groups = intel_vgpu_groups, | |
1723 | }, | |
1724 | .probe = intel_vgpu_probe, | |
1725 | .remove = intel_vgpu_remove, | |
978cf586 | 1726 | .supported_type_groups = gvt_vgpu_type_groups, |
659643f7 JS |
1727 | }; |
1728 | ||
4c2baaaf | 1729 | int intel_gvt_page_track_add(struct intel_vgpu *info, u64 gfn) |
f30437c5 | 1730 | { |
3c340d05 | 1731 | struct kvm *kvm = info->kvm; |
f30437c5 JS |
1732 | struct kvm_memory_slot *slot; |
1733 | int idx; | |
1734 | ||
3c340d05 | 1735 | if (!info->attached) |
659643f7 JS |
1736 | return -ESRCH; |
1737 | ||
f30437c5 JS |
1738 | idx = srcu_read_lock(&kvm->srcu); |
1739 | slot = gfn_to_memslot(kvm, gfn); | |
faaaa53b JS |
1740 | if (!slot) { |
1741 | srcu_read_unlock(&kvm->srcu, idx); | |
1742 | return -EINVAL; | |
1743 | } | |
f30437c5 | 1744 | |
e36b250e | 1745 | write_lock(&kvm->mmu_lock); |
f30437c5 JS |
1746 | |
1747 | if (kvmgt_gfn_is_write_protected(info, gfn)) | |
1748 | goto out; | |
1749 | ||
1750 | kvm_slot_page_track_add_page(kvm, slot, gfn, KVM_PAGE_TRACK_WRITE); | |
1751 | kvmgt_protect_table_add(info, gfn); | |
1752 | ||
1753 | out: | |
e36b250e | 1754 | write_unlock(&kvm->mmu_lock); |
f30437c5 JS |
1755 | srcu_read_unlock(&kvm->srcu, idx); |
1756 | return 0; | |
1757 | } | |
1758 | ||
4c2baaaf | 1759 | int intel_gvt_page_track_remove(struct intel_vgpu *info, u64 gfn) |
f30437c5 | 1760 | { |
3c340d05 | 1761 | struct kvm *kvm = info->kvm; |
f30437c5 JS |
1762 | struct kvm_memory_slot *slot; |
1763 | int idx; | |
1764 | ||
3c340d05 | 1765 | if (!info->attached) |
659643f7 JS |
1766 | return 0; |
1767 | ||
f30437c5 JS |
1768 | idx = srcu_read_lock(&kvm->srcu); |
1769 | slot = gfn_to_memslot(kvm, gfn); | |
faaaa53b JS |
1770 | if (!slot) { |
1771 | srcu_read_unlock(&kvm->srcu, idx); | |
1772 | return -EINVAL; | |
1773 | } | |
f30437c5 | 1774 | |
e36b250e | 1775 | write_lock(&kvm->mmu_lock); |
f30437c5 JS |
1776 | |
1777 | if (!kvmgt_gfn_is_write_protected(info, gfn)) | |
1778 | goto out; | |
1779 | ||
1780 | kvm_slot_page_track_remove_page(kvm, slot, gfn, KVM_PAGE_TRACK_WRITE); | |
1781 | kvmgt_protect_table_del(info, gfn); | |
1782 | ||
1783 | out: | |
e36b250e | 1784 | write_unlock(&kvm->mmu_lock); |
f30437c5 JS |
1785 | srcu_read_unlock(&kvm->srcu, idx); |
1786 | return 0; | |
1787 | } | |
1788 | ||
1789 | static void kvmgt_page_track_write(struct kvm_vcpu *vcpu, gpa_t gpa, | |
1790 | const u8 *val, int len, | |
1791 | struct kvm_page_track_notifier_node *node) | |
1792 | { | |
10ddb962 CH |
1793 | struct intel_vgpu *info = |
1794 | container_of(node, struct intel_vgpu, track_node); | |
f30437c5 JS |
1795 | |
1796 | if (kvmgt_gfn_is_write_protected(info, gpa_to_gfn(gpa))) | |
10ddb962 | 1797 | intel_vgpu_page_track_handler(info, gpa, |
4fafba2d | 1798 | (void *)val, len); |
f30437c5 JS |
1799 | } |
1800 | ||
1801 | static void kvmgt_page_track_flush_slot(struct kvm *kvm, | |
1802 | struct kvm_memory_slot *slot, | |
1803 | struct kvm_page_track_notifier_node *node) | |
1804 | { | |
1805 | int i; | |
1806 | gfn_t gfn; | |
10ddb962 CH |
1807 | struct intel_vgpu *info = |
1808 | container_of(node, struct intel_vgpu, track_node); | |
f30437c5 | 1809 | |
e36b250e | 1810 | write_lock(&kvm->mmu_lock); |
f30437c5 JS |
1811 | for (i = 0; i < slot->npages; i++) { |
1812 | gfn = slot->base_gfn + i; | |
1813 | if (kvmgt_gfn_is_write_protected(info, gfn)) { | |
1814 | kvm_slot_page_track_remove_page(kvm, slot, gfn, | |
1815 | KVM_PAGE_TRACK_WRITE); | |
1816 | kvmgt_protect_table_del(info, gfn); | |
1817 | } | |
1818 | } | |
e36b250e | 1819 | write_unlock(&kvm->mmu_lock); |
f30437c5 JS |
1820 | } |
1821 | ||
4c705ad0 | 1822 | void intel_vgpu_detach_regions(struct intel_vgpu *vgpu) |
f30437c5 | 1823 | { |
6c2d0f99 | 1824 | int i; |
6c2d0f99 | 1825 | |
62980cac | 1826 | if (!vgpu->region) |
6c2d0f99 HY |
1827 | return; |
1828 | ||
62980cac CH |
1829 | for (i = 0; i < vgpu->num_regions; i++) |
1830 | if (vgpu->region[i].ops->release) | |
1831 | vgpu->region[i].ops->release(vgpu, | |
1832 | &vgpu->region[i]); | |
1833 | vgpu->num_regions = 0; | |
1834 | kfree(vgpu->region); | |
1835 | vgpu->region = NULL; | |
f30437c5 JS |
1836 | } |
1837 | ||
8398eee8 | 1838 | int intel_gvt_dma_map_guest_page(struct intel_vgpu *vgpu, unsigned long gfn, |
79e542f5 | 1839 | unsigned long size, dma_addr_t *dma_addr) |
cf4ee73f | 1840 | { |
cf4ee73f CD |
1841 | struct gvt_dma *entry; |
1842 | int ret; | |
1843 | ||
3c340d05 | 1844 | if (!vgpu->attached) |
cf4ee73f CD |
1845 | return -EINVAL; |
1846 | ||
62980cac | 1847 | mutex_lock(&vgpu->cache_lock); |
cf4ee73f | 1848 | |
06d63c48 | 1849 | entry = __gvt_cache_find_gfn(vgpu, gfn); |
cf4ee73f | 1850 | if (!entry) { |
7366aeb7 XZ |
1851 | ret = gvt_dma_map_page(vgpu, gfn, dma_addr, size); |
1852 | if (ret) | |
1853 | goto err_unlock; | |
1854 | ||
06d63c48 | 1855 | ret = __gvt_cache_add(vgpu, gfn, *dma_addr, size); |
7366aeb7 XZ |
1856 | if (ret) |
1857 | goto err_unmap; | |
1858 | } else if (entry->size != size) { | |
1859 | /* the same gfn with different size: unmap and re-map */ | |
1860 | gvt_dma_unmap_page(vgpu, gfn, entry->dma_addr, entry->size); | |
1861 | __gvt_cache_remove_entry(vgpu, entry); | |
1862 | ||
79e542f5 | 1863 | ret = gvt_dma_map_page(vgpu, gfn, dma_addr, size); |
5cd4223e CD |
1864 | if (ret) |
1865 | goto err_unlock; | |
1866 | ||
06d63c48 | 1867 | ret = __gvt_cache_add(vgpu, gfn, *dma_addr, size); |
5cd4223e CD |
1868 | if (ret) |
1869 | goto err_unmap; | |
cf4ee73f CD |
1870 | } else { |
1871 | kref_get(&entry->ref); | |
1872 | *dma_addr = entry->dma_addr; | |
4a0b3444 | 1873 | } |
f30437c5 | 1874 | |
62980cac | 1875 | mutex_unlock(&vgpu->cache_lock); |
cf4ee73f | 1876 | return 0; |
5cd4223e CD |
1877 | |
1878 | err_unmap: | |
79e542f5 | 1879 | gvt_dma_unmap_page(vgpu, gfn, *dma_addr, size); |
5cd4223e | 1880 | err_unlock: |
62980cac | 1881 | mutex_unlock(&vgpu->cache_lock); |
5cd4223e | 1882 | return ret; |
cf4ee73f CD |
1883 | } |
1884 | ||
91879bba | 1885 | int intel_gvt_dma_pin_guest_page(struct intel_vgpu *vgpu, dma_addr_t dma_addr) |
9f674c81 | 1886 | { |
9f674c81 TZ |
1887 | struct gvt_dma *entry; |
1888 | int ret = 0; | |
1889 | ||
3c340d05 | 1890 | if (!vgpu->attached) |
9f674c81 TZ |
1891 | return -ENODEV; |
1892 | ||
10ddb962 CH |
1893 | mutex_lock(&vgpu->cache_lock); |
1894 | entry = __gvt_cache_find_dma_addr(vgpu, dma_addr); | |
9f674c81 TZ |
1895 | if (entry) |
1896 | kref_get(&entry->ref); | |
1897 | else | |
1898 | ret = -ENOMEM; | |
10ddb962 | 1899 | mutex_unlock(&vgpu->cache_lock); |
9f674c81 TZ |
1900 | |
1901 | return ret; | |
1902 | } | |
1903 | ||
cf4ee73f CD |
1904 | static void __gvt_dma_release(struct kref *ref) |
1905 | { | |
1906 | struct gvt_dma *entry = container_of(ref, typeof(*entry), ref); | |
1907 | ||
79e542f5 CD |
1908 | gvt_dma_unmap_page(entry->vgpu, entry->gfn, entry->dma_addr, |
1909 | entry->size); | |
cf4ee73f CD |
1910 | __gvt_cache_remove_entry(entry->vgpu, entry); |
1911 | } | |
1912 | ||
8398eee8 | 1913 | void intel_gvt_dma_unmap_guest_page(struct intel_vgpu *vgpu, |
3c340d05 | 1914 | dma_addr_t dma_addr) |
cf4ee73f | 1915 | { |
cf4ee73f CD |
1916 | struct gvt_dma *entry; |
1917 | ||
3c340d05 | 1918 | if (!vgpu->attached) |
cf4ee73f CD |
1919 | return; |
1920 | ||
62980cac | 1921 | mutex_lock(&vgpu->cache_lock); |
06d63c48 | 1922 | entry = __gvt_cache_find_dma_addr(vgpu, dma_addr); |
cf4ee73f CD |
1923 | if (entry) |
1924 | kref_put(&entry->ref, __gvt_dma_release); | |
62980cac | 1925 | mutex_unlock(&vgpu->cache_lock); |
f30437c5 JS |
1926 | } |
1927 | ||
cba619cb CH |
1928 | static void init_device_info(struct intel_gvt *gvt) |
1929 | { | |
1930 | struct intel_gvt_device_info *info = &gvt->device_info; | |
1931 | struct pci_dev *pdev = to_pci_dev(gvt->gt->i915->drm.dev); | |
1932 | ||
1933 | info->max_support_vgpus = 8; | |
1934 | info->cfg_space_size = PCI_CFG_SPACE_EXP_SIZE; | |
1935 | info->mmio_size = 2 * 1024 * 1024; | |
1936 | info->mmio_bar = 0; | |
1937 | info->gtt_start_offset = 8 * 1024 * 1024; | |
1938 | info->gtt_entry_size = 8; | |
1939 | info->gtt_entry_size_shift = 3; | |
1940 | info->gmadr_bytes_in_cmd = 8; | |
1941 | info->max_surface_size = 36 * 1024 * 1024; | |
1942 | info->msi_cap_offset = pdev->msi_cap; | |
1943 | } | |
1944 | ||
1945 | static void intel_gvt_test_and_emulate_vblank(struct intel_gvt *gvt) | |
1946 | { | |
1947 | struct intel_vgpu *vgpu; | |
1948 | int id; | |
1949 | ||
1950 | mutex_lock(&gvt->lock); | |
1951 | idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) { | |
1952 | if (test_and_clear_bit(INTEL_GVT_REQUEST_EMULATE_VBLANK + id, | |
1953 | (void *)&gvt->service_request)) { | |
1954 | if (vgpu->active) | |
1955 | intel_vgpu_emulate_vblank(vgpu); | |
1956 | } | |
1957 | } | |
1958 | mutex_unlock(&gvt->lock); | |
1959 | } | |
1960 | ||
1961 | static int gvt_service_thread(void *data) | |
1962 | { | |
1963 | struct intel_gvt *gvt = (struct intel_gvt *)data; | |
1964 | int ret; | |
1965 | ||
1966 | gvt_dbg_core("service thread start\n"); | |
1967 | ||
1968 | while (!kthread_should_stop()) { | |
1969 | ret = wait_event_interruptible(gvt->service_thread_wq, | |
1970 | kthread_should_stop() || gvt->service_request); | |
1971 | ||
1972 | if (kthread_should_stop()) | |
1973 | break; | |
1974 | ||
1975 | if (WARN_ONCE(ret, "service thread is waken up by signal.\n")) | |
1976 | continue; | |
1977 | ||
1978 | intel_gvt_test_and_emulate_vblank(gvt); | |
1979 | ||
1980 | if (test_bit(INTEL_GVT_REQUEST_SCHED, | |
1981 | (void *)&gvt->service_request) || | |
1982 | test_bit(INTEL_GVT_REQUEST_EVENT_SCHED, | |
1983 | (void *)&gvt->service_request)) { | |
1984 | intel_gvt_schedule(gvt); | |
1985 | } | |
1986 | } | |
1987 | ||
1988 | return 0; | |
1989 | } | |
1990 | ||
1991 | static void clean_service_thread(struct intel_gvt *gvt) | |
1992 | { | |
1993 | kthread_stop(gvt->service_thread); | |
1994 | } | |
1995 | ||
1996 | static int init_service_thread(struct intel_gvt *gvt) | |
1997 | { | |
1998 | init_waitqueue_head(&gvt->service_thread_wq); | |
1999 | ||
2000 | gvt->service_thread = kthread_run(gvt_service_thread, | |
2001 | gvt, "gvt_service_thread"); | |
2002 | if (IS_ERR(gvt->service_thread)) { | |
2003 | gvt_err("fail to start service thread.\n"); | |
2004 | return PTR_ERR(gvt->service_thread); | |
2005 | } | |
2006 | return 0; | |
2007 | } | |
2008 | ||
2009 | /** | |
2010 | * intel_gvt_clean_device - clean a GVT device | |
2011 | * @i915: i915 private | |
2012 | * | |
2013 | * This function is called at the driver unloading stage, to free the | |
2014 | * resources owned by a GVT device. | |
2015 | * | |
2016 | */ | |
2017 | static void intel_gvt_clean_device(struct drm_i915_private *i915) | |
2018 | { | |
2019 | struct intel_gvt *gvt = fetch_and_zero(&i915->gvt); | |
2020 | ||
2021 | if (drm_WARN_ON(&i915->drm, !gvt)) | |
2022 | return; | |
2023 | ||
2024 | mdev_unregister_device(i915->drm.dev); | |
2025 | intel_gvt_cleanup_vgpu_type_groups(gvt); | |
2026 | intel_gvt_destroy_idle_vgpu(gvt->idle_vgpu); | |
2027 | intel_gvt_clean_vgpu_types(gvt); | |
2028 | ||
2029 | intel_gvt_debugfs_clean(gvt); | |
2030 | clean_service_thread(gvt); | |
2031 | intel_gvt_clean_cmd_parser(gvt); | |
2032 | intel_gvt_clean_sched_policy(gvt); | |
2033 | intel_gvt_clean_workload_scheduler(gvt); | |
2034 | intel_gvt_clean_gtt(gvt); | |
2035 | intel_gvt_free_firmware(gvt); | |
2036 | intel_gvt_clean_mmio_info(gvt); | |
2037 | idr_destroy(&gvt->vgpu_idr); | |
2038 | ||
2039 | kfree(i915->gvt); | |
2040 | } | |
2041 | ||
2042 | /** | |
2043 | * intel_gvt_init_device - initialize a GVT device | |
2044 | * @i915: drm i915 private data | |
2045 | * | |
2046 | * This function is called at the initialization stage, to initialize | |
2047 | * necessary GVT components. | |
2048 | * | |
2049 | * Returns: | |
2050 | * Zero on success, negative error code if failed. | |
2051 | * | |
2052 | */ | |
2053 | static int intel_gvt_init_device(struct drm_i915_private *i915) | |
2054 | { | |
2055 | struct intel_gvt *gvt; | |
2056 | struct intel_vgpu *vgpu; | |
2057 | int ret; | |
2058 | ||
2059 | if (drm_WARN_ON(&i915->drm, i915->gvt)) | |
2060 | return -EEXIST; | |
2061 | ||
2062 | gvt = kzalloc(sizeof(struct intel_gvt), GFP_KERNEL); | |
2063 | if (!gvt) | |
2064 | return -ENOMEM; | |
2065 | ||
2066 | gvt_dbg_core("init gvt device\n"); | |
2067 | ||
2068 | idr_init_base(&gvt->vgpu_idr, 1); | |
2069 | spin_lock_init(&gvt->scheduler.mmio_context_lock); | |
2070 | mutex_init(&gvt->lock); | |
2071 | mutex_init(&gvt->sched_lock); | |
2072 | gvt->gt = to_gt(i915); | |
2073 | i915->gvt = gvt; | |
2074 | ||
2075 | init_device_info(gvt); | |
2076 | ||
2077 | ret = intel_gvt_setup_mmio_info(gvt); | |
2078 | if (ret) | |
2079 | goto out_clean_idr; | |
2080 | ||
2081 | intel_gvt_init_engine_mmio_context(gvt); | |
2082 | ||
2083 | ret = intel_gvt_load_firmware(gvt); | |
2084 | if (ret) | |
2085 | goto out_clean_mmio_info; | |
2086 | ||
2087 | ret = intel_gvt_init_irq(gvt); | |
2088 | if (ret) | |
2089 | goto out_free_firmware; | |
2090 | ||
2091 | ret = intel_gvt_init_gtt(gvt); | |
2092 | if (ret) | |
2093 | goto out_free_firmware; | |
2094 | ||
2095 | ret = intel_gvt_init_workload_scheduler(gvt); | |
2096 | if (ret) | |
2097 | goto out_clean_gtt; | |
2098 | ||
2099 | ret = intel_gvt_init_sched_policy(gvt); | |
2100 | if (ret) | |
2101 | goto out_clean_workload_scheduler; | |
2102 | ||
2103 | ret = intel_gvt_init_cmd_parser(gvt); | |
2104 | if (ret) | |
2105 | goto out_clean_sched_policy; | |
2106 | ||
2107 | ret = init_service_thread(gvt); | |
2108 | if (ret) | |
2109 | goto out_clean_cmd_parser; | |
2110 | ||
2111 | ret = intel_gvt_init_vgpu_types(gvt); | |
2112 | if (ret) | |
2113 | goto out_clean_thread; | |
2114 | ||
2115 | vgpu = intel_gvt_create_idle_vgpu(gvt); | |
2116 | if (IS_ERR(vgpu)) { | |
2117 | ret = PTR_ERR(vgpu); | |
2118 | gvt_err("failed to create idle vgpu\n"); | |
2119 | goto out_clean_types; | |
2120 | } | |
2121 | gvt->idle_vgpu = vgpu; | |
2122 | ||
2123 | intel_gvt_debugfs_init(gvt); | |
2124 | ||
2125 | ret = intel_gvt_init_vgpu_type_groups(gvt); | |
2126 | if (ret) | |
2127 | goto out_destroy_idle_vgpu; | |
2128 | ||
6b42f491 | 2129 | ret = mdev_register_device(i915->drm.dev, &intel_vgpu_mdev_driver); |
cba619cb CH |
2130 | if (ret) |
2131 | goto out_cleanup_vgpu_type_groups; | |
2132 | ||
2133 | gvt_dbg_core("gvt device initialization is done\n"); | |
2134 | return 0; | |
2135 | ||
2136 | out_cleanup_vgpu_type_groups: | |
2137 | intel_gvt_cleanup_vgpu_type_groups(gvt); | |
2138 | out_destroy_idle_vgpu: | |
2139 | intel_gvt_destroy_idle_vgpu(gvt->idle_vgpu); | |
2140 | intel_gvt_debugfs_clean(gvt); | |
2141 | out_clean_types: | |
2142 | intel_gvt_clean_vgpu_types(gvt); | |
2143 | out_clean_thread: | |
2144 | clean_service_thread(gvt); | |
2145 | out_clean_cmd_parser: | |
2146 | intel_gvt_clean_cmd_parser(gvt); | |
2147 | out_clean_sched_policy: | |
2148 | intel_gvt_clean_sched_policy(gvt); | |
2149 | out_clean_workload_scheduler: | |
2150 | intel_gvt_clean_workload_scheduler(gvt); | |
2151 | out_clean_gtt: | |
2152 | intel_gvt_clean_gtt(gvt); | |
2153 | out_free_firmware: | |
2154 | intel_gvt_free_firmware(gvt); | |
2155 | out_clean_mmio_info: | |
2156 | intel_gvt_clean_mmio_info(gvt); | |
2157 | out_clean_idr: | |
2158 | idr_destroy(&gvt->vgpu_idr); | |
2159 | kfree(gvt); | |
2160 | i915->gvt = NULL; | |
2161 | return ret; | |
2162 | } | |
2163 | ||
2164 | static void intel_gvt_pm_resume(struct drm_i915_private *i915) | |
2165 | { | |
2166 | struct intel_gvt *gvt = i915->gvt; | |
2167 | ||
2168 | intel_gvt_restore_fence(gvt); | |
2169 | intel_gvt_restore_mmio(gvt); | |
2170 | intel_gvt_restore_ggtt(gvt); | |
2171 | } | |
2172 | ||
2173 | static const struct intel_vgpu_ops intel_gvt_vgpu_ops = { | |
2174 | .init_device = intel_gvt_init_device, | |
2175 | .clean_device = intel_gvt_clean_device, | |
2176 | .pm_resume = intel_gvt_pm_resume, | |
2177 | }; | |
2178 | ||
f30437c5 JS |
2179 | static int __init kvmgt_init(void) |
2180 | { | |
978cf586 CH |
2181 | int ret; |
2182 | ||
2183 | ret = intel_gvt_set_ops(&intel_gvt_vgpu_ops); | |
2184 | if (ret) | |
2185 | return ret; | |
2186 | ||
2187 | ret = mdev_register_driver(&intel_vgpu_mdev_driver); | |
2188 | if (ret) | |
2189 | intel_gvt_clear_ops(&intel_gvt_vgpu_ops); | |
2190 | return ret; | |
f30437c5 JS |
2191 | } |
2192 | ||
2193 | static void __exit kvmgt_exit(void) | |
2194 | { | |
978cf586 | 2195 | mdev_unregister_driver(&intel_vgpu_mdev_driver); |
8b750bf7 | 2196 | intel_gvt_clear_ops(&intel_gvt_vgpu_ops); |
f30437c5 JS |
2197 | } |
2198 | ||
2199 | module_init(kvmgt_init); | |
2200 | module_exit(kvmgt_exit); | |
2201 | ||
2202 | MODULE_LICENSE("GPL and additional rights"); | |
2203 | MODULE_AUTHOR("Intel Corporation"); |