Commit | Line | Data |
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f30437c5 JS |
1 | /* |
2 | * KVMGT - the implementation of Intel mediated pass-through framework for KVM | |
3 | * | |
cba619cb | 4 | * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. |
f30437c5 JS |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
23 | * SOFTWARE. | |
24 | * | |
25 | * Authors: | |
26 | * Kevin Tian <kevin.tian@intel.com> | |
27 | * Jike Song <jike.song@intel.com> | |
28 | * Xiaoguang Chen <xiaoguang.chen@intel.com> | |
cba619cb CH |
29 | * Eddie Dong <eddie.dong@intel.com> |
30 | * | |
31 | * Contributors: | |
32 | * Niu Bing <bing.niu@intel.com> | |
33 | * Zhi Wang <zhi.a.wang@intel.com> | |
f30437c5 JS |
34 | */ |
35 | ||
36 | #include <linux/init.h> | |
f30437c5 | 37 | #include <linux/mm.h> |
9bf5b9eb | 38 | #include <linux/kthread.h> |
0a1b60d7 | 39 | #include <linux/sched/mm.h> |
f30437c5 JS |
40 | #include <linux/types.h> |
41 | #include <linux/list.h> | |
42 | #include <linux/rbtree.h> | |
43 | #include <linux/spinlock.h> | |
44 | #include <linux/eventfd.h> | |
659643f7 | 45 | #include <linux/mdev.h> |
6846dfeb | 46 | #include <linux/debugfs.h> |
f30437c5 | 47 | |
de5372da GS |
48 | #include <linux/nospec.h> |
49 | ||
a4c260de JN |
50 | #include <drm/drm_edid.h> |
51 | ||
f30437c5 | 52 | #include "i915_drv.h" |
8b750bf7 | 53 | #include "intel_gvt.h" |
f30437c5 JS |
54 | #include "gvt.h" |
55 | ||
8b750bf7 CH |
56 | MODULE_IMPORT_NS(DMA_BUF); |
57 | MODULE_IMPORT_NS(I915_GVT); | |
58 | ||
f30437c5 JS |
59 | /* helper macros copied from vfio-pci */ |
60 | #define VFIO_PCI_OFFSET_SHIFT 40 | |
61 | #define VFIO_PCI_OFFSET_TO_INDEX(off) (off >> VFIO_PCI_OFFSET_SHIFT) | |
62 | #define VFIO_PCI_INDEX_TO_OFFSET(index) ((u64)(index) << VFIO_PCI_OFFSET_SHIFT) | |
63 | #define VFIO_PCI_OFFSET_MASK (((u64)(1) << VFIO_PCI_OFFSET_SHIFT) - 1) | |
64 | ||
39c68e87 HY |
65 | #define EDID_BLOB_OFFSET (PAGE_SIZE/2) |
66 | ||
b851adea TZ |
67 | #define OPREGION_SIGNATURE "IntelGraphicsMem" |
68 | ||
69 | struct vfio_region; | |
70 | struct intel_vgpu_regops { | |
71 | size_t (*rw)(struct intel_vgpu *vgpu, char *buf, | |
72 | size_t count, loff_t *ppos, bool iswrite); | |
73 | void (*release)(struct intel_vgpu *vgpu, | |
74 | struct vfio_region *region); | |
75 | }; | |
76 | ||
f30437c5 JS |
77 | struct vfio_region { |
78 | u32 type; | |
79 | u32 subtype; | |
80 | size_t size; | |
81 | u32 flags; | |
b851adea TZ |
82 | const struct intel_vgpu_regops *ops; |
83 | void *data; | |
f30437c5 JS |
84 | }; |
85 | ||
39c68e87 HY |
86 | struct vfio_edid_region { |
87 | struct vfio_region_gfx_edid vfio_edid_regs; | |
88 | void *edid_blob; | |
89 | }; | |
90 | ||
f30437c5 JS |
91 | struct kvmgt_pgfn { |
92 | gfn_t gfn; | |
93 | struct hlist_node hnode; | |
94 | }; | |
95 | ||
f30437c5 | 96 | struct gvt_dma { |
cf4ee73f CD |
97 | struct intel_vgpu *vgpu; |
98 | struct rb_node gfn_node; | |
99 | struct rb_node dma_addr_node; | |
f30437c5 | 100 | gfn_t gfn; |
cf4ee73f | 101 | dma_addr_t dma_addr; |
79e542f5 | 102 | unsigned long size; |
cf4ee73f | 103 | struct kref ref; |
f30437c5 JS |
104 | }; |
105 | ||
978cf586 CH |
106 | #define vfio_dev_to_vgpu(vfio_dev) \ |
107 | container_of((vfio_dev), struct intel_vgpu, vfio_device) | |
108 | ||
b271e17d SC |
109 | static void kvmgt_page_track_write(gpa_t gpa, const u8 *val, int len, |
110 | struct kvm_page_track_notifier_node *node); | |
c15fcf12 YZ |
111 | static void kvmgt_page_track_remove_region(gfn_t gfn, unsigned long nr_pages, |
112 | struct kvm_page_track_notifier_node *node); | |
0e09f406 | 113 | |
685a1537 | 114 | static ssize_t intel_vgpu_show_description(struct mdev_type *mtype, char *buf) |
145e06b5 | 115 | { |
da44c340 CH |
116 | struct intel_vgpu_type *type = |
117 | container_of(mtype, struct intel_vgpu_type, type); | |
145e06b5 ZW |
118 | |
119 | return sprintf(buf, "low_gm_size: %dMB\nhigh_gm_size: %dMB\n" | |
120 | "fence: %d\nresolution: %s\n" | |
121 | "weight: %d\n", | |
1aa3834f CH |
122 | BYTES_TO_MB(type->conf->low_mm), |
123 | BYTES_TO_MB(type->conf->high_mm), | |
124 | type->conf->fence, vgpu_edid_str(type->conf->edid), | |
125 | type->conf->weight); | |
145e06b5 ZW |
126 | } |
127 | ||
79e542f5 CD |
128 | static void gvt_unpin_guest_page(struct intel_vgpu *vgpu, unsigned long gfn, |
129 | unsigned long size) | |
130 | { | |
44abdd16 NC |
131 | vfio_unpin_pages(&vgpu->vfio_device, gfn << PAGE_SHIFT, |
132 | DIV_ROUND_UP(size, PAGE_SIZE)); | |
79e542f5 CD |
133 | } |
134 | ||
135 | /* Pin a normal or compound guest page for dma. */ | |
136 | static int gvt_pin_guest_page(struct intel_vgpu *vgpu, unsigned long gfn, | |
137 | unsigned long size, struct page **page) | |
138 | { | |
2c9e8c01 | 139 | int total_pages = DIV_ROUND_UP(size, PAGE_SIZE); |
34a255e6 | 140 | struct page *base_page = NULL; |
79e542f5 CD |
141 | int npage; |
142 | int ret; | |
143 | ||
79e542f5 CD |
144 | /* |
145 | * We pin the pages one-by-one to avoid allocating a big arrary | |
146 | * on stack to hold pfns. | |
147 | */ | |
148 | for (npage = 0; npage < total_pages; npage++) { | |
44abdd16 | 149 | dma_addr_t cur_iova = (gfn + npage) << PAGE_SHIFT; |
34a255e6 | 150 | struct page *cur_page; |
79e542f5 | 151 | |
44abdd16 | 152 | ret = vfio_pin_pages(&vgpu->vfio_device, cur_iova, 1, |
34a255e6 | 153 | IOMMU_READ | IOMMU_WRITE, &cur_page); |
79e542f5 | 154 | if (ret != 1) { |
44abdd16 NC |
155 | gvt_vgpu_err("vfio_pin_pages failed for iova %pad, ret %d\n", |
156 | &cur_iova, ret); | |
79e542f5 CD |
157 | goto err; |
158 | } | |
159 | ||
79e542f5 | 160 | if (npage == 0) |
34a255e6 | 161 | base_page = cur_page; |
adc7b226 | 162 | else if (page_to_pfn(base_page) + npage != page_to_pfn(cur_page)) { |
79e542f5 CD |
163 | ret = -EINVAL; |
164 | npage++; | |
165 | goto err; | |
166 | } | |
167 | } | |
168 | ||
34a255e6 | 169 | *page = base_page; |
79e542f5 CD |
170 | return 0; |
171 | err: | |
a15e61f3 YZ |
172 | if (npage) |
173 | gvt_unpin_guest_page(vgpu, gfn, npage * PAGE_SIZE); | |
79e542f5 CD |
174 | return ret; |
175 | } | |
176 | ||
cf4ee73f | 177 | static int gvt_dma_map_page(struct intel_vgpu *vgpu, unsigned long gfn, |
79e542f5 | 178 | dma_addr_t *dma_addr, unsigned long size) |
b86dc6ed | 179 | { |
9ff06c38 | 180 | struct device *dev = vgpu->gvt->gt->i915->drm.dev; |
79e542f5 | 181 | struct page *page = NULL; |
cf4ee73f | 182 | int ret; |
b86dc6ed | 183 | |
79e542f5 CD |
184 | ret = gvt_pin_guest_page(vgpu, gfn, size, &page); |
185 | if (ret) | |
186 | return ret; | |
b86dc6ed | 187 | |
cf4ee73f | 188 | /* Setup DMA mapping. */ |
c4f61203 | 189 | *dma_addr = dma_map_page(dev, page, 0, size, DMA_BIDIRECTIONAL); |
13bdff33 | 190 | if (dma_mapping_error(dev, *dma_addr)) { |
79e542f5 CD |
191 | gvt_vgpu_err("DMA mapping failed for pfn 0x%lx, ret %d\n", |
192 | page_to_pfn(page), ret); | |
193 | gvt_unpin_guest_page(vgpu, gfn, size); | |
13bdff33 | 194 | return -ENOMEM; |
cf4ee73f | 195 | } |
b86dc6ed | 196 | |
13bdff33 | 197 | return 0; |
b86dc6ed CD |
198 | } |
199 | ||
cf4ee73f | 200 | static void gvt_dma_unmap_page(struct intel_vgpu *vgpu, unsigned long gfn, |
79e542f5 | 201 | dma_addr_t dma_addr, unsigned long size) |
b86dc6ed | 202 | { |
9ff06c38 | 203 | struct device *dev = vgpu->gvt->gt->i915->drm.dev; |
b86dc6ed | 204 | |
c4f61203 | 205 | dma_unmap_page(dev, dma_addr, size, DMA_BIDIRECTIONAL); |
79e542f5 | 206 | gvt_unpin_guest_page(vgpu, gfn, size); |
b86dc6ed CD |
207 | } |
208 | ||
cf4ee73f CD |
209 | static struct gvt_dma *__gvt_cache_find_dma_addr(struct intel_vgpu *vgpu, |
210 | dma_addr_t dma_addr) | |
f30437c5 | 211 | { |
62980cac | 212 | struct rb_node *node = vgpu->dma_addr_cache.rb_node; |
cf4ee73f | 213 | struct gvt_dma *itr; |
f30437c5 JS |
214 | |
215 | while (node) { | |
cf4ee73f | 216 | itr = rb_entry(node, struct gvt_dma, dma_addr_node); |
f30437c5 | 217 | |
cf4ee73f | 218 | if (dma_addr < itr->dma_addr) |
f30437c5 | 219 | node = node->rb_left; |
cf4ee73f | 220 | else if (dma_addr > itr->dma_addr) |
f30437c5 | 221 | node = node->rb_right; |
cf4ee73f CD |
222 | else |
223 | return itr; | |
f30437c5 | 224 | } |
cf4ee73f | 225 | return NULL; |
f30437c5 JS |
226 | } |
227 | ||
cf4ee73f | 228 | static struct gvt_dma *__gvt_cache_find_gfn(struct intel_vgpu *vgpu, gfn_t gfn) |
f30437c5 | 229 | { |
62980cac | 230 | struct rb_node *node = vgpu->gfn_cache.rb_node; |
cf4ee73f | 231 | struct gvt_dma *itr; |
f30437c5 | 232 | |
cf4ee73f CD |
233 | while (node) { |
234 | itr = rb_entry(node, struct gvt_dma, gfn_node); | |
f30437c5 | 235 | |
cf4ee73f CD |
236 | if (gfn < itr->gfn) |
237 | node = node->rb_left; | |
238 | else if (gfn > itr->gfn) | |
239 | node = node->rb_right; | |
240 | else | |
241 | return itr; | |
242 | } | |
243 | return NULL; | |
f30437c5 JS |
244 | } |
245 | ||
5cd4223e | 246 | static int __gvt_cache_add(struct intel_vgpu *vgpu, gfn_t gfn, |
79e542f5 | 247 | dma_addr_t dma_addr, unsigned long size) |
f30437c5 JS |
248 | { |
249 | struct gvt_dma *new, *itr; | |
cf4ee73f | 250 | struct rb_node **link, *parent = NULL; |
f30437c5 JS |
251 | |
252 | new = kzalloc(sizeof(struct gvt_dma), GFP_KERNEL); | |
253 | if (!new) | |
5cd4223e | 254 | return -ENOMEM; |
f30437c5 | 255 | |
cf4ee73f | 256 | new->vgpu = vgpu; |
f30437c5 | 257 | new->gfn = gfn; |
cf4ee73f | 258 | new->dma_addr = dma_addr; |
79e542f5 | 259 | new->size = size; |
cf4ee73f | 260 | kref_init(&new->ref); |
f30437c5 | 261 | |
cf4ee73f | 262 | /* gfn_cache maps gfn to struct gvt_dma. */ |
62980cac | 263 | link = &vgpu->gfn_cache.rb_node; |
f30437c5 JS |
264 | while (*link) { |
265 | parent = *link; | |
cf4ee73f | 266 | itr = rb_entry(parent, struct gvt_dma, gfn_node); |
f30437c5 | 267 | |
cf4ee73f | 268 | if (gfn < itr->gfn) |
f30437c5 JS |
269 | link = &parent->rb_left; |
270 | else | |
271 | link = &parent->rb_right; | |
272 | } | |
cf4ee73f | 273 | rb_link_node(&new->gfn_node, parent, link); |
62980cac | 274 | rb_insert_color(&new->gfn_node, &vgpu->gfn_cache); |
f30437c5 | 275 | |
cf4ee73f CD |
276 | /* dma_addr_cache maps dma addr to struct gvt_dma. */ |
277 | parent = NULL; | |
62980cac | 278 | link = &vgpu->dma_addr_cache.rb_node; |
cf4ee73f CD |
279 | while (*link) { |
280 | parent = *link; | |
281 | itr = rb_entry(parent, struct gvt_dma, dma_addr_node); | |
f30437c5 | 282 | |
cf4ee73f CD |
283 | if (dma_addr < itr->dma_addr) |
284 | link = &parent->rb_left; | |
285 | else | |
286 | link = &parent->rb_right; | |
287 | } | |
288 | rb_link_node(&new->dma_addr_node, parent, link); | |
62980cac | 289 | rb_insert_color(&new->dma_addr_node, &vgpu->dma_addr_cache); |
6846dfeb | 290 | |
62980cac | 291 | vgpu->nr_cache_entries++; |
5cd4223e | 292 | return 0; |
f30437c5 JS |
293 | } |
294 | ||
295 | static void __gvt_cache_remove_entry(struct intel_vgpu *vgpu, | |
296 | struct gvt_dma *entry) | |
297 | { | |
62980cac CH |
298 | rb_erase(&entry->gfn_node, &vgpu->gfn_cache); |
299 | rb_erase(&entry->dma_addr_node, &vgpu->dma_addr_cache); | |
f30437c5 | 300 | kfree(entry); |
62980cac | 301 | vgpu->nr_cache_entries--; |
f30437c5 JS |
302 | } |
303 | ||
f30437c5 JS |
304 | static void gvt_cache_destroy(struct intel_vgpu *vgpu) |
305 | { | |
306 | struct gvt_dma *dma; | |
307 | struct rb_node *node = NULL; | |
f30437c5 | 308 | |
f16bd3dd | 309 | for (;;) { |
62980cac CH |
310 | mutex_lock(&vgpu->cache_lock); |
311 | node = rb_first(&vgpu->gfn_cache); | |
f16bd3dd | 312 | if (!node) { |
62980cac | 313 | mutex_unlock(&vgpu->cache_lock); |
f16bd3dd CD |
314 | break; |
315 | } | |
cf4ee73f | 316 | dma = rb_entry(node, struct gvt_dma, gfn_node); |
79e542f5 | 317 | gvt_dma_unmap_page(vgpu, dma->gfn, dma->dma_addr, dma->size); |
f30437c5 | 318 | __gvt_cache_remove_entry(vgpu, dma); |
62980cac | 319 | mutex_unlock(&vgpu->cache_lock); |
f30437c5 | 320 | } |
f30437c5 JS |
321 | } |
322 | ||
cf4ee73f CD |
323 | static void gvt_cache_init(struct intel_vgpu *vgpu) |
324 | { | |
62980cac CH |
325 | vgpu->gfn_cache = RB_ROOT; |
326 | vgpu->dma_addr_cache = RB_ROOT; | |
327 | vgpu->nr_cache_entries = 0; | |
328 | mutex_init(&vgpu->cache_lock); | |
cf4ee73f CD |
329 | } |
330 | ||
10ddb962 | 331 | static void kvmgt_protect_table_init(struct intel_vgpu *info) |
f30437c5 JS |
332 | { |
333 | hash_init(info->ptable); | |
334 | } | |
335 | ||
10ddb962 | 336 | static void kvmgt_protect_table_destroy(struct intel_vgpu *info) |
f30437c5 JS |
337 | { |
338 | struct kvmgt_pgfn *p; | |
339 | struct hlist_node *tmp; | |
340 | int i; | |
341 | ||
342 | hash_for_each_safe(info->ptable, i, tmp, p, hnode) { | |
343 | hash_del(&p->hnode); | |
344 | kfree(p); | |
345 | } | |
346 | } | |
347 | ||
348 | static struct kvmgt_pgfn * | |
10ddb962 | 349 | __kvmgt_protect_table_find(struct intel_vgpu *info, gfn_t gfn) |
f30437c5 JS |
350 | { |
351 | struct kvmgt_pgfn *p, *res = NULL; | |
352 | ||
3cca6b26 SC |
353 | lockdep_assert_held(&info->vgpu_lock); |
354 | ||
f30437c5 JS |
355 | hash_for_each_possible(info->ptable, p, hnode, gfn) { |
356 | if (gfn == p->gfn) { | |
357 | res = p; | |
358 | break; | |
359 | } | |
360 | } | |
361 | ||
362 | return res; | |
363 | } | |
364 | ||
10ddb962 | 365 | static bool kvmgt_gfn_is_write_protected(struct intel_vgpu *info, gfn_t gfn) |
f30437c5 JS |
366 | { |
367 | struct kvmgt_pgfn *p; | |
368 | ||
369 | p = __kvmgt_protect_table_find(info, gfn); | |
370 | return !!p; | |
371 | } | |
372 | ||
10ddb962 | 373 | static void kvmgt_protect_table_add(struct intel_vgpu *info, gfn_t gfn) |
f30437c5 JS |
374 | { |
375 | struct kvmgt_pgfn *p; | |
376 | ||
377 | if (kvmgt_gfn_is_write_protected(info, gfn)) | |
378 | return; | |
379 | ||
c55b1de0 | 380 | p = kzalloc(sizeof(struct kvmgt_pgfn), GFP_ATOMIC); |
f30437c5 JS |
381 | if (WARN(!p, "gfn: 0x%llx\n", gfn)) |
382 | return; | |
383 | ||
384 | p->gfn = gfn; | |
385 | hash_add(info->ptable, &p->hnode, gfn); | |
386 | } | |
387 | ||
10ddb962 | 388 | static void kvmgt_protect_table_del(struct intel_vgpu *info, gfn_t gfn) |
f30437c5 JS |
389 | { |
390 | struct kvmgt_pgfn *p; | |
391 | ||
392 | p = __kvmgt_protect_table_find(info, gfn); | |
393 | if (p) { | |
394 | hash_del(&p->hnode); | |
395 | kfree(p); | |
396 | } | |
397 | } | |
398 | ||
b851adea TZ |
399 | static size_t intel_vgpu_reg_rw_opregion(struct intel_vgpu *vgpu, char *buf, |
400 | size_t count, loff_t *ppos, bool iswrite) | |
401 | { | |
402 | unsigned int i = VFIO_PCI_OFFSET_TO_INDEX(*ppos) - | |
403 | VFIO_PCI_NUM_REGIONS; | |
62980cac | 404 | void *base = vgpu->region[i].data; |
b851adea TZ |
405 | loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK; |
406 | ||
06d63c48 | 407 | |
62980cac | 408 | if (pos >= vgpu->region[i].size || iswrite) { |
b851adea TZ |
409 | gvt_vgpu_err("invalid op or offset for Intel vgpu OpRegion\n"); |
410 | return -EINVAL; | |
411 | } | |
62980cac | 412 | count = min(count, (size_t)(vgpu->region[i].size - pos)); |
b851adea TZ |
413 | memcpy(buf, base + pos, count); |
414 | ||
415 | return count; | |
416 | } | |
417 | ||
418 | static void intel_vgpu_reg_release_opregion(struct intel_vgpu *vgpu, | |
419 | struct vfio_region *region) | |
420 | { | |
421 | } | |
422 | ||
423 | static const struct intel_vgpu_regops intel_vgpu_regops_opregion = { | |
424 | .rw = intel_vgpu_reg_rw_opregion, | |
425 | .release = intel_vgpu_reg_release_opregion, | |
426 | }; | |
427 | ||
39c68e87 HY |
428 | static int handle_edid_regs(struct intel_vgpu *vgpu, |
429 | struct vfio_edid_region *region, char *buf, | |
430 | size_t count, u16 offset, bool is_write) | |
431 | { | |
432 | struct vfio_region_gfx_edid *regs = ®ion->vfio_edid_regs; | |
433 | unsigned int data; | |
434 | ||
435 | if (offset + count > sizeof(*regs)) | |
436 | return -EINVAL; | |
437 | ||
438 | if (count != 4) | |
439 | return -EINVAL; | |
440 | ||
441 | if (is_write) { | |
442 | data = *((unsigned int *)buf); | |
443 | switch (offset) { | |
444 | case offsetof(struct vfio_region_gfx_edid, link_state): | |
445 | if (data == VFIO_DEVICE_GFX_LINK_STATE_UP) { | |
446 | if (!drm_edid_block_valid( | |
447 | (u8 *)region->edid_blob, | |
448 | 0, | |
449 | true, | |
450 | NULL)) { | |
451 | gvt_vgpu_err("invalid EDID blob\n"); | |
452 | return -EINVAL; | |
453 | } | |
675e5c4a | 454 | intel_vgpu_emulate_hotplug(vgpu, true); |
39c68e87 | 455 | } else if (data == VFIO_DEVICE_GFX_LINK_STATE_DOWN) |
675e5c4a | 456 | intel_vgpu_emulate_hotplug(vgpu, false); |
39c68e87 HY |
457 | else { |
458 | gvt_vgpu_err("invalid EDID link state %d\n", | |
459 | regs->link_state); | |
460 | return -EINVAL; | |
461 | } | |
462 | regs->link_state = data; | |
463 | break; | |
464 | case offsetof(struct vfio_region_gfx_edid, edid_size): | |
465 | if (data > regs->edid_max_size) { | |
466 | gvt_vgpu_err("EDID size is bigger than %d!\n", | |
467 | regs->edid_max_size); | |
468 | return -EINVAL; | |
469 | } | |
470 | regs->edid_size = data; | |
471 | break; | |
472 | default: | |
473 | /* read-only regs */ | |
474 | gvt_vgpu_err("write read-only EDID region at offset %d\n", | |
475 | offset); | |
476 | return -EPERM; | |
477 | } | |
478 | } else { | |
479 | memcpy(buf, (char *)regs + offset, count); | |
480 | } | |
481 | ||
482 | return count; | |
483 | } | |
484 | ||
485 | static int handle_edid_blob(struct vfio_edid_region *region, char *buf, | |
486 | size_t count, u16 offset, bool is_write) | |
487 | { | |
488 | if (offset + count > region->vfio_edid_regs.edid_size) | |
489 | return -EINVAL; | |
490 | ||
491 | if (is_write) | |
492 | memcpy(region->edid_blob + offset, buf, count); | |
493 | else | |
494 | memcpy(buf, region->edid_blob + offset, count); | |
495 | ||
496 | return count; | |
497 | } | |
498 | ||
499 | static size_t intel_vgpu_reg_rw_edid(struct intel_vgpu *vgpu, char *buf, | |
500 | size_t count, loff_t *ppos, bool iswrite) | |
501 | { | |
502 | int ret; | |
503 | unsigned int i = VFIO_PCI_OFFSET_TO_INDEX(*ppos) - | |
504 | VFIO_PCI_NUM_REGIONS; | |
62980cac | 505 | struct vfio_edid_region *region = vgpu->region[i].data; |
39c68e87 HY |
506 | loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK; |
507 | ||
508 | if (pos < region->vfio_edid_regs.edid_offset) { | |
509 | ret = handle_edid_regs(vgpu, region, buf, count, pos, iswrite); | |
510 | } else { | |
511 | pos -= EDID_BLOB_OFFSET; | |
512 | ret = handle_edid_blob(region, buf, count, pos, iswrite); | |
513 | } | |
514 | ||
515 | if (ret < 0) | |
516 | gvt_vgpu_err("failed to access EDID region\n"); | |
517 | ||
518 | return ret; | |
519 | } | |
520 | ||
521 | static void intel_vgpu_reg_release_edid(struct intel_vgpu *vgpu, | |
522 | struct vfio_region *region) | |
523 | { | |
524 | kfree(region->data); | |
525 | } | |
526 | ||
527 | static const struct intel_vgpu_regops intel_vgpu_regops_edid = { | |
528 | .rw = intel_vgpu_reg_rw_edid, | |
529 | .release = intel_vgpu_reg_release_edid, | |
530 | }; | |
531 | ||
b851adea TZ |
532 | static int intel_vgpu_register_reg(struct intel_vgpu *vgpu, |
533 | unsigned int type, unsigned int subtype, | |
534 | const struct intel_vgpu_regops *ops, | |
535 | size_t size, u32 flags, void *data) | |
536 | { | |
537 | struct vfio_region *region; | |
538 | ||
62980cac CH |
539 | region = krealloc(vgpu->region, |
540 | (vgpu->num_regions + 1) * sizeof(*region), | |
b851adea TZ |
541 | GFP_KERNEL); |
542 | if (!region) | |
543 | return -ENOMEM; | |
544 | ||
62980cac CH |
545 | vgpu->region = region; |
546 | vgpu->region[vgpu->num_regions].type = type; | |
547 | vgpu->region[vgpu->num_regions].subtype = subtype; | |
548 | vgpu->region[vgpu->num_regions].ops = ops; | |
549 | vgpu->region[vgpu->num_regions].size = size; | |
550 | vgpu->region[vgpu->num_regions].flags = flags; | |
551 | vgpu->region[vgpu->num_regions].data = data; | |
552 | vgpu->num_regions++; | |
e546e281 TZ |
553 | return 0; |
554 | } | |
555 | ||
f9399b0e | 556 | int intel_gvt_set_opregion(struct intel_vgpu *vgpu) |
b851adea | 557 | { |
b851adea TZ |
558 | void *base; |
559 | int ret; | |
560 | ||
561 | /* Each vgpu has its own opregion, although VFIO would create another | |
562 | * one later. This one is used to expose opregion to VFIO. And the | |
563 | * other one created by VFIO later, is used by guest actually. | |
564 | */ | |
565 | base = vgpu_opregion(vgpu)->va; | |
566 | if (!base) | |
567 | return -ENOMEM; | |
568 | ||
569 | if (memcmp(base, OPREGION_SIGNATURE, 16)) { | |
570 | memunmap(base); | |
571 | return -EINVAL; | |
572 | } | |
573 | ||
574 | ret = intel_vgpu_register_reg(vgpu, | |
575 | PCI_VENDOR_ID_INTEL | VFIO_REGION_TYPE_PCI_VENDOR_TYPE, | |
576 | VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION, | |
2619861c | 577 | &intel_vgpu_regops_opregion, INTEL_GVT_OPREGION_SIZE, |
b851adea TZ |
578 | VFIO_REGION_INFO_FLAG_READ, base); |
579 | ||
580 | return ret; | |
581 | } | |
582 | ||
f9399b0e | 583 | int intel_gvt_set_edid(struct intel_vgpu *vgpu, int port_num) |
39c68e87 | 584 | { |
39c68e87 HY |
585 | struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); |
586 | struct vfio_edid_region *base; | |
587 | int ret; | |
588 | ||
589 | base = kzalloc(sizeof(*base), GFP_KERNEL); | |
590 | if (!base) | |
591 | return -ENOMEM; | |
592 | ||
593 | /* TODO: Add multi-port and EDID extension block support */ | |
594 | base->vfio_edid_regs.edid_offset = EDID_BLOB_OFFSET; | |
595 | base->vfio_edid_regs.edid_max_size = EDID_SIZE; | |
596 | base->vfio_edid_regs.edid_size = EDID_SIZE; | |
597 | base->vfio_edid_regs.max_xres = vgpu_edid_xres(port->id); | |
598 | base->vfio_edid_regs.max_yres = vgpu_edid_yres(port->id); | |
599 | base->edid_blob = port->edid->edid_block; | |
600 | ||
601 | ret = intel_vgpu_register_reg(vgpu, | |
602 | VFIO_REGION_TYPE_GFX, | |
603 | VFIO_REGION_SUBTYPE_GFX_EDID, | |
604 | &intel_vgpu_regops_edid, EDID_SIZE, | |
605 | VFIO_REGION_INFO_FLAG_READ | | |
606 | VFIO_REGION_INFO_FLAG_WRITE | | |
607 | VFIO_REGION_INFO_FLAG_CAPS, base); | |
608 | ||
609 | return ret; | |
610 | } | |
611 | ||
ce4b4657 JG |
612 | static void intel_vgpu_dma_unmap(struct vfio_device *vfio_dev, u64 iova, |
613 | u64 length) | |
659643f7 | 614 | { |
ce4b4657 JG |
615 | struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); |
616 | struct gvt_dma *entry; | |
617 | u64 iov_pfn = iova >> PAGE_SHIFT; | |
618 | u64 end_iov_pfn = iov_pfn + length / PAGE_SIZE; | |
619 | ||
620 | mutex_lock(&vgpu->cache_lock); | |
621 | for (; iov_pfn < end_iov_pfn; iov_pfn++) { | |
622 | entry = __gvt_cache_find_gfn(vgpu, iov_pfn); | |
623 | if (!entry) | |
624 | continue; | |
659643f7 | 625 | |
ce4b4657 JG |
626 | gvt_dma_unmap_page(vgpu, entry->gfn, entry->dma_addr, |
627 | entry->size); | |
628 | __gvt_cache_remove_entry(vgpu, entry); | |
659643f7 | 629 | } |
ce4b4657 | 630 | mutex_unlock(&vgpu->cache_lock); |
659643f7 JS |
631 | } |
632 | ||
0e09f406 CH |
633 | static bool __kvmgt_vgpu_exist(struct intel_vgpu *vgpu) |
634 | { | |
635 | struct intel_vgpu *itr; | |
636 | int id; | |
637 | bool ret = false; | |
638 | ||
639 | mutex_lock(&vgpu->gvt->lock); | |
640 | for_each_active_vgpu(vgpu->gvt, itr, id) { | |
a06d4b9e | 641 | if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, itr->status)) |
0e09f406 CH |
642 | continue; |
643 | ||
421cfe65 | 644 | if (vgpu->vfio_device.kvm == itr->vfio_device.kvm) { |
0e09f406 CH |
645 | ret = true; |
646 | goto out; | |
647 | } | |
648 | } | |
649 | out: | |
650 | mutex_unlock(&vgpu->gvt->lock); | |
651 | return ret; | |
652 | } | |
653 | ||
978cf586 | 654 | static int intel_vgpu_open_device(struct vfio_device *vfio_dev) |
659643f7 | 655 | { |
978cf586 | 656 | struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); |
f22b1e85 | 657 | int ret; |
0e09f406 | 658 | |
0e09f406 | 659 | if (__kvmgt_vgpu_exist(vgpu)) |
ce4b4657 | 660 | return -EEXIST; |
364fb6b7 | 661 | |
0e09f406 | 662 | vgpu->track_node.track_write = kvmgt_page_track_write; |
c15fcf12 | 663 | vgpu->track_node.track_remove_region = kvmgt_page_track_remove_region; |
f22b1e85 SC |
664 | ret = kvm_page_track_register_notifier(vgpu->vfio_device.kvm, |
665 | &vgpu->track_node); | |
666 | if (ret) { | |
667 | gvt_vgpu_err("KVM is required to use Intel vGPU\n"); | |
668 | return ret; | |
669 | } | |
0e09f406 | 670 | |
a06d4b9e ZW |
671 | set_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status); |
672 | ||
0e09f406 CH |
673 | debugfs_create_ulong(KVMGT_DEBUGFS_FILENAME, 0444, vgpu->debugfs, |
674 | &vgpu->nr_cache_entries); | |
675 | ||
675e5c4a | 676 | intel_gvt_activate_vgpu(vgpu); |
b79c52ae | 677 | |
0e09f406 | 678 | return 0; |
659643f7 JS |
679 | } |
680 | ||
d54e7934 XZ |
681 | static void intel_vgpu_release_msi_eventfd_ctx(struct intel_vgpu *vgpu) |
682 | { | |
683 | struct eventfd_ctx *trigger; | |
684 | ||
62980cac | 685 | trigger = vgpu->msi_trigger; |
d54e7934 XZ |
686 | if (trigger) { |
687 | eventfd_ctx_put(trigger); | |
62980cac | 688 | vgpu->msi_trigger = NULL; |
d54e7934 XZ |
689 | } |
690 | } | |
691 | ||
421cfe65 | 692 | static void intel_vgpu_close_device(struct vfio_device *vfio_dev) |
659643f7 | 693 | { |
421cfe65 | 694 | struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); |
659643f7 | 695 | |
675e5c4a | 696 | intel_gvt_release_vgpu(vgpu); |
b79c52ae | 697 | |
a06d4b9e ZW |
698 | clear_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status); |
699 | ||
d989bf54 | 700 | debugfs_lookup_and_remove(KVMGT_DEBUGFS_FILENAME, vgpu->debugfs); |
0e09f406 | 701 | |
421cfe65 MR |
702 | kvm_page_track_unregister_notifier(vgpu->vfio_device.kvm, |
703 | &vgpu->track_node); | |
3c9fd44b | 704 | |
0e09f406 CH |
705 | kvmgt_protect_table_destroy(vgpu); |
706 | gvt_cache_destroy(vgpu); | |
364fb6b7 | 707 | |
4dc334ca YL |
708 | WARN_ON(vgpu->nr_cache_entries); |
709 | ||
710 | vgpu->gfn_cache = RB_ROOT; | |
711 | vgpu->dma_addr_cache = RB_ROOT; | |
712 | ||
d54e7934 | 713 | intel_vgpu_release_msi_eventfd_ctx(vgpu); |
659643f7 JS |
714 | } |
715 | ||
2e679d48 | 716 | static u64 intel_vgpu_get_bar_addr(struct intel_vgpu *vgpu, int bar) |
659643f7 JS |
717 | { |
718 | u32 start_lo, start_hi; | |
719 | u32 mem_type; | |
659643f7 | 720 | |
f090a00d | 721 | start_lo = (*(u32 *)(vgpu->cfg_space.virtual_cfg_space + bar)) & |
659643f7 | 722 | PCI_BASE_ADDRESS_MEM_MASK; |
f090a00d | 723 | mem_type = (*(u32 *)(vgpu->cfg_space.virtual_cfg_space + bar)) & |
659643f7 JS |
724 | PCI_BASE_ADDRESS_MEM_TYPE_MASK; |
725 | ||
726 | switch (mem_type) { | |
727 | case PCI_BASE_ADDRESS_MEM_TYPE_64: | |
728 | start_hi = (*(u32 *)(vgpu->cfg_space.virtual_cfg_space | |
f090a00d | 729 | + bar + 4)); |
659643f7 JS |
730 | break; |
731 | case PCI_BASE_ADDRESS_MEM_TYPE_32: | |
732 | case PCI_BASE_ADDRESS_MEM_TYPE_1M: | |
733 | /* 1M mem BAR treated as 32-bit BAR */ | |
734 | default: | |
735 | /* mem unknown type treated as 32-bit BAR */ | |
736 | start_hi = 0; | |
737 | break; | |
738 | } | |
739 | ||
740 | return ((u64)start_hi << 32) | start_lo; | |
741 | } | |
742 | ||
2e679d48 | 743 | static int intel_vgpu_bar_rw(struct intel_vgpu *vgpu, int bar, u64 off, |
f090a00d CD |
744 | void *buf, unsigned int count, bool is_write) |
745 | { | |
2e679d48 | 746 | u64 bar_start = intel_vgpu_get_bar_addr(vgpu, bar); |
f090a00d CD |
747 | int ret; |
748 | ||
749 | if (is_write) | |
675e5c4a | 750 | ret = intel_vgpu_emulate_mmio_write(vgpu, |
f090a00d CD |
751 | bar_start + off, buf, count); |
752 | else | |
675e5c4a | 753 | ret = intel_vgpu_emulate_mmio_read(vgpu, |
f090a00d CD |
754 | bar_start + off, buf, count); |
755 | return ret; | |
756 | } | |
757 | ||
2e679d48 | 758 | static inline bool intel_vgpu_in_aperture(struct intel_vgpu *vgpu, u64 off) |
d480b28a CD |
759 | { |
760 | return off >= vgpu_aperture_offset(vgpu) && | |
761 | off < vgpu_aperture_offset(vgpu) + vgpu_aperture_sz(vgpu); | |
762 | } | |
763 | ||
2e679d48 | 764 | static int intel_vgpu_aperture_rw(struct intel_vgpu *vgpu, u64 off, |
d480b28a CD |
765 | void *buf, unsigned long count, bool is_write) |
766 | { | |
196a6627 | 767 | void __iomem *aperture_va; |
d480b28a CD |
768 | |
769 | if (!intel_vgpu_in_aperture(vgpu, off) || | |
770 | !intel_vgpu_in_aperture(vgpu, off + count)) { | |
771 | gvt_vgpu_err("Invalid aperture offset %llu\n", off); | |
772 | return -EINVAL; | |
773 | } | |
774 | ||
a61ac1e7 | 775 | aperture_va = io_mapping_map_wc(&vgpu->gvt->gt->ggtt->iomap, |
d480b28a CD |
776 | ALIGN_DOWN(off, PAGE_SIZE), |
777 | count + offset_in_page(off)); | |
778 | if (!aperture_va) | |
779 | return -EIO; | |
780 | ||
781 | if (is_write) | |
196a6627 | 782 | memcpy_toio(aperture_va + offset_in_page(off), buf, count); |
d480b28a | 783 | else |
196a6627 | 784 | memcpy_fromio(buf, aperture_va + offset_in_page(off), count); |
d480b28a CD |
785 | |
786 | io_mapping_unmap(aperture_va); | |
787 | ||
788 | return 0; | |
789 | } | |
790 | ||
7f11e689 | 791 | static ssize_t intel_vgpu_rw(struct intel_vgpu *vgpu, char *buf, |
659643f7 JS |
792 | size_t count, loff_t *ppos, bool is_write) |
793 | { | |
659643f7 | 794 | unsigned int index = VFIO_PCI_OFFSET_TO_INDEX(*ppos); |
2e679d48 | 795 | u64 pos = *ppos & VFIO_PCI_OFFSET_MASK; |
659643f7 JS |
796 | int ret = -EINVAL; |
797 | ||
798 | ||
62980cac | 799 | if (index >= VFIO_PCI_NUM_REGIONS + vgpu->num_regions) { |
695fbc08 | 800 | gvt_vgpu_err("invalid index: %u\n", index); |
659643f7 JS |
801 | return -EINVAL; |
802 | } | |
803 | ||
804 | switch (index) { | |
805 | case VFIO_PCI_CONFIG_REGION_INDEX: | |
806 | if (is_write) | |
675e5c4a | 807 | ret = intel_vgpu_emulate_cfg_write(vgpu, pos, |
659643f7 JS |
808 | buf, count); |
809 | else | |
675e5c4a | 810 | ret = intel_vgpu_emulate_cfg_read(vgpu, pos, |
659643f7 JS |
811 | buf, count); |
812 | break; | |
813 | case VFIO_PCI_BAR0_REGION_INDEX: | |
f090a00d CD |
814 | ret = intel_vgpu_bar_rw(vgpu, PCI_BASE_ADDRESS_0, pos, |
815 | buf, count, is_write); | |
659643f7 JS |
816 | break; |
817 | case VFIO_PCI_BAR2_REGION_INDEX: | |
d480b28a | 818 | ret = intel_vgpu_aperture_rw(vgpu, pos, buf, count, is_write); |
f090a00d CD |
819 | break; |
820 | case VFIO_PCI_BAR1_REGION_INDEX: | |
659643f7 JS |
821 | case VFIO_PCI_BAR3_REGION_INDEX: |
822 | case VFIO_PCI_BAR4_REGION_INDEX: | |
823 | case VFIO_PCI_BAR5_REGION_INDEX: | |
824 | case VFIO_PCI_VGA_REGION_INDEX: | |
825 | case VFIO_PCI_ROM_REGION_INDEX: | |
b851adea | 826 | break; |
659643f7 | 827 | default: |
62980cac | 828 | if (index >= VFIO_PCI_NUM_REGIONS + vgpu->num_regions) |
b851adea TZ |
829 | return -EINVAL; |
830 | ||
831 | index -= VFIO_PCI_NUM_REGIONS; | |
62980cac | 832 | return vgpu->region[index].ops->rw(vgpu, buf, count, |
b851adea | 833 | ppos, is_write); |
659643f7 JS |
834 | } |
835 | ||
836 | return ret == 0 ? count : ret; | |
837 | } | |
838 | ||
7f11e689 | 839 | static bool gtt_entry(struct intel_vgpu *vgpu, loff_t *ppos) |
a26ca6ad | 840 | { |
a26ca6ad TZ |
841 | unsigned int index = VFIO_PCI_OFFSET_TO_INDEX(*ppos); |
842 | struct intel_gvt *gvt = vgpu->gvt; | |
843 | int offset; | |
844 | ||
845 | /* Only allow MMIO GGTT entry access */ | |
846 | if (index != PCI_BASE_ADDRESS_0) | |
847 | return false; | |
848 | ||
849 | offset = (u64)(*ppos & VFIO_PCI_OFFSET_MASK) - | |
850 | intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_0); | |
851 | ||
852 | return (offset >= gvt->device_info.gtt_start_offset && | |
853 | offset < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt)) ? | |
854 | true : false; | |
855 | } | |
856 | ||
978cf586 | 857 | static ssize_t intel_vgpu_read(struct vfio_device *vfio_dev, char __user *buf, |
659643f7 JS |
858 | size_t count, loff_t *ppos) |
859 | { | |
978cf586 | 860 | struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); |
659643f7 JS |
861 | unsigned int done = 0; |
862 | int ret; | |
863 | ||
864 | while (count) { | |
865 | size_t filled; | |
866 | ||
a26ca6ad TZ |
867 | /* Only support GGTT entry 8 bytes read */ |
868 | if (count >= 8 && !(*ppos % 8) && | |
7f11e689 | 869 | gtt_entry(vgpu, ppos)) { |
a26ca6ad TZ |
870 | u64 val; |
871 | ||
7f11e689 | 872 | ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val), |
a26ca6ad TZ |
873 | ppos, false); |
874 | if (ret <= 0) | |
875 | goto read_err; | |
876 | ||
877 | if (copy_to_user(buf, &val, sizeof(val))) | |
878 | goto read_err; | |
879 | ||
880 | filled = 8; | |
881 | } else if (count >= 4 && !(*ppos % 4)) { | |
659643f7 JS |
882 | u32 val; |
883 | ||
7f11e689 | 884 | ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val), |
659643f7 JS |
885 | ppos, false); |
886 | if (ret <= 0) | |
887 | goto read_err; | |
888 | ||
889 | if (copy_to_user(buf, &val, sizeof(val))) | |
890 | goto read_err; | |
891 | ||
892 | filled = 4; | |
893 | } else if (count >= 2 && !(*ppos % 2)) { | |
894 | u16 val; | |
895 | ||
7f11e689 | 896 | ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val), |
659643f7 JS |
897 | ppos, false); |
898 | if (ret <= 0) | |
899 | goto read_err; | |
900 | ||
901 | if (copy_to_user(buf, &val, sizeof(val))) | |
902 | goto read_err; | |
903 | ||
904 | filled = 2; | |
905 | } else { | |
906 | u8 val; | |
907 | ||
7f11e689 | 908 | ret = intel_vgpu_rw(vgpu, &val, sizeof(val), ppos, |
659643f7 JS |
909 | false); |
910 | if (ret <= 0) | |
911 | goto read_err; | |
912 | ||
913 | if (copy_to_user(buf, &val, sizeof(val))) | |
914 | goto read_err; | |
915 | ||
916 | filled = 1; | |
917 | } | |
918 | ||
919 | count -= filled; | |
920 | done += filled; | |
921 | *ppos += filled; | |
922 | buf += filled; | |
923 | } | |
924 | ||
925 | return done; | |
926 | ||
927 | read_err: | |
928 | return -EFAULT; | |
929 | } | |
930 | ||
978cf586 | 931 | static ssize_t intel_vgpu_write(struct vfio_device *vfio_dev, |
659643f7 JS |
932 | const char __user *buf, |
933 | size_t count, loff_t *ppos) | |
934 | { | |
978cf586 | 935 | struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); |
659643f7 JS |
936 | unsigned int done = 0; |
937 | int ret; | |
938 | ||
939 | while (count) { | |
940 | size_t filled; | |
941 | ||
a26ca6ad TZ |
942 | /* Only support GGTT entry 8 bytes write */ |
943 | if (count >= 8 && !(*ppos % 8) && | |
7f11e689 | 944 | gtt_entry(vgpu, ppos)) { |
a26ca6ad TZ |
945 | u64 val; |
946 | ||
947 | if (copy_from_user(&val, buf, sizeof(val))) | |
948 | goto write_err; | |
949 | ||
7f11e689 | 950 | ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val), |
a26ca6ad TZ |
951 | ppos, true); |
952 | if (ret <= 0) | |
953 | goto write_err; | |
954 | ||
955 | filled = 8; | |
956 | } else if (count >= 4 && !(*ppos % 4)) { | |
659643f7 JS |
957 | u32 val; |
958 | ||
959 | if (copy_from_user(&val, buf, sizeof(val))) | |
960 | goto write_err; | |
961 | ||
7f11e689 | 962 | ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val), |
659643f7 JS |
963 | ppos, true); |
964 | if (ret <= 0) | |
965 | goto write_err; | |
966 | ||
967 | filled = 4; | |
968 | } else if (count >= 2 && !(*ppos % 2)) { | |
969 | u16 val; | |
970 | ||
971 | if (copy_from_user(&val, buf, sizeof(val))) | |
972 | goto write_err; | |
973 | ||
7f11e689 | 974 | ret = intel_vgpu_rw(vgpu, (char *)&val, |
659643f7 JS |
975 | sizeof(val), ppos, true); |
976 | if (ret <= 0) | |
977 | goto write_err; | |
978 | ||
979 | filled = 2; | |
980 | } else { | |
981 | u8 val; | |
982 | ||
983 | if (copy_from_user(&val, buf, sizeof(val))) | |
984 | goto write_err; | |
985 | ||
7f11e689 | 986 | ret = intel_vgpu_rw(vgpu, &val, sizeof(val), |
659643f7 JS |
987 | ppos, true); |
988 | if (ret <= 0) | |
989 | goto write_err; | |
990 | ||
991 | filled = 1; | |
992 | } | |
993 | ||
994 | count -= filled; | |
995 | done += filled; | |
996 | *ppos += filled; | |
997 | buf += filled; | |
998 | } | |
999 | ||
1000 | return done; | |
1001 | write_err: | |
1002 | return -EFAULT; | |
1003 | } | |
1004 | ||
978cf586 CH |
1005 | static int intel_vgpu_mmap(struct vfio_device *vfio_dev, |
1006 | struct vm_area_struct *vma) | |
659643f7 | 1007 | { |
978cf586 | 1008 | struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); |
659643f7 JS |
1009 | unsigned int index; |
1010 | u64 virtaddr; | |
51b00d85 | 1011 | unsigned long req_size, pgoff, req_start; |
659643f7 | 1012 | pgprot_t pg_prot; |
659643f7 JS |
1013 | |
1014 | index = vma->vm_pgoff >> (VFIO_PCI_OFFSET_SHIFT - PAGE_SHIFT); | |
1015 | if (index >= VFIO_PCI_ROM_REGION_INDEX) | |
1016 | return -EINVAL; | |
1017 | ||
1018 | if (vma->vm_end < vma->vm_start) | |
1019 | return -EINVAL; | |
1020 | if ((vma->vm_flags & VM_SHARED) == 0) | |
1021 | return -EINVAL; | |
1022 | if (index != VFIO_PCI_BAR2_REGION_INDEX) | |
1023 | return -EINVAL; | |
1024 | ||
1025 | pg_prot = vma->vm_page_prot; | |
1026 | virtaddr = vma->vm_start; | |
1027 | req_size = vma->vm_end - vma->vm_start; | |
51b00d85 ZW |
1028 | pgoff = vma->vm_pgoff & |
1029 | ((1U << (VFIO_PCI_OFFSET_SHIFT - PAGE_SHIFT)) - 1); | |
1030 | req_start = pgoff << PAGE_SHIFT; | |
1031 | ||
1032 | if (!intel_vgpu_in_aperture(vgpu, req_start)) | |
1033 | return -EINVAL; | |
1034 | if (req_start + req_size > | |
1035 | vgpu_aperture_offset(vgpu) + vgpu_aperture_sz(vgpu)) | |
1036 | return -EINVAL; | |
1037 | ||
1038 | pgoff = (gvt_aperture_pa_base(vgpu->gvt) >> PAGE_SHIFT) + pgoff; | |
659643f7 JS |
1039 | |
1040 | return remap_pfn_range(vma, virtaddr, pgoff, req_size, pg_prot); | |
1041 | } | |
1042 | ||
1043 | static int intel_vgpu_get_irq_count(struct intel_vgpu *vgpu, int type) | |
1044 | { | |
1045 | if (type == VFIO_PCI_INTX_IRQ_INDEX || type == VFIO_PCI_MSI_IRQ_INDEX) | |
1046 | return 1; | |
1047 | ||
1048 | return 0; | |
1049 | } | |
1050 | ||
1051 | static int intel_vgpu_set_intx_mask(struct intel_vgpu *vgpu, | |
1052 | unsigned int index, unsigned int start, | |
2e679d48 | 1053 | unsigned int count, u32 flags, |
659643f7 JS |
1054 | void *data) |
1055 | { | |
1056 | return 0; | |
1057 | } | |
1058 | ||
1059 | static int intel_vgpu_set_intx_unmask(struct intel_vgpu *vgpu, | |
1060 | unsigned int index, unsigned int start, | |
2e679d48 | 1061 | unsigned int count, u32 flags, void *data) |
659643f7 JS |
1062 | { |
1063 | return 0; | |
1064 | } | |
1065 | ||
1066 | static int intel_vgpu_set_intx_trigger(struct intel_vgpu *vgpu, | |
1067 | unsigned int index, unsigned int start, unsigned int count, | |
2e679d48 | 1068 | u32 flags, void *data) |
659643f7 JS |
1069 | { |
1070 | return 0; | |
1071 | } | |
1072 | ||
1073 | static int intel_vgpu_set_msi_trigger(struct intel_vgpu *vgpu, | |
1074 | unsigned int index, unsigned int start, unsigned int count, | |
2e679d48 | 1075 | u32 flags, void *data) |
659643f7 JS |
1076 | { |
1077 | struct eventfd_ctx *trigger; | |
1078 | ||
1079 | if (flags & VFIO_IRQ_SET_DATA_EVENTFD) { | |
1080 | int fd = *(int *)data; | |
1081 | ||
1082 | trigger = eventfd_ctx_fdget(fd); | |
1083 | if (IS_ERR(trigger)) { | |
695fbc08 | 1084 | gvt_vgpu_err("eventfd_ctx_fdget failed\n"); |
659643f7 JS |
1085 | return PTR_ERR(trigger); |
1086 | } | |
62980cac | 1087 | vgpu->msi_trigger = trigger; |
d54e7934 XZ |
1088 | } else if ((flags & VFIO_IRQ_SET_DATA_NONE) && !count) |
1089 | intel_vgpu_release_msi_eventfd_ctx(vgpu); | |
659643f7 JS |
1090 | |
1091 | return 0; | |
1092 | } | |
1093 | ||
2e679d48 | 1094 | static int intel_vgpu_set_irqs(struct intel_vgpu *vgpu, u32 flags, |
659643f7 JS |
1095 | unsigned int index, unsigned int start, unsigned int count, |
1096 | void *data) | |
1097 | { | |
1098 | int (*func)(struct intel_vgpu *vgpu, unsigned int index, | |
2e679d48 | 1099 | unsigned int start, unsigned int count, u32 flags, |
659643f7 JS |
1100 | void *data) = NULL; |
1101 | ||
1102 | switch (index) { | |
1103 | case VFIO_PCI_INTX_IRQ_INDEX: | |
1104 | switch (flags & VFIO_IRQ_SET_ACTION_TYPE_MASK) { | |
1105 | case VFIO_IRQ_SET_ACTION_MASK: | |
1106 | func = intel_vgpu_set_intx_mask; | |
1107 | break; | |
1108 | case VFIO_IRQ_SET_ACTION_UNMASK: | |
1109 | func = intel_vgpu_set_intx_unmask; | |
1110 | break; | |
1111 | case VFIO_IRQ_SET_ACTION_TRIGGER: | |
1112 | func = intel_vgpu_set_intx_trigger; | |
1113 | break; | |
1114 | } | |
1115 | break; | |
1116 | case VFIO_PCI_MSI_IRQ_INDEX: | |
1117 | switch (flags & VFIO_IRQ_SET_ACTION_TYPE_MASK) { | |
1118 | case VFIO_IRQ_SET_ACTION_MASK: | |
1119 | case VFIO_IRQ_SET_ACTION_UNMASK: | |
1120 | /* XXX Need masking support exported */ | |
1121 | break; | |
1122 | case VFIO_IRQ_SET_ACTION_TRIGGER: | |
1123 | func = intel_vgpu_set_msi_trigger; | |
1124 | break; | |
1125 | } | |
1126 | break; | |
1127 | } | |
1128 | ||
1129 | if (!func) | |
1130 | return -ENOTTY; | |
1131 | ||
1132 | return func(vgpu, index, start, count, flags, data); | |
1133 | } | |
1134 | ||
978cf586 | 1135 | static long intel_vgpu_ioctl(struct vfio_device *vfio_dev, unsigned int cmd, |
659643f7 JS |
1136 | unsigned long arg) |
1137 | { | |
978cf586 | 1138 | struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); |
659643f7 JS |
1139 | unsigned long minsz; |
1140 | ||
1141 | gvt_dbg_core("vgpu%d ioctl, cmd: %d\n", vgpu->id, cmd); | |
1142 | ||
1143 | if (cmd == VFIO_DEVICE_GET_INFO) { | |
1144 | struct vfio_device_info info; | |
1145 | ||
1146 | minsz = offsetofend(struct vfio_device_info, num_irqs); | |
1147 | ||
1148 | if (copy_from_user(&info, (void __user *)arg, minsz)) | |
1149 | return -EFAULT; | |
1150 | ||
1151 | if (info.argsz < minsz) | |
1152 | return -EINVAL; | |
1153 | ||
1154 | info.flags = VFIO_DEVICE_FLAGS_PCI; | |
1155 | info.flags |= VFIO_DEVICE_FLAGS_RESET; | |
b851adea | 1156 | info.num_regions = VFIO_PCI_NUM_REGIONS + |
62980cac | 1157 | vgpu->num_regions; |
659643f7 JS |
1158 | info.num_irqs = VFIO_PCI_NUM_IRQS; |
1159 | ||
1160 | return copy_to_user((void __user *)arg, &info, minsz) ? | |
1161 | -EFAULT : 0; | |
1162 | ||
1163 | } else if (cmd == VFIO_DEVICE_GET_REGION_INFO) { | |
1164 | struct vfio_region_info info; | |
1165 | struct vfio_info_cap caps = { .buf = NULL, .size = 0 }; | |
de5372da GS |
1166 | unsigned int i; |
1167 | int ret; | |
659643f7 | 1168 | struct vfio_region_info_cap_sparse_mmap *sparse = NULL; |
659643f7 JS |
1169 | int nr_areas = 1; |
1170 | int cap_type_id; | |
1171 | ||
1172 | minsz = offsetofend(struct vfio_region_info, offset); | |
1173 | ||
1174 | if (copy_from_user(&info, (void __user *)arg, minsz)) | |
1175 | return -EFAULT; | |
1176 | ||
1177 | if (info.argsz < minsz) | |
1178 | return -EINVAL; | |
1179 | ||
1180 | switch (info.index) { | |
1181 | case VFIO_PCI_CONFIG_REGION_INDEX: | |
1182 | info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); | |
02d578e5 | 1183 | info.size = vgpu->gvt->device_info.cfg_space_size; |
659643f7 JS |
1184 | info.flags = VFIO_REGION_INFO_FLAG_READ | |
1185 | VFIO_REGION_INFO_FLAG_WRITE; | |
1186 | break; | |
1187 | case VFIO_PCI_BAR0_REGION_INDEX: | |
1188 | info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); | |
1189 | info.size = vgpu->cfg_space.bar[info.index].size; | |
1190 | if (!info.size) { | |
1191 | info.flags = 0; | |
1192 | break; | |
1193 | } | |
1194 | ||
1195 | info.flags = VFIO_REGION_INFO_FLAG_READ | | |
1196 | VFIO_REGION_INFO_FLAG_WRITE; | |
1197 | break; | |
1198 | case VFIO_PCI_BAR1_REGION_INDEX: | |
1199 | info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); | |
1200 | info.size = 0; | |
1201 | info.flags = 0; | |
1202 | break; | |
1203 | case VFIO_PCI_BAR2_REGION_INDEX: | |
1204 | info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); | |
1205 | info.flags = VFIO_REGION_INFO_FLAG_CAPS | | |
1206 | VFIO_REGION_INFO_FLAG_MMAP | | |
1207 | VFIO_REGION_INFO_FLAG_READ | | |
1208 | VFIO_REGION_INFO_FLAG_WRITE; | |
1209 | info.size = gvt_aperture_sz(vgpu->gvt); | |
1210 | ||
cd3e0583 GS |
1211 | sparse = kzalloc(struct_size(sparse, areas, nr_areas), |
1212 | GFP_KERNEL); | |
659643f7 JS |
1213 | if (!sparse) |
1214 | return -ENOMEM; | |
1215 | ||
dda01f78 AW |
1216 | sparse->header.id = VFIO_REGION_INFO_CAP_SPARSE_MMAP; |
1217 | sparse->header.version = 1; | |
659643f7 JS |
1218 | sparse->nr_areas = nr_areas; |
1219 | cap_type_id = VFIO_REGION_INFO_CAP_SPARSE_MMAP; | |
1220 | sparse->areas[0].offset = | |
1221 | PAGE_ALIGN(vgpu_aperture_offset(vgpu)); | |
1222 | sparse->areas[0].size = vgpu_aperture_sz(vgpu); | |
659643f7 JS |
1223 | break; |
1224 | ||
1225 | case VFIO_PCI_BAR3_REGION_INDEX ... VFIO_PCI_BAR5_REGION_INDEX: | |
1226 | info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); | |
1227 | info.size = 0; | |
659643f7 | 1228 | info.flags = 0; |
072ec93d | 1229 | |
659643f7 JS |
1230 | gvt_dbg_core("get region info bar:%d\n", info.index); |
1231 | break; | |
1232 | ||
1233 | case VFIO_PCI_ROM_REGION_INDEX: | |
1234 | case VFIO_PCI_VGA_REGION_INDEX: | |
072ec93d PZ |
1235 | info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); |
1236 | info.size = 0; | |
1237 | info.flags = 0; | |
1238 | ||
659643f7 JS |
1239 | gvt_dbg_core("get region info index:%d\n", info.index); |
1240 | break; | |
1241 | default: | |
1242 | { | |
dda01f78 AW |
1243 | struct vfio_region_info_cap_type cap_type = { |
1244 | .header.id = VFIO_REGION_INFO_CAP_TYPE, | |
1245 | .header.version = 1 }; | |
659643f7 JS |
1246 | |
1247 | if (info.index >= VFIO_PCI_NUM_REGIONS + | |
62980cac | 1248 | vgpu->num_regions) |
659643f7 | 1249 | return -EINVAL; |
de5372da GS |
1250 | info.index = |
1251 | array_index_nospec(info.index, | |
1252 | VFIO_PCI_NUM_REGIONS + | |
62980cac | 1253 | vgpu->num_regions); |
659643f7 JS |
1254 | |
1255 | i = info.index - VFIO_PCI_NUM_REGIONS; | |
1256 | ||
1257 | info.offset = | |
1258 | VFIO_PCI_INDEX_TO_OFFSET(info.index); | |
62980cac CH |
1259 | info.size = vgpu->region[i].size; |
1260 | info.flags = vgpu->region[i].flags; | |
659643f7 | 1261 | |
62980cac CH |
1262 | cap_type.type = vgpu->region[i].type; |
1263 | cap_type.subtype = vgpu->region[i].subtype; | |
659643f7 JS |
1264 | |
1265 | ret = vfio_info_add_capability(&caps, | |
dda01f78 AW |
1266 | &cap_type.header, |
1267 | sizeof(cap_type)); | |
659643f7 JS |
1268 | if (ret) |
1269 | return ret; | |
1270 | } | |
1271 | } | |
1272 | ||
1273 | if ((info.flags & VFIO_REGION_INFO_FLAG_CAPS) && sparse) { | |
1274 | switch (cap_type_id) { | |
1275 | case VFIO_REGION_INFO_CAP_SPARSE_MMAP: | |
1276 | ret = vfio_info_add_capability(&caps, | |
cd3e0583 GS |
1277 | &sparse->header, |
1278 | struct_size(sparse, areas, | |
1279 | sparse->nr_areas)); | |
7590ebb8 YW |
1280 | if (ret) { |
1281 | kfree(sparse); | |
659643f7 | 1282 | return ret; |
7590ebb8 | 1283 | } |
659643f7 JS |
1284 | break; |
1285 | default: | |
7590ebb8 | 1286 | kfree(sparse); |
659643f7 JS |
1287 | return -EINVAL; |
1288 | } | |
1289 | } | |
1290 | ||
1291 | if (caps.size) { | |
b851adea | 1292 | info.flags |= VFIO_REGION_INFO_FLAG_CAPS; |
659643f7 JS |
1293 | if (info.argsz < sizeof(info) + caps.size) { |
1294 | info.argsz = sizeof(info) + caps.size; | |
1295 | info.cap_offset = 0; | |
1296 | } else { | |
1297 | vfio_info_cap_shift(&caps, sizeof(info)); | |
1298 | if (copy_to_user((void __user *)arg + | |
1299 | sizeof(info), caps.buf, | |
1300 | caps.size)) { | |
1301 | kfree(caps.buf); | |
7590ebb8 | 1302 | kfree(sparse); |
659643f7 JS |
1303 | return -EFAULT; |
1304 | } | |
1305 | info.cap_offset = sizeof(info); | |
1306 | } | |
1307 | ||
1308 | kfree(caps.buf); | |
1309 | } | |
1310 | ||
7590ebb8 | 1311 | kfree(sparse); |
659643f7 JS |
1312 | return copy_to_user((void __user *)arg, &info, minsz) ? |
1313 | -EFAULT : 0; | |
1314 | } else if (cmd == VFIO_DEVICE_GET_IRQ_INFO) { | |
1315 | struct vfio_irq_info info; | |
1316 | ||
1317 | minsz = offsetofend(struct vfio_irq_info, count); | |
1318 | ||
1319 | if (copy_from_user(&info, (void __user *)arg, minsz)) | |
1320 | return -EFAULT; | |
1321 | ||
1322 | if (info.argsz < minsz || info.index >= VFIO_PCI_NUM_IRQS) | |
1323 | return -EINVAL; | |
1324 | ||
1325 | switch (info.index) { | |
1326 | case VFIO_PCI_INTX_IRQ_INDEX: | |
1327 | case VFIO_PCI_MSI_IRQ_INDEX: | |
1328 | break; | |
1329 | default: | |
1330 | return -EINVAL; | |
1331 | } | |
1332 | ||
1333 | info.flags = VFIO_IRQ_INFO_EVENTFD; | |
1334 | ||
1335 | info.count = intel_vgpu_get_irq_count(vgpu, info.index); | |
1336 | ||
1337 | if (info.index == VFIO_PCI_INTX_IRQ_INDEX) | |
1338 | info.flags |= (VFIO_IRQ_INFO_MASKABLE | | |
1339 | VFIO_IRQ_INFO_AUTOMASKED); | |
1340 | else | |
1341 | info.flags |= VFIO_IRQ_INFO_NORESIZE; | |
1342 | ||
1343 | return copy_to_user((void __user *)arg, &info, minsz) ? | |
1344 | -EFAULT : 0; | |
1345 | } else if (cmd == VFIO_DEVICE_SET_IRQS) { | |
1346 | struct vfio_irq_set hdr; | |
1347 | u8 *data = NULL; | |
1348 | int ret = 0; | |
1349 | size_t data_size = 0; | |
1350 | ||
1351 | minsz = offsetofend(struct vfio_irq_set, count); | |
1352 | ||
1353 | if (copy_from_user(&hdr, (void __user *)arg, minsz)) | |
1354 | return -EFAULT; | |
1355 | ||
1356 | if (!(hdr.flags & VFIO_IRQ_SET_DATA_NONE)) { | |
1357 | int max = intel_vgpu_get_irq_count(vgpu, hdr.index); | |
1358 | ||
1359 | ret = vfio_set_irqs_validate_and_prepare(&hdr, max, | |
1360 | VFIO_PCI_NUM_IRQS, &data_size); | |
1361 | if (ret) { | |
695fbc08 | 1362 | gvt_vgpu_err("intel:vfio_set_irqs_validate_and_prepare failed\n"); |
659643f7 JS |
1363 | return -EINVAL; |
1364 | } | |
1365 | if (data_size) { | |
1366 | data = memdup_user((void __user *)(arg + minsz), | |
1367 | data_size); | |
1368 | if (IS_ERR(data)) | |
1369 | return PTR_ERR(data); | |
1370 | } | |
1371 | } | |
1372 | ||
1373 | ret = intel_vgpu_set_irqs(vgpu, hdr.flags, hdr.index, | |
1374 | hdr.start, hdr.count, data); | |
1375 | kfree(data); | |
1376 | ||
1377 | return ret; | |
1378 | } else if (cmd == VFIO_DEVICE_RESET) { | |
675e5c4a | 1379 | intel_gvt_reset_vgpu(vgpu); |
659643f7 | 1380 | return 0; |
e546e281 | 1381 | } else if (cmd == VFIO_DEVICE_QUERY_GFX_PLANE) { |
a7bea9f4 | 1382 | struct vfio_device_gfx_plane_info dmabuf = {}; |
e546e281 TZ |
1383 | int ret = 0; |
1384 | ||
1385 | minsz = offsetofend(struct vfio_device_gfx_plane_info, | |
1386 | dmabuf_id); | |
1387 | if (copy_from_user(&dmabuf, (void __user *)arg, minsz)) | |
1388 | return -EFAULT; | |
1389 | if (dmabuf.argsz < minsz) | |
1390 | return -EINVAL; | |
1391 | ||
675e5c4a | 1392 | ret = intel_vgpu_query_plane(vgpu, &dmabuf); |
e546e281 TZ |
1393 | if (ret != 0) |
1394 | return ret; | |
1395 | ||
1396 | return copy_to_user((void __user *)arg, &dmabuf, minsz) ? | |
1397 | -EFAULT : 0; | |
1398 | } else if (cmd == VFIO_DEVICE_GET_GFX_DMABUF) { | |
1399 | __u32 dmabuf_id; | |
e546e281 TZ |
1400 | |
1401 | if (get_user(dmabuf_id, (__u32 __user *)arg)) | |
1402 | return -EFAULT; | |
675e5c4a | 1403 | return intel_vgpu_get_dmabuf(vgpu, dmabuf_id); |
659643f7 JS |
1404 | } |
1405 | ||
9f591ae6 | 1406 | return -ENOTTY; |
659643f7 JS |
1407 | } |
1408 | ||
7a7a6561 ZW |
1409 | static ssize_t |
1410 | vgpu_id_show(struct device *dev, struct device_attribute *attr, | |
1411 | char *buf) | |
1412 | { | |
978cf586 | 1413 | struct intel_vgpu *vgpu = dev_get_drvdata(dev); |
7a7a6561 | 1414 | |
978cf586 | 1415 | return sprintf(buf, "%d\n", vgpu->id); |
7a7a6561 ZW |
1416 | } |
1417 | ||
1418 | static DEVICE_ATTR_RO(vgpu_id); | |
1419 | ||
1420 | static struct attribute *intel_vgpu_attrs[] = { | |
1421 | &dev_attr_vgpu_id.attr, | |
1422 | NULL | |
1423 | }; | |
1424 | ||
1425 | static const struct attribute_group intel_vgpu_group = { | |
1426 | .name = "intel_vgpu", | |
1427 | .attrs = intel_vgpu_attrs, | |
1428 | }; | |
1429 | ||
1430 | static const struct attribute_group *intel_vgpu_groups[] = { | |
1431 | &intel_vgpu_group, | |
1432 | NULL, | |
1433 | }; | |
1434 | ||
a5ddd2a9 KT |
1435 | static int intel_vgpu_init_dev(struct vfio_device *vfio_dev) |
1436 | { | |
1437 | struct mdev_device *mdev = to_mdev_device(vfio_dev->dev); | |
a5ddd2a9 | 1438 | struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); |
da44c340 CH |
1439 | struct intel_vgpu_type *type = |
1440 | container_of(mdev->type, struct intel_vgpu_type, type); | |
4dc334ca | 1441 | int ret; |
a5ddd2a9 | 1442 | |
062e720c | 1443 | vgpu->gvt = kdev_to_i915(mdev->type->parent->dev)->gvt; |
4dc334ca YL |
1444 | ret = intel_gvt_create_vgpu(vgpu, type->conf); |
1445 | if (ret) | |
1446 | return ret; | |
1447 | ||
1448 | kvmgt_protect_table_init(vgpu); | |
1449 | gvt_cache_init(vgpu); | |
1450 | ||
1451 | return 0; | |
a5ddd2a9 KT |
1452 | } |
1453 | ||
1454 | static void intel_vgpu_release_dev(struct vfio_device *vfio_dev) | |
1455 | { | |
1456 | struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); | |
1457 | ||
1458 | intel_gvt_destroy_vgpu(vgpu); | |
a5ddd2a9 KT |
1459 | } |
1460 | ||
978cf586 | 1461 | static const struct vfio_device_ops intel_vgpu_dev_ops = { |
a5ddd2a9 KT |
1462 | .init = intel_vgpu_init_dev, |
1463 | .release = intel_vgpu_release_dev, | |
978cf586 CH |
1464 | .open_device = intel_vgpu_open_device, |
1465 | .close_device = intel_vgpu_close_device, | |
1466 | .read = intel_vgpu_read, | |
1467 | .write = intel_vgpu_write, | |
1468 | .mmap = intel_vgpu_mmap, | |
1469 | .ioctl = intel_vgpu_ioctl, | |
ce4b4657 | 1470 | .dma_unmap = intel_vgpu_dma_unmap, |
4741f2e9 JG |
1471 | .bind_iommufd = vfio_iommufd_emulated_bind, |
1472 | .unbind_iommufd = vfio_iommufd_emulated_unbind, | |
1473 | .attach_ioas = vfio_iommufd_emulated_attach_ioas, | |
8cfa7186 | 1474 | .detach_ioas = vfio_iommufd_emulated_detach_ioas, |
978cf586 | 1475 | }; |
659643f7 | 1476 | |
978cf586 CH |
1477 | static int intel_vgpu_probe(struct mdev_device *mdev) |
1478 | { | |
978cf586 CH |
1479 | struct intel_vgpu *vgpu; |
1480 | int ret; | |
1481 | ||
a5ddd2a9 KT |
1482 | vgpu = vfio_alloc_device(intel_vgpu, vfio_device, &mdev->dev, |
1483 | &intel_vgpu_dev_ops); | |
978cf586 CH |
1484 | if (IS_ERR(vgpu)) { |
1485 | gvt_err("failed to create intel vgpu: %ld\n", PTR_ERR(vgpu)); | |
1486 | return PTR_ERR(vgpu); | |
1487 | } | |
659643f7 | 1488 | |
978cf586 CH |
1489 | dev_set_drvdata(&mdev->dev, vgpu); |
1490 | ret = vfio_register_emulated_iommu_dev(&vgpu->vfio_device); | |
a5ddd2a9 KT |
1491 | if (ret) |
1492 | goto out_put_vdev; | |
978cf586 CH |
1493 | |
1494 | gvt_dbg_core("intel_vgpu_create succeeded for mdev: %s\n", | |
1495 | dev_name(mdev_dev(mdev))); | |
1496 | return 0; | |
a5ddd2a9 KT |
1497 | |
1498 | out_put_vdev: | |
1499 | vfio_put_device(&vgpu->vfio_device); | |
1500 | return ret; | |
978cf586 CH |
1501 | } |
1502 | ||
1503 | static void intel_vgpu_remove(struct mdev_device *mdev) | |
1504 | { | |
1505 | struct intel_vgpu *vgpu = dev_get_drvdata(&mdev->dev); | |
1506 | ||
f423fa1b | 1507 | vfio_unregister_group_dev(&vgpu->vfio_device); |
a5ddd2a9 | 1508 | vfio_put_device(&vgpu->vfio_device); |
978cf586 CH |
1509 | } |
1510 | ||
f2fbc72e CH |
1511 | static unsigned int intel_vgpu_get_available(struct mdev_type *mtype) |
1512 | { | |
1513 | struct intel_vgpu_type *type = | |
1514 | container_of(mtype, struct intel_vgpu_type, type); | |
1515 | struct intel_gvt *gvt = kdev_to_i915(mtype->parent->dev)->gvt; | |
1516 | unsigned int low_gm_avail, high_gm_avail, fence_avail; | |
1517 | ||
1518 | mutex_lock(&gvt->lock); | |
1519 | low_gm_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE - | |
1520 | gvt->gm.vgpu_allocated_low_gm_size; | |
1521 | high_gm_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE - | |
1522 | gvt->gm.vgpu_allocated_high_gm_size; | |
1523 | fence_avail = gvt_fence_sz(gvt) - HOST_FENCE - | |
1524 | gvt->fence.vgpu_allocated_fence_num; | |
1525 | mutex_unlock(&gvt->lock); | |
1526 | ||
1527 | return min3(low_gm_avail / type->conf->low_mm, | |
1528 | high_gm_avail / type->conf->high_mm, | |
1529 | fence_avail / type->conf->fence); | |
1530 | } | |
1531 | ||
978cf586 | 1532 | static struct mdev_driver intel_vgpu_mdev_driver = { |
290aac5d | 1533 | .device_api = VFIO_DEVICE_API_PCI_STRING, |
978cf586 CH |
1534 | .driver = { |
1535 | .name = "intel_vgpu_mdev", | |
1536 | .owner = THIS_MODULE, | |
1537 | .dev_groups = intel_vgpu_groups, | |
1538 | }, | |
685a1537 CH |
1539 | .probe = intel_vgpu_probe, |
1540 | .remove = intel_vgpu_remove, | |
1541 | .get_available = intel_vgpu_get_available, | |
1542 | .show_description = intel_vgpu_show_description, | |
659643f7 JS |
1543 | }; |
1544 | ||
4c2baaaf | 1545 | int intel_gvt_page_track_add(struct intel_vgpu *info, u64 gfn) |
f30437c5 | 1546 | { |
96316a06 | 1547 | int r; |
f30437c5 | 1548 | |
a06d4b9e | 1549 | if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, info->status)) |
659643f7 JS |
1550 | return -ESRCH; |
1551 | ||
f30437c5 | 1552 | if (kvmgt_gfn_is_write_protected(info, gfn)) |
3cca6b26 | 1553 | return 0; |
f30437c5 | 1554 | |
96316a06 SC |
1555 | r = kvm_write_track_add_gfn(info->vfio_device.kvm, gfn); |
1556 | if (r) | |
1557 | return r; | |
f30437c5 | 1558 | |
3cca6b26 | 1559 | kvmgt_protect_table_add(info, gfn); |
f30437c5 JS |
1560 | return 0; |
1561 | } | |
1562 | ||
4c2baaaf | 1563 | int intel_gvt_page_track_remove(struct intel_vgpu *info, u64 gfn) |
f30437c5 | 1564 | { |
96316a06 | 1565 | int r; |
f30437c5 | 1566 | |
a06d4b9e ZW |
1567 | if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, info->status)) |
1568 | return -ESRCH; | |
659643f7 | 1569 | |
f30437c5 | 1570 | if (!kvmgt_gfn_is_write_protected(info, gfn)) |
3cca6b26 | 1571 | return 0; |
f30437c5 | 1572 | |
96316a06 SC |
1573 | r = kvm_write_track_remove_gfn(info->vfio_device.kvm, gfn); |
1574 | if (r) | |
1575 | return r; | |
f30437c5 | 1576 | |
3cca6b26 | 1577 | kvmgt_protect_table_del(info, gfn); |
f30437c5 JS |
1578 | return 0; |
1579 | } | |
1580 | ||
b271e17d SC |
1581 | static void kvmgt_page_track_write(gpa_t gpa, const u8 *val, int len, |
1582 | struct kvm_page_track_notifier_node *node) | |
f30437c5 | 1583 | { |
10ddb962 CH |
1584 | struct intel_vgpu *info = |
1585 | container_of(node, struct intel_vgpu, track_node); | |
f30437c5 | 1586 | |
3cca6b26 SC |
1587 | mutex_lock(&info->vgpu_lock); |
1588 | ||
09c8726f | 1589 | if (kvmgt_gfn_is_write_protected(info, gpa >> PAGE_SHIFT)) |
10ddb962 | 1590 | intel_vgpu_page_track_handler(info, gpa, |
4fafba2d | 1591 | (void *)val, len); |
3cca6b26 SC |
1592 | |
1593 | mutex_unlock(&info->vgpu_lock); | |
f30437c5 JS |
1594 | } |
1595 | ||
c15fcf12 YZ |
1596 | static void kvmgt_page_track_remove_region(gfn_t gfn, unsigned long nr_pages, |
1597 | struct kvm_page_track_notifier_node *node) | |
f30437c5 | 1598 | { |
16735297 | 1599 | unsigned long i; |
10ddb962 CH |
1600 | struct intel_vgpu *info = |
1601 | container_of(node, struct intel_vgpu, track_node); | |
f30437c5 | 1602 | |
3cca6b26 SC |
1603 | mutex_lock(&info->vgpu_lock); |
1604 | ||
c15fcf12 YZ |
1605 | for (i = 0; i < nr_pages; i++) { |
1606 | if (kvmgt_gfn_is_write_protected(info, gfn + i)) | |
1607 | kvmgt_protect_table_del(info, gfn + i); | |
f30437c5 | 1608 | } |
c15fcf12 | 1609 | |
3cca6b26 | 1610 | mutex_unlock(&info->vgpu_lock); |
f30437c5 JS |
1611 | } |
1612 | ||
4c705ad0 | 1613 | void intel_vgpu_detach_regions(struct intel_vgpu *vgpu) |
f30437c5 | 1614 | { |
6c2d0f99 | 1615 | int i; |
6c2d0f99 | 1616 | |
62980cac | 1617 | if (!vgpu->region) |
6c2d0f99 HY |
1618 | return; |
1619 | ||
62980cac CH |
1620 | for (i = 0; i < vgpu->num_regions; i++) |
1621 | if (vgpu->region[i].ops->release) | |
1622 | vgpu->region[i].ops->release(vgpu, | |
1623 | &vgpu->region[i]); | |
1624 | vgpu->num_regions = 0; | |
1625 | kfree(vgpu->region); | |
1626 | vgpu->region = NULL; | |
f30437c5 JS |
1627 | } |
1628 | ||
8398eee8 | 1629 | int intel_gvt_dma_map_guest_page(struct intel_vgpu *vgpu, unsigned long gfn, |
79e542f5 | 1630 | unsigned long size, dma_addr_t *dma_addr) |
cf4ee73f | 1631 | { |
cf4ee73f CD |
1632 | struct gvt_dma *entry; |
1633 | int ret; | |
1634 | ||
a06d4b9e | 1635 | if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status)) |
cf4ee73f CD |
1636 | return -EINVAL; |
1637 | ||
62980cac | 1638 | mutex_lock(&vgpu->cache_lock); |
cf4ee73f | 1639 | |
06d63c48 | 1640 | entry = __gvt_cache_find_gfn(vgpu, gfn); |
cf4ee73f | 1641 | if (!entry) { |
7366aeb7 XZ |
1642 | ret = gvt_dma_map_page(vgpu, gfn, dma_addr, size); |
1643 | if (ret) | |
1644 | goto err_unlock; | |
1645 | ||
06d63c48 | 1646 | ret = __gvt_cache_add(vgpu, gfn, *dma_addr, size); |
7366aeb7 XZ |
1647 | if (ret) |
1648 | goto err_unmap; | |
1649 | } else if (entry->size != size) { | |
1650 | /* the same gfn with different size: unmap and re-map */ | |
1651 | gvt_dma_unmap_page(vgpu, gfn, entry->dma_addr, entry->size); | |
1652 | __gvt_cache_remove_entry(vgpu, entry); | |
1653 | ||
79e542f5 | 1654 | ret = gvt_dma_map_page(vgpu, gfn, dma_addr, size); |
5cd4223e CD |
1655 | if (ret) |
1656 | goto err_unlock; | |
1657 | ||
06d63c48 | 1658 | ret = __gvt_cache_add(vgpu, gfn, *dma_addr, size); |
5cd4223e CD |
1659 | if (ret) |
1660 | goto err_unmap; | |
cf4ee73f CD |
1661 | } else { |
1662 | kref_get(&entry->ref); | |
1663 | *dma_addr = entry->dma_addr; | |
4a0b3444 | 1664 | } |
f30437c5 | 1665 | |
62980cac | 1666 | mutex_unlock(&vgpu->cache_lock); |
cf4ee73f | 1667 | return 0; |
5cd4223e CD |
1668 | |
1669 | err_unmap: | |
79e542f5 | 1670 | gvt_dma_unmap_page(vgpu, gfn, *dma_addr, size); |
5cd4223e | 1671 | err_unlock: |
62980cac | 1672 | mutex_unlock(&vgpu->cache_lock); |
5cd4223e | 1673 | return ret; |
cf4ee73f CD |
1674 | } |
1675 | ||
91879bba | 1676 | int intel_gvt_dma_pin_guest_page(struct intel_vgpu *vgpu, dma_addr_t dma_addr) |
9f674c81 | 1677 | { |
9f674c81 TZ |
1678 | struct gvt_dma *entry; |
1679 | int ret = 0; | |
1680 | ||
a06d4b9e ZW |
1681 | if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status)) |
1682 | return -EINVAL; | |
9f674c81 | 1683 | |
10ddb962 CH |
1684 | mutex_lock(&vgpu->cache_lock); |
1685 | entry = __gvt_cache_find_dma_addr(vgpu, dma_addr); | |
9f674c81 TZ |
1686 | if (entry) |
1687 | kref_get(&entry->ref); | |
1688 | else | |
1689 | ret = -ENOMEM; | |
10ddb962 | 1690 | mutex_unlock(&vgpu->cache_lock); |
9f674c81 TZ |
1691 | |
1692 | return ret; | |
1693 | } | |
1694 | ||
cf4ee73f CD |
1695 | static void __gvt_dma_release(struct kref *ref) |
1696 | { | |
1697 | struct gvt_dma *entry = container_of(ref, typeof(*entry), ref); | |
1698 | ||
79e542f5 CD |
1699 | gvt_dma_unmap_page(entry->vgpu, entry->gfn, entry->dma_addr, |
1700 | entry->size); | |
cf4ee73f CD |
1701 | __gvt_cache_remove_entry(entry->vgpu, entry); |
1702 | } | |
1703 | ||
8398eee8 | 1704 | void intel_gvt_dma_unmap_guest_page(struct intel_vgpu *vgpu, |
3c340d05 | 1705 | dma_addr_t dma_addr) |
cf4ee73f | 1706 | { |
cf4ee73f CD |
1707 | struct gvt_dma *entry; |
1708 | ||
a06d4b9e | 1709 | if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status)) |
cf4ee73f CD |
1710 | return; |
1711 | ||
62980cac | 1712 | mutex_lock(&vgpu->cache_lock); |
06d63c48 | 1713 | entry = __gvt_cache_find_dma_addr(vgpu, dma_addr); |
cf4ee73f CD |
1714 | if (entry) |
1715 | kref_put(&entry->ref, __gvt_dma_release); | |
62980cac | 1716 | mutex_unlock(&vgpu->cache_lock); |
f30437c5 JS |
1717 | } |
1718 | ||
cba619cb CH |
1719 | static void init_device_info(struct intel_gvt *gvt) |
1720 | { | |
1721 | struct intel_gvt_device_info *info = &gvt->device_info; | |
1722 | struct pci_dev *pdev = to_pci_dev(gvt->gt->i915->drm.dev); | |
1723 | ||
1724 | info->max_support_vgpus = 8; | |
1725 | info->cfg_space_size = PCI_CFG_SPACE_EXP_SIZE; | |
1726 | info->mmio_size = 2 * 1024 * 1024; | |
1727 | info->mmio_bar = 0; | |
1728 | info->gtt_start_offset = 8 * 1024 * 1024; | |
1729 | info->gtt_entry_size = 8; | |
1730 | info->gtt_entry_size_shift = 3; | |
1731 | info->gmadr_bytes_in_cmd = 8; | |
1732 | info->max_surface_size = 36 * 1024 * 1024; | |
1733 | info->msi_cap_offset = pdev->msi_cap; | |
1734 | } | |
1735 | ||
1736 | static void intel_gvt_test_and_emulate_vblank(struct intel_gvt *gvt) | |
1737 | { | |
1738 | struct intel_vgpu *vgpu; | |
1739 | int id; | |
1740 | ||
1741 | mutex_lock(&gvt->lock); | |
1742 | idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) { | |
1743 | if (test_and_clear_bit(INTEL_GVT_REQUEST_EMULATE_VBLANK + id, | |
1744 | (void *)&gvt->service_request)) { | |
a06d4b9e | 1745 | if (test_bit(INTEL_VGPU_STATUS_ACTIVE, vgpu->status)) |
cba619cb CH |
1746 | intel_vgpu_emulate_vblank(vgpu); |
1747 | } | |
1748 | } | |
1749 | mutex_unlock(&gvt->lock); | |
1750 | } | |
1751 | ||
1752 | static int gvt_service_thread(void *data) | |
1753 | { | |
1754 | struct intel_gvt *gvt = (struct intel_gvt *)data; | |
1755 | int ret; | |
1756 | ||
1757 | gvt_dbg_core("service thread start\n"); | |
1758 | ||
1759 | while (!kthread_should_stop()) { | |
1760 | ret = wait_event_interruptible(gvt->service_thread_wq, | |
1761 | kthread_should_stop() || gvt->service_request); | |
1762 | ||
1763 | if (kthread_should_stop()) | |
1764 | break; | |
1765 | ||
1766 | if (WARN_ONCE(ret, "service thread is waken up by signal.\n")) | |
1767 | continue; | |
1768 | ||
1769 | intel_gvt_test_and_emulate_vblank(gvt); | |
1770 | ||
1771 | if (test_bit(INTEL_GVT_REQUEST_SCHED, | |
1772 | (void *)&gvt->service_request) || | |
1773 | test_bit(INTEL_GVT_REQUEST_EVENT_SCHED, | |
1774 | (void *)&gvt->service_request)) { | |
1775 | intel_gvt_schedule(gvt); | |
1776 | } | |
1777 | } | |
1778 | ||
1779 | return 0; | |
1780 | } | |
1781 | ||
1782 | static void clean_service_thread(struct intel_gvt *gvt) | |
1783 | { | |
1784 | kthread_stop(gvt->service_thread); | |
1785 | } | |
1786 | ||
1787 | static int init_service_thread(struct intel_gvt *gvt) | |
1788 | { | |
1789 | init_waitqueue_head(&gvt->service_thread_wq); | |
1790 | ||
1791 | gvt->service_thread = kthread_run(gvt_service_thread, | |
1792 | gvt, "gvt_service_thread"); | |
1793 | if (IS_ERR(gvt->service_thread)) { | |
1794 | gvt_err("fail to start service thread.\n"); | |
1795 | return PTR_ERR(gvt->service_thread); | |
1796 | } | |
1797 | return 0; | |
1798 | } | |
1799 | ||
1800 | /** | |
1801 | * intel_gvt_clean_device - clean a GVT device | |
1802 | * @i915: i915 private | |
1803 | * | |
1804 | * This function is called at the driver unloading stage, to free the | |
1805 | * resources owned by a GVT device. | |
1806 | * | |
1807 | */ | |
1808 | static void intel_gvt_clean_device(struct drm_i915_private *i915) | |
1809 | { | |
1810 | struct intel_gvt *gvt = fetch_and_zero(&i915->gvt); | |
1811 | ||
1812 | if (drm_WARN_ON(&i915->drm, !gvt)) | |
1813 | return; | |
1814 | ||
89345d51 | 1815 | mdev_unregister_parent(&gvt->parent); |
cba619cb CH |
1816 | intel_gvt_destroy_idle_vgpu(gvt->idle_vgpu); |
1817 | intel_gvt_clean_vgpu_types(gvt); | |
1818 | ||
1819 | intel_gvt_debugfs_clean(gvt); | |
1820 | clean_service_thread(gvt); | |
1821 | intel_gvt_clean_cmd_parser(gvt); | |
1822 | intel_gvt_clean_sched_policy(gvt); | |
1823 | intel_gvt_clean_workload_scheduler(gvt); | |
1824 | intel_gvt_clean_gtt(gvt); | |
1825 | intel_gvt_free_firmware(gvt); | |
1826 | intel_gvt_clean_mmio_info(gvt); | |
1827 | idr_destroy(&gvt->vgpu_idr); | |
1828 | ||
1829 | kfree(i915->gvt); | |
1830 | } | |
1831 | ||
1832 | /** | |
1833 | * intel_gvt_init_device - initialize a GVT device | |
1834 | * @i915: drm i915 private data | |
1835 | * | |
1836 | * This function is called at the initialization stage, to initialize | |
1837 | * necessary GVT components. | |
1838 | * | |
1839 | * Returns: | |
1840 | * Zero on success, negative error code if failed. | |
1841 | * | |
1842 | */ | |
1843 | static int intel_gvt_init_device(struct drm_i915_private *i915) | |
1844 | { | |
1845 | struct intel_gvt *gvt; | |
1846 | struct intel_vgpu *vgpu; | |
1847 | int ret; | |
1848 | ||
1849 | if (drm_WARN_ON(&i915->drm, i915->gvt)) | |
1850 | return -EEXIST; | |
1851 | ||
1852 | gvt = kzalloc(sizeof(struct intel_gvt), GFP_KERNEL); | |
1853 | if (!gvt) | |
1854 | return -ENOMEM; | |
1855 | ||
1856 | gvt_dbg_core("init gvt device\n"); | |
1857 | ||
1858 | idr_init_base(&gvt->vgpu_idr, 1); | |
1859 | spin_lock_init(&gvt->scheduler.mmio_context_lock); | |
1860 | mutex_init(&gvt->lock); | |
1861 | mutex_init(&gvt->sched_lock); | |
1862 | gvt->gt = to_gt(i915); | |
1863 | i915->gvt = gvt; | |
1864 | ||
1865 | init_device_info(gvt); | |
1866 | ||
1867 | ret = intel_gvt_setup_mmio_info(gvt); | |
1868 | if (ret) | |
1869 | goto out_clean_idr; | |
1870 | ||
1871 | intel_gvt_init_engine_mmio_context(gvt); | |
1872 | ||
1873 | ret = intel_gvt_load_firmware(gvt); | |
1874 | if (ret) | |
1875 | goto out_clean_mmio_info; | |
1876 | ||
1877 | ret = intel_gvt_init_irq(gvt); | |
1878 | if (ret) | |
1879 | goto out_free_firmware; | |
1880 | ||
1881 | ret = intel_gvt_init_gtt(gvt); | |
1882 | if (ret) | |
1883 | goto out_free_firmware; | |
1884 | ||
1885 | ret = intel_gvt_init_workload_scheduler(gvt); | |
1886 | if (ret) | |
1887 | goto out_clean_gtt; | |
1888 | ||
1889 | ret = intel_gvt_init_sched_policy(gvt); | |
1890 | if (ret) | |
1891 | goto out_clean_workload_scheduler; | |
1892 | ||
1893 | ret = intel_gvt_init_cmd_parser(gvt); | |
1894 | if (ret) | |
1895 | goto out_clean_sched_policy; | |
1896 | ||
1897 | ret = init_service_thread(gvt); | |
1898 | if (ret) | |
1899 | goto out_clean_cmd_parser; | |
1900 | ||
1901 | ret = intel_gvt_init_vgpu_types(gvt); | |
1902 | if (ret) | |
1903 | goto out_clean_thread; | |
1904 | ||
1905 | vgpu = intel_gvt_create_idle_vgpu(gvt); | |
1906 | if (IS_ERR(vgpu)) { | |
1907 | ret = PTR_ERR(vgpu); | |
1908 | gvt_err("failed to create idle vgpu\n"); | |
1909 | goto out_clean_types; | |
1910 | } | |
1911 | gvt->idle_vgpu = vgpu; | |
1912 | ||
1913 | intel_gvt_debugfs_init(gvt); | |
1914 | ||
89345d51 | 1915 | ret = mdev_register_parent(&gvt->parent, i915->drm.dev, |
da44c340 CH |
1916 | &intel_vgpu_mdev_driver, |
1917 | gvt->mdev_types, gvt->num_types); | |
cba619cb | 1918 | if (ret) |
da44c340 | 1919 | goto out_destroy_idle_vgpu; |
cba619cb CH |
1920 | |
1921 | gvt_dbg_core("gvt device initialization is done\n"); | |
1922 | return 0; | |
1923 | ||
cba619cb CH |
1924 | out_destroy_idle_vgpu: |
1925 | intel_gvt_destroy_idle_vgpu(gvt->idle_vgpu); | |
1926 | intel_gvt_debugfs_clean(gvt); | |
1927 | out_clean_types: | |
1928 | intel_gvt_clean_vgpu_types(gvt); | |
1929 | out_clean_thread: | |
1930 | clean_service_thread(gvt); | |
1931 | out_clean_cmd_parser: | |
1932 | intel_gvt_clean_cmd_parser(gvt); | |
1933 | out_clean_sched_policy: | |
1934 | intel_gvt_clean_sched_policy(gvt); | |
1935 | out_clean_workload_scheduler: | |
1936 | intel_gvt_clean_workload_scheduler(gvt); | |
1937 | out_clean_gtt: | |
1938 | intel_gvt_clean_gtt(gvt); | |
1939 | out_free_firmware: | |
1940 | intel_gvt_free_firmware(gvt); | |
1941 | out_clean_mmio_info: | |
1942 | intel_gvt_clean_mmio_info(gvt); | |
1943 | out_clean_idr: | |
1944 | idr_destroy(&gvt->vgpu_idr); | |
1945 | kfree(gvt); | |
1946 | i915->gvt = NULL; | |
1947 | return ret; | |
1948 | } | |
1949 | ||
1950 | static void intel_gvt_pm_resume(struct drm_i915_private *i915) | |
1951 | { | |
1952 | struct intel_gvt *gvt = i915->gvt; | |
1953 | ||
1954 | intel_gvt_restore_fence(gvt); | |
1955 | intel_gvt_restore_mmio(gvt); | |
1956 | intel_gvt_restore_ggtt(gvt); | |
1957 | } | |
1958 | ||
1959 | static const struct intel_vgpu_ops intel_gvt_vgpu_ops = { | |
1960 | .init_device = intel_gvt_init_device, | |
1961 | .clean_device = intel_gvt_clean_device, | |
1962 | .pm_resume = intel_gvt_pm_resume, | |
1963 | }; | |
1964 | ||
f30437c5 JS |
1965 | static int __init kvmgt_init(void) |
1966 | { | |
978cf586 CH |
1967 | int ret; |
1968 | ||
1969 | ret = intel_gvt_set_ops(&intel_gvt_vgpu_ops); | |
1970 | if (ret) | |
1971 | return ret; | |
1972 | ||
1973 | ret = mdev_register_driver(&intel_vgpu_mdev_driver); | |
1974 | if (ret) | |
1975 | intel_gvt_clear_ops(&intel_gvt_vgpu_ops); | |
1976 | return ret; | |
f30437c5 JS |
1977 | } |
1978 | ||
1979 | static void __exit kvmgt_exit(void) | |
1980 | { | |
978cf586 | 1981 | mdev_unregister_driver(&intel_vgpu_mdev_driver); |
8b750bf7 | 1982 | intel_gvt_clear_ops(&intel_gvt_vgpu_ops); |
f30437c5 JS |
1983 | } |
1984 | ||
1985 | module_init(kvmgt_init); | |
1986 | module_exit(kvmgt_exit); | |
1987 | ||
1988 | MODULE_LICENSE("GPL and additional rights"); | |
1989 | MODULE_AUTHOR("Intel Corporation"); |