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drm/i915/gvt: Add missing breaks in switch statement
[linux-2.6-block.git] / drivers / gpu / drm / i915 / gvt / handlers.c
CommitLineData
12d14cc4
ZW		 1/*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Kevin Tian <kevin.tian@intel.com>
25 * Eddie Dong <eddie.dong@intel.com>
26 * Zhiyuan Lv <zhiyuan.lv@intel.com>
27 *
28 * Contributors:
29 * Min He <min.he@intel.com>
30 * Tina Zhang <tina.zhang@intel.com>
31 * Pei Zhang <pei.zhang@intel.com>
32 * Niu Bing <bing.niu@intel.com>
33 * Ping Gao <ping.a.gao@intel.com>
34 * Zhi Wang <zhi.a.wang@intel.com>
35 *
36
37 */
38
39#include "i915_drv.h"
feddf6e8
ZW		 40#include "gvt.h"
41#include "i915_pvinfo.h"
12d14cc4 42
e39c5add
ZW		 43/* XXX FIXME i915 has changed PP_XXX definition */
44#define PCH_PP_STATUS _MMIO(0xc7200)
45#define PCH_PP_CONTROL _MMIO(0xc7204)
46#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
47#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
48#define PCH_PP_DIVISOR _MMIO(0xc7210)
49
12d14cc4
ZW		 50unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
51{
52 if (IS_BROADWELL(gvt->dev_priv))
53 return D_BDW;
54 else if (IS_SKYLAKE(gvt->dev_priv))
55 return D_SKL;
e3476c00
XH		 56 else if (IS_KABYLAKE(gvt->dev_priv))
57 return D_KBL;
12d14cc4
ZW		 58
59 return 0;
60}
61
62bool intel_gvt_match_device(struct intel_gvt *gvt,
63 unsigned long device)
64{
65 return intel_gvt_get_device_type(gvt) & device;
66}
67
e39c5add
ZW		 68static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset,
69 void *p_data, unsigned int bytes)
70{
71 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
72}
73
74static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset,
75 void *p_data, unsigned int bytes)
76{
77 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
78}
79
65f9f6fe
CD		 80static struct intel_gvt_mmio_info *find_mmio_info(struct intel_gvt *gvt,
81 unsigned int offset)
82{
83 struct intel_gvt_mmio_info *e;
84
85 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) {
86 if (e->offset == offset)
87 return e;
88 }
89 return NULL;
90}
91
12d14cc4 92static int new_mmio_info(struct intel_gvt *gvt,
56a78de5 93 u32 offset, u8 flags, u32 size,
12d14cc4 94 u32 addr_mask, u32 ro_mask, u32 device,
65f9f6fe 95 gvt_mmio_func read, gvt_mmio_func write)
12d14cc4
ZW		 96{
97 struct intel_gvt_mmio_info *info, *p;
98 u32 start, end, i;
99
100 if (!intel_gvt_match_device(gvt, device))
101 return 0;
102
103 if (WARN_ON(!IS_ALIGNED(offset, 4)))
104 return -EINVAL;
105
106 start = offset;
107 end = offset + size;
108
109 for (i = start; i < end; i += 4) {
110 info = kzalloc(sizeof(*info), GFP_KERNEL);
111 if (!info)
112 return -ENOMEM;
113
114 info->offset = i;
65f9f6fe 115 p = find_mmio_info(gvt, info->offset);
36ed7e97
JJC		 116 if (p) {
117 WARN(1, "dup mmio definition offset %x\n",
12d14cc4 118 info->offset);
36ed7e97
JJC		 119 kfree(info);
120
121 /* We return -EEXIST here to make GVT-g load fail.
122 * So duplicated MMIO can be found as soon as
123 * possible.
124 */
125 return -EEXIST;
126 }
d8d94ba3 127
4ec3dd89 128 info->ro_mask = ro_mask;
12d14cc4 129 info->device = device;
e39c5add
ZW		 130 info->read = read ? read : intel_vgpu_default_mmio_read;
131 info->write = write ? write : intel_vgpu_default_mmio_write;
12d14cc4
ZW		 132 gvt->mmio.mmio_attribute[info->offset / 4] = flags;
133 INIT_HLIST_NODE(&info->node);
134 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset);
fbfd76c3 135 gvt->mmio.num_tracked_mmio++;
12d14cc4
ZW		 136 }
137 return 0;
138}
139
62a6a537
ZW		 140/**
141 * intel_gvt_render_mmio_to_ring_id - convert a mmio offset into ring id
142 * @gvt: a GVT device
143 * @offset: register offset
144 *
145 * Returns:
146 * Ring ID on success, negative error code if failed.
147 */
148int intel_gvt_render_mmio_to_ring_id(struct intel_gvt *gvt,
149 unsigned int offset)
28c4c6ca 150{
0fac21e7
ZW		 151 enum intel_engine_id id;
152 struct intel_engine_cs *engine;
28c4c6ca 153
62a6a537 154 offset &= ~GENMASK(11, 0);
0fac21e7 155 for_each_engine(engine, gvt->dev_priv, id) {
62a6a537 156 if (engine->mmio_base == offset)
0fac21e7 157 return id;
28c4c6ca 158 }
62a6a537 159 return -ENODEV;
28c4c6ca
ZW		 160}
161
e39c5add
ZW		 162#define offset_to_fence_num(offset) \
163 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3)
164
165#define fence_num_to_offset(num) \
166 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0)))
167
fd64be63 168
e011c6ce 169void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason)
fd64be63
MH		 170{
171 switch (reason) {
172 case GVT_FAILSAFE_UNSUPPORTED_GUEST:
173 pr_err("Detected your guest driver doesn't support GVT-g.\n");
174 break;
a33fc7a0
MH		 175 case GVT_FAILSAFE_INSUFFICIENT_RESOURCE:
176 pr_err("Graphics resource is not enough for the guest\n");
f745e9cc 177 break;
e011c6ce 178 case GVT_FAILSAFE_GUEST_ERR:
179 pr_err("GVT Internal error for the guest\n");
f745e9cc 180 break;
fd64be63
MH		 181 default:
182 break;
183 }
184 pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id);
185 vgpu->failsafe = true;
186}
187
e39c5add
ZW		 188static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu,
189 unsigned int fence_num, void *p_data, unsigned int bytes)
190{
191 if (fence_num >= vgpu_fence_sz(vgpu)) {
fd64be63
MH		 192
193 /* When guest access oob fence regs without access
194 * pv_info first, we treat guest not supporting GVT,
195 * and we will let vgpu enter failsafe mode.
196 */
d1be371d 197 if (!vgpu->pv_notified)
fd64be63
MH		 198 enter_failsafe_mode(vgpu,
199 GVT_FAILSAFE_UNSUPPORTED_GUEST);
d1be371d
ZX		 200
201 if (!vgpu->mmio.disable_warn_untrack) {
695fbc08
TZ		 202 gvt_vgpu_err("found oob fence register access\n");
203 gvt_vgpu_err("total fence %d, access fence %d\n",
204 vgpu_fence_sz(vgpu), fence_num);
fd64be63 205 }
e39c5add 206 memset(p_data, 0, bytes);
d1be371d 207 return -EINVAL;
e39c5add
ZW		 208 }
209 return 0;
210}
211
212static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off,
213 void *p_data, unsigned int bytes)
214{
215 int ret;
216
217 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off),
218 p_data, bytes);
219 if (ret)
220 return ret;
221 read_vreg(vgpu, off, p_data, bytes);
222 return 0;
223}
224
225static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
226 void *p_data, unsigned int bytes)
227{
9b7bd65e 228 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
e39c5add
ZW		 229 unsigned int fence_num = offset_to_fence_num(off);
230 int ret;
231
232 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes);
233 if (ret)
234 return ret;
235 write_vreg(vgpu, off, p_data, bytes);
236
9b7bd65e 237 mmio_hw_access_pre(dev_priv);
e39c5add
ZW		 238 intel_vgpu_write_fence(vgpu, fence_num,
239 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num)));
9b7bd65e 240 mmio_hw_access_post(dev_priv);
e39c5add
ZW		 241 return 0;
242}
243
244#define CALC_MODE_MASK_REG(old, new) \
245 (((new) & GENMASK(31, 16)) \
246 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \
247 | ((new) & ((new) >> 16))))
248
249static int mul_force_wake_write(struct intel_vgpu *vgpu,
250 unsigned int offset, void *p_data, unsigned int bytes)
251{
252 u32 old, new;
253 uint32_t ack_reg_offset;
254
255 old = vgpu_vreg(vgpu, offset);
256 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data);
257
e3476c00
XH		 258 if (IS_SKYLAKE(vgpu->gvt->dev_priv)
259 || IS_KABYLAKE(vgpu->gvt->dev_priv)) {
e39c5add
ZW		 260 switch (offset) {
261 case FORCEWAKE_RENDER_GEN9_REG:
262 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG;
263 break;
264 case FORCEWAKE_BLITTER_GEN9_REG:
265 ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG;
266 break;
267 case FORCEWAKE_MEDIA_GEN9_REG:
268 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG;
269 break;
270 default:
271 /*should not hit here*/
695fbc08 272 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset);
39762ad4 273 return -EINVAL;
e39c5add
ZW		 274 }
275 } else {
276 ack_reg_offset = FORCEWAKE_ACK_HSW_REG;
277 }
278
279 vgpu_vreg(vgpu, offset) = new;
280 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0));
281 return 0;
282}
283
284static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
c34eaa8d 285 void *p_data, unsigned int bytes)
e39c5add 286{
c34eaa8d 287 unsigned int engine_mask = 0;
e39c5add 288 u32 data;
e39c5add 289
40d2428b 290 write_vreg(vgpu, offset, p_data, bytes);
e39c5add
ZW		 291 data = vgpu_vreg(vgpu, offset);
292
293 if (data & GEN6_GRDOM_FULL) {
294 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id);
c34eaa8d
CD		 295 engine_mask = ALL_ENGINES;
296 } else {
297 if (data & GEN6_GRDOM_RENDER) {
298 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id);
299 engine_mask |= (1 << RCS);
300 }
301 if (data & GEN6_GRDOM_MEDIA) {
302 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id);
303 engine_mask |= (1 << VCS);
304 }
305 if (data & GEN6_GRDOM_BLT) {
306 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id);
307 engine_mask |= (1 << BCS);
308 }
309 if (data & GEN6_GRDOM_VECS) {
310 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id);
311 engine_mask |= (1 << VECS);
312 }
313 if (data & GEN8_GRDOM_MEDIA2) {
314 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id);
315 if (HAS_BSD2(vgpu->gvt->dev_priv))
316 engine_mask |= (1 << VCS2);
317 }
e39c5add 318 }
c34eaa8d
CD		 319
320 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask);
321
0811fa66 322 /* sw will wait for the device to ack the reset request */
323 vgpu_vreg(vgpu, offset) = 0;
324
c34eaa8d 325 return 0;
e39c5add
ZW		 326}
327
04d348ae
ZW		 328static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
329 void *p_data, unsigned int bytes)
330{
331 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes);
332}
333
334static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
335 void *p_data, unsigned int bytes)
336{
337 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes);
338}
339
340static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu,
341 unsigned int offset, void *p_data, unsigned int bytes)
342{
343 write_vreg(vgpu, offset, p_data, bytes);
344
345 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) {
346 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_ON;
347 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE;
348 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN;
349 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE;
350
351 } else
352 vgpu_vreg(vgpu, PCH_PP_STATUS) &=
353 ~(PP_ON | PP_SEQUENCE_POWER_DOWN
354 | PP_CYCLE_DELAY_ACTIVE);
355 return 0;
356}
357
358static int transconf_mmio_write(struct intel_vgpu *vgpu,
359 unsigned int offset, void *p_data, unsigned int bytes)
360{
361 write_vreg(vgpu, offset, p_data, bytes);
362
363 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE)
364 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE;
365 else
366 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE;
367 return 0;
368}
369
370static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
371 void *p_data, unsigned int bytes)
372{
373 write_vreg(vgpu, offset, p_data, bytes);
374
375 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE)
376 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK;
377 else
378 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK;
379
380 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK)
381 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE;
382 else
383 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE;
384
385 return 0;
386}
387
388static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
389 void *p_data, unsigned int bytes)
390{
5cd82b75
CD		 391 switch (offset) {
392 case 0xe651c:
393 case 0xe661c:
394 case 0xe671c:
395 case 0xe681c:
396 vgpu_vreg(vgpu, offset) = 1 << 17;
397 break;
398 case 0xe6c04:
399 vgpu_vreg(vgpu, offset) = 0x3;
400 break;
401 case 0xe6e1c:
402 vgpu_vreg(vgpu, offset) = 0x2f << 16;
403 break;
404 default:
405 return -EINVAL;
406 }
04d348ae 407
5cd82b75 408 read_vreg(vgpu, offset, p_data, bytes);
04d348ae
ZW		 409 return 0;
410}
411
412static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
413 void *p_data, unsigned int bytes)
414{
415 u32 data;
416
417 write_vreg(vgpu, offset, p_data, bytes);
418 data = vgpu_vreg(vgpu, offset);
419
420 if (data & PIPECONF_ENABLE)
421 vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE;
422 else
423 vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE;
424 intel_gvt_check_vblank_emulation(vgpu->gvt);
425 return 0;
426}
427
e6cedfea
ZY		 428/* ascendingly sorted */
429static i915_reg_t force_nonpriv_white_list[] = {
430 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec)
431 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248)
432 GEN8_CS_CHICKEN1,//_MMIO(0x2580)
433 _MMIO(0x2690),
434 _MMIO(0x2694),
435 _MMIO(0x2698),
436 _MMIO(0x4de0),
437 _MMIO(0x4de4),
438 _MMIO(0x4dfc),
439 GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010)
440 _MMIO(0x7014),
441 HDC_CHICKEN0,//_MMIO(0x7300)
442 GEN8_HDC_CHICKEN1,//_MMIO(0x7304)
443 _MMIO(0x7700),
444 _MMIO(0x7704),
445 _MMIO(0x7708),
446 _MMIO(0x770c),
447 _MMIO(0xb110),
448 GEN8_L3SQCREG4,//_MMIO(0xb118)
449 _MMIO(0xe100),
450 _MMIO(0xe18c),
451 _MMIO(0xe48c),
452 _MMIO(0xe5f4),
453};
454
455/* a simple bsearch */
456static inline bool in_whitelist(unsigned int reg)
457{
458 int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list);
459 i915_reg_t *array = force_nonpriv_white_list;
460
461 while (left < right) {
462 int mid = (left + right)/2;
463
464 if (reg > array[mid].reg)
465 left = mid + 1;
466 else if (reg < array[mid].reg)
467 right = mid;
468 else
469 return true;
470 }
471 return false;
472}
473
474static int force_nonpriv_write(struct intel_vgpu *vgpu,
475 unsigned int offset, void *p_data, unsigned int bytes)
476{
477 u32 reg_nonpriv = *(u32 *)p_data;
478 int ret = -EINVAL;
479
480 if ((bytes != 4) || ((offset & (bytes - 1)) != 0)) {
481 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV offset %x(%dB)\n",
482 vgpu->id, offset, bytes);
483 return ret;
484 }
485
486 if (in_whitelist(reg_nonpriv)) {
487 ret = intel_vgpu_default_mmio_write(vgpu, offset, p_data,
488 bytes);
489 } else {
490 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x\n",
491 vgpu->id, reg_nonpriv);
492 }
493 return ret;
494}
495
04d348ae
ZW		 496static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
497 void *p_data, unsigned int bytes)
498{
499 write_vreg(vgpu, offset, p_data, bytes);
500
501 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) {
502 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE;
503 } else {
504 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE;
505 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E)))
506 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E))
507 &= ~DP_TP_STATUS_AUTOTRAIN_DONE;
508 }
509 return 0;
510}
511
512static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu,
513 unsigned int offset, void *p_data, unsigned int bytes)
514{
515 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data;
516 return 0;
517}
518
519#define FDI_LINK_TRAIN_PATTERN1 0
520#define FDI_LINK_TRAIN_PATTERN2 1
521
522static int fdi_auto_training_started(struct intel_vgpu *vgpu)
523{
524 u32 ddi_buf_ctl = vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_E));
525 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL);
526 u32 tx_ctl = vgpu_vreg(vgpu, DP_TP_CTL(PORT_E));
527
528 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) &&
529 (rx_ctl & FDI_RX_ENABLE) &&
530 (rx_ctl & FDI_AUTO_TRAINING) &&
531 (tx_ctl & DP_TP_CTL_ENABLE) &&
532 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN))
533 return 1;
534 else
535 return 0;
536}
537
538static int check_fdi_rx_train_status(struct intel_vgpu *vgpu,
539 enum pipe pipe, unsigned int train_pattern)
540{
541 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl;
542 unsigned int fdi_rx_check_bits, fdi_tx_check_bits;
543 unsigned int fdi_rx_train_bits, fdi_tx_train_bits;
544 unsigned int fdi_iir_check_bits;
545
546 fdi_rx_imr = FDI_RX_IMR(pipe);
547 fdi_tx_ctl = FDI_TX_CTL(pipe);
548 fdi_rx_ctl = FDI_RX_CTL(pipe);
549
550 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) {
551 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT;
552 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1;
553 fdi_iir_check_bits = FDI_RX_BIT_LOCK;
554 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) {
555 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT;
556 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2;
557 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK;
558 } else {
695fbc08 559 gvt_vgpu_err("Invalid train pattern %d\n", train_pattern);
04d348ae
ZW		 560 return -EINVAL;
561 }
562
563 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits;
564 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits;
565
566 /* If imr bit has been masked */
567 if (vgpu_vreg(vgpu, fdi_rx_imr) & fdi_iir_check_bits)
568 return 0;
569
570 if (((vgpu_vreg(vgpu, fdi_tx_ctl) & fdi_tx_check_bits)
571 == fdi_tx_check_bits)
572 && ((vgpu_vreg(vgpu, fdi_rx_ctl) & fdi_rx_check_bits)
573 == fdi_rx_check_bits))
574 return 1;
575 else
576 return 0;
577}
578
579#define INVALID_INDEX (~0U)
580
581static unsigned int calc_index(unsigned int offset, unsigned int start,
582 unsigned int next, unsigned int end, i915_reg_t i915_end)
583{
584 unsigned int range = next - start;
585
586 if (!end)
587 end = i915_mmio_reg_offset(i915_end);
588 if (offset < start || offset > end)
589 return INVALID_INDEX;
590 offset -= start;
591 return offset / range;
592}
593
594#define FDI_RX_CTL_TO_PIPE(offset) \
595 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C))
596
597#define FDI_TX_CTL_TO_PIPE(offset) \
598 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C))
599
600#define FDI_RX_IMR_TO_PIPE(offset) \
601 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C))
602
603static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu,
604 unsigned int offset, void *p_data, unsigned int bytes)
605{
606 i915_reg_t fdi_rx_iir;
607 unsigned int index;
608 int ret;
609
610 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX)
611 index = FDI_RX_CTL_TO_PIPE(offset);
612 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX)
613 index = FDI_TX_CTL_TO_PIPE(offset);
614 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX)
615 index = FDI_RX_IMR_TO_PIPE(offset);
616 else {
695fbc08 617 gvt_vgpu_err("Unsupport registers %x\n", offset);
04d348ae
ZW		 618 return -EINVAL;
619 }
620
621 write_vreg(vgpu, offset, p_data, bytes);
622
623 fdi_rx_iir = FDI_RX_IIR(index);
624
625 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1);
626 if (ret < 0)
627 return ret;
628 if (ret)
629 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK;
630
631 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2);
632 if (ret < 0)
633 return ret;
634 if (ret)
635 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK;
636
637 if (offset == _FDI_RXA_CTL)
638 if (fdi_auto_training_started(vgpu))
639 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E)) |=
640 DP_TP_STATUS_AUTOTRAIN_DONE;
641 return 0;
642}
643
644#define DP_TP_CTL_TO_PORT(offset) \
645 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E))
646
647static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
648 void *p_data, unsigned int bytes)
649{
650 i915_reg_t status_reg;
651 unsigned int index;
652 u32 data;
653
654 write_vreg(vgpu, offset, p_data, bytes);
655
656 index = DP_TP_CTL_TO_PORT(offset);
657 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8;
658 if (data == 0x2) {
659 status_reg = DP_TP_STATUS(index);
660 vgpu_vreg(vgpu, status_reg) |= (1 << 25);
661 }
662 return 0;
663}
664
665static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu,
666 unsigned int offset, void *p_data, unsigned int bytes)
667{
668 u32 reg_val;
669 u32 sticky_mask;
670
671 reg_val = *((u32 *)p_data);
672 sticky_mask = GENMASK(27, 26) | (1 << 24);
673
674 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) |
675 (vgpu_vreg(vgpu, offset) & sticky_mask);
676 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask);
677 return 0;
678}
679
680static int pch_adpa_mmio_write(struct intel_vgpu *vgpu,
681 unsigned int offset, void *p_data, unsigned int bytes)
682{
683 u32 data;
684
685 write_vreg(vgpu, offset, p_data, bytes);
686 data = vgpu_vreg(vgpu, offset);
687
688 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER)
689 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
690 return 0;
691}
692
693static int south_chicken2_mmio_write(struct intel_vgpu *vgpu,
694 unsigned int offset, void *p_data, unsigned int bytes)
695{
696 u32 data;
697
698 write_vreg(vgpu, offset, p_data, bytes);
699 data = vgpu_vreg(vgpu, offset);
700
701 if (data & FDI_MPHY_IOSFSB_RESET_CTL)
702 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS;
703 else
704 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS;
705 return 0;
706}
707
708#define DSPSURF_TO_PIPE(offset) \
709 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C))
710
711static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
712 void *p_data, unsigned int bytes)
713{
714 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
715 unsigned int index = DSPSURF_TO_PIPE(offset);
716 i915_reg_t surflive_reg = DSPSURFLIVE(index);
717 int flip_event[] = {
718 [PIPE_A] = PRIMARY_A_FLIP_DONE,
719 [PIPE_B] = PRIMARY_B_FLIP_DONE,
720 [PIPE_C] = PRIMARY_C_FLIP_DONE,
721 };
722
723 write_vreg(vgpu, offset, p_data, bytes);
724 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset);
725
726 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]);
727 return 0;
728}
729
730#define SPRSURF_TO_PIPE(offset) \
731 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C))
732
733static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
734 void *p_data, unsigned int bytes)
735{
736 unsigned int index = SPRSURF_TO_PIPE(offset);
737 i915_reg_t surflive_reg = SPRSURFLIVE(index);
738 int flip_event[] = {
739 [PIPE_A] = SPRITE_A_FLIP_DONE,
740 [PIPE_B] = SPRITE_B_FLIP_DONE,
741 [PIPE_C] = SPRITE_C_FLIP_DONE,
742 };
743
744 write_vreg(vgpu, offset, p_data, bytes);
745 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset);
746
747 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]);
748 return 0;
749}
750
751static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu,
752 unsigned int reg)
753{
754 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
755 enum intel_gvt_event_type event;
756
757 if (reg == _DPA_AUX_CH_CTL)
758 event = AUX_CHANNEL_A;
759 else if (reg == _PCH_DPB_AUX_CH_CTL || reg == _DPB_AUX_CH_CTL)
760 event = AUX_CHANNEL_B;
761 else if (reg == _PCH_DPC_AUX_CH_CTL || reg == _DPC_AUX_CH_CTL)
762 event = AUX_CHANNEL_C;
763 else if (reg == _PCH_DPD_AUX_CH_CTL || reg == _DPD_AUX_CH_CTL)
764 event = AUX_CHANNEL_D;
765 else {
766 WARN_ON(true);
767 return -EINVAL;
768 }
769
770 intel_vgpu_trigger_virtual_event(vgpu, event);
771 return 0;
772}
773
774static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value,
775 unsigned int reg, int len, bool data_valid)
776{
777 /* mark transaction done */
778 value |= DP_AUX_CH_CTL_DONE;
779 value &= ~DP_AUX_CH_CTL_SEND_BUSY;
780 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR;
781
782 if (data_valid)
783 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR;
784 else
785 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR;
786
787 /* message size */
788 value &= ~(0xf << 20);
789 value |= (len << 20);
790 vgpu_vreg(vgpu, reg) = value;
791
792 if (value & DP_AUX_CH_CTL_INTERRUPT)
793 return trigger_aux_channel_interrupt(vgpu, reg);
794 return 0;
795}
796
797static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd,
798 uint8_t t)
799{
800 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) {
801 /* training pattern 1 for CR */
802 /* set LANE0_CR_DONE, LANE1_CR_DONE */
803 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE;
804 /* set LANE2_CR_DONE, LANE3_CR_DONE */
805 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE;
806 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) ==
807 DPCD_TRAINING_PATTERN_2) {
808 /* training pattern 2 for EQ */
809 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */
810 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE;
811 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED;
812 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */
813 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE;
814 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED;
815 /* set INTERLANE_ALIGN_DONE */
816 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |=
817 DPCD_INTERLANE_ALIGN_DONE;
818 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) ==
819 DPCD_LINK_TRAINING_DISABLED) {
820 /* finish link training */
821 /* set sink status as synchronized */
822 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC;
823 }
824}
825
826#define _REG_HSW_DP_AUX_CH_CTL(dp) \
827 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010)
828
829#define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100)
830
831#define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8)
832
833#define dpy_is_valid_port(port) \
834 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS))
835
836static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu,
837 unsigned int offset, void *p_data, unsigned int bytes)
838{
839 struct intel_vgpu_display *display = &vgpu->display;
840 int msg, addr, ctrl, op, len;
841 int port_index = OFFSET_TO_DP_AUX_PORT(offset);
842 struct intel_vgpu_dpcd_data *dpcd = NULL;
843 struct intel_vgpu_port *port = NULL;
844 u32 data;
845
846 if (!dpy_is_valid_port(port_index)) {
695fbc08 847 gvt_vgpu_err("Unsupported DP port access!\n");
04d348ae
ZW		 848 return 0;
849 }
850
851 write_vreg(vgpu, offset, p_data, bytes);
852 data = vgpu_vreg(vgpu, offset);
853
e3476c00
XH		 854 if ((IS_SKYLAKE(vgpu->gvt->dev_priv)
855 || IS_KABYLAKE(vgpu->gvt->dev_priv))
856 && offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) {
04d348ae
ZW		 857 /* SKL DPB/C/D aux ctl register changed */
858 return 0;
859 } else if (IS_BROADWELL(vgpu->gvt->dev_priv) &&
860 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) {
861 /* write to the data registers */
862 return 0;
863 }
864
865 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) {
866 /* just want to clear the sticky bits */
867 vgpu_vreg(vgpu, offset) = 0;
868 return 0;
869 }
870
871 port = &display->ports[port_index];
872 dpcd = port->dpcd;
873
874 /* read out message from DATA1 register */
875 msg = vgpu_vreg(vgpu, offset + 4);
876 addr = (msg >> 8) & 0xffff;
877 ctrl = (msg >> 24) & 0xff;
878 len = msg & 0xff;
879 op = ctrl >> 4;
880
881 if (op == GVT_AUX_NATIVE_WRITE) {
882 int t;
883 uint8_t buf[16];
884
885 if ((addr + len + 1) >= DPCD_SIZE) {
886 /*
887 * Write request exceeds what we supported,
888 * DCPD spec: When a Source Device is writing a DPCD
889 * address not supported by the Sink Device, the Sink
890 * Device shall reply with AUX NACK and “M” equal to
891 * zero.
892 */
893
894 /* NAK the write */
895 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK;
896 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true);
897 return 0;
898 }
899
900 /*
901 * Write request format: (command + address) occupies
902 * 3 bytes, followed by (len + 1) bytes of data.
903 */
904 if (WARN_ON((len + 4) > AUX_BURST_SIZE))
905 return -EINVAL;
906
907 /* unpack data from vreg to buf */
908 for (t = 0; t < 4; t++) {
909 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4);
910
911 buf[t * 4] = (r >> 24) & 0xff;
912 buf[t * 4 + 1] = (r >> 16) & 0xff;
913 buf[t * 4 + 2] = (r >> 8) & 0xff;
914 buf[t * 4 + 3] = r & 0xff;
915 }
916
917 /* write to virtual DPCD */
918 if (dpcd && dpcd->data_valid) {
919 for (t = 0; t <= len; t++) {
920 int p = addr + t;
921
922 dpcd->data[p] = buf[t];
923 /* check for link training */
924 if (p == DPCD_TRAINING_PATTERN_SET)
925 dp_aux_ch_ctl_link_training(dpcd,
926 buf[t]);
927 }
928 }
929
930 /* ACK the write */
931 vgpu_vreg(vgpu, offset + 4) = 0;
932 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1,
933 dpcd && dpcd->data_valid);
934 return 0;
935 }
936
937 if (op == GVT_AUX_NATIVE_READ) {
938 int idx, i, ret = 0;
939
940 if ((addr + len + 1) >= DPCD_SIZE) {
941 /*
942 * read request exceeds what we supported
943 * DPCD spec: A Sink Device receiving a Native AUX CH
944 * read request for an unsupported DPCD address must
945 * reply with an AUX ACK and read data set equal to
946 * zero instead of replying with AUX NACK.
947 */
948
949 /* ACK the READ*/
950 vgpu_vreg(vgpu, offset + 4) = 0;
951 vgpu_vreg(vgpu, offset + 8) = 0;
952 vgpu_vreg(vgpu, offset + 12) = 0;
953 vgpu_vreg(vgpu, offset + 16) = 0;
954 vgpu_vreg(vgpu, offset + 20) = 0;
955
956 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
957 true);
958 return 0;
959 }
960
961 for (idx = 1; idx <= 5; idx++) {
962 /* clear the data registers */
963 vgpu_vreg(vgpu, offset + 4 * idx) = 0;
964 }
965
966 /*
967 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data.
968 */
969 if (WARN_ON((len + 2) > AUX_BURST_SIZE))
970 return -EINVAL;
971
972 /* read from virtual DPCD to vreg */
973 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */
974 if (dpcd && dpcd->data_valid) {
975 for (i = 1; i <= (len + 1); i++) {
976 int t;
977
978 t = dpcd->data[addr + i - 1];
979 t <<= (24 - 8 * (i % 4));
980 ret |= t;
981
982 if ((i % 4 == 3) || (i == (len + 1))) {
983 vgpu_vreg(vgpu, offset +
984 (i / 4 + 1) * 4) = ret;
985 ret = 0;
986 }
987 }
988 }
989 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
990 dpcd && dpcd->data_valid);
991 return 0;
992 }
993
994 /* i2c transaction starts */
995 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data);
996
997 if (data & DP_AUX_CH_CTL_INTERRUPT)
998 trigger_aux_channel_interrupt(vgpu, offset);
999 return 0;
1000}
1001
975629c3
PZ		 1002static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset,
1003 void *p_data, unsigned int bytes)
1004{
1005 *(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH);
1006 write_vreg(vgpu, offset, p_data, bytes);
1007 return 0;
1008}
1009
04d348ae
ZW		 1010static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1011 void *p_data, unsigned int bytes)
1012{
1013 bool vga_disable;
1014
1015 write_vreg(vgpu, offset, p_data, bytes);
1016 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE;
1017
1018 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id,
1019 vga_disable ? "Disable" : "Enable");
1020 return 0;
1021}
1022
1023static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu,
1024 unsigned int sbi_offset)
1025{
1026 struct intel_vgpu_display *display = &vgpu->display;
1027 int num = display->sbi.number;
1028 int i;
1029
1030 for (i = 0; i < num; ++i)
1031 if (display->sbi.registers[i].offset == sbi_offset)
1032 break;
1033
1034 if (i == num)
1035 return 0;
1036
1037 return display->sbi.registers[i].value;
1038}
1039
1040static void write_virtual_sbi_register(struct intel_vgpu *vgpu,
1041 unsigned int offset, u32 value)
1042{
1043 struct intel_vgpu_display *display = &vgpu->display;
1044 int num = display->sbi.number;
1045 int i;
1046
1047 for (i = 0; i < num; ++i) {
1048 if (display->sbi.registers[i].offset == offset)
1049 break;
1050 }
1051
1052 if (i == num) {
1053 if (num == SBI_REG_MAX) {
695fbc08 1054 gvt_vgpu_err("SBI caching meets maximum limits\n");
04d348ae
ZW		 1055 return;
1056 }
1057 display->sbi.number++;
1058 }
1059
1060 display->sbi.registers[i].offset = offset;
1061 display->sbi.registers[i].value = value;
1062}
1063
1064static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
1065 void *p_data, unsigned int bytes)
1066{
1067 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
1068 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) {
1069 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) &
1070 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
1071 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu,
1072 sbi_offset);
1073 }
1074 read_vreg(vgpu, offset, p_data, bytes);
1075 return 0;
1076}
1077
3e70c5d6 1078static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
04d348ae
ZW		 1079 void *p_data, unsigned int bytes)
1080{
1081 u32 data;
1082
1083 write_vreg(vgpu, offset, p_data, bytes);
1084 data = vgpu_vreg(vgpu, offset);
1085
1086 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT);
1087 data |= SBI_READY;
1088
1089 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT);
1090 data |= SBI_RESPONSE_SUCCESS;
1091
1092 vgpu_vreg(vgpu, offset) = data;
1093
1094 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
1095 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) {
1096 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) &
1097 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
1098
1099 write_virtual_sbi_register(vgpu, sbi_offset,
1100 vgpu_vreg(vgpu, SBI_DATA));
1101 }
1102 return 0;
1103}
1104
e39c5add
ZW		 1105#define _vgtif_reg(x) \
1106 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x))
1107
1108static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
1109 void *p_data, unsigned int bytes)
1110{
1111 bool invalid_read = false;
1112
1113 read_vreg(vgpu, offset, p_data, bytes);
1114
1115 switch (offset) {
1116 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id):
1117 if (offset + bytes > _vgtif_reg(vgt_id) + 4)
1118 invalid_read = true;
1119 break;
1120 case _vgtif_reg(avail_rs.mappable_gmadr.base) ...
1121 _vgtif_reg(avail_rs.fence_num):
1122 if (offset + bytes >
1123 _vgtif_reg(avail_rs.fence_num) + 4)
1124 invalid_read = true;
1125 break;
1126 case 0x78010: /* vgt_caps */
1127 case 0x7881c:
1128 break;
1129 default:
1130 invalid_read = true;
1131 break;
1132 }
1133 if (invalid_read)
695fbc08 1134 gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n",
e39c5add 1135 offset, bytes, *(u32 *)p_data);
fd64be63 1136 vgpu->pv_notified = true;
e39c5add
ZW		 1137 return 0;
1138}
1139
1140static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification)
1141{
1142 int ret = 0;
1143
1144 switch (notification) {
1145 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE:
1146 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 3);
1147 break;
1148 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY:
1149 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 3);
1150 break;
1151 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE:
1152 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 4);
1153 break;
1154 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY:
1155 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 4);
1156 break;
1157 case VGT_G2V_EXECLIST_CONTEXT_CREATE:
1158 case VGT_G2V_EXECLIST_CONTEXT_DESTROY:
1159 case 1: /* Remove this in guest driver. */
1160 break;
1161 default:
695fbc08 1162 gvt_vgpu_err("Invalid PV notification %d\n", notification);
e39c5add
ZW		 1163 }
1164 return ret;
1165}
1166
04d348ae
ZW		 1167static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready)
1168{
1169 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1170 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
1171 char *env[3] = {NULL, NULL, NULL};
1172 char vmid_str[20];
1173 char display_ready_str[20];
1174
d8e9b2b9 1175 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready);
04d348ae
ZW		 1176 env[0] = display_ready_str;
1177
1178 snprintf(vmid_str, 20, "VMID=%d", vgpu->id);
1179 env[1] = vmid_str;
1180
1181 return kobject_uevent_env(kobj, KOBJ_ADD, env);
1182}
1183
e39c5add
ZW		 1184static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1185 void *p_data, unsigned int bytes)
1186{
1187 u32 data;
1188 int ret;
1189
1190 write_vreg(vgpu, offset, p_data, bytes);
1191 data = vgpu_vreg(vgpu, offset);
1192
1193 switch (offset) {
1194 case _vgtif_reg(display_ready):
04d348ae
ZW		 1195 send_display_ready_uevent(vgpu, data ? 1 : 0);
1196 break;
e39c5add
ZW		 1197 case _vgtif_reg(g2v_notify):
1198 ret = handle_g2v_notification(vgpu, data);
1199 break;
1200 /* add xhot and yhot to handled list to avoid error log */
1201 case 0x78830:
1202 case 0x78834:
1203 case _vgtif_reg(pdp[0].lo):
1204 case _vgtif_reg(pdp[0].hi):
1205 case _vgtif_reg(pdp[1].lo):
1206 case _vgtif_reg(pdp[1].hi):
1207 case _vgtif_reg(pdp[2].lo):
1208 case _vgtif_reg(pdp[2].hi):
1209 case _vgtif_reg(pdp[3].lo):
1210 case _vgtif_reg(pdp[3].hi):
1211 case _vgtif_reg(execlist_context_descriptor_lo):
1212 case _vgtif_reg(execlist_context_descriptor_hi):
1213 break;
a33fc7a0
MH		 1214 case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]):
1215 enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE);
1216 break;
e39c5add 1217 default:
695fbc08 1218 gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n",
e39c5add
ZW		 1219 offset, bytes, data);
1220 break;
1221 }
1222 return 0;
1223}
1224
04d348ae
ZW		 1225static int pf_write(struct intel_vgpu *vgpu,
1226 unsigned int offset, void *p_data, unsigned int bytes)
1227{
1228 u32 val = *(u32 *)p_data;
1229
1230 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL ||
1231 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL ||
1232 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) {
1233 WARN_ONCE(true, "VM(%d): guest is trying to scaling a plane\n",
1234 vgpu->id);
1235 return 0;
1236 }
1237
1238 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);
1239}
1240
1241static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu,
1242 unsigned int offset, void *p_data, unsigned int bytes)
1243{
1244 write_vreg(vgpu, offset, p_data, bytes);
1245
1af474fe
ID		 1246 if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_CTL_REQ(HSW_DISP_PW_GLOBAL))
1247 vgpu_vreg(vgpu, offset) |=
1248 HSW_PWR_WELL_CTL_STATE(HSW_DISP_PW_GLOBAL);
04d348ae 1249 else
1af474fe
ID		 1250 vgpu_vreg(vgpu, offset) &=
1251 ~HSW_PWR_WELL_CTL_STATE(HSW_DISP_PW_GLOBAL);
04d348ae
ZW		 1252 return 0;
1253}
1254
e39c5add
ZW		 1255static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu,
1256 unsigned int offset, void *p_data, unsigned int bytes)
1257{
1258 write_vreg(vgpu, offset, p_data, bytes);
1259
1260 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM)
1261 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM;
1262 return 0;
1263}
1264
1265static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset,
1266 void *p_data, unsigned int bytes)
1267{
5f399f11
PG		 1268 u32 mode;
1269
1270 write_vreg(vgpu, offset, p_data, bytes);
1271 mode = vgpu_vreg(vgpu, offset);
e39c5add
ZW		 1272
1273 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) {
7f48d0b4 1274 WARN_ONCE(1, "VM(%d): iGVT-g doesn't support GuC\n",
e39c5add
ZW		 1275 vgpu->id);
1276 return 0;
1277 }
1278
1279 return 0;
1280}
1281
1282static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset,
1283 void *p_data, unsigned int bytes)
1284{
1285 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1286 u32 trtte = *(u32 *)p_data;
1287
1288 if ((trtte & 1) && (trtte & (1 << 1)) == 0) {
1289 WARN(1, "VM(%d): Use physical address for TRTT!\n",
1290 vgpu->id);
1291 return -EINVAL;
1292 }
1293 write_vreg(vgpu, offset, p_data, bytes);
1294 /* TRTTE is not per-context */
9b7bd65e
CD		 1295
1296 mmio_hw_access_pre(dev_priv);
e39c5add 1297 I915_WRITE(_MMIO(offset), vgpu_vreg(vgpu, offset));
9b7bd65e 1298 mmio_hw_access_post(dev_priv);
e39c5add
ZW		 1299
1300 return 0;
1301}
1302
1303static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset,
1304 void *p_data, unsigned int bytes)
1305{
1306 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1307 u32 val = *(u32 *)p_data;
1308
1309 if (val & 1) {
1310 /* unblock hw logic */
9b7bd65e 1311 mmio_hw_access_pre(dev_priv);
e39c5add 1312 I915_WRITE(_MMIO(offset), val);
9b7bd65e 1313 mmio_hw_access_post(dev_priv);
e39c5add
ZW		 1314 }
1315 write_vreg(vgpu, offset, p_data, bytes);
1316 return 0;
1317}
1318
04d348ae
ZW		 1319static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset,
1320 void *p_data, unsigned int bytes)
1321{
1322 u32 v = 0;
1323
1324 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31))
1325 v |= (1 << 0);
1326
1327 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31))
1328 v |= (1 << 8);
1329
1330 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31))
1331 v |= (1 << 16);
1332
1333 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31))
1334 v |= (1 << 24);
1335
1336 vgpu_vreg(vgpu, offset) = v;
1337
1338 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1339}
1340
1341static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset,
1342 void *p_data, unsigned int bytes)
1343{
1344 u32 value = *(u32 *)p_data;
1345 u32 cmd = value & 0xff;
1346 u32 *data0 = &vgpu_vreg(vgpu, GEN6_PCODE_DATA);
1347
1348 switch (cmd) {
8bcd7c18 1349 case GEN9_PCODE_READ_MEM_LATENCY:
e3476c00
XH		 1350 if (IS_SKYLAKE(vgpu->gvt->dev_priv)
1351 || IS_KABYLAKE(vgpu->gvt->dev_priv)) {
8bcd7c18
WL		 1352 /**
1353 * "Read memory latency" command on gen9.
1354 * Below memory latency values are read
1355 * from skylake platform.
1356 */
1357 if (!*data0)
1358 *data0 = 0x1e1a1100;
1359 else
1360 *data0 = 0x61514b3d;
1361 }
04d348ae 1362 break;
d8a355be 1363 case SKL_PCODE_CDCLK_CONTROL:
e3476c00
XH		 1364 if (IS_SKYLAKE(vgpu->gvt->dev_priv)
1365 || IS_KABYLAKE(vgpu->gvt->dev_priv))
8bcd7c18 1366 *data0 = SKL_CDCLK_READY_FOR_CHANGE;
d8a355be 1367 break;
8bcd7c18 1368 case GEN6_PCODE_READ_RC6VIDS:
04d348ae
ZW		 1369 *data0 |= 0x1;
1370 break;
1371 }
1372
1373 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n",
1374 vgpu->id, value, *data0);
d8a355be
WL		 1375 /**
1376 * PCODE_READY clear means ready for pcode read/write,
1377 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we
1378 * always emulate as pcode read/write success and ready for access
1379 * anytime, since we don't touch real physical registers here.
1380 */
1381 value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK);
04d348ae
ZW		 1382 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
1383}
1384
a2ae95af
WL		 1385static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset,
1386 void *p_data, unsigned int bytes)
1387{
1388 u32 value = *(u32 *)p_data;
1389 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
1390
1391 if (!intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) {
1392 gvt_vgpu_err("VM(%d) write invalid HWSP address, reg:0x%x, value:0x%x\n",
1393 vgpu->id, offset, value);
1394 return -EINVAL;
1395 }
1396 /*
1397 * Need to emulate all the HWSP register write to ensure host can
1398 * update the VM CSB status correctly. Here listed registers can
1399 * support BDW, SKL or other platforms with same HWSP registers.
1400 */
1401 if (unlikely(ring_id < 0 || ring_id > I915_NUM_ENGINES)) {
1402 gvt_vgpu_err("VM(%d) access unknown hardware status page register:0x%x\n",
1403 vgpu->id, offset);
1404 return -EINVAL;
1405 }
1406 vgpu->hws_pga[ring_id] = value;
1407 gvt_dbg_mmio("VM(%d) write: 0x%x to HWSP: 0x%x\n",
1408 vgpu->id, value, offset);
1409
1410 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
1411}
1412
04d348ae
ZW		 1413static int skl_power_well_ctl_write(struct intel_vgpu *vgpu,
1414 unsigned int offset, void *p_data, unsigned int bytes)
1415{
1416 u32 v = *(u32 *)p_data;
1417
1418 v &= (1 << 31) | (1 << 29) | (1 << 9) |
1419 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1);
1420 v |= (v >> 1);
1421
1422 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes);
1423}
1424
1425static int skl_misc_ctl_write(struct intel_vgpu *vgpu, unsigned int offset,
1426 void *p_data, unsigned int bytes)
1427{
1428 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1999f108
CD		 1429 u32 v = *(u32 *)p_data;
1430
1431 if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv))
1432 return intel_vgpu_default_mmio_write(vgpu,
1433 offset, p_data, bytes);
04d348ae
ZW		 1434
1435 switch (offset) {
1436 case 0x4ddc:
1999f108
CD		 1437 /* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */
1438 vgpu_vreg(vgpu, offset) = v & ~(1 << 31);
04d348ae
ZW		 1439 break;
1440 case 0x42080:
1999f108
CD		 1441 /* bypass WaCompressedResourceDisplayNewHashMode */
1442 vgpu_vreg(vgpu, offset) = v & ~(1 << 15);
1443 break;
1444 case 0xe194:
1445 /* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */
1446 vgpu_vreg(vgpu, offset) = v & ~(1 << 8);
1447 break;
1448 case 0x7014:
1449 /* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */
1450 vgpu_vreg(vgpu, offset) = v & ~(1 << 13);
04d348ae
ZW		 1451 break;
1452 default:
1453 return -EINVAL;
1454 }
1455
04d348ae
ZW		 1456 return 0;
1457}
1458
1459static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset,
1460 void *p_data, unsigned int bytes)
1461{
1462 u32 v = *(u32 *)p_data;
1463
1464 /* other bits are MBZ. */
1465 v &= (1 << 31) | (1 << 30);
1466 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30));
1467
1468 vgpu_vreg(vgpu, offset) = v;
1469
1470 return 0;
1471}
1472
20a2bcde 1473static int mmio_read_from_hw(struct intel_vgpu *vgpu,
23ce0592
WL		 1474 unsigned int offset, void *p_data, unsigned int bytes)
1475{
295764cd
XZ		 1476 struct intel_gvt *gvt = vgpu->gvt;
1477 struct drm_i915_private *dev_priv = gvt->dev_priv;
1478 int ring_id;
1479 u32 ring_base;
1480
1481 ring_id = intel_gvt_render_mmio_to_ring_id(gvt, offset);
1482 /**
1483 * Read HW reg in following case
1484 * a. the offset isn't a ring mmio
1485 * b. the offset's ring is running on hw.
1486 * c. the offset is ring time stamp mmio
1487 */
1488 if (ring_id >= 0)
1489 ring_base = dev_priv->engine[ring_id]->mmio_base;
1490
1491 if (ring_id < 0 || vgpu == gvt->scheduler.engine_owner[ring_id] ||
1492 offset == i915_mmio_reg_offset(RING_TIMESTAMP(ring_base)) ||
1493 offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(ring_base))) {
1494 mmio_hw_access_pre(dev_priv);
1495 vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset));
1496 mmio_hw_access_post(dev_priv);
1497 }
23ce0592 1498
04d348ae
ZW		 1499 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1500}
1501
28c4c6ca
ZW		 1502static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1503 void *p_data, unsigned int bytes)
1504{
62a6a537 1505 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
28c4c6ca
ZW		 1506 struct intel_vgpu_execlist *execlist;
1507 u32 data = *(u32 *)p_data;
6fb5082a 1508 int ret = 0;
28c4c6ca 1509
0fac21e7 1510 if (WARN_ON(ring_id < 0 || ring_id > I915_NUM_ENGINES - 1))
28c4c6ca
ZW		 1511 return -EINVAL;
1512
1406a14b 1513 execlist = &vgpu->submission.execlist[ring_id];
28c4c6ca 1514
54cff647 1515 execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data;
6fb5082a 1516 if (execlist->elsp_dwords.index == 3) {
28c4c6ca 1517 ret = intel_vgpu_submit_execlist(vgpu, ring_id);
6fb5082a 1518 if(ret)
695fbc08
TZ		 1519 gvt_vgpu_err("fail submit workload on ring %d\n",
1520 ring_id);
6fb5082a 1521 }
28c4c6ca
ZW		 1522
1523 ++execlist->elsp_dwords.index;
1524 execlist->elsp_dwords.index &= 0x3;
6fb5082a 1525 return ret;
28c4c6ca
ZW		 1526}
1527
4b63960e
ZW		 1528static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1529 void *p_data, unsigned int bytes)
1530{
ad1d3636 1531 struct intel_vgpu_submission *s = &vgpu->submission;
4b63960e 1532 u32 data = *(u32 *)p_data;
62a6a537 1533 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
4b63960e 1534 bool enable_execlist;
ad1d3636 1535 int ret;
4b63960e
ZW		 1536
1537 write_vreg(vgpu, offset, p_data, bytes);
fd64be63
MH		 1538
1539 /* when PPGTT mode enabled, we will check if guest has called
1540 * pvinfo, if not, we will treat this guest as non-gvtg-aware
1541 * guest, and stop emulating its cfg space, mmio, gtt, etc.
1542 */
1543 if (((data & _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)) ||
1544 (data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)))
1545 && !vgpu->pv_notified) {
1546 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
1547 return 0;
1548 }
4b63960e
ZW		 1549 if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE))
1550 || (data & _MASKED_BIT_DISABLE(GFX_RUN_LIST_ENABLE))) {
1551 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE);
1552
1553 gvt_dbg_core("EXECLIST %s on ring %d\n",
1554 (enable_execlist ? "enabling" : "disabling"),
1555 ring_id);
1556
ad1d3636
ZW		 1557 if (!enable_execlist)
1558 return 0;
1559
1560 if (s->active)
1561 return 0;
1562
1563 ret = intel_vgpu_select_submission_ops(vgpu,
1564 INTEL_VGPU_EXECLIST_SUBMISSION);
1565 if (ret)
1566 return ret;
1567
1568 intel_vgpu_start_schedule(vgpu);
4b63960e
ZW		 1569 }
1570 return 0;
1571}
1572
17865713
ZW		 1573static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu,
1574 unsigned int offset, void *p_data, unsigned int bytes)
1575{
17865713
ZW		 1576 unsigned int id = 0;
1577
f24940e0 1578 write_vreg(vgpu, offset, p_data, bytes);
4f3f1aed 1579 vgpu_vreg(vgpu, offset) = 0;
f24940e0 1580
17865713
ZW		 1581 switch (offset) {
1582 case 0x4260:
1583 id = RCS;
1584 break;
1585 case 0x4264:
1586 id = VCS;
1587 break;
1588 case 0x4268:
1589 id = VCS2;
1590 break;
1591 case 0x426c:
1592 id = BCS;
1593 break;
1594 case 0x4270:
1595 id = VECS;
1596 break;
1597 default:
a1201053 1598 return -EINVAL;
17865713 1599 }
91d5d854 1600 set_bit(id, (void *)vgpu->submission.tlb_handle_pending);
17865713 1601
a1201053 1602 return 0;
17865713
ZW		 1603}
1604
2fb39fad
DC		 1605static int ring_reset_ctl_write(struct intel_vgpu *vgpu,
1606 unsigned int offset, void *p_data, unsigned int bytes)
1607{
1608 u32 data;
1609
1610 write_vreg(vgpu, offset, p_data, bytes);
1611 data = vgpu_vreg(vgpu, offset);
1612
1613 if (data & _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET))
1614 data |= RESET_CTL_READY_TO_RESET;
1615 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET))
1616 data &= ~RESET_CTL_READY_TO_RESET;
1617
1618 vgpu_vreg(vgpu, offset) = data;
1619 return 0;
1620}
1621
12d14cc4
ZW		 1622#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
1623 ret = new_mmio_info(gvt, INTEL_GVT_MMIO_OFFSET(reg), \
1624 f, s, am, rm, d, r, w); \
1625 if (ret) \
1626 return ret; \
1627} while (0)
1628
1629#define MMIO_D(reg, d) \
1630 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
1631
1632#define MMIO_DH(reg, d, r, w) \
1633 MMIO_F(reg, 4, 0, 0, 0, d, r, w)
1634
1635#define MMIO_DFH(reg, d, f, r, w) \
1636 MMIO_F(reg, 4, f, 0, 0, d, r, w)
1637
1638#define MMIO_GM(reg, d, r, w) \
1639 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
1640
0aa5277c
ZY		 1641#define MMIO_GM_RDR(reg, d, r, w) \
1642 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
1643
12d14cc4
ZW		 1644#define MMIO_RO(reg, d, f, rm, r, w) \
1645 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
1646
1647#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
1648 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
1649 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
1650 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
1651 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
edee7ecd
ZW		 1652 if (HAS_BSD2(dev_priv)) \
1653 MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
12d14cc4
ZW		 1654} while (0)
1655
1656#define MMIO_RING_D(prefix, d) \
1657 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
1658
1659#define MMIO_RING_DFH(prefix, d, f, r, w) \
1660 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
1661
1662#define MMIO_RING_GM(prefix, d, r, w) \
1663 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
1664
0aa5277c
ZY		 1665#define MMIO_RING_GM_RDR(prefix, d, r, w) \
1666 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
1667
12d14cc4
ZW		 1668#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
1669 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
1670
1671static int init_generic_mmio_info(struct intel_gvt *gvt)
1672{
e39c5add 1673 struct drm_i915_private *dev_priv = gvt->dev_priv;
12d14cc4
ZW		 1674 int ret;
1675
0aa5277c
ZY		 1676 MMIO_RING_DFH(RING_IMR, D_ALL, F_CMD_ACCESS, NULL,
1677 intel_vgpu_reg_imr_handler);
e39c5add
ZW		 1678
1679 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
1680 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
1681 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
1682 MMIO_D(SDEISR, D_ALL);
1683
0aa5277c 1684 MMIO_RING_DFH(RING_HWSTAM, D_ALL, F_CMD_ACCESS, NULL, NULL);
e39c5add 1685
0aa5277c
ZY		 1686 MMIO_GM_RDR(RENDER_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1687 MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1688 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1689 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
e39c5add
ZW		 1690
1691#define RING_REG(base) (base + 0x28)
0aa5277c 1692 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
e39c5add
ZW		 1693#undef RING_REG
1694
1695#define RING_REG(base) (base + 0x134)
0aa5277c 1696 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
e39c5add
ZW		 1697#undef RING_REG
1698
23ce0592 1699#define RING_REG(base) (base + 0x6c)
20a2bcde 1700 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
23ce0592 1701#undef RING_REG
20a2bcde 1702 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
23ce0592 1703
0aa5277c
ZY		 1704 MMIO_GM_RDR(0x2148, D_ALL, NULL, NULL);
1705 MMIO_GM_RDR(CCID, D_ALL, NULL, NULL);
1706 MMIO_GM_RDR(0x12198, D_ALL, NULL, NULL);
e39c5add
ZW		 1707 MMIO_D(GEN7_CXT_SIZE, D_ALL);
1708
0aa5277c
ZY		 1709 MMIO_RING_DFH(RING_TAIL, D_ALL, F_CMD_ACCESS, NULL, NULL);
1710 MMIO_RING_DFH(RING_HEAD, D_ALL, F_CMD_ACCESS, NULL, NULL);
1711 MMIO_RING_DFH(RING_CTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
894e287b 1712 MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, mmio_read_from_hw, NULL);
0aa5277c 1713 MMIO_RING_GM_RDR(RING_START, D_ALL, NULL, NULL);
e39c5add
ZW		 1714
1715 /* RING MODE */
1716#define RING_REG(base) (base + 0x29c)
0aa5277c
ZY		 1717 MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL,
1718 ring_mode_mmio_write);
e39c5add
ZW		 1719#undef RING_REG
1720
0aa5277c
ZY		 1721 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1722 NULL, NULL);
41bfab35
PZ		 1723 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1724 NULL, NULL);
04d348ae 1725 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
20a2bcde 1726 mmio_read_from_hw, NULL);
04d348ae 1727 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
20a2bcde 1728 mmio_read_from_hw, NULL);
e39c5add 1729
0aa5277c
ZY		 1730 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1731 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1732 NULL, NULL);
a045fba4 1733 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
0aa5277c
ZY		 1734 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1735 MMIO_DFH(0x2124, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1736
1737 MMIO_DFH(0x20dc, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1738 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1739 MMIO_DFH(0x2088, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1740 MMIO_DFH(0x20e4, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1741 MMIO_DFH(0x2470, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1742 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
1743 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1744 NULL, NULL);
1999f108
CD		 1745 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL,
1746 skl_misc_ctl_write);
0aa5277c
ZY		 1747 MMIO_DFH(0x9030, D_ALL, F_CMD_ACCESS, NULL, NULL);
1748 MMIO_DFH(0x20a0, D_ALL, F_CMD_ACCESS, NULL, NULL);
1749 MMIO_DFH(0x2420, D_ALL, F_CMD_ACCESS, NULL, NULL);
1750 MMIO_DFH(0x2430, D_ALL, F_CMD_ACCESS, NULL, NULL);
1751 MMIO_DFH(0x2434, D_ALL, F_CMD_ACCESS, NULL, NULL);
1752 MMIO_DFH(0x2438, D_ALL, F_CMD_ACCESS, NULL, NULL);
1753 MMIO_DFH(0x243c, D_ALL, F_CMD_ACCESS, NULL, NULL);
1754 MMIO_DFH(0x7018, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
a045fba4 1755 MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
187447a1 1756 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
e39c5add
ZW		 1757
1758 /* display */
1759 MMIO_F(0x60220, 0x20, 0, 0, 0, D_ALL, NULL, NULL);
1760 MMIO_D(0x602a0, D_ALL);
1761
1762 MMIO_D(0x65050, D_ALL);
1763 MMIO_D(0x650b4, D_ALL);
1764
1765 MMIO_D(0xc4040, D_ALL);
1766 MMIO_D(DERRMR, D_ALL);
1767
1768 MMIO_D(PIPEDSL(PIPE_A), D_ALL);
1769 MMIO_D(PIPEDSL(PIPE_B), D_ALL);
1770 MMIO_D(PIPEDSL(PIPE_C), D_ALL);
1771 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
1772
04d348ae
ZW		 1773 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
1774 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
1775 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
1776 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
e39c5add
ZW		 1777
1778 MMIO_D(PIPESTAT(PIPE_A), D_ALL);
1779 MMIO_D(PIPESTAT(PIPE_B), D_ALL);
1780 MMIO_D(PIPESTAT(PIPE_C), D_ALL);
1781 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
1782
1783 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
1784 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
1785 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
1786 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
1787
1788 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
1789 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
1790 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
1791 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
1792
1793 MMIO_D(CURCNTR(PIPE_A), D_ALL);
1794 MMIO_D(CURCNTR(PIPE_B), D_ALL);
1795 MMIO_D(CURCNTR(PIPE_C), D_ALL);
1796
1797 MMIO_D(CURPOS(PIPE_A), D_ALL);
1798 MMIO_D(CURPOS(PIPE_B), D_ALL);
1799 MMIO_D(CURPOS(PIPE_C), D_ALL);
1800
1801 MMIO_D(CURBASE(PIPE_A), D_ALL);
1802 MMIO_D(CURBASE(PIPE_B), D_ALL);
1803 MMIO_D(CURBASE(PIPE_C), D_ALL);
1804
1805 MMIO_D(0x700ac, D_ALL);
1806 MMIO_D(0x710ac, D_ALL);
1807 MMIO_D(0x720ac, D_ALL);
1808
1809 MMIO_D(0x70090, D_ALL);
1810 MMIO_D(0x70094, D_ALL);
1811 MMIO_D(0x70098, D_ALL);
1812 MMIO_D(0x7009c, D_ALL);
1813
1814 MMIO_D(DSPCNTR(PIPE_A), D_ALL);
1815 MMIO_D(DSPADDR(PIPE_A), D_ALL);
1816 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
1817 MMIO_D(DSPPOS(PIPE_A), D_ALL);
1818 MMIO_D(DSPSIZE(PIPE_A), D_ALL);
04d348ae 1819 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
e39c5add
ZW		 1820 MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
1821 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
1822
1823 MMIO_D(DSPCNTR(PIPE_B), D_ALL);
1824 MMIO_D(DSPADDR(PIPE_B), D_ALL);
1825 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
1826 MMIO_D(DSPPOS(PIPE_B), D_ALL);
1827 MMIO_D(DSPSIZE(PIPE_B), D_ALL);
04d348ae 1828 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
e39c5add
ZW		 1829 MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
1830 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
1831
1832 MMIO_D(DSPCNTR(PIPE_C), D_ALL);
1833 MMIO_D(DSPADDR(PIPE_C), D_ALL);
1834 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
1835 MMIO_D(DSPPOS(PIPE_C), D_ALL);
1836 MMIO_D(DSPSIZE(PIPE_C), D_ALL);
04d348ae 1837 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
e39c5add
ZW		 1838 MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
1839 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
1840
1841 MMIO_D(SPRCTL(PIPE_A), D_ALL);
1842 MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
1843 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
1844 MMIO_D(SPRPOS(PIPE_A), D_ALL);
1845 MMIO_D(SPRSIZE(PIPE_A), D_ALL);
1846 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
1847 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
04d348ae 1848 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
e39c5add
ZW		 1849 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
1850 MMIO_D(SPROFFSET(PIPE_A), D_ALL);
1851 MMIO_D(SPRSCALE(PIPE_A), D_ALL);
1852 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
1853
1854 MMIO_D(SPRCTL(PIPE_B), D_ALL);
1855 MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
1856 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
1857 MMIO_D(SPRPOS(PIPE_B), D_ALL);
1858 MMIO_D(SPRSIZE(PIPE_B), D_ALL);
1859 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
1860 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
04d348ae 1861 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
e39c5add
ZW		 1862 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
1863 MMIO_D(SPROFFSET(PIPE_B), D_ALL);
1864 MMIO_D(SPRSCALE(PIPE_B), D_ALL);
1865 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
1866
1867 MMIO_D(SPRCTL(PIPE_C), D_ALL);
1868 MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
1869 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
1870 MMIO_D(SPRPOS(PIPE_C), D_ALL);
1871 MMIO_D(SPRSIZE(PIPE_C), D_ALL);
1872 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
1873 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
04d348ae 1874 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
e39c5add
ZW		 1875 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
1876 MMIO_D(SPROFFSET(PIPE_C), D_ALL);
1877 MMIO_D(SPRSCALE(PIPE_C), D_ALL);
1878 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
1879
e39c5add
ZW		 1880 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
1881 MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
1882 MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
1883 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
1884 MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
1885 MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
1886 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
1887 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
1888 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
1889
1890 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
1891 MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
1892 MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
1893 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
1894 MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
1895 MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
1896 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
1897 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
1898 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
1899
1900 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
1901 MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
1902 MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
1903 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
1904 MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
1905 MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
1906 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
1907 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
1908 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
1909
1910 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
1911 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
1912 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
1913 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
1914 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
1915 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
1916 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
1917 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
1918
1919 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
1920 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
1921 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
1922 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
1923 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
1924 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
1925 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
1926 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
1927
1928 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
1929 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
1930 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
1931 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
1932 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
1933 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
1934 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
1935 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
1936
1937 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
1938 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
1939 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
1940 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
1941 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
1942 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
1943 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
1944 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
1945
1946 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
1947 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
1948 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
1949 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
1950 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
1951 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
1952 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
1953 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
1954
1955 MMIO_D(PF_CTL(PIPE_A), D_ALL);
1956 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
1957 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
1958 MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
1959 MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
1960
1961 MMIO_D(PF_CTL(PIPE_B), D_ALL);
1962 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
1963 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
1964 MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
1965 MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
1966
1967 MMIO_D(PF_CTL(PIPE_C), D_ALL);
1968 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
1969 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
1970 MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
1971 MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
1972
1973 MMIO_D(WM0_PIPEA_ILK, D_ALL);
1974 MMIO_D(WM0_PIPEB_ILK, D_ALL);
1975 MMIO_D(WM0_PIPEC_IVB, D_ALL);
1976 MMIO_D(WM1_LP_ILK, D_ALL);
1977 MMIO_D(WM2_LP_ILK, D_ALL);
1978 MMIO_D(WM3_LP_ILK, D_ALL);
1979 MMIO_D(WM1S_LP_ILK, D_ALL);
1980 MMIO_D(WM2S_LP_IVB, D_ALL);
1981 MMIO_D(WM3S_LP_IVB, D_ALL);
1982
1983 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
1984 MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
1985 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
1986 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
1987
1988 MMIO_D(0x48268, D_ALL);
1989
04d348ae
ZW		 1990 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
1991 gmbus_mmio_write);
1992 MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
e39c5add
ZW		 1993 MMIO_F(0xe4f00, 0x28, 0, 0, 0, D_ALL, NULL, NULL);
1994
04d348ae
ZW		 1995 MMIO_F(_PCH_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
1996 dp_aux_ch_ctl_mmio_write);
1997 MMIO_F(_PCH_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
1998 dp_aux_ch_ctl_mmio_write);
1999 MMIO_F(_PCH_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
2000 dp_aux_ch_ctl_mmio_write);
e39c5add 2001
75e64ff2 2002 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
e39c5add 2003
04d348ae
ZW		 2004 MMIO_DH(_PCH_TRANSACONF, D_ALL, NULL, transconf_mmio_write);
2005 MMIO_DH(_PCH_TRANSBCONF, D_ALL, NULL, transconf_mmio_write);
e39c5add 2006
04d348ae
ZW		 2007 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
2008 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
2009 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
2010 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
2011 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
2012 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
2013 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
2014 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
2015 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
e39c5add
ZW		 2016
2017 MMIO_D(_PCH_TRANS_HTOTAL_A, D_ALL);
2018 MMIO_D(_PCH_TRANS_HBLANK_A, D_ALL);
2019 MMIO_D(_PCH_TRANS_HSYNC_A, D_ALL);
2020 MMIO_D(_PCH_TRANS_VTOTAL_A, D_ALL);
2021 MMIO_D(_PCH_TRANS_VBLANK_A, D_ALL);
2022 MMIO_D(_PCH_TRANS_VSYNC_A, D_ALL);
2023 MMIO_D(_PCH_TRANS_VSYNCSHIFT_A, D_ALL);
2024
2025 MMIO_D(_PCH_TRANS_HTOTAL_B, D_ALL);
2026 MMIO_D(_PCH_TRANS_HBLANK_B, D_ALL);
2027 MMIO_D(_PCH_TRANS_HSYNC_B, D_ALL);
2028 MMIO_D(_PCH_TRANS_VTOTAL_B, D_ALL);
2029 MMIO_D(_PCH_TRANS_VBLANK_B, D_ALL);
2030 MMIO_D(_PCH_TRANS_VSYNC_B, D_ALL);
2031 MMIO_D(_PCH_TRANS_VSYNCSHIFT_B, D_ALL);
2032
2033 MMIO_D(_PCH_TRANSA_DATA_M1, D_ALL);
2034 MMIO_D(_PCH_TRANSA_DATA_N1, D_ALL);
2035 MMIO_D(_PCH_TRANSA_DATA_M2, D_ALL);
2036 MMIO_D(_PCH_TRANSA_DATA_N2, D_ALL);
2037 MMIO_D(_PCH_TRANSA_LINK_M1, D_ALL);
2038 MMIO_D(_PCH_TRANSA_LINK_N1, D_ALL);
2039 MMIO_D(_PCH_TRANSA_LINK_M2, D_ALL);
2040 MMIO_D(_PCH_TRANSA_LINK_N2, D_ALL);
2041
2042 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
2043 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
2044 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
2045
2046 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
2047 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
2048 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
2049
2050 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
2051 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
2052 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
2053
2054 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
2055 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
2056 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
2057
2058 MMIO_D(_FDI_RXA_MISC, D_ALL);
2059 MMIO_D(_FDI_RXB_MISC, D_ALL);
2060 MMIO_D(_FDI_RXA_TUSIZE1, D_ALL);
2061 MMIO_D(_FDI_RXA_TUSIZE2, D_ALL);
2062 MMIO_D(_FDI_RXB_TUSIZE1, D_ALL);
2063 MMIO_D(_FDI_RXB_TUSIZE2, D_ALL);
2064
04d348ae 2065 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
e39c5add
ZW		 2066 MMIO_D(PCH_PP_DIVISOR, D_ALL);
2067 MMIO_D(PCH_PP_STATUS, D_ALL);
2068 MMIO_D(PCH_LVDS, D_ALL);
2069 MMIO_D(_PCH_DPLL_A, D_ALL);
2070 MMIO_D(_PCH_DPLL_B, D_ALL);
2071 MMIO_D(_PCH_FPA0, D_ALL);
2072 MMIO_D(_PCH_FPA1, D_ALL);
2073 MMIO_D(_PCH_FPB0, D_ALL);
2074 MMIO_D(_PCH_FPB1, D_ALL);
2075 MMIO_D(PCH_DREF_CONTROL, D_ALL);
2076 MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
2077 MMIO_D(PCH_DPLL_SEL, D_ALL);
2078
2079 MMIO_D(0x61208, D_ALL);
2080 MMIO_D(0x6120c, D_ALL);
2081 MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
2082 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
2083
04d348ae
ZW		 2084 MMIO_DH(0xe651c, D_ALL, dpy_reg_mmio_read, NULL);
2085 MMIO_DH(0xe661c, D_ALL, dpy_reg_mmio_read, NULL);
2086 MMIO_DH(0xe671c, D_ALL, dpy_reg_mmio_read, NULL);
2087 MMIO_DH(0xe681c, D_ALL, dpy_reg_mmio_read, NULL);
5cd82b75
CD		 2088 MMIO_DH(0xe6c04, D_ALL, dpy_reg_mmio_read, NULL);
2089 MMIO_DH(0xe6e1c, D_ALL, dpy_reg_mmio_read, NULL);
e39c5add
ZW		 2090
2091 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
2092 PORTA_HOTPLUG_STATUS_MASK
2093 | PORTB_HOTPLUG_STATUS_MASK
2094 | PORTC_HOTPLUG_STATUS_MASK
2095 | PORTD_HOTPLUG_STATUS_MASK,
2096 NULL, NULL);
2097
04d348ae 2098 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
e39c5add
ZW		 2099 MMIO_D(FUSE_STRAP, D_ALL);
2100 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
2101
2102 MMIO_D(DISP_ARB_CTL, D_ALL);
2103 MMIO_D(DISP_ARB_CTL2, D_ALL);
2104
2105 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
2106 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
2107 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
2108
2109 MMIO_D(SOUTH_CHICKEN1, D_ALL);
04d348ae 2110 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
e39c5add
ZW		 2111 MMIO_D(_TRANSA_CHICKEN1, D_ALL);
2112 MMIO_D(_TRANSB_CHICKEN1, D_ALL);
2113 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
2114 MMIO_D(_TRANSA_CHICKEN2, D_ALL);
2115 MMIO_D(_TRANSB_CHICKEN2, D_ALL);
2116
2117 MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
2118 MMIO_D(ILK_DPFC_CONTROL, D_ALL);
2119 MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
2120 MMIO_D(ILK_DPFC_STATUS, D_ALL);
2121 MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
2122 MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
2123 MMIO_D(ILK_FBC_RT_BASE, D_ALL);
2124
2125 MMIO_D(IPS_CTL, D_ALL);
2126
2127 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
2128 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
2129 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
2130 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
2131 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
2132 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
2133 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
2134 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
2135 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
2136 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
2137 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
2138 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
2139 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
2140
2141 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
2142 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
2143 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
2144 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
2145 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
2146 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
2147 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
2148 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
2149 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
2150 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
2151 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
2152 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
2153 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
2154
2155 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
2156 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
2157 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
2158 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
2159 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
2160 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
2161 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
2162 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
2163 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
2164 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
2165 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
2166 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
2167 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
2168
04d348ae
ZW		 2169 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
2170 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
2171 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2172
2173 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
2174 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
2175 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2176
2177 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
2178 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
2179 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2180
e39c5add
ZW		 2181 MMIO_D(0x60110, D_ALL);
2182 MMIO_D(0x61110, D_ALL);
2183 MMIO_F(0x70400, 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2184 MMIO_F(0x71400, 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2185 MMIO_F(0x72400, 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2186 MMIO_F(0x70440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2187 MMIO_F(0x71440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2188 MMIO_F(0x72440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2189 MMIO_F(0x7044c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2190 MMIO_F(0x7144c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2191 MMIO_F(0x7244c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2192
2193 MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL);
2194 MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL);
2195 MMIO_D(PIPE_WM_LINETIME(PIPE_C), D_ALL);
2196 MMIO_D(SPLL_CTL, D_ALL);
2197 MMIO_D(_WRPLL_CTL1, D_ALL);
2198 MMIO_D(_WRPLL_CTL2, D_ALL);
2199 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
2200 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
2201 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
2202 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
2203 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
2204 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
2205 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
2206 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
2207
2208 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
2209 MMIO_D(0x46508, D_ALL);
2210
2211 MMIO_D(0x49080, D_ALL);
2212 MMIO_D(0x49180, D_ALL);
2213 MMIO_D(0x49280, D_ALL);
2214
2215 MMIO_F(0x49090, 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2216 MMIO_F(0x49190, 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2217 MMIO_F(0x49290, 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2218
2219 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
2220 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
2221 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
2222
e39c5add
ZW		 2223 MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
2224 MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
2225 MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
2226
2227 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
2228 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
2229 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
2230
2231 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
2232 MMIO_D(SBI_ADDR, D_ALL);
04d348ae
ZW		 2233 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
2234 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
e39c5add
ZW		 2235 MMIO_D(PIXCLK_GATE, D_ALL);
2236
04d348ae
ZW		 2237 MMIO_F(_DPA_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_ALL, NULL,
2238 dp_aux_ch_ctl_mmio_write);
2239
2240 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2241 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2242 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2243 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2244 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2245
2246 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
2247 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
2248 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
2249 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
2250 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
2251
2252 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
2253 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
2254 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
2255 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
2256 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
e39c5add
ZW		 2257
2258 MMIO_F(_DDI_BUF_TRANS_A, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2259 MMIO_F(0x64e60, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2260 MMIO_F(0x64eC0, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2261 MMIO_F(0x64f20, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2262 MMIO_F(0x64f80, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2263
2264 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
2265 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
2266
2267 MMIO_DH(_TRANS_DDI_FUNC_CTL_A, D_ALL, NULL, NULL);
2268 MMIO_DH(_TRANS_DDI_FUNC_CTL_B, D_ALL, NULL, NULL);
2269 MMIO_DH(_TRANS_DDI_FUNC_CTL_C, D_ALL, NULL, NULL);
2270 MMIO_DH(_TRANS_DDI_FUNC_CTL_EDP, D_ALL, NULL, NULL);
2271
2272 MMIO_D(_TRANSA_MSA_MISC, D_ALL);
2273 MMIO_D(_TRANSB_MSA_MISC, D_ALL);
2274 MMIO_D(_TRANSC_MSA_MISC, D_ALL);
2275 MMIO_D(_TRANS_EDP_MSA_MISC, D_ALL);
2276
2277 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
2278 MMIO_D(FORCEWAKE_ACK, D_ALL);
2279 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
2280 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
0aa5277c
ZY		 2281 MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
2282 MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
e39c5add 2283 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
a1dcba90 2284 MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
e39c5add
ZW		 2285 MMIO_D(ECOBUS, D_ALL);
2286 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
2287 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
2288 MMIO_D(GEN6_RPNSWREQ, D_ALL);
2289 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
2290 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
2291 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
2292 MMIO_D(GEN6_RPSTAT1, D_ALL);
2293 MMIO_D(GEN6_RP_CONTROL, D_ALL);
2294 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
2295 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
2296 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
2297 MMIO_D(GEN6_RP_CUR_UP, D_ALL);
2298 MMIO_D(GEN6_RP_PREV_UP, D_ALL);
2299 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
2300 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
2301 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
2302 MMIO_D(GEN6_RP_UP_EI, D_ALL);
2303 MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
2304 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
2305 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
2306 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
2307 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
2308 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
2309 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
2310 MMIO_D(GEN6_RC_SLEEP, D_ALL);
2311 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
2312 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
2313 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
2314 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
2315 MMIO_D(GEN6_PMINTRMSK, D_ALL);
9c3a16c8
ID		 2316 /*
2317 * Use an arbitrary power well controlled by the PWR_WELL_CTL
2318 * register.
2319 */
2320 MMIO_DH(HSW_PWR_WELL_CTL_BIOS(HSW_DISP_PW_GLOBAL), D_BDW, NULL,
2321 power_well_ctl_mmio_write);
2322 MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL), D_BDW, NULL,
2323 power_well_ctl_mmio_write);
2324 MMIO_DH(HSW_PWR_WELL_CTL_KVMR, D_BDW, NULL, power_well_ctl_mmio_write);
2325 MMIO_DH(HSW_PWR_WELL_CTL_DEBUG(HSW_DISP_PW_GLOBAL), D_BDW, NULL,
2326 power_well_ctl_mmio_write);
a1dcba90 2327 MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
2328 MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
e39c5add
ZW		 2329
2330 MMIO_D(RSTDBYCTL, D_ALL);
2331
2332 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
2333 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
04d348ae 2334 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
e39c5add 2335
e39c5add
ZW		 2336 MMIO_D(TILECTL, D_ALL);
2337
2338 MMIO_D(GEN6_UCGCTL1, D_ALL);
2339 MMIO_D(GEN6_UCGCTL2, D_ALL);
2340
2341 MMIO_F(0x4f000, 0x90, 0, 0, 0, D_ALL, NULL, NULL);
2342
e39c5add
ZW		 2343 MMIO_D(GEN6_PCODE_DATA, D_ALL);
2344 MMIO_D(0x13812c, D_ALL);
2345 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
2346 MMIO_D(HSW_EDRAM_CAP, D_ALL);
2347 MMIO_D(HSW_IDICR, D_ALL);
2348 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
2349
2350 MMIO_D(0x3c, D_ALL);
2351 MMIO_D(0x860, D_ALL);
2352 MMIO_D(ECOSKPD, D_ALL);
2353 MMIO_D(0x121d0, D_ALL);
2354 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
2355 MMIO_D(0x41d0, D_ALL);
2356 MMIO_D(GAC_ECO_BITS, D_ALL);
2357 MMIO_D(0x6200, D_ALL);
2358 MMIO_D(0x6204, D_ALL);
2359 MMIO_D(0x6208, D_ALL);
2360 MMIO_D(0x7118, D_ALL);
2361 MMIO_D(0x7180, D_ALL);
2362 MMIO_D(0x7408, D_ALL);
2363 MMIO_D(0x7c00, D_ALL);
975629c3 2364 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
e39c5add
ZW		 2365 MMIO_D(0x911c, D_ALL);
2366 MMIO_D(0x9120, D_ALL);
a045fba4 2367 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
e39c5add
ZW		 2368
2369 MMIO_D(GAB_CTL, D_ALL);
2370 MMIO_D(0x48800, D_ALL);
2371 MMIO_D(0xce044, D_ALL);
2372 MMIO_D(0xe6500, D_ALL);
2373 MMIO_D(0xe6504, D_ALL);
2374 MMIO_D(0xe6600, D_ALL);
2375 MMIO_D(0xe6604, D_ALL);
2376 MMIO_D(0xe6700, D_ALL);
2377 MMIO_D(0xe6704, D_ALL);
2378 MMIO_D(0xe6800, D_ALL);
2379 MMIO_D(0xe6804, D_ALL);
2380 MMIO_D(PCH_GMBUS4, D_ALL);
2381 MMIO_D(PCH_GMBUS5, D_ALL);
2382
2383 MMIO_D(0x902c, D_ALL);
2384 MMIO_D(0xec008, D_ALL);
2385 MMIO_D(0xec00c, D_ALL);
2386 MMIO_D(0xec008 + 0x18, D_ALL);
2387 MMIO_D(0xec00c + 0x18, D_ALL);
2388 MMIO_D(0xec008 + 0x18 * 2, D_ALL);
2389 MMIO_D(0xec00c + 0x18 * 2, D_ALL);
2390 MMIO_D(0xec008 + 0x18 * 3, D_ALL);
2391 MMIO_D(0xec00c + 0x18 * 3, D_ALL);
2392 MMIO_D(0xec408, D_ALL);
2393 MMIO_D(0xec40c, D_ALL);
2394 MMIO_D(0xec408 + 0x18, D_ALL);
2395 MMIO_D(0xec40c + 0x18, D_ALL);
2396 MMIO_D(0xec408 + 0x18 * 2, D_ALL);
2397 MMIO_D(0xec40c + 0x18 * 2, D_ALL);
2398 MMIO_D(0xec408 + 0x18 * 3, D_ALL);
2399 MMIO_D(0xec40c + 0x18 * 3, D_ALL);
2400 MMIO_D(0xfc810, D_ALL);
2401 MMIO_D(0xfc81c, D_ALL);
2402 MMIO_D(0xfc828, D_ALL);
2403 MMIO_D(0xfc834, D_ALL);
2404 MMIO_D(0xfcc00, D_ALL);
2405 MMIO_D(0xfcc0c, D_ALL);
2406 MMIO_D(0xfcc18, D_ALL);
2407 MMIO_D(0xfcc24, D_ALL);
2408 MMIO_D(0xfd000, D_ALL);
2409 MMIO_D(0xfd00c, D_ALL);
2410 MMIO_D(0xfd018, D_ALL);
2411 MMIO_D(0xfd024, D_ALL);
2412 MMIO_D(0xfd034, D_ALL);
2413
2414 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
2415 MMIO_D(0x2054, D_ALL);
2416 MMIO_D(0x12054, D_ALL);
2417 MMIO_D(0x22054, D_ALL);
2418 MMIO_D(0x1a054, D_ALL);
2419
2420 MMIO_D(0x44070, D_ALL);
a1dcba90 2421 MMIO_DFH(0x215c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
e39c5add
ZW		 2422 MMIO_DFH(0x2178, D_ALL, F_CMD_ACCESS, NULL, NULL);
2423 MMIO_DFH(0x217c, D_ALL, F_CMD_ACCESS, NULL, NULL);
2424 MMIO_DFH(0x12178, D_ALL, F_CMD_ACCESS, NULL, NULL);
2425 MMIO_DFH(0x1217c, D_ALL, F_CMD_ACCESS, NULL, NULL);
2426
a1dcba90 2427 MMIO_F(0x2290, 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
e39c5add
ZW		 2428 MMIO_D(0x2b00, D_BDW_PLUS);
2429 MMIO_D(0x2360, D_BDW_PLUS);
0aa5277c
ZY		 2430 MMIO_F(0x5200, 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2431 MMIO_F(0x5240, 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2432 MMIO_F(0x5280, 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
e39c5add
ZW		 2433
2434 MMIO_DFH(0x1c17c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2435 MMIO_DFH(0x1c178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
0aa5277c
ZY		 2436 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
2437
2438 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2439 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2440 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2441 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2442 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2443 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2444 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2445 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2446 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2447 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2448 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
17865713
ZW		 2449 MMIO_DH(0x4260, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2450 MMIO_DH(0x4264, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2451 MMIO_DH(0x4268, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2452 MMIO_DH(0x426c, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2453 MMIO_DH(0x4270, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
e39c5add
ZW		 2454 MMIO_DFH(0x4094, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2455
9112caaf
ZY		 2456 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2457 MMIO_RING_GM_RDR(RING_BBADDR, D_ALL, NULL, NULL);
2458 MMIO_DFH(0x2220, D_ALL, F_CMD_ACCESS, NULL, NULL);
2459 MMIO_DFH(0x12220, D_ALL, F_CMD_ACCESS, NULL, NULL);
2460 MMIO_DFH(0x22220, D_ALL, F_CMD_ACCESS, NULL, NULL);
2461 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
2462 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
2463 MMIO_DFH(0x22178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2464 MMIO_DFH(0x1a178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2465 MMIO_DFH(0x1a17c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2466 MMIO_DFH(0x2217c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
12d14cc4
ZW		 2467 return 0;
2468}
2469
2470static int init_broadwell_mmio_info(struct intel_gvt *gvt)
2471{
e39c5add 2472 struct drm_i915_private *dev_priv = gvt->dev_priv;
12d14cc4
ZW		 2473 int ret;
2474
e39c5add
ZW		 2475 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2476 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2477 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2478 MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
2479
2480 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2481 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2482 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2483 MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
2484
2485 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2486 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2487 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2488 MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
2489
2490 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2491 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2492 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2493 MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
2494
2495 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
2496 intel_vgpu_reg_imr_handler);
2497 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
2498 intel_vgpu_reg_ier_handler);
2499 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
2500 intel_vgpu_reg_iir_handler);
2501 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
2502
2503 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
2504 intel_vgpu_reg_imr_handler);
2505 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
2506 intel_vgpu_reg_ier_handler);
2507 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
2508 intel_vgpu_reg_iir_handler);
2509 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
2510
2511 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
2512 intel_vgpu_reg_imr_handler);
2513 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
2514 intel_vgpu_reg_ier_handler);
2515 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
2516 intel_vgpu_reg_iir_handler);
2517 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
2518
2519 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2520 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2521 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2522 MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
2523
2524 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2525 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2526 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2527 MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
2528
2529 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2530 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2531 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2532 MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
2533
2534 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
2535 intel_vgpu_reg_master_irq_handler);
2536
894e287b
XZ		 2537 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS,
2538 mmio_read_from_hw, NULL);
e39c5add 2539
2fb39fad
DC		 2540#define RING_REG(base) (base + 0xd0)
2541 MMIO_RING_F(RING_REG, 4, F_RO, 0,
2542 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
2543 ring_reset_ctl_write);
2fb39fad
DC		 2544#undef RING_REG
2545
e39c5add 2546#define RING_REG(base) (base + 0x230)
28c4c6ca 2547 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
e39c5add
ZW		 2548#undef RING_REG
2549
2550#define RING_REG(base) (base + 0x234)
0aa5277c
ZY		 2551 MMIO_RING_F(RING_REG, 8, F_RO | F_CMD_ACCESS, 0, ~0, D_BDW_PLUS,
2552 NULL, NULL);
e39c5add
ZW		 2553#undef RING_REG
2554
2555#define RING_REG(base) (base + 0x244)
0aa5277c 2556 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
e39c5add
ZW		 2557#undef RING_REG
2558
2559#define RING_REG(base) (base + 0x370)
2560 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
e39c5add
ZW		 2561#undef RING_REG
2562
2563#define RING_REG(base) (base + 0x3a0)
2564 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
e39c5add
ZW		 2565#undef RING_REG
2566
2567 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
2568 MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
2569 MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
2570 MMIO_D(0x1c1d0, D_BDW_PLUS);
2571 MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
2572 MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
2573 MMIO_D(0x1c054, D_BDW_PLUS);
2574
8bcd7c18
WL		 2575 MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
2576
e39c5add
ZW		 2577 MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS);
2578 MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
2579
2580 MMIO_D(GAMTARBMODE, D_BDW_PLUS);
2581
2582#define RING_REG(base) (base + 0x270)
2583 MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL);
e39c5add
ZW		 2584#undef RING_REG
2585
a2ae95af 2586 MMIO_RING_GM_RDR(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
e39c5add 2587
a045fba4 2588 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
e39c5add 2589
593e59b4
ZY		 2590 MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
2591 MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
2592 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
e39c5add
ZW		 2593
2594 MMIO_D(WM_MISC, D_BDW);
2595 MMIO_D(BDW_EDP_PSR_BASE, D_BDW);
2596
2597 MMIO_D(0x66c00, D_BDW_PLUS);
2598 MMIO_D(0x66c04, D_BDW_PLUS);
2599
2600 MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
2601
2602 MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
2603 MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
2604 MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
2605
593e59b4 2606 MMIO_D(0xfdc, D_BDW_PLUS);
0aa5277c
ZY		 2607 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2608 NULL, NULL);
2609 MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2610 NULL, NULL);
2611 MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
e39c5add 2612
0aa5277c
ZY		 2613 MMIO_DFH(0xb1f0, D_BDW, F_CMD_ACCESS, NULL, NULL);
2614 MMIO_DFH(0xb1c0, D_BDW, F_CMD_ACCESS, NULL, NULL);
e39c5add 2615 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
0aa5277c
ZY		 2616 MMIO_DFH(0xb100, D_BDW, F_CMD_ACCESS, NULL, NULL);
2617 MMIO_DFH(0xb10c, D_BDW, F_CMD_ACCESS, NULL, NULL);
e39c5add
ZW		 2618 MMIO_D(0xb110, D_BDW);
2619
e6cedfea
ZY		 2620 MMIO_F(0x24d0, 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS,
2621 NULL, force_nonpriv_write);
e39c5add 2622
593e59b4
ZY		 2623 MMIO_D(0x44484, D_BDW_PLUS);
2624 MMIO_D(0x4448c, D_BDW_PLUS);
2625
0aa5277c 2626 MMIO_DFH(0x83a4, D_BDW, F_CMD_ACCESS, NULL, NULL);
e39c5add
ZW		 2627 MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
2628
0aa5277c 2629 MMIO_DFH(0x8430, D_BDW, F_CMD_ACCESS, NULL, NULL);
e39c5add
ZW		 2630
2631 MMIO_D(0x110000, D_BDW_PLUS);
2632
2633 MMIO_D(0x48400, D_BDW_PLUS);
2634
2635 MMIO_D(0x6e570, D_BDW_PLUS);
2636 MMIO_D(0x65f10, D_BDW_PLUS);
2637
1999f108
CD		 2638 MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL,
2639 skl_misc_ctl_write);
a045fba4
PG		 2640 MMIO_DFH(0xe188, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2641 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
0aa5277c 2642 MMIO_DFH(0x2580, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
e39c5add 2643
0aa5277c 2644 MMIO_DFH(0x2248, D_BDW, F_CMD_ACCESS, NULL, NULL);
e39c5add 2645
9112caaf
ZY		 2646 MMIO_DFH(0xe220, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2647 MMIO_DFH(0xe230, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2648 MMIO_DFH(0xe240, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2649 MMIO_DFH(0xe260, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2650 MMIO_DFH(0xe270, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2651 MMIO_DFH(0xe280, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2652 MMIO_DFH(0xe2a0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2653 MMIO_DFH(0xe2b0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2654 MMIO_DFH(0xe2c0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
12d14cc4
ZW		 2655 return 0;
2656}
2657
e39c5add
ZW		 2658static int init_skl_mmio_info(struct intel_gvt *gvt)
2659{
2660 struct drm_i915_private *dev_priv = gvt->dev_priv;
2661 int ret;
2662
2663 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2664 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
2665 MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2666 MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL);
2667 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2668 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
2669
5cf5fe8f
XH		 2670 MMIO_F(_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2671 dp_aux_ch_ctl_mmio_write);
2672 MMIO_F(_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2673 dp_aux_ch_ctl_mmio_write);
2674 MMIO_F(_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2675 dp_aux_ch_ctl_mmio_write);
2676
9c3a16c8
ID		 2677 /*
2678 * Use an arbitrary power well controlled by the PWR_WELL_CTL
2679 * register.
2680 */
2681 MMIO_D(HSW_PWR_WELL_CTL_BIOS(SKL_DISP_PW_MISC_IO), D_SKL_PLUS);
2682 MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(SKL_DISP_PW_MISC_IO), D_SKL_PLUS, NULL,
2683 skl_power_well_ctl_write);
e39c5add 2684
e39c5add
ZW		 2685 MMIO_D(0xa210, D_SKL_PLUS);
2686 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
2687 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
a045fba4 2688 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
5cf5fe8f
XH		 2689 MMIO_DH(0x4ddc, D_SKL_PLUS, NULL, skl_misc_ctl_write);
2690 MMIO_DH(0x42080, D_SKL_PLUS, NULL, skl_misc_ctl_write);
2691 MMIO_D(0x45504, D_SKL_PLUS);
2692 MMIO_D(0x45520, D_SKL_PLUS);
2693 MMIO_D(0x46000, D_SKL_PLUS);
2694 MMIO_DH(0x46010, D_SKL | D_KBL, NULL, skl_lcpll_write);
2695 MMIO_DH(0x46014, D_SKL | D_KBL, NULL, skl_lcpll_write);
2696 MMIO_D(0x6C040, D_SKL | D_KBL);
2697 MMIO_D(0x6C048, D_SKL | D_KBL);
2698 MMIO_D(0x6C050, D_SKL | D_KBL);
2699 MMIO_D(0x6C044, D_SKL | D_KBL);
2700 MMIO_D(0x6C04C, D_SKL | D_KBL);
2701 MMIO_D(0x6C054, D_SKL | D_KBL);
2702 MMIO_D(0x6c058, D_SKL | D_KBL);
2703 MMIO_D(0x6c05c, D_SKL | D_KBL);
2704 MMIO_DH(0X6c060, D_SKL | D_KBL, dpll_status_read, NULL);
2705
2706 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2707 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2708 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2709 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2710 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2711 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2712
2713 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2714 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2715 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2716 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2717 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2718 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2719
2720 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2721 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2722 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2723 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2724 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2725 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2726
2727 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2728 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2729 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2730 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2731
2732 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2733 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2734 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2735 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2736
2737 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2738 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2739 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2740 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2741
2742 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
2743 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
2744 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
2745
2746 MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2747 MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2748 MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2749
2750 MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2751 MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2752 MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2753
2754 MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2755 MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2756 MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2757
2758 MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2759 MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2760 MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2761
2762 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2763 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2764 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2765
2766 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2767 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2768 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2769
2770 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2771 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2772 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2773
2774 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
2775 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
2776 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
2777
2778 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2779 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2780 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2781 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2782
2783 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2784 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2785 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2786 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2787
2788 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2789 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2790 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2791 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2792
2793 MMIO_DH(_REG_701C0(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2794 MMIO_DH(_REG_701C0(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2795 MMIO_DH(_REG_701C0(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2796 MMIO_DH(_REG_701C0(PIPE_A, 4), D_SKL_PLUS, NULL, NULL);
2797
2798 MMIO_DH(_REG_701C0(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2799 MMIO_DH(_REG_701C0(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2800 MMIO_DH(_REG_701C0(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2801 MMIO_DH(_REG_701C0(PIPE_B, 4), D_SKL_PLUS, NULL, NULL);
2802
2803 MMIO_DH(_REG_701C0(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2804 MMIO_DH(_REG_701C0(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2805 MMIO_DH(_REG_701C0(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2806 MMIO_DH(_REG_701C0(PIPE_C, 4), D_SKL_PLUS, NULL, NULL);
2807
2808 MMIO_DH(_REG_701C4(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2809 MMIO_DH(_REG_701C4(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2810 MMIO_DH(_REG_701C4(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2811 MMIO_DH(_REG_701C4(PIPE_A, 4), D_SKL_PLUS, NULL, NULL);
2812
2813 MMIO_DH(_REG_701C4(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2814 MMIO_DH(_REG_701C4(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2815 MMIO_DH(_REG_701C4(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2816 MMIO_DH(_REG_701C4(PIPE_B, 4), D_SKL_PLUS, NULL, NULL);
2817
2818 MMIO_DH(_REG_701C4(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2819 MMIO_DH(_REG_701C4(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2820 MMIO_DH(_REG_701C4(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2821 MMIO_DH(_REG_701C4(PIPE_C, 4), D_SKL_PLUS, NULL, NULL);
2822
2823 MMIO_D(0x70380, D_SKL_PLUS);
2824 MMIO_D(0x71380, D_SKL_PLUS);
2825 MMIO_D(0x72380, D_SKL_PLUS);
2826 MMIO_D(0x7039c, D_SKL_PLUS);
2827
5cf5fe8f
XH		 2828 MMIO_D(0x8f074, D_SKL | D_KBL);
2829 MMIO_D(0x8f004, D_SKL | D_KBL);
2830 MMIO_D(0x8f034, D_SKL | D_KBL);
2831
2832 MMIO_D(0xb11c, D_SKL | D_KBL);
2833
2834 MMIO_D(0x51000, D_SKL | D_KBL);
2835 MMIO_D(0x6c00c, D_SKL_PLUS);
2836
2837 MMIO_F(0xc800, 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL | D_KBL, NULL, NULL);
2838 MMIO_F(0xb020, 0x80, F_CMD_ACCESS, 0, 0, D_SKL | D_KBL, NULL, NULL);
2839
2840 MMIO_D(0xd08, D_SKL_PLUS);
2841 MMIO_DFH(0x20e0, D_SKL_PLUS, F_MODE_MASK, NULL, NULL);
2842 MMIO_DFH(0x20ec, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
e39c5add
ZW		 2843
2844 /* TRTT */
5cf5fe8f
XH		 2845 MMIO_DFH(0x4de0, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
2846 MMIO_DFH(0x4de4, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
2847 MMIO_DFH(0x4de8, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
2848 MMIO_DFH(0x4dec, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
2849 MMIO_DFH(0x4df0, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
2850 MMIO_DFH(0x4df4, D_SKL | D_KBL, F_CMD_ACCESS, NULL, gen9_trtte_write);
2851 MMIO_DH(0x4dfc, D_SKL | D_KBL, NULL, gen9_trtt_chicken_write);
e39c5add 2852
5cf5fe8f 2853 MMIO_D(0x45008, D_SKL | D_KBL);
e39c5add 2854
5cf5fe8f 2855 MMIO_D(0x46430, D_SKL | D_KBL);
e39c5add 2856
5cf5fe8f 2857 MMIO_D(0x46520, D_SKL | D_KBL);
e39c5add 2858
5cf5fe8f
XH		 2859 MMIO_D(0xc403c, D_SKL | D_KBL);
2860 MMIO_D(0xb004, D_SKL_PLUS);
e39c5add
ZW		 2861 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
2862
5cf5fe8f
XH		 2863 MMIO_D(0x65900, D_SKL_PLUS);
2864 MMIO_D(0x1082c0, D_SKL | D_KBL);
2865 MMIO_D(0x4068, D_SKL | D_KBL);
2866 MMIO_D(0x67054, D_SKL | D_KBL);
2867 MMIO_D(0x6e560, D_SKL | D_KBL);
2868 MMIO_D(0x6e554, D_SKL | D_KBL);
2869 MMIO_D(0x2b20, D_SKL | D_KBL);
2870 MMIO_D(0x65f00, D_SKL | D_KBL);
2871 MMIO_D(0x65f08, D_SKL | D_KBL);
2872 MMIO_D(0x320f0, D_SKL | D_KBL);
2873
5cf5fe8f
XH		 2874 MMIO_D(0x70034, D_SKL_PLUS);
2875 MMIO_D(0x71034, D_SKL_PLUS);
2876 MMIO_D(0x72034, D_SKL_PLUS);
2877
2878 MMIO_D(_PLANE_KEYVAL_1(PIPE_A), D_SKL_PLUS);
2879 MMIO_D(_PLANE_KEYVAL_1(PIPE_B), D_SKL_PLUS);
2880 MMIO_D(_PLANE_KEYVAL_1(PIPE_C), D_SKL_PLUS);
2881 MMIO_D(_PLANE_KEYMSK_1(PIPE_A), D_SKL_PLUS);
2882 MMIO_D(_PLANE_KEYMSK_1(PIPE_B), D_SKL_PLUS);
2883 MMIO_D(_PLANE_KEYMSK_1(PIPE_C), D_SKL_PLUS);
2884
2885 MMIO_D(0x44500, D_SKL_PLUS);
0aa5277c 2886 MMIO_DFH(GEN9_CSFE_CHICKEN1_RCS, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
5cf5fe8f 2887 MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL | D_KBL, F_MODE_MASK | F_CMD_ACCESS,
9112caaf 2888 NULL, NULL);
5cf5fe8f
XH		 2889
2890 MMIO_D(0x4ab8, D_KBL);
5cf5fe8f 2891 MMIO_D(0x2248, D_SKL_PLUS | D_KBL);
5cf5fe8f 2892
e39c5add
ZW		 2893 return 0;
2894}
04d348ae 2895
65f9f6fe
CD		 2896static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
2897 unsigned int offset)
2898{
2899 unsigned long device = intel_gvt_get_device_type(gvt);
02b6ed44
TZ		 2900 struct gvt_mmio_block *block = gvt->mmio.mmio_block;
2901 int num = gvt->mmio.num_mmio_block;
65f9f6fe 2902 int i;
12d14cc4 2903
02b6ed44 2904 for (i = 0; i < num; i++, block++) {
65f9f6fe
CD		 2905 if (!(device & block->device))
2906 continue;
2907 if (offset >= INTEL_GVT_MMIO_OFFSET(block->offset) &&
2908 offset < INTEL_GVT_MMIO_OFFSET(block->offset) + block->size)
2909 return block;
12d14cc4
ZW		 2910 }
2911 return NULL;
2912}
2913
2914/**
2915 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device
2916 * @gvt: GVT device
2917 *
2918 * This function is called at the driver unloading stage, to clean up the MMIO
2919 * information table of GVT device
2920 *
2921 */
2922void intel_gvt_clean_mmio_info(struct intel_gvt *gvt)
2923{
2924 struct hlist_node *tmp;
2925 struct intel_gvt_mmio_info *e;
2926 int i;
2927
2928 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node)
2929 kfree(e);
2930
2931 vfree(gvt->mmio.mmio_attribute);
2932 gvt->mmio.mmio_attribute = NULL;
2933}
2934
02b6ed44
TZ		 2935/* Special MMIO blocks. */
2936static struct gvt_mmio_block mmio_blocks[] = {
2937 {D_SKL_PLUS, _MMIO(CSR_MMIO_START_RANGE), 0x3000, NULL, NULL},
2938 {D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL},
2939 {D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE,
2940 pvinfo_mmio_read, pvinfo_mmio_write},
2941 {D_ALL, LGC_PALETTE(PIPE_A, 0), 1024, NULL, NULL},
2942 {D_ALL, LGC_PALETTE(PIPE_B, 0), 1024, NULL, NULL},
2943 {D_ALL, LGC_PALETTE(PIPE_C, 0), 1024, NULL, NULL},
2944};
2945
12d14cc4
ZW		 2946/**
2947 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device
2948 * @gvt: GVT device
2949 *
2950 * This function is called at the initialization stage, to setup the MMIO
2951 * information table for GVT device
2952 *
2953 * Returns:
2954 * zero on success, negative if failed.
2955 */
2956int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
2957{
2958 struct intel_gvt_device_info *info = &gvt->device_info;
2959 struct drm_i915_private *dev_priv = gvt->dev_priv;
56a78de5 2960 int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute);
12d14cc4
ZW		 2961 int ret;
2962
56a78de5 2963 gvt->mmio.mmio_attribute = vzalloc(size);
12d14cc4
ZW		 2964 if (!gvt->mmio.mmio_attribute)
2965 return -ENOMEM;
2966
2967 ret = init_generic_mmio_info(gvt);
2968 if (ret)
2969 goto err;
2970
2971 if (IS_BROADWELL(dev_priv)) {
2972 ret = init_broadwell_mmio_info(gvt);
2973 if (ret)
2974 goto err;
e3476c00
XH		 2975 } else if (IS_SKYLAKE(dev_priv)
2976 || IS_KABYLAKE(dev_priv)) {
e39c5add
ZW		 2977 ret = init_broadwell_mmio_info(gvt);
2978 if (ret)
2979 goto err;
2980 ret = init_skl_mmio_info(gvt);
2981 if (ret)
2982 goto err;
12d14cc4 2983 }
fbfd76c3 2984
02b6ed44
TZ		 2985 gvt->mmio.mmio_block = mmio_blocks;
2986 gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks);
2987
12d14cc4
ZW		 2988 return 0;
2989err:
2990 intel_gvt_clean_mmio_info(gvt);
2991 return ret;
2992}
e39c5add 2993
7cb16018
CD		 2994/**
2995 * intel_gvt_for_each_tracked_mmio - iterate each tracked mmio
2996 * @gvt: a GVT device
2997 * @handler: the handler
2998 * @data: private data given to handler
2999 *
3000 * Returns:
3001 * Zero on success, negative error code if failed.
3002 */
3003int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt,
3004 int (*handler)(struct intel_gvt *gvt, u32 offset, void *data),
3005 void *data)
3006{
3007 struct gvt_mmio_block *block = gvt->mmio.mmio_block;
3008 struct intel_gvt_mmio_info *e;
3009 int i, j, ret;
3010
3011 hash_for_each(gvt->mmio.mmio_info_table, i, e, node) {
3012 ret = handler(gvt, e->offset, data);
3013 if (ret)
3014 return ret;
3015 }
3016
3017 for (i = 0; i < gvt->mmio.num_mmio_block; i++, block++) {
3018 for (j = 0; j < block->size; j += 4) {
3019 ret = handler(gvt,
3020 INTEL_GVT_MMIO_OFFSET(block->offset) + j,
3021 data);
3022 if (ret)
3023 return ret;
3024 }
3025 }
3026 return 0;
3027}
e39c5add
ZW		 3028
3029/**
3030 * intel_vgpu_default_mmio_read - default MMIO read handler
3031 * @vgpu: a vGPU
3032 * @offset: access offset
3033 * @p_data: data return buffer
3034 * @bytes: access data length
3035 *
3036 * Returns:
3037 * Zero on success, negative error code if failed.
3038 */
3039int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
3040 void *p_data, unsigned int bytes)
3041{
3042 read_vreg(vgpu, offset, p_data, bytes);
3043 return 0;
3044}
3045
3046/**
3047 * intel_t_default_mmio_write - default MMIO write handler
3048 * @vgpu: a vGPU
3049 * @offset: access offset
3050 * @p_data: write data buffer
3051 * @bytes: access data length
3052 *
3053 * Returns:
3054 * Zero on success, negative error code if failed.
3055 */
3056int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
3057 void *p_data, unsigned int bytes)
3058{
3059 write_vreg(vgpu, offset, p_data, bytes);
3060 return 0;
3061}
4938ca90
ZY		 3062
3063/**
3064 * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be
3065 * force-nopriv register
3066 *
3067 * @gvt: a GVT device
3068 * @offset: register offset
3069 *
3070 * Returns:
3071 * True if the register is in force-nonpriv whitelist;
3072 * False if outside;
3073 */
3074bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
3075 unsigned int offset)
3076{
3077 return in_whitelist(offset);
3078}
65f9f6fe
CD		 3079
3080/**
3081 * intel_vgpu_mmio_reg_rw - emulate tracked mmio registers
3082 * @vgpu: a vGPU
3083 * @offset: register offset
3084 * @pdata: data buffer
3085 * @bytes: data length
3086 *
3087 * Returns:
3088 * Zero on success, negative error code if failed.
3089 */
3090int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset,
3091 void *pdata, unsigned int bytes, bool is_read)
3092{
3093 struct intel_gvt *gvt = vgpu->gvt;
3094 struct intel_gvt_mmio_info *mmio_info;
3095 struct gvt_mmio_block *mmio_block;
3096 gvt_mmio_func func;
3097 int ret;
3098
d6086598 3099 if (WARN_ON(bytes > 8))
65f9f6fe
CD		 3100 return -EINVAL;
3101
3102 /*
3103 * Handle special MMIO blocks.
3104 */
3105 mmio_block = find_mmio_block(gvt, offset);
3106 if (mmio_block) {
3107 func = is_read ? mmio_block->read : mmio_block->write;
3108 if (func)
3109 return func(vgpu, offset, pdata, bytes);
3110 goto default_rw;
3111 }
3112
3113 /*
3114 * Normal tracked MMIOs.
3115 */
3116 mmio_info = find_mmio_info(gvt, offset);
3117 if (!mmio_info) {
3118 if (!vgpu->mmio.disable_warn_untrack)
3119 gvt_vgpu_err("untracked MMIO %08x len %d\n",
3120 offset, bytes);
3121 goto default_rw;
3122 }
3123
65f9f6fe
CD		 3124 if (is_read)
3125 return mmio_info->read(vgpu, offset, pdata, bytes);
3126 else {
3127 u64 ro_mask = mmio_info->ro_mask;
3128 u32 old_vreg = 0, old_sreg = 0;
3129 u64 data = 0;
3130
3131 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) {
3132 old_vreg = vgpu_vreg(vgpu, offset);
3133 old_sreg = vgpu_sreg(vgpu, offset);
3134 }
3135
3136 if (likely(!ro_mask))
3137 ret = mmio_info->write(vgpu, offset, pdata, bytes);
3138 else if (!~ro_mask) {
3139 gvt_vgpu_err("try to write RO reg %x\n", offset);
3140 return 0;
3141 } else {
3142 /* keep the RO bits in the virtual register */
3143 memcpy(&data, pdata, bytes);
3144 data &= ~ro_mask;
3145 data |= vgpu_vreg(vgpu, offset) & ro_mask;
3146 ret = mmio_info->write(vgpu, offset, &data, bytes);
3147 }
3148
3149 /* higher 16bits of mode ctl regs are mask bits for change */
3150 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) {
3151 u32 mask = vgpu_vreg(vgpu, offset) >> 16;
3152
3153 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask)
3154 | (vgpu_vreg(vgpu, offset) & mask);
3155 vgpu_sreg(vgpu, offset) = (old_sreg & ~mask)
3156 | (vgpu_sreg(vgpu, offset) & mask);
3157 }
3158 }
3159
3160 return ret;
3161
3162default_rw:
3163 return is_read ?
3164 intel_vgpu_default_mmio_read(vgpu, offset, pdata, bytes) :
3165 intel_vgpu_default_mmio_write(vgpu, offset, pdata, bytes);
3166}
Linux 6.x block layer and io_uring tree(s)